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* doc/tm.texi (IS_ASM_LOGICAL_LINE_SEPARATOR): Document new argument.
[official-gcc/alias-decl.git] / gcc / config / bfin / bfin.h
blobb568d9a05eb17684ee2746149b020bd433dd5b48
1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #ifndef _BFIN_CONFIG
22 #define _BFIN_CONFIG
23
24 #define OBJECT_FORMAT_ELF
25
26 #define BRT 1
27 #define BRF 0
28
29 /* Print subsidiary information on the compiler version in use. */
30 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
31
32 /* Run-time compilation parameters selecting different hardware subsets. */
33
34 extern int target_flags;
35
36 #ifndef DEFAULT_CPU_TYPE
37 #define DEFAULT_CPU_TYPE BFIN_CPU_BF532
38 #endif
39
40 /* Predefinition in the preprocessor for this target machine */
41 #ifndef TARGET_CPU_CPP_BUILTINS
42 #define TARGET_CPU_CPP_BUILTINS() \
43 do \
44 { \
45 builtin_define_std ("bfin"); \
46 builtin_define_std ("BFIN"); \
47 builtin_define ("__ADSPBLACKFIN__"); \
48 builtin_define ("__ADSPLPBLACKFIN__"); \
49 \
50 switch (bfin_cpu_type) \
51 { \
52 case BFIN_CPU_BF522: \
53 builtin_define ("__ADSPBF522__"); \
54 builtin_define ("__ADSPBF52x__"); \
55 break; \
56 case BFIN_CPU_BF525: \
57 builtin_define ("__ADSPBF525__"); \
58 builtin_define ("__ADSPBF52x__"); \
59 break; \
60 case BFIN_CPU_BF527: \
61 builtin_define ("__ADSPBF527__"); \
62 builtin_define ("__ADSPBF52x__"); \
63 break; \
64 case BFIN_CPU_BF531: \
65 builtin_define ("__ADSPBF531__"); \
66 break; \
67 case BFIN_CPU_BF532: \
68 builtin_define ("__ADSPBF532__"); \
69 break; \
70 case BFIN_CPU_BF533: \
71 builtin_define ("__ADSPBF533__"); \
72 break; \
73 case BFIN_CPU_BF534: \
74 builtin_define ("__ADSPBF534__"); \
75 break; \
76 case BFIN_CPU_BF536: \
77 builtin_define ("__ADSPBF536__"); \
78 break; \
79 case BFIN_CPU_BF537: \
80 builtin_define ("__ADSPBF537__"); \
81 break; \
82 case BFIN_CPU_BF538: \
83 builtin_define ("__ADSPBF538__"); \
84 break; \
85 case BFIN_CPU_BF539: \
86 builtin_define ("__ADSPBF539__"); \
87 break; \
88 case BFIN_CPU_BF542: \
89 builtin_define ("__ADSPBF542__"); \
90 builtin_define ("__ADSPBF54x__"); \
91 break; \
92 case BFIN_CPU_BF544: \
93 builtin_define ("__ADSPBF544__"); \
94 builtin_define ("__ADSPBF54x__"); \
95 break; \
96 case BFIN_CPU_BF548: \
97 builtin_define ("__ADSPBF548__"); \
98 builtin_define ("__ADSPBF54x__"); \
99 break; \
100 case BFIN_CPU_BF549: \
101 builtin_define ("__ADSPBF549__"); \
102 builtin_define ("__ADSPBF54x__"); \
103 break; \
104 case BFIN_CPU_BF561: \
105 builtin_define ("__ADSPBF561__"); \
106 break; \
107 } \
108 \
109 if (bfin_si_revision != -1) \
110 { \
111 /* space of 0xnnnn and a NUL */ \
112 char *buf = alloca (7); \
113 \
114 sprintf (buf, "0x%04x", bfin_si_revision); \
115 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
116 } \
117 \
118 if (bfin_workarounds) \
119 builtin_define ("__WORKAROUNDS_ENABLED"); \
120 if (ENABLE_WA_SPECULATIVE_LOADS) \
121 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
122 if (ENABLE_WA_SPECULATIVE_SYNCS) \
123 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
124 \
125 if (TARGET_FDPIC) \
126 builtin_define ("__BFIN_FDPIC__"); \
127 if (TARGET_ID_SHARED_LIBRARY \
128 && !TARGET_SEP_DATA) \
129 builtin_define ("__ID_SHARED_LIB__"); \
130 if (flag_no_builtin) \
131 builtin_define ("__NO_BUILTIN"); \
132 } \
133 while (0)
134 #endif
135
136 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
137 %{!mcpu=*:-mcpu=bf532} \
138 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
139 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
140 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
141 "
142 #ifndef SUBTARGET_DRIVER_SELF_SPECS
143 # define SUBTARGET_DRIVER_SELF_SPECS
144 #endif
145
146 #define LINK_GCC_C_SEQUENCE_SPEC "\
147 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
148 "
149
150 /* A C string constant that tells the GCC driver program options to pass to
151 the assembler. It can also specify how to translate options you give to GNU
152 CC into options for GCC to pass to the assembler. See the file `sun3.h'
153 for an example of this.
154
155 Do not define this macro if it does not need to do anything.
156
157 Defined in svr4.h. */
158 #undef ASM_SPEC
159 #define ASM_SPEC "\
160 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
161 %{mno-fdpic:-mnopic} %{mfdpic}"
162
163 #define LINK_SPEC "\
164 %{h*} %{v:-V} \
165 %{b} \
166 %{mfdpic:-melf32bfinfd -z text} \
167 %{static:-dn -Bstatic} \
168 %{shared:-G -Bdynamic} \
169 %{symbolic:-Bsymbolic} \
170 %{G*} \
171 %{YP,*} \
172 %{Qy:} %{!Qn:-Qy} \
173 -init __init -fini __fini "
174
175 /* Generate DSP instructions, like DSP halfword loads */
176 #define TARGET_DSP (1)
177
178 #define TARGET_DEFAULT 0
179
180 /* Maximum number of library ids we permit */
181 #define MAX_LIBRARY_ID 255
182
183 extern const char *bfin_library_id_string;
184
185 /* Sometimes certain combinations of command options do not make
186 sense on a particular target machine. You can define a macro
187 `OVERRIDE_OPTIONS' to take account of this. This macro, if
188 defined, is executed once just after all the command options have
189 been parsed.
190
191 Don't use this macro to turn on various extra optimizations for
192 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
193
194 #define OVERRIDE_OPTIONS override_options ()
195
196 #define FUNCTION_MODE SImode
197 #define Pmode SImode
198
199 /* store-condition-codes instructions store 0 for false
200 This is the value stored for true. */
201 #define STORE_FLAG_VALUE 1
202
203 /* Define this if pushing a word on the stack
204 makes the stack pointer a smaller address. */
205 #define STACK_GROWS_DOWNWARD
206
207 #define STACK_PUSH_CODE PRE_DEC
208
209 /* Define this to nonzero if the nominal address of the stack frame
210 is at the high-address end of the local variables;
211 that is, each additional local variable allocated
212 goes at a more negative offset in the frame. */
213 #define FRAME_GROWS_DOWNWARD 1
214
215 /* We define a dummy ARGP register; the parameters start at offset 0 from
216 it. */
217 #define FIRST_PARM_OFFSET(DECL) 0
218
219 /* Offset within stack frame to start allocating local variables at.
220 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
221 first local allocated. Otherwise, it is the offset to the BEGINNING
222 of the first local allocated. */
223 #define STARTING_FRAME_OFFSET 0
224
225 /* Register to use for pushing function arguments. */
226 #define STACK_POINTER_REGNUM REG_P6
227
228 /* Base register for access to local variables of the function. */
229 #define FRAME_POINTER_REGNUM REG_P7
230
231 /* A dummy register that will be eliminated to either FP or SP. */
232 #define ARG_POINTER_REGNUM REG_ARGP
233
234 /* `PIC_OFFSET_TABLE_REGNUM'
235 The register number of the register used to address a table of
236 static data addresses in memory. In some cases this register is
237 defined by a processor's "application binary interface" (ABI).
238 When this macro is defined, RTL is generated for this register
239 once, as with the stack pointer and frame pointer registers. If
240 this macro is not defined, it is up to the machine-dependent files
241 to allocate such a register (if necessary). */
242 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
243
244 #define FDPIC_FPTR_REGNO REG_P1
245 #define FDPIC_REGNO REG_P3
246 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
247
248 /* A static chain register for nested functions. We need to use a
249 call-clobbered register for this. */
250 #define STATIC_CHAIN_REGNUM REG_P2
251
252 /* Define this if functions should assume that stack space has been
253 allocated for arguments even when their values are passed in
254 registers.
255
256 The value of this macro is the size, in bytes, of the area reserved for
257 arguments passed in registers.
258
259 This space can either be allocated by the caller or be a part of the
260 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
261 says which. */
262 #define FIXED_STACK_AREA 12
263 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
264
265 /* Define this if the above stack space is to be considered part of the
266 * space allocated by the caller. */
267 #define OUTGOING_REG_PARM_STACK_SPACE 1
268
269 /* Define this if the maximum size of all the outgoing args is to be
270 accumulated and pushed during the prologue. The amount can be
271 found in the variable current_function_outgoing_args_size. */
272 #define ACCUMULATE_OUTGOING_ARGS 1
273
274 /* Value should be nonzero if functions must have frame pointers.
275 Zero means the frame pointer need not be set up (and parms
276 may be accessed via the stack pointer) in functions that seem suitable.
277 This is computed in `reload', in reload1.c.
278 */
279 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
280
281 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
282
283 /* If defined, a C expression to compute the alignment for a local
284 variable. TYPE is the data type, and ALIGN is the alignment that
285 the object would ordinarily have. The value of this macro is used
286 instead of that alignment to align the object.
287
288 If this macro is not defined, then ALIGN is used.
289
290 One use of this macro is to increase alignment of medium-size
291 data to make it all fit in fewer cache lines. */
292
293 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
294
295 /* Make strings word-aligned so strcpy from constants will be faster. */
296 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
297 (TREE_CODE (EXP) == STRING_CST \
298 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
299
300 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
301 #define TRAMPOLINE_TEMPLATE(FILE) \
302 if (TARGET_FDPIC) \
303 { \
304 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
305 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
306 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
307 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
308 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
309 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
310 fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \
311 fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \
312 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
313 } \
314 else \
315 { \
316 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
317 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
318 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
319 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
320 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
321 }
322
323 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
324 initialize_trampoline (TRAMP, FNADDR, CXT)
325 \f
326 /* Definitions for register eliminations.
327
328 This is an array of structures. Each structure initializes one pair
329 of eliminable registers. The "from" register number is given first,
330 followed by "to". Eliminations of the same "from" register are listed
331 in order of preference.
332
333 There are two registers that can always be eliminated on the i386.
334 The frame pointer and the arg pointer can be replaced by either the
335 hard frame pointer or to the stack pointer, depending upon the
336 circumstances. The hard frame pointer is not used before reload and
337 so it is not eligible for elimination. */
338
339 #define ELIMINABLE_REGS \
340 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
341 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
342 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
343
344 /* Given FROM and TO register numbers, say whether this elimination is
345 allowed. Frame pointer elimination is automatically handled.
346
347 All other eliminations are valid. */
348
349 #define CAN_ELIMINATE(FROM, TO) \
350 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
351
352 /* Define the offset between two registers, one to be eliminated, and the other
353 its replacement, at the start of a routine. */
354
355 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
356 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
357 \f
358 /* This processor has
359 8 data register for doing arithmetic
360 8 pointer register for doing addressing, including
361 1 stack pointer P6
362 1 frame pointer P7
363 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
364 1 condition code flag register CC
365 5 return address registers RETS/I/X/N/E
366 1 arithmetic status register (ASTAT). */
367
368 #define FIRST_PSEUDO_REGISTER 50
369
370 #define D_REGNO_P(X) ((X) <= REG_R7)
371 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
372 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
373 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
374 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
375 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
376 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
377 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
378 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
379
380 #define REGISTER_NAMES { \
381 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
382 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
383 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
384 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
385 "A0", "A1", \
386 "CC", \
387 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
388 "ARGP", \
389 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
390 }
391
392 #define SHORT_REGISTER_NAMES { \
393 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
394 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
395 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
396 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
397
398 #define HIGH_REGISTER_NAMES { \
399 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
400 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
401 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
402 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
403
404 #define DREGS_PAIR_NAMES { \
405 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
406
407 #define BYTE_REGISTER_NAMES { \
408 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
409
410
411 /* 1 for registers that have pervasive standard uses
412 and are not available for the register allocator. */
413
414 #define FIXED_REGISTERS \
415 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
416 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
417 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
418 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
419 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
420 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
421 /*lb0/1 */ \
422 1, 1 \
423 }
424
425 /* 1 for registers not available across function calls.
426 These must include the FIXED_REGISTERS and also any
427 registers that can be used without being saved.
428 The latter must include the registers where values are returned
429 and the register where structure-value addresses are passed.
430 Aside from that, you can include as many other registers as you like. */
431
432 #define CALL_USED_REGISTERS \
433 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
434 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
435 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
436 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
437 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
438 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
439 /*lb0/1 */ \
440 1, 1 \
441 }
442
443 /* Order in which to allocate registers. Each register must be
444 listed once, even those in FIXED_REGISTERS. List frame pointer
445 late and fixed registers last. Note that, in general, we prefer
446 registers listed in CALL_USED_REGISTERS, keeping the others
447 available for storage of persistent values. */
448
449 #define REG_ALLOC_ORDER \
450 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
451 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
452 REG_A0, REG_A1, \
453 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
454 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
455 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
456 REG_ASTAT, REG_SEQSTAT, REG_USP, \
457 REG_CC, REG_ARGP, \
458 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
459 }
460
461 /* Macro to conditionally modify fixed_regs/call_used_regs. */
462 #define CONDITIONAL_REGISTER_USAGE \
463 { \
464 conditional_register_usage(); \
465 if (TARGET_FDPIC) \
466 call_used_regs[FDPIC_REGNO] = 1; \
467 if (!TARGET_FDPIC && flag_pic) \
468 { \
469 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
470 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
471 } \
472 }
473
474 /* Define the classes of registers for register constraints in the
475 machine description. Also define ranges of constants.
476
477 One of the classes must always be named ALL_REGS and include all hard regs.
478 If there is more than one class, another class must be named NO_REGS
479 and contain no registers.
480
481 The name GENERAL_REGS must be the name of a class (or an alias for
482 another name such as ALL_REGS). This is the class of registers
483 that is allowed by "g" or "r" in a register constraint.
484 Also, registers outside this class are allocated only when
485 instructions express preferences for them.
486
487 The classes must be numbered in nondecreasing order; that is,
488 a larger-numbered class must never be contained completely
489 in a smaller-numbered class.
490
491 For any two classes, it is very desirable that there be another
492 class that represents their union. */
493
494
495 enum reg_class
496 {
497 NO_REGS,
498 IREGS,
499 BREGS,
500 LREGS,
501 MREGS,
502 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
503 DAGREGS,
504 EVEN_AREGS,
505 ODD_AREGS,
506 AREGS,
507 CCREGS,
508 EVEN_DREGS,
509 ODD_DREGS,
510 D0REGS,
511 D1REGS,
512 D2REGS,
513 D3REGS,
514 D4REGS,
515 D5REGS,
516 D6REGS,
517 D7REGS,
518 DREGS,
519 P0REGS,
520 FDPIC_REGS,
521 FDPIC_FPTR_REGS,
522 PREGS_CLOBBERED,
523 PREGS,
524 IPREGS,
525 DPREGS,
526 MOST_REGS,
527 LT_REGS,
528 LC_REGS,
529 LB_REGS,
530 PROLOGUE_REGS,
531 NON_A_CC_REGS,
532 ALL_REGS, LIM_REG_CLASSES
533 };
534
535 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
536
537 #define GENERAL_REGS DPREGS
538
539 /* Give names of register classes as strings for dump file. */
540
541 #define REG_CLASS_NAMES \
542 { "NO_REGS", \
543 "IREGS", \
544 "BREGS", \
545 "LREGS", \
546 "MREGS", \
547 "CIRCREGS", \
548 "DAGREGS", \
549 "EVEN_AREGS", \
550 "ODD_AREGS", \
551 "AREGS", \
552 "CCREGS", \
553 "EVEN_DREGS", \
554 "ODD_DREGS", \
555 "D0REGS", \
556 "D1REGS", \
557 "D2REGS", \
558 "D3REGS", \
559 "D4REGS", \
560 "D5REGS", \
561 "D6REGS", \
562 "D7REGS", \
563 "DREGS", \
564 "P0REGS", \
565 "FDPIC_REGS", \
566 "FDPIC_FPTR_REGS", \
567 "PREGS_CLOBBERED", \
568 "PREGS", \
569 "IPREGS", \
570 "DPREGS", \
571 "MOST_REGS", \
572 "LT_REGS", \
573 "LC_REGS", \
574 "LB_REGS", \
575 "PROLOGUE_REGS", \
576 "NON_A_CC_REGS", \
577 "ALL_REGS" }
578
579 /* An initializer containing the contents of the register classes, as integers
580 which are bit masks. The Nth integer specifies the contents of class N.
581 The way the integer MASK is interpreted is that register R is in the class
582 if `MASK & (1 << R)' is 1.
583
584 When the machine has more than 32 registers, an integer does not suffice.
585 Then the integers are replaced by sub-initializers, braced groupings
586 containing several integers. Each sub-initializer must be suitable as an
587 initializer for the type `HARD_REG_SET' which is defined in
588 `hard-reg-set.h'. */
589
590 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
591 MOST_REGS as the union of DPREGS and DAGREGS. */
592
593 #define REG_CLASS_CONTENTS \
594 /* 31 - 0 63-32 */ \
595 { { 0x00000000, 0 }, /* NO_REGS */ \
596 { 0x000f0000, 0 }, /* IREGS */ \
597 { 0x00f00000, 0 }, /* BREGS */ \
598 { 0x0f000000, 0 }, /* LREGS */ \
599 { 0xf0000000, 0 }, /* MREGS */ \
600 { 0x0fff0000, 0 }, /* CIRCREGS */ \
601 { 0xffff0000, 0 }, /* DAGREGS */ \
602 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
603 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
604 { 0x00000000, 0x3 }, /* AREGS */ \
605 { 0x00000000, 0x4 }, /* CCREGS */ \
606 { 0x00000055, 0 }, /* EVEN_DREGS */ \
607 { 0x000000aa, 0 }, /* ODD_DREGS */ \
608 { 0x00000001, 0 }, /* D0REGS */ \
609 { 0x00000002, 0 }, /* D1REGS */ \
610 { 0x00000004, 0 }, /* D2REGS */ \
611 { 0x00000008, 0 }, /* D3REGS */ \
612 { 0x00000010, 0 }, /* D4REGS */ \
613 { 0x00000020, 0 }, /* D5REGS */ \
614 { 0x00000040, 0 }, /* D6REGS */ \
615 { 0x00000080, 0 }, /* D7REGS */ \
616 { 0x000000ff, 0 }, /* DREGS */ \
617 { 0x00000100, 0x000 }, /* P0REGS */ \
618 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
619 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
620 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
621 { 0x0000ff00, 0x800 }, /* PREGS */ \
622 { 0x000fff00, 0x800 }, /* IPREGS */ \
623 { 0x0000ffff, 0x800 }, /* DPREGS */ \
624 { 0xffffffff, 0x800 }, /* MOST_REGS */\
625 { 0x00000000, 0x3000 }, /* LT_REGS */\
626 { 0x00000000, 0xc000 }, /* LC_REGS */\
627 { 0x00000000, 0x30000 }, /* LB_REGS */\
628 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
629 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
630 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
631
632 #define IREG_POSSIBLE_P(OUTER) \
633 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
634 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
635 || (OUTER) == MEM || (OUTER) == ADDRESS)
636
637 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
638 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
639
640 #define INDEX_REG_CLASS PREGS
641
642 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
643 (P_REGNO_P (X) || (X) == REG_ARGP \
644 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
645 && I_REGNO_P (X)))
646
647 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
648 ((X) >= FIRST_PSEUDO_REGISTER \
649 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
650
651 #ifdef REG_OK_STRICT
652 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
653 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
654 #else
655 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
656 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
657 #endif
658
659 #define REGNO_OK_FOR_INDEX_P(X) 0
660
661 /* Get reg_class from a letter such as appears in the machine description. */
662
663 #define REG_CLASS_FROM_CONSTRAINT(LETTER, STR) \
664 ((LETTER) == 'a' ? PREGS : \
665 (LETTER) == 'Z' ? FDPIC_REGS : \
666 (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \
667 (LETTER) == 'd' ? DREGS : \
668 (LETTER) == 'z' ? PREGS_CLOBBERED : \
669 (LETTER) == 'D' ? EVEN_DREGS : \
670 (LETTER) == 'W' ? ODD_DREGS : \
671 (LETTER) == 'e' ? AREGS : \
672 (LETTER) == 'A' ? EVEN_AREGS : \
673 (LETTER) == 'B' ? ODD_AREGS : \
674 (LETTER) == 'b' ? IREGS : \
675 (LETTER) == 'v' ? BREGS : \
676 (LETTER) == 'f' ? MREGS : \
677 (LETTER) == 'c' ? CIRCREGS : \
678 (LETTER) == 'C' ? CCREGS : \
679 (LETTER) == 't' ? LT_REGS : \
680 (LETTER) == 'k' ? LC_REGS : \
681 (LETTER) == 'u' ? LB_REGS : \
682 (LETTER) == 'x' ? MOST_REGS : \
683 (LETTER) == 'y' ? PROLOGUE_REGS : \
684 (LETTER) == 'w' ? NON_A_CC_REGS : \
685 (LETTER) == 'q' \
686 ? ((STR)[1] == '0' ? D0REGS \
687 : (STR)[1] == '1' ? D1REGS \
688 : (STR)[1] == '2' ? D2REGS \
689 : (STR)[1] == '3' ? D3REGS \
690 : (STR)[1] == '4' ? D4REGS \
691 : (STR)[1] == '5' ? D5REGS \
692 : (STR)[1] == '6' ? D6REGS \
693 : (STR)[1] == '7' ? D7REGS \
694 : (STR)[1] == 'A' ? P0REGS \
695 : NO_REGS) : \
696 NO_REGS)
697
698 /* The same information, inverted:
699 Return the class number of the smallest class containing
700 reg number REGNO. This could be a conditional expression
701 or could index an array. */
702
703 #define REGNO_REG_CLASS(REGNO) \
704 ((REGNO) == REG_R0 ? D0REGS \
705 : (REGNO) == REG_R1 ? D1REGS \
706 : (REGNO) == REG_R2 ? D2REGS \
707 : (REGNO) == REG_R3 ? D3REGS \
708 : (REGNO) == REG_R4 ? D4REGS \
709 : (REGNO) == REG_R5 ? D5REGS \
710 : (REGNO) == REG_R6 ? D6REGS \
711 : (REGNO) == REG_R7 ? D7REGS \
712 : (REGNO) == REG_P0 ? P0REGS \
713 : (REGNO) < REG_I0 ? PREGS \
714 : (REGNO) == REG_ARGP ? PREGS \
715 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
716 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
717 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
718 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
719 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
720 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
721 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
722 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
723 : (REGNO) == REG_CC ? CCREGS \
724 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
725 : NO_REGS)
726
727 /* When defined, the compiler allows registers explicitly used in the
728 rtl to be used as spill registers but prevents the compiler from
729 extending the lifetime of these registers. */
730 #define SMALL_REGISTER_CLASSES 1
731
732 #define CLASS_LIKELY_SPILLED_P(CLASS) \
733 ((CLASS) == PREGS_CLOBBERED \
734 || (CLASS) == PROLOGUE_REGS \
735 || (CLASS) == P0REGS \
736 || (CLASS) == D0REGS \
737 || (CLASS) == D1REGS \
738 || (CLASS) == D2REGS \
739 || (CLASS) == CCREGS)
740
741 /* Do not allow to store a value in REG_CC for any mode */
742 /* Do not allow to store value in pregs if mode is not SI*/
743 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
744
745 /* Return the maximum number of consecutive registers
746 needed to represent mode MODE in a register of class CLASS. */
747 #define CLASS_MAX_NREGS(CLASS, MODE) \
748 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
749 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
750
751 #define HARD_REGNO_NREGS(REGNO, MODE) \
752 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
753 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
754 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
755
756 /* A C expression that is nonzero if hard register TO can be
757 considered for use as a rename register for FROM register */
758 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
759
760 /* A C expression that is nonzero if it is desirable to choose
761 register allocation so as to avoid move instructions between a
762 value of mode MODE1 and a value of mode MODE2.
763
764 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
765 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
766 MODE2)' must be zero. */
767 #define MODES_TIEABLE_P(MODE1, MODE2) \
768 ((MODE1) == (MODE2) \
769 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
770 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
771 && (GET_MODE_CLASS (MODE2) == MODE_INT \
772 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
773 && (MODE1) != BImode && (MODE2) != BImode \
774 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
775 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
776
777 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
778 A C expression that places additional restrictions on the register
779 class to use when it is necessary to copy value X into a register
780 in class CLASS. The value is a register class; perhaps CLASS, or
781 perhaps another, smaller class. */
782 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
783 (GET_CODE (X) == POST_INC \
784 || GET_CODE (X) == POST_DEC \
785 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
786
787 /* Function Calling Conventions. */
788
789 /* The type of the current function; normal functions are of type
790 SUBROUTINE. */
791 typedef enum {
792 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
793 } e_funkind;
794
795 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
796
797 /* Flags for the call/call_value rtl operations set up by function_arg */
798 #define CALL_NORMAL 0x00000000 /* no special processing */
799 #define CALL_LONG 0x00000001 /* always call indirect */
800 #define CALL_SHORT 0x00000002 /* always call by symbol */
801
802 typedef struct {
803 int words; /* # words passed so far */
804 int nregs; /* # registers available for passing */
805 int *arg_regs; /* array of register -1 terminated */
806 int call_cookie; /* Do special things for this call */
807 } CUMULATIVE_ARGS;
808
809 /* Define where to put the arguments to a function.
810 Value is zero to push the argument on the stack,
811 or a hard register in which to store the argument.
812
813 MODE is the argument's machine mode.
814 TYPE is the data type of the argument (as a tree).
815 This is null for libcalls where that information may
816 not be available.
817 CUM is a variable of type CUMULATIVE_ARGS which gives info about
818 the preceding args and about the function being called.
819 NAMED is nonzero if this argument is a named parameter
820 (otherwise it is an extra parameter matching an ellipsis). */
821
822 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
823 (function_arg (&CUM, MODE, TYPE, NAMED))
824
825 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
826
827
828 /* Initialize a variable CUM of type CUMULATIVE_ARGS
829 for a call to a function whose data type is FNTYPE.
830 For a library call, FNTYPE is 0. */
831 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
832 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
833
834 /* Update the data in CUM to advance over an argument
835 of mode MODE and data type TYPE.
836 (TYPE is null for libcalls where that information may not be available.) */
837 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
838 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
839
840 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
841
842 /* Define how to find the value returned by a function.
843 VALTYPE is the data type of the value (as a tree).
844 If the precise function being called is known, FUNC is its FUNCTION_DECL;
845 otherwise, FUNC is 0.
846 */
847
848 #define VALUE_REGNO(MODE) (REG_R0)
849
850 #define FUNCTION_VALUE(VALTYPE, FUNC) \
851 gen_rtx_REG (TYPE_MODE (VALTYPE), \
852 VALUE_REGNO(TYPE_MODE(VALTYPE)))
853
854 /* Define how to find the value returned by a library function
855 assuming the value has mode MODE. */
856
857 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
858
859 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
860
861 #define DEFAULT_PCC_STRUCT_RETURN 0
862 #define RETURN_IN_MEMORY(TYPE) bfin_return_in_memory(TYPE)
863
864 /* Before the prologue, the return address is in the RETS register. */
865 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
866
867 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
868
869 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
870
871 /* Call instructions don't modify the stack pointer on the Blackfin. */
872 #define INCOMING_FRAME_SP_OFFSET 0
873
874 /* Describe how we implement __builtin_eh_return. */
875 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
876 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
877 #define EH_RETURN_HANDLER_RTX \
878 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
879
880 /* Addressing Modes */
881
882 /* Recognize any constant value that is a valid address. */
883 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
884
885 /* Nonzero if the constant value X is a legitimate general operand.
886 symbol_ref are not legitimate and will be put into constant pool.
887 See force_const_mem().
888 If -mno-pool, all constants are legitimate.
889 */
890 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
891
892 /* A number, the maximum number of registers that can appear in a
893 valid memory address. Note that it is up to you to specify a
894 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
895 would ever accept. */
896 #define MAX_REGS_PER_ADDRESS 1
897
898 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
899 that is a valid memory address for an instruction.
900 The MODE argument is the machine mode for the MEM expression
901 that wants to use this address.
902
903 Blackfin addressing modes are as follows:
904
905 [preg]
906 [preg + imm16]
907
908 B [ Preg + uimm15 ]
909 W [ Preg + uimm16m2 ]
910 [ Preg + uimm17m4 ]
911
912 [preg++]
913 [preg--]
914 [--sp]
915 */
916
917 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
918 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
919
920 #ifdef REG_OK_STRICT
921 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
922 do { \
923 if (bfin_legitimate_address_p (MODE, X, 1)) \
924 goto WIN; \
925 } while (0);
926 #else
927 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
928 do { \
929 if (bfin_legitimate_address_p (MODE, X, 0)) \
930 goto WIN; \
931 } while (0);
932 #endif
933
934 /* Try machine-dependent ways of modifying an illegitimate address
935 to be legitimate. If we find one, return the new, valid address.
936 This macro is used in only one place: `memory_address' in explow.c.
937
938 OLDX is the address as it was before break_out_memory_refs was called.
939 In some cases it is useful to look at this to decide what needs to be done.
940
941 MODE and WIN are passed so that this macro can use
942 GO_IF_LEGITIMATE_ADDRESS.
943
944 It is always safe for this macro to do nothing. It exists to recognize
945 opportunities to optimize the output.
946 */
947 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
948 do { \
949 rtx _q = legitimize_address(X, OLDX, MODE); \
950 if (_q) { X = _q; goto WIN; } \
951 } while (0)
952
953 #define HAVE_POST_INCREMENT 1
954 #define HAVE_POST_DECREMENT 1
955 #define HAVE_PRE_DECREMENT 1
956
957 /* `LEGITIMATE_PIC_OPERAND_P (X)'
958 A C expression that is nonzero if X is a legitimate immediate
959 operand on the target machine when generating position independent
960 code. You can assume that X satisfies `CONSTANT_P', so you need
961 not check this. You can also assume FLAG_PIC is true, so you need
962 not check it either. You need not define this macro if all
963 constants (including `SYMBOL_REF') can be immediate operands when
964 generating position independent code. */
965 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
966
967 #define SYMBOLIC_CONST(X) \
968 (GET_CODE (X) == SYMBOL_REF \
969 || GET_CODE (X) == LABEL_REF \
970 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
971
972 /*
973 A C statement or compound statement with a conditional `goto
974 LABEL;' executed if memory address X (an RTX) can have different
975 meanings depending on the machine mode of the memory reference it
976 is used for or if the address is valid for some modes but not
977 others.
978
979 Autoincrement and autodecrement addresses typically have
980 mode-dependent effects because the amount of the increment or
981 decrement is the size of the operand being addressed. Some
982 machines have other mode-dependent addresses. Many RISC machines
983 have no mode-dependent addresses.
984
985 You may assume that ADDR is a valid address for the machine.
986 */
987 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
988
989 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
990
991 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
992 is done just by pretending it is already truncated. */
993 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
994
995 /* Max number of bytes we can move from memory to memory
996 in one reasonably fast instruction. */
997 #define MOVE_MAX UNITS_PER_WORD
998
999 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1000 move-instruction pairs, we will do a movmem or libcall instead. */
1001
1002 #define MOVE_RATIO 5
1003
1004 /* STORAGE LAYOUT: target machine storage layout
1005 Define this macro as a C expression which is nonzero if accessing
1006 less than a word of memory (i.e. a `char' or a `short') is no
1007 faster than accessing a word of memory, i.e., if such access
1008 require more than one instruction or if there is no difference in
1009 cost between byte and (aligned) word loads.
1010
1011 When this macro is not defined, the compiler will access a field by
1012 finding the smallest containing object; when it is defined, a
1013 fullword load will be used if alignment permits. Unless bytes
1014 accesses are faster than word accesses, using word accesses is
1015 preferable since it may eliminate subsequent memory access if
1016 subsequent accesses occur to other fields in the same word of the
1017 structure, but to different bytes. */
1018 #define SLOW_BYTE_ACCESS 0
1019 #define SLOW_SHORT_ACCESS 0
1020
1021 /* Define this if most significant bit is lowest numbered
1022 in instructions that operate on numbered bit-fields. */
1023 #define BITS_BIG_ENDIAN 0
1024
1025 /* Define this if most significant byte of a word is the lowest numbered.
1026 We can't access bytes but if we could we would in the Big Endian order. */
1027 #define BYTES_BIG_ENDIAN 0
1028
1029 /* Define this if most significant word of a multiword number is numbered. */
1030 #define WORDS_BIG_ENDIAN 0
1031
1032 /* number of bits in an addressable storage unit */
1033 #define BITS_PER_UNIT 8
1034
1035 /* Width in bits of a "word", which is the contents of a machine register.
1036 Note that this is not necessarily the width of data type `int';
1037 if using 16-bit ints on a 68000, this would still be 32.
1038 But on a machine with 16-bit registers, this would be 16. */
1039 #define BITS_PER_WORD 32
1040
1041 /* Width of a word, in units (bytes). */
1042 #define UNITS_PER_WORD 4
1043
1044 /* Width in bits of a pointer.
1045 See also the macro `Pmode1' defined below. */
1046 #define POINTER_SIZE 32
1047
1048 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1049 #define POINTER_BOUNDARY 32
1050
1051 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1052 #define PARM_BOUNDARY 32
1053
1054 /* Boundary (in *bits*) on which stack pointer should be aligned. */
1055 #define STACK_BOUNDARY 32
1056
1057 /* Allocation boundary (in *bits*) for the code of a function. */
1058 #define FUNCTION_BOUNDARY 32
1059
1060 /* Alignment of field after `int : 0' in a structure. */
1061 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
1062
1063 /* No data type wants to be aligned rounder than this. */
1064 #define BIGGEST_ALIGNMENT 32
1065
1066 /* Define this if move instructions will actually fail to work
1067 when given unaligned data. */
1068 #define STRICT_ALIGNMENT 1
1069
1070 /* (shell-command "rm c-decl.o stor-layout.o")
1071 * never define PCC_BITFIELD_TYPE_MATTERS
1072 * really cause some alignment problem
1073 */
1074
1075 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1076 BITS_PER_UNIT)
1077
1078 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1079 BITS_PER_UNIT)
1080
1081
1082 /* what is the 'type' of size_t */
1083 #define SIZE_TYPE "long unsigned int"
1084
1085 /* Define this as 1 if `char' should by default be signed; else as 0. */
1086 #define DEFAULT_SIGNED_CHAR 1
1087 #define FLOAT_TYPE_SIZE BITS_PER_WORD
1088 #define SHORT_TYPE_SIZE 16
1089 #define CHAR_TYPE_SIZE 8
1090 #define INT_TYPE_SIZE 32
1091 #define LONG_TYPE_SIZE 32
1092 #define LONG_LONG_TYPE_SIZE 64
1093
1094 /* Note: Fix this to depend on target switch. -- lev */
1095
1096 /* Note: Try to implement double and force long double. -- tonyko
1097 * #define __DOUBLES_ARE_FLOATS__
1098 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
1099 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
1100 * #define DOUBLES_ARE_FLOATS 1
1101 */
1102
1103 #define DOUBLE_TYPE_SIZE 64
1104 #define LONG_DOUBLE_TYPE_SIZE 64
1105
1106 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
1107 A macro to update M and UNSIGNEDP when an object whose type is
1108 TYPE and which has the specified mode and signedness is to be
1109 stored in a register. This macro is only called when TYPE is a
1110 scalar type.
1111
1112 On most RISC machines, which only have operations that operate on
1113 a full register, define this macro to set M to `word_mode' if M is
1114 an integer mode narrower than `BITS_PER_WORD'. In most cases,
1115 only integer modes should be widened because wider-precision
1116 floating-point operations are usually more expensive than their
1117 narrower counterparts.
1118
1119 For most machines, the macro definition does not change UNSIGNEDP.
1120 However, some machines, have instructions that preferentially
1121 handle either signed or unsigned quantities of certain modes. For
1122 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1123 instructions sign-extend the result to 64 bits. On such machines,
1124 set UNSIGNEDP according to which kind of extension is more
1125 efficient.
1126
1127 Do not define this macro if it would never modify M.*/
1128
1129 #define BFIN_PROMOTE_MODE_P(MODE) \
1130 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
1131 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1132
1133 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1134 if (BFIN_PROMOTE_MODE_P(MODE)) \
1135 { \
1136 if (MODE == QImode) \
1137 UNSIGNEDP = 1; \
1138 else if (MODE == HImode) \
1139 UNSIGNEDP = 0; \
1140 (MODE) = SImode; \
1141 }
1142
1143 /* Describing Relative Costs of Operations */
1144
1145 /* Do not put function addr into constant pool */
1146 #define NO_FUNCTION_CSE 1
1147
1148 /* A C expression for the cost of moving data from a register in class FROM to
1149 one in class TO. The classes are expressed using the enumeration values
1150 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1151 interpreted relative to that.
1152
1153 It is not required that the cost always equal 2 when FROM is the same as TO;
1154 on some machines it is expensive to move between registers if they are not
1155 general registers. */
1156
1157 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1158 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1159
1160 /* A C expression for the cost of moving data of mode M between a
1161 register and memory. A value of 2 is the default; this cost is
1162 relative to those in `REGISTER_MOVE_COST'.
1163
1164 If moving between registers and memory is more expensive than
1165 between two registers, you should define this macro to express the
1166 relative cost. */
1167
1168 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1169 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1170
1171 /* Specify the machine mode that this machine uses
1172 for the index in the tablejump instruction. */
1173 #define CASE_VECTOR_MODE SImode
1174
1175 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1176
1177 /* Define if operations between registers always perform the operation
1178 on the full register even if a narrower mode is specified.
1179 #define WORD_REGISTER_OPERATIONS
1180 */
1181
1182 #define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140)
1183 #define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767)
1184 #define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535)
1185 #define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63)
1186 #define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0)
1187 #define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31)
1188 #define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7)
1189 #define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15)
1190 #define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3)
1191 #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
1192
1193 #define CONSTRAINT_LEN(C, STR) \
1194 ((C) == 'P' || (C) == 'M' || (C) == 'N' || (C) == 'q' ? 2 \
1195 : (C) == 'K' ? 3 \
1196 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1197
1198 #define CONST_OK_FOR_P(VALUE, STR) \
1199 ((STR)[1] == '0' ? (VALUE) == 0 \
1200 : (STR)[1] == '1' ? (VALUE) == 1 \
1201 : (STR)[1] == '2' ? (VALUE) == 2 \
1202 : (STR)[1] == '3' ? (VALUE) == 3 \
1203 : (STR)[1] == '4' ? (VALUE) == 4 \
1204 : (STR)[1] == 'A' ? (VALUE) != MACFLAG_M && (VALUE) != MACFLAG_IS_M \
1205 : (STR)[1] == 'B' ? (VALUE) == MACFLAG_M || (VALUE) == MACFLAG_IS_M \
1206 : 0)
1207
1208 #define CONST_OK_FOR_K(VALUE, STR) \
1209 ((STR)[1] == 'u' \
1210 ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \
1211 : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \
1212 : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \
1213 : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \
1214 : 0) \
1215 : (STR)[1] == 's' \
1216 ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \
1217 : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \
1218 : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \
1219 : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \
1220 : 0) \
1221 : (STR)[1] == 'n' \
1222 ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \
1223 : 0) \
1224 : (STR)[1] == 'N' \
1225 ? ((STR)[2] == '7' ? CONST_7BIT_IMM_P (-(VALUE)) \
1226 : 0) \
1227 : 0)
1228
1229 #define CONST_OK_FOR_M(VALUE, STR) \
1230 ((STR)[1] == '1' ? (VALUE) == 255 \
1231 : (STR)[1] == '2' ? (VALUE) == 65535 \
1232 : 0)
1233
1234 /* The letters I, J, K, L and M in a register constraint string
1235 can be used to stand for particular ranges of immediate operands.
1236 This macro defines what the ranges are.
1237 C is the letter, and VALUE is a constant value.
1238 Return 1 if VALUE is in the range specified by C.
1239
1240 bfin constant operands are as follows
1241
1242 J 2**N 5bit imm scaled
1243 Ks7 -64 .. 63 signed 7bit imm
1244 Ku5 0..31 unsigned 5bit imm
1245 Ks4 -8 .. 7 signed 4bit imm
1246 Ks3 -4 .. 3 signed 3bit imm
1247 Ku3 0 .. 7 unsigned 3bit imm
1248 Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
1249 */
1250 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1251 ((C) == 'J' ? (log2constp (VALUE)) \
1252 : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \
1253 : (C) == 'L' ? log2constp (~(VALUE)) \
1254 : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \
1255 : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \
1256 : 0)
1257
1258 /*Constant Output Formats */
1259 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1260 ((C) == 'H' ? 1 : 0)
1261
1262 #define EXTRA_CONSTRAINT(VALUE, D) \
1263 ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0)
1264
1265 /* Evaluates to true if A and B are mac flags that can be used
1266 together in a single multiply insn. That is the case if they are
1267 both the same flag not involving M, or if one is a combination of
1268 the other with M. */
1269 #define MACFLAGS_MATCH_P(A, B) \
1270 ((A) == (B) \
1271 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1272 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1273 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1274 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1275
1276 /* Switch into a generic section. */
1277 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1278
1279 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1280 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1281
1282 typedef enum sections {
1283 CODE_DIR,
1284 DATA_DIR,
1285 LAST_SECT_NM
1286 } SECT_ENUM_T;
1287
1288 typedef enum directives {
1289 LONG_CONST_DIR,
1290 SHORT_CONST_DIR,
1291 BYTE_CONST_DIR,
1292 SPACE_DIR,
1293 INIT_DIR,
1294 LAST_DIR_NM
1295 } DIR_ENUM_T;
1296
1297 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1298 ((C) == ';' \
1299 || ((C) == '|' && (STR)[1] == '|'))
1300
1301 #define TEXT_SECTION_ASM_OP ".text;"
1302 #define DATA_SECTION_ASM_OP ".data;"
1303
1304 #define ASM_APP_ON ""
1305 #define ASM_APP_OFF ""
1306
1307 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1308 do { fputs (".global ", FILE); \
1309 assemble_name (FILE, NAME); \
1310 fputc (';',FILE); \
1311 fputc ('\n',FILE); \
1312 } while (0)
1313
1314 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1315 do { \
1316 fputs (".type ", FILE); \
1317 assemble_name (FILE, NAME); \
1318 fputs (", STT_FUNC", FILE); \
1319 fputc (';',FILE); \
1320 fputc ('\n',FILE); \
1321 ASM_OUTPUT_LABEL(FILE, NAME); \
1322 } while (0)
1323
1324 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1325 do { assemble_name (FILE, NAME); \
1326 fputs (":\n",FILE); \
1327 } while (0)
1328
1329 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1330 do { fprintf (FILE, "_%s", NAME); \
1331 } while (0)
1332
1333 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1334 do { char __buf[256]; \
1335 fprintf (FILE, "\t.dd\t"); \
1336 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1337 assemble_name (FILE, __buf); \
1338 fputc (';', FILE); \
1339 fputc ('\n', FILE); \
1340 } while (0)
1341
1342 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1343 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1344
1345 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1346 do { \
1347 char __buf[256]; \
1348 fprintf (FILE, "\t.dd\t"); \
1349 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1350 assemble_name (FILE, __buf); \
1351 fputs (" - ", FILE); \
1352 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1353 assemble_name (FILE, __buf); \
1354 fputc (';', FILE); \
1355 fputc ('\n', FILE); \
1356 } while (0)
1357
1358 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1359 do { \
1360 if ((LOG) != 0) \
1361 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1362 } while (0)
1363
1364 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1365 do { \
1366 asm_output_skip (FILE, SIZE); \
1367 } while (0)
1368
1369 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1370 do { \
1371 switch_to_section (data_section); \
1372 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1373 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1374 ASM_OUTPUT_LABEL (FILE, NAME); \
1375 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1376 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1377 } while (0)
1378
1379 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1380 do { \
1381 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1382 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1383
1384 #define ASM_COMMENT_START "//"
1385
1386 #define FUNCTION_PROFILER(FILE, LABELNO) \
1387 do { \
1388 fprintf (FILE, "\tCALL __mcount;\n"); \
1389 } while(0)
1390
1391 #undef NO_PROFILE_COUNTERS
1392 #define NO_PROFILE_COUNTERS 1
1393
1394 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1395 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1396
1397 extern struct rtx_def *bfin_compare_op0, *bfin_compare_op1;
1398 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1399
1400 /* This works for GAS and some other assemblers. */
1401 #define SET_ASM_OP ".set "
1402
1403 /* DBX register number for a given compiler register number */
1404 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1405
1406 #define SIZE_ASM_OP "\t.size\t"
1407
1408 extern int splitting_for_sched;
1409
1410 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1411
1412 #endif /* _BFIN_CONFIG */