gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "tm_p.h"
  85 #include "flags.h"
  86 #include "regs.h"
  87 #include "hard-reg-set.h"
  88 #include "basic-block.h"
  89 #include "insn-config.h"
  90 #include "function.h"
  91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  92 #include "expr.h"
  93 #include "insn-attr.h"
  94 #include "recog.h"
  95 #include "real.h"
  96 #include "toplev.h"
  97 #include "target.h"
  98 #include "optabs.h"
  99 #include "insn-codes.h"
 100 #include "rtlhooks-def.h"
 101 /* Include output.h for dump_file.  */
 102 #include "output.h"
 103 #include "params.h"
 104 #include "timevar.h"
 105 #include "tree-pass.h"
 106 #include "df.h"
 107 #include "cgraph.h"
 108
 109 /* Number of attempts to combine instructions in this function.  */
 110
 111 static int combine_attempts;
 112
 113 /* Number of attempts that got as far as substitution in this function.  */
 114
 115 static int combine_merges;
 116
 117 /* Number of instructions combined with added SETs in this function.  */
 118
 119 static int combine_extras;
 120
 121 /* Number of instructions combined in this function.  */
 122
 123 static int combine_successes;
 124
 125 /* Totals over entire compilation.  */
 126
 127 static int total_attempts, total_merges, total_extras, total_successes;
 128
 129 /* combine_instructions may try to replace the right hand side of the
 130    second instruction with the value of an associated REG_EQUAL note
 131    before throwing it at try_combine.  That is problematic when there
 132    is a REG_DEAD note for a register used in the old right hand side
 133    and can cause distribute_notes to do wrong things.  This is the
 134    second instruction if it has been so modified, null otherwise.  */
 135
 136 static rtx i2mod;
 137
 138 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 139
 140 static rtx i2mod_old_rhs;
 141
 142 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 143
 144 static rtx i2mod_new_rhs;
 145 \f
 146 typedef struct reg_stat_struct {
 147   /* Record last point of death of (hard or pseudo) register n.  */
 148   rtx                           last_death;
 149
 150   /* Record last point of modification of (hard or pseudo) register n.  */
 151   rtx                           last_set;
 152
 153   /* The next group of fields allows the recording of the last value assigned
 154      to (hard or pseudo) register n.  We use this information to see if an
 155      operation being processed is redundant given a prior operation performed
 156      on the register.  For example, an `and' with a constant is redundant if
 157      all the zero bits are already known to be turned off.
 158
 159      We use an approach similar to that used by cse, but change it in the
 160      following ways:
 161
 162      (1) We do not want to reinitialize at each label.
 163      (2) It is useful, but not critical, to know the actual value assigned
 164          to a register.  Often just its form is helpful.
 165
 166      Therefore, we maintain the following fields:
 167
 168      last_set_value             the last value assigned
 169      last_set_label             records the value of label_tick when the
 170                                 register was assigned
 171      last_set_table_tick        records the value of label_tick when a
 172                                 value using the register is assigned
 173      last_set_invalid           set to nonzero when it is not valid
 174                                 to use the value of this register in some
 175                                 register's value
 176
 177      To understand the usage of these tables, it is important to understand
 178      the distinction between the value in last_set_value being valid and
 179      the register being validly contained in some other expression in the
 180      table.
 181
 182      (The next two parameters are out of date).
 183
 184      reg_stat[i].last_set_value is valid if it is nonzero, and either
 185      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 186
 187      Register I may validly appear in any expression returned for the value
 188      of another register if reg_n_sets[i] is 1.  It may also appear in the
 189      value for register J if reg_stat[j].last_set_invalid is zero, or
 190      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 191
 192      If an expression is found in the table containing a register which may
 193      not validly appear in an expression, the register is replaced by
 194      something that won't match, (clobber (const_int 0)).  */
 195
 196   /* Record last value assigned to (hard or pseudo) register n.  */
 197
 198   rtx                           last_set_value;
 199
 200   /* Record the value of label_tick when an expression involving register n
 201      is placed in last_set_value.  */
 202
 203   int                           last_set_table_tick;
 204
 205   /* Record the value of label_tick when the value for register n is placed in
 206      last_set_value.  */
 207
 208   int                           last_set_label;
 209
 210   /* These fields are maintained in parallel with last_set_value and are
 211      used to store the mode in which the register was last set, the bits
 212      that were known to be zero when it was last set, and the number of
 213      sign bits copies it was known to have when it was last set.  */
 214
 215   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 216   char                          last_set_sign_bit_copies;
 217   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 218
 219   /* Set nonzero if references to register n in expressions should not be
 220      used.  last_set_invalid is set nonzero when this register is being
 221      assigned to and last_set_table_tick == label_tick.  */
 222
 223   char                          last_set_invalid;
 224
 225   /* Some registers that are set more than once and used in more than one
 226      basic block are nevertheless always set in similar ways.  For example,
 227      a QImode register may be loaded from memory in two places on a machine
 228      where byte loads zero extend.
 229
 230      We record in the following fields if a register has some leading bits
 231      that are always equal to the sign bit, and what we know about the
 232      nonzero bits of a register, specifically which bits are known to be
 233      zero.
 234
 235      If an entry is zero, it means that we don't know anything special.  */
 236
 237   unsigned char                 sign_bit_copies;
 238
 239   unsigned HOST_WIDE_INT        nonzero_bits;
 240
 241   /* Record the value of the label_tick when the last truncation
 242      happened.  The field truncated_to_mode is only valid if
 243      truncation_label == label_tick.  */
 244
 245   int                           truncation_label;
 246
 247   /* Record the last truncation seen for this register.  If truncation
 248      is not a nop to this mode we might be able to save an explicit
 249      truncation if we know that value already contains a truncated
 250      value.  */
 251
 252   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 253 } reg_stat_type;
 254
 255 DEF_VEC_O(reg_stat_type);
 256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
 257
 258 static VEC(reg_stat_type,heap) *reg_stat;
 259
 260 /* Record the luid of the last insn that invalidated memory
 261    (anything that writes memory, and subroutine calls, but not pushes).  */
 262
 263 static int mem_last_set;
 264
 265 /* Record the luid of the last CALL_INSN
 266    so we can tell whether a potential combination crosses any calls.  */
 267
 268 static int last_call_luid;
 269
 270 /* When `subst' is called, this is the insn that is being modified
 271    (by combining in a previous insn).  The PATTERN of this insn
 272    is still the old pattern partially modified and it should not be
 273    looked at, but this may be used to examine the successors of the insn
 274    to judge whether a simplification is valid.  */
 275
 276 static rtx subst_insn;
 277
 278 /* This is the lowest LUID that `subst' is currently dealing with.
 279    get_last_value will not return a value if the register was set at or
 280    after this LUID.  If not for this mechanism, we could get confused if
 281    I2 or I1 in try_combine were an insn that used the old value of a register
 282    to obtain a new value.  In that case, we might erroneously get the
 283    new value of the register when we wanted the old one.  */
 284
 285 static int subst_low_luid;
 286
 287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 288    must consider all these registers to be always live.  */
 289
 290 static HARD_REG_SET newpat_used_regs;
 291
 292 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 293    insn is the earlier than I2 or I3, combine should rescan starting at
 294    that location.  */
 295
 296 static rtx added_links_insn;
 297
 298 /* Basic block in which we are performing combines.  */
 299 static basic_block this_basic_block;
 300 static bool optimize_this_for_speed_p;
 301
 302 \f
 303 /* Length of the currently allocated uid_insn_cost array.  */
 304
 305 static int max_uid_known;
 306
 307 /* The following array records the insn_rtx_cost for every insn
 308    in the instruction stream.  */
 309
 310 static int *uid_insn_cost;
 311
 312 /* The following array records the LOG_LINKS for every insn in the
 313    instruction stream as an INSN_LIST rtx.  */
 314
 315 static rtx *uid_log_links;
 316
 317 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 318 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 319
 320 /* Incremented for each basic block.  */
 321
 322 static int label_tick;
 323
 324 /* Reset to label_tick for each label.  */
 325
 326 static int label_tick_ebb_start;
 327
 328 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 329    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 330
 331 static enum machine_mode nonzero_bits_mode;
 332
 333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 334    be safely used.  It is zero while computing them and after combine has
 335    completed.  This former test prevents propagating values based on
 336    previously set values, which can be incorrect if a variable is modified
 337    in a loop.  */
 338
 339 static int nonzero_sign_valid;
 340
 341 \f
 342 /* Record one modification to rtl structure
 343    to be undone by storing old_contents into *where.  */
 344
 345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
 346
 347 struct undo
 348 {
 349   struct undo *next;
 350   enum undo_kind kind;
 351   union { rtx r; int i; enum machine_mode m; } old_contents;
 352   union { rtx *r; int *i; } where;
 353 };
 354
 355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 356    num_undo says how many are currently recorded.
 357
 358    other_insn is nonzero if we have modified some other insn in the process
 359    of working on subst_insn.  It must be verified too.  */
 360
 361 struct undobuf
 362 {
 363   struct undo *undos;
 364   struct undo *frees;
 365   rtx other_insn;
 366 };
 367
 368 static struct undobuf undobuf;
 369
 370 /* Number of times the pseudo being substituted for
 371    was found and replaced.  */
 372
 373 static int n_occurrences;
 374
 375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 376                                          enum machine_mode,
 377                                          unsigned HOST_WIDE_INT,
 378                                          unsigned HOST_WIDE_INT *);
 379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 380                                                 enum machine_mode,
 381                                                 unsigned int, unsigned int *);
 382 static void do_SUBST (rtx *, rtx);
 383 static void do_SUBST_INT (int *, int);
 384 static void init_reg_last (void);
 385 static void setup_incoming_promotions (rtx);
 386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 387 static int cant_combine_insn_p (rtx);
 388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 390 static int contains_muldiv (rtx);
 391 static rtx try_combine (rtx, rtx, rtx, int *);
 392 static void undo_all (void);
 393 static void undo_commit (void);
 394 static rtx *find_split_point (rtx *, rtx);
 395 static rtx subst (rtx, rtx, rtx, int, int);
 396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 397 static rtx simplify_if_then_else (rtx);
 398 static rtx simplify_set (rtx);
 399 static rtx simplify_logical (rtx);
 400 static rtx expand_compound_operation (rtx);
 401 static const_rtx expand_field_assignment (const_rtx);
 402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 403                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 404 static rtx extract_left_shift (rtx, int);
 405 static rtx make_compound_operation (rtx, enum rtx_code);
 406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 407                               unsigned HOST_WIDE_INT *);
 408 static rtx canon_reg_for_combine (rtx, rtx);
 409 static rtx force_to_mode (rtx, enum machine_mode,
 410                           unsigned HOST_WIDE_INT, int);
 411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 414 static rtx make_field_assignment (rtx);
 415 static rtx apply_distributive_law (rtx);
 416 static rtx distribute_and_simplify_rtx (rtx, int);
 417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 418                                      unsigned HOST_WIDE_INT);
 419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 420                                    unsigned HOST_WIDE_INT);
 421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 422                             HOST_WIDE_INT, enum machine_mode, int *);
 423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 425                                  int);
 426 static int recog_for_combine (rtx *, rtx, rtx *);
 427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 429 static void update_table_tick (rtx);
 430 static void record_value_for_reg (rtx, rtx, rtx);
 431 static void check_promoted_subreg (rtx, rtx);
 432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 433 static void record_dead_and_set_regs (rtx);
 434 static int get_last_value_validate (rtx *, rtx, int, int);
 435 static rtx get_last_value (const_rtx);
 436 static int use_crosses_set_p (const_rtx, int);
 437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 438 static int reg_dead_at_p (rtx, rtx);
 439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 440 static int reg_bitfield_target_p (rtx, rtx);
 441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 442 static void distribute_links (rtx);
 443 static void mark_used_regs_combine (rtx);
 444 static void record_promoted_value (rtx, rtx);
 445 static int unmentioned_reg_p_1 (rtx *, void *);
 446 static bool unmentioned_reg_p (rtx, rtx);
 447 static int record_truncated_value (rtx *, void *);
 448 static void record_truncated_values (rtx *, void *);
 449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 451 \f
 452
 453 /* It is not safe to use ordinary gen_lowpart in combine.
 454    See comments in gen_lowpart_for_combine.  */
 455 #undef RTL_HOOKS_GEN_LOWPART
 456 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 457
 458 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 461
 462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 463 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 464
 465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 467
 468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 470
 471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 472
 473 \f
 474 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 475    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 476    This is a wrapper around split_insns which ensures that the
 477    reg_stat vector is made larger if the splitter creates a new
 478    register.  */
 479
 480 static rtx
 481 combine_split_insns (rtx pattern, rtx insn)
 482 {
 483   rtx ret;
 484   unsigned int nregs;
 485
 486   ret = split_insns (pattern, insn);
 487   nregs = max_reg_num ();
 488   if (nregs > VEC_length (reg_stat_type, reg_stat))
 489     VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
 490   return ret;
 491 }
 492
 493 /* This is used by find_single_use to locate an rtx in LOC that
 494    contains exactly one use of DEST, which is typically either a REG
 495    or CC0.  It returns a pointer to the innermost rtx expression
 496    containing DEST.  Appearances of DEST that are being used to
 497    totally replace it are not counted.  */
 498
 499 static rtx *
 500 find_single_use_1 (rtx dest, rtx *loc)
 501 {
 502   rtx x = *loc;
 503   enum rtx_code code = GET_CODE (x);
 504   rtx *result = NULL;
 505   rtx *this_result;
 506   int i;
 507   const char *fmt;
 508
 509   switch (code)
 510     {
 511     case CONST_INT:
 512     case CONST:
 513     case LABEL_REF:
 514     case SYMBOL_REF:
 515     case CONST_DOUBLE:
 516     case CONST_VECTOR:
 517     case CLOBBER:
 518       return 0;
 519
 520     case SET:
 521       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 522          of a REG that occupies all of the REG, the insn uses DEST if
 523          it is mentioned in the destination or the source.  Otherwise, we
 524          need just check the source.  */
 525       if (GET_CODE (SET_DEST (x)) != CC0
 526           && GET_CODE (SET_DEST (x)) != PC
 527           && !REG_P (SET_DEST (x))
 528           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 529                 && REG_P (SUBREG_REG (SET_DEST (x)))
 530                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 531                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 532                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 533                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 534         break;
 535
 536       return find_single_use_1 (dest, &SET_SRC (x));
 537
 538     case MEM:
 539     case SUBREG:
 540       return find_single_use_1 (dest, &XEXP (x, 0));
 541
 542     default:
 543       break;
 544     }
 545
 546   /* If it wasn't one of the common cases above, check each expression and
 547      vector of this code.  Look for a unique usage of DEST.  */
 548
 549   fmt = GET_RTX_FORMAT (code);
 550   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 551     {
 552       if (fmt[i] == 'e')
 553         {
 554           if (dest == XEXP (x, i)
 555               || (REG_P (dest) && REG_P (XEXP (x, i))
 556                   && REGNO (dest) == REGNO (XEXP (x, i))))
 557             this_result = loc;
 558           else
 559             this_result = find_single_use_1 (dest, &XEXP (x, i));
 560
 561           if (result == NULL)
 562             result = this_result;
 563           else if (this_result)
 564             /* Duplicate usage.  */
 565             return NULL;
 566         }
 567       else if (fmt[i] == 'E')
 568         {
 569           int j;
 570
 571           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 572             {
 573               if (XVECEXP (x, i, j) == dest
 574                   || (REG_P (dest)
 575                       && REG_P (XVECEXP (x, i, j))
 576                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 577                 this_result = loc;
 578               else
 579                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 580
 581               if (result == NULL)
 582                 result = this_result;
 583               else if (this_result)
 584                 return NULL;
 585             }
 586         }
 587     }
 588
 589   return result;
 590 }
 591
 592
 593 /* See if DEST, produced in INSN, is used only a single time in the
 594    sequel.  If so, return a pointer to the innermost rtx expression in which
 595    it is used.
 596
 597    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 598
 599    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 600    care about REG_DEAD notes or LOG_LINKS.
 601
 602    Otherwise, we find the single use by finding an insn that has a
 603    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 604    only referenced once in that insn, we know that it must be the first
 605    and last insn referencing DEST.  */
 606
 607 static rtx *
 608 find_single_use (rtx dest, rtx insn, rtx *ploc)
 609 {
 610   basic_block bb;
 611   rtx next;
 612   rtx *result;
 613   rtx link;
 614
 615 #ifdef HAVE_cc0
 616   if (dest == cc0_rtx)
 617     {
 618       next = NEXT_INSN (insn);
 619       if (next == 0
 620           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 621         return 0;
 622
 623       result = find_single_use_1 (dest, &PATTERN (next));
 624       if (result && ploc)
 625         *ploc = next;
 626       return result;
 627     }
 628 #endif
 629
 630   if (!REG_P (dest))
 631     return 0;
 632
 633   bb = BLOCK_FOR_INSN (insn);
 634   for (next = NEXT_INSN (insn);
 635        next && BLOCK_FOR_INSN (next) == bb;
 636        next = NEXT_INSN (next))
 637     if (INSN_P (next) && dead_or_set_p (next, dest))
 638       {
 639         for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
 640           if (XEXP (link, 0) == insn)
 641             break;
 642
 643         if (link)
 644           {
 645             result = find_single_use_1 (dest, &PATTERN (next));
 646             if (ploc)
 647               *ploc = next;
 648             return result;
 649           }
 650       }
 651
 652   return 0;
 653 }
 654 \f
 655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 656    insn.  The substitution can be undone by undo_all.  If INTO is already
 657    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 658    also call SUBST, we have to compute it before we put anything into
 659    the undo table.  */
 660
 661 static void
 662 do_SUBST (rtx *into, rtx newval)
 663 {
 664   struct undo *buf;
 665   rtx oldval = *into;
 666
 667   if (oldval == newval)
 668     return;
 669
 670   /* We'd like to catch as many invalid transformations here as
 671      possible.  Unfortunately, there are way too many mode changes
 672      that are perfectly valid, so we'd waste too much effort for
 673      little gain doing the checks here.  Focus on catching invalid
 674      transformations involving integer constants.  */
 675   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 676       && CONST_INT_P (newval))
 677     {
 678       /* Sanity check that we're replacing oldval with a CONST_INT
 679          that is a valid sign-extension for the original mode.  */
 680       gcc_assert (INTVAL (newval)
 681                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 682
 683       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 684          CONST_INT is not valid, because after the replacement, the
 685          original mode would be gone.  Unfortunately, we can't tell
 686          when do_SUBST is called to replace the operand thereof, so we
 687          perform this test on oldval instead, checking whether an
 688          invalid replacement took place before we got here.  */
 689       gcc_assert (!(GET_CODE (oldval) == SUBREG
 690                     && CONST_INT_P (SUBREG_REG (oldval))));
 691       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 692                     && CONST_INT_P (XEXP (oldval, 0))));
 693     }
 694
 695   if (undobuf.frees)
 696     buf = undobuf.frees, undobuf.frees = buf->next;
 697   else
 698     buf = XNEW (struct undo);
 699
 700   buf->kind = UNDO_RTX;
 701   buf->where.r = into;
 702   buf->old_contents.r = oldval;
 703   *into = newval;
 704
 705   buf->next = undobuf.undos, undobuf.undos = buf;
 706 }
 707
 708 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 709
 710 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 711    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 712    not safe.  */
 713
 714 static void
 715 do_SUBST_INT (int *into, int newval)
 716 {
 717   struct undo *buf;
 718   int oldval = *into;
 719
 720   if (oldval == newval)
 721     return;
 722
 723   if (undobuf.frees)
 724     buf = undobuf.frees, undobuf.frees = buf->next;
 725   else
 726     buf = XNEW (struct undo);
 727
 728   buf->kind = UNDO_INT;
 729   buf->where.i = into;
 730   buf->old_contents.i = oldval;
 731   *into = newval;
 732
 733   buf->next = undobuf.undos, undobuf.undos = buf;
 734 }
 735
 736 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 737
 738 /* Similar to SUBST, but just substitute the mode.  This is used when
 739    changing the mode of a pseudo-register, so that any other
 740    references to the entry in the regno_reg_rtx array will change as
 741    well.  */
 742
 743 static void
 744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 745 {
 746   struct undo *buf;
 747   enum machine_mode oldval = GET_MODE (*into);
 748
 749   if (oldval == newval)
 750     return;
 751
 752   if (undobuf.frees)
 753     buf = undobuf.frees, undobuf.frees = buf->next;
 754   else
 755     buf = XNEW (struct undo);
 756
 757   buf->kind = UNDO_MODE;
 758   buf->where.r = into;
 759   buf->old_contents.m = oldval;
 760   adjust_reg_mode (*into, newval);
 761
 762   buf->next = undobuf.undos, undobuf.undos = buf;
 763 }
 764
 765 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 766 \f
 767 /* Subroutine of try_combine.  Determine whether the combine replacement
 768    patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
 769    insn_rtx_cost that the original instruction sequence I1, I2, I3 and
 770    undobuf.other_insn.  Note that I1 and/or NEWI2PAT may be NULL_RTX.
 771    NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX.  This
 772    function returns false, if the costs of all instructions can be
 773    estimated, and the replacements are more expensive than the original
 774    sequence.  */
 775
 776 static bool
 777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
 778                        rtx newotherpat)
 779 {
 780   int i1_cost, i2_cost, i3_cost;
 781   int new_i2_cost, new_i3_cost;
 782   int old_cost, new_cost;
 783
 784   /* Lookup the original insn_rtx_costs.  */
 785   i2_cost = INSN_COST (i2);
 786   i3_cost = INSN_COST (i3);
 787
 788   if (i1)
 789     {
 790       i1_cost = INSN_COST (i1);
 791       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 792                  ? i1_cost + i2_cost + i3_cost : 0;
 793     }
 794   else
 795     {
 796       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 797       i1_cost = 0;
 798     }
 799
 800   /* Calculate the replacement insn_rtx_costs.  */
 801   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 802   if (newi2pat)
 803     {
 804       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 805       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 806                  ? new_i2_cost + new_i3_cost : 0;
 807     }
 808   else
 809     {
 810       new_cost = new_i3_cost;
 811       new_i2_cost = 0;
 812     }
 813
 814   if (undobuf.other_insn)
 815     {
 816       int old_other_cost, new_other_cost;
 817
 818       old_other_cost = INSN_COST (undobuf.other_insn);
 819       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 820       if (old_other_cost > 0 && new_other_cost > 0)
 821         {
 822           old_cost += old_other_cost;
 823           new_cost += new_other_cost;
 824         }
 825       else
 826         old_cost = 0;
 827     }
 828
 829   /* Disallow this recombination if both new_cost and old_cost are
 830      greater than zero, and new_cost is greater than old cost.  */
 831   if (old_cost > 0
 832       && new_cost > old_cost)
 833     {
 834       if (dump_file)
 835         {
 836           if (i1)
 837             {
 838               fprintf (dump_file,
 839                        "rejecting combination of insns %d, %d and %d\n",
 840                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 841               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 842                        i1_cost, i2_cost, i3_cost, old_cost);
 843             }
 844           else
 845             {
 846               fprintf (dump_file,
 847                        "rejecting combination of insns %d and %d\n",
 848                        INSN_UID (i2), INSN_UID (i3));
 849               fprintf (dump_file, "original costs %d + %d = %d\n",
 850                        i2_cost, i3_cost, old_cost);
 851             }
 852
 853           if (newi2pat)
 854             {
 855               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 856                        new_i2_cost, new_i3_cost, new_cost);
 857             }
 858           else
 859             fprintf (dump_file, "replacement cost %d\n", new_cost);
 860         }
 861
 862       return false;
 863     }
 864
 865   /* Update the uid_insn_cost array with the replacement costs.  */
 866   INSN_COST (i2) = new_i2_cost;
 867   INSN_COST (i3) = new_i3_cost;
 868   if (i1)
 869     INSN_COST (i1) = 0;
 870
 871   return true;
 872 }
 873
 874
 875 /* Delete any insns that copy a register to itself.  */
 876
 877 static void
 878 delete_noop_moves (void)
 879 {
 880   rtx insn, next;
 881   basic_block bb;
 882
 883   FOR_EACH_BB (bb)
 884     {
 885       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 886         {
 887           next = NEXT_INSN (insn);
 888           if (INSN_P (insn) && noop_move_p (insn))
 889             {
 890               if (dump_file)
 891                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 892
 893               delete_insn_and_edges (insn);
 894             }
 895         }
 896     }
 897 }
 898
 899 \f
 900 /* Fill in log links field for all insns.  */
 901
 902 static void
 903 create_log_links (void)
 904 {
 905   basic_block bb;
 906   rtx *next_use, insn;
 907   df_ref *def_vec, *use_vec;
 908
 909   next_use = XCNEWVEC (rtx, max_reg_num ());
 910
 911   /* Pass through each block from the end, recording the uses of each
 912      register and establishing log links when def is encountered.
 913      Note that we do not clear next_use array in order to save time,
 914      so we have to test whether the use is in the same basic block as def.
 915
 916      There are a few cases below when we do not consider the definition or
 917      usage -- these are taken from original flow.c did. Don't ask me why it is
 918      done this way; I don't know and if it works, I don't want to know.  */
 919
 920   FOR_EACH_BB (bb)
 921     {
 922       FOR_BB_INSNS_REVERSE (bb, insn)
 923         {
 924           if (!NONDEBUG_INSN_P (insn))
 925             continue;
 926
 927           /* Log links are created only once.  */
 928           gcc_assert (!LOG_LINKS (insn));
 929
 930           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
 931             {
 932               df_ref def = *def_vec;
 933               int regno = DF_REF_REGNO (def);
 934               rtx use_insn;
 935
 936               if (!next_use[regno])
 937                 continue;
 938
 939               /* Do not consider if it is pre/post modification in MEM.  */
 940               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
 941                 continue;
 942
 943               /* Do not make the log link for frame pointer.  */
 944               if ((regno == FRAME_POINTER_REGNUM
 945                    && (! reload_completed || frame_pointer_needed))
 946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
 947                   || (regno == HARD_FRAME_POINTER_REGNUM
 948                       && (! reload_completed || frame_pointer_needed))
 949 #endif
 950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
 951                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
 952 #endif
 953                   )
 954                 continue;
 955
 956               use_insn = next_use[regno];
 957               if (BLOCK_FOR_INSN (use_insn) == bb)
 958                 {
 959                   /* flow.c claimed:
 960
 961                      We don't build a LOG_LINK for hard registers contained
 962                      in ASM_OPERANDs.  If these registers get replaced,
 963                      we might wind up changing the semantics of the insn,
 964                      even if reload can make what appear to be valid
 965                      assignments later.  */
 966                   if (regno >= FIRST_PSEUDO_REGISTER
 967                       || asm_noperands (PATTERN (use_insn)) < 0)
 968                     {
 969                       /* Don't add duplicate links between instructions.  */
 970                       rtx links;
 971                       for (links = LOG_LINKS (use_insn); links;
 972                            links = XEXP (links, 1))
 973                         if (insn == XEXP (links, 0))
 974                           break;
 975
 976                       if (!links)
 977                         LOG_LINKS (use_insn) =
 978                           alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
 979                     }
 980                 }
 981               next_use[regno] = NULL_RTX;
 982             }
 983
 984           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
 985             {
 986               df_ref use = *use_vec;
 987               int regno = DF_REF_REGNO (use);
 988
 989               /* Do not consider the usage of the stack pointer
 990                  by function call.  */
 991               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
 992                 continue;
 993
 994               next_use[regno] = insn;
 995             }
 996         }
 997     }
 998
 999   free (next_use);
1000 }
1001
1002 /* Clear LOG_LINKS fields of insns.  */
1003
1004 static void
1005 clear_log_links (void)
1006 {
1007   rtx insn;
1008
1009   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1010     if (INSN_P (insn))
1011       free_INSN_LIST_list (&LOG_LINKS (insn));
1012 }
1013
1014
1015
1016 \f
1017 /* Main entry point for combiner.  F is the first insn of the function.
1018    NREGS is the first unused pseudo-reg number.
1019
1020    Return nonzero if the combiner has turned an indirect jump
1021    instruction into a direct jump.  */
1022 static int
1023 combine_instructions (rtx f, unsigned int nregs)
1024 {
1025   rtx insn, next;
1026 #ifdef HAVE_cc0
1027   rtx prev;
1028 #endif
1029   rtx links, nextlinks;
1030   rtx first;
1031
1032   int new_direct_jump_p = 0;
1033
1034   for (first = f; first && !INSN_P (first); )
1035     first = NEXT_INSN (first);
1036   if (!first)
1037     return 0;
1038
1039   combine_attempts = 0;
1040   combine_merges = 0;
1041   combine_extras = 0;
1042   combine_successes = 0;
1043
1044   rtl_hooks = combine_rtl_hooks;
1045
1046   VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1047
1048   init_recog_no_volatile ();
1049
1050   /* Allocate array for insn info.  */
1051   max_uid_known = get_max_uid ();
1052   uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1053   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1054
1055   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1056
1057   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1058      problems when, for example, we have j <<= 1 in a loop.  */
1059
1060   nonzero_sign_valid = 0;
1061
1062   /* Scan all SETs and see if we can deduce anything about what
1063      bits are known to be zero for some registers and how many copies
1064      of the sign bit are known to exist for those registers.
1065
1066      Also set any known values so that we can use it while searching
1067      for what bits are known to be set.  */
1068
1069   setup_incoming_promotions (first);
1070
1071   create_log_links ();
1072   label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1073   FOR_EACH_BB (this_basic_block)
1074     {
1075       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1076       last_call_luid = 0;
1077       mem_last_set = -1;
1078       label_tick = this_basic_block->index;
1079       if (!single_pred_p (this_basic_block)
1080           || single_pred (this_basic_block)->index != label_tick - 1)
1081         label_tick_ebb_start = label_tick;
1082       FOR_BB_INSNS (this_basic_block, insn)
1083         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1084           {
1085             subst_low_luid = DF_INSN_LUID (insn);
1086             subst_insn = insn;
1087
1088             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1089                          insn);
1090             record_dead_and_set_regs (insn);
1091
1092 #ifdef AUTO_INC_DEC
1093             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1094               if (REG_NOTE_KIND (links) == REG_INC)
1095                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1096                                                   insn);
1097 #endif
1098
1099             /* Record the current insn_rtx_cost of this instruction.  */
1100             if (NONJUMP_INSN_P (insn))
1101               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1102                                                 optimize_this_for_speed_p);
1103             if (dump_file)
1104               fprintf(dump_file, "insn_cost %d: %d\n",
1105                     INSN_UID (insn), INSN_COST (insn));
1106           }
1107     }
1108
1109   nonzero_sign_valid = 1;
1110
1111   /* Now scan all the insns in forward order.  */
1112
1113   label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1114   init_reg_last ();
1115   setup_incoming_promotions (first);
1116
1117   FOR_EACH_BB (this_basic_block)
1118     {
1119       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1120       last_call_luid = 0;
1121       mem_last_set = -1;
1122       label_tick = this_basic_block->index;
1123       if (!single_pred_p (this_basic_block)
1124           || single_pred (this_basic_block)->index != label_tick - 1)
1125         label_tick_ebb_start = label_tick;
1126       rtl_profile_for_bb (this_basic_block);
1127       for (insn = BB_HEAD (this_basic_block);
1128            insn != NEXT_INSN (BB_END (this_basic_block));
1129            insn = next ? next : NEXT_INSN (insn))
1130         {
1131           next = 0;
1132           if (NONDEBUG_INSN_P (insn))
1133             {
1134               /* See if we know about function return values before this
1135                  insn based upon SUBREG flags.  */
1136               check_promoted_subreg (insn, PATTERN (insn));
1137
1138               /* See if we can find hardregs and subreg of pseudos in
1139                  narrower modes.  This could help turning TRUNCATEs
1140                  into SUBREGs.  */
1141               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1142
1143               /* Try this insn with each insn it links back to.  */
1144
1145               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1146                 if ((next = try_combine (insn, XEXP (links, 0),
1147                                          NULL_RTX, &new_direct_jump_p)) != 0)
1148                   goto retry;
1149
1150               /* Try each sequence of three linked insns ending with this one.  */
1151
1152               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1153                 {
1154                   rtx link = XEXP (links, 0);
1155
1156                   /* If the linked insn has been replaced by a note, then there
1157                      is no point in pursuing this chain any further.  */
1158                   if (NOTE_P (link))
1159                     continue;
1160
1161                   for (nextlinks = LOG_LINKS (link);
1162                        nextlinks;
1163                        nextlinks = XEXP (nextlinks, 1))
1164                     if ((next = try_combine (insn, link,
1165                                              XEXP (nextlinks, 0),
1166                                              &new_direct_jump_p)) != 0)
1167                       goto retry;
1168                 }
1169
1170 #ifdef HAVE_cc0
1171               /* Try to combine a jump insn that uses CC0
1172                  with a preceding insn that sets CC0, and maybe with its
1173                  logical predecessor as well.
1174                  This is how we make decrement-and-branch insns.
1175                  We need this special code because data flow connections
1176                  via CC0 do not get entered in LOG_LINKS.  */
1177
1178               if (JUMP_P (insn)
1179                   && (prev = prev_nonnote_insn (insn)) != 0
1180                   && NONJUMP_INSN_P (prev)
1181                   && sets_cc0_p (PATTERN (prev)))
1182                 {
1183                   if ((next = try_combine (insn, prev,
1184                                            NULL_RTX, &new_direct_jump_p)) != 0)
1185                     goto retry;
1186
1187                   for (nextlinks = LOG_LINKS (prev); nextlinks;
1188                        nextlinks = XEXP (nextlinks, 1))
1189                     if ((next = try_combine (insn, prev,
1190                                              XEXP (nextlinks, 0),
1191                                              &new_direct_jump_p)) != 0)
1192                       goto retry;
1193                 }
1194
1195               /* Do the same for an insn that explicitly references CC0.  */
1196               if (NONJUMP_INSN_P (insn)
1197                   && (prev = prev_nonnote_insn (insn)) != 0
1198                   && NONJUMP_INSN_P (prev)
1199                   && sets_cc0_p (PATTERN (prev))
1200                   && GET_CODE (PATTERN (insn)) == SET
1201                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1202                 {
1203                   if ((next = try_combine (insn, prev,
1204                                            NULL_RTX, &new_direct_jump_p)) != 0)
1205                     goto retry;
1206
1207                   for (nextlinks = LOG_LINKS (prev); nextlinks;
1208                        nextlinks = XEXP (nextlinks, 1))
1209                     if ((next = try_combine (insn, prev,
1210                                              XEXP (nextlinks, 0),
1211                                              &new_direct_jump_p)) != 0)
1212                       goto retry;
1213                 }
1214
1215               /* Finally, see if any of the insns that this insn links to
1216                  explicitly references CC0.  If so, try this insn, that insn,
1217                  and its predecessor if it sets CC0.  */
1218               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1219                 if (NONJUMP_INSN_P (XEXP (links, 0))
1220                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1221                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1222                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1223                     && NONJUMP_INSN_P (prev)
1224                     && sets_cc0_p (PATTERN (prev))
1225                     && (next = try_combine (insn, XEXP (links, 0),
1226                                             prev, &new_direct_jump_p)) != 0)
1227                   goto retry;
1228 #endif
1229
1230               /* Try combining an insn with two different insns whose results it
1231                  uses.  */
1232               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1233                 for (nextlinks = XEXP (links, 1); nextlinks;
1234                      nextlinks = XEXP (nextlinks, 1))
1235                   if ((next = try_combine (insn, XEXP (links, 0),
1236                                            XEXP (nextlinks, 0),
1237                                            &new_direct_jump_p)) != 0)
1238                     goto retry;
1239
1240               /* Try this insn with each REG_EQUAL note it links back to.  */
1241               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1242                 {
1243                   rtx set, note;
1244                   rtx temp = XEXP (links, 0);
1245                   if ((set = single_set (temp)) != 0
1246                       && (note = find_reg_equal_equiv_note (temp)) != 0
1247                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1248                       /* Avoid using a register that may already been marked
1249                          dead by an earlier instruction.  */
1250                       && ! unmentioned_reg_p (note, SET_SRC (set))
1251                       && (GET_MODE (note) == VOIDmode
1252                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1253                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1254                     {
1255                       /* Temporarily replace the set's source with the
1256                          contents of the REG_EQUAL note.  The insn will
1257                          be deleted or recognized by try_combine.  */
1258                       rtx orig = SET_SRC (set);
1259                       SET_SRC (set) = note;
1260                       i2mod = temp;
1261                       i2mod_old_rhs = copy_rtx (orig);
1262                       i2mod_new_rhs = copy_rtx (note);
1263                       next = try_combine (insn, i2mod, NULL_RTX,
1264                                           &new_direct_jump_p);
1265                       i2mod = NULL_RTX;
1266                       if (next)
1267                         goto retry;
1268                       SET_SRC (set) = orig;
1269                     }
1270                 }
1271
1272               if (!NOTE_P (insn))
1273                 record_dead_and_set_regs (insn);
1274
1275             retry:
1276               ;
1277             }
1278         }
1279     }
1280
1281   default_rtl_profile ();
1282   clear_log_links ();
1283   clear_bb_flags ();
1284   new_direct_jump_p |= purge_all_dead_edges ();
1285   delete_noop_moves ();
1286
1287   /* Clean up.  */
1288   free (uid_log_links);
1289   free (uid_insn_cost);
1290   VEC_free (reg_stat_type, heap, reg_stat);
1291
1292   {
1293     struct undo *undo, *next;
1294     for (undo = undobuf.frees; undo; undo = next)
1295       {
1296         next = undo->next;
1297         free (undo);
1298       }
1299     undobuf.frees = 0;
1300   }
1301
1302   total_attempts += combine_attempts;
1303   total_merges += combine_merges;
1304   total_extras += combine_extras;
1305   total_successes += combine_successes;
1306
1307   nonzero_sign_valid = 0;
1308   rtl_hooks = general_rtl_hooks;
1309
1310   /* Make recognizer allow volatile MEMs again.  */
1311   init_recog ();
1312
1313   return new_direct_jump_p;
1314 }
1315
1316 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1317
1318 static void
1319 init_reg_last (void)
1320 {
1321   unsigned int i;
1322   reg_stat_type *p;
1323
1324   for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1325     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1326 }
1327 \f
1328 /* Set up any promoted values for incoming argument registers.  */
1329
1330 static void
1331 setup_incoming_promotions (rtx first)
1332 {
1333   tree arg;
1334   bool strictly_local = false;
1335
1336   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1337        arg = TREE_CHAIN (arg))
1338     {
1339       rtx reg = DECL_INCOMING_RTL (arg);
1340       int uns1, uns3;
1341       enum machine_mode mode1, mode2, mode3, mode4;
1342
1343       /* Only continue if the incoming argument is in a register.  */
1344       if (!REG_P (reg))
1345         continue;
1346
1347       /* Determine, if possible, whether all call sites of the current
1348          function lie within the current compilation unit.  (This does
1349          take into account the exporting of a function via taking its
1350          address, and so forth.)  */
1351       strictly_local = cgraph_local_info (current_function_decl)->local;
1352
1353       /* The mode and signedness of the argument before any promotions happen
1354          (equal to the mode of the pseudo holding it at that stage).  */
1355       mode1 = TYPE_MODE (TREE_TYPE (arg));
1356       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1357
1358       /* The mode and signedness of the argument after any source language and
1359          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1360       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1361       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1362
1363       /* The mode and signedness of the argument as it is actually passed,
1364          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1365       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1366                                      TREE_TYPE (cfun->decl), 0);
1367
1368       /* The mode of the register in which the argument is being passed.  */
1369       mode4 = GET_MODE (reg);
1370
1371       /* Eliminate sign extensions in the callee when possible.  Only
1372          do this when:
1373          (a) a mode promotion has occurred;
1374          (b) the mode of the register is the same as the mode of
1375              the argument as it is passed; and
1376          (c) the signedness does not change across any of the promotions; and
1377          (d) when no language-level promotions (which we cannot guarantee
1378              will have been done by an external caller) are necessary,
1379              unless we know that this function is only ever called from
1380              the current compilation unit -- all of whose call sites will
1381              do the mode1 --> mode2 promotion.  */
1382       if (mode1 != mode3
1383           && mode3 == mode4
1384           && uns1 == uns3
1385           && (mode1 == mode2 || strictly_local))
1386         {
1387           /* Record that the value was promoted from mode1 to mode3,
1388              so that any sign extension at the head of the current
1389              function may be eliminated.  */
1390           rtx x;
1391           x = gen_rtx_CLOBBER (mode1, const0_rtx);
1392           x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1393           record_value_for_reg (reg, first, x);
1394         }
1395     }
1396 }
1397
1398 /* Called via note_stores.  If X is a pseudo that is narrower than
1399    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1400
1401    If we are setting only a portion of X and we can't figure out what
1402    portion, assume all bits will be used since we don't know what will
1403    be happening.
1404
1405    Similarly, set how many bits of X are known to be copies of the sign bit
1406    at all locations in the function.  This is the smallest number implied
1407    by any set of X.  */
1408
1409 static void
1410 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1411 {
1412   rtx insn = (rtx) data;
1413   unsigned int num;
1414
1415   if (REG_P (x)
1416       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1417       /* If this register is undefined at the start of the file, we can't
1418          say what its contents were.  */
1419       && ! REGNO_REG_SET_P
1420            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1421       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1422     {
1423       reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1424
1425       if (set == 0 || GET_CODE (set) == CLOBBER)
1426         {
1427           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1428           rsp->sign_bit_copies = 1;
1429           return;
1430         }
1431
1432       /* If this register is being initialized using itself, and the
1433          register is uninitialized in this basic block, and there are
1434          no LOG_LINKS which set the register, then part of the
1435          register is uninitialized.  In that case we can't assume
1436          anything about the number of nonzero bits.
1437
1438          ??? We could do better if we checked this in
1439          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1440          could avoid making assumptions about the insn which initially
1441          sets the register, while still using the information in other
1442          insns.  We would have to be careful to check every insn
1443          involved in the combination.  */
1444
1445       if (insn
1446           && reg_referenced_p (x, PATTERN (insn))
1447           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1448                                REGNO (x)))
1449         {
1450           rtx link;
1451
1452           for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1453             {
1454               if (dead_or_set_p (XEXP (link, 0), x))
1455                 break;
1456             }
1457           if (!link)
1458             {
1459               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1460               rsp->sign_bit_copies = 1;
1461               return;
1462             }
1463         }
1464
1465       /* If this is a complex assignment, see if we can convert it into a
1466          simple assignment.  */
1467       set = expand_field_assignment (set);
1468
1469       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1470          set what we know about X.  */
1471
1472       if (SET_DEST (set) == x
1473           || (GET_CODE (SET_DEST (set)) == SUBREG
1474               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1475                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1476               && SUBREG_REG (SET_DEST (set)) == x))
1477         {
1478           rtx src = SET_SRC (set);
1479
1480 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1481           /* If X is narrower than a word and SRC is a non-negative
1482              constant that would appear negative in the mode of X,
1483              sign-extend it for use in reg_stat[].nonzero_bits because some
1484              machines (maybe most) will actually do the sign-extension
1485              and this is the conservative approach.
1486
1487              ??? For 2.5, try to tighten up the MD files in this regard
1488              instead of this kludge.  */
1489
1490           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1491               && CONST_INT_P (src)
1492               && INTVAL (src) > 0
1493               && 0 != (INTVAL (src)
1494                        & ((HOST_WIDE_INT) 1
1495                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1496             src = GEN_INT (INTVAL (src)
1497                            | ((HOST_WIDE_INT) (-1)
1498                               << GET_MODE_BITSIZE (GET_MODE (x))));
1499 #endif
1500
1501           /* Don't call nonzero_bits if it cannot change anything.  */
1502           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1503             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1504           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1505           if (rsp->sign_bit_copies == 0
1506               || rsp->sign_bit_copies > num)
1507             rsp->sign_bit_copies = num;
1508         }
1509       else
1510         {
1511           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1512           rsp->sign_bit_copies = 1;
1513         }
1514     }
1515 }
1516 \f
1517 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1518    insns that were previously combined into I3 or that will be combined
1519    into the merger of INSN and I3.
1520
1521    Return 0 if the combination is not allowed for any reason.
1522
1523    If the combination is allowed, *PDEST will be set to the single
1524    destination of INSN and *PSRC to the single source, and this function
1525    will return 1.  */
1526
1527 static int
1528 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1529                rtx *pdest, rtx *psrc)
1530 {
1531   int i;
1532   const_rtx set = 0;
1533   rtx src, dest;
1534   rtx p;
1535 #ifdef AUTO_INC_DEC
1536   rtx link;
1537 #endif
1538   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1539                               && next_active_insn (succ) == i3)
1540                       : next_active_insn (insn) == i3);
1541
1542   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1543      or a PARALLEL consisting of such a SET and CLOBBERs.
1544
1545      If INSN has CLOBBER parallel parts, ignore them for our processing.
1546      By definition, these happen during the execution of the insn.  When it
1547      is merged with another insn, all bets are off.  If they are, in fact,
1548      needed and aren't also supplied in I3, they may be added by
1549      recog_for_combine.  Otherwise, it won't match.
1550
1551      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1552      note.
1553
1554      Get the source and destination of INSN.  If more than one, can't
1555      combine.  */
1556
1557   if (GET_CODE (PATTERN (insn)) == SET)
1558     set = PATTERN (insn);
1559   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1560            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1561     {
1562       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1563         {
1564           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1565           rtx note;
1566
1567           switch (GET_CODE (elt))
1568             {
1569             /* This is important to combine floating point insns
1570                for the SH4 port.  */
1571             case USE:
1572               /* Combining an isolated USE doesn't make sense.
1573                  We depend here on combinable_i3pat to reject them.  */
1574               /* The code below this loop only verifies that the inputs of
1575                  the SET in INSN do not change.  We call reg_set_between_p
1576                  to verify that the REG in the USE does not change between
1577                  I3 and INSN.
1578                  If the USE in INSN was for a pseudo register, the matching
1579                  insn pattern will likely match any register; combining this
1580                  with any other USE would only be safe if we knew that the
1581                  used registers have identical values, or if there was
1582                  something to tell them apart, e.g. different modes.  For
1583                  now, we forgo such complicated tests and simply disallow
1584                  combining of USES of pseudo registers with any other USE.  */
1585               if (REG_P (XEXP (elt, 0))
1586                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1587                 {
1588                   rtx i3pat = PATTERN (i3);
1589                   int i = XVECLEN (i3pat, 0) - 1;
1590                   unsigned int regno = REGNO (XEXP (elt, 0));
1591
1592                   do
1593                     {
1594                       rtx i3elt = XVECEXP (i3pat, 0, i);
1595
1596                       if (GET_CODE (i3elt) == USE
1597                           && REG_P (XEXP (i3elt, 0))
1598                           && (REGNO (XEXP (i3elt, 0)) == regno
1599                               ? reg_set_between_p (XEXP (elt, 0),
1600                                                    PREV_INSN (insn), i3)
1601                               : regno >= FIRST_PSEUDO_REGISTER))
1602                         return 0;
1603                     }
1604                   while (--i >= 0);
1605                 }
1606               break;
1607
1608               /* We can ignore CLOBBERs.  */
1609             case CLOBBER:
1610               break;
1611
1612             case SET:
1613               /* Ignore SETs whose result isn't used but not those that
1614                  have side-effects.  */
1615               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1616                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1617                       || INTVAL (XEXP (note, 0)) <= 0)
1618                   && ! side_effects_p (elt))
1619                 break;
1620
1621               /* If we have already found a SET, this is a second one and
1622                  so we cannot combine with this insn.  */
1623               if (set)
1624                 return 0;
1625
1626               set = elt;
1627               break;
1628
1629             default:
1630               /* Anything else means we can't combine.  */
1631               return 0;
1632             }
1633         }
1634
1635       if (set == 0
1636           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1637              so don't do anything with it.  */
1638           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1639         return 0;
1640     }
1641   else
1642     return 0;
1643
1644   if (set == 0)
1645     return 0;
1646
1647   set = expand_field_assignment (set);
1648   src = SET_SRC (set), dest = SET_DEST (set);
1649
1650   /* Don't eliminate a store in the stack pointer.  */
1651   if (dest == stack_pointer_rtx
1652       /* Don't combine with an insn that sets a register to itself if it has
1653          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1654       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1655       /* Can't merge an ASM_OPERANDS.  */
1656       || GET_CODE (src) == ASM_OPERANDS
1657       /* Can't merge a function call.  */
1658       || GET_CODE (src) == CALL
1659       /* Don't eliminate a function call argument.  */
1660       || (CALL_P (i3)
1661           && (find_reg_fusage (i3, USE, dest)
1662               || (REG_P (dest)
1663                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1664                   && global_regs[REGNO (dest)])))
1665       /* Don't substitute into an incremented register.  */
1666       || FIND_REG_INC_NOTE (i3, dest)
1667       || (succ && FIND_REG_INC_NOTE (succ, dest))
1668       /* Don't substitute into a non-local goto, this confuses CFG.  */
1669       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1670       /* Make sure that DEST is not used after SUCC but before I3.  */
1671       || (succ && ! all_adjacent
1672           && reg_used_between_p (dest, succ, i3))
1673       /* Make sure that the value that is to be substituted for the register
1674          does not use any registers whose values alter in between.  However,
1675          If the insns are adjacent, a use can't cross a set even though we
1676          think it might (this can happen for a sequence of insns each setting
1677          the same destination; last_set of that register might point to
1678          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1679          equivalent to the memory so the substitution is valid even if there
1680          are intervening stores.  Also, don't move a volatile asm or
1681          UNSPEC_VOLATILE across any other insns.  */
1682       || (! all_adjacent
1683           && (((!MEM_P (src)
1684                 || ! find_reg_note (insn, REG_EQUIV, src))
1685                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1686               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1687               || GET_CODE (src) == UNSPEC_VOLATILE))
1688       /* Don't combine across a CALL_INSN, because that would possibly
1689          change whether the life span of some REGs crosses calls or not,
1690          and it is a pain to update that information.
1691          Exception: if source is a constant, moving it later can't hurt.
1692          Accept that as a special case.  */
1693       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1694     return 0;
1695
1696   /* DEST must either be a REG or CC0.  */
1697   if (REG_P (dest))
1698     {
1699       /* If register alignment is being enforced for multi-word items in all
1700          cases except for parameters, it is possible to have a register copy
1701          insn referencing a hard register that is not allowed to contain the
1702          mode being copied and which would not be valid as an operand of most
1703          insns.  Eliminate this problem by not combining with such an insn.
1704
1705          Also, on some machines we don't want to extend the life of a hard
1706          register.  */
1707
1708       if (REG_P (src)
1709           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1710                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1711               /* Don't extend the life of a hard register unless it is
1712                  user variable (if we have few registers) or it can't
1713                  fit into the desired register (meaning something special
1714                  is going on).
1715                  Also avoid substituting a return register into I3, because
1716                  reload can't handle a conflict with constraints of other
1717                  inputs.  */
1718               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1719                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1720         return 0;
1721     }
1722   else if (GET_CODE (dest) != CC0)
1723     return 0;
1724
1725
1726   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1727     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1728       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1729         {
1730           /* Don't substitute for a register intended as a clobberable
1731              operand.  */
1732           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1733           if (rtx_equal_p (reg, dest))
1734             return 0;
1735
1736           /* If the clobber represents an earlyclobber operand, we must not
1737              substitute an expression containing the clobbered register.
1738              As we do not analyze the constraint strings here, we have to
1739              make the conservative assumption.  However, if the register is
1740              a fixed hard reg, the clobber cannot represent any operand;
1741              we leave it up to the machine description to either accept or
1742              reject use-and-clobber patterns.  */
1743           if (!REG_P (reg)
1744               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1745               || !fixed_regs[REGNO (reg)])
1746             if (reg_overlap_mentioned_p (reg, src))
1747               return 0;
1748         }
1749
1750   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1751      or not), reject, unless nothing volatile comes between it and I3 */
1752
1753   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1754     {
1755       /* Make sure succ doesn't contain a volatile reference.  */
1756       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1757         return 0;
1758
1759       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1760         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1761           return 0;
1762     }
1763
1764   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1765      to be an explicit register variable, and was chosen for a reason.  */
1766
1767   if (GET_CODE (src) == ASM_OPERANDS
1768       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1769     return 0;
1770
1771   /* If there are any volatile insns between INSN and I3, reject, because
1772      they might affect machine state.  */
1773
1774   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1775     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1776       return 0;
1777
1778   /* If INSN contains an autoincrement or autodecrement, make sure that
1779      register is not used between there and I3, and not already used in
1780      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1781      Also insist that I3 not be a jump; if it were one
1782      and the incremented register were spilled, we would lose.  */
1783
1784 #ifdef AUTO_INC_DEC
1785   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1786     if (REG_NOTE_KIND (link) == REG_INC
1787         && (JUMP_P (i3)
1788             || reg_used_between_p (XEXP (link, 0), insn, i3)
1789             || (pred != NULL_RTX
1790                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1791             || (succ != NULL_RTX
1792                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1793             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1794       return 0;
1795 #endif
1796
1797 #ifdef HAVE_cc0
1798   /* Don't combine an insn that follows a CC0-setting insn.
1799      An insn that uses CC0 must not be separated from the one that sets it.
1800      We do, however, allow I2 to follow a CC0-setting insn if that insn
1801      is passed as I1; in that case it will be deleted also.
1802      We also allow combining in this case if all the insns are adjacent
1803      because that would leave the two CC0 insns adjacent as well.
1804      It would be more logical to test whether CC0 occurs inside I1 or I2,
1805      but that would be much slower, and this ought to be equivalent.  */
1806
1807   p = prev_nonnote_insn (insn);
1808   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1809       && ! all_adjacent)
1810     return 0;
1811 #endif
1812
1813   /* If we get here, we have passed all the tests and the combination is
1814      to be allowed.  */
1815
1816   *pdest = dest;
1817   *psrc = src;
1818
1819   return 1;
1820 }
1821 \f
1822 /* LOC is the location within I3 that contains its pattern or the component
1823    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1824
1825    One problem is if I3 modifies its output, as opposed to replacing it
1826    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1827    so would produce an insn that is not equivalent to the original insns.
1828
1829    Consider:
1830
1831          (set (reg:DI 101) (reg:DI 100))
1832          (set (subreg:SI (reg:DI 101) 0) <foo>)
1833
1834    This is NOT equivalent to:
1835
1836          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1837                     (set (reg:DI 101) (reg:DI 100))])
1838
1839    Not only does this modify 100 (in which case it might still be valid
1840    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1841
1842    We can also run into a problem if I2 sets a register that I1
1843    uses and I1 gets directly substituted into I3 (not via I2).  In that
1844    case, we would be getting the wrong value of I2DEST into I3, so we
1845    must reject the combination.  This case occurs when I2 and I1 both
1846    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1847    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1848    of a SET must prevent combination from occurring.
1849
1850    Before doing the above check, we first try to expand a field assignment
1851    into a set of logical operations.
1852
1853    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1854    we place a register that is both set and used within I3.  If more than one
1855    such register is detected, we fail.
1856
1857    Return 1 if the combination is valid, zero otherwise.  */
1858
1859 static int
1860 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1861                   int i1_not_in_src, rtx *pi3dest_killed)
1862 {
1863   rtx x = *loc;
1864
1865   if (GET_CODE (x) == SET)
1866     {
1867       rtx set = x ;
1868       rtx dest = SET_DEST (set);
1869       rtx src = SET_SRC (set);
1870       rtx inner_dest = dest;
1871       rtx subdest;
1872
1873       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1874              || GET_CODE (inner_dest) == SUBREG
1875              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1876         inner_dest = XEXP (inner_dest, 0);
1877
1878       /* Check for the case where I3 modifies its output, as discussed
1879          above.  We don't want to prevent pseudos from being combined
1880          into the address of a MEM, so only prevent the combination if
1881          i1 or i2 set the same MEM.  */
1882       if ((inner_dest != dest &&
1883            (!MEM_P (inner_dest)
1884             || rtx_equal_p (i2dest, inner_dest)
1885             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1886            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1887                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1888
1889           /* This is the same test done in can_combine_p except we can't test
1890              all_adjacent; we don't have to, since this instruction will stay
1891              in place, thus we are not considering increasing the lifetime of
1892              INNER_DEST.
1893
1894              Also, if this insn sets a function argument, combining it with
1895              something that might need a spill could clobber a previous
1896              function argument; the all_adjacent test in can_combine_p also
1897              checks this; here, we do a more specific test for this case.  */
1898
1899           || (REG_P (inner_dest)
1900               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1901               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1902                                         GET_MODE (inner_dest))))
1903           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1904         return 0;
1905
1906       /* If DEST is used in I3, it is being killed in this insn, so
1907          record that for later.  We have to consider paradoxical
1908          subregs here, since they kill the whole register, but we
1909          ignore partial subregs, STRICT_LOW_PART, etc.
1910          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1911          STACK_POINTER_REGNUM, since these are always considered to be
1912          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1913       subdest = dest;
1914       if (GET_CODE (subdest) == SUBREG
1915           && (GET_MODE_SIZE (GET_MODE (subdest))
1916               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1917         subdest = SUBREG_REG (subdest);
1918       if (pi3dest_killed
1919           && REG_P (subdest)
1920           && reg_referenced_p (subdest, PATTERN (i3))
1921           && REGNO (subdest) != FRAME_POINTER_REGNUM
1922 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1923           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1924 #endif
1925 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1926           && (REGNO (subdest) != ARG_POINTER_REGNUM
1927               || ! fixed_regs [REGNO (subdest)])
1928 #endif
1929           && REGNO (subdest) != STACK_POINTER_REGNUM)
1930         {
1931           if (*pi3dest_killed)
1932             return 0;
1933
1934           *pi3dest_killed = subdest;
1935         }
1936     }
1937
1938   else if (GET_CODE (x) == PARALLEL)
1939     {
1940       int i;
1941
1942       for (i = 0; i < XVECLEN (x, 0); i++)
1943         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1944                                 i1_not_in_src, pi3dest_killed))
1945           return 0;
1946     }
1947
1948   return 1;
1949 }
1950 \f
1951 /* Return 1 if X is an arithmetic expression that contains a multiplication
1952    and division.  We don't count multiplications by powers of two here.  */
1953
1954 static int
1955 contains_muldiv (rtx x)
1956 {
1957   switch (GET_CODE (x))
1958     {
1959     case MOD:  case DIV:  case UMOD:  case UDIV:
1960       return 1;
1961
1962     case MULT:
1963       return ! (CONST_INT_P (XEXP (x, 1))
1964                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1965     default:
1966       if (BINARY_P (x))
1967         return contains_muldiv (XEXP (x, 0))
1968             || contains_muldiv (XEXP (x, 1));
1969
1970       if (UNARY_P (x))
1971         return contains_muldiv (XEXP (x, 0));
1972
1973       return 0;
1974     }
1975 }
1976 \f
1977 /* Determine whether INSN can be used in a combination.  Return nonzero if
1978    not.  This is used in try_combine to detect early some cases where we
1979    can't perform combinations.  */
1980
1981 static int
1982 cant_combine_insn_p (rtx insn)
1983 {
1984   rtx set;
1985   rtx src, dest;
1986
1987   /* If this isn't really an insn, we can't do anything.
1988      This can occur when flow deletes an insn that it has merged into an
1989      auto-increment address.  */
1990   if (! INSN_P (insn))
1991     return 1;
1992
1993   /* Never combine loads and stores involving hard regs that are likely
1994      to be spilled.  The register allocator can usually handle such
1995      reg-reg moves by tying.  If we allow the combiner to make
1996      substitutions of likely-spilled regs, reload might die.
1997      As an exception, we allow combinations involving fixed regs; these are
1998      not available to the register allocator so there's no risk involved.  */
1999
2000   set = single_set (insn);
2001   if (! set)
2002     return 0;
2003   src = SET_SRC (set);
2004   dest = SET_DEST (set);
2005   if (GET_CODE (src) == SUBREG)
2006     src = SUBREG_REG (src);
2007   if (GET_CODE (dest) == SUBREG)
2008     dest = SUBREG_REG (dest);
2009   if (REG_P (src) && REG_P (dest)
2010       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2011            && ! fixed_regs[REGNO (src)]
2012            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2013           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2014               && ! fixed_regs[REGNO (dest)]
2015               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2016     return 1;
2017
2018   return 0;
2019 }
2020
2021 struct likely_spilled_retval_info
2022 {
2023   unsigned regno, nregs;
2024   unsigned mask;
2025 };
2026
2027 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2028    hard registers that are known to be written to / clobbered in full.  */
2029 static void
2030 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2031 {
2032   struct likely_spilled_retval_info *const info =
2033     (struct likely_spilled_retval_info *) data;
2034   unsigned regno, nregs;
2035   unsigned new_mask;
2036
2037   if (!REG_P (XEXP (set, 0)))
2038     return;
2039   regno = REGNO (x);
2040   if (regno >= info->regno + info->nregs)
2041     return;
2042   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2043   if (regno + nregs <= info->regno)
2044     return;
2045   new_mask = (2U << (nregs - 1)) - 1;
2046   if (regno < info->regno)
2047     new_mask >>= info->regno - regno;
2048   else
2049     new_mask <<= regno - info->regno;
2050   info->mask &= ~new_mask;
2051 }
2052
2053 /* Return nonzero iff part of the return value is live during INSN, and
2054    it is likely spilled.  This can happen when more than one insn is needed
2055    to copy the return value, e.g. when we consider to combine into the
2056    second copy insn for a complex value.  */
2057
2058 static int
2059 likely_spilled_retval_p (rtx insn)
2060 {
2061   rtx use = BB_END (this_basic_block);
2062   rtx reg, p;
2063   unsigned regno, nregs;
2064   /* We assume here that no machine mode needs more than
2065      32 hard registers when the value overlaps with a register
2066      for which FUNCTION_VALUE_REGNO_P is true.  */
2067   unsigned mask;
2068   struct likely_spilled_retval_info info;
2069
2070   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2071     return 0;
2072   reg = XEXP (PATTERN (use), 0);
2073   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2074     return 0;
2075   regno = REGNO (reg);
2076   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2077   if (nregs == 1)
2078     return 0;
2079   mask = (2U << (nregs - 1)) - 1;
2080
2081   /* Disregard parts of the return value that are set later.  */
2082   info.regno = regno;
2083   info.nregs = nregs;
2084   info.mask = mask;
2085   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2086     if (INSN_P (p))
2087       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2088   mask = info.mask;
2089
2090   /* Check if any of the (probably) live return value registers is
2091      likely spilled.  */
2092   nregs --;
2093   do
2094     {
2095       if ((mask & 1 << nregs)
2096           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2097         return 1;
2098     } while (nregs--);
2099   return 0;
2100 }
2101
2102 /* Adjust INSN after we made a change to its destination.
2103
2104    Changing the destination can invalidate notes that say something about
2105    the results of the insn and a LOG_LINK pointing to the insn.  */
2106
2107 static void
2108 adjust_for_new_dest (rtx insn)
2109 {
2110   /* For notes, be conservative and simply remove them.  */
2111   remove_reg_equal_equiv_notes (insn);
2112
2113   /* The new insn will have a destination that was previously the destination
2114      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2115      the next use of that destination.  */
2116   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2117
2118   df_insn_rescan (insn);
2119 }
2120
2121 /* Return TRUE if combine can reuse reg X in mode MODE.
2122    ADDED_SETS is nonzero if the original set is still required.  */
2123 static bool
2124 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2125 {
2126   unsigned int regno;
2127
2128   if (!REG_P(x))
2129     return false;
2130
2131   regno = REGNO (x);
2132   /* Allow hard registers if the new mode is legal, and occupies no more
2133      registers than the old mode.  */
2134   if (regno < FIRST_PSEUDO_REGISTER)
2135     return (HARD_REGNO_MODE_OK (regno, mode)
2136             && (hard_regno_nregs[regno][GET_MODE (x)]
2137                 >= hard_regno_nregs[regno][mode]));
2138
2139   /* Or a pseudo that is only used once.  */
2140   return (REG_N_SETS (regno) == 1 && !added_sets
2141           && !REG_USERVAR_P (x));
2142 }
2143
2144
2145 /* Check whether X, the destination of a set, refers to part of
2146    the register specified by REG.  */
2147
2148 static bool
2149 reg_subword_p (rtx x, rtx reg)
2150 {
2151   /* Check that reg is an integer mode register.  */
2152   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2153     return false;
2154
2155   if (GET_CODE (x) == STRICT_LOW_PART
2156       || GET_CODE (x) == ZERO_EXTRACT)
2157     x = XEXP (x, 0);
2158
2159   return GET_CODE (x) == SUBREG
2160          && SUBREG_REG (x) == reg
2161          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2162 }
2163
2164 #ifdef AUTO_INC_DEC
2165 /* Replace auto-increment addressing modes with explicit operations to
2166    access the same addresses without modifying the corresponding
2167    registers.  If AFTER holds, SRC is meant to be reused after the
2168    side effect, otherwise it is to be reused before that.  */
2169
2170 static rtx
2171 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2172 {
2173   rtx x = src;
2174   const RTX_CODE code = GET_CODE (x);
2175   int i;
2176   const char *fmt;
2177
2178   switch (code)
2179     {
2180     case REG:
2181     case CONST_INT:
2182     case CONST_DOUBLE:
2183     case CONST_FIXED:
2184     case CONST_VECTOR:
2185     case SYMBOL_REF:
2186     case CODE_LABEL:
2187     case PC:
2188     case CC0:
2189     case SCRATCH:
2190       /* SCRATCH must be shared because they represent distinct values.  */
2191       return x;
2192     case CLOBBER:
2193       if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2194         return x;
2195       break;
2196
2197     case CONST:
2198       if (shared_const_p (x))
2199         return x;
2200       break;
2201
2202     case MEM:
2203       mem_mode = GET_MODE (x);
2204       break;
2205
2206     case PRE_INC:
2207     case PRE_DEC:
2208     case POST_INC:
2209     case POST_DEC:
2210       gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2211       if (after == (code == PRE_INC || code == PRE_DEC))
2212         x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2213       else
2214         x = gen_rtx_PLUS (GET_MODE (x),
2215                           cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2216                           GEN_INT ((code == PRE_INC || code == POST_INC)
2217                                    ? GET_MODE_SIZE (mem_mode)
2218                                    : -GET_MODE_SIZE (mem_mode)));
2219       return x;
2220
2221     case PRE_MODIFY:
2222     case POST_MODIFY:
2223       if (after == (code == PRE_MODIFY))
2224         x = XEXP (x, 0);
2225       else
2226         x = XEXP (x, 1);
2227       return cleanup_auto_inc_dec (x, after, mem_mode);
2228
2229     default:
2230       break;
2231     }
2232
2233   /* Copy the various flags, fields, and other information.  We assume
2234      that all fields need copying, and then clear the fields that should
2235      not be copied.  That is the sensible default behavior, and forces
2236      us to explicitly document why we are *not* copying a flag.  */
2237   x = shallow_copy_rtx (x);
2238
2239   /* We do not copy the USED flag, which is used as a mark bit during
2240      walks over the RTL.  */
2241   RTX_FLAG (x, used) = 0;
2242
2243   /* We do not copy FRAME_RELATED for INSNs.  */
2244   if (INSN_P (x))
2245     RTX_FLAG (x, frame_related) = 0;
2246
2247   fmt = GET_RTX_FORMAT (code);
2248   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2249     if (fmt[i] == 'e')
2250       XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2251     else if (fmt[i] == 'E' || fmt[i] == 'V')
2252       {
2253         int j;
2254         XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2255         for (j = 0; j < XVECLEN (x, i); j++)
2256           XVECEXP (x, i, j)
2257             = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2258       }
2259
2260   return x;
2261 }
2262 #endif
2263
2264 /* Auxiliary data structure for propagate_for_debug_stmt.  */
2265
2266 struct rtx_subst_pair
2267 {
2268   rtx from, to;
2269   bool changed;
2270 #ifdef AUTO_INC_DEC
2271   bool adjusted;
2272   bool after;
2273 #endif
2274 };
2275
2276 /* Clean up any auto-updates in PAIR->to the first time it is called
2277    for a PAIR.  PAIR->adjusted is used to tell whether we've cleaned
2278    up before.  */
2279
2280 static void
2281 auto_adjust_pair (struct rtx_subst_pair *pair ATTRIBUTE_UNUSED)
2282 {
2283 #ifdef AUTO_INC_DEC
2284   if (!pair->adjusted)
2285     {
2286       pair->adjusted = true;
2287       pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2288     }
2289 #endif
2290 }
2291
2292 /* If *LOC is the same as FROM in the struct rtx_subst_pair passed as
2293    DATA, replace it with a copy of TO.  Handle SUBREGs of *LOC as
2294    well.  */
2295
2296 static int
2297 propagate_for_debug_subst (rtx *loc, void *data)
2298 {
2299   struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2300   rtx from = pair->from, to = pair->to;
2301   rtx x = *loc, s = x;
2302
2303   if (rtx_equal_p (x, from)
2304       || (GET_CODE (x) == SUBREG && rtx_equal_p ((s = SUBREG_REG (x)), from)))
2305     {
2306       auto_adjust_pair (pair);
2307       if (pair->to != to)
2308         to = pair->to;
2309       else
2310         to = copy_rtx (to);
2311       if (s != x)
2312         {
2313           gcc_assert (GET_CODE (x) == SUBREG && SUBREG_REG (x) == s);
2314           to = simplify_gen_subreg (GET_MODE (x), to,
2315                                     GET_MODE (from), SUBREG_BYTE (x));
2316         }
2317       *loc = to;
2318       pair->changed = true;
2319       return -1;
2320     }
2321
2322   return 0;
2323 }
2324
2325 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2326    and LAST.  If MOVE holds, debug insns must also be moved past
2327    LAST.  */
2328
2329 static void
2330 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2331 {
2332   struct rtx_subst_pair p;
2333   rtx next, move_pos = move ? last : NULL_RTX;
2334
2335   p.from = dest;
2336   p.to = src;
2337   p.changed = false;
2338
2339 #ifdef AUTO_INC_DEC
2340   p.adjusted = false;
2341   p.after = move;
2342 #endif
2343
2344   next = NEXT_INSN (insn);
2345   while (next != last)
2346     {
2347       insn = next;
2348       next = NEXT_INSN (insn);
2349       if (DEBUG_INSN_P (insn))
2350         {
2351           for_each_rtx (&INSN_VAR_LOCATION_LOC (insn),
2352                         propagate_for_debug_subst, &p);
2353           if (!p.changed)
2354             continue;
2355           p.changed = false;
2356           if (move_pos)
2357             {
2358               remove_insn (insn);
2359               PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2360               move_pos = emit_debug_insn_after (insn, move_pos);
2361             }
2362           else
2363             df_insn_rescan (insn);
2364         }
2365     }
2366 }
2367
2368 /* Delete the conditional jump INSN and adjust the CFG correspondingly.
2369    Note that the INSN should be deleted *after* removing dead edges, so
2370    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2371    but not for a (set (pc) (label_ref FOO)).  */
2372
2373 static void
2374 update_cfg_for_uncondjump (rtx insn)
2375 {
2376   basic_block bb = BLOCK_FOR_INSN (insn);
2377
2378   if (BB_END (bb) == insn)
2379     purge_dead_edges (bb);
2380
2381   delete_insn (insn);
2382   if (EDGE_COUNT (bb->succs) == 1)
2383     single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2384 }
2385
2386
2387 /* Try to combine the insns I1 and I2 into I3.
2388    Here I1 and I2 appear earlier than I3.
2389    I1 can be zero; then we combine just I2 into I3.
2390
2391    If we are combining three insns and the resulting insn is not recognized,
2392    try splitting it into two insns.  If that happens, I2 and I3 are retained
2393    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
2394    are pseudo-deleted.
2395
2396    Return 0 if the combination does not work.  Then nothing is changed.
2397    If we did the combination, return the insn at which combine should
2398    resume scanning.
2399
2400    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2401    new direct jump instruction.  */
2402
2403 static rtx
2404 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2405 {
2406   /* New patterns for I3 and I2, respectively.  */
2407   rtx newpat, newi2pat = 0;
2408   rtvec newpat_vec_with_clobbers = 0;
2409   int substed_i2 = 0, substed_i1 = 0;
2410   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
2411   int added_sets_1, added_sets_2;
2412   /* Total number of SETs to put into I3.  */
2413   int total_sets;
2414   /* Nonzero if I2's body now appears in I3.  */
2415   int i2_is_used;
2416   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2417   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2418   /* Contains I3 if the destination of I3 is used in its source, which means
2419      that the old life of I3 is being killed.  If that usage is placed into
2420      I2 and not in I3, a REG_DEAD note must be made.  */
2421   rtx i3dest_killed = 0;
2422   /* SET_DEST and SET_SRC of I2 and I1.  */
2423   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2424   /* Set if I2DEST was reused as a scratch register.  */
2425   bool i2scratch = false;
2426   /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases.  */
2427   rtx i1pat = 0, i2pat = 0;
2428   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2429   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2430   int i2dest_killed = 0, i1dest_killed = 0;
2431   int i1_feeds_i3 = 0;
2432   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2433   rtx new_i3_notes, new_i2_notes;
2434   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2435   int i3_subst_into_i2 = 0;
2436   /* Notes that I1, I2 or I3 is a MULT operation.  */
2437   int have_mult = 0;
2438   int swap_i2i3 = 0;
2439   int changed_i3_dest = 0;
2440
2441   int maxreg;
2442   rtx temp;
2443   rtx link;
2444   rtx other_pat = 0;
2445   rtx new_other_notes;
2446   int i;
2447
2448   /* Exit early if one of the insns involved can't be used for
2449      combinations.  */
2450   if (cant_combine_insn_p (i3)
2451       || cant_combine_insn_p (i2)
2452       || (i1 && cant_combine_insn_p (i1))
2453       || likely_spilled_retval_p (i3))
2454     return 0;
2455
2456   combine_attempts++;
2457   undobuf.other_insn = 0;
2458
2459   /* Reset the hard register usage information.  */
2460   CLEAR_HARD_REG_SET (newpat_used_regs);
2461
2462   if (dump_file && (dump_flags & TDF_DETAILS))
2463     {
2464       if (i1)
2465         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2466                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2467       else
2468         fprintf (dump_file, "\nTrying %d -> %d:\n",
2469                  INSN_UID (i2), INSN_UID (i3));
2470     }
2471
2472   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
2473      code below, set I1 to be the earlier of the two insns.  */
2474   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2475     temp = i1, i1 = i2, i2 = temp;
2476
2477   added_links_insn = 0;
2478
2479   /* First check for one important special-case that the code below will
2480      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2481      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2482      we may be able to replace that destination with the destination of I3.
2483      This occurs in the common code where we compute both a quotient and
2484      remainder into a structure, in which case we want to do the computation
2485      directly into the structure to avoid register-register copies.
2486
2487      Note that this case handles both multiple sets in I2 and also
2488      cases where I2 has a number of CLOBBER or PARALLELs.
2489
2490      We make very conservative checks below and only try to handle the
2491      most common cases of this.  For example, we only handle the case
2492      where I2 and I3 are adjacent to avoid making difficult register
2493      usage tests.  */
2494
2495   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2496       && REG_P (SET_SRC (PATTERN (i3)))
2497       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2498       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2499       && GET_CODE (PATTERN (i2)) == PARALLEL
2500       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2501       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2502          below would need to check what is inside (and reg_overlap_mentioned_p
2503          doesn't support those codes anyway).  Don't allow those destinations;
2504          the resulting insn isn't likely to be recognized anyway.  */
2505       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2506       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2507       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2508                                     SET_DEST (PATTERN (i3)))
2509       && next_active_insn (i2) == i3)
2510     {
2511       rtx p2 = PATTERN (i2);
2512
2513       /* Make sure that the destination of I3,
2514          which we are going to substitute into one output of I2,
2515          is not used within another output of I2.  We must avoid making this:
2516          (parallel [(set (mem (reg 69)) ...)
2517                     (set (reg 69) ...)])
2518          which is not well-defined as to order of actions.
2519          (Besides, reload can't handle output reloads for this.)
2520
2521          The problem can also happen if the dest of I3 is a memory ref,
2522          if another dest in I2 is an indirect memory ref.  */
2523       for (i = 0; i < XVECLEN (p2, 0); i++)
2524         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2525              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2526             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2527                                         SET_DEST (XVECEXP (p2, 0, i))))
2528           break;
2529
2530       if (i == XVECLEN (p2, 0))
2531         for (i = 0; i < XVECLEN (p2, 0); i++)
2532           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2533                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2534               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2535             {
2536               combine_merges++;
2537
2538               subst_insn = i3;
2539               subst_low_luid = DF_INSN_LUID (i2);
2540
2541               added_sets_2 = added_sets_1 = 0;
2542               i2src = SET_DEST (PATTERN (i3));
2543               i2dest = SET_SRC (PATTERN (i3));
2544               i2dest_killed = dead_or_set_p (i2, i2dest);
2545
2546               /* Replace the dest in I2 with our dest and make the resulting
2547                  insn the new pattern for I3.  Then skip to where we
2548                  validate the pattern.  Everything was set up above.  */
2549               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2550                      SET_DEST (PATTERN (i3)));
2551
2552               newpat = p2;
2553               i3_subst_into_i2 = 1;
2554               goto validate_replacement;
2555             }
2556     }
2557
2558   /* If I2 is setting a pseudo to a constant and I3 is setting some
2559      sub-part of it to another constant, merge them by making a new
2560      constant.  */
2561   if (i1 == 0
2562       && (temp = single_set (i2)) != 0
2563       && (CONST_INT_P (SET_SRC (temp))
2564           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2565       && GET_CODE (PATTERN (i3)) == SET
2566       && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2567           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2568       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2569     {
2570       rtx dest = SET_DEST (PATTERN (i3));
2571       int offset = -1;
2572       int width = 0;
2573
2574       if (GET_CODE (dest) == ZERO_EXTRACT)
2575         {
2576           if (CONST_INT_P (XEXP (dest, 1))
2577               && CONST_INT_P (XEXP (dest, 2)))
2578             {
2579               width = INTVAL (XEXP (dest, 1));
2580               offset = INTVAL (XEXP (dest, 2));
2581               dest = XEXP (dest, 0);
2582               if (BITS_BIG_ENDIAN)
2583                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2584             }
2585         }
2586       else
2587         {
2588           if (GET_CODE (dest) == STRICT_LOW_PART)
2589             dest = XEXP (dest, 0);
2590           width = GET_MODE_BITSIZE (GET_MODE (dest));
2591           offset = 0;
2592         }
2593
2594       if (offset >= 0)
2595         {
2596           /* If this is the low part, we're done.  */
2597           if (subreg_lowpart_p (dest))
2598             ;
2599           /* Handle the case where inner is twice the size of outer.  */
2600           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2601                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2602             offset += GET_MODE_BITSIZE (GET_MODE (dest));
2603           /* Otherwise give up for now.  */
2604           else
2605             offset = -1;
2606         }
2607
2608       if (offset >= 0
2609           && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2610               <= HOST_BITS_PER_WIDE_INT * 2))
2611         {
2612           HOST_WIDE_INT mhi, ohi, ihi;
2613           HOST_WIDE_INT mlo, olo, ilo;
2614           rtx inner = SET_SRC (PATTERN (i3));
2615           rtx outer = SET_SRC (temp);
2616
2617           if (CONST_INT_P (outer))
2618             {
2619               olo = INTVAL (outer);
2620               ohi = olo < 0 ? -1 : 0;
2621             }
2622           else
2623             {
2624               olo = CONST_DOUBLE_LOW (outer);
2625               ohi = CONST_DOUBLE_HIGH (outer);
2626             }
2627
2628           if (CONST_INT_P (inner))
2629             {
2630               ilo = INTVAL (inner);
2631               ihi = ilo < 0 ? -1 : 0;
2632             }
2633           else
2634             {
2635               ilo = CONST_DOUBLE_LOW (inner);
2636               ihi = CONST_DOUBLE_HIGH (inner);
2637             }
2638
2639           if (width < HOST_BITS_PER_WIDE_INT)
2640             {
2641               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2642               mhi = 0;
2643             }
2644           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2645             {
2646               mhi = ((unsigned HOST_WIDE_INT) 1
2647                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2648               mlo = -1;
2649             }
2650           else
2651             {
2652               mlo = -1;
2653               mhi = -1;
2654             }
2655
2656           ilo &= mlo;
2657           ihi &= mhi;
2658
2659           if (offset >= HOST_BITS_PER_WIDE_INT)
2660             {
2661               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2662               mlo = 0;
2663               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2664               ilo = 0;
2665             }
2666           else if (offset > 0)
2667             {
2668               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2669                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2670               mlo = mlo << offset;
2671               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2672                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2673               ilo = ilo << offset;
2674             }
2675
2676           olo = (olo & ~mlo) | ilo;
2677           ohi = (ohi & ~mhi) | ihi;
2678
2679           combine_merges++;
2680           subst_insn = i3;
2681           subst_low_luid = DF_INSN_LUID (i2);
2682           added_sets_2 = added_sets_1 = 0;
2683           i2dest = SET_DEST (temp);
2684           i2dest_killed = dead_or_set_p (i2, i2dest);
2685
2686           SUBST (SET_SRC (temp),
2687                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2688
2689           newpat = PATTERN (i2);
2690           goto validate_replacement;
2691         }
2692     }
2693
2694 #ifndef HAVE_cc0
2695   /* If we have no I1 and I2 looks like:
2696         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2697                    (set Y OP)])
2698      make up a dummy I1 that is
2699         (set Y OP)
2700      and change I2 to be
2701         (set (reg:CC X) (compare:CC Y (const_int 0)))
2702
2703      (We can ignore any trailing CLOBBERs.)
2704
2705      This undoes a previous combination and allows us to match a branch-and-
2706      decrement insn.  */
2707
2708   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2709       && XVECLEN (PATTERN (i2), 0) >= 2
2710       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2711       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2712           == MODE_CC)
2713       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2714       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2715       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2716       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2717       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2718                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2719     {
2720       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2721         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2722           break;
2723
2724       if (i == 1)
2725         {
2726           /* We make I1 with the same INSN_UID as I2.  This gives it
2727              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2728              never appear in the insn stream so giving it the same INSN_UID
2729              as I2 will not cause a problem.  */
2730
2731           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2732                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2733                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2734
2735           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2736           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2737                  SET_DEST (PATTERN (i1)));
2738         }
2739     }
2740 #endif
2741
2742   /* Verify that I2 and I1 are valid for combining.  */
2743   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2744       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2745     {
2746       undo_all ();
2747       return 0;
2748     }
2749
2750   /* Record whether I2DEST is used in I2SRC and similarly for the other
2751      cases.  Knowing this will help in register status updating below.  */
2752   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2753   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2754   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2755   i2dest_killed = dead_or_set_p (i2, i2dest);
2756   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2757
2758   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2759      in I2SRC.  */
2760   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2761
2762   /* Ensure that I3's pattern can be the destination of combines.  */
2763   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2764                           i1 && i2dest_in_i1src && i1_feeds_i3,
2765                           &i3dest_killed))
2766     {
2767       undo_all ();
2768       return 0;
2769     }
2770
2771   /* See if any of the insns is a MULT operation.  Unless one is, we will
2772      reject a combination that is, since it must be slower.  Be conservative
2773      here.  */
2774   if (GET_CODE (i2src) == MULT
2775       || (i1 != 0 && GET_CODE (i1src) == MULT)
2776       || (GET_CODE (PATTERN (i3)) == SET
2777           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2778     have_mult = 1;
2779
2780   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2781      We used to do this EXCEPT in one case: I3 has a post-inc in an
2782      output operand.  However, that exception can give rise to insns like
2783         mov r3,(r3)+
2784      which is a famous insn on the PDP-11 where the value of r3 used as the
2785      source was model-dependent.  Avoid this sort of thing.  */
2786
2787 #if 0
2788   if (!(GET_CODE (PATTERN (i3)) == SET
2789         && REG_P (SET_SRC (PATTERN (i3)))
2790         && MEM_P (SET_DEST (PATTERN (i3)))
2791         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2792             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2793     /* It's not the exception.  */
2794 #endif
2795 #ifdef AUTO_INC_DEC
2796     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2797       if (REG_NOTE_KIND (link) == REG_INC
2798           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2799               || (i1 != 0
2800                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2801         {
2802           undo_all ();
2803           return 0;
2804         }
2805 #endif
2806
2807   /* See if the SETs in I1 or I2 need to be kept around in the merged
2808      instruction: whenever the value set there is still needed past I3.
2809      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2810
2811      For the SET in I1, we have two cases:  If I1 and I2 independently
2812      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2813      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2814      in I1 needs to be kept around unless I1DEST dies or is set in either
2815      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2816      I1DEST.  If so, we know I1 feeds into I2.  */
2817
2818   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2819
2820   added_sets_1
2821     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2822                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2823
2824   /* If the set in I2 needs to be kept around, we must make a copy of
2825      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2826      PATTERN (I2), we are only substituting for the original I1DEST, not into
2827      an already-substituted copy.  This also prevents making self-referential
2828      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2829      I2DEST.  */
2830
2831   if (added_sets_2)
2832     {
2833       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2834         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2835       else
2836         i2pat = copy_rtx (PATTERN (i2));
2837     }
2838
2839   if (added_sets_1)
2840     {
2841       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2842         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2843       else
2844         i1pat = copy_rtx (PATTERN (i1));
2845     }
2846
2847   combine_merges++;
2848
2849   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2850
2851   maxreg = max_reg_num ();
2852
2853   subst_insn = i3;
2854
2855 #ifndef HAVE_cc0
2856   /* Many machines that don't use CC0 have insns that can both perform an
2857      arithmetic operation and set the condition code.  These operations will
2858      be represented as a PARALLEL with the first element of the vector
2859      being a COMPARE of an arithmetic operation with the constant zero.
2860      The second element of the vector will set some pseudo to the result
2861      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2862      match such a pattern and so will generate an extra insn.   Here we test
2863      for this case, where both the comparison and the operation result are
2864      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2865      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2866
2867   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2868       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2869       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2870       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2871     {
2872 #ifdef SELECT_CC_MODE
2873       rtx *cc_use;
2874       enum machine_mode compare_mode;
2875 #endif
2876
2877       newpat = PATTERN (i3);
2878       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2879
2880       i2_is_used = 1;
2881
2882 #ifdef SELECT_CC_MODE
2883       /* See if a COMPARE with the operand we substituted in should be done
2884          with the mode that is currently being used.  If not, do the same
2885          processing we do in `subst' for a SET; namely, if the destination
2886          is used only once, try to replace it with a register of the proper
2887          mode and also replace the COMPARE.  */
2888       if (undobuf.other_insn == 0
2889           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2890                                         &undobuf.other_insn))
2891           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2892                                               i2src, const0_rtx))
2893               != GET_MODE (SET_DEST (newpat))))
2894         {
2895           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2896                                    compare_mode))
2897             {
2898               unsigned int regno = REGNO (SET_DEST (newpat));
2899               rtx new_dest;
2900
2901               if (regno < FIRST_PSEUDO_REGISTER)
2902                 new_dest = gen_rtx_REG (compare_mode, regno);
2903               else
2904                 {
2905                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2906                   new_dest = regno_reg_rtx[regno];
2907                 }
2908
2909               SUBST (SET_DEST (newpat), new_dest);
2910               SUBST (XEXP (*cc_use, 0), new_dest);
2911               SUBST (SET_SRC (newpat),
2912                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2913             }
2914           else
2915             undobuf.other_insn = 0;
2916         }
2917 #endif
2918     }
2919   else
2920 #endif
2921     {
2922       /* It is possible that the source of I2 or I1 may be performing
2923          an unneeded operation, such as a ZERO_EXTEND of something
2924          that is known to have the high part zero.  Handle that case
2925          by letting subst look at the innermost one of them.
2926
2927          Another way to do this would be to have a function that tries
2928          to simplify a single insn instead of merging two or more
2929          insns.  We don't do this because of the potential of infinite
2930          loops and because of the potential extra memory required.
2931          However, doing it the way we are is a bit of a kludge and
2932          doesn't catch all cases.
2933
2934          But only do this if -fexpensive-optimizations since it slows
2935          things down and doesn't usually win.
2936
2937          This is not done in the COMPARE case above because the
2938          unmodified I2PAT is used in the PARALLEL and so a pattern
2939          with a modified I2SRC would not match.  */
2940
2941       if (flag_expensive_optimizations)
2942         {
2943           /* Pass pc_rtx so no substitutions are done, just
2944              simplifications.  */
2945           if (i1)
2946             {
2947               subst_low_luid = DF_INSN_LUID (i1);
2948               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2949             }
2950           else
2951             {
2952               subst_low_luid = DF_INSN_LUID (i2);
2953               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2954             }
2955         }
2956
2957       n_occurrences = 0;                /* `subst' counts here */
2958
2959       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2960          need to make a unique copy of I2SRC each time we substitute it
2961          to avoid self-referential rtl.  */
2962
2963       subst_low_luid = DF_INSN_LUID (i2);
2964       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2965                       ! i1_feeds_i3 && i1dest_in_i1src);
2966       substed_i2 = 1;
2967
2968       /* Record whether i2's body now appears within i3's body.  */
2969       i2_is_used = n_occurrences;
2970     }
2971
2972   /* If we already got a failure, don't try to do more.  Otherwise,
2973      try to substitute in I1 if we have it.  */
2974
2975   if (i1 && GET_CODE (newpat) != CLOBBER)
2976     {
2977       /* Check that an autoincrement side-effect on I1 has not been lost.
2978          This happens if I1DEST is mentioned in I2 and dies there, and
2979          has disappeared from the new pattern.  */
2980       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2981            && !i1_feeds_i3
2982            && dead_or_set_p (i2, i1dest)
2983            && !reg_overlap_mentioned_p (i1dest, newpat))
2984           /* Before we can do this substitution, we must redo the test done
2985              above (see detailed comments there) that ensures  that I1DEST
2986              isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2987           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2988         {
2989           undo_all ();
2990           return 0;
2991         }
2992
2993       n_occurrences = 0;
2994       subst_low_luid = DF_INSN_LUID (i1);
2995       newpat = subst (newpat, i1dest, i1src, 0, 0);
2996       substed_i1 = 1;
2997     }
2998
2999   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3000      to count all the ways that I2SRC and I1SRC can be used.  */
3001   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3002        && i2_is_used + added_sets_2 > 1)
3003       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3004           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
3005               > 1))
3006       /* Fail if we tried to make a new register.  */
3007       || max_reg_num () != maxreg
3008       /* Fail if we couldn't do something and have a CLOBBER.  */
3009       || GET_CODE (newpat) == CLOBBER
3010       /* Fail if this new pattern is a MULT and we didn't have one before
3011          at the outer level.  */
3012       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3013           && ! have_mult))
3014     {
3015       undo_all ();
3016       return 0;
3017     }
3018
3019   /* If the actions of the earlier insns must be kept
3020      in addition to substituting them into the latest one,
3021      we must make a new PARALLEL for the latest insn
3022      to hold additional the SETs.  */
3023
3024   if (added_sets_1 || added_sets_2)
3025     {
3026       combine_extras++;
3027
3028       if (GET_CODE (newpat) == PARALLEL)
3029         {
3030           rtvec old = XVEC (newpat, 0);
3031           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
3032           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3033           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3034                   sizeof (old->elem[0]) * old->num_elem);
3035         }
3036       else
3037         {
3038           rtx old = newpat;
3039           total_sets = 1 + added_sets_1 + added_sets_2;
3040           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3041           XVECEXP (newpat, 0, 0) = old;
3042         }
3043
3044       if (added_sets_1)
3045         XVECEXP (newpat, 0, --total_sets) = i1pat;
3046
3047       if (added_sets_2)
3048         {
3049           /* If there is no I1, use I2's body as is.  We used to also not do
3050              the subst call below if I2 was substituted into I3,
3051              but that could lose a simplification.  */
3052           if (i1 == 0)
3053             XVECEXP (newpat, 0, --total_sets) = i2pat;
3054           else
3055             /* See comment where i2pat is assigned.  */
3056             XVECEXP (newpat, 0, --total_sets)
3057               = subst (i2pat, i1dest, i1src, 0, 0);
3058         }
3059     }
3060
3061   /* We come here when we are replacing a destination in I2 with the
3062      destination of I3.  */
3063  validate_replacement:
3064
3065   /* Note which hard regs this insn has as inputs.  */
3066   mark_used_regs_combine (newpat);
3067
3068   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3069      consider splitting this pattern, we might need these clobbers.  */
3070   if (i1 && GET_CODE (newpat) == PARALLEL
3071       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3072     {
3073       int len = XVECLEN (newpat, 0);
3074
3075       newpat_vec_with_clobbers = rtvec_alloc (len);
3076       for (i = 0; i < len; i++)
3077         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3078     }
3079
3080   /* Is the result of combination a valid instruction?  */
3081   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3082
3083   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3084      the second SET's destination is a register that is unused and isn't
3085      marked as an instruction that might trap in an EH region.  In that case,
3086      we just need the first SET.   This can occur when simplifying a divmod
3087      insn.  We *must* test for this case here because the code below that
3088      splits two independent SETs doesn't handle this case correctly when it
3089      updates the register status.
3090
3091      It's pointless doing this if we originally had two sets, one from
3092      i3, and one from i2.  Combining then splitting the parallel results
3093      in the original i2 again plus an invalid insn (which we delete).
3094      The net effect is only to move instructions around, which makes
3095      debug info less accurate.
3096
3097      Also check the case where the first SET's destination is unused.
3098      That would not cause incorrect code, but does cause an unneeded
3099      insn to remain.  */
3100
3101   if (insn_code_number < 0
3102       && !(added_sets_2 && i1 == 0)
3103       && GET_CODE (newpat) == PARALLEL
3104       && XVECLEN (newpat, 0) == 2
3105       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3106       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3107       && asm_noperands (newpat) < 0)
3108     {
3109       rtx set0 = XVECEXP (newpat, 0, 0);
3110       rtx set1 = XVECEXP (newpat, 0, 1);
3111       rtx note;
3112
3113       if (((REG_P (SET_DEST (set1))
3114             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3115            || (GET_CODE (SET_DEST (set1)) == SUBREG
3116                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3117           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
3118               || INTVAL (XEXP (note, 0)) <= 0)
3119           && ! side_effects_p (SET_SRC (set1)))
3120         {
3121           newpat = set0;
3122           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3123         }
3124
3125       else if (((REG_P (SET_DEST (set0))
3126                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3127                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3128                     && find_reg_note (i3, REG_UNUSED,
3129                                       SUBREG_REG (SET_DEST (set0)))))
3130                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
3131                    || INTVAL (XEXP (note, 0)) <= 0)
3132                && ! side_effects_p (SET_SRC (set0)))
3133         {
3134           newpat = set1;
3135           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3136
3137           if (insn_code_number >= 0)
3138             changed_i3_dest = 1;
3139         }
3140     }
3141
3142   /* If we were combining three insns and the result is a simple SET
3143      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3144      insns.  There are two ways to do this.  It can be split using a
3145      machine-specific method (like when you have an addition of a large
3146      constant) or by combine in the function find_split_point.  */
3147
3148   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3149       && asm_noperands (newpat) < 0)
3150     {
3151       rtx parallel, m_split, *split;
3152
3153       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3154          use I2DEST as a scratch register will help.  In the latter case,
3155          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3156
3157       m_split = combine_split_insns (newpat, i3);
3158
3159       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3160          inputs of NEWPAT.  */
3161
3162       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3163          possible to try that as a scratch reg.  This would require adding
3164          more code to make it work though.  */
3165
3166       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3167         {
3168           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3169
3170           /* First try to split using the original register as a
3171              scratch register.  */
3172           parallel = gen_rtx_PARALLEL (VOIDmode,
3173                                        gen_rtvec (2, newpat,
3174                                                   gen_rtx_CLOBBER (VOIDmode,
3175                                                                    i2dest)));
3176           m_split = combine_split_insns (parallel, i3);
3177
3178           /* If that didn't work, try changing the mode of I2DEST if
3179              we can.  */
3180           if (m_split == 0
3181               && new_mode != GET_MODE (i2dest)
3182               && new_mode != VOIDmode
3183               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3184             {
3185               enum machine_mode old_mode = GET_MODE (i2dest);
3186               rtx ni2dest;
3187
3188               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3189                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3190               else
3191                 {
3192                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3193                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3194                 }
3195
3196               parallel = (gen_rtx_PARALLEL
3197                           (VOIDmode,
3198                            gen_rtvec (2, newpat,
3199                                       gen_rtx_CLOBBER (VOIDmode,
3200                                                        ni2dest))));
3201               m_split = combine_split_insns (parallel, i3);
3202
3203               if (m_split == 0
3204                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3205                 {
3206                   struct undo *buf;
3207
3208                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3209                   buf = undobuf.undos;
3210                   undobuf.undos = buf->next;
3211                   buf->next = undobuf.frees;
3212                   undobuf.frees = buf;
3213                 }
3214             }
3215
3216           i2scratch = m_split != 0;
3217         }
3218
3219       /* If recog_for_combine has discarded clobbers, try to use them
3220          again for the split.  */
3221       if (m_split == 0 && newpat_vec_with_clobbers)
3222         {
3223           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3224           m_split = combine_split_insns (parallel, i3);
3225         }
3226
3227       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3228         {
3229           m_split = PATTERN (m_split);
3230           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3231           if (insn_code_number >= 0)
3232             newpat = m_split;
3233         }
3234       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3235                && (next_real_insn (i2) == i3
3236                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3237         {
3238           rtx i2set, i3set;
3239           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3240           newi2pat = PATTERN (m_split);
3241
3242           i3set = single_set (NEXT_INSN (m_split));
3243           i2set = single_set (m_split);
3244
3245           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3246
3247           /* If I2 or I3 has multiple SETs, we won't know how to track
3248              register status, so don't use these insns.  If I2's destination
3249              is used between I2 and I3, we also can't use these insns.  */
3250
3251           if (i2_code_number >= 0 && i2set && i3set
3252               && (next_real_insn (i2) == i3
3253                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3254             insn_code_number = recog_for_combine (&newi3pat, i3,
3255                                                   &new_i3_notes);
3256           if (insn_code_number >= 0)
3257             newpat = newi3pat;
3258
3259           /* It is possible that both insns now set the destination of I3.
3260              If so, we must show an extra use of it.  */
3261
3262           if (insn_code_number >= 0)
3263             {
3264               rtx new_i3_dest = SET_DEST (i3set);
3265               rtx new_i2_dest = SET_DEST (i2set);
3266
3267               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3268                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3269                      || GET_CODE (new_i3_dest) == SUBREG)
3270                 new_i3_dest = XEXP (new_i3_dest, 0);
3271
3272               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3273                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3274                      || GET_CODE (new_i2_dest) == SUBREG)
3275                 new_i2_dest = XEXP (new_i2_dest, 0);
3276
3277               if (REG_P (new_i3_dest)
3278                   && REG_P (new_i2_dest)
3279                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3280                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3281             }
3282         }
3283
3284       /* If we can split it and use I2DEST, go ahead and see if that
3285          helps things be recognized.  Verify that none of the registers
3286          are set between I2 and I3.  */
3287       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3288 #ifdef HAVE_cc0
3289           && REG_P (i2dest)
3290 #endif
3291           /* We need I2DEST in the proper mode.  If it is a hard register
3292              or the only use of a pseudo, we can change its mode.
3293              Make sure we don't change a hard register to have a mode that
3294              isn't valid for it, or change the number of registers.  */
3295           && (GET_MODE (*split) == GET_MODE (i2dest)
3296               || GET_MODE (*split) == VOIDmode
3297               || can_change_dest_mode (i2dest, added_sets_2,
3298                                        GET_MODE (*split)))
3299           && (next_real_insn (i2) == i3
3300               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3301           /* We can't overwrite I2DEST if its value is still used by
3302              NEWPAT.  */
3303           && ! reg_referenced_p (i2dest, newpat))
3304         {
3305           rtx newdest = i2dest;
3306           enum rtx_code split_code = GET_CODE (*split);
3307           enum machine_mode split_mode = GET_MODE (*split);
3308           bool subst_done = false;
3309           newi2pat = NULL_RTX;
3310
3311           i2scratch = true;
3312
3313           /* Get NEWDEST as a register in the proper mode.  We have already
3314              validated that we can do this.  */
3315           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3316             {
3317               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3318                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3319               else
3320                 {
3321                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3322                   newdest = regno_reg_rtx[REGNO (i2dest)];
3323                 }
3324             }
3325
3326           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3327              an ASHIFT.  This can occur if it was inside a PLUS and hence
3328              appeared to be a memory address.  This is a kludge.  */
3329           if (split_code == MULT
3330               && CONST_INT_P (XEXP (*split, 1))
3331               && INTVAL (XEXP (*split, 1)) > 0
3332               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3333             {
3334               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3335                                              XEXP (*split, 0), GEN_INT (i)));
3336               /* Update split_code because we may not have a multiply
3337                  anymore.  */
3338               split_code = GET_CODE (*split);
3339             }
3340
3341 #ifdef INSN_SCHEDULING
3342           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3343              be written as a ZERO_EXTEND.  */
3344           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3345             {
3346 #ifdef LOAD_EXTEND_OP
3347               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3348                  what it really is.  */
3349               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3350                   == SIGN_EXTEND)
3351                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3352                                                     SUBREG_REG (*split)));
3353               else
3354 #endif
3355                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3356                                                     SUBREG_REG (*split)));
3357             }
3358 #endif
3359
3360           /* Attempt to split binary operators using arithmetic identities.  */
3361           if (BINARY_P (SET_SRC (newpat))
3362               && split_mode == GET_MODE (SET_SRC (newpat))
3363               && ! side_effects_p (SET_SRC (newpat)))
3364             {
3365               rtx setsrc = SET_SRC (newpat);
3366               enum machine_mode mode = GET_MODE (setsrc);
3367               enum rtx_code code = GET_CODE (setsrc);
3368               rtx src_op0 = XEXP (setsrc, 0);
3369               rtx src_op1 = XEXP (setsrc, 1);
3370
3371               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3372               if (rtx_equal_p (src_op0, src_op1))
3373                 {
3374                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3375                   SUBST (XEXP (setsrc, 0), newdest);
3376                   SUBST (XEXP (setsrc, 1), newdest);
3377                   subst_done = true;
3378                 }
3379               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3380               else if ((code == PLUS || code == MULT)
3381                        && GET_CODE (src_op0) == code
3382                        && GET_CODE (XEXP (src_op0, 0)) == code
3383                        && (INTEGRAL_MODE_P (mode)
3384                            || (FLOAT_MODE_P (mode)
3385                                && flag_unsafe_math_optimizations)))
3386                 {
3387                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3388                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3389                   rtx r = XEXP (src_op0, 1);
3390                   rtx s = src_op1;
3391
3392                   /* Split both "((X op Y) op X) op Y" and
3393                      "((X op Y) op Y) op X" as "T op T" where T is
3394                      "X op Y".  */
3395                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3396                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3397                     {
3398                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3399                                               XEXP (src_op0, 0));
3400                       SUBST (XEXP (setsrc, 0), newdest);
3401                       SUBST (XEXP (setsrc, 1), newdest);
3402                       subst_done = true;
3403                     }
3404                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3405                      T is "X op Y".  */
3406                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3407                     {
3408                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3409                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3410                       SUBST (XEXP (setsrc, 0), newdest);
3411                       SUBST (XEXP (setsrc, 1), newdest);
3412                       subst_done = true;
3413                     }
3414                 }
3415             }
3416
3417           if (!subst_done)
3418             {
3419               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3420               SUBST (*split, newdest);
3421             }
3422
3423           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3424
3425           /* recog_for_combine might have added CLOBBERs to newi2pat.
3426              Make sure NEWPAT does not depend on the clobbered regs.  */
3427           if (GET_CODE (newi2pat) == PARALLEL)
3428             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3429               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3430                 {
3431                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3432                   if (reg_overlap_mentioned_p (reg, newpat))
3433                     {
3434                       undo_all ();
3435                       return 0;
3436                     }
3437                 }
3438
3439           /* If the split point was a MULT and we didn't have one before,
3440              don't use one now.  */
3441           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3442             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3443         }
3444     }
3445
3446   /* Check for a case where we loaded from memory in a narrow mode and
3447      then sign extended it, but we need both registers.  In that case,
3448      we have a PARALLEL with both loads from the same memory location.
3449      We can split this into a load from memory followed by a register-register
3450      copy.  This saves at least one insn, more if register allocation can
3451      eliminate the copy.
3452
3453      We cannot do this if the destination of the first assignment is a
3454      condition code register or cc0.  We eliminate this case by making sure
3455      the SET_DEST and SET_SRC have the same mode.
3456
3457      We cannot do this if the destination of the second assignment is
3458      a register that we have already assumed is zero-extended.  Similarly
3459      for a SUBREG of such a register.  */
3460
3461   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3462            && GET_CODE (newpat) == PARALLEL
3463            && XVECLEN (newpat, 0) == 2
3464            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3465            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3466            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3467                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3468            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3469            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3470                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3471            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3472                                    DF_INSN_LUID (i2))
3473            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3474            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3475            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3476                  (REG_P (temp)
3477                   && VEC_index (reg_stat_type, reg_stat,
3478                                 REGNO (temp))->nonzero_bits != 0
3479                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3480                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3481                   && (VEC_index (reg_stat_type, reg_stat,
3482                                  REGNO (temp))->nonzero_bits
3483                       != GET_MODE_MASK (word_mode))))
3484            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3485                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3486                      (REG_P (temp)
3487                       && VEC_index (reg_stat_type, reg_stat,
3488                                     REGNO (temp))->nonzero_bits != 0
3489                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3490                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3491                       && (VEC_index (reg_stat_type, reg_stat,
3492                                      REGNO (temp))->nonzero_bits
3493                           != GET_MODE_MASK (word_mode)))))
3494            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3495                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3496            && ! find_reg_note (i3, REG_UNUSED,
3497                                SET_DEST (XVECEXP (newpat, 0, 0))))
3498     {
3499       rtx ni2dest;
3500
3501       newi2pat = XVECEXP (newpat, 0, 0);
3502       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3503       newpat = XVECEXP (newpat, 0, 1);
3504       SUBST (SET_SRC (newpat),
3505              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3506       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3507
3508       if (i2_code_number >= 0)
3509         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3510
3511       if (insn_code_number >= 0)
3512         swap_i2i3 = 1;
3513     }
3514
3515   /* Similarly, check for a case where we have a PARALLEL of two independent
3516      SETs but we started with three insns.  In this case, we can do the sets
3517      as two separate insns.  This case occurs when some SET allows two
3518      other insns to combine, but the destination of that SET is still live.  */
3519
3520   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3521            && GET_CODE (newpat) == PARALLEL
3522            && XVECLEN (newpat, 0) == 2
3523            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3524            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3525            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3526            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3527            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3528            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3529            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3530                                    DF_INSN_LUID (i2))
3531            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3532                                   XVECEXP (newpat, 0, 0))
3533            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3534                                   XVECEXP (newpat, 0, 1))
3535            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3536                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3537 #ifdef HAVE_cc0
3538            /* We cannot split the parallel into two sets if both sets
3539               reference cc0.  */
3540            && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3541                  && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3542 #endif
3543            )
3544     {
3545       /* Normally, it doesn't matter which of the two is done first,
3546          but it does if one references cc0.  In that case, it has to
3547          be first.  */
3548 #ifdef HAVE_cc0
3549       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3550         {
3551           newi2pat = XVECEXP (newpat, 0, 0);
3552           newpat = XVECEXP (newpat, 0, 1);
3553         }
3554       else
3555 #endif
3556         {
3557           newi2pat = XVECEXP (newpat, 0, 1);
3558           newpat = XVECEXP (newpat, 0, 0);
3559         }
3560
3561       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3562
3563       if (i2_code_number >= 0)
3564         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3565     }
3566
3567   /* If it still isn't recognized, fail and change things back the way they
3568      were.  */
3569   if ((insn_code_number < 0
3570        /* Is the result a reasonable ASM_OPERANDS?  */
3571        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3572     {
3573       undo_all ();
3574       return 0;
3575     }
3576
3577   /* If we had to change another insn, make sure it is valid also.  */
3578   if (undobuf.other_insn)
3579     {
3580       CLEAR_HARD_REG_SET (newpat_used_regs);
3581
3582       other_pat = PATTERN (undobuf.other_insn);
3583       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3584                                              &new_other_notes);
3585
3586       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3587         {
3588           undo_all ();
3589           return 0;
3590         }
3591     }
3592
3593 #ifdef HAVE_cc0
3594   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3595      they are adjacent to each other or not.  */
3596   {
3597     rtx p = prev_nonnote_insn (i3);
3598     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3599         && sets_cc0_p (newi2pat))
3600       {
3601         undo_all ();
3602         return 0;
3603       }
3604   }
3605 #endif
3606
3607   /* Only allow this combination if insn_rtx_costs reports that the
3608      replacement instructions are cheaper than the originals.  */
3609   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3610     {
3611       undo_all ();
3612       return 0;
3613     }
3614
3615   if (MAY_HAVE_DEBUG_INSNS)
3616     {
3617       struct undo *undo;
3618
3619       for (undo = undobuf.undos; undo; undo = undo->next)
3620         if (undo->kind == UNDO_MODE)
3621           {
3622             rtx reg = *undo->where.r;
3623             enum machine_mode new_mode = GET_MODE (reg);
3624             enum machine_mode old_mode = undo->old_contents.m;
3625
3626             /* Temporarily revert mode back.  */
3627             adjust_reg_mode (reg, old_mode);
3628
3629             if (reg == i2dest && i2scratch)
3630               {
3631                 /* If we used i2dest as a scratch register with a
3632                    different mode, substitute it for the original
3633                    i2src while its original mode is temporarily
3634                    restored, and then clear i2scratch so that we don't
3635                    do it again later.  */
3636                 propagate_for_debug (i2, i3, reg, i2src, false);
3637                 i2scratch = false;
3638                 /* Put back the new mode.  */
3639                 adjust_reg_mode (reg, new_mode);
3640               }
3641             else
3642               {
3643                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3644                 rtx first, last;
3645
3646                 if (reg == i2dest)
3647                   {
3648                     first = i2;
3649                     last = i3;
3650                   }
3651                 else
3652                   {
3653                     first = i3;
3654                     last = undobuf.other_insn;
3655                     gcc_assert (last);
3656                   }
3657
3658                 /* We're dealing with a reg that changed mode but not
3659                    meaning, so we want to turn it into a subreg for
3660                    the new mode.  However, because of REG sharing and
3661                    because its mode had already changed, we have to do
3662                    it in two steps.  First, replace any debug uses of
3663                    reg, with its original mode temporarily restored,
3664                    with this copy we have created; then, replace the
3665                    copy with the SUBREG of the original shared reg,
3666                    once again changed to the new mode.  */
3667                 propagate_for_debug (first, last, reg, tempreg, false);
3668                 adjust_reg_mode (reg, new_mode);
3669                 propagate_for_debug (first, last, tempreg,
3670                                      lowpart_subreg (old_mode, reg, new_mode),
3671                                      false);
3672               }
3673           }
3674     }
3675
3676   /* If we will be able to accept this, we have made a
3677      change to the destination of I3.  This requires us to
3678      do a few adjustments.  */
3679
3680   if (changed_i3_dest)
3681     {
3682       PATTERN (i3) = newpat;
3683       adjust_for_new_dest (i3);
3684     }
3685
3686   /* We now know that we can do this combination.  Merge the insns and
3687      update the status of registers and LOG_LINKS.  */
3688
3689   if (undobuf.other_insn)
3690     {
3691       rtx note, next;
3692
3693       PATTERN (undobuf.other_insn) = other_pat;
3694
3695       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3696          are still valid.  Then add any non-duplicate notes added by
3697          recog_for_combine.  */
3698       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3699         {
3700           next = XEXP (note, 1);
3701
3702           if (REG_NOTE_KIND (note) == REG_UNUSED
3703               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3704             remove_note (undobuf.other_insn, note);
3705         }
3706
3707       distribute_notes (new_other_notes, undobuf.other_insn,
3708                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3709     }
3710
3711   if (swap_i2i3)
3712     {
3713       rtx insn;
3714       rtx link;
3715       rtx ni2dest;
3716
3717       /* I3 now uses what used to be its destination and which is now
3718          I2's destination.  This requires us to do a few adjustments.  */
3719       PATTERN (i3) = newpat;
3720       adjust_for_new_dest (i3);
3721
3722       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3723          so we still will.
3724
3725          However, some later insn might be using I2's dest and have
3726          a LOG_LINK pointing at I3.  We must remove this link.
3727          The simplest way to remove the link is to point it at I1,
3728          which we know will be a NOTE.  */
3729
3730       /* newi2pat is usually a SET here; however, recog_for_combine might
3731          have added some clobbers.  */
3732       if (GET_CODE (newi2pat) == PARALLEL)
3733         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3734       else
3735         ni2dest = SET_DEST (newi2pat);
3736
3737       for (insn = NEXT_INSN (i3);
3738            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3739                     || insn != BB_HEAD (this_basic_block->next_bb));
3740            insn = NEXT_INSN (insn))
3741         {
3742           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3743             {
3744               for (link = LOG_LINKS (insn); link;
3745                    link = XEXP (link, 1))
3746                 if (XEXP (link, 0) == i3)
3747                   XEXP (link, 0) = i1;
3748
3749               break;
3750             }
3751         }
3752     }
3753
3754   {
3755     rtx i3notes, i2notes, i1notes = 0;
3756     rtx i3links, i2links, i1links = 0;
3757     rtx midnotes = 0;
3758     unsigned int regno;
3759     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3760        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3761        same as i3dest, in which case newi2pat may be setting i1dest.  */
3762     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3763                    || i2dest_in_i2src || i2dest_in_i1src
3764                    || !i2dest_killed
3765                    ? 0 : i2dest);
3766     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3767                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3768                    || !i1dest_killed
3769                    ? 0 : i1dest);
3770
3771     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3772        clear them.  */
3773     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3774     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3775     if (i1)
3776       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3777
3778     /* Ensure that we do not have something that should not be shared but
3779        occurs multiple times in the new insns.  Check this by first
3780        resetting all the `used' flags and then copying anything is shared.  */
3781
3782     reset_used_flags (i3notes);
3783     reset_used_flags (i2notes);
3784     reset_used_flags (i1notes);
3785     reset_used_flags (newpat);
3786     reset_used_flags (newi2pat);
3787     if (undobuf.other_insn)
3788       reset_used_flags (PATTERN (undobuf.other_insn));
3789
3790     i3notes = copy_rtx_if_shared (i3notes);
3791     i2notes = copy_rtx_if_shared (i2notes);
3792     i1notes = copy_rtx_if_shared (i1notes);
3793     newpat = copy_rtx_if_shared (newpat);
3794     newi2pat = copy_rtx_if_shared (newi2pat);
3795     if (undobuf.other_insn)
3796       reset_used_flags (PATTERN (undobuf.other_insn));
3797
3798     INSN_CODE (i3) = insn_code_number;
3799     PATTERN (i3) = newpat;
3800
3801     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3802       {
3803         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3804
3805         reset_used_flags (call_usage);
3806         call_usage = copy_rtx (call_usage);
3807
3808         if (substed_i2)
3809           replace_rtx (call_usage, i2dest, i2src);
3810
3811         if (substed_i1)
3812           replace_rtx (call_usage, i1dest, i1src);
3813
3814         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3815       }
3816
3817     if (undobuf.other_insn)
3818       INSN_CODE (undobuf.other_insn) = other_code_number;
3819
3820     /* We had one special case above where I2 had more than one set and
3821        we replaced a destination of one of those sets with the destination
3822        of I3.  In that case, we have to update LOG_LINKS of insns later
3823        in this basic block.  Note that this (expensive) case is rare.
3824
3825        Also, in this case, we must pretend that all REG_NOTEs for I2
3826        actually came from I3, so that REG_UNUSED notes from I2 will be
3827        properly handled.  */
3828
3829     if (i3_subst_into_i2)
3830       {
3831         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3832           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3833                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3834               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3835               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3836               && ! find_reg_note (i2, REG_UNUSED,
3837                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3838             for (temp = NEXT_INSN (i2);
3839                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3840                           || BB_HEAD (this_basic_block) != temp);
3841                  temp = NEXT_INSN (temp))
3842               if (temp != i3 && INSN_P (temp))
3843                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3844                   if (XEXP (link, 0) == i2)
3845                     XEXP (link, 0) = i3;
3846
3847         if (i3notes)
3848           {
3849             rtx link = i3notes;
3850             while (XEXP (link, 1))
3851               link = XEXP (link, 1);
3852             XEXP (link, 1) = i2notes;
3853           }
3854         else
3855           i3notes = i2notes;
3856         i2notes = 0;
3857       }
3858
3859     LOG_LINKS (i3) = 0;
3860     REG_NOTES (i3) = 0;
3861     LOG_LINKS (i2) = 0;
3862     REG_NOTES (i2) = 0;
3863
3864     if (newi2pat)
3865       {
3866         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3867           propagate_for_debug (i2, i3, i2dest, i2src, false);
3868         INSN_CODE (i2) = i2_code_number;
3869         PATTERN (i2) = newi2pat;
3870       }
3871     else
3872       {
3873         if (MAY_HAVE_DEBUG_INSNS && i2src)
3874           propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3875         SET_INSN_DELETED (i2);
3876       }
3877
3878     if (i1)
3879       {
3880         LOG_LINKS (i1) = 0;
3881         REG_NOTES (i1) = 0;
3882         if (MAY_HAVE_DEBUG_INSNS)
3883           propagate_for_debug (i1, i3, i1dest, i1src, false);
3884         SET_INSN_DELETED (i1);
3885       }
3886
3887     /* Get death notes for everything that is now used in either I3 or
3888        I2 and used to die in a previous insn.  If we built two new
3889        patterns, move from I1 to I2 then I2 to I3 so that we get the
3890        proper movement on registers that I2 modifies.  */
3891
3892     if (newi2pat)
3893       {
3894         move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3895         move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3896       }
3897     else
3898       move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3899                    i3, &midnotes);
3900
3901     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3902     if (i3notes)
3903       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3904                         elim_i2, elim_i1);
3905     if (i2notes)
3906       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3907                         elim_i2, elim_i1);
3908     if (i1notes)
3909       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3910                         elim_i2, elim_i1);
3911     if (midnotes)
3912       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3913                         elim_i2, elim_i1);
3914
3915     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3916        know these are REG_UNUSED and want them to go to the desired insn,
3917        so we always pass it as i3.  */
3918
3919     if (newi2pat && new_i2_notes)
3920       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3921
3922     if (new_i3_notes)
3923       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3924
3925     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3926        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3927        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3928        in that case, it might delete I2.  Similarly for I2 and I1.
3929        Show an additional death due to the REG_DEAD note we make here.  If
3930        we discard it in distribute_notes, we will decrement it again.  */
3931
3932     if (i3dest_killed)
3933       {
3934         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3935           distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3936                                             NULL_RTX),
3937                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3938         else
3939           distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3940                                             NULL_RTX),
3941                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3942                             elim_i2, elim_i1);
3943       }
3944
3945     if (i2dest_in_i2src)
3946       {
3947         if (newi2pat && reg_set_p (i2dest, newi2pat))
3948           distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3949                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3950         else
3951           distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3952                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3953                             NULL_RTX, NULL_RTX);
3954       }
3955
3956     if (i1dest_in_i1src)
3957       {
3958         if (newi2pat && reg_set_p (i1dest, newi2pat))
3959           distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3960                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3961         else
3962           distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3963                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3964                             NULL_RTX, NULL_RTX);
3965       }
3966
3967     distribute_links (i3links);
3968     distribute_links (i2links);
3969     distribute_links (i1links);
3970
3971     if (REG_P (i2dest))
3972       {
3973         rtx link;
3974         rtx i2_insn = 0, i2_val = 0, set;
3975
3976         /* The insn that used to set this register doesn't exist, and
3977            this life of the register may not exist either.  See if one of
3978            I3's links points to an insn that sets I2DEST.  If it does,
3979            that is now the last known value for I2DEST. If we don't update
3980            this and I2 set the register to a value that depended on its old
3981            contents, we will get confused.  If this insn is used, thing
3982            will be set correctly in combine_instructions.  */
3983
3984         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3985           if ((set = single_set (XEXP (link, 0))) != 0
3986               && rtx_equal_p (i2dest, SET_DEST (set)))
3987             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3988
3989         record_value_for_reg (i2dest, i2_insn, i2_val);
3990
3991         /* If the reg formerly set in I2 died only once and that was in I3,
3992            zero its use count so it won't make `reload' do any work.  */
3993         if (! added_sets_2
3994             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3995             && ! i2dest_in_i2src)
3996           {
3997             regno = REGNO (i2dest);
3998             INC_REG_N_SETS (regno, -1);
3999           }
4000       }
4001
4002     if (i1 && REG_P (i1dest))
4003       {
4004         rtx link;
4005         rtx i1_insn = 0, i1_val = 0, set;
4006
4007         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4008           if ((set = single_set (XEXP (link, 0))) != 0
4009               && rtx_equal_p (i1dest, SET_DEST (set)))
4010             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
4011
4012         record_value_for_reg (i1dest, i1_insn, i1_val);
4013
4014         regno = REGNO (i1dest);
4015         if (! added_sets_1 && ! i1dest_in_i1src)
4016           INC_REG_N_SETS (regno, -1);
4017       }
4018
4019     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4020        been made to this insn.  The order of
4021        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
4022        can affect nonzero_bits of newpat */
4023     if (newi2pat)
4024       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4025     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4026   }
4027
4028   if (undobuf.other_insn != NULL_RTX)
4029     {
4030       if (dump_file)
4031         {
4032           fprintf (dump_file, "modifying other_insn ");
4033           dump_insn_slim (dump_file, undobuf.other_insn);
4034         }
4035       df_insn_rescan (undobuf.other_insn);
4036     }
4037
4038   if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4039     {
4040       if (dump_file)
4041         {
4042           fprintf (dump_file, "modifying insn i1 ");
4043           dump_insn_slim (dump_file, i1);
4044         }
4045       df_insn_rescan (i1);
4046     }
4047
4048   if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4049     {
4050       if (dump_file)
4051         {
4052           fprintf (dump_file, "modifying insn i2 ");
4053           dump_insn_slim (dump_file, i2);
4054         }
4055       df_insn_rescan (i2);
4056     }
4057
4058   if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4059     {
4060       if (dump_file)
4061         {
4062           fprintf (dump_file, "modifying insn i3 ");
4063           dump_insn_slim (dump_file, i3);
4064         }
4065       df_insn_rescan (i3);
4066     }
4067
4068   /* Set new_direct_jump_p if a new return or simple jump instruction
4069      has been created.  Adjust the CFG accordingly.  */
4070
4071   if (returnjump_p (i3) || any_uncondjump_p (i3))
4072     {
4073       *new_direct_jump_p = 1;
4074       mark_jump_label (PATTERN (i3), i3, 0);
4075       update_cfg_for_uncondjump (i3);
4076     }
4077
4078   if (undobuf.other_insn != NULL_RTX
4079       && (returnjump_p (undobuf.other_insn)
4080           || any_uncondjump_p (undobuf.other_insn)))
4081     {
4082       *new_direct_jump_p = 1;
4083       update_cfg_for_uncondjump (undobuf.other_insn);
4084     }
4085
4086   /* A noop might also need cleaning up of CFG, if it comes from the
4087      simplification of a jump.  */
4088   if (GET_CODE (newpat) == SET
4089       && SET_SRC (newpat) == pc_rtx
4090       && SET_DEST (newpat) == pc_rtx)
4091     {
4092       *new_direct_jump_p = 1;
4093       update_cfg_for_uncondjump (i3);
4094     }
4095
4096   combine_successes++;
4097   undo_commit ();
4098
4099   if (added_links_insn
4100       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4101       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4102     return added_links_insn;
4103   else
4104     return newi2pat ? i2 : i3;
4105 }
4106 \f
4107 /* Undo all the modifications recorded in undobuf.  */
4108
4109 static void
4110 undo_all (void)
4111 {
4112   struct undo *undo, *next;
4113
4114   for (undo = undobuf.undos; undo; undo = next)
4115     {
4116       next = undo->next;
4117       switch (undo->kind)
4118         {
4119         case UNDO_RTX:
4120           *undo->where.r = undo->old_contents.r;
4121           break;
4122         case UNDO_INT:
4123           *undo->where.i = undo->old_contents.i;
4124           break;
4125         case UNDO_MODE:
4126           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4127           break;
4128         default:
4129           gcc_unreachable ();
4130         }
4131
4132       undo->next = undobuf.frees;
4133       undobuf.frees = undo;
4134     }
4135
4136   undobuf.undos = 0;
4137 }
4138
4139 /* We've committed to accepting the changes we made.  Move all
4140    of the undos to the free list.  */
4141
4142 static void
4143 undo_commit (void)
4144 {
4145   struct undo *undo, *next;
4146
4147   for (undo = undobuf.undos; undo; undo = next)
4148     {
4149       next = undo->next;
4150       undo->next = undobuf.frees;
4151       undobuf.frees = undo;
4152     }
4153   undobuf.undos = 0;
4154 }
4155 \f
4156 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4157    where we have an arithmetic expression and return that point.  LOC will
4158    be inside INSN.
4159
4160    try_combine will call this function to see if an insn can be split into
4161    two insns.  */
4162
4163 static rtx *
4164 find_split_point (rtx *loc, rtx insn)
4165 {
4166   rtx x = *loc;
4167   enum rtx_code code = GET_CODE (x);
4168   rtx *split;
4169   unsigned HOST_WIDE_INT len = 0;
4170   HOST_WIDE_INT pos = 0;
4171   int unsignedp = 0;
4172   rtx inner = NULL_RTX;
4173
4174   /* First special-case some codes.  */
4175   switch (code)
4176     {
4177     case SUBREG:
4178 #ifdef INSN_SCHEDULING
4179       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4180          point.  */
4181       if (MEM_P (SUBREG_REG (x)))
4182         return loc;
4183 #endif
4184       return find_split_point (&SUBREG_REG (x), insn);
4185
4186     case MEM:
4187 #ifdef HAVE_lo_sum
4188       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4189          using LO_SUM and HIGH.  */
4190       if (GET_CODE (XEXP (x, 0)) == CONST
4191           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4192         {
4193           SUBST (XEXP (x, 0),
4194                  gen_rtx_LO_SUM (Pmode,
4195                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
4196                                  XEXP (x, 0)));
4197           return &XEXP (XEXP (x, 0), 0);
4198         }
4199 #endif
4200
4201       /* If we have a PLUS whose second operand is a constant and the
4202          address is not valid, perhaps will can split it up using
4203          the machine-specific way to split large constants.  We use
4204          the first pseudo-reg (one of the virtual regs) as a placeholder;
4205          it will not remain in the result.  */
4206       if (GET_CODE (XEXP (x, 0)) == PLUS
4207           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4208           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
4209         {
4210           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4211           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4212                                                       XEXP (x, 0)),
4213                                          subst_insn);
4214
4215           /* This should have produced two insns, each of which sets our
4216              placeholder.  If the source of the second is a valid address,
4217              we can make put both sources together and make a split point
4218              in the middle.  */
4219
4220           if (seq
4221               && NEXT_INSN (seq) != NULL_RTX
4222               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4223               && NONJUMP_INSN_P (seq)
4224               && GET_CODE (PATTERN (seq)) == SET
4225               && SET_DEST (PATTERN (seq)) == reg
4226               && ! reg_mentioned_p (reg,
4227                                     SET_SRC (PATTERN (seq)))
4228               && NONJUMP_INSN_P (NEXT_INSN (seq))
4229               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4230               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4231               && memory_address_p (GET_MODE (x),
4232                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
4233             {
4234               rtx src1 = SET_SRC (PATTERN (seq));
4235               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4236
4237               /* Replace the placeholder in SRC2 with SRC1.  If we can
4238                  find where in SRC2 it was placed, that can become our
4239                  split point and we can replace this address with SRC2.
4240                  Just try two obvious places.  */
4241
4242               src2 = replace_rtx (src2, reg, src1);
4243               split = 0;
4244               if (XEXP (src2, 0) == src1)
4245                 split = &XEXP (src2, 0);
4246               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4247                        && XEXP (XEXP (src2, 0), 0) == src1)
4248                 split = &XEXP (XEXP (src2, 0), 0);
4249
4250               if (split)
4251                 {
4252                   SUBST (XEXP (x, 0), src2);
4253                   return split;
4254                 }
4255             }
4256
4257           /* If that didn't work, perhaps the first operand is complex and
4258              needs to be computed separately, so make a split point there.
4259              This will occur on machines that just support REG + CONST
4260              and have a constant moved through some previous computation.  */
4261
4262           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4263                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4264                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4265             return &XEXP (XEXP (x, 0), 0);
4266         }
4267
4268       /* If we have a PLUS whose first operand is complex, try computing it
4269          separately by making a split there.  */
4270       if (GET_CODE (XEXP (x, 0)) == PLUS
4271           && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
4272           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4273           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4274                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4275         return &XEXP (XEXP (x, 0), 0);
4276       break;
4277
4278     case SET:
4279 #ifdef HAVE_cc0
4280       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4281          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4282          we need to put the operand into a register.  So split at that
4283          point.  */
4284
4285       if (SET_DEST (x) == cc0_rtx
4286           && GET_CODE (SET_SRC (x)) != COMPARE
4287           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4288           && !OBJECT_P (SET_SRC (x))
4289           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4290                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4291         return &SET_SRC (x);
4292 #endif
4293
4294       /* See if we can split SET_SRC as it stands.  */
4295       split = find_split_point (&SET_SRC (x), insn);
4296       if (split && split != &SET_SRC (x))
4297         return split;
4298
4299       /* See if we can split SET_DEST as it stands.  */
4300       split = find_split_point (&SET_DEST (x), insn);
4301       if (split && split != &SET_DEST (x))
4302         return split;
4303
4304       /* See if this is a bitfield assignment with everything constant.  If
4305          so, this is an IOR of an AND, so split it into that.  */
4306       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4307           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4308               <= HOST_BITS_PER_WIDE_INT)
4309           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4310           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4311           && CONST_INT_P (SET_SRC (x))
4312           && ((INTVAL (XEXP (SET_DEST (x), 1))
4313                + INTVAL (XEXP (SET_DEST (x), 2)))
4314               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4315           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4316         {
4317           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4318           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4319           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4320           rtx dest = XEXP (SET_DEST (x), 0);
4321           enum machine_mode mode = GET_MODE (dest);
4322           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4323           rtx or_mask;
4324
4325           if (BITS_BIG_ENDIAN)
4326             pos = GET_MODE_BITSIZE (mode) - len - pos;
4327
4328           or_mask = gen_int_mode (src << pos, mode);
4329           if (src == mask)
4330             SUBST (SET_SRC (x),
4331                    simplify_gen_binary (IOR, mode, dest, or_mask));
4332           else
4333             {
4334               rtx negmask = gen_int_mode (~(mask << pos), mode);
4335               SUBST (SET_SRC (x),
4336                      simplify_gen_binary (IOR, mode,
4337                                           simplify_gen_binary (AND, mode,
4338                                                                dest, negmask),
4339                                           or_mask));
4340             }
4341
4342           SUBST (SET_DEST (x), dest);
4343
4344           split = find_split_point (&SET_SRC (x), insn);
4345           if (split && split != &SET_SRC (x))
4346             return split;
4347         }
4348
4349       /* Otherwise, see if this is an operation that we can split into two.
4350          If so, try to split that.  */
4351       code = GET_CODE (SET_SRC (x));
4352
4353       switch (code)
4354         {
4355         case AND:
4356           /* If we are AND'ing with a large constant that is only a single
4357              bit and the result is only being used in a context where we
4358              need to know if it is zero or nonzero, replace it with a bit
4359              extraction.  This will avoid the large constant, which might
4360              have taken more than one insn to make.  If the constant were
4361              not a valid argument to the AND but took only one insn to make,
4362              this is no worse, but if it took more than one insn, it will
4363              be better.  */
4364
4365           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4366               && REG_P (XEXP (SET_SRC (x), 0))
4367               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4368               && REG_P (SET_DEST (x))
4369               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4370               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4371               && XEXP (*split, 0) == SET_DEST (x)
4372               && XEXP (*split, 1) == const0_rtx)
4373             {
4374               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4375                                                 XEXP (SET_SRC (x), 0),
4376                                                 pos, NULL_RTX, 1, 1, 0, 0);
4377               if (extraction != 0)
4378                 {
4379                   SUBST (SET_SRC (x), extraction);
4380                   return find_split_point (loc, insn);
4381                 }
4382             }
4383           break;
4384
4385         case NE:
4386           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4387              is known to be on, this can be converted into a NEG of a shift.  */
4388           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4389               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4390               && 1 <= (pos = exact_log2
4391                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4392                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4393             {
4394               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4395
4396               SUBST (SET_SRC (x),
4397                      gen_rtx_NEG (mode,
4398                                   gen_rtx_LSHIFTRT (mode,
4399                                                     XEXP (SET_SRC (x), 0),
4400                                                     GEN_INT (pos))));
4401
4402               split = find_split_point (&SET_SRC (x), insn);
4403               if (split && split != &SET_SRC (x))
4404                 return split;
4405             }
4406           break;
4407
4408         case SIGN_EXTEND:
4409           inner = XEXP (SET_SRC (x), 0);
4410
4411           /* We can't optimize if either mode is a partial integer
4412              mode as we don't know how many bits are significant
4413              in those modes.  */
4414           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4415               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4416             break;
4417
4418           pos = 0;
4419           len = GET_MODE_BITSIZE (GET_MODE (inner));
4420           unsignedp = 0;
4421           break;
4422
4423         case SIGN_EXTRACT:
4424         case ZERO_EXTRACT:
4425           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4426               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4427             {
4428               inner = XEXP (SET_SRC (x), 0);
4429               len = INTVAL (XEXP (SET_SRC (x), 1));
4430               pos = INTVAL (XEXP (SET_SRC (x), 2));
4431
4432               if (BITS_BIG_ENDIAN)
4433                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4434               unsignedp = (code == ZERO_EXTRACT);
4435             }
4436           break;
4437
4438         default:
4439           break;
4440         }
4441
4442       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4443         {
4444           enum machine_mode mode = GET_MODE (SET_SRC (x));
4445
4446           /* For unsigned, we have a choice of a shift followed by an
4447              AND or two shifts.  Use two shifts for field sizes where the
4448              constant might be too large.  We assume here that we can
4449              always at least get 8-bit constants in an AND insn, which is
4450              true for every current RISC.  */
4451
4452           if (unsignedp && len <= 8)
4453             {
4454               SUBST (SET_SRC (x),
4455                      gen_rtx_AND (mode,
4456                                   gen_rtx_LSHIFTRT
4457                                   (mode, gen_lowpart (mode, inner),
4458                                    GEN_INT (pos)),
4459                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4460
4461               split = find_split_point (&SET_SRC (x), insn);
4462               if (split && split != &SET_SRC (x))
4463                 return split;
4464             }
4465           else
4466             {
4467               SUBST (SET_SRC (x),
4468                      gen_rtx_fmt_ee
4469                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4470                       gen_rtx_ASHIFT (mode,
4471                                       gen_lowpart (mode, inner),
4472                                       GEN_INT (GET_MODE_BITSIZE (mode)
4473                                                - len - pos)),
4474                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4475
4476               split = find_split_point (&SET_SRC (x), insn);
4477               if (split && split != &SET_SRC (x))
4478                 return split;
4479             }
4480         }
4481
4482       /* See if this is a simple operation with a constant as the second
4483          operand.  It might be that this constant is out of range and hence
4484          could be used as a split point.  */
4485       if (BINARY_P (SET_SRC (x))
4486           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4487           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4488               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4489                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4490         return &XEXP (SET_SRC (x), 1);
4491
4492       /* Finally, see if this is a simple operation with its first operand
4493          not in a register.  The operation might require this operand in a
4494          register, so return it as a split point.  We can always do this
4495          because if the first operand were another operation, we would have
4496          already found it as a split point.  */
4497       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4498           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4499         return &XEXP (SET_SRC (x), 0);
4500
4501       return 0;
4502
4503     case AND:
4504     case IOR:
4505       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4506          it is better to write this as (not (ior A B)) so we can split it.
4507          Similarly for IOR.  */
4508       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4509         {
4510           SUBST (*loc,
4511                  gen_rtx_NOT (GET_MODE (x),
4512                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4513                                               GET_MODE (x),
4514                                               XEXP (XEXP (x, 0), 0),
4515                                               XEXP (XEXP (x, 1), 0))));
4516           return find_split_point (loc, insn);
4517         }
4518
4519       /* Many RISC machines have a large set of logical insns.  If the
4520          second operand is a NOT, put it first so we will try to split the
4521          other operand first.  */
4522       if (GET_CODE (XEXP (x, 1)) == NOT)
4523         {
4524           rtx tem = XEXP (x, 0);
4525           SUBST (XEXP (x, 0), XEXP (x, 1));
4526           SUBST (XEXP (x, 1), tem);
4527         }
4528       break;
4529
4530     default:
4531       break;
4532     }
4533
4534   /* Otherwise, select our actions depending on our rtx class.  */
4535   switch (GET_RTX_CLASS (code))
4536     {
4537     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4538     case RTX_TERNARY:
4539       split = find_split_point (&XEXP (x, 2), insn);
4540       if (split)
4541         return split;
4542       /* ... fall through ...  */
4543     case RTX_BIN_ARITH:
4544     case RTX_COMM_ARITH:
4545     case RTX_COMPARE:
4546     case RTX_COMM_COMPARE:
4547       split = find_split_point (&XEXP (x, 1), insn);
4548       if (split)
4549         return split;
4550       /* ... fall through ...  */
4551     case RTX_UNARY:
4552       /* Some machines have (and (shift ...) ...) insns.  If X is not
4553          an AND, but XEXP (X, 0) is, use it as our split point.  */
4554       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4555         return &XEXP (x, 0);
4556
4557       split = find_split_point (&XEXP (x, 0), insn);
4558       if (split)
4559         return split;
4560       return loc;
4561
4562     default:
4563       /* Otherwise, we don't have a split point.  */
4564       return 0;
4565     }
4566 }
4567 \f
4568 /* Throughout X, replace FROM with TO, and return the result.
4569    The result is TO if X is FROM;
4570    otherwise the result is X, but its contents may have been modified.
4571    If they were modified, a record was made in undobuf so that
4572    undo_all will (among other things) return X to its original state.
4573
4574    If the number of changes necessary is too much to record to undo,
4575    the excess changes are not made, so the result is invalid.
4576    The changes already made can still be undone.
4577    undobuf.num_undo is incremented for such changes, so by testing that
4578    the caller can tell whether the result is valid.
4579
4580    `n_occurrences' is incremented each time FROM is replaced.
4581
4582    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4583
4584    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4585    by copying if `n_occurrences' is nonzero.  */
4586
4587 static rtx
4588 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4589 {
4590   enum rtx_code code = GET_CODE (x);
4591   enum machine_mode op0_mode = VOIDmode;
4592   const char *fmt;
4593   int len, i;
4594   rtx new_rtx;
4595
4596 /* Two expressions are equal if they are identical copies of a shared
4597    RTX or if they are both registers with the same register number
4598    and mode.  */
4599
4600 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4601   ((X) == (Y)                                           \
4602    || (REG_P (X) && REG_P (Y)   \
4603        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4604
4605   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4606     {
4607       n_occurrences++;
4608       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4609     }
4610
4611   /* If X and FROM are the same register but different modes, they
4612      will not have been seen as equal above.  However, the log links code
4613      will make a LOG_LINKS entry for that case.  If we do nothing, we
4614      will try to rerecognize our original insn and, when it succeeds,
4615      we will delete the feeding insn, which is incorrect.
4616
4617      So force this insn not to match in this (rare) case.  */
4618   if (! in_dest && code == REG && REG_P (from)
4619       && reg_overlap_mentioned_p (x, from))
4620     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4621
4622   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4623      of which may contain things that can be combined.  */
4624   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4625     return x;
4626
4627   /* It is possible to have a subexpression appear twice in the insn.
4628      Suppose that FROM is a register that appears within TO.
4629      Then, after that subexpression has been scanned once by `subst',
4630      the second time it is scanned, TO may be found.  If we were
4631      to scan TO here, we would find FROM within it and create a
4632      self-referent rtl structure which is completely wrong.  */
4633   if (COMBINE_RTX_EQUAL_P (x, to))
4634     return to;
4635
4636   /* Parallel asm_operands need special attention because all of the
4637      inputs are shared across the arms.  Furthermore, unsharing the
4638      rtl results in recognition failures.  Failure to handle this case
4639      specially can result in circular rtl.
4640
4641      Solve this by doing a normal pass across the first entry of the
4642      parallel, and only processing the SET_DESTs of the subsequent
4643      entries.  Ug.  */
4644
4645   if (code == PARALLEL
4646       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4647       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4648     {
4649       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4650
4651       /* If this substitution failed, this whole thing fails.  */
4652       if (GET_CODE (new_rtx) == CLOBBER
4653           && XEXP (new_rtx, 0) == const0_rtx)
4654         return new_rtx;
4655
4656       SUBST (XVECEXP (x, 0, 0), new_rtx);
4657
4658       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4659         {
4660           rtx dest = SET_DEST (XVECEXP (x, 0, i));
4661
4662           if (!REG_P (dest)
4663               && GET_CODE (dest) != CC0
4664               && GET_CODE (dest) != PC)
4665             {
4666               new_rtx = subst (dest, from, to, 0, unique_copy);
4667
4668               /* If this substitution failed, this whole thing fails.  */
4669               if (GET_CODE (new_rtx) == CLOBBER
4670                   && XEXP (new_rtx, 0) == const0_rtx)
4671                 return new_rtx;
4672
4673               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4674             }
4675         }
4676     }
4677   else
4678     {
4679       len = GET_RTX_LENGTH (code);
4680       fmt = GET_RTX_FORMAT (code);
4681
4682       /* We don't need to process a SET_DEST that is a register, CC0,
4683          or PC, so set up to skip this common case.  All other cases
4684          where we want to suppress replacing something inside a
4685          SET_SRC are handled via the IN_DEST operand.  */
4686       if (code == SET
4687           && (REG_P (SET_DEST (x))
4688               || GET_CODE (SET_DEST (x)) == CC0
4689               || GET_CODE (SET_DEST (x)) == PC))
4690         fmt = "ie";
4691
4692       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4693          constant.  */
4694       if (fmt[0] == 'e')
4695         op0_mode = GET_MODE (XEXP (x, 0));
4696
4697       for (i = 0; i < len; i++)
4698         {
4699           if (fmt[i] == 'E')
4700             {
4701               int j;
4702               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4703                 {
4704                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4705                     {
4706                       new_rtx = (unique_copy && n_occurrences
4707                              ? copy_rtx (to) : to);
4708                       n_occurrences++;
4709                     }
4710                   else
4711                     {
4712                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4713                                    unique_copy);
4714
4715                       /* If this substitution failed, this whole thing
4716                          fails.  */
4717                       if (GET_CODE (new_rtx) == CLOBBER
4718                           && XEXP (new_rtx, 0) == const0_rtx)
4719                         return new_rtx;
4720                     }
4721
4722                   SUBST (XVECEXP (x, i, j), new_rtx);
4723                 }
4724             }
4725           else if (fmt[i] == 'e')
4726             {
4727               /* If this is a register being set, ignore it.  */
4728               new_rtx = XEXP (x, i);
4729               if (in_dest
4730                   && i == 0
4731                   && (((code == SUBREG || code == ZERO_EXTRACT)
4732                        && REG_P (new_rtx))
4733                       || code == STRICT_LOW_PART))
4734                 ;
4735
4736               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4737                 {
4738                   /* In general, don't install a subreg involving two
4739                      modes not tieable.  It can worsen register
4740                      allocation, and can even make invalid reload
4741                      insns, since the reg inside may need to be copied
4742                      from in the outside mode, and that may be invalid
4743                      if it is an fp reg copied in integer mode.
4744
4745                      We allow two exceptions to this: It is valid if
4746                      it is inside another SUBREG and the mode of that
4747                      SUBREG and the mode of the inside of TO is
4748                      tieable and it is valid if X is a SET that copies
4749                      FROM to CC0.  */
4750
4751                   if (GET_CODE (to) == SUBREG
4752                       && ! MODES_TIEABLE_P (GET_MODE (to),
4753                                             GET_MODE (SUBREG_REG (to)))
4754                       && ! (code == SUBREG
4755                             && MODES_TIEABLE_P (GET_MODE (x),
4756                                                 GET_MODE (SUBREG_REG (to))))
4757 #ifdef HAVE_cc0
4758                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4759 #endif
4760                       )
4761                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4762
4763 #ifdef CANNOT_CHANGE_MODE_CLASS
4764                   if (code == SUBREG
4765                       && REG_P (to)
4766                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4767                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4768                                                    GET_MODE (to),
4769                                                    GET_MODE (x)))
4770                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4771 #endif
4772
4773                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4774                   n_occurrences++;
4775                 }
4776               else
4777                 /* If we are in a SET_DEST, suppress most cases unless we
4778                    have gone inside a MEM, in which case we want to
4779                    simplify the address.  We assume here that things that
4780                    are actually part of the destination have their inner
4781                    parts in the first expression.  This is true for SUBREG,
4782                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4783                    things aside from REG and MEM that should appear in a
4784                    SET_DEST.  */
4785                 new_rtx = subst (XEXP (x, i), from, to,
4786                              (((in_dest
4787                                 && (code == SUBREG || code == STRICT_LOW_PART
4788                                     || code == ZERO_EXTRACT))
4789                                || code == SET)
4790                               && i == 0), unique_copy);
4791
4792               /* If we found that we will have to reject this combination,
4793                  indicate that by returning the CLOBBER ourselves, rather than
4794                  an expression containing it.  This will speed things up as
4795                  well as prevent accidents where two CLOBBERs are considered
4796                  to be equal, thus producing an incorrect simplification.  */
4797
4798               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4799                 return new_rtx;
4800
4801               if (GET_CODE (x) == SUBREG
4802                   && (CONST_INT_P (new_rtx)
4803                       || GET_CODE (new_rtx) == CONST_DOUBLE))
4804                 {
4805                   enum machine_mode mode = GET_MODE (x);
4806
4807                   x = simplify_subreg (GET_MODE (x), new_rtx,
4808                                        GET_MODE (SUBREG_REG (x)),
4809                                        SUBREG_BYTE (x));
4810                   if (! x)
4811                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4812                 }
4813               else if (CONST_INT_P (new_rtx)
4814                        && GET_CODE (x) == ZERO_EXTEND)
4815                 {
4816                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4817                                                 new_rtx, GET_MODE (XEXP (x, 0)));
4818                   gcc_assert (x);
4819                 }
4820               else
4821                 SUBST (XEXP (x, i), new_rtx);
4822             }
4823         }
4824     }
4825
4826   /* Check if we are loading something from the constant pool via float
4827      extension; in this case we would undo compress_float_constant
4828      optimization and degenerate constant load to an immediate value.  */
4829   if (GET_CODE (x) == FLOAT_EXTEND
4830       && MEM_P (XEXP (x, 0))
4831       && MEM_READONLY_P (XEXP (x, 0)))
4832     {
4833       rtx tmp = avoid_constant_pool_reference (x);
4834       if (x != tmp)
4835         return x;
4836     }
4837
4838   /* Try to simplify X.  If the simplification changed the code, it is likely
4839      that further simplification will help, so loop, but limit the number
4840      of repetitions that will be performed.  */
4841
4842   for (i = 0; i < 4; i++)
4843     {
4844       /* If X is sufficiently simple, don't bother trying to do anything
4845          with it.  */
4846       if (code != CONST_INT && code != REG && code != CLOBBER)
4847         x = combine_simplify_rtx (x, op0_mode, in_dest);
4848
4849       if (GET_CODE (x) == code)
4850         break;
4851
4852       code = GET_CODE (x);
4853
4854       /* We no longer know the original mode of operand 0 since we
4855          have changed the form of X)  */
4856       op0_mode = VOIDmode;
4857     }
4858
4859   return x;
4860 }
4861 \f
4862 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4863    outer level; call `subst' to simplify recursively.  Return the new
4864    expression.
4865
4866    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4867    if we are inside a SET_DEST.  */
4868
4869 static rtx
4870 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4871 {
4872   enum rtx_code code = GET_CODE (x);
4873   enum machine_mode mode = GET_MODE (x);
4874   rtx temp;
4875   int i;
4876
4877   /* If this is a commutative operation, put a constant last and a complex
4878      expression first.  We don't need to do this for comparisons here.  */
4879   if (COMMUTATIVE_ARITH_P (x)
4880       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4881     {
4882       temp = XEXP (x, 0);
4883       SUBST (XEXP (x, 0), XEXP (x, 1));
4884       SUBST (XEXP (x, 1), temp);
4885     }
4886
4887   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4888      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4889      things.  Check for cases where both arms are testing the same
4890      condition.
4891
4892      Don't do anything if all operands are very simple.  */
4893
4894   if ((BINARY_P (x)
4895        && ((!OBJECT_P (XEXP (x, 0))
4896             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4897                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4898            || (!OBJECT_P (XEXP (x, 1))
4899                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4900                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4901       || (UNARY_P (x)
4902           && (!OBJECT_P (XEXP (x, 0))
4903                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4904                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4905     {
4906       rtx cond, true_rtx, false_rtx;
4907
4908       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4909       if (cond != 0
4910           /* If everything is a comparison, what we have is highly unlikely
4911              to be simpler, so don't use it.  */
4912           && ! (COMPARISON_P (x)
4913                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4914         {
4915           rtx cop1 = const0_rtx;
4916           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4917
4918           if (cond_code == NE && COMPARISON_P (cond))
4919             return x;
4920
4921           /* Simplify the alternative arms; this may collapse the true and
4922              false arms to store-flag values.  Be careful to use copy_rtx
4923              here since true_rtx or false_rtx might share RTL with x as a
4924              result of the if_then_else_cond call above.  */
4925           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4926           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4927
4928           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4929              is unlikely to be simpler.  */
4930           if (general_operand (true_rtx, VOIDmode)
4931               && general_operand (false_rtx, VOIDmode))
4932             {
4933               enum rtx_code reversed;
4934
4935               /* Restarting if we generate a store-flag expression will cause
4936                  us to loop.  Just drop through in this case.  */
4937
4938               /* If the result values are STORE_FLAG_VALUE and zero, we can
4939                  just make the comparison operation.  */
4940               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4941                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4942                                              cond, cop1);
4943               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4944                        && ((reversed = reversed_comparison_code_parts
4945                                         (cond_code, cond, cop1, NULL))
4946                            != UNKNOWN))
4947                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4948                                              cond, cop1);
4949
4950               /* Likewise, we can make the negate of a comparison operation
4951                  if the result values are - STORE_FLAG_VALUE and zero.  */
4952               else if (CONST_INT_P (true_rtx)
4953                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4954                        && false_rtx == const0_rtx)
4955                 x = simplify_gen_unary (NEG, mode,
4956                                         simplify_gen_relational (cond_code,
4957                                                                  mode, VOIDmode,
4958                                                                  cond, cop1),
4959                                         mode);
4960               else if (CONST_INT_P (false_rtx)
4961                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4962                        && true_rtx == const0_rtx
4963                        && ((reversed = reversed_comparison_code_parts
4964                                         (cond_code, cond, cop1, NULL))
4965                            != UNKNOWN))
4966                 x = simplify_gen_unary (NEG, mode,
4967                                         simplify_gen_relational (reversed,
4968                                                                  mode, VOIDmode,
4969                                                                  cond, cop1),
4970                                         mode);
4971               else
4972                 return gen_rtx_IF_THEN_ELSE (mode,
4973                                              simplify_gen_relational (cond_code,
4974                                                                       mode,
4975                                                                       VOIDmode,
4976                                                                       cond,
4977                                                                       cop1),
4978                                              true_rtx, false_rtx);
4979
4980               code = GET_CODE (x);
4981               op0_mode = VOIDmode;
4982             }
4983         }
4984     }
4985
4986   /* Try to fold this expression in case we have constants that weren't
4987      present before.  */
4988   temp = 0;
4989   switch (GET_RTX_CLASS (code))
4990     {
4991     case RTX_UNARY:
4992       if (op0_mode == VOIDmode)
4993         op0_mode = GET_MODE (XEXP (x, 0));
4994       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4995       break;
4996     case RTX_COMPARE:
4997     case RTX_COMM_COMPARE:
4998       {
4999         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5000         if (cmp_mode == VOIDmode)
5001           {
5002             cmp_mode = GET_MODE (XEXP (x, 1));
5003             if (cmp_mode == VOIDmode)
5004               cmp_mode = op0_mode;
5005           }
5006         temp = simplify_relational_operation (code, mode, cmp_mode,
5007                                               XEXP (x, 0), XEXP (x, 1));
5008       }
5009       break;
5010     case RTX_COMM_ARITH:
5011     case RTX_BIN_ARITH:
5012       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5013       break;
5014     case RTX_BITFIELD_OPS:
5015     case RTX_TERNARY:
5016       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5017                                          XEXP (x, 1), XEXP (x, 2));
5018       break;
5019     default:
5020       break;
5021     }
5022
5023   if (temp)
5024     {
5025       x = temp;
5026       code = GET_CODE (temp);
5027       op0_mode = VOIDmode;
5028       mode = GET_MODE (temp);
5029     }
5030
5031   /* First see if we can apply the inverse distributive law.  */
5032   if (code == PLUS || code == MINUS
5033       || code == AND || code == IOR || code == XOR)
5034     {
5035       x = apply_distributive_law (x);
5036       code = GET_CODE (x);
5037       op0_mode = VOIDmode;
5038     }
5039
5040   /* If CODE is an associative operation not otherwise handled, see if we
5041      can associate some operands.  This can win if they are constants or
5042      if they are logically related (i.e. (a & b) & a).  */
5043   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5044        || code == AND || code == IOR || code == XOR
5045        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5046       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5047           || (flag_associative_math && FLOAT_MODE_P (mode))))
5048     {
5049       if (GET_CODE (XEXP (x, 0)) == code)
5050         {
5051           rtx other = XEXP (XEXP (x, 0), 0);
5052           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5053           rtx inner_op1 = XEXP (x, 1);
5054           rtx inner;
5055
5056           /* Make sure we pass the constant operand if any as the second
5057              one if this is a commutative operation.  */
5058           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5059             {
5060               rtx tem = inner_op0;
5061               inner_op0 = inner_op1;
5062               inner_op1 = tem;
5063             }
5064           inner = simplify_binary_operation (code == MINUS ? PLUS
5065                                              : code == DIV ? MULT
5066                                              : code,
5067                                              mode, inner_op0, inner_op1);
5068
5069           /* For commutative operations, try the other pair if that one
5070              didn't simplify.  */
5071           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5072             {
5073               other = XEXP (XEXP (x, 0), 1);
5074               inner = simplify_binary_operation (code, mode,
5075                                                  XEXP (XEXP (x, 0), 0),
5076                                                  XEXP (x, 1));
5077             }
5078
5079           if (inner)
5080             return simplify_gen_binary (code, mode, other, inner);
5081         }
5082     }
5083
5084   /* A little bit of algebraic simplification here.  */
5085   switch (code)
5086     {
5087     case MEM:
5088       /* Ensure that our address has any ASHIFTs converted to MULT in case
5089          address-recognizing predicates are called later.  */
5090       temp = make_compound_operation (XEXP (x, 0), MEM);
5091       SUBST (XEXP (x, 0), temp);
5092       break;
5093
5094     case SUBREG:
5095       if (op0_mode == VOIDmode)
5096         op0_mode = GET_MODE (SUBREG_REG (x));
5097
5098       /* See if this can be moved to simplify_subreg.  */
5099       if (CONSTANT_P (SUBREG_REG (x))
5100           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5101              /* Don't call gen_lowpart if the inner mode
5102                 is VOIDmode and we cannot simplify it, as SUBREG without
5103                 inner mode is invalid.  */
5104           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5105               || gen_lowpart_common (mode, SUBREG_REG (x))))
5106         return gen_lowpart (mode, SUBREG_REG (x));
5107
5108       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5109         break;
5110       {
5111         rtx temp;
5112         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5113                                 SUBREG_BYTE (x));
5114         if (temp)
5115           return temp;
5116       }
5117
5118       /* Don't change the mode of the MEM if that would change the meaning
5119          of the address.  */
5120       if (MEM_P (SUBREG_REG (x))
5121           && (MEM_VOLATILE_P (SUBREG_REG (x))
5122               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5123         return gen_rtx_CLOBBER (mode, const0_rtx);
5124
5125       /* Note that we cannot do any narrowing for non-constants since
5126          we might have been counting on using the fact that some bits were
5127          zero.  We now do this in the SET.  */
5128
5129       break;
5130
5131     case NEG:
5132       temp = expand_compound_operation (XEXP (x, 0));
5133
5134       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5135          replaced by (lshiftrt X C).  This will convert
5136          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5137
5138       if (GET_CODE (temp) == ASHIFTRT
5139           && CONST_INT_P (XEXP (temp, 1))
5140           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5141         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5142                                      INTVAL (XEXP (temp, 1)));
5143
5144       /* If X has only a single bit that might be nonzero, say, bit I, convert
5145          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5146          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5147          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5148          or a SUBREG of one since we'd be making the expression more
5149          complex if it was just a register.  */
5150
5151       if (!REG_P (temp)
5152           && ! (GET_CODE (temp) == SUBREG
5153                 && REG_P (SUBREG_REG (temp)))
5154           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5155         {
5156           rtx temp1 = simplify_shift_const
5157             (NULL_RTX, ASHIFTRT, mode,
5158              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5159                                    GET_MODE_BITSIZE (mode) - 1 - i),
5160              GET_MODE_BITSIZE (mode) - 1 - i);
5161
5162           /* If all we did was surround TEMP with the two shifts, we
5163              haven't improved anything, so don't use it.  Otherwise,
5164              we are better off with TEMP1.  */
5165           if (GET_CODE (temp1) != ASHIFTRT
5166               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5167               || XEXP (XEXP (temp1, 0), 0) != temp)
5168             return temp1;
5169         }
5170       break;
5171
5172     case TRUNCATE:
5173       /* We can't handle truncation to a partial integer mode here
5174          because we don't know the real bitsize of the partial
5175          integer mode.  */
5176       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5177         break;
5178
5179       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5180         SUBST (XEXP (x, 0),
5181                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5182                               GET_MODE_MASK (mode), 0));
5183
5184       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5185          whose value is a comparison can be replaced with a subreg if
5186          STORE_FLAG_VALUE permits.  */
5187       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5188           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5189           && (temp = get_last_value (XEXP (x, 0)))
5190           && COMPARISON_P (temp))
5191         return gen_lowpart (mode, XEXP (x, 0));
5192       break;
5193
5194     case CONST:
5195       /* (const (const X)) can become (const X).  Do it this way rather than
5196          returning the inner CONST since CONST can be shared with a
5197          REG_EQUAL note.  */
5198       if (GET_CODE (XEXP (x, 0)) == CONST)
5199         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5200       break;
5201
5202 #ifdef HAVE_lo_sum
5203     case LO_SUM:
5204       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5205          can add in an offset.  find_split_point will split this address up
5206          again if it doesn't match.  */
5207       if (GET_CODE (XEXP (x, 0)) == HIGH
5208           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5209         return XEXP (x, 1);
5210       break;
5211 #endif
5212
5213     case PLUS:
5214       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5215          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5216          bit-field and can be replaced by either a sign_extend or a
5217          sign_extract.  The `and' may be a zero_extend and the two
5218          <c>, -<c> constants may be reversed.  */
5219       if (GET_CODE (XEXP (x, 0)) == XOR
5220           && CONST_INT_P (XEXP (x, 1))
5221           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5222           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5223           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5224               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5225           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5226           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5227                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5228                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5229                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5230               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5231                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5232                       == (unsigned int) i + 1))))
5233         return simplify_shift_const
5234           (NULL_RTX, ASHIFTRT, mode,
5235            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5236                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5237                                  GET_MODE_BITSIZE (mode) - (i + 1)),
5238            GET_MODE_BITSIZE (mode) - (i + 1));
5239
5240       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5241          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5242          the bitsize of the mode - 1.  This allows simplification of
5243          "a = (b & 8) == 0;"  */
5244       if (XEXP (x, 1) == constm1_rtx
5245           && !REG_P (XEXP (x, 0))
5246           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5247                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5248           && nonzero_bits (XEXP (x, 0), mode) == 1)
5249         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5250            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5251                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5252                                  GET_MODE_BITSIZE (mode) - 1),
5253            GET_MODE_BITSIZE (mode) - 1);
5254
5255       /* If we are adding two things that have no bits in common, convert
5256          the addition into an IOR.  This will often be further simplified,
5257          for example in cases like ((a & 1) + (a & 2)), which can
5258          become a & 3.  */
5259
5260       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5261           && (nonzero_bits (XEXP (x, 0), mode)
5262               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5263         {
5264           /* Try to simplify the expression further.  */
5265           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5266           temp = combine_simplify_rtx (tor, mode, in_dest);
5267
5268           /* If we could, great.  If not, do not go ahead with the IOR
5269              replacement, since PLUS appears in many special purpose
5270              address arithmetic instructions.  */
5271           if (GET_CODE (temp) != CLOBBER && temp != tor)
5272             return temp;
5273         }
5274       break;
5275
5276     case MINUS:
5277       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5278          (and <foo> (const_int pow2-1))  */
5279       if (GET_CODE (XEXP (x, 1)) == AND
5280           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5281           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5282           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5283         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5284                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5285       break;
5286
5287     case MULT:
5288       /* If we have (mult (plus A B) C), apply the distributive law and then
5289          the inverse distributive law to see if things simplify.  This
5290          occurs mostly in addresses, often when unrolling loops.  */
5291
5292       if (GET_CODE (XEXP (x, 0)) == PLUS)
5293         {
5294           rtx result = distribute_and_simplify_rtx (x, 0);
5295           if (result)
5296             return result;
5297         }
5298
5299       /* Try simplify a*(b/c) as (a*b)/c.  */
5300       if (FLOAT_MODE_P (mode) && flag_associative_math
5301           && GET_CODE (XEXP (x, 0)) == DIV)
5302         {
5303           rtx tem = simplify_binary_operation (MULT, mode,
5304                                                XEXP (XEXP (x, 0), 0),
5305                                                XEXP (x, 1));
5306           if (tem)
5307             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5308         }
5309       break;
5310
5311     case UDIV:
5312       /* If this is a divide by a power of two, treat it as a shift if
5313          its first operand is a shift.  */
5314       if (CONST_INT_P (XEXP (x, 1))
5315           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5316           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5317               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5318               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5319               || GET_CODE (XEXP (x, 0)) == ROTATE
5320               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5321         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5322       break;
5323
5324     case EQ:  case NE:
5325     case GT:  case GTU:  case GE:  case GEU:
5326     case LT:  case LTU:  case LE:  case LEU:
5327     case UNEQ:  case LTGT:
5328     case UNGT:  case UNGE:
5329     case UNLT:  case UNLE:
5330     case UNORDERED: case ORDERED:
5331       /* If the first operand is a condition code, we can't do anything
5332          with it.  */
5333       if (GET_CODE (XEXP (x, 0)) == COMPARE
5334           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5335               && ! CC0_P (XEXP (x, 0))))
5336         {
5337           rtx op0 = XEXP (x, 0);
5338           rtx op1 = XEXP (x, 1);
5339           enum rtx_code new_code;
5340
5341           if (GET_CODE (op0) == COMPARE)
5342             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5343
5344           /* Simplify our comparison, if possible.  */
5345           new_code = simplify_comparison (code, &op0, &op1);
5346
5347           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5348              if only the low-order bit is possibly nonzero in X (such as when
5349              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5350              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5351              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5352              (plus X 1).
5353
5354              Remove any ZERO_EXTRACT we made when thinking this was a
5355              comparison.  It may now be simpler to use, e.g., an AND.  If a
5356              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5357              the call to make_compound_operation in the SET case.  */
5358
5359           if (STORE_FLAG_VALUE == 1
5360               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5361               && op1 == const0_rtx
5362               && mode == GET_MODE (op0)
5363               && nonzero_bits (op0, mode) == 1)
5364             return gen_lowpart (mode,
5365                                 expand_compound_operation (op0));
5366
5367           else if (STORE_FLAG_VALUE == 1
5368                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5369                    && op1 == const0_rtx
5370                    && mode == GET_MODE (op0)
5371                    && (num_sign_bit_copies (op0, mode)
5372                        == GET_MODE_BITSIZE (mode)))
5373             {
5374               op0 = expand_compound_operation (op0);
5375               return simplify_gen_unary (NEG, mode,
5376                                          gen_lowpart (mode, op0),
5377                                          mode);
5378             }
5379
5380           else if (STORE_FLAG_VALUE == 1
5381                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5382                    && op1 == const0_rtx
5383                    && mode == GET_MODE (op0)
5384                    && nonzero_bits (op0, mode) == 1)
5385             {
5386               op0 = expand_compound_operation (op0);
5387               return simplify_gen_binary (XOR, mode,
5388                                           gen_lowpart (mode, op0),
5389                                           const1_rtx);
5390             }
5391
5392           else if (STORE_FLAG_VALUE == 1
5393                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5394                    && op1 == const0_rtx
5395                    && mode == GET_MODE (op0)
5396                    && (num_sign_bit_copies (op0, mode)
5397                        == GET_MODE_BITSIZE (mode)))
5398             {
5399               op0 = expand_compound_operation (op0);
5400               return plus_constant (gen_lowpart (mode, op0), 1);
5401             }
5402
5403           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5404              those above.  */
5405           if (STORE_FLAG_VALUE == -1
5406               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5407               && op1 == const0_rtx
5408               && (num_sign_bit_copies (op0, mode)
5409                   == GET_MODE_BITSIZE (mode)))
5410             return gen_lowpart (mode,
5411                                 expand_compound_operation (op0));
5412
5413           else if (STORE_FLAG_VALUE == -1
5414                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5415                    && op1 == const0_rtx
5416                    && mode == GET_MODE (op0)
5417                    && nonzero_bits (op0, mode) == 1)
5418             {
5419               op0 = expand_compound_operation (op0);
5420               return simplify_gen_unary (NEG, mode,
5421                                          gen_lowpart (mode, op0),
5422                                          mode);
5423             }
5424
5425           else if (STORE_FLAG_VALUE == -1
5426                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5427                    && op1 == const0_rtx
5428                    && mode == GET_MODE (op0)
5429                    && (num_sign_bit_copies (op0, mode)
5430                        == GET_MODE_BITSIZE (mode)))
5431             {
5432               op0 = expand_compound_operation (op0);
5433               return simplify_gen_unary (NOT, mode,
5434                                          gen_lowpart (mode, op0),
5435                                          mode);
5436             }
5437
5438           /* If X is 0/1, (eq X 0) is X-1.  */
5439           else if (STORE_FLAG_VALUE == -1
5440                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5441                    && op1 == const0_rtx
5442                    && mode == GET_MODE (op0)
5443                    && nonzero_bits (op0, mode) == 1)
5444             {
5445               op0 = expand_compound_operation (op0);
5446               return plus_constant (gen_lowpart (mode, op0), -1);
5447             }
5448
5449           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5450              one bit that might be nonzero, we can convert (ne x 0) to
5451              (ashift x c) where C puts the bit in the sign bit.  Remove any
5452              AND with STORE_FLAG_VALUE when we are done, since we are only
5453              going to test the sign bit.  */
5454           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5455               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5456               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5457                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5458               && op1 == const0_rtx
5459               && mode == GET_MODE (op0)
5460               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5461             {
5462               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5463                                         expand_compound_operation (op0),
5464                                         GET_MODE_BITSIZE (mode) - 1 - i);
5465               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5466                 return XEXP (x, 0);
5467               else
5468                 return x;
5469             }
5470
5471           /* If the code changed, return a whole new comparison.  */
5472           if (new_code != code)
5473             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5474
5475           /* Otherwise, keep this operation, but maybe change its operands.
5476              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5477           SUBST (XEXP (x, 0), op0);
5478           SUBST (XEXP (x, 1), op1);
5479         }
5480       break;
5481
5482     case IF_THEN_ELSE:
5483       return simplify_if_then_else (x);
5484
5485     case ZERO_EXTRACT:
5486     case SIGN_EXTRACT:
5487     case ZERO_EXTEND:
5488     case SIGN_EXTEND:
5489       /* If we are processing SET_DEST, we are done.  */
5490       if (in_dest)
5491         return x;
5492
5493       return expand_compound_operation (x);
5494
5495     case SET:
5496       return simplify_set (x);
5497
5498     case AND:
5499     case IOR:
5500       return simplify_logical (x);
5501
5502     case ASHIFT:
5503     case LSHIFTRT:
5504     case ASHIFTRT:
5505     case ROTATE:
5506     case ROTATERT:
5507       /* If this is a shift by a constant amount, simplify it.  */
5508       if (CONST_INT_P (XEXP (x, 1)))
5509         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5510                                      INTVAL (XEXP (x, 1)));
5511
5512       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5513         SUBST (XEXP (x, 1),
5514                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5515                               ((HOST_WIDE_INT) 1
5516                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5517                               - 1,
5518                               0));
5519       break;
5520
5521     default:
5522       break;
5523     }
5524
5525   return x;
5526 }
5527 \f
5528 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5529
5530 static rtx
5531 simplify_if_then_else (rtx x)
5532 {
5533   enum machine_mode mode = GET_MODE (x);
5534   rtx cond = XEXP (x, 0);
5535   rtx true_rtx = XEXP (x, 1);
5536   rtx false_rtx = XEXP (x, 2);
5537   enum rtx_code true_code = GET_CODE (cond);
5538   int comparison_p = COMPARISON_P (cond);
5539   rtx temp;
5540   int i;
5541   enum rtx_code false_code;
5542   rtx reversed;
5543
5544   /* Simplify storing of the truth value.  */
5545   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5546     return simplify_gen_relational (true_code, mode, VOIDmode,
5547                                     XEXP (cond, 0), XEXP (cond, 1));
5548
5549   /* Also when the truth value has to be reversed.  */
5550   if (comparison_p
5551       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5552       && (reversed = reversed_comparison (cond, mode)))
5553     return reversed;
5554
5555   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5556      in it is being compared against certain values.  Get the true and false
5557      comparisons and see if that says anything about the value of each arm.  */
5558
5559   if (comparison_p
5560       && ((false_code = reversed_comparison_code (cond, NULL))
5561           != UNKNOWN)
5562       && REG_P (XEXP (cond, 0)))
5563     {
5564       HOST_WIDE_INT nzb;
5565       rtx from = XEXP (cond, 0);
5566       rtx true_val = XEXP (cond, 1);
5567       rtx false_val = true_val;
5568       int swapped = 0;
5569
5570       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5571
5572       if (false_code == EQ)
5573         {
5574           swapped = 1, true_code = EQ, false_code = NE;
5575           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5576         }
5577
5578       /* If we are comparing against zero and the expression being tested has
5579          only a single bit that might be nonzero, that is its value when it is
5580          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5581
5582       if (true_code == EQ && true_val == const0_rtx
5583           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5584         {
5585           false_code = EQ;
5586           false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5587         }
5588       else if (true_code == EQ && true_val == const0_rtx
5589                && (num_sign_bit_copies (from, GET_MODE (from))
5590                    == GET_MODE_BITSIZE (GET_MODE (from))))
5591         {
5592           false_code = EQ;
5593           false_val = constm1_rtx;
5594         }
5595
5596       /* Now simplify an arm if we know the value of the register in the
5597          branch and it is used in the arm.  Be careful due to the potential
5598          of locally-shared RTL.  */
5599
5600       if (reg_mentioned_p (from, true_rtx))
5601         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5602                                       from, true_val),
5603                       pc_rtx, pc_rtx, 0, 0);
5604       if (reg_mentioned_p (from, false_rtx))
5605         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5606                                    from, false_val),
5607                        pc_rtx, pc_rtx, 0, 0);
5608
5609       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5610       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5611
5612       true_rtx = XEXP (x, 1);
5613       false_rtx = XEXP (x, 2);
5614       true_code = GET_CODE (cond);
5615     }
5616
5617   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5618      reversed, do so to avoid needing two sets of patterns for
5619      subtract-and-branch insns.  Similarly if we have a constant in the true
5620      arm, the false arm is the same as the first operand of the comparison, or
5621      the false arm is more complicated than the true arm.  */
5622
5623   if (comparison_p
5624       && reversed_comparison_code (cond, NULL) != UNKNOWN
5625       && (true_rtx == pc_rtx
5626           || (CONSTANT_P (true_rtx)
5627               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5628           || true_rtx == const0_rtx
5629           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5630           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5631               && !OBJECT_P (false_rtx))
5632           || reg_mentioned_p (true_rtx, false_rtx)
5633           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5634     {
5635       true_code = reversed_comparison_code (cond, NULL);
5636       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5637       SUBST (XEXP (x, 1), false_rtx);
5638       SUBST (XEXP (x, 2), true_rtx);
5639
5640       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5641       cond = XEXP (x, 0);
5642
5643       /* It is possible that the conditional has been simplified out.  */
5644       true_code = GET_CODE (cond);
5645       comparison_p = COMPARISON_P (cond);
5646     }
5647
5648   /* If the two arms are identical, we don't need the comparison.  */
5649
5650   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5651     return true_rtx;
5652
5653   /* Convert a == b ? b : a to "a".  */
5654   if (true_code == EQ && ! side_effects_p (cond)
5655       && !HONOR_NANS (mode)
5656       && rtx_equal_p (XEXP (cond, 0), false_rtx)
5657       && rtx_equal_p (XEXP (cond, 1), true_rtx))
5658     return false_rtx;
5659   else if (true_code == NE && ! side_effects_p (cond)
5660            && !HONOR_NANS (mode)
5661            && rtx_equal_p (XEXP (cond, 0), true_rtx)
5662            && rtx_equal_p (XEXP (cond, 1), false_rtx))
5663     return true_rtx;
5664
5665   /* Look for cases where we have (abs x) or (neg (abs X)).  */
5666
5667   if (GET_MODE_CLASS (mode) == MODE_INT
5668       && comparison_p
5669       && XEXP (cond, 1) == const0_rtx
5670       && GET_CODE (false_rtx) == NEG
5671       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5672       && rtx_equal_p (true_rtx, XEXP (cond, 0))
5673       && ! side_effects_p (true_rtx))
5674     switch (true_code)
5675       {
5676       case GT:
5677       case GE:
5678         return simplify_gen_unary (ABS, mode, true_rtx, mode);
5679       case LT:
5680       case LE:
5681         return
5682           simplify_gen_unary (NEG, mode,
5683                               simplify_gen_unary (ABS, mode, true_rtx, mode),
5684                               mode);
5685       default:
5686         break;
5687       }
5688
5689   /* Look for MIN or MAX.  */
5690
5691   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5692       && comparison_p
5693       && rtx_equal_p (XEXP (cond, 0), true_rtx)
5694       && rtx_equal_p (XEXP (cond, 1), false_rtx)
5695       && ! side_effects_p (cond))
5696     switch (true_code)
5697       {
5698       case GE:
5699       case GT:
5700         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5701       case LE:
5702       case LT:
5703         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5704       case GEU:
5705       case GTU:
5706         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5707       case LEU:
5708       case LTU:
5709         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5710       default:
5711         break;
5712       }
5713
5714   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5715      second operand is zero, this can be done as (OP Z (mult COND C2)) where
5716      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5717      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5718      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5719      neither 1 or -1, but it isn't worth checking for.  */
5720
5721   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5722       && comparison_p
5723       && GET_MODE_CLASS (mode) == MODE_INT
5724       && ! side_effects_p (x))
5725     {
5726       rtx t = make_compound_operation (true_rtx, SET);
5727       rtx f = make_compound_operation (false_rtx, SET);
5728       rtx cond_op0 = XEXP (cond, 0);
5729       rtx cond_op1 = XEXP (cond, 1);
5730       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5731       enum machine_mode m = mode;
5732       rtx z = 0, c1 = NULL_RTX;
5733
5734       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5735            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5736            || GET_CODE (t) == ASHIFT
5737            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5738           && rtx_equal_p (XEXP (t, 0), f))
5739         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5740
5741       /* If an identity-zero op is commutative, check whether there
5742          would be a match if we swapped the operands.  */
5743       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5744                 || GET_CODE (t) == XOR)
5745                && rtx_equal_p (XEXP (t, 1), f))
5746         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5747       else if (GET_CODE (t) == SIGN_EXTEND
5748                && (GET_CODE (XEXP (t, 0)) == PLUS
5749                    || GET_CODE (XEXP (t, 0)) == MINUS
5750                    || GET_CODE (XEXP (t, 0)) == IOR
5751                    || GET_CODE (XEXP (t, 0)) == XOR
5752                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5753                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5754                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5755                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5756                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5757                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5758                && (num_sign_bit_copies (f, GET_MODE (f))
5759                    > (unsigned int)
5760                      (GET_MODE_BITSIZE (mode)
5761                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5762         {
5763           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5764           extend_op = SIGN_EXTEND;
5765           m = GET_MODE (XEXP (t, 0));
5766         }
5767       else if (GET_CODE (t) == SIGN_EXTEND
5768                && (GET_CODE (XEXP (t, 0)) == PLUS
5769                    || GET_CODE (XEXP (t, 0)) == IOR
5770                    || GET_CODE (XEXP (t, 0)) == XOR)
5771                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5772                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5773                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5774                && (num_sign_bit_copies (f, GET_MODE (f))
5775                    > (unsigned int)
5776                      (GET_MODE_BITSIZE (mode)
5777                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5778         {
5779           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5780           extend_op = SIGN_EXTEND;
5781           m = GET_MODE (XEXP (t, 0));
5782         }
5783       else if (GET_CODE (t) == ZERO_EXTEND
5784                && (GET_CODE (XEXP (t, 0)) == PLUS
5785                    || GET_CODE (XEXP (t, 0)) == MINUS
5786                    || GET_CODE (XEXP (t, 0)) == IOR
5787                    || GET_CODE (XEXP (t, 0)) == XOR
5788                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5789                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5790                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5791                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5792                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5793                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5794                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5795                && ((nonzero_bits (f, GET_MODE (f))
5796                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5797                    == 0))
5798         {
5799           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5800           extend_op = ZERO_EXTEND;
5801           m = GET_MODE (XEXP (t, 0));
5802         }
5803       else if (GET_CODE (t) == ZERO_EXTEND
5804                && (GET_CODE (XEXP (t, 0)) == PLUS
5805                    || GET_CODE (XEXP (t, 0)) == IOR
5806                    || GET_CODE (XEXP (t, 0)) == XOR)
5807                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5808                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5809                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5810                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5811                && ((nonzero_bits (f, GET_MODE (f))
5812                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5813                    == 0))
5814         {
5815           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5816           extend_op = ZERO_EXTEND;
5817           m = GET_MODE (XEXP (t, 0));
5818         }
5819
5820       if (z)
5821         {
5822           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5823                                                  cond_op0, cond_op1),
5824                         pc_rtx, pc_rtx, 0, 0);
5825           temp = simplify_gen_binary (MULT, m, temp,
5826                                       simplify_gen_binary (MULT, m, c1,
5827                                                            const_true_rtx));
5828           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5829           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5830
5831           if (extend_op != UNKNOWN)
5832             temp = simplify_gen_unary (extend_op, mode, temp, m);
5833
5834           return temp;
5835         }
5836     }
5837
5838   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5839      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5840      negation of a single bit, we can convert this operation to a shift.  We
5841      can actually do this more generally, but it doesn't seem worth it.  */
5842
5843   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5844       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5845       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5846            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5847           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5848                == GET_MODE_BITSIZE (mode))
5849               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5850     return
5851       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5852                             gen_lowpart (mode, XEXP (cond, 0)), i);
5853
5854   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5855   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5856       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5857       && GET_MODE (XEXP (cond, 0)) == mode
5858       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5859           == nonzero_bits (XEXP (cond, 0), mode)
5860       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5861     return XEXP (cond, 0);
5862
5863   return x;
5864 }
5865 \f
5866 /* Simplify X, a SET expression.  Return the new expression.  */
5867
5868 static rtx
5869 simplify_set (rtx x)
5870 {
5871   rtx src = SET_SRC (x);
5872   rtx dest = SET_DEST (x);
5873   enum machine_mode mode
5874     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5875   rtx other_insn;
5876   rtx *cc_use;
5877
5878   /* (set (pc) (return)) gets written as (return).  */
5879   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5880     return src;
5881
5882   /* Now that we know for sure which bits of SRC we are using, see if we can
5883      simplify the expression for the object knowing that we only need the
5884      low-order bits.  */
5885
5886   if (GET_MODE_CLASS (mode) == MODE_INT
5887       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5888     {
5889       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5890       SUBST (SET_SRC (x), src);
5891     }
5892
5893   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5894      the comparison result and try to simplify it unless we already have used
5895      undobuf.other_insn.  */
5896   if ((GET_MODE_CLASS (mode) == MODE_CC
5897        || GET_CODE (src) == COMPARE
5898        || CC0_P (dest))
5899       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5900       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5901       && COMPARISON_P (*cc_use)
5902       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5903     {
5904       enum rtx_code old_code = GET_CODE (*cc_use);
5905       enum rtx_code new_code;
5906       rtx op0, op1, tmp;
5907       int other_changed = 0;
5908       enum machine_mode compare_mode = GET_MODE (dest);
5909
5910       if (GET_CODE (src) == COMPARE)
5911         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5912       else
5913         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5914
5915       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5916                                            op0, op1);
5917       if (!tmp)
5918         new_code = old_code;
5919       else if (!CONSTANT_P (tmp))
5920         {
5921           new_code = GET_CODE (tmp);
5922           op0 = XEXP (tmp, 0);
5923           op1 = XEXP (tmp, 1);
5924         }
5925       else
5926         {
5927           rtx pat = PATTERN (other_insn);
5928           undobuf.other_insn = other_insn;
5929           SUBST (*cc_use, tmp);
5930
5931           /* Attempt to simplify CC user.  */
5932           if (GET_CODE (pat) == SET)
5933             {
5934               rtx new_rtx = simplify_rtx (SET_SRC (pat));
5935               if (new_rtx != NULL_RTX)
5936                 SUBST (SET_SRC (pat), new_rtx);
5937             }
5938
5939           /* Convert X into a no-op move.  */
5940           SUBST (SET_DEST (x), pc_rtx);
5941           SUBST (SET_SRC (x), pc_rtx);
5942           return x;
5943         }
5944
5945       /* Simplify our comparison, if possible.  */
5946       new_code = simplify_comparison (new_code, &op0, &op1);
5947
5948 #ifdef SELECT_CC_MODE
5949       /* If this machine has CC modes other than CCmode, check to see if we
5950          need to use a different CC mode here.  */
5951       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5952         compare_mode = GET_MODE (op0);
5953       else
5954         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5955
5956 #ifndef HAVE_cc0
5957       /* If the mode changed, we have to change SET_DEST, the mode in the
5958          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5959          a hard register, just build new versions with the proper mode.  If it
5960          is a pseudo, we lose unless it is only time we set the pseudo, in
5961          which case we can safely change its mode.  */
5962       if (compare_mode != GET_MODE (dest))
5963         {
5964           if (can_change_dest_mode (dest, 0, compare_mode))
5965             {
5966               unsigned int regno = REGNO (dest);
5967               rtx new_dest;
5968
5969               if (regno < FIRST_PSEUDO_REGISTER)
5970                 new_dest = gen_rtx_REG (compare_mode, regno);
5971               else
5972                 {
5973                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5974                   new_dest = regno_reg_rtx[regno];
5975                 }
5976
5977               SUBST (SET_DEST (x), new_dest);
5978               SUBST (XEXP (*cc_use, 0), new_dest);
5979               other_changed = 1;
5980
5981               dest = new_dest;
5982             }
5983         }
5984 #endif  /* cc0 */
5985 #endif  /* SELECT_CC_MODE */
5986
5987       /* If the code changed, we have to build a new comparison in
5988          undobuf.other_insn.  */
5989       if (new_code != old_code)
5990         {
5991           int other_changed_previously = other_changed;
5992           unsigned HOST_WIDE_INT mask;
5993           rtx old_cc_use = *cc_use;
5994
5995           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5996                                           dest, const0_rtx));
5997           other_changed = 1;
5998
5999           /* If the only change we made was to change an EQ into an NE or
6000              vice versa, OP0 has only one bit that might be nonzero, and OP1
6001              is zero, check if changing the user of the condition code will
6002              produce a valid insn.  If it won't, we can keep the original code
6003              in that insn by surrounding our operation with an XOR.  */
6004
6005           if (((old_code == NE && new_code == EQ)
6006                || (old_code == EQ && new_code == NE))
6007               && ! other_changed_previously && op1 == const0_rtx
6008               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6009               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6010             {
6011               rtx pat = PATTERN (other_insn), note = 0;
6012
6013               if ((recog_for_combine (&pat, other_insn, &note) < 0
6014                    && ! check_asm_operands (pat)))
6015                 {
6016                   *cc_use = old_cc_use;
6017                   other_changed = 0;
6018
6019                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6020                                              op0, GEN_INT (mask));
6021                 }
6022             }
6023         }
6024
6025       if (other_changed)
6026         undobuf.other_insn = other_insn;
6027
6028       /* Otherwise, if we didn't previously have a COMPARE in the
6029          correct mode, we need one.  */
6030       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6031         {
6032           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6033           src = SET_SRC (x);
6034         }
6035       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6036         {
6037           SUBST (SET_SRC (x), op0);
6038           src = SET_SRC (x);
6039         }
6040       /* Otherwise, update the COMPARE if needed.  */
6041       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6042         {
6043           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6044           src = SET_SRC (x);
6045         }
6046     }
6047   else
6048     {
6049       /* Get SET_SRC in a form where we have placed back any
6050          compound expressions.  Then do the checks below.  */
6051       src = make_compound_operation (src, SET);
6052       SUBST (SET_SRC (x), src);
6053     }
6054
6055   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6056      and X being a REG or (subreg (reg)), we may be able to convert this to
6057      (set (subreg:m2 x) (op)).
6058
6059      We can always do this if M1 is narrower than M2 because that means that
6060      we only care about the low bits of the result.
6061
6062      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6063      perform a narrower operation than requested since the high-order bits will
6064      be undefined.  On machine where it is defined, this transformation is safe
6065      as long as M1 and M2 have the same number of words.  */
6066
6067   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6068       && !OBJECT_P (SUBREG_REG (src))
6069       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6070            / UNITS_PER_WORD)
6071           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6072                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6073 #ifndef WORD_REGISTER_OPERATIONS
6074       && (GET_MODE_SIZE (GET_MODE (src))
6075         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6076 #endif
6077 #ifdef CANNOT_CHANGE_MODE_CLASS
6078       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6079             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6080                                          GET_MODE (SUBREG_REG (src)),
6081                                          GET_MODE (src)))
6082 #endif
6083       && (REG_P (dest)
6084           || (GET_CODE (dest) == SUBREG
6085               && REG_P (SUBREG_REG (dest)))))
6086     {
6087       SUBST (SET_DEST (x),
6088              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6089                                       dest));
6090       SUBST (SET_SRC (x), SUBREG_REG (src));
6091
6092       src = SET_SRC (x), dest = SET_DEST (x);
6093     }
6094
6095 #ifdef HAVE_cc0
6096   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6097      in SRC.  */
6098   if (dest == cc0_rtx
6099       && GET_CODE (src) == SUBREG
6100       && subreg_lowpart_p (src)
6101       && (GET_MODE_BITSIZE (GET_MODE (src))
6102           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6103     {
6104       rtx inner = SUBREG_REG (src);
6105       enum machine_mode inner_mode = GET_MODE (inner);
6106
6107       /* Here we make sure that we don't have a sign bit on.  */
6108       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6109           && (nonzero_bits (inner, inner_mode)
6110               < ((unsigned HOST_WIDE_INT) 1
6111                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6112         {
6113           SUBST (SET_SRC (x), inner);
6114           src = SET_SRC (x);
6115         }
6116     }
6117 #endif
6118
6119 #ifdef LOAD_EXTEND_OP
6120   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6121      would require a paradoxical subreg.  Replace the subreg with a
6122      zero_extend to avoid the reload that would otherwise be required.  */
6123
6124   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6125       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6126       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6127       && SUBREG_BYTE (src) == 0
6128       && (GET_MODE_SIZE (GET_MODE (src))
6129           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6130       && MEM_P (SUBREG_REG (src)))
6131     {
6132       SUBST (SET_SRC (x),
6133              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6134                             GET_MODE (src), SUBREG_REG (src)));
6135
6136       src = SET_SRC (x);
6137     }
6138 #endif
6139
6140   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6141      are comparing an item known to be 0 or -1 against 0, use a logical
6142      operation instead. Check for one of the arms being an IOR of the other
6143      arm with some value.  We compute three terms to be IOR'ed together.  In
6144      practice, at most two will be nonzero.  Then we do the IOR's.  */
6145
6146   if (GET_CODE (dest) != PC
6147       && GET_CODE (src) == IF_THEN_ELSE
6148       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6149       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6150       && XEXP (XEXP (src, 0), 1) == const0_rtx
6151       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6152 #ifdef HAVE_conditional_move
6153       && ! can_conditionally_move_p (GET_MODE (src))
6154 #endif
6155       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6156                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6157           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6158       && ! side_effects_p (src))
6159     {
6160       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6161                       ? XEXP (src, 1) : XEXP (src, 2));
6162       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6163                    ? XEXP (src, 2) : XEXP (src, 1));
6164       rtx term1 = const0_rtx, term2, term3;
6165
6166       if (GET_CODE (true_rtx) == IOR
6167           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6168         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6169       else if (GET_CODE (true_rtx) == IOR
6170                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6171         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6172       else if (GET_CODE (false_rtx) == IOR
6173                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6174         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6175       else if (GET_CODE (false_rtx) == IOR
6176                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6177         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6178
6179       term2 = simplify_gen_binary (AND, GET_MODE (src),
6180                                    XEXP (XEXP (src, 0), 0), true_rtx);
6181       term3 = simplify_gen_binary (AND, GET_MODE (src),
6182                                    simplify_gen_unary (NOT, GET_MODE (src),
6183                                                        XEXP (XEXP (src, 0), 0),
6184                                                        GET_MODE (src)),
6185                                    false_rtx);
6186
6187       SUBST (SET_SRC (x),
6188              simplify_gen_binary (IOR, GET_MODE (src),
6189                                   simplify_gen_binary (IOR, GET_MODE (src),
6190                                                        term1, term2),
6191                                   term3));
6192
6193       src = SET_SRC (x);
6194     }
6195
6196   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6197      whole thing fail.  */
6198   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6199     return src;
6200   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6201     return dest;
6202   else
6203     /* Convert this into a field assignment operation, if possible.  */
6204     return make_field_assignment (x);
6205 }
6206 \f
6207 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6208    result.  */
6209
6210 static rtx
6211 simplify_logical (rtx x)
6212 {
6213   enum machine_mode mode = GET_MODE (x);
6214   rtx op0 = XEXP (x, 0);
6215   rtx op1 = XEXP (x, 1);
6216
6217   switch (GET_CODE (x))
6218     {
6219     case AND:
6220       /* We can call simplify_and_const_int only if we don't lose
6221          any (sign) bits when converting INTVAL (op1) to
6222          "unsigned HOST_WIDE_INT".  */
6223       if (CONST_INT_P (op1)
6224           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6225               || INTVAL (op1) > 0))
6226         {
6227           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6228           if (GET_CODE (x) != AND)
6229             return x;
6230
6231           op0 = XEXP (x, 0);
6232           op1 = XEXP (x, 1);
6233         }
6234
6235       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6236          apply the distributive law and then the inverse distributive
6237          law to see if things simplify.  */
6238       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6239         {
6240           rtx result = distribute_and_simplify_rtx (x, 0);
6241           if (result)
6242             return result;
6243         }
6244       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6245         {
6246           rtx result = distribute_and_simplify_rtx (x, 1);
6247           if (result)
6248             return result;
6249         }
6250       break;
6251
6252     case IOR:
6253       /* If we have (ior (and A B) C), apply the distributive law and then
6254          the inverse distributive law to see if things simplify.  */
6255
6256       if (GET_CODE (op0) == AND)
6257         {
6258           rtx result = distribute_and_simplify_rtx (x, 0);
6259           if (result)
6260             return result;
6261         }
6262
6263       if (GET_CODE (op1) == AND)
6264         {
6265           rtx result = distribute_and_simplify_rtx (x, 1);
6266           if (result)
6267             return result;
6268         }
6269       break;
6270
6271     default:
6272       gcc_unreachable ();
6273     }
6274
6275   return x;
6276 }
6277 \f
6278 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6279    operations" because they can be replaced with two more basic operations.
6280    ZERO_EXTEND is also considered "compound" because it can be replaced with
6281    an AND operation, which is simpler, though only one operation.
6282
6283    The function expand_compound_operation is called with an rtx expression
6284    and will convert it to the appropriate shifts and AND operations,
6285    simplifying at each stage.
6286
6287    The function make_compound_operation is called to convert an expression
6288    consisting of shifts and ANDs into the equivalent compound expression.
6289    It is the inverse of this function, loosely speaking.  */
6290
6291 static rtx
6292 expand_compound_operation (rtx x)
6293 {
6294   unsigned HOST_WIDE_INT pos = 0, len;
6295   int unsignedp = 0;
6296   unsigned int modewidth;
6297   rtx tem;
6298
6299   switch (GET_CODE (x))
6300     {
6301     case ZERO_EXTEND:
6302       unsignedp = 1;
6303     case SIGN_EXTEND:
6304       /* We can't necessarily use a const_int for a multiword mode;
6305          it depends on implicitly extending the value.
6306          Since we don't know the right way to extend it,
6307          we can't tell whether the implicit way is right.
6308
6309          Even for a mode that is no wider than a const_int,
6310          we can't win, because we need to sign extend one of its bits through
6311          the rest of it, and we don't know which bit.  */
6312       if (CONST_INT_P (XEXP (x, 0)))
6313         return x;
6314
6315       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6316          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6317          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6318          reloaded. If not for that, MEM's would very rarely be safe.
6319
6320          Reject MODEs bigger than a word, because we might not be able
6321          to reference a two-register group starting with an arbitrary register
6322          (and currently gen_lowpart might crash for a SUBREG).  */
6323
6324       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6325         return x;
6326
6327       /* Reject MODEs that aren't scalar integers because turning vector
6328          or complex modes into shifts causes problems.  */
6329
6330       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6331         return x;
6332
6333       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6334       /* If the inner object has VOIDmode (the only way this can happen
6335          is if it is an ASM_OPERANDS), we can't do anything since we don't
6336          know how much masking to do.  */
6337       if (len == 0)
6338         return x;
6339
6340       break;
6341
6342     case ZERO_EXTRACT:
6343       unsignedp = 1;
6344
6345       /* ... fall through ...  */
6346
6347     case SIGN_EXTRACT:
6348       /* If the operand is a CLOBBER, just return it.  */
6349       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6350         return XEXP (x, 0);
6351
6352       if (!CONST_INT_P (XEXP (x, 1))
6353           || !CONST_INT_P (XEXP (x, 2))
6354           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6355         return x;
6356
6357       /* Reject MODEs that aren't scalar integers because turning vector
6358          or complex modes into shifts causes problems.  */
6359
6360       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6361         return x;
6362
6363       len = INTVAL (XEXP (x, 1));
6364       pos = INTVAL (XEXP (x, 2));
6365
6366       /* This should stay within the object being extracted, fail otherwise.  */
6367       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6368         return x;
6369
6370       if (BITS_BIG_ENDIAN)
6371         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6372
6373       break;
6374
6375     default:
6376       return x;
6377     }
6378   /* Convert sign extension to zero extension, if we know that the high
6379      bit is not set, as this is easier to optimize.  It will be converted
6380      back to cheaper alternative in make_extraction.  */
6381   if (GET_CODE (x) == SIGN_EXTEND
6382       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6383           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6384                 & ~(((unsigned HOST_WIDE_INT)
6385                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6386                      >> 1))
6387                == 0)))
6388     {
6389       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6390       rtx temp2 = expand_compound_operation (temp);
6391
6392       /* Make sure this is a profitable operation.  */
6393       if (rtx_cost (x, SET, optimize_this_for_speed_p)
6394           > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6395        return temp2;
6396       else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6397                > rtx_cost (temp, SET, optimize_this_for_speed_p))
6398        return temp;
6399       else
6400        return x;
6401     }
6402
6403   /* We can optimize some special cases of ZERO_EXTEND.  */
6404   if (GET_CODE (x) == ZERO_EXTEND)
6405     {
6406       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6407          know that the last value didn't have any inappropriate bits
6408          set.  */
6409       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6410           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6411           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6412           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6413               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6414         return XEXP (XEXP (x, 0), 0);
6415
6416       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6417       if (GET_CODE (XEXP (x, 0)) == SUBREG
6418           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6419           && subreg_lowpart_p (XEXP (x, 0))
6420           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6421           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6422               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6423         return SUBREG_REG (XEXP (x, 0));
6424
6425       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6426          is a comparison and STORE_FLAG_VALUE permits.  This is like
6427          the first case, but it works even when GET_MODE (x) is larger
6428          than HOST_WIDE_INT.  */
6429       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6430           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6431           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6432           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6433               <= HOST_BITS_PER_WIDE_INT)
6434           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6435               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6436         return XEXP (XEXP (x, 0), 0);
6437
6438       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6439       if (GET_CODE (XEXP (x, 0)) == SUBREG
6440           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6441           && subreg_lowpart_p (XEXP (x, 0))
6442           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6443           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6444               <= HOST_BITS_PER_WIDE_INT)
6445           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6446               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6447         return SUBREG_REG (XEXP (x, 0));
6448
6449     }
6450
6451   /* If we reach here, we want to return a pair of shifts.  The inner
6452      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6453      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6454      logical depending on the value of UNSIGNEDP.
6455
6456      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6457      converted into an AND of a shift.
6458
6459      We must check for the case where the left shift would have a negative
6460      count.  This can happen in a case like (x >> 31) & 255 on machines
6461      that can't shift by a constant.  On those machines, we would first
6462      combine the shift with the AND to produce a variable-position
6463      extraction.  Then the constant of 31 would be substituted in to produce
6464      a such a position.  */
6465
6466   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6467   if (modewidth + len >= pos)
6468     {
6469       enum machine_mode mode = GET_MODE (x);
6470       tem = gen_lowpart (mode, XEXP (x, 0));
6471       if (!tem || GET_CODE (tem) == CLOBBER)
6472         return x;
6473       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6474                                   tem, modewidth - pos - len);
6475       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6476                                   mode, tem, modewidth - len);
6477     }
6478   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6479     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6480                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6481                                                         GET_MODE (x),
6482                                                         XEXP (x, 0), pos),
6483                                   ((HOST_WIDE_INT) 1 << len) - 1);
6484   else
6485     /* Any other cases we can't handle.  */
6486     return x;
6487
6488   /* If we couldn't do this for some reason, return the original
6489      expression.  */
6490   if (GET_CODE (tem) == CLOBBER)
6491     return x;
6492
6493   return tem;
6494 }
6495 \f
6496 /* X is a SET which contains an assignment of one object into
6497    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6498    or certain SUBREGS). If possible, convert it into a series of
6499    logical operations.
6500
6501    We half-heartedly support variable positions, but do not at all
6502    support variable lengths.  */
6503
6504 static const_rtx
6505 expand_field_assignment (const_rtx x)
6506 {
6507   rtx inner;
6508   rtx pos;                      /* Always counts from low bit.  */
6509   int len;
6510   rtx mask, cleared, masked;
6511   enum machine_mode compute_mode;
6512
6513   /* Loop until we find something we can't simplify.  */
6514   while (1)
6515     {
6516       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6517           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6518         {
6519           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6520           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6521           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6522         }
6523       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6524                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6525         {
6526           inner = XEXP (SET_DEST (x), 0);
6527           len = INTVAL (XEXP (SET_DEST (x), 1));
6528           pos = XEXP (SET_DEST (x), 2);
6529
6530           /* A constant position should stay within the width of INNER.  */
6531           if (CONST_INT_P (pos)
6532               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6533             break;
6534
6535           if (BITS_BIG_ENDIAN)
6536             {
6537               if (CONST_INT_P (pos))
6538                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6539                                - INTVAL (pos));
6540               else if (GET_CODE (pos) == MINUS
6541                        && CONST_INT_P (XEXP (pos, 1))
6542                        && (INTVAL (XEXP (pos, 1))
6543                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6544                 /* If position is ADJUST - X, new position is X.  */
6545                 pos = XEXP (pos, 0);
6546               else
6547                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6548                                            GEN_INT (GET_MODE_BITSIZE (
6549                                                     GET_MODE (inner))
6550                                                     - len),
6551                                            pos);
6552             }
6553         }
6554
6555       /* A SUBREG between two modes that occupy the same numbers of words
6556          can be done by moving the SUBREG to the source.  */
6557       else if (GET_CODE (SET_DEST (x)) == SUBREG
6558                /* We need SUBREGs to compute nonzero_bits properly.  */
6559                && nonzero_sign_valid
6560                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6561                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6562                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6563                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6564         {
6565           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6566                            gen_lowpart
6567                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6568                             SET_SRC (x)));
6569           continue;
6570         }
6571       else
6572         break;
6573
6574       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6575         inner = SUBREG_REG (inner);
6576
6577       compute_mode = GET_MODE (inner);
6578
6579       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6580       if (! SCALAR_INT_MODE_P (compute_mode))
6581         {
6582           enum machine_mode imode;
6583
6584           /* Don't do anything for vector or complex integral types.  */
6585           if (! FLOAT_MODE_P (compute_mode))
6586             break;
6587
6588           /* Try to find an integral mode to pun with.  */
6589           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6590           if (imode == BLKmode)
6591             break;
6592
6593           compute_mode = imode;
6594           inner = gen_lowpart (imode, inner);
6595         }
6596
6597       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6598       if (len >= HOST_BITS_PER_WIDE_INT)
6599         break;
6600
6601       /* Now compute the equivalent expression.  Make a copy of INNER
6602          for the SET_DEST in case it is a MEM into which we will substitute;
6603          we don't want shared RTL in that case.  */
6604       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6605       cleared = simplify_gen_binary (AND, compute_mode,
6606                                      simplify_gen_unary (NOT, compute_mode,
6607                                        simplify_gen_binary (ASHIFT,
6608                                                             compute_mode,
6609                                                             mask, pos),
6610                                        compute_mode),
6611                                      inner);
6612       masked = simplify_gen_binary (ASHIFT, compute_mode,
6613                                     simplify_gen_binary (
6614                                       AND, compute_mode,
6615                                       gen_lowpart (compute_mode, SET_SRC (x)),
6616                                       mask),
6617                                     pos);
6618
6619       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6620                        simplify_gen_binary (IOR, compute_mode,
6621                                             cleared, masked));
6622     }
6623
6624   return x;
6625 }
6626 \f
6627 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
6628    it is an RTX that represents a variable starting position; otherwise,
6629    POS is the (constant) starting bit position (counted from the LSB).
6630
6631    UNSIGNEDP is nonzero for an unsigned reference and zero for a
6632    signed reference.
6633
6634    IN_DEST is nonzero if this is a reference in the destination of a
6635    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
6636    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6637    be used.
6638
6639    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
6640    ZERO_EXTRACT should be built even for bits starting at bit 0.
6641
6642    MODE is the desired mode of the result (if IN_DEST == 0).
6643
6644    The result is an RTX for the extraction or NULL_RTX if the target
6645    can't handle it.  */
6646
6647 static rtx
6648 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6649                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6650                  int in_dest, int in_compare)
6651 {
6652   /* This mode describes the size of the storage area
6653      to fetch the overall value from.  Within that, we
6654      ignore the POS lowest bits, etc.  */
6655   enum machine_mode is_mode = GET_MODE (inner);
6656   enum machine_mode inner_mode;
6657   enum machine_mode wanted_inner_mode;
6658   enum machine_mode wanted_inner_reg_mode = word_mode;
6659   enum machine_mode pos_mode = word_mode;
6660   enum machine_mode extraction_mode = word_mode;
6661   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6662   rtx new_rtx = 0;
6663   rtx orig_pos_rtx = pos_rtx;
6664   HOST_WIDE_INT orig_pos;
6665
6666   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6667     {
6668       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6669          consider just the QI as the memory to extract from.
6670          The subreg adds or removes high bits; its mode is
6671          irrelevant to the meaning of this extraction,
6672          since POS and LEN count from the lsb.  */
6673       if (MEM_P (SUBREG_REG (inner)))
6674         is_mode = GET_MODE (SUBREG_REG (inner));
6675       inner = SUBREG_REG (inner);
6676     }
6677   else if (GET_CODE (inner) == ASHIFT
6678            && CONST_INT_P (XEXP (inner, 1))
6679            && pos_rtx == 0 && pos == 0
6680            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6681     {
6682       /* We're extracting the least significant bits of an rtx
6683          (ashift X (const_int C)), where LEN > C.  Extract the
6684          least significant (LEN - C) bits of X, giving an rtx
6685          whose mode is MODE, then shift it left C times.  */
6686       new_rtx = make_extraction (mode, XEXP (inner, 0),
6687                              0, 0, len - INTVAL (XEXP (inner, 1)),
6688                              unsignedp, in_dest, in_compare);
6689       if (new_rtx != 0)
6690         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6691     }
6692
6693   inner_mode = GET_MODE (inner);
6694
6695   if (pos_rtx && CONST_INT_P (pos_rtx))
6696     pos = INTVAL (pos_rtx), pos_rtx = 0;
6697
6698   /* See if this can be done without an extraction.  We never can if the
6699      width of the field is not the same as that of some integer mode. For
6700      registers, we can only avoid the extraction if the position is at the
6701      low-order bit and this is either not in the destination or we have the
6702      appropriate STRICT_LOW_PART operation available.
6703
6704      For MEM, we can avoid an extract if the field starts on an appropriate
6705      boundary and we can change the mode of the memory reference.  */
6706
6707   if (tmode != BLKmode
6708       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6709            && !MEM_P (inner)
6710            && (inner_mode == tmode
6711                || !REG_P (inner)
6712                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6713                                          GET_MODE_BITSIZE (inner_mode))
6714                || reg_truncated_to_mode (tmode, inner))
6715            && (! in_dest
6716                || (REG_P (inner)
6717                    && have_insn_for (STRICT_LOW_PART, tmode))))
6718           || (MEM_P (inner) && pos_rtx == 0
6719               && (pos
6720                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6721                      : BITS_PER_UNIT)) == 0
6722               /* We can't do this if we are widening INNER_MODE (it
6723                  may not be aligned, for one thing).  */
6724               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6725               && (inner_mode == tmode
6726                   || (! mode_dependent_address_p (XEXP (inner, 0))
6727                       && ! MEM_VOLATILE_P (inner))))))
6728     {
6729       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6730          field.  If the original and current mode are the same, we need not
6731          adjust the offset.  Otherwise, we do if bytes big endian.
6732
6733          If INNER is not a MEM, get a piece consisting of just the field
6734          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6735
6736       if (MEM_P (inner))
6737         {
6738           HOST_WIDE_INT offset;
6739
6740           /* POS counts from lsb, but make OFFSET count in memory order.  */
6741           if (BYTES_BIG_ENDIAN)
6742             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6743           else
6744             offset = pos / BITS_PER_UNIT;
6745
6746           new_rtx = adjust_address_nv (inner, tmode, offset);
6747         }
6748       else if (REG_P (inner))
6749         {
6750           if (tmode != inner_mode)
6751             {
6752               /* We can't call gen_lowpart in a DEST since we
6753                  always want a SUBREG (see below) and it would sometimes
6754                  return a new hard register.  */
6755               if (pos || in_dest)
6756                 {
6757                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6758
6759                   if (WORDS_BIG_ENDIAN
6760                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6761                     final_word = ((GET_MODE_SIZE (inner_mode)
6762                                    - GET_MODE_SIZE (tmode))
6763                                   / UNITS_PER_WORD) - final_word;
6764
6765                   final_word *= UNITS_PER_WORD;
6766                   if (BYTES_BIG_ENDIAN &&
6767                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6768                     final_word += (GET_MODE_SIZE (inner_mode)
6769                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6770
6771                   /* Avoid creating invalid subregs, for example when
6772                      simplifying (x>>32)&255.  */
6773                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6774                     return NULL_RTX;
6775
6776                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6777                 }
6778               else
6779                 new_rtx = gen_lowpart (tmode, inner);
6780             }
6781           else
6782             new_rtx = inner;
6783         }
6784       else
6785         new_rtx = force_to_mode (inner, tmode,
6786                              len >= HOST_BITS_PER_WIDE_INT
6787                              ? ~(unsigned HOST_WIDE_INT) 0
6788                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6789                              0);
6790
6791       /* If this extraction is going into the destination of a SET,
6792          make a STRICT_LOW_PART unless we made a MEM.  */
6793
6794       if (in_dest)
6795         return (MEM_P (new_rtx) ? new_rtx
6796                 : (GET_CODE (new_rtx) != SUBREG
6797                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6798                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6799
6800       if (mode == tmode)
6801         return new_rtx;
6802
6803       if (CONST_INT_P (new_rtx))
6804         return gen_int_mode (INTVAL (new_rtx), mode);
6805
6806       /* If we know that no extraneous bits are set, and that the high
6807          bit is not set, convert the extraction to the cheaper of
6808          sign and zero extension, that are equivalent in these cases.  */
6809       if (flag_expensive_optimizations
6810           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6811               && ((nonzero_bits (new_rtx, tmode)
6812                    & ~(((unsigned HOST_WIDE_INT)
6813                         GET_MODE_MASK (tmode))
6814                        >> 1))
6815                   == 0)))
6816         {
6817           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6818           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6819
6820           /* Prefer ZERO_EXTENSION, since it gives more information to
6821              backends.  */
6822           if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6823               <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6824             return temp;
6825           return temp1;
6826         }
6827
6828       /* Otherwise, sign- or zero-extend unless we already are in the
6829          proper mode.  */
6830
6831       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6832                              mode, new_rtx));
6833     }
6834
6835   /* Unless this is a COMPARE or we have a funny memory reference,
6836      don't do anything with zero-extending field extracts starting at
6837      the low-order bit since they are simple AND operations.  */
6838   if (pos_rtx == 0 && pos == 0 && ! in_dest
6839       && ! in_compare && unsignedp)
6840     return 0;
6841
6842   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6843      if the position is not a constant and the length is not 1.  In all
6844      other cases, we would only be going outside our object in cases when
6845      an original shift would have been undefined.  */
6846   if (MEM_P (inner)
6847       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6848           || (pos_rtx != 0 && len != 1)))
6849     return 0;
6850
6851   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6852      and the mode for the result.  */
6853   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6854     {
6855       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6856       pos_mode = mode_for_extraction (EP_insv, 2);
6857       extraction_mode = mode_for_extraction (EP_insv, 3);
6858     }
6859
6860   if (! in_dest && unsignedp
6861       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6862     {
6863       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6864       pos_mode = mode_for_extraction (EP_extzv, 3);
6865       extraction_mode = mode_for_extraction (EP_extzv, 0);
6866     }
6867
6868   if (! in_dest && ! unsignedp
6869       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6870     {
6871       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6872       pos_mode = mode_for_extraction (EP_extv, 3);
6873       extraction_mode = mode_for_extraction (EP_extv, 0);
6874     }
6875
6876   /* Never narrow an object, since that might not be safe.  */
6877
6878   if (mode != VOIDmode
6879       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6880     extraction_mode = mode;
6881
6882   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6883       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6884     pos_mode = GET_MODE (pos_rtx);
6885
6886   /* If this is not from memory, the desired mode is the preferred mode
6887      for an extraction pattern's first input operand, or word_mode if there
6888      is none.  */
6889   if (!MEM_P (inner))
6890     wanted_inner_mode = wanted_inner_reg_mode;
6891   else
6892     {
6893       /* Be careful not to go beyond the extracted object and maintain the
6894          natural alignment of the memory.  */
6895       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6896       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6897              > GET_MODE_BITSIZE (wanted_inner_mode))
6898         {
6899           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6900           gcc_assert (wanted_inner_mode != VOIDmode);
6901         }
6902
6903       /* If we have to change the mode of memory and cannot, the desired mode
6904          is EXTRACTION_MODE.  */
6905       if (inner_mode != wanted_inner_mode
6906           && (mode_dependent_address_p (XEXP (inner, 0))
6907               || MEM_VOLATILE_P (inner)
6908               || pos_rtx))
6909         wanted_inner_mode = extraction_mode;
6910     }
6911
6912   orig_pos = pos;
6913
6914   if (BITS_BIG_ENDIAN)
6915     {
6916       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6917          BITS_BIG_ENDIAN style.  If position is constant, compute new
6918          position.  Otherwise, build subtraction.
6919          Note that POS is relative to the mode of the original argument.
6920          If it's a MEM we need to recompute POS relative to that.
6921          However, if we're extracting from (or inserting into) a register,
6922          we want to recompute POS relative to wanted_inner_mode.  */
6923       int width = (MEM_P (inner)
6924                    ? GET_MODE_BITSIZE (is_mode)
6925                    : GET_MODE_BITSIZE (wanted_inner_mode));
6926
6927       if (pos_rtx == 0)
6928         pos = width - len - pos;
6929       else
6930         pos_rtx
6931           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6932       /* POS may be less than 0 now, but we check for that below.
6933          Note that it can only be less than 0 if !MEM_P (inner).  */
6934     }
6935
6936   /* If INNER has a wider mode, and this is a constant extraction, try to
6937      make it smaller and adjust the byte to point to the byte containing
6938      the value.  */
6939   if (wanted_inner_mode != VOIDmode
6940       && inner_mode != wanted_inner_mode
6941       && ! pos_rtx
6942       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6943       && MEM_P (inner)
6944       && ! mode_dependent_address_p (XEXP (inner, 0))
6945       && ! MEM_VOLATILE_P (inner))
6946     {
6947       int offset = 0;
6948
6949       /* The computations below will be correct if the machine is big
6950          endian in both bits and bytes or little endian in bits and bytes.
6951          If it is mixed, we must adjust.  */
6952
6953       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6954          adjust OFFSET to compensate.  */
6955       if (BYTES_BIG_ENDIAN
6956           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6957         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6958
6959       /* We can now move to the desired byte.  */
6960       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6961                 * GET_MODE_SIZE (wanted_inner_mode);
6962       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6963
6964       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6965           && is_mode != wanted_inner_mode)
6966         offset = (GET_MODE_SIZE (is_mode)
6967                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6968
6969       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6970     }
6971
6972   /* If INNER is not memory, get it into the proper mode.  If we are changing
6973      its mode, POS must be a constant and smaller than the size of the new
6974      mode.  */
6975   else if (!MEM_P (inner))
6976     {
6977       /* On the LHS, don't create paradoxical subregs implicitely truncating
6978          the register unless TRULY_NOOP_TRUNCATION.  */
6979       if (in_dest
6980           && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6981                                      GET_MODE_BITSIZE (wanted_inner_mode)))
6982         return NULL_RTX;
6983
6984       if (GET_MODE (inner) != wanted_inner_mode
6985           && (pos_rtx != 0
6986               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6987         return NULL_RTX;
6988
6989       if (orig_pos < 0)
6990         return NULL_RTX;
6991
6992       inner = force_to_mode (inner, wanted_inner_mode,
6993                              pos_rtx
6994                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6995                              ? ~(unsigned HOST_WIDE_INT) 0
6996                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6997                                 << orig_pos),
6998                              0);
6999     }
7000
7001   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7002      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7003   if (pos_rtx != 0
7004       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7005     {
7006       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7007
7008       /* If we know that no extraneous bits are set, and that the high
7009          bit is not set, convert extraction to cheaper one - either
7010          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7011          cases.  */
7012       if (flag_expensive_optimizations
7013           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7014               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7015                    & ~(((unsigned HOST_WIDE_INT)
7016                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7017                        >> 1))
7018                   == 0)))
7019         {
7020           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7021
7022           /* Prefer ZERO_EXTENSION, since it gives more information to
7023              backends.  */
7024           if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7025               < rtx_cost (temp, SET, optimize_this_for_speed_p))
7026             temp = temp1;
7027         }
7028       pos_rtx = temp;
7029     }
7030   else if (pos_rtx != 0
7031            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7032     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7033
7034   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7035      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7036      be a CONST_INT.  */
7037   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7038     pos_rtx = orig_pos_rtx;
7039
7040   else if (pos_rtx == 0)
7041     pos_rtx = GEN_INT (pos);
7042
7043   /* Make the required operation.  See if we can use existing rtx.  */
7044   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7045                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7046   if (! in_dest)
7047     new_rtx = gen_lowpart (mode, new_rtx);
7048
7049   return new_rtx;
7050 }
7051 \f
7052 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7053    with any other operations in X.  Return X without that shift if so.  */
7054
7055 static rtx
7056 extract_left_shift (rtx x, int count)
7057 {
7058   enum rtx_code code = GET_CODE (x);
7059   enum machine_mode mode = GET_MODE (x);
7060   rtx tem;
7061
7062   switch (code)
7063     {
7064     case ASHIFT:
7065       /* This is the shift itself.  If it is wide enough, we will return
7066          either the value being shifted if the shift count is equal to
7067          COUNT or a shift for the difference.  */
7068       if (CONST_INT_P (XEXP (x, 1))
7069           && INTVAL (XEXP (x, 1)) >= count)
7070         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7071                                      INTVAL (XEXP (x, 1)) - count);
7072       break;
7073
7074     case NEG:  case NOT:
7075       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7076         return simplify_gen_unary (code, mode, tem, mode);
7077
7078       break;
7079
7080     case PLUS:  case IOR:  case XOR:  case AND:
7081       /* If we can safely shift this constant and we find the inner shift,
7082          make a new operation.  */
7083       if (CONST_INT_P (XEXP (x, 1))
7084           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7085           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7086         return simplify_gen_binary (code, mode, tem,
7087                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7088
7089       break;
7090
7091     default:
7092       break;
7093     }
7094
7095   return 0;
7096 }
7097 \f
7098 /* Look at the expression rooted at X.  Look for expressions
7099    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7100    Form these expressions.
7101
7102    Return the new rtx, usually just X.
7103
7104    Also, for machines like the VAX that don't have logical shift insns,
7105    try to convert logical to arithmetic shift operations in cases where
7106    they are equivalent.  This undoes the canonicalizations to logical
7107    shifts done elsewhere.
7108
7109    We try, as much as possible, to re-use rtl expressions to save memory.
7110
7111    IN_CODE says what kind of expression we are processing.  Normally, it is
7112    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7113    being kludges), it is MEM.  When processing the arguments of a comparison
7114    or a COMPARE against zero, it is COMPARE.  */
7115
7116 static rtx
7117 make_compound_operation (rtx x, enum rtx_code in_code)
7118 {
7119   enum rtx_code code = GET_CODE (x);
7120   enum machine_mode mode = GET_MODE (x);
7121   int mode_width = GET_MODE_BITSIZE (mode);
7122   rtx rhs, lhs;
7123   enum rtx_code next_code;
7124   int i, j;
7125   rtx new_rtx = 0;
7126   rtx tem;
7127   const char *fmt;
7128
7129   /* Select the code to be used in recursive calls.  Once we are inside an
7130      address, we stay there.  If we have a comparison, set to COMPARE,
7131      but once inside, go back to our default of SET.  */
7132
7133   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7134                : ((code == COMPARE || COMPARISON_P (x))
7135                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7136                : in_code == COMPARE ? SET : in_code);
7137
7138   /* Process depending on the code of this operation.  If NEW is set
7139      nonzero, it will be returned.  */
7140
7141   switch (code)
7142     {
7143     case ASHIFT:
7144       /* Convert shifts by constants into multiplications if inside
7145          an address.  */
7146       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7147           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7148           && INTVAL (XEXP (x, 1)) >= 0)
7149         {
7150           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7151           new_rtx = gen_rtx_MULT (mode, new_rtx,
7152                               GEN_INT ((HOST_WIDE_INT) 1
7153                                        << INTVAL (XEXP (x, 1))));
7154         }
7155       break;
7156
7157     case AND:
7158       /* If the second operand is not a constant, we can't do anything
7159          with it.  */
7160       if (!CONST_INT_P (XEXP (x, 1)))
7161         break;
7162
7163       /* If the constant is a power of two minus one and the first operand
7164          is a logical right shift, make an extraction.  */
7165       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7166           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7167         {
7168           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7169           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7170                                  0, in_code == COMPARE);
7171         }
7172
7173       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7174       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7175                && subreg_lowpart_p (XEXP (x, 0))
7176                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7177                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7178         {
7179           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7180                                          next_code);
7181           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7182                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7183                                  0, in_code == COMPARE);
7184         }
7185       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7186       else if ((GET_CODE (XEXP (x, 0)) == XOR
7187                 || GET_CODE (XEXP (x, 0)) == IOR)
7188                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7189                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7190                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7191         {
7192           /* Apply the distributive law, and then try to make extractions.  */
7193           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7194                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7195                                              XEXP (x, 1)),
7196                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7197                                              XEXP (x, 1)));
7198           new_rtx = make_compound_operation (new_rtx, in_code);
7199         }
7200
7201       /* If we are have (and (rotate X C) M) and C is larger than the number
7202          of bits in M, this is an extraction.  */
7203
7204       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7205                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7206                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7207                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7208         {
7209           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7210           new_rtx = make_extraction (mode, new_rtx,
7211                                  (GET_MODE_BITSIZE (mode)
7212                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7213                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7214         }
7215
7216       /* On machines without logical shifts, if the operand of the AND is
7217          a logical shift and our mask turns off all the propagated sign
7218          bits, we can replace the logical shift with an arithmetic shift.  */
7219       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7220                && !have_insn_for (LSHIFTRT, mode)
7221                && have_insn_for (ASHIFTRT, mode)
7222                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7223                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7224                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7225                && mode_width <= HOST_BITS_PER_WIDE_INT)
7226         {
7227           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7228
7229           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7230           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7231             SUBST (XEXP (x, 0),
7232                    gen_rtx_ASHIFTRT (mode,
7233                                      make_compound_operation
7234                                      (XEXP (XEXP (x, 0), 0), next_code),
7235                                      XEXP (XEXP (x, 0), 1)));
7236         }
7237
7238       /* If the constant is one less than a power of two, this might be
7239          representable by an extraction even if no shift is present.
7240          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7241          we are in a COMPARE.  */
7242       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7243         new_rtx = make_extraction (mode,
7244                                make_compound_operation (XEXP (x, 0),
7245                                                         next_code),
7246                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7247
7248       /* If we are in a comparison and this is an AND with a power of two,
7249          convert this into the appropriate bit extract.  */
7250       else if (in_code == COMPARE
7251                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7252         new_rtx = make_extraction (mode,
7253                                make_compound_operation (XEXP (x, 0),
7254                                                         next_code),
7255                                i, NULL_RTX, 1, 1, 0, 1);
7256
7257       break;
7258
7259     case LSHIFTRT:
7260       /* If the sign bit is known to be zero, replace this with an
7261          arithmetic shift.  */
7262       if (have_insn_for (ASHIFTRT, mode)
7263           && ! have_insn_for (LSHIFTRT, mode)
7264           && mode_width <= HOST_BITS_PER_WIDE_INT
7265           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7266         {
7267           new_rtx = gen_rtx_ASHIFTRT (mode,
7268                                   make_compound_operation (XEXP (x, 0),
7269                                                            next_code),
7270                                   XEXP (x, 1));
7271           break;
7272         }
7273
7274       /* ... fall through ...  */
7275
7276     case ASHIFTRT:
7277       lhs = XEXP (x, 0);
7278       rhs = XEXP (x, 1);
7279
7280       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7281          this is a SIGN_EXTRACT.  */
7282       if (CONST_INT_P (rhs)
7283           && GET_CODE (lhs) == ASHIFT
7284           && CONST_INT_P (XEXP (lhs, 1))
7285           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7286           && INTVAL (rhs) < mode_width)
7287         {
7288           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7289           new_rtx = make_extraction (mode, new_rtx,
7290                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7291                                  NULL_RTX, mode_width - INTVAL (rhs),
7292                                  code == LSHIFTRT, 0, in_code == COMPARE);
7293           break;
7294         }
7295
7296       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7297          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7298          also do this for some cases of SIGN_EXTRACT, but it doesn't
7299          seem worth the effort; the case checked for occurs on Alpha.  */
7300
7301       if (!OBJECT_P (lhs)
7302           && ! (GET_CODE (lhs) == SUBREG
7303                 && (OBJECT_P (SUBREG_REG (lhs))))
7304           && CONST_INT_P (rhs)
7305           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7306           && INTVAL (rhs) < mode_width
7307           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7308         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7309                                0, NULL_RTX, mode_width - INTVAL (rhs),
7310                                code == LSHIFTRT, 0, in_code == COMPARE);
7311
7312       break;
7313
7314     case SUBREG:
7315       /* Call ourselves recursively on the inner expression.  If we are
7316          narrowing the object and it has a different RTL code from
7317          what it originally did, do this SUBREG as a force_to_mode.  */
7318
7319       tem = make_compound_operation (SUBREG_REG (x), in_code);
7320
7321       {
7322         rtx simplified;
7323         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7324                                       SUBREG_BYTE (x));
7325
7326         if (simplified)
7327           tem = simplified;
7328
7329         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7330             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7331             && subreg_lowpart_p (x))
7332           {
7333             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7334                                        0);
7335
7336             /* If we have something other than a SUBREG, we might have
7337                done an expansion, so rerun ourselves.  */
7338             if (GET_CODE (newer) != SUBREG)
7339               newer = make_compound_operation (newer, in_code);
7340
7341             /* force_to_mode can expand compounds.  If it just re-expanded the
7342                compound use gen_lowpart instead to convert to the desired
7343                mode.  */
7344             if (rtx_equal_p (newer, x))
7345               return gen_lowpart (GET_MODE (x), tem);
7346
7347             return newer;
7348           }
7349
7350         if (simplified)
7351           return tem;
7352       }
7353       break;
7354
7355     default:
7356       break;
7357     }
7358
7359   if (new_rtx)
7360     {
7361       x = gen_lowpart (mode, new_rtx);
7362       code = GET_CODE (x);
7363     }
7364
7365   /* Now recursively process each operand of this operation.  */
7366   fmt = GET_RTX_FORMAT (code);
7367   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7368     if (fmt[i] == 'e')
7369       {
7370         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7371         SUBST (XEXP (x, i), new_rtx);
7372       }
7373     else if (fmt[i] == 'E')
7374       for (j = 0; j < XVECLEN (x, i); j++)
7375         {
7376           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7377           SUBST (XVECEXP (x, i, j), new_rtx);
7378         }
7379
7380   /* If this is a commutative operation, the changes to the operands
7381      may have made it noncanonical.  */
7382   if (COMMUTATIVE_ARITH_P (x)
7383       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7384     {
7385       tem = XEXP (x, 0);
7386       SUBST (XEXP (x, 0), XEXP (x, 1));
7387       SUBST (XEXP (x, 1), tem);
7388     }
7389
7390   return x;
7391 }
7392 \f
7393 /* Given M see if it is a value that would select a field of bits
7394    within an item, but not the entire word.  Return -1 if not.
7395    Otherwise, return the starting position of the field, where 0 is the
7396    low-order bit.
7397
7398    *PLEN is set to the length of the field.  */
7399
7400 static int
7401 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7402 {
7403   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7404   int pos = exact_log2 (m & -m);
7405   int len = 0;
7406
7407   if (pos >= 0)
7408     /* Now shift off the low-order zero bits and see if we have a
7409        power of two minus 1.  */
7410     len = exact_log2 ((m >> pos) + 1);
7411
7412   if (len <= 0)
7413     pos = -1;
7414
7415   *plen = len;
7416   return pos;
7417 }
7418 \f
7419 /* If X refers to a register that equals REG in value, replace these
7420    references with REG.  */
7421 static rtx
7422 canon_reg_for_combine (rtx x, rtx reg)
7423 {
7424   rtx op0, op1, op2;
7425   const char *fmt;
7426   int i;
7427   bool copied;
7428
7429   enum rtx_code code = GET_CODE (x);
7430   switch (GET_RTX_CLASS (code))
7431     {
7432     case RTX_UNARY:
7433       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7434       if (op0 != XEXP (x, 0))
7435         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7436                                    GET_MODE (reg));
7437       break;
7438
7439     case RTX_BIN_ARITH:
7440     case RTX_COMM_ARITH:
7441       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7442       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7443       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7444         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7445       break;
7446
7447     case RTX_COMPARE:
7448     case RTX_COMM_COMPARE:
7449       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7450       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7451       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7452         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7453                                         GET_MODE (op0), op0, op1);
7454       break;
7455
7456     case RTX_TERNARY:
7457     case RTX_BITFIELD_OPS:
7458       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7459       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7460       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7461       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7462         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7463                                      GET_MODE (op0), op0, op1, op2);
7464
7465     case RTX_OBJ:
7466       if (REG_P (x))
7467         {
7468           if (rtx_equal_p (get_last_value (reg), x)
7469               || rtx_equal_p (reg, get_last_value (x)))
7470             return reg;
7471           else
7472             break;
7473         }
7474
7475       /* fall through */
7476
7477     default:
7478       fmt = GET_RTX_FORMAT (code);
7479       copied = false;
7480       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7481         if (fmt[i] == 'e')
7482           {
7483             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7484             if (op != XEXP (x, i))
7485               {
7486                 if (!copied)
7487                   {
7488                     copied = true;
7489                     x = copy_rtx (x);
7490                   }
7491                 XEXP (x, i) = op;
7492               }
7493           }
7494         else if (fmt[i] == 'E')
7495           {
7496             int j;
7497             for (j = 0; j < XVECLEN (x, i); j++)
7498               {
7499                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7500                 if (op != XVECEXP (x, i, j))
7501                   {
7502                     if (!copied)
7503                       {
7504                         copied = true;
7505                         x = copy_rtx (x);
7506                       }
7507                     XVECEXP (x, i, j) = op;
7508                   }
7509               }
7510           }
7511
7512       break;
7513     }
7514
7515   return x;
7516 }
7517
7518 /* Return X converted to MODE.  If the value is already truncated to
7519    MODE we can just return a subreg even though in the general case we
7520    would need an explicit truncation.  */
7521
7522 static rtx
7523 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7524 {
7525   if (!CONST_INT_P (x)
7526       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7527       && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7528                                  GET_MODE_BITSIZE (GET_MODE (x)))
7529       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7530     {
7531       /* Bit-cast X into an integer mode.  */
7532       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7533         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7534       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7535                               x, GET_MODE (x));
7536     }
7537
7538   return gen_lowpart (mode, x);
7539 }
7540
7541 /* See if X can be simplified knowing that we will only refer to it in
7542    MODE and will only refer to those bits that are nonzero in MASK.
7543    If other bits are being computed or if masking operations are done
7544    that select a superset of the bits in MASK, they can sometimes be
7545    ignored.
7546
7547    Return a possibly simplified expression, but always convert X to
7548    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
7549
7550    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7551    are all off in X.  This is used when X will be complemented, by either
7552    NOT, NEG, or XOR.  */
7553
7554 static rtx
7555 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7556                int just_select)
7557 {
7558   enum rtx_code code = GET_CODE (x);
7559   int next_select = just_select || code == XOR || code == NOT || code == NEG;
7560   enum machine_mode op_mode;
7561   unsigned HOST_WIDE_INT fuller_mask, nonzero;
7562   rtx op0, op1, temp;
7563
7564   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
7565      code below will do the wrong thing since the mode of such an
7566      expression is VOIDmode.
7567
7568      Also do nothing if X is a CLOBBER; this can happen if X was
7569      the return value from a call to gen_lowpart.  */
7570   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7571     return x;
7572
7573   /* We want to perform the operation is its present mode unless we know
7574      that the operation is valid in MODE, in which case we do the operation
7575      in MODE.  */
7576   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7577               && have_insn_for (code, mode))
7578              ? mode : GET_MODE (x));
7579
7580   /* It is not valid to do a right-shift in a narrower mode
7581      than the one it came in with.  */
7582   if ((code == LSHIFTRT || code == ASHIFTRT)
7583       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7584     op_mode = GET_MODE (x);
7585
7586   /* Truncate MASK to fit OP_MODE.  */
7587   if (op_mode)
7588     mask &= GET_MODE_MASK (op_mode);
7589
7590   /* When we have an arithmetic operation, or a shift whose count we
7591      do not know, we need to assume that all bits up to the highest-order
7592      bit in MASK will be needed.  This is how we form such a mask.  */
7593   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7594     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7595   else
7596     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7597                    - 1);
7598
7599   /* Determine what bits of X are guaranteed to be (non)zero.  */
7600   nonzero = nonzero_bits (x, mode);
7601
7602   /* If none of the bits in X are needed, return a zero.  */
7603   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7604     x = const0_rtx;
7605
7606   /* If X is a CONST_INT, return a new one.  Do this here since the
7607      test below will fail.  */
7608   if (CONST_INT_P (x))
7609     {
7610       if (SCALAR_INT_MODE_P (mode))
7611         return gen_int_mode (INTVAL (x) & mask, mode);
7612       else
7613         {
7614           x = GEN_INT (INTVAL (x) & mask);
7615           return gen_lowpart_common (mode, x);
7616         }
7617     }
7618
7619   /* If X is narrower than MODE and we want all the bits in X's mode, just
7620      get X in the proper mode.  */
7621   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7622       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7623     return gen_lowpart (mode, x);
7624
7625   /* We can ignore the effect of a SUBREG if it narrows the mode or
7626      if the constant masks to zero all the bits the mode doesn't have.  */
7627   if (GET_CODE (x) == SUBREG
7628       && subreg_lowpart_p (x)
7629       && ((GET_MODE_SIZE (GET_MODE (x))
7630            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7631           || (0 == (mask
7632                     & GET_MODE_MASK (GET_MODE (x))
7633                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7634     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7635
7636   /* The arithmetic simplifications here only work for scalar integer modes.  */
7637   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7638     return gen_lowpart_or_truncate (mode, x);
7639
7640   switch (code)
7641     {
7642     case CLOBBER:
7643       /* If X is a (clobber (const_int)), return it since we know we are
7644          generating something that won't match.  */
7645       return x;
7646
7647     case SIGN_EXTEND:
7648     case ZERO_EXTEND:
7649     case ZERO_EXTRACT:
7650     case SIGN_EXTRACT:
7651       x = expand_compound_operation (x);
7652       if (GET_CODE (x) != code)
7653         return force_to_mode (x, mode, mask, next_select);
7654       break;
7655
7656     case TRUNCATE:
7657       /* Similarly for a truncate.  */
7658       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7659
7660     case AND:
7661       /* If this is an AND with a constant, convert it into an AND
7662          whose constant is the AND of that constant with MASK.  If it
7663          remains an AND of MASK, delete it since it is redundant.  */
7664
7665       if (CONST_INT_P (XEXP (x, 1)))
7666         {
7667           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7668                                       mask & INTVAL (XEXP (x, 1)));
7669
7670           /* If X is still an AND, see if it is an AND with a mask that
7671              is just some low-order bits.  If so, and it is MASK, we don't
7672              need it.  */
7673
7674           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7675               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7676                   == mask))
7677             x = XEXP (x, 0);
7678
7679           /* If it remains an AND, try making another AND with the bits
7680              in the mode mask that aren't in MASK turned on.  If the
7681              constant in the AND is wide enough, this might make a
7682              cheaper constant.  */
7683
7684           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7685               && GET_MODE_MASK (GET_MODE (x)) != mask
7686               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7687             {
7688               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7689                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7690               int width = GET_MODE_BITSIZE (GET_MODE (x));
7691               rtx y;
7692
7693               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7694                  number, sign extend it.  */
7695               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7696                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7697                 cval |= (HOST_WIDE_INT) -1 << width;
7698
7699               y = simplify_gen_binary (AND, GET_MODE (x),
7700                                        XEXP (x, 0), GEN_INT (cval));
7701               if (rtx_cost (y, SET, optimize_this_for_speed_p)
7702                   < rtx_cost (x, SET, optimize_this_for_speed_p))
7703                 x = y;
7704             }
7705
7706           break;
7707         }
7708
7709       goto binop;
7710
7711     case PLUS:
7712       /* In (and (plus FOO C1) M), if M is a mask that just turns off
7713          low-order bits (as in an alignment operation) and FOO is already
7714          aligned to that boundary, mask C1 to that boundary as well.
7715          This may eliminate that PLUS and, later, the AND.  */
7716
7717       {
7718         unsigned int width = GET_MODE_BITSIZE (mode);
7719         unsigned HOST_WIDE_INT smask = mask;
7720
7721         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7722            number, sign extend it.  */
7723
7724         if (width < HOST_BITS_PER_WIDE_INT
7725             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7726           smask |= (HOST_WIDE_INT) -1 << width;
7727
7728         if (CONST_INT_P (XEXP (x, 1))
7729             && exact_log2 (- smask) >= 0
7730             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7731             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7732           return force_to_mode (plus_constant (XEXP (x, 0),
7733                                                (INTVAL (XEXP (x, 1)) & smask)),
7734                                 mode, smask, next_select);
7735       }
7736
7737       /* ... fall through ...  */
7738
7739     case MULT:
7740       /* For PLUS, MINUS and MULT, we need any bits less significant than the
7741          most significant bit in MASK since carries from those bits will
7742          affect the bits we are interested in.  */
7743       mask = fuller_mask;
7744       goto binop;
7745
7746     case MINUS:
7747       /* If X is (minus C Y) where C's least set bit is larger than any bit
7748          in the mask, then we may replace with (neg Y).  */
7749       if (CONST_INT_P (XEXP (x, 0))
7750           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7751                                         & -INTVAL (XEXP (x, 0))))
7752               > mask))
7753         {
7754           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7755                                   GET_MODE (x));
7756           return force_to_mode (x, mode, mask, next_select);
7757         }
7758
7759       /* Similarly, if C contains every bit in the fuller_mask, then we may
7760          replace with (not Y).  */
7761       if (CONST_INT_P (XEXP (x, 0))
7762           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7763               == INTVAL (XEXP (x, 0))))
7764         {
7765           x = simplify_gen_unary (NOT, GET_MODE (x),
7766                                   XEXP (x, 1), GET_MODE (x));
7767           return force_to_mode (x, mode, mask, next_select);
7768         }
7769
7770       mask = fuller_mask;
7771       goto binop;
7772
7773     case IOR:
7774     case XOR:
7775       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7776          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7777          operation which may be a bitfield extraction.  Ensure that the
7778          constant we form is not wider than the mode of X.  */
7779
7780       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7781           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7782           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7783           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7784           && CONST_INT_P (XEXP (x, 1))
7785           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7786                + floor_log2 (INTVAL (XEXP (x, 1))))
7787               < GET_MODE_BITSIZE (GET_MODE (x)))
7788           && (INTVAL (XEXP (x, 1))
7789               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7790         {
7791           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7792                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7793           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7794                                       XEXP (XEXP (x, 0), 0), temp);
7795           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7796                                    XEXP (XEXP (x, 0), 1));
7797           return force_to_mode (x, mode, mask, next_select);
7798         }
7799
7800     binop:
7801       /* For most binary operations, just propagate into the operation and
7802          change the mode if we have an operation of that mode.  */
7803
7804       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7805       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7806
7807       /* If we ended up truncating both operands, truncate the result of the
7808          operation instead.  */
7809       if (GET_CODE (op0) == TRUNCATE
7810           && GET_CODE (op1) == TRUNCATE)
7811         {
7812           op0 = XEXP (op0, 0);
7813           op1 = XEXP (op1, 0);
7814         }
7815
7816       op0 = gen_lowpart_or_truncate (op_mode, op0);
7817       op1 = gen_lowpart_or_truncate (op_mode, op1);
7818
7819       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7820         x = simplify_gen_binary (code, op_mode, op0, op1);
7821       break;
7822
7823     case ASHIFT:
7824       /* For left shifts, do the same, but just for the first operand.
7825          However, we cannot do anything with shifts where we cannot
7826          guarantee that the counts are smaller than the size of the mode
7827          because such a count will have a different meaning in a
7828          wider mode.  */
7829
7830       if (! (CONST_INT_P (XEXP (x, 1))
7831              && INTVAL (XEXP (x, 1)) >= 0
7832              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7833           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7834                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7835                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7836         break;
7837
7838       /* If the shift count is a constant and we can do arithmetic in
7839          the mode of the shift, refine which bits we need.  Otherwise, use the
7840          conservative form of the mask.  */
7841       if (CONST_INT_P (XEXP (x, 1))
7842           && INTVAL (XEXP (x, 1)) >= 0
7843           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7844           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7845         mask >>= INTVAL (XEXP (x, 1));
7846       else
7847         mask = fuller_mask;
7848
7849       op0 = gen_lowpart_or_truncate (op_mode,
7850                                      force_to_mode (XEXP (x, 0), op_mode,
7851                                                     mask, next_select));
7852
7853       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7854         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7855       break;
7856
7857     case LSHIFTRT:
7858       /* Here we can only do something if the shift count is a constant,
7859          this shift constant is valid for the host, and we can do arithmetic
7860          in OP_MODE.  */
7861
7862       if (CONST_INT_P (XEXP (x, 1))
7863           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7864           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7865         {
7866           rtx inner = XEXP (x, 0);
7867           unsigned HOST_WIDE_INT inner_mask;
7868
7869           /* Select the mask of the bits we need for the shift operand.  */
7870           inner_mask = mask << INTVAL (XEXP (x, 1));
7871
7872           /* We can only change the mode of the shift if we can do arithmetic
7873              in the mode of the shift and INNER_MASK is no wider than the
7874              width of X's mode.  */
7875           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7876             op_mode = GET_MODE (x);
7877
7878           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7879
7880           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7881             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7882         }
7883
7884       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7885          shift and AND produces only copies of the sign bit (C2 is one less
7886          than a power of two), we can do this with just a shift.  */
7887
7888       if (GET_CODE (x) == LSHIFTRT
7889           && CONST_INT_P (XEXP (x, 1))
7890           /* The shift puts one of the sign bit copies in the least significant
7891              bit.  */
7892           && ((INTVAL (XEXP (x, 1))
7893                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7894               >= GET_MODE_BITSIZE (GET_MODE (x)))
7895           && exact_log2 (mask + 1) >= 0
7896           /* Number of bits left after the shift must be more than the mask
7897              needs.  */
7898           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7899               <= GET_MODE_BITSIZE (GET_MODE (x)))
7900           /* Must be more sign bit copies than the mask needs.  */
7901           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7902               >= exact_log2 (mask + 1)))
7903         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7904                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7905                                           - exact_log2 (mask + 1)));
7906
7907       goto shiftrt;
7908
7909     case ASHIFTRT:
7910       /* If we are just looking for the sign bit, we don't need this shift at
7911          all, even if it has a variable count.  */
7912       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7913           && (mask == ((unsigned HOST_WIDE_INT) 1
7914                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7915         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7916
7917       /* If this is a shift by a constant, get a mask that contains those bits
7918          that are not copies of the sign bit.  We then have two cases:  If
7919          MASK only includes those bits, this can be a logical shift, which may
7920          allow simplifications.  If MASK is a single-bit field not within
7921          those bits, we are requesting a copy of the sign bit and hence can
7922          shift the sign bit to the appropriate location.  */
7923
7924       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7925           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7926         {
7927           int i;
7928
7929           /* If the considered data is wider than HOST_WIDE_INT, we can't
7930              represent a mask for all its bits in a single scalar.
7931              But we only care about the lower bits, so calculate these.  */
7932
7933           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7934             {
7935               nonzero = ~(HOST_WIDE_INT) 0;
7936
7937               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7938                  is the number of bits a full-width mask would have set.
7939                  We need only shift if these are fewer than nonzero can
7940                  hold.  If not, we must keep all bits set in nonzero.  */
7941
7942               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7943                   < HOST_BITS_PER_WIDE_INT)
7944                 nonzero >>= INTVAL (XEXP (x, 1))
7945                             + HOST_BITS_PER_WIDE_INT
7946                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7947             }
7948           else
7949             {
7950               nonzero = GET_MODE_MASK (GET_MODE (x));
7951               nonzero >>= INTVAL (XEXP (x, 1));
7952             }
7953
7954           if ((mask & ~nonzero) == 0)
7955             {
7956               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7957                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7958               if (GET_CODE (x) != ASHIFTRT)
7959                 return force_to_mode (x, mode, mask, next_select);
7960             }
7961
7962           else if ((i = exact_log2 (mask)) >= 0)
7963             {
7964               x = simplify_shift_const
7965                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7966                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7967
7968               if (GET_CODE (x) != ASHIFTRT)
7969                 return force_to_mode (x, mode, mask, next_select);
7970             }
7971         }
7972
7973       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7974          even if the shift count isn't a constant.  */
7975       if (mask == 1)
7976         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7977                                  XEXP (x, 0), XEXP (x, 1));
7978
7979     shiftrt:
7980
7981       /* If this is a zero- or sign-extension operation that just affects bits
7982          we don't care about, remove it.  Be sure the call above returned
7983          something that is still a shift.  */
7984
7985       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7986           && CONST_INT_P (XEXP (x, 1))
7987           && INTVAL (XEXP (x, 1)) >= 0
7988           && (INTVAL (XEXP (x, 1))
7989               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7990           && GET_CODE (XEXP (x, 0)) == ASHIFT
7991           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7992         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7993                               next_select);
7994
7995       break;
7996
7997     case ROTATE:
7998     case ROTATERT:
7999       /* If the shift count is constant and we can do computations
8000          in the mode of X, compute where the bits we care about are.
8001          Otherwise, we can't do anything.  Don't change the mode of
8002          the shift or propagate MODE into the shift, though.  */
8003       if (CONST_INT_P (XEXP (x, 1))
8004           && INTVAL (XEXP (x, 1)) >= 0)
8005         {
8006           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8007                                             GET_MODE (x), GEN_INT (mask),
8008                                             XEXP (x, 1));
8009           if (temp && CONST_INT_P (temp))
8010             SUBST (XEXP (x, 0),
8011                    force_to_mode (XEXP (x, 0), GET_MODE (x),
8012                                   INTVAL (temp), next_select));
8013         }
8014       break;
8015
8016     case NEG:
8017       /* If we just want the low-order bit, the NEG isn't needed since it
8018          won't change the low-order bit.  */
8019       if (mask == 1)
8020         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8021
8022       /* We need any bits less significant than the most significant bit in
8023          MASK since carries from those bits will affect the bits we are
8024          interested in.  */
8025       mask = fuller_mask;
8026       goto unop;
8027
8028     case NOT:
8029       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8030          same as the XOR case above.  Ensure that the constant we form is not
8031          wider than the mode of X.  */
8032
8033       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8034           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8035           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8036           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8037               < GET_MODE_BITSIZE (GET_MODE (x)))
8038           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8039         {
8040           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8041                                GET_MODE (x));
8042           temp = simplify_gen_binary (XOR, GET_MODE (x),
8043                                       XEXP (XEXP (x, 0), 0), temp);
8044           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8045                                    temp, XEXP (XEXP (x, 0), 1));
8046
8047           return force_to_mode (x, mode, mask, next_select);
8048         }
8049
8050       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8051          use the full mask inside the NOT.  */
8052       mask = fuller_mask;
8053
8054     unop:
8055       op0 = gen_lowpart_or_truncate (op_mode,
8056                                      force_to_mode (XEXP (x, 0), mode, mask,
8057                                                     next_select));
8058       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8059         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8060       break;
8061
8062     case NE:
8063       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8064          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8065          which is equal to STORE_FLAG_VALUE.  */
8066       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8067           && GET_MODE (XEXP (x, 0)) == mode
8068           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8069           && (nonzero_bits (XEXP (x, 0), mode)
8070               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8071         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8072
8073       break;
8074
8075     case IF_THEN_ELSE:
8076       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8077          written in a narrower mode.  We play it safe and do not do so.  */
8078
8079       SUBST (XEXP (x, 1),
8080              gen_lowpart_or_truncate (GET_MODE (x),
8081                                       force_to_mode (XEXP (x, 1), mode,
8082                                                      mask, next_select)));
8083       SUBST (XEXP (x, 2),
8084              gen_lowpart_or_truncate (GET_MODE (x),
8085                                       force_to_mode (XEXP (x, 2), mode,
8086                                                      mask, next_select)));
8087       break;
8088
8089     default:
8090       break;
8091     }
8092
8093   /* Ensure we return a value of the proper mode.  */
8094   return gen_lowpart_or_truncate (mode, x);
8095 }
8096 \f
8097 /* Return nonzero if X is an expression that has one of two values depending on
8098    whether some other value is zero or nonzero.  In that case, we return the
8099    value that is being tested, *PTRUE is set to the value if the rtx being
8100    returned has a nonzero value, and *PFALSE is set to the other alternative.
8101
8102    If we return zero, we set *PTRUE and *PFALSE to X.  */
8103
8104 static rtx
8105 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8106 {
8107   enum machine_mode mode = GET_MODE (x);
8108   enum rtx_code code = GET_CODE (x);
8109   rtx cond0, cond1, true0, true1, false0, false1;
8110   unsigned HOST_WIDE_INT nz;
8111
8112   /* If we are comparing a value against zero, we are done.  */
8113   if ((code == NE || code == EQ)
8114       && XEXP (x, 1) == const0_rtx)
8115     {
8116       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8117       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8118       return XEXP (x, 0);
8119     }
8120
8121   /* If this is a unary operation whose operand has one of two values, apply
8122      our opcode to compute those values.  */
8123   else if (UNARY_P (x)
8124            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8125     {
8126       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8127       *pfalse = simplify_gen_unary (code, mode, false0,
8128                                     GET_MODE (XEXP (x, 0)));
8129       return cond0;
8130     }
8131
8132   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8133      make can't possibly match and would suppress other optimizations.  */
8134   else if (code == COMPARE)
8135     ;
8136
8137   /* If this is a binary operation, see if either side has only one of two
8138      values.  If either one does or if both do and they are conditional on
8139      the same value, compute the new true and false values.  */
8140   else if (BINARY_P (x))
8141     {
8142       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8143       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8144
8145       if ((cond0 != 0 || cond1 != 0)
8146           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8147         {
8148           /* If if_then_else_cond returned zero, then true/false are the
8149              same rtl.  We must copy one of them to prevent invalid rtl
8150              sharing.  */
8151           if (cond0 == 0)
8152             true0 = copy_rtx (true0);
8153           else if (cond1 == 0)
8154             true1 = copy_rtx (true1);
8155
8156           if (COMPARISON_P (x))
8157             {
8158               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8159                                                 true0, true1);
8160               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8161                                                  false0, false1);
8162              }
8163           else
8164             {
8165               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8166               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8167             }
8168
8169           return cond0 ? cond0 : cond1;
8170         }
8171
8172       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8173          operands is zero when the other is nonzero, and vice-versa,
8174          and STORE_FLAG_VALUE is 1 or -1.  */
8175
8176       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8177           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8178               || code == UMAX)
8179           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8180         {
8181           rtx op0 = XEXP (XEXP (x, 0), 1);
8182           rtx op1 = XEXP (XEXP (x, 1), 1);
8183
8184           cond0 = XEXP (XEXP (x, 0), 0);
8185           cond1 = XEXP (XEXP (x, 1), 0);
8186
8187           if (COMPARISON_P (cond0)
8188               && COMPARISON_P (cond1)
8189               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8190                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8191                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8192                   || ((swap_condition (GET_CODE (cond0))
8193                        == reversed_comparison_code (cond1, NULL))
8194                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8195                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8196               && ! side_effects_p (x))
8197             {
8198               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8199               *pfalse = simplify_gen_binary (MULT, mode,
8200                                              (code == MINUS
8201                                               ? simplify_gen_unary (NEG, mode,
8202                                                                     op1, mode)
8203                                               : op1),
8204                                               const_true_rtx);
8205               return cond0;
8206             }
8207         }
8208
8209       /* Similarly for MULT, AND and UMIN, except that for these the result
8210          is always zero.  */
8211       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8212           && (code == MULT || code == AND || code == UMIN)
8213           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8214         {
8215           cond0 = XEXP (XEXP (x, 0), 0);
8216           cond1 = XEXP (XEXP (x, 1), 0);
8217
8218           if (COMPARISON_P (cond0)
8219               && COMPARISON_P (cond1)
8220               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8221                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8222                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8223                   || ((swap_condition (GET_CODE (cond0))
8224                        == reversed_comparison_code (cond1, NULL))
8225                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8226                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8227               && ! side_effects_p (x))
8228             {
8229               *ptrue = *pfalse = const0_rtx;
8230               return cond0;
8231             }
8232         }
8233     }
8234
8235   else if (code == IF_THEN_ELSE)
8236     {
8237       /* If we have IF_THEN_ELSE already, extract the condition and
8238          canonicalize it if it is NE or EQ.  */
8239       cond0 = XEXP (x, 0);
8240       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8241       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8242         return XEXP (cond0, 0);
8243       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8244         {
8245           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8246           return XEXP (cond0, 0);
8247         }
8248       else
8249         return cond0;
8250     }
8251
8252   /* If X is a SUBREG, we can narrow both the true and false values
8253      if the inner expression, if there is a condition.  */
8254   else if (code == SUBREG
8255            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8256                                                &true0, &false0)))
8257     {
8258       true0 = simplify_gen_subreg (mode, true0,
8259                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8260       false0 = simplify_gen_subreg (mode, false0,
8261                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8262       if (true0 && false0)
8263         {
8264           *ptrue = true0;
8265           *pfalse = false0;
8266           return cond0;
8267         }
8268     }
8269
8270   /* If X is a constant, this isn't special and will cause confusions
8271      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8272   else if (CONSTANT_P (x)
8273            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8274     ;
8275
8276   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8277      will be least confusing to the rest of the compiler.  */
8278   else if (mode == BImode)
8279     {
8280       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8281       return x;
8282     }
8283
8284   /* If X is known to be either 0 or -1, those are the true and
8285      false values when testing X.  */
8286   else if (x == constm1_rtx || x == const0_rtx
8287            || (mode != VOIDmode
8288                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8289     {
8290       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8291       return x;
8292     }
8293
8294   /* Likewise for 0 or a single bit.  */
8295   else if (SCALAR_INT_MODE_P (mode)
8296            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8297            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8298     {
8299       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8300       return x;
8301     }
8302
8303   /* Otherwise fail; show no condition with true and false values the same.  */
8304   *ptrue = *pfalse = x;
8305   return 0;
8306 }
8307 \f
8308 /* Return the value of expression X given the fact that condition COND
8309    is known to be true when applied to REG as its first operand and VAL
8310    as its second.  X is known to not be shared and so can be modified in
8311    place.
8312
8313    We only handle the simplest cases, and specifically those cases that
8314    arise with IF_THEN_ELSE expressions.  */
8315
8316 static rtx
8317 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8318 {
8319   enum rtx_code code = GET_CODE (x);
8320   rtx temp;
8321   const char *fmt;
8322   int i, j;
8323
8324   if (side_effects_p (x))
8325     return x;
8326
8327   /* If either operand of the condition is a floating point value,
8328      then we have to avoid collapsing an EQ comparison.  */
8329   if (cond == EQ
8330       && rtx_equal_p (x, reg)
8331       && ! FLOAT_MODE_P (GET_MODE (x))
8332       && ! FLOAT_MODE_P (GET_MODE (val)))
8333     return val;
8334
8335   if (cond == UNEQ && rtx_equal_p (x, reg))
8336     return val;
8337
8338   /* If X is (abs REG) and we know something about REG's relationship
8339      with zero, we may be able to simplify this.  */
8340
8341   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8342     switch (cond)
8343       {
8344       case GE:  case GT:  case EQ:
8345         return XEXP (x, 0);
8346       case LT:  case LE:
8347         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8348                                    XEXP (x, 0),
8349                                    GET_MODE (XEXP (x, 0)));
8350       default:
8351         break;
8352       }
8353
8354   /* The only other cases we handle are MIN, MAX, and comparisons if the
8355      operands are the same as REG and VAL.  */
8356
8357   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8358     {
8359       if (rtx_equal_p (XEXP (x, 0), val))
8360         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8361
8362       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8363         {
8364           if (COMPARISON_P (x))
8365             {
8366               if (comparison_dominates_p (cond, code))
8367                 return const_true_rtx;
8368
8369               code = reversed_comparison_code (x, NULL);
8370               if (code != UNKNOWN
8371                   && comparison_dominates_p (cond, code))
8372                 return const0_rtx;
8373               else
8374                 return x;
8375             }
8376           else if (code == SMAX || code == SMIN
8377                    || code == UMIN || code == UMAX)
8378             {
8379               int unsignedp = (code == UMIN || code == UMAX);
8380
8381               /* Do not reverse the condition when it is NE or EQ.
8382                  This is because we cannot conclude anything about
8383                  the value of 'SMAX (x, y)' when x is not equal to y,
8384                  but we can when x equals y.  */
8385               if ((code == SMAX || code == UMAX)
8386                   && ! (cond == EQ || cond == NE))
8387                 cond = reverse_condition (cond);
8388
8389               switch (cond)
8390                 {
8391                 case GE:   case GT:
8392                   return unsignedp ? x : XEXP (x, 1);
8393                 case LE:   case LT:
8394                   return unsignedp ? x : XEXP (x, 0);
8395                 case GEU:  case GTU:
8396                   return unsignedp ? XEXP (x, 1) : x;
8397                 case LEU:  case LTU:
8398                   return unsignedp ? XEXP (x, 0) : x;
8399                 default:
8400                   break;
8401                 }
8402             }
8403         }
8404     }
8405   else if (code == SUBREG)
8406     {
8407       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8408       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8409
8410       if (SUBREG_REG (x) != r)
8411         {
8412           /* We must simplify subreg here, before we lose track of the
8413              original inner_mode.  */
8414           new_rtx = simplify_subreg (GET_MODE (x), r,
8415                                  inner_mode, SUBREG_BYTE (x));
8416           if (new_rtx)
8417             return new_rtx;
8418           else
8419             SUBST (SUBREG_REG (x), r);
8420         }
8421
8422       return x;
8423     }
8424   /* We don't have to handle SIGN_EXTEND here, because even in the
8425      case of replacing something with a modeless CONST_INT, a
8426      CONST_INT is already (supposed to be) a valid sign extension for
8427      its narrower mode, which implies it's already properly
8428      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8429      story is different.  */
8430   else if (code == ZERO_EXTEND)
8431     {
8432       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8433       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8434
8435       if (XEXP (x, 0) != r)
8436         {
8437           /* We must simplify the zero_extend here, before we lose
8438              track of the original inner_mode.  */
8439           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8440                                           r, inner_mode);
8441           if (new_rtx)
8442             return new_rtx;
8443           else
8444             SUBST (XEXP (x, 0), r);
8445         }
8446
8447       return x;
8448     }
8449
8450   fmt = GET_RTX_FORMAT (code);
8451   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8452     {
8453       if (fmt[i] == 'e')
8454         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8455       else if (fmt[i] == 'E')
8456         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8457           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8458                                                 cond, reg, val));
8459     }
8460
8461   return x;
8462 }
8463 \f
8464 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8465    assignment as a field assignment.  */
8466
8467 static int
8468 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8469 {
8470   if (x == y || rtx_equal_p (x, y))
8471     return 1;
8472
8473   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8474     return 0;
8475
8476   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8477      Note that all SUBREGs of MEM are paradoxical; otherwise they
8478      would have been rewritten.  */
8479   if (MEM_P (x) && GET_CODE (y) == SUBREG
8480       && MEM_P (SUBREG_REG (y))
8481       && rtx_equal_p (SUBREG_REG (y),
8482                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8483     return 1;
8484
8485   if (MEM_P (y) && GET_CODE (x) == SUBREG
8486       && MEM_P (SUBREG_REG (x))
8487       && rtx_equal_p (SUBREG_REG (x),
8488                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8489     return 1;
8490
8491   /* We used to see if get_last_value of X and Y were the same but that's
8492      not correct.  In one direction, we'll cause the assignment to have
8493      the wrong destination and in the case, we'll import a register into this
8494      insn that might have already have been dead.   So fail if none of the
8495      above cases are true.  */
8496   return 0;
8497 }
8498 \f
8499 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8500    Return that assignment if so.
8501
8502    We only handle the most common cases.  */
8503
8504 static rtx
8505 make_field_assignment (rtx x)
8506 {
8507   rtx dest = SET_DEST (x);
8508   rtx src = SET_SRC (x);
8509   rtx assign;
8510   rtx rhs, lhs;
8511   HOST_WIDE_INT c1;
8512   HOST_WIDE_INT pos;
8513   unsigned HOST_WIDE_INT len;
8514   rtx other;
8515   enum machine_mode mode;
8516
8517   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8518      a clear of a one-bit field.  We will have changed it to
8519      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
8520      for a SUBREG.  */
8521
8522   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8523       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8524       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8525       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8526     {
8527       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8528                                 1, 1, 1, 0);
8529       if (assign != 0)
8530         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8531       return x;
8532     }
8533
8534   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8535       && subreg_lowpart_p (XEXP (src, 0))
8536       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8537           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8538       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8539       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8540       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8541       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8542     {
8543       assign = make_extraction (VOIDmode, dest, 0,
8544                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8545                                 1, 1, 1, 0);
8546       if (assign != 0)
8547         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8548       return x;
8549     }
8550
8551   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8552      one-bit field.  */
8553   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8554       && XEXP (XEXP (src, 0), 0) == const1_rtx
8555       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8556     {
8557       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8558                                 1, 1, 1, 0);
8559       if (assign != 0)
8560         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8561       return x;
8562     }
8563
8564   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8565      SRC is an AND with all bits of that field set, then we can discard
8566      the AND.  */
8567   if (GET_CODE (dest) == ZERO_EXTRACT
8568       && CONST_INT_P (XEXP (dest, 1))
8569       && GET_CODE (src) == AND
8570       && CONST_INT_P (XEXP (src, 1)))
8571     {
8572       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8573       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8574       unsigned HOST_WIDE_INT ze_mask;
8575
8576       if (width >= HOST_BITS_PER_WIDE_INT)
8577         ze_mask = -1;
8578       else
8579         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8580
8581       /* Complete overlap.  We can remove the source AND.  */
8582       if ((and_mask & ze_mask) == ze_mask)
8583         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8584
8585       /* Partial overlap.  We can reduce the source AND.  */
8586       if ((and_mask & ze_mask) != and_mask)
8587         {
8588           mode = GET_MODE (src);
8589           src = gen_rtx_AND (mode, XEXP (src, 0),
8590                              gen_int_mode (and_mask & ze_mask, mode));
8591           return gen_rtx_SET (VOIDmode, dest, src);
8592         }
8593     }
8594
8595   /* The other case we handle is assignments into a constant-position
8596      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
8597      a mask that has all one bits except for a group of zero bits and
8598      OTHER is known to have zeros where C1 has ones, this is such an
8599      assignment.  Compute the position and length from C1.  Shift OTHER
8600      to the appropriate position, force it to the required mode, and
8601      make the extraction.  Check for the AND in both operands.  */
8602
8603   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8604     return x;
8605
8606   rhs = expand_compound_operation (XEXP (src, 0));
8607   lhs = expand_compound_operation (XEXP (src, 1));
8608
8609   if (GET_CODE (rhs) == AND
8610       && CONST_INT_P (XEXP (rhs, 1))
8611       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8612     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8613   else if (GET_CODE (lhs) == AND
8614            && CONST_INT_P (XEXP (lhs, 1))
8615            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8616     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8617   else
8618     return x;
8619
8620   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8621   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8622       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8623       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8624     return x;
8625
8626   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8627   if (assign == 0)
8628     return x;
8629
8630   /* The mode to use for the source is the mode of the assignment, or of
8631      what is inside a possible STRICT_LOW_PART.  */
8632   mode = (GET_CODE (assign) == STRICT_LOW_PART
8633           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8634
8635   /* Shift OTHER right POS places and make it the source, restricting it
8636      to the proper length and mode.  */
8637
8638   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8639                                                      GET_MODE (src),
8640                                                      other, pos),
8641                                dest);
8642   src = force_to_mode (src, mode,
8643                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8644                        ? ~(unsigned HOST_WIDE_INT) 0
8645                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8646                        0);
8647
8648   /* If SRC is masked by an AND that does not make a difference in
8649      the value being stored, strip it.  */
8650   if (GET_CODE (assign) == ZERO_EXTRACT
8651       && CONST_INT_P (XEXP (assign, 1))
8652       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8653       && GET_CODE (src) == AND
8654       && CONST_INT_P (XEXP (src, 1))
8655       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8656           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8657     src = XEXP (src, 0);
8658
8659   return gen_rtx_SET (VOIDmode, assign, src);
8660 }
8661 \f
8662 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8663    if so.  */
8664
8665 static rtx
8666 apply_distributive_law (rtx x)
8667 {
8668   enum rtx_code code = GET_CODE (x);
8669   enum rtx_code inner_code;
8670   rtx lhs, rhs, other;
8671   rtx tem;
8672
8673   /* Distributivity is not true for floating point as it can change the
8674      value.  So we don't do it unless -funsafe-math-optimizations.  */
8675   if (FLOAT_MODE_P (GET_MODE (x))
8676       && ! flag_unsafe_math_optimizations)
8677     return x;
8678
8679   /* The outer operation can only be one of the following:  */
8680   if (code != IOR && code != AND && code != XOR
8681       && code != PLUS && code != MINUS)
8682     return x;
8683
8684   lhs = XEXP (x, 0);
8685   rhs = XEXP (x, 1);
8686
8687   /* If either operand is a primitive we can't do anything, so get out
8688      fast.  */
8689   if (OBJECT_P (lhs) || OBJECT_P (rhs))
8690     return x;
8691
8692   lhs = expand_compound_operation (lhs);
8693   rhs = expand_compound_operation (rhs);
8694   inner_code = GET_CODE (lhs);
8695   if (inner_code != GET_CODE (rhs))
8696     return x;
8697
8698   /* See if the inner and outer operations distribute.  */
8699   switch (inner_code)
8700     {
8701     case LSHIFTRT:
8702     case ASHIFTRT:
8703     case AND:
8704     case IOR:
8705       /* These all distribute except over PLUS.  */
8706       if (code == PLUS || code == MINUS)
8707         return x;
8708       break;
8709
8710     case MULT:
8711       if (code != PLUS && code != MINUS)
8712         return x;
8713       break;
8714
8715     case ASHIFT:
8716       /* This is also a multiply, so it distributes over everything.  */
8717       break;
8718
8719     case SUBREG:
8720       /* Non-paradoxical SUBREGs distributes over all operations,
8721          provided the inner modes and byte offsets are the same, this
8722          is an extraction of a low-order part, we don't convert an fp
8723          operation to int or vice versa, this is not a vector mode,
8724          and we would not be converting a single-word operation into a
8725          multi-word operation.  The latter test is not required, but
8726          it prevents generating unneeded multi-word operations.  Some
8727          of the previous tests are redundant given the latter test,
8728          but are retained because they are required for correctness.
8729
8730          We produce the result slightly differently in this case.  */
8731
8732       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8733           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8734           || ! subreg_lowpart_p (lhs)
8735           || (GET_MODE_CLASS (GET_MODE (lhs))
8736               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8737           || (GET_MODE_SIZE (GET_MODE (lhs))
8738               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8739           || VECTOR_MODE_P (GET_MODE (lhs))
8740           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8741           /* Result might need to be truncated.  Don't change mode if
8742              explicit truncation is needed.  */
8743           || !TRULY_NOOP_TRUNCATION
8744                (GET_MODE_BITSIZE (GET_MODE (x)),
8745                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8746         return x;
8747
8748       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8749                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
8750       return gen_lowpart (GET_MODE (x), tem);
8751
8752     default:
8753       return x;
8754     }
8755
8756   /* Set LHS and RHS to the inner operands (A and B in the example
8757      above) and set OTHER to the common operand (C in the example).
8758      There is only one way to do this unless the inner operation is
8759      commutative.  */
8760   if (COMMUTATIVE_ARITH_P (lhs)
8761       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8762     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8763   else if (COMMUTATIVE_ARITH_P (lhs)
8764            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8765     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8766   else if (COMMUTATIVE_ARITH_P (lhs)
8767            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8768     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8769   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8770     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8771   else
8772     return x;
8773
8774   /* Form the new inner operation, seeing if it simplifies first.  */
8775   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8776
8777   /* There is one exception to the general way of distributing:
8778      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8779   if (code == XOR && inner_code == IOR)
8780     {
8781       inner_code = AND;
8782       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8783     }
8784
8785   /* We may be able to continuing distributing the result, so call
8786      ourselves recursively on the inner operation before forming the
8787      outer operation, which we return.  */
8788   return simplify_gen_binary (inner_code, GET_MODE (x),
8789                               apply_distributive_law (tem), other);
8790 }
8791
8792 /* See if X is of the form (* (+ A B) C), and if so convert to
8793    (+ (* A C) (* B C)) and try to simplify.
8794
8795    Most of the time, this results in no change.  However, if some of
8796    the operands are the same or inverses of each other, simplifications
8797    will result.
8798
8799    For example, (and (ior A B) (not B)) can occur as the result of
8800    expanding a bit field assignment.  When we apply the distributive
8801    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8802    which then simplifies to (and (A (not B))).
8803
8804    Note that no checks happen on the validity of applying the inverse
8805    distributive law.  This is pointless since we can do it in the
8806    few places where this routine is called.
8807
8808    N is the index of the term that is decomposed (the arithmetic operation,
8809    i.e. (+ A B) in the first example above).  !N is the index of the term that
8810    is distributed, i.e. of C in the first example above.  */
8811 static rtx
8812 distribute_and_simplify_rtx (rtx x, int n)
8813 {
8814   enum machine_mode mode;
8815   enum rtx_code outer_code, inner_code;
8816   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8817
8818   decomposed = XEXP (x, n);
8819   if (!ARITHMETIC_P (decomposed))
8820     return NULL_RTX;
8821
8822   mode = GET_MODE (x);
8823   outer_code = GET_CODE (x);
8824   distributed = XEXP (x, !n);
8825
8826   inner_code = GET_CODE (decomposed);
8827   inner_op0 = XEXP (decomposed, 0);
8828   inner_op1 = XEXP (decomposed, 1);
8829
8830   /* Special case (and (xor B C) (not A)), which is equivalent to
8831      (xor (ior A B) (ior A C))  */
8832   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8833     {
8834       distributed = XEXP (distributed, 0);
8835       outer_code = IOR;
8836     }
8837
8838   if (n == 0)
8839     {
8840       /* Distribute the second term.  */
8841       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8842       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8843     }
8844   else
8845     {
8846       /* Distribute the first term.  */
8847       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8848       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8849     }
8850
8851   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8852                                                      new_op0, new_op1));
8853   if (GET_CODE (tmp) != outer_code
8854       && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8855          < rtx_cost (x, SET, optimize_this_for_speed_p))
8856     return tmp;
8857
8858   return NULL_RTX;
8859 }
8860 \f
8861 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8862    in MODE.  Return an equivalent form, if different from (and VAROP
8863    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8864
8865 static rtx
8866 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8867                           unsigned HOST_WIDE_INT constop)
8868 {
8869   unsigned HOST_WIDE_INT nonzero;
8870   unsigned HOST_WIDE_INT orig_constop;
8871   rtx orig_varop;
8872   int i;
8873
8874   orig_varop = varop;
8875   orig_constop = constop;
8876   if (GET_CODE (varop) == CLOBBER)
8877     return NULL_RTX;
8878
8879   /* Simplify VAROP knowing that we will be only looking at some of the
8880      bits in it.
8881
8882      Note by passing in CONSTOP, we guarantee that the bits not set in
8883      CONSTOP are not significant and will never be examined.  We must
8884      ensure that is the case by explicitly masking out those bits
8885      before returning.  */
8886   varop = force_to_mode (varop, mode, constop, 0);
8887
8888   /* If VAROP is a CLOBBER, we will fail so return it.  */
8889   if (GET_CODE (varop) == CLOBBER)
8890     return varop;
8891
8892   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8893      to VAROP and return the new constant.  */
8894   if (CONST_INT_P (varop))
8895     return gen_int_mode (INTVAL (varop) & constop, mode);
8896
8897   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8898      a call to nonzero_bits, here we don't care about bits outside
8899      MODE.  */
8900
8901   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8902
8903   /* Turn off all bits in the constant that are known to already be zero.
8904      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8905      which is tested below.  */
8906
8907   constop &= nonzero;
8908
8909   /* If we don't have any bits left, return zero.  */
8910   if (constop == 0)
8911     return const0_rtx;
8912
8913   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8914      a power of two, we can replace this with an ASHIFT.  */
8915   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8916       && (i = exact_log2 (constop)) >= 0)
8917     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8918
8919   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8920      or XOR, then try to apply the distributive law.  This may eliminate
8921      operations if either branch can be simplified because of the AND.
8922      It may also make some cases more complex, but those cases probably
8923      won't match a pattern either with or without this.  */
8924
8925   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8926     return
8927       gen_lowpart
8928         (mode,
8929          apply_distributive_law
8930          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8931                                simplify_and_const_int (NULL_RTX,
8932                                                        GET_MODE (varop),
8933                                                        XEXP (varop, 0),
8934                                                        constop),
8935                                simplify_and_const_int (NULL_RTX,
8936                                                        GET_MODE (varop),
8937                                                        XEXP (varop, 1),
8938                                                        constop))));
8939
8940   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8941      the AND and see if one of the operands simplifies to zero.  If so, we
8942      may eliminate it.  */
8943
8944   if (GET_CODE (varop) == PLUS
8945       && exact_log2 (constop + 1) >= 0)
8946     {
8947       rtx o0, o1;
8948
8949       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8950       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8951       if (o0 == const0_rtx)
8952         return o1;
8953       if (o1 == const0_rtx)
8954         return o0;
8955     }
8956
8957   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8958   varop = gen_lowpart (mode, varop);
8959   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8960     return NULL_RTX;
8961
8962   /* If we are only masking insignificant bits, return VAROP.  */
8963   if (constop == nonzero)
8964     return varop;
8965
8966   if (varop == orig_varop && constop == orig_constop)
8967     return NULL_RTX;
8968
8969   /* Otherwise, return an AND.  */
8970   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8971 }
8972
8973
8974 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8975    in MODE.
8976
8977    Return an equivalent form, if different from X.  Otherwise, return X.  If
8978    X is zero, we are to always construct the equivalent form.  */
8979
8980 static rtx
8981 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8982                         unsigned HOST_WIDE_INT constop)
8983 {
8984   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8985   if (tem)
8986     return tem;
8987
8988   if (!x)
8989     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8990                              gen_int_mode (constop, mode));
8991   if (GET_MODE (x) != mode)
8992     x = gen_lowpart (mode, x);
8993   return x;
8994 }
8995 \f
8996 /* Given a REG, X, compute which bits in X can be nonzero.
8997    We don't care about bits outside of those defined in MODE.
8998
8999    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9000    a shift, AND, or zero_extract, we can do better.  */
9001
9002 static rtx
9003 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9004                               const_rtx known_x ATTRIBUTE_UNUSED,
9005                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9006                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9007                               unsigned HOST_WIDE_INT *nonzero)
9008 {
9009   rtx tem;
9010   reg_stat_type *rsp;
9011
9012   /* If X is a register whose nonzero bits value is current, use it.
9013      Otherwise, if X is a register whose value we can find, use that
9014      value.  Otherwise, use the previously-computed global nonzero bits
9015      for this register.  */
9016
9017   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9018   if (rsp->last_set_value != 0
9019       && (rsp->last_set_mode == mode
9020           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9021               && GET_MODE_CLASS (mode) == MODE_INT))
9022       && ((rsp->last_set_label >= label_tick_ebb_start
9023            && rsp->last_set_label < label_tick)
9024           || (rsp->last_set_label == label_tick
9025               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9026           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9027               && REG_N_SETS (REGNO (x)) == 1
9028               && !REGNO_REG_SET_P
9029                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9030     {
9031       *nonzero &= rsp->last_set_nonzero_bits;
9032       return NULL;
9033     }
9034
9035   tem = get_last_value (x);
9036
9037   if (tem)
9038     {
9039 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9040       /* If X is narrower than MODE and TEM is a non-negative
9041          constant that would appear negative in the mode of X,
9042          sign-extend it for use in reg_nonzero_bits because some
9043          machines (maybe most) will actually do the sign-extension
9044          and this is the conservative approach.
9045
9046          ??? For 2.5, try to tighten up the MD files in this regard
9047          instead of this kludge.  */
9048
9049       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9050           && CONST_INT_P (tem)
9051           && INTVAL (tem) > 0
9052           && 0 != (INTVAL (tem)
9053                    & ((HOST_WIDE_INT) 1
9054                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9055         tem = GEN_INT (INTVAL (tem)
9056                        | ((HOST_WIDE_INT) (-1)
9057                           << GET_MODE_BITSIZE (GET_MODE (x))));
9058 #endif
9059       return tem;
9060     }
9061   else if (nonzero_sign_valid && rsp->nonzero_bits)
9062     {
9063       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9064
9065       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9066         /* We don't know anything about the upper bits.  */
9067         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9068       *nonzero &= mask;
9069     }
9070
9071   return NULL;
9072 }
9073
9074 /* Return the number of bits at the high-order end of X that are known to
9075    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9076    VOIDmode, X will be used in its own mode.  The returned value  will always
9077    be between 1 and the number of bits in MODE.  */
9078
9079 static rtx
9080 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9081                                      const_rtx known_x ATTRIBUTE_UNUSED,
9082                                      enum machine_mode known_mode
9083                                      ATTRIBUTE_UNUSED,
9084                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9085                                      unsigned int *result)
9086 {
9087   rtx tem;
9088   reg_stat_type *rsp;
9089
9090   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9091   if (rsp->last_set_value != 0
9092       && rsp->last_set_mode == mode
9093       && ((rsp->last_set_label >= label_tick_ebb_start
9094            && rsp->last_set_label < label_tick)
9095           || (rsp->last_set_label == label_tick
9096               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9097           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9098               && REG_N_SETS (REGNO (x)) == 1
9099               && !REGNO_REG_SET_P
9100                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9101     {
9102       *result = rsp->last_set_sign_bit_copies;
9103       return NULL;
9104     }
9105
9106   tem = get_last_value (x);
9107   if (tem != 0)
9108     return tem;
9109
9110   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9111       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9112     *result = rsp->sign_bit_copies;
9113
9114   return NULL;
9115 }
9116 \f
9117 /* Return the number of "extended" bits there are in X, when interpreted
9118    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9119    unsigned quantities, this is the number of high-order zero bits.
9120    For signed quantities, this is the number of copies of the sign bit
9121    minus 1.  In both case, this function returns the number of "spare"
9122    bits.  For example, if two quantities for which this function returns
9123    at least 1 are added, the addition is known not to overflow.
9124
9125    This function will always return 0 unless called during combine, which
9126    implies that it must be called from a define_split.  */
9127
9128 unsigned int
9129 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9130 {
9131   if (nonzero_sign_valid == 0)
9132     return 0;
9133
9134   return (unsignedp
9135           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9136              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9137                                - floor_log2 (nonzero_bits (x, mode)))
9138              : 0)
9139           : num_sign_bit_copies (x, mode) - 1);
9140 }
9141 \f
9142 /* This function is called from `simplify_shift_const' to merge two
9143    outer operations.  Specifically, we have already found that we need
9144    to perform operation *POP0 with constant *PCONST0 at the outermost
9145    position.  We would now like to also perform OP1 with constant CONST1
9146    (with *POP0 being done last).
9147
9148    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9149    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9150    complement the innermost operand, otherwise it is unchanged.
9151
9152    MODE is the mode in which the operation will be done.  No bits outside
9153    the width of this mode matter.  It is assumed that the width of this mode
9154    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9155
9156    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9157    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9158    result is simply *PCONST0.
9159
9160    If the resulting operation cannot be expressed as one operation, we
9161    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9162
9163 static int
9164 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9165 {
9166   enum rtx_code op0 = *pop0;
9167   HOST_WIDE_INT const0 = *pconst0;
9168
9169   const0 &= GET_MODE_MASK (mode);
9170   const1 &= GET_MODE_MASK (mode);
9171
9172   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9173   if (op0 == AND)
9174     const1 &= const0;
9175
9176   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9177      if OP0 is SET.  */
9178
9179   if (op1 == UNKNOWN || op0 == SET)
9180     return 1;
9181
9182   else if (op0 == UNKNOWN)
9183     op0 = op1, const0 = const1;
9184
9185   else if (op0 == op1)
9186     {
9187       switch (op0)
9188         {
9189         case AND:
9190           const0 &= const1;
9191           break;
9192         case IOR:
9193           const0 |= const1;
9194           break;
9195         case XOR:
9196           const0 ^= const1;
9197           break;
9198         case PLUS:
9199           const0 += const1;
9200           break;
9201         case NEG:
9202           op0 = UNKNOWN;
9203           break;
9204         default:
9205           break;
9206         }
9207     }
9208
9209   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9210   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9211     return 0;
9212
9213   /* If the two constants aren't the same, we can't do anything.  The
9214      remaining six cases can all be done.  */
9215   else if (const0 != const1)
9216     return 0;
9217
9218   else
9219     switch (op0)
9220       {
9221       case IOR:
9222         if (op1 == AND)
9223           /* (a & b) | b == b */
9224           op0 = SET;
9225         else /* op1 == XOR */
9226           /* (a ^ b) | b == a | b */
9227           {;}
9228         break;
9229
9230       case XOR:
9231         if (op1 == AND)
9232           /* (a & b) ^ b == (~a) & b */
9233           op0 = AND, *pcomp_p = 1;
9234         else /* op1 == IOR */
9235           /* (a | b) ^ b == a & ~b */
9236           op0 = AND, const0 = ~const0;
9237         break;
9238
9239       case AND:
9240         if (op1 == IOR)
9241           /* (a | b) & b == b */
9242         op0 = SET;
9243         else /* op1 == XOR */
9244           /* (a ^ b) & b) == (~a) & b */
9245           *pcomp_p = 1;
9246         break;
9247       default:
9248         break;
9249       }
9250
9251   /* Check for NO-OP cases.  */
9252   const0 &= GET_MODE_MASK (mode);
9253   if (const0 == 0
9254       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9255     op0 = UNKNOWN;
9256   else if (const0 == 0 && op0 == AND)
9257     op0 = SET;
9258   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9259            && op0 == AND)
9260     op0 = UNKNOWN;
9261
9262   *pop0 = op0;
9263
9264   /* ??? Slightly redundant with the above mask, but not entirely.
9265      Moving this above means we'd have to sign-extend the mode mask
9266      for the final test.  */
9267   if (op0 != UNKNOWN && op0 != NEG)
9268     *pconst0 = trunc_int_for_mode (const0, mode);
9269
9270   return 1;
9271 }
9272 \f
9273 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9274    the shift in.  The original shift operation CODE is performed on OP in
9275    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9276    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9277    result of the shift is subject to operation OUTER_CODE with operand
9278    OUTER_CONST.  */
9279
9280 static enum machine_mode
9281 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9282                       enum machine_mode orig_mode, enum machine_mode mode,
9283                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9284 {
9285   if (orig_mode == mode)
9286     return mode;
9287   gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9288
9289   /* In general we can't perform in wider mode for right shift and rotate.  */
9290   switch (code)
9291     {
9292     case ASHIFTRT:
9293       /* We can still widen if the bits brought in from the left are identical
9294          to the sign bit of ORIG_MODE.  */
9295       if (num_sign_bit_copies (op, mode)
9296           > (unsigned) (GET_MODE_BITSIZE (mode)
9297                         - GET_MODE_BITSIZE (orig_mode)))
9298         return mode;
9299       return orig_mode;
9300
9301     case LSHIFTRT:
9302       /* Similarly here but with zero bits.  */
9303       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9304           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9305         return mode;
9306
9307       /* We can also widen if the bits brought in will be masked off.  This
9308          operation is performed in ORIG_MODE.  */
9309       if (outer_code == AND)
9310         {
9311           int care_bits = low_bitmask_len (orig_mode, outer_const);
9312
9313           if (care_bits >= 0
9314               && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9315             return mode;
9316         }
9317       /* fall through */
9318
9319     case ROTATE:
9320       return orig_mode;
9321
9322     case ROTATERT:
9323       gcc_unreachable ();
9324
9325     default:
9326       return mode;
9327     }
9328 }
9329
9330 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9331    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
9332    simplify it.  Otherwise, return a simplified value.
9333
9334    The shift is normally computed in the widest mode we find in VAROP, as
9335    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9336    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9337
9338 static rtx
9339 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9340                         rtx varop, int orig_count)
9341 {
9342   enum rtx_code orig_code = code;
9343   rtx orig_varop = varop;
9344   int count;
9345   enum machine_mode mode = result_mode;
9346   enum machine_mode shift_mode, tmode;
9347   unsigned int mode_words
9348     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9349   /* We form (outer_op (code varop count) (outer_const)).  */
9350   enum rtx_code outer_op = UNKNOWN;
9351   HOST_WIDE_INT outer_const = 0;
9352   int complement_p = 0;
9353   rtx new_rtx, x;
9354
9355   /* Make sure and truncate the "natural" shift on the way in.  We don't
9356      want to do this inside the loop as it makes it more difficult to
9357      combine shifts.  */
9358   if (SHIFT_COUNT_TRUNCATED)
9359     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9360
9361   /* If we were given an invalid count, don't do anything except exactly
9362      what was requested.  */
9363
9364   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9365     return NULL_RTX;
9366
9367   count = orig_count;
9368
9369   /* Unless one of the branches of the `if' in this loop does a `continue',
9370      we will `break' the loop after the `if'.  */
9371
9372   while (count != 0)
9373     {
9374       /* If we have an operand of (clobber (const_int 0)), fail.  */
9375       if (GET_CODE (varop) == CLOBBER)
9376         return NULL_RTX;
9377
9378       /* Convert ROTATERT to ROTATE.  */
9379       if (code == ROTATERT)
9380         {
9381           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9382           code = ROTATE;
9383           if (VECTOR_MODE_P (result_mode))
9384             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9385           else
9386             count = bitsize - count;
9387         }
9388
9389       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9390                                          mode, outer_op, outer_const);
9391
9392       /* Handle cases where the count is greater than the size of the mode
9393          minus 1.  For ASHIFT, use the size minus one as the count (this can
9394          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9395          take the count modulo the size.  For other shifts, the result is
9396          zero.
9397
9398          Since these shifts are being produced by the compiler by combining
9399          multiple operations, each of which are defined, we know what the
9400          result is supposed to be.  */
9401
9402       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9403         {
9404           if (code == ASHIFTRT)
9405             count = GET_MODE_BITSIZE (shift_mode) - 1;
9406           else if (code == ROTATE || code == ROTATERT)
9407             count %= GET_MODE_BITSIZE (shift_mode);
9408           else
9409             {
9410               /* We can't simply return zero because there may be an
9411                  outer op.  */
9412               varop = const0_rtx;
9413               count = 0;
9414               break;
9415             }
9416         }
9417
9418       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9419          here would cause an infinite loop.  */
9420       if (complement_p)
9421         break;
9422
9423       /* An arithmetic right shift of a quantity known to be -1 or 0
9424          is a no-op.  */
9425       if (code == ASHIFTRT
9426           && (num_sign_bit_copies (varop, shift_mode)
9427               == GET_MODE_BITSIZE (shift_mode)))
9428         {
9429           count = 0;
9430           break;
9431         }
9432
9433       /* If we are doing an arithmetic right shift and discarding all but
9434          the sign bit copies, this is equivalent to doing a shift by the
9435          bitsize minus one.  Convert it into that shift because it will often
9436          allow other simplifications.  */
9437
9438       if (code == ASHIFTRT
9439           && (count + num_sign_bit_copies (varop, shift_mode)
9440               >= GET_MODE_BITSIZE (shift_mode)))
9441         count = GET_MODE_BITSIZE (shift_mode) - 1;
9442
9443       /* We simplify the tests below and elsewhere by converting
9444          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9445          `make_compound_operation' will convert it to an ASHIFTRT for
9446          those machines (such as VAX) that don't have an LSHIFTRT.  */
9447       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9448           && code == ASHIFTRT
9449           && ((nonzero_bits (varop, shift_mode)
9450                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9451               == 0))
9452         code = LSHIFTRT;
9453
9454       if (((code == LSHIFTRT
9455             && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9456             && !(nonzero_bits (varop, shift_mode) >> count))
9457            || (code == ASHIFT
9458                && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9459                && !((nonzero_bits (varop, shift_mode) << count)
9460                     & GET_MODE_MASK (shift_mode))))
9461           && !side_effects_p (varop))
9462         varop = const0_rtx;
9463
9464       switch (GET_CODE (varop))
9465         {
9466         case SIGN_EXTEND:
9467         case ZERO_EXTEND:
9468         case SIGN_EXTRACT:
9469         case ZERO_EXTRACT:
9470           new_rtx = expand_compound_operation (varop);
9471           if (new_rtx != varop)
9472             {
9473               varop = new_rtx;
9474               continue;
9475             }
9476           break;
9477
9478         case MEM:
9479           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9480              minus the width of a smaller mode, we can do this with a
9481              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9482           if ((code == ASHIFTRT || code == LSHIFTRT)
9483               && ! mode_dependent_address_p (XEXP (varop, 0))
9484               && ! MEM_VOLATILE_P (varop)
9485               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9486                                          MODE_INT, 1)) != BLKmode)
9487             {
9488               new_rtx = adjust_address_nv (varop, tmode,
9489                                        BYTES_BIG_ENDIAN ? 0
9490                                        : count / BITS_PER_UNIT);
9491
9492               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9493                                      : ZERO_EXTEND, mode, new_rtx);
9494               count = 0;
9495               continue;
9496             }
9497           break;
9498
9499         case SUBREG:
9500           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9501              the same number of words as what we've seen so far.  Then store
9502              the widest mode in MODE.  */
9503           if (subreg_lowpart_p (varop)
9504               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9505                   > GET_MODE_SIZE (GET_MODE (varop)))
9506               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9507                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9508                  == mode_words)
9509             {
9510               varop = SUBREG_REG (varop);
9511               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9512                 mode = GET_MODE (varop);
9513               continue;
9514             }
9515           break;
9516
9517         case MULT:
9518           /* Some machines use MULT instead of ASHIFT because MULT
9519              is cheaper.  But it is still better on those machines to
9520              merge two shifts into one.  */
9521           if (CONST_INT_P (XEXP (varop, 1))
9522               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9523             {
9524               varop
9525                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9526                                        XEXP (varop, 0),
9527                                        GEN_INT (exact_log2 (
9528                                                 INTVAL (XEXP (varop, 1)))));
9529               continue;
9530             }
9531           break;
9532
9533         case UDIV:
9534           /* Similar, for when divides are cheaper.  */
9535           if (CONST_INT_P (XEXP (varop, 1))
9536               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9537             {
9538               varop
9539                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9540                                        XEXP (varop, 0),
9541                                        GEN_INT (exact_log2 (
9542                                                 INTVAL (XEXP (varop, 1)))));
9543               continue;
9544             }
9545           break;
9546
9547         case ASHIFTRT:
9548           /* If we are extracting just the sign bit of an arithmetic
9549              right shift, that shift is not needed.  However, the sign
9550              bit of a wider mode may be different from what would be
9551              interpreted as the sign bit in a narrower mode, so, if
9552              the result is narrower, don't discard the shift.  */
9553           if (code == LSHIFTRT
9554               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9555               && (GET_MODE_BITSIZE (result_mode)
9556                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
9557             {
9558               varop = XEXP (varop, 0);
9559               continue;
9560             }
9561
9562           /* ... fall through ...  */
9563
9564         case LSHIFTRT:
9565         case ASHIFT:
9566         case ROTATE:
9567           /* Here we have two nested shifts.  The result is usually the
9568              AND of a new shift with a mask.  We compute the result below.  */
9569           if (CONST_INT_P (XEXP (varop, 1))
9570               && INTVAL (XEXP (varop, 1)) >= 0
9571               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9572               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9573               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9574               && !VECTOR_MODE_P (result_mode))
9575             {
9576               enum rtx_code first_code = GET_CODE (varop);
9577               unsigned int first_count = INTVAL (XEXP (varop, 1));
9578               unsigned HOST_WIDE_INT mask;
9579               rtx mask_rtx;
9580
9581               /* We have one common special case.  We can't do any merging if
9582                  the inner code is an ASHIFTRT of a smaller mode.  However, if
9583                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9584                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9585                  we can convert it to
9586                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9587                  This simplifies certain SIGN_EXTEND operations.  */
9588               if (code == ASHIFT && first_code == ASHIFTRT
9589                   && count == (GET_MODE_BITSIZE (result_mode)
9590                                - GET_MODE_BITSIZE (GET_MODE (varop))))
9591                 {
9592                   /* C3 has the low-order C1 bits zero.  */
9593
9594                   mask = (GET_MODE_MASK (mode)
9595                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9596
9597                   varop = simplify_and_const_int (NULL_RTX, result_mode,
9598                                                   XEXP (varop, 0), mask);
9599                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9600                                                 varop, count);
9601                   count = first_count;
9602                   code = ASHIFTRT;
9603                   continue;
9604                 }
9605
9606               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9607                  than C1 high-order bits equal to the sign bit, we can convert
9608                  this to either an ASHIFT or an ASHIFTRT depending on the
9609                  two counts.
9610
9611                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
9612
9613               if (code == ASHIFTRT && first_code == ASHIFT
9614                   && GET_MODE (varop) == shift_mode
9615                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9616                       > first_count))
9617                 {
9618                   varop = XEXP (varop, 0);
9619                   count -= first_count;
9620                   if (count < 0)
9621                     {
9622                       count = -count;
9623                       code = ASHIFT;
9624                     }
9625
9626                   continue;
9627                 }
9628
9629               /* There are some cases we can't do.  If CODE is ASHIFTRT,
9630                  we can only do this if FIRST_CODE is also ASHIFTRT.
9631
9632                  We can't do the case when CODE is ROTATE and FIRST_CODE is
9633                  ASHIFTRT.
9634
9635                  If the mode of this shift is not the mode of the outer shift,
9636                  we can't do this if either shift is a right shift or ROTATE.
9637
9638                  Finally, we can't do any of these if the mode is too wide
9639                  unless the codes are the same.
9640
9641                  Handle the case where the shift codes are the same
9642                  first.  */
9643
9644               if (code == first_code)
9645                 {
9646                   if (GET_MODE (varop) != result_mode
9647                       && (code == ASHIFTRT || code == LSHIFTRT
9648                           || code == ROTATE))
9649                     break;
9650
9651                   count += first_count;
9652                   varop = XEXP (varop, 0);
9653                   continue;
9654                 }
9655
9656               if (code == ASHIFTRT
9657                   || (code == ROTATE && first_code == ASHIFTRT)
9658                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9659                   || (GET_MODE (varop) != result_mode
9660                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
9661                           || first_code == ROTATE
9662                           || code == ROTATE)))
9663                 break;
9664
9665               /* To compute the mask to apply after the shift, shift the
9666                  nonzero bits of the inner shift the same way the
9667                  outer shift will.  */
9668
9669               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9670
9671               mask_rtx
9672                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9673                                                    GEN_INT (count));
9674
9675               /* Give up if we can't compute an outer operation to use.  */
9676               if (mask_rtx == 0
9677                   || !CONST_INT_P (mask_rtx)
9678                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
9679                                         INTVAL (mask_rtx),
9680                                         result_mode, &complement_p))
9681                 break;
9682
9683               /* If the shifts are in the same direction, we add the
9684                  counts.  Otherwise, we subtract them.  */
9685               if ((code == ASHIFTRT || code == LSHIFTRT)
9686                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9687                 count += first_count;
9688               else
9689                 count -= first_count;
9690
9691               /* If COUNT is positive, the new shift is usually CODE,
9692                  except for the two exceptions below, in which case it is
9693                  FIRST_CODE.  If the count is negative, FIRST_CODE should
9694                  always be used  */
9695               if (count > 0
9696                   && ((first_code == ROTATE && code == ASHIFT)
9697                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
9698                 code = first_code;
9699               else if (count < 0)
9700                 code = first_code, count = -count;
9701
9702               varop = XEXP (varop, 0);
9703               continue;
9704             }
9705
9706           /* If we have (A << B << C) for any shift, we can convert this to
9707              (A << C << B).  This wins if A is a constant.  Only try this if
9708              B is not a constant.  */
9709
9710           else if (GET_CODE (varop) == code
9711                    && CONST_INT_P (XEXP (varop, 0))
9712                    && !CONST_INT_P (XEXP (varop, 1)))
9713             {
9714               rtx new_rtx = simplify_const_binary_operation (code, mode,
9715                                                          XEXP (varop, 0),
9716                                                          GEN_INT (count));
9717               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9718               count = 0;
9719               continue;
9720             }
9721           break;
9722
9723         case NOT:
9724           if (VECTOR_MODE_P (mode))
9725             break;
9726
9727           /* Make this fit the case below.  */
9728           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9729                                GEN_INT (GET_MODE_MASK (mode)));
9730           continue;
9731
9732         case IOR:
9733         case AND:
9734         case XOR:
9735           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9736              with C the size of VAROP - 1 and the shift is logical if
9737              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9738              we have an (le X 0) operation.   If we have an arithmetic shift
9739              and STORE_FLAG_VALUE is 1 or we have a logical shift with
9740              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
9741
9742           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9743               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9744               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9745               && (code == LSHIFTRT || code == ASHIFTRT)
9746               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9747               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9748             {
9749               count = 0;
9750               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9751                                   const0_rtx);
9752
9753               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9754                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9755
9756               continue;
9757             }
9758
9759           /* If we have (shift (logical)), move the logical to the outside
9760              to allow it to possibly combine with another logical and the
9761              shift to combine with another shift.  This also canonicalizes to
9762              what a ZERO_EXTRACT looks like.  Also, some machines have
9763              (and (shift)) insns.  */
9764
9765           if (CONST_INT_P (XEXP (varop, 1))
9766               /* We can't do this if we have (ashiftrt (xor))  and the
9767                  constant has its sign bit set in shift_mode.  */
9768               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9769                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9770                                               shift_mode))
9771               && (new_rtx = simplify_const_binary_operation (code, result_mode,
9772                                                          XEXP (varop, 1),
9773                                                          GEN_INT (count))) != 0
9774               && CONST_INT_P (new_rtx)
9775               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9776                                   INTVAL (new_rtx), result_mode, &complement_p))
9777             {
9778               varop = XEXP (varop, 0);
9779               continue;
9780             }
9781
9782           /* If we can't do that, try to simplify the shift in each arm of the
9783              logical expression, make a new logical expression, and apply
9784              the inverse distributive law.  This also can't be done
9785              for some (ashiftrt (xor)).  */
9786           if (CONST_INT_P (XEXP (varop, 1))
9787              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9788                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9789                                              shift_mode)))
9790             {
9791               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9792                                               XEXP (varop, 0), count);
9793               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9794                                               XEXP (varop, 1), count);
9795
9796               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9797                                            lhs, rhs);
9798               varop = apply_distributive_law (varop);
9799
9800               count = 0;
9801               continue;
9802             }
9803           break;
9804
9805         case EQ:
9806           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9807              says that the sign bit can be tested, FOO has mode MODE, C is
9808              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9809              that may be nonzero.  */
9810           if (code == LSHIFTRT
9811               && XEXP (varop, 1) == const0_rtx
9812               && GET_MODE (XEXP (varop, 0)) == result_mode
9813               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9814               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9815               && STORE_FLAG_VALUE == -1
9816               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9817               && merge_outer_ops (&outer_op, &outer_const, XOR,
9818                                   (HOST_WIDE_INT) 1, result_mode,
9819                                   &complement_p))
9820             {
9821               varop = XEXP (varop, 0);
9822               count = 0;
9823               continue;
9824             }
9825           break;
9826
9827         case NEG:
9828           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9829              than the number of bits in the mode is equivalent to A.  */
9830           if (code == LSHIFTRT
9831               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9832               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9833             {
9834               varop = XEXP (varop, 0);
9835               count = 0;
9836               continue;
9837             }
9838
9839           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9840              NEG outside to allow shifts to combine.  */
9841           if (code == ASHIFT
9842               && merge_outer_ops (&outer_op, &outer_const, NEG,
9843                                   (HOST_WIDE_INT) 0, result_mode,
9844                                   &complement_p))
9845             {
9846               varop = XEXP (varop, 0);
9847               continue;
9848             }
9849           break;
9850
9851         case PLUS:
9852           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9853              is one less than the number of bits in the mode is
9854              equivalent to (xor A 1).  */
9855           if (code == LSHIFTRT
9856               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9857               && XEXP (varop, 1) == constm1_rtx
9858               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9859               && merge_outer_ops (&outer_op, &outer_const, XOR,
9860                                   (HOST_WIDE_INT) 1, result_mode,
9861                                   &complement_p))
9862             {
9863               count = 0;
9864               varop = XEXP (varop, 0);
9865               continue;
9866             }
9867
9868           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9869              that might be nonzero in BAR are those being shifted out and those
9870              bits are known zero in FOO, we can replace the PLUS with FOO.
9871              Similarly in the other operand order.  This code occurs when
9872              we are computing the size of a variable-size array.  */
9873
9874           if ((code == ASHIFTRT || code == LSHIFTRT)
9875               && count < HOST_BITS_PER_WIDE_INT
9876               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9877               && (nonzero_bits (XEXP (varop, 1), result_mode)
9878                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9879             {
9880               varop = XEXP (varop, 0);
9881               continue;
9882             }
9883           else if ((code == ASHIFTRT || code == LSHIFTRT)
9884                    && count < HOST_BITS_PER_WIDE_INT
9885                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9886                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9887                             >> count)
9888                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9889                             & nonzero_bits (XEXP (varop, 1),
9890                                                  result_mode)))
9891             {
9892               varop = XEXP (varop, 1);
9893               continue;
9894             }
9895
9896           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9897           if (code == ASHIFT
9898               && CONST_INT_P (XEXP (varop, 1))
9899               && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9900                                                          XEXP (varop, 1),
9901                                                          GEN_INT (count))) != 0
9902               && CONST_INT_P (new_rtx)
9903               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9904                                   INTVAL (new_rtx), result_mode, &complement_p))
9905             {
9906               varop = XEXP (varop, 0);
9907               continue;
9908             }
9909
9910           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9911              signbit', and attempt to change the PLUS to an XOR and move it to
9912              the outer operation as is done above in the AND/IOR/XOR case
9913              leg for shift(logical). See details in logical handling above
9914              for reasoning in doing so.  */
9915           if (code == LSHIFTRT
9916               && CONST_INT_P (XEXP (varop, 1))
9917               && mode_signbit_p (result_mode, XEXP (varop, 1))
9918               && (new_rtx = simplify_const_binary_operation (code, result_mode,
9919                                                          XEXP (varop, 1),
9920                                                          GEN_INT (count))) != 0
9921               && CONST_INT_P (new_rtx)
9922               && merge_outer_ops (&outer_op, &outer_const, XOR,
9923                                   INTVAL (new_rtx), result_mode, &complement_p))
9924             {
9925               varop = XEXP (varop, 0);
9926               continue;
9927             }
9928
9929           break;
9930
9931         case MINUS:
9932           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9933              with C the size of VAROP - 1 and the shift is logical if
9934              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9935              we have a (gt X 0) operation.  If the shift is arithmetic with
9936              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9937              we have a (neg (gt X 0)) operation.  */
9938
9939           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9940               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9941               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9942               && (code == LSHIFTRT || code == ASHIFTRT)
9943               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9944               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9945               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9946             {
9947               count = 0;
9948               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9949                                   const0_rtx);
9950
9951               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9952                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9953
9954               continue;
9955             }
9956           break;
9957
9958         case TRUNCATE:
9959           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9960              if the truncate does not affect the value.  */
9961           if (code == LSHIFTRT
9962               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9963               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9964               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9965                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9966                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9967             {
9968               rtx varop_inner = XEXP (varop, 0);
9969
9970               varop_inner
9971                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9972                                     XEXP (varop_inner, 0),
9973                                     GEN_INT
9974                                     (count + INTVAL (XEXP (varop_inner, 1))));
9975               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9976               count = 0;
9977               continue;
9978             }
9979           break;
9980
9981         default:
9982           break;
9983         }
9984
9985       break;
9986     }
9987
9988   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
9989                                      outer_op, outer_const);
9990
9991   /* We have now finished analyzing the shift.  The result should be
9992      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9993      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9994      to the result of the shift.  OUTER_CONST is the relevant constant,
9995      but we must turn off all bits turned off in the shift.  */
9996
9997   if (outer_op == UNKNOWN
9998       && orig_code == code && orig_count == count
9999       && varop == orig_varop
10000       && shift_mode == GET_MODE (varop))
10001     return NULL_RTX;
10002
10003   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10004   varop = gen_lowpart (shift_mode, varop);
10005   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10006     return NULL_RTX;
10007
10008   /* If we have an outer operation and we just made a shift, it is
10009      possible that we could have simplified the shift were it not
10010      for the outer operation.  So try to do the simplification
10011      recursively.  */
10012
10013   if (outer_op != UNKNOWN)
10014     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10015   else
10016     x = NULL_RTX;
10017
10018   if (x == NULL_RTX)
10019     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10020
10021   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10022      turn off all the bits that the shift would have turned off.  */
10023   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10024     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10025                                 GET_MODE_MASK (result_mode) >> orig_count);
10026
10027   /* Do the remainder of the processing in RESULT_MODE.  */
10028   x = gen_lowpart_or_truncate (result_mode, x);
10029
10030   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10031      operation.  */
10032   if (complement_p)
10033     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10034
10035   if (outer_op != UNKNOWN)
10036     {
10037       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10038           && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10039         outer_const = trunc_int_for_mode (outer_const, result_mode);
10040
10041       if (outer_op == AND)
10042         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10043       else if (outer_op == SET)
10044         {
10045           /* This means that we have determined that the result is
10046              equivalent to a constant.  This should be rare.  */
10047           if (!side_effects_p (x))
10048             x = GEN_INT (outer_const);
10049         }
10050       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10051         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10052       else
10053         x = simplify_gen_binary (outer_op, result_mode, x,
10054                                  GEN_INT (outer_const));
10055     }
10056
10057   return x;
10058 }
10059
10060 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10061    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10062    return X or, if it is NULL, synthesize the expression with
10063    simplify_gen_binary.  Otherwise, return a simplified value.
10064
10065    The shift is normally computed in the widest mode we find in VAROP, as
10066    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10067    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10068
10069 static rtx
10070 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10071                       rtx varop, int count)
10072 {
10073   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10074   if (tem)
10075     return tem;
10076
10077   if (!x)
10078     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10079   if (GET_MODE (x) != result_mode)
10080     x = gen_lowpart (result_mode, x);
10081   return x;
10082 }
10083
10084 \f
10085 /* Like recog, but we receive the address of a pointer to a new pattern.
10086    We try to match the rtx that the pointer points to.
10087    If that fails, we may try to modify or replace the pattern,
10088    storing the replacement into the same pointer object.
10089
10090    Modifications include deletion or addition of CLOBBERs.
10091
10092    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10093    the CLOBBERs are placed.
10094
10095    The value is the final insn code from the pattern ultimately matched,
10096    or -1.  */
10097
10098 static int
10099 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10100 {
10101   rtx pat = *pnewpat;
10102   int insn_code_number;
10103   int num_clobbers_to_add = 0;
10104   int i;
10105   rtx notes = 0;
10106   rtx old_notes, old_pat;
10107
10108   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10109      we use to indicate that something didn't match.  If we find such a
10110      thing, force rejection.  */
10111   if (GET_CODE (pat) == PARALLEL)
10112     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10113       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10114           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10115         return -1;
10116
10117   old_pat = PATTERN (insn);
10118   old_notes = REG_NOTES (insn);
10119   PATTERN (insn) = pat;
10120   REG_NOTES (insn) = 0;
10121
10122   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10123   if (dump_file && (dump_flags & TDF_DETAILS))
10124     {
10125       if (insn_code_number < 0)
10126         fputs ("Failed to match this instruction:\n", dump_file);
10127       else
10128         fputs ("Successfully matched this instruction:\n", dump_file);
10129       print_rtl_single (dump_file, pat);
10130     }
10131
10132   /* If it isn't, there is the possibility that we previously had an insn
10133      that clobbered some register as a side effect, but the combined
10134      insn doesn't need to do that.  So try once more without the clobbers
10135      unless this represents an ASM insn.  */
10136
10137   if (insn_code_number < 0 && ! check_asm_operands (pat)
10138       && GET_CODE (pat) == PARALLEL)
10139     {
10140       int pos;
10141
10142       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10143         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10144           {
10145             if (i != pos)
10146               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10147             pos++;
10148           }
10149
10150       SUBST_INT (XVECLEN (pat, 0), pos);
10151
10152       if (pos == 1)
10153         pat = XVECEXP (pat, 0, 0);
10154
10155       PATTERN (insn) = pat;
10156       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10157       if (dump_file && (dump_flags & TDF_DETAILS))
10158         {
10159           if (insn_code_number < 0)
10160             fputs ("Failed to match this instruction:\n", dump_file);
10161           else
10162             fputs ("Successfully matched this instruction:\n", dump_file);
10163           print_rtl_single (dump_file, pat);
10164         }
10165     }
10166   PATTERN (insn) = old_pat;
10167   REG_NOTES (insn) = old_notes;
10168
10169   /* Recognize all noop sets, these will be killed by followup pass.  */
10170   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10171     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10172
10173   /* If we had any clobbers to add, make a new pattern than contains
10174      them.  Then check to make sure that all of them are dead.  */
10175   if (num_clobbers_to_add)
10176     {
10177       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10178                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10179                                                   ? (XVECLEN (pat, 0)
10180                                                      + num_clobbers_to_add)
10181                                                   : num_clobbers_to_add + 1));
10182
10183       if (GET_CODE (pat) == PARALLEL)
10184         for (i = 0; i < XVECLEN (pat, 0); i++)
10185           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10186       else
10187         XVECEXP (newpat, 0, 0) = pat;
10188
10189       add_clobbers (newpat, insn_code_number);
10190
10191       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10192            i < XVECLEN (newpat, 0); i++)
10193         {
10194           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10195               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10196             return -1;
10197           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10198             {
10199               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10200               notes = alloc_reg_note (REG_UNUSED,
10201                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10202             }
10203         }
10204       pat = newpat;
10205     }
10206
10207   *pnewpat = pat;
10208   *pnotes = notes;
10209
10210   return insn_code_number;
10211 }
10212 \f
10213 /* Like gen_lowpart_general but for use by combine.  In combine it
10214    is not possible to create any new pseudoregs.  However, it is
10215    safe to create invalid memory addresses, because combine will
10216    try to recognize them and all they will do is make the combine
10217    attempt fail.
10218
10219    If for some reason this cannot do its job, an rtx
10220    (clobber (const_int 0)) is returned.
10221    An insn containing that will not be recognized.  */
10222
10223 static rtx
10224 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10225 {
10226   enum machine_mode imode = GET_MODE (x);
10227   unsigned int osize = GET_MODE_SIZE (omode);
10228   unsigned int isize = GET_MODE_SIZE (imode);
10229   rtx result;
10230
10231   if (omode == imode)
10232     return x;
10233
10234   /* Return identity if this is a CONST or symbolic reference.  */
10235   if (omode == Pmode
10236       && (GET_CODE (x) == CONST
10237           || GET_CODE (x) == SYMBOL_REF
10238           || GET_CODE (x) == LABEL_REF))
10239     return x;
10240
10241   /* We can only support MODE being wider than a word if X is a
10242      constant integer or has a mode the same size.  */
10243   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10244       && ! ((imode == VOIDmode
10245              && (CONST_INT_P (x)
10246                  || GET_CODE (x) == CONST_DOUBLE))
10247             || isize == osize))
10248     goto fail;
10249
10250   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10251      won't know what to do.  So we will strip off the SUBREG here and
10252      process normally.  */
10253   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10254     {
10255       x = SUBREG_REG (x);
10256
10257       /* For use in case we fall down into the address adjustments
10258          further below, we need to adjust the known mode and size of
10259          x; imode and isize, since we just adjusted x.  */
10260       imode = GET_MODE (x);
10261
10262       if (imode == omode)
10263         return x;
10264
10265       isize = GET_MODE_SIZE (imode);
10266     }
10267
10268   result = gen_lowpart_common (omode, x);
10269
10270   if (result)
10271     return result;
10272
10273   if (MEM_P (x))
10274     {
10275       int offset = 0;
10276
10277       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10278          address.  */
10279       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10280         goto fail;
10281
10282       /* If we want to refer to something bigger than the original memref,
10283          generate a paradoxical subreg instead.  That will force a reload
10284          of the original memref X.  */
10285       if (isize < osize)
10286         return gen_rtx_SUBREG (omode, x, 0);
10287
10288       if (WORDS_BIG_ENDIAN)
10289         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10290
10291       /* Adjust the address so that the address-after-the-data is
10292          unchanged.  */
10293       if (BYTES_BIG_ENDIAN)
10294         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10295
10296       return adjust_address_nv (x, omode, offset);
10297     }
10298
10299   /* If X is a comparison operator, rewrite it in a new mode.  This
10300      probably won't match, but may allow further simplifications.  */
10301   else if (COMPARISON_P (x))
10302     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10303
10304   /* If we couldn't simplify X any other way, just enclose it in a
10305      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10306      include an explicit SUBREG or we may simplify it further in combine.  */
10307   else
10308     {
10309       int offset = 0;
10310       rtx res;
10311
10312       offset = subreg_lowpart_offset (omode, imode);
10313       if (imode == VOIDmode)
10314         {
10315           imode = int_mode_for_mode (omode);
10316           x = gen_lowpart_common (imode, x);
10317           if (x == NULL)
10318             goto fail;
10319         }
10320       res = simplify_gen_subreg (omode, x, imode, offset);
10321       if (res)
10322         return res;
10323     }
10324
10325  fail:
10326   return gen_rtx_CLOBBER (omode, const0_rtx);
10327 }
10328 \f
10329 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10330    comparison code that will be tested.
10331
10332    The result is a possibly different comparison code to use.  *POP0 and
10333    *POP1 may be updated.
10334
10335    It is possible that we might detect that a comparison is either always
10336    true or always false.  However, we do not perform general constant
10337    folding in combine, so this knowledge isn't useful.  Such tautologies
10338    should have been detected earlier.  Hence we ignore all such cases.  */
10339
10340 static enum rtx_code
10341 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10342 {
10343   rtx op0 = *pop0;
10344   rtx op1 = *pop1;
10345   rtx tem, tem1;
10346   int i;
10347   enum machine_mode mode, tmode;
10348
10349   /* Try a few ways of applying the same transformation to both operands.  */
10350   while (1)
10351     {
10352 #ifndef WORD_REGISTER_OPERATIONS
10353       /* The test below this one won't handle SIGN_EXTENDs on these machines,
10354          so check specially.  */
10355       if (code != GTU && code != GEU && code != LTU && code != LEU
10356           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10357           && GET_CODE (XEXP (op0, 0)) == ASHIFT
10358           && GET_CODE (XEXP (op1, 0)) == ASHIFT
10359           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10360           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10361           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10362               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10363           && CONST_INT_P (XEXP (op0, 1))
10364           && XEXP (op0, 1) == XEXP (op1, 1)
10365           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10366           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10367           && (INTVAL (XEXP (op0, 1))
10368               == (GET_MODE_BITSIZE (GET_MODE (op0))
10369                   - (GET_MODE_BITSIZE
10370                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10371         {
10372           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10373           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10374         }
10375 #endif
10376
10377       /* If both operands are the same constant shift, see if we can ignore the
10378          shift.  We can if the shift is a rotate or if the bits shifted out of
10379          this shift are known to be zero for both inputs and if the type of
10380          comparison is compatible with the shift.  */
10381       if (GET_CODE (op0) == GET_CODE (op1)
10382           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10383           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10384               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10385                   && (code != GT && code != LT && code != GE && code != LE))
10386               || (GET_CODE (op0) == ASHIFTRT
10387                   && (code != GTU && code != LTU
10388                       && code != GEU && code != LEU)))
10389           && CONST_INT_P (XEXP (op0, 1))
10390           && INTVAL (XEXP (op0, 1)) >= 0
10391           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10392           && XEXP (op0, 1) == XEXP (op1, 1))
10393         {
10394           enum machine_mode mode = GET_MODE (op0);
10395           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10396           int shift_count = INTVAL (XEXP (op0, 1));
10397
10398           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10399             mask &= (mask >> shift_count) << shift_count;
10400           else if (GET_CODE (op0) == ASHIFT)
10401             mask = (mask & (mask << shift_count)) >> shift_count;
10402
10403           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10404               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10405             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10406           else
10407             break;
10408         }
10409
10410       /* If both operands are AND's of a paradoxical SUBREG by constant, the
10411          SUBREGs are of the same mode, and, in both cases, the AND would
10412          be redundant if the comparison was done in the narrower mode,
10413          do the comparison in the narrower mode (e.g., we are AND'ing with 1
10414          and the operand's possibly nonzero bits are 0xffffff01; in that case
10415          if we only care about QImode, we don't need the AND).  This case
10416          occurs if the output mode of an scc insn is not SImode and
10417          STORE_FLAG_VALUE == 1 (e.g., the 386).
10418
10419          Similarly, check for a case where the AND's are ZERO_EXTEND
10420          operations from some narrower mode even though a SUBREG is not
10421          present.  */
10422
10423       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10424                && CONST_INT_P (XEXP (op0, 1))
10425                && CONST_INT_P (XEXP (op1, 1)))
10426         {
10427           rtx inner_op0 = XEXP (op0, 0);
10428           rtx inner_op1 = XEXP (op1, 0);
10429           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10430           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10431           int changed = 0;
10432
10433           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10434               && (GET_MODE_SIZE (GET_MODE (inner_op0))
10435                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10436               && (GET_MODE (SUBREG_REG (inner_op0))
10437                   == GET_MODE (SUBREG_REG (inner_op1)))
10438               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10439                   <= HOST_BITS_PER_WIDE_INT)
10440               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10441                                              GET_MODE (SUBREG_REG (inner_op0)))))
10442               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10443                                              GET_MODE (SUBREG_REG (inner_op1))))))
10444             {
10445               op0 = SUBREG_REG (inner_op0);
10446               op1 = SUBREG_REG (inner_op1);
10447
10448               /* The resulting comparison is always unsigned since we masked
10449                  off the original sign bit.  */
10450               code = unsigned_condition (code);
10451
10452               changed = 1;
10453             }
10454
10455           else if (c0 == c1)
10456             for (tmode = GET_CLASS_NARROWEST_MODE
10457                  (GET_MODE_CLASS (GET_MODE (op0)));
10458                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10459               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10460                 {
10461                   op0 = gen_lowpart (tmode, inner_op0);
10462                   op1 = gen_lowpart (tmode, inner_op1);
10463                   code = unsigned_condition (code);
10464                   changed = 1;
10465                   break;
10466                 }
10467
10468           if (! changed)
10469             break;
10470         }
10471
10472       /* If both operands are NOT, we can strip off the outer operation
10473          and adjust the comparison code for swapped operands; similarly for
10474          NEG, except that this must be an equality comparison.  */
10475       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10476                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10477                    && (code == EQ || code == NE)))
10478         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10479
10480       else
10481         break;
10482     }
10483
10484   /* If the first operand is a constant, swap the operands and adjust the
10485      comparison code appropriately, but don't do this if the second operand
10486      is already a constant integer.  */
10487   if (swap_commutative_operands_p (op0, op1))
10488     {
10489       tem = op0, op0 = op1, op1 = tem;
10490       code = swap_condition (code);
10491     }
10492
10493   /* We now enter a loop during which we will try to simplify the comparison.
10494      For the most part, we only are concerned with comparisons with zero,
10495      but some things may really be comparisons with zero but not start
10496      out looking that way.  */
10497
10498   while (CONST_INT_P (op1))
10499     {
10500       enum machine_mode mode = GET_MODE (op0);
10501       unsigned int mode_width = GET_MODE_BITSIZE (mode);
10502       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10503       int equality_comparison_p;
10504       int sign_bit_comparison_p;
10505       int unsigned_comparison_p;
10506       HOST_WIDE_INT const_op;
10507
10508       /* We only want to handle integral modes.  This catches VOIDmode,
10509          CCmode, and the floating-point modes.  An exception is that we
10510          can handle VOIDmode if OP0 is a COMPARE or a comparison
10511          operation.  */
10512
10513       if (GET_MODE_CLASS (mode) != MODE_INT
10514           && ! (mode == VOIDmode
10515                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10516         break;
10517
10518       /* Get the constant we are comparing against and turn off all bits
10519          not on in our mode.  */
10520       const_op = INTVAL (op1);
10521       if (mode != VOIDmode)
10522         const_op = trunc_int_for_mode (const_op, mode);
10523       op1 = GEN_INT (const_op);
10524
10525       /* If we are comparing against a constant power of two and the value
10526          being compared can only have that single bit nonzero (e.g., it was
10527          `and'ed with that bit), we can replace this with a comparison
10528          with zero.  */
10529       if (const_op
10530           && (code == EQ || code == NE || code == GE || code == GEU
10531               || code == LT || code == LTU)
10532           && mode_width <= HOST_BITS_PER_WIDE_INT
10533           && exact_log2 (const_op) >= 0
10534           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10535         {
10536           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10537           op1 = const0_rtx, const_op = 0;
10538         }
10539
10540       /* Similarly, if we are comparing a value known to be either -1 or
10541          0 with -1, change it to the opposite comparison against zero.  */
10542
10543       if (const_op == -1
10544           && (code == EQ || code == NE || code == GT || code == LE
10545               || code == GEU || code == LTU)
10546           && num_sign_bit_copies (op0, mode) == mode_width)
10547         {
10548           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10549           op1 = const0_rtx, const_op = 0;
10550         }
10551
10552       /* Do some canonicalizations based on the comparison code.  We prefer
10553          comparisons against zero and then prefer equality comparisons.
10554          If we can reduce the size of a constant, we will do that too.  */
10555
10556       switch (code)
10557         {
10558         case LT:
10559           /* < C is equivalent to <= (C - 1) */
10560           if (const_op > 0)
10561             {
10562               const_op -= 1;
10563               op1 = GEN_INT (const_op);
10564               code = LE;
10565               /* ... fall through to LE case below.  */
10566             }
10567           else
10568             break;
10569
10570         case LE:
10571           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10572           if (const_op < 0)
10573             {
10574               const_op += 1;
10575               op1 = GEN_INT (const_op);
10576               code = LT;
10577             }
10578
10579           /* If we are doing a <= 0 comparison on a value known to have
10580              a zero sign bit, we can replace this with == 0.  */
10581           else if (const_op == 0
10582                    && mode_width <= HOST_BITS_PER_WIDE_INT
10583                    && (nonzero_bits (op0, mode)
10584                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10585             code = EQ;
10586           break;
10587
10588         case GE:
10589           /* >= C is equivalent to > (C - 1).  */
10590           if (const_op > 0)
10591             {
10592               const_op -= 1;
10593               op1 = GEN_INT (const_op);
10594               code = GT;
10595               /* ... fall through to GT below.  */
10596             }
10597           else
10598             break;
10599
10600         case GT:
10601           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10602           if (const_op < 0)
10603             {
10604               const_op += 1;
10605               op1 = GEN_INT (const_op);
10606               code = GE;
10607             }
10608
10609           /* If we are doing a > 0 comparison on a value known to have
10610              a zero sign bit, we can replace this with != 0.  */
10611           else if (const_op == 0
10612                    && mode_width <= HOST_BITS_PER_WIDE_INT
10613                    && (nonzero_bits (op0, mode)
10614                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10615             code = NE;
10616           break;
10617
10618         case LTU:
10619           /* < C is equivalent to <= (C - 1).  */
10620           if (const_op > 0)
10621             {
10622               const_op -= 1;
10623               op1 = GEN_INT (const_op);
10624               code = LEU;
10625               /* ... fall through ...  */
10626             }
10627
10628           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10629           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10630                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10631             {
10632               const_op = 0, op1 = const0_rtx;
10633               code = GE;
10634               break;
10635             }
10636           else
10637             break;
10638
10639         case LEU:
10640           /* unsigned <= 0 is equivalent to == 0 */
10641           if (const_op == 0)
10642             code = EQ;
10643
10644           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10645           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10646                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10647             {
10648               const_op = 0, op1 = const0_rtx;
10649               code = GE;
10650             }
10651           break;
10652
10653         case GEU:
10654           /* >= C is equivalent to > (C - 1).  */
10655           if (const_op > 1)
10656             {
10657               const_op -= 1;
10658               op1 = GEN_INT (const_op);
10659               code = GTU;
10660               /* ... fall through ...  */
10661             }
10662
10663           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10664           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10665                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10666             {
10667               const_op = 0, op1 = const0_rtx;
10668               code = LT;
10669               break;
10670             }
10671           else
10672             break;
10673
10674         case GTU:
10675           /* unsigned > 0 is equivalent to != 0 */
10676           if (const_op == 0)
10677             code = NE;
10678
10679           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10680           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10681                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10682             {
10683               const_op = 0, op1 = const0_rtx;
10684               code = LT;
10685             }
10686           break;
10687
10688         default:
10689           break;
10690         }
10691
10692       /* Compute some predicates to simplify code below.  */
10693
10694       equality_comparison_p = (code == EQ || code == NE);
10695       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10696       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10697                                || code == GEU);
10698
10699       /* If this is a sign bit comparison and we can do arithmetic in
10700          MODE, say that we will only be needing the sign bit of OP0.  */
10701       if (sign_bit_comparison_p
10702           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10703         op0 = force_to_mode (op0, mode,
10704                              ((HOST_WIDE_INT) 1
10705                               << (GET_MODE_BITSIZE (mode) - 1)),
10706                              0);
10707
10708       /* Now try cases based on the opcode of OP0.  If none of the cases
10709          does a "continue", we exit this loop immediately after the
10710          switch.  */
10711
10712       switch (GET_CODE (op0))
10713         {
10714         case ZERO_EXTRACT:
10715           /* If we are extracting a single bit from a variable position in
10716              a constant that has only a single bit set and are comparing it
10717              with zero, we can convert this into an equality comparison
10718              between the position and the location of the single bit.  */
10719           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10720              have already reduced the shift count modulo the word size.  */
10721           if (!SHIFT_COUNT_TRUNCATED
10722               && CONST_INT_P (XEXP (op0, 0))
10723               && XEXP (op0, 1) == const1_rtx
10724               && equality_comparison_p && const_op == 0
10725               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10726             {
10727               if (BITS_BIG_ENDIAN)
10728                 {
10729                   enum machine_mode new_mode
10730                     = mode_for_extraction (EP_extzv, 1);
10731                   if (new_mode == MAX_MACHINE_MODE)
10732                     i = BITS_PER_WORD - 1 - i;
10733                   else
10734                     {
10735                       mode = new_mode;
10736                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
10737                     }
10738                 }
10739
10740               op0 = XEXP (op0, 2);
10741               op1 = GEN_INT (i);
10742               const_op = i;
10743
10744               /* Result is nonzero iff shift count is equal to I.  */
10745               code = reverse_condition (code);
10746               continue;
10747             }
10748
10749           /* ... fall through ...  */
10750
10751         case SIGN_EXTRACT:
10752           tem = expand_compound_operation (op0);
10753           if (tem != op0)
10754             {
10755               op0 = tem;
10756               continue;
10757             }
10758           break;
10759
10760         case NOT:
10761           /* If testing for equality, we can take the NOT of the constant.  */
10762           if (equality_comparison_p
10763               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10764             {
10765               op0 = XEXP (op0, 0);
10766               op1 = tem;
10767               continue;
10768             }
10769
10770           /* If just looking at the sign bit, reverse the sense of the
10771              comparison.  */
10772           if (sign_bit_comparison_p)
10773             {
10774               op0 = XEXP (op0, 0);
10775               code = (code == GE ? LT : GE);
10776               continue;
10777             }
10778           break;
10779
10780         case NEG:
10781           /* If testing for equality, we can take the NEG of the constant.  */
10782           if (equality_comparison_p
10783               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10784             {
10785               op0 = XEXP (op0, 0);
10786               op1 = tem;
10787               continue;
10788             }
10789
10790           /* The remaining cases only apply to comparisons with zero.  */
10791           if (const_op != 0)
10792             break;
10793
10794           /* When X is ABS or is known positive,
10795              (neg X) is < 0 if and only if X != 0.  */
10796
10797           if (sign_bit_comparison_p
10798               && (GET_CODE (XEXP (op0, 0)) == ABS
10799                   || (mode_width <= HOST_BITS_PER_WIDE_INT
10800                       && (nonzero_bits (XEXP (op0, 0), mode)
10801                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10802             {
10803               op0 = XEXP (op0, 0);
10804               code = (code == LT ? NE : EQ);
10805               continue;
10806             }
10807
10808           /* If we have NEG of something whose two high-order bits are the
10809              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
10810           if (num_sign_bit_copies (op0, mode) >= 2)
10811             {
10812               op0 = XEXP (op0, 0);
10813               code = swap_condition (code);
10814               continue;
10815             }
10816           break;
10817
10818         case ROTATE:
10819           /* If we are testing equality and our count is a constant, we
10820              can perform the inverse operation on our RHS.  */
10821           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10822               && (tem = simplify_binary_operation (ROTATERT, mode,
10823                                                    op1, XEXP (op0, 1))) != 0)
10824             {
10825               op0 = XEXP (op0, 0);
10826               op1 = tem;
10827               continue;
10828             }
10829
10830           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10831              a particular bit.  Convert it to an AND of a constant of that
10832              bit.  This will be converted into a ZERO_EXTRACT.  */
10833           if (const_op == 0 && sign_bit_comparison_p
10834               && CONST_INT_P (XEXP (op0, 1))
10835               && mode_width <= HOST_BITS_PER_WIDE_INT)
10836             {
10837               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10838                                             ((HOST_WIDE_INT) 1
10839                                              << (mode_width - 1
10840                                                  - INTVAL (XEXP (op0, 1)))));
10841               code = (code == LT ? NE : EQ);
10842               continue;
10843             }
10844
10845           /* Fall through.  */
10846
10847         case ABS:
10848           /* ABS is ignorable inside an equality comparison with zero.  */
10849           if (const_op == 0 && equality_comparison_p)
10850             {
10851               op0 = XEXP (op0, 0);
10852               continue;
10853             }
10854           break;
10855
10856         case SIGN_EXTEND:
10857           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10858              (compare FOO CONST) if CONST fits in FOO's mode and we
10859              are either testing inequality or have an unsigned
10860              comparison with ZERO_EXTEND or a signed comparison with
10861              SIGN_EXTEND.  But don't do it if we don't have a compare
10862              insn of the given mode, since we'd have to revert it
10863              later on, and then we wouldn't know whether to sign- or
10864              zero-extend.  */
10865           mode = GET_MODE (XEXP (op0, 0));
10866           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10867               && ! unsigned_comparison_p
10868               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10869               && ((unsigned HOST_WIDE_INT) const_op
10870                   < (((unsigned HOST_WIDE_INT) 1
10871                       << (GET_MODE_BITSIZE (mode) - 1))))
10872               && have_insn_for (COMPARE, mode))
10873             {
10874               op0 = XEXP (op0, 0);
10875               continue;
10876             }
10877           break;
10878
10879         case SUBREG:
10880           /* Check for the case where we are comparing A - C1 with C2, that is
10881
10882                (subreg:MODE (plus (A) (-C1))) op (C2)
10883
10884              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10885              comparison in the wider mode.  One of the following two conditions
10886              must be true in order for this to be valid:
10887
10888                1. The mode extension results in the same bit pattern being added
10889                   on both sides and the comparison is equality or unsigned.  As
10890                   C2 has been truncated to fit in MODE, the pattern can only be
10891                   all 0s or all 1s.
10892
10893                2. The mode extension results in the sign bit being copied on
10894                   each side.
10895
10896              The difficulty here is that we have predicates for A but not for
10897              (A - C1) so we need to check that C1 is within proper bounds so
10898              as to perturbate A as little as possible.  */
10899
10900           if (mode_width <= HOST_BITS_PER_WIDE_INT
10901               && subreg_lowpart_p (op0)
10902               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10903               && GET_CODE (SUBREG_REG (op0)) == PLUS
10904               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10905             {
10906               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10907               rtx a = XEXP (SUBREG_REG (op0), 0);
10908               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10909
10910               if ((c1 > 0
10911                    && (unsigned HOST_WIDE_INT) c1
10912                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10913                    && (equality_comparison_p || unsigned_comparison_p)
10914                    /* (A - C1) zero-extends if it is positive and sign-extends
10915                       if it is negative, C2 both zero- and sign-extends.  */
10916                    && ((0 == (nonzero_bits (a, inner_mode)
10917                               & ~GET_MODE_MASK (mode))
10918                         && const_op >= 0)
10919                        /* (A - C1) sign-extends if it is positive and 1-extends
10920                           if it is negative, C2 both sign- and 1-extends.  */
10921                        || (num_sign_bit_copies (a, inner_mode)
10922                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10923                                              - mode_width)
10924                            && const_op < 0)))
10925                   || ((unsigned HOST_WIDE_INT) c1
10926                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10927                       /* (A - C1) always sign-extends, like C2.  */
10928                       && num_sign_bit_copies (a, inner_mode)
10929                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10930                                            - (mode_width - 1))))
10931                 {
10932                   op0 = SUBREG_REG (op0);
10933                   continue;
10934                 }
10935             }
10936
10937           /* If the inner mode is narrower and we are extracting the low part,
10938              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10939           if (subreg_lowpart_p (op0)
10940               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10941             /* Fall through */ ;
10942           else
10943             break;
10944
10945           /* ... fall through ...  */
10946
10947         case ZERO_EXTEND:
10948           mode = GET_MODE (XEXP (op0, 0));
10949           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10950               && (unsigned_comparison_p || equality_comparison_p)
10951               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10952               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10953               && have_insn_for (COMPARE, mode))
10954             {
10955               op0 = XEXP (op0, 0);
10956               continue;
10957             }
10958           break;
10959
10960         case PLUS:
10961           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10962              this for equality comparisons due to pathological cases involving
10963              overflows.  */
10964           if (equality_comparison_p
10965               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10966                                                         op1, XEXP (op0, 1))))
10967             {
10968               op0 = XEXP (op0, 0);
10969               op1 = tem;
10970               continue;
10971             }
10972
10973           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10974           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10975               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10976             {
10977               op0 = XEXP (XEXP (op0, 0), 0);
10978               code = (code == LT ? EQ : NE);
10979               continue;
10980             }
10981           break;
10982
10983         case MINUS:
10984           /* We used to optimize signed comparisons against zero, but that
10985              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10986              arrive here as equality comparisons, or (GEU, LTU) are
10987              optimized away.  No need to special-case them.  */
10988
10989           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10990              (eq B (minus A C)), whichever simplifies.  We can only do
10991              this for equality comparisons due to pathological cases involving
10992              overflows.  */
10993           if (equality_comparison_p
10994               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10995                                                         XEXP (op0, 1), op1)))
10996             {
10997               op0 = XEXP (op0, 0);
10998               op1 = tem;
10999               continue;
11000             }
11001
11002           if (equality_comparison_p
11003               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11004                                                         XEXP (op0, 0), op1)))
11005             {
11006               op0 = XEXP (op0, 1);
11007               op1 = tem;
11008               continue;
11009             }
11010
11011           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11012              of bits in X minus 1, is one iff X > 0.  */
11013           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11014               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11015               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
11016                  == mode_width - 1
11017               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11018             {
11019               op0 = XEXP (op0, 1);
11020               code = (code == GE ? LE : GT);
11021               continue;
11022             }
11023           break;
11024
11025         case XOR:
11026           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11027              if C is zero or B is a constant.  */
11028           if (equality_comparison_p
11029               && 0 != (tem = simplify_binary_operation (XOR, mode,
11030                                                         XEXP (op0, 1), op1)))
11031             {
11032               op0 = XEXP (op0, 0);
11033               op1 = tem;
11034               continue;
11035             }
11036           break;
11037
11038         case EQ:  case NE:
11039         case UNEQ:  case LTGT:
11040         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11041         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11042         case UNORDERED: case ORDERED:
11043           /* We can't do anything if OP0 is a condition code value, rather
11044              than an actual data value.  */
11045           if (const_op != 0
11046               || CC0_P (XEXP (op0, 0))
11047               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11048             break;
11049
11050           /* Get the two operands being compared.  */
11051           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11052             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11053           else
11054             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11055
11056           /* Check for the cases where we simply want the result of the
11057              earlier test or the opposite of that result.  */
11058           if (code == NE || code == EQ
11059               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11060                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11061                   && (STORE_FLAG_VALUE
11062                       & (((HOST_WIDE_INT) 1
11063                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11064                   && (code == LT || code == GE)))
11065             {
11066               enum rtx_code new_code;
11067               if (code == LT || code == NE)
11068                 new_code = GET_CODE (op0);
11069               else
11070                 new_code = reversed_comparison_code (op0, NULL);
11071
11072               if (new_code != UNKNOWN)
11073                 {
11074                   code = new_code;
11075                   op0 = tem;
11076                   op1 = tem1;
11077                   continue;
11078                 }
11079             }
11080           break;
11081
11082         case IOR:
11083           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11084              iff X <= 0.  */
11085           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11086               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11087               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11088             {
11089               op0 = XEXP (op0, 1);
11090               code = (code == GE ? GT : LE);
11091               continue;
11092             }
11093           break;
11094
11095         case AND:
11096           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11097              will be converted to a ZERO_EXTRACT later.  */
11098           if (const_op == 0 && equality_comparison_p
11099               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11100               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11101             {
11102               op0 = simplify_and_const_int
11103                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11104                                                    XEXP (op0, 1),
11105                                                    XEXP (XEXP (op0, 0), 1)),
11106                  (HOST_WIDE_INT) 1);
11107               continue;
11108             }
11109
11110           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11111              zero and X is a comparison and C1 and C2 describe only bits set
11112              in STORE_FLAG_VALUE, we can compare with X.  */
11113           if (const_op == 0 && equality_comparison_p
11114               && mode_width <= HOST_BITS_PER_WIDE_INT
11115               && CONST_INT_P (XEXP (op0, 1))
11116               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11117               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11118               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11119               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11120             {
11121               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11122                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11123               if ((~STORE_FLAG_VALUE & mask) == 0
11124                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11125                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11126                           && COMPARISON_P (tem))))
11127                 {
11128                   op0 = XEXP (XEXP (op0, 0), 0);
11129                   continue;
11130                 }
11131             }
11132
11133           /* If we are doing an equality comparison of an AND of a bit equal
11134              to the sign bit, replace this with a LT or GE comparison of
11135              the underlying value.  */
11136           if (equality_comparison_p
11137               && const_op == 0
11138               && CONST_INT_P (XEXP (op0, 1))
11139               && mode_width <= HOST_BITS_PER_WIDE_INT
11140               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11141                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11142             {
11143               op0 = XEXP (op0, 0);
11144               code = (code == EQ ? GE : LT);
11145               continue;
11146             }
11147
11148           /* If this AND operation is really a ZERO_EXTEND from a narrower
11149              mode, the constant fits within that mode, and this is either an
11150              equality or unsigned comparison, try to do this comparison in
11151              the narrower mode.
11152
11153              Note that in:
11154
11155              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11156              -> (ne:DI (reg:SI 4) (const_int 0))
11157
11158              unless TRULY_NOOP_TRUNCATION allows it or the register is
11159              known to hold a value of the required mode the
11160              transformation is invalid.  */
11161           if ((equality_comparison_p || unsigned_comparison_p)
11162               && CONST_INT_P (XEXP (op0, 1))
11163               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11164                                    & GET_MODE_MASK (mode))
11165                                   + 1)) >= 0
11166               && const_op >> i == 0
11167               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11168               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11169                                          GET_MODE_BITSIZE (GET_MODE (op0)))
11170                   || (REG_P (XEXP (op0, 0))
11171                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11172             {
11173               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11174               continue;
11175             }
11176
11177           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11178              fits in both M1 and M2 and the SUBREG is either paradoxical
11179              or represents the low part, permute the SUBREG and the AND
11180              and try again.  */
11181           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11182             {
11183               unsigned HOST_WIDE_INT c1;
11184               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11185               /* Require an integral mode, to avoid creating something like
11186                  (AND:SF ...).  */
11187               if (SCALAR_INT_MODE_P (tmode)
11188                   /* It is unsafe to commute the AND into the SUBREG if the
11189                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11190                      not defined.  As originally written the upper bits
11191                      have a defined value due to the AND operation.
11192                      However, if we commute the AND inside the SUBREG then
11193                      they no longer have defined values and the meaning of
11194                      the code has been changed.  */
11195                   && (0
11196 #ifdef WORD_REGISTER_OPERATIONS
11197                       || (mode_width > GET_MODE_BITSIZE (tmode)
11198                           && mode_width <= BITS_PER_WORD)
11199 #endif
11200                       || (mode_width <= GET_MODE_BITSIZE (tmode)
11201                           && subreg_lowpart_p (XEXP (op0, 0))))
11202                   && CONST_INT_P (XEXP (op0, 1))
11203                   && mode_width <= HOST_BITS_PER_WIDE_INT
11204                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11205                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11206                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11207                   && c1 != mask
11208                   && c1 != GET_MODE_MASK (tmode))
11209                 {
11210                   op0 = simplify_gen_binary (AND, tmode,
11211                                              SUBREG_REG (XEXP (op0, 0)),
11212                                              gen_int_mode (c1, tmode));
11213                   op0 = gen_lowpart (mode, op0);
11214                   continue;
11215                 }
11216             }
11217
11218           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11219           if (const_op == 0 && equality_comparison_p
11220               && XEXP (op0, 1) == const1_rtx
11221               && GET_CODE (XEXP (op0, 0)) == NOT)
11222             {
11223               op0 = simplify_and_const_int
11224                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11225               code = (code == NE ? EQ : NE);
11226               continue;
11227             }
11228
11229           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11230              (eq (and (lshiftrt X) 1) 0).
11231              Also handle the case where (not X) is expressed using xor.  */
11232           if (const_op == 0 && equality_comparison_p
11233               && XEXP (op0, 1) == const1_rtx
11234               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11235             {
11236               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11237               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11238
11239               if (GET_CODE (shift_op) == NOT
11240                   || (GET_CODE (shift_op) == XOR
11241                       && CONST_INT_P (XEXP (shift_op, 1))
11242                       && CONST_INT_P (shift_count)
11243                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11244                       && (INTVAL (XEXP (shift_op, 1))
11245                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11246                 {
11247                   op0 = simplify_and_const_int
11248                     (NULL_RTX, mode,
11249                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11250                      (HOST_WIDE_INT) 1);
11251                   code = (code == NE ? EQ : NE);
11252                   continue;
11253                 }
11254             }
11255           break;
11256
11257         case ASHIFT:
11258           /* If we have (compare (ashift FOO N) (const_int C)) and
11259              the high order N bits of FOO (N+1 if an inequality comparison)
11260              are known to be zero, we can do this by comparing FOO with C
11261              shifted right N bits so long as the low-order N bits of C are
11262              zero.  */
11263           if (CONST_INT_P (XEXP (op0, 1))
11264               && INTVAL (XEXP (op0, 1)) >= 0
11265               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11266                   < HOST_BITS_PER_WIDE_INT)
11267               && ((const_op
11268                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11269               && mode_width <= HOST_BITS_PER_WIDE_INT
11270               && (nonzero_bits (XEXP (op0, 0), mode)
11271                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11272                                + ! equality_comparison_p))) == 0)
11273             {
11274               /* We must perform a logical shift, not an arithmetic one,
11275                  as we want the top N bits of C to be zero.  */
11276               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11277
11278               temp >>= INTVAL (XEXP (op0, 1));
11279               op1 = gen_int_mode (temp, mode);
11280               op0 = XEXP (op0, 0);
11281               continue;
11282             }
11283
11284           /* If we are doing a sign bit comparison, it means we are testing
11285              a particular bit.  Convert it to the appropriate AND.  */
11286           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11287               && mode_width <= HOST_BITS_PER_WIDE_INT)
11288             {
11289               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11290                                             ((HOST_WIDE_INT) 1
11291                                              << (mode_width - 1
11292                                                  - INTVAL (XEXP (op0, 1)))));
11293               code = (code == LT ? NE : EQ);
11294               continue;
11295             }
11296
11297           /* If this an equality comparison with zero and we are shifting
11298              the low bit to the sign bit, we can convert this to an AND of the
11299              low-order bit.  */
11300           if (const_op == 0 && equality_comparison_p
11301               && CONST_INT_P (XEXP (op0, 1))
11302               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11303                  == mode_width - 1)
11304             {
11305               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11306                                             (HOST_WIDE_INT) 1);
11307               continue;
11308             }
11309           break;
11310
11311         case ASHIFTRT:
11312           /* If this is an equality comparison with zero, we can do this
11313              as a logical shift, which might be much simpler.  */
11314           if (equality_comparison_p && const_op == 0
11315               && CONST_INT_P (XEXP (op0, 1)))
11316             {
11317               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11318                                           XEXP (op0, 0),
11319                                           INTVAL (XEXP (op0, 1)));
11320               continue;
11321             }
11322
11323           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11324              do the comparison in a narrower mode.  */
11325           if (! unsigned_comparison_p
11326               && CONST_INT_P (XEXP (op0, 1))
11327               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11328               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11329               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11330                                          MODE_INT, 1)) != BLKmode
11331               && (((unsigned HOST_WIDE_INT) const_op
11332                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11333                   <= GET_MODE_MASK (tmode)))
11334             {
11335               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11336               continue;
11337             }
11338
11339           /* Likewise if OP0 is a PLUS of a sign extension with a
11340              constant, which is usually represented with the PLUS
11341              between the shifts.  */
11342           if (! unsigned_comparison_p
11343               && CONST_INT_P (XEXP (op0, 1))
11344               && GET_CODE (XEXP (op0, 0)) == PLUS
11345               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11346               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11347               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11348               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11349                                          MODE_INT, 1)) != BLKmode
11350               && (((unsigned HOST_WIDE_INT) const_op
11351                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11352                   <= GET_MODE_MASK (tmode)))
11353             {
11354               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11355               rtx add_const = XEXP (XEXP (op0, 0), 1);
11356               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11357                                                    add_const, XEXP (op0, 1));
11358
11359               op0 = simplify_gen_binary (PLUS, tmode,
11360                                          gen_lowpart (tmode, inner),
11361                                          new_const);
11362               continue;
11363             }
11364
11365           /* ... fall through ...  */
11366         case LSHIFTRT:
11367           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11368              the low order N bits of FOO are known to be zero, we can do this
11369              by comparing FOO with C shifted left N bits so long as no
11370              overflow occurs.  */
11371           if (CONST_INT_P (XEXP (op0, 1))
11372               && INTVAL (XEXP (op0, 1)) >= 0
11373               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11374               && mode_width <= HOST_BITS_PER_WIDE_INT
11375               && (nonzero_bits (XEXP (op0, 0), mode)
11376                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11377               && (((unsigned HOST_WIDE_INT) const_op
11378                    + (GET_CODE (op0) != LSHIFTRT
11379                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11380                          + 1)
11381                       : 0))
11382                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11383             {
11384               /* If the shift was logical, then we must make the condition
11385                  unsigned.  */
11386               if (GET_CODE (op0) == LSHIFTRT)
11387                 code = unsigned_condition (code);
11388
11389               const_op <<= INTVAL (XEXP (op0, 1));
11390               op1 = GEN_INT (const_op);
11391               op0 = XEXP (op0, 0);
11392               continue;
11393             }
11394
11395           /* If we are using this shift to extract just the sign bit, we
11396              can replace this with an LT or GE comparison.  */
11397           if (const_op == 0
11398               && (equality_comparison_p || sign_bit_comparison_p)
11399               && CONST_INT_P (XEXP (op0, 1))
11400               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11401                  == mode_width - 1)
11402             {
11403               op0 = XEXP (op0, 0);
11404               code = (code == NE || code == GT ? LT : GE);
11405               continue;
11406             }
11407           break;
11408
11409         default:
11410           break;
11411         }
11412
11413       break;
11414     }
11415
11416   /* Now make any compound operations involved in this comparison.  Then,
11417      check for an outmost SUBREG on OP0 that is not doing anything or is
11418      paradoxical.  The latter transformation must only be performed when
11419      it is known that the "extra" bits will be the same in op0 and op1 or
11420      that they don't matter.  There are three cases to consider:
11421
11422      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11423      care bits and we can assume they have any convenient value.  So
11424      making the transformation is safe.
11425
11426      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11427      In this case the upper bits of op0 are undefined.  We should not make
11428      the simplification in that case as we do not know the contents of
11429      those bits.
11430
11431      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11432      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11433      also be sure that they are the same as the upper bits of op1.
11434
11435      We can never remove a SUBREG for a non-equality comparison because
11436      the sign bit is in a different place in the underlying object.  */
11437
11438   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11439   op1 = make_compound_operation (op1, SET);
11440
11441   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11442       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11443       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11444       && (code == NE || code == EQ))
11445     {
11446       if (GET_MODE_SIZE (GET_MODE (op0))
11447           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11448         {
11449           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11450              implemented.  */
11451           if (REG_P (SUBREG_REG (op0)))
11452             {
11453               op0 = SUBREG_REG (op0);
11454               op1 = gen_lowpart (GET_MODE (op0), op1);
11455             }
11456         }
11457       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11458                 <= HOST_BITS_PER_WIDE_INT)
11459                && (nonzero_bits (SUBREG_REG (op0),
11460                                  GET_MODE (SUBREG_REG (op0)))
11461                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11462         {
11463           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11464
11465           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11466                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11467             op0 = SUBREG_REG (op0), op1 = tem;
11468         }
11469     }
11470
11471   /* We now do the opposite procedure: Some machines don't have compare
11472      insns in all modes.  If OP0's mode is an integer mode smaller than a
11473      word and we can't do a compare in that mode, see if there is a larger
11474      mode for which we can do the compare.  There are a number of cases in
11475      which we can use the wider mode.  */
11476
11477   mode = GET_MODE (op0);
11478   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11479       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11480       && ! have_insn_for (COMPARE, mode))
11481     for (tmode = GET_MODE_WIDER_MODE (mode);
11482          (tmode != VOIDmode
11483           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11484          tmode = GET_MODE_WIDER_MODE (tmode))
11485       if (have_insn_for (COMPARE, tmode))
11486         {
11487           int zero_extended;
11488
11489           /* If the only nonzero bits in OP0 and OP1 are those in the
11490              narrower mode and this is an equality or unsigned comparison,
11491              we can use the wider mode.  Similarly for sign-extended
11492              values, in which case it is true for all comparisons.  */
11493           zero_extended = ((code == EQ || code == NE
11494                             || code == GEU || code == GTU
11495                             || code == LEU || code == LTU)
11496                            && (nonzero_bits (op0, tmode)
11497                                & ~GET_MODE_MASK (mode)) == 0
11498                            && ((CONST_INT_P (op1)
11499                                 || (nonzero_bits (op1, tmode)
11500                                     & ~GET_MODE_MASK (mode)) == 0)));
11501
11502           if (zero_extended
11503               || ((num_sign_bit_copies (op0, tmode)
11504                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
11505                                      - GET_MODE_BITSIZE (mode)))
11506                   && (num_sign_bit_copies (op1, tmode)
11507                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
11508                                         - GET_MODE_BITSIZE (mode)))))
11509             {
11510               /* If OP0 is an AND and we don't have an AND in MODE either,
11511                  make a new AND in the proper mode.  */
11512               if (GET_CODE (op0) == AND
11513                   && !have_insn_for (AND, mode))
11514                 op0 = simplify_gen_binary (AND, tmode,
11515                                            gen_lowpart (tmode,
11516                                                         XEXP (op0, 0)),
11517                                            gen_lowpart (tmode,
11518                                                         XEXP (op0, 1)));
11519
11520               op0 = gen_lowpart (tmode, op0);
11521               if (zero_extended && CONST_INT_P (op1))
11522                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11523               op1 = gen_lowpart (tmode, op1);
11524               break;
11525             }
11526
11527           /* If this is a test for negative, we can make an explicit
11528              test of the sign bit.  */
11529
11530           if (op1 == const0_rtx && (code == LT || code == GE)
11531               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11532             {
11533               op0 = simplify_gen_binary (AND, tmode,
11534                                          gen_lowpart (tmode, op0),
11535                                          GEN_INT ((HOST_WIDE_INT) 1
11536                                                   << (GET_MODE_BITSIZE (mode)
11537                                                       - 1)));
11538               code = (code == LT) ? NE : EQ;
11539               break;
11540             }
11541         }
11542
11543 #ifdef CANONICALIZE_COMPARISON
11544   /* If this machine only supports a subset of valid comparisons, see if we
11545      can convert an unsupported one into a supported one.  */
11546   CANONICALIZE_COMPARISON (code, op0, op1);
11547 #endif
11548
11549   *pop0 = op0;
11550   *pop1 = op1;
11551
11552   return code;
11553 }
11554 \f
11555 /* Utility function for record_value_for_reg.  Count number of
11556    rtxs in X.  */
11557 static int
11558 count_rtxs (rtx x)
11559 {
11560   enum rtx_code code = GET_CODE (x);
11561   const char *fmt;
11562   int i, j, ret = 1;
11563
11564   if (GET_RTX_CLASS (code) == '2'
11565       || GET_RTX_CLASS (code) == 'c')
11566     {
11567       rtx x0 = XEXP (x, 0);
11568       rtx x1 = XEXP (x, 1);
11569
11570       if (x0 == x1)
11571         return 1 + 2 * count_rtxs (x0);
11572
11573       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11574            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11575           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11576         return 2 + 2 * count_rtxs (x0)
11577                + count_rtxs (x == XEXP (x1, 0)
11578                              ? XEXP (x1, 1) : XEXP (x1, 0));
11579
11580       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11581            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11582           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11583         return 2 + 2 * count_rtxs (x1)
11584                + count_rtxs (x == XEXP (x0, 0)
11585                              ? XEXP (x0, 1) : XEXP (x0, 0));
11586     }
11587
11588   fmt = GET_RTX_FORMAT (code);
11589   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11590     if (fmt[i] == 'e')
11591       ret += count_rtxs (XEXP (x, i));
11592     else if (fmt[i] == 'E')
11593       for (j = 0; j < XVECLEN (x, i); j++)
11594         ret += count_rtxs (XVECEXP (x, i, j));
11595
11596   return ret;
11597 }
11598 \f
11599 /* Utility function for following routine.  Called when X is part of a value
11600    being stored into last_set_value.  Sets last_set_table_tick
11601    for each register mentioned.  Similar to mention_regs in cse.c  */
11602
11603 static void
11604 update_table_tick (rtx x)
11605 {
11606   enum rtx_code code = GET_CODE (x);
11607   const char *fmt = GET_RTX_FORMAT (code);
11608   int i, j;
11609
11610   if (code == REG)
11611     {
11612       unsigned int regno = REGNO (x);
11613       unsigned int endregno = END_REGNO (x);
11614       unsigned int r;
11615
11616       for (r = regno; r < endregno; r++)
11617         {
11618           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11619           rsp->last_set_table_tick = label_tick;
11620         }
11621
11622       return;
11623     }
11624
11625   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11626     if (fmt[i] == 'e')
11627       {
11628         /* Check for identical subexpressions.  If x contains
11629            identical subexpression we only have to traverse one of
11630            them.  */
11631         if (i == 0 && ARITHMETIC_P (x))
11632           {
11633             /* Note that at this point x1 has already been
11634                processed.  */
11635             rtx x0 = XEXP (x, 0);
11636             rtx x1 = XEXP (x, 1);
11637
11638             /* If x0 and x1 are identical then there is no need to
11639                process x0.  */
11640             if (x0 == x1)
11641               break;
11642
11643             /* If x0 is identical to a subexpression of x1 then while
11644                processing x1, x0 has already been processed.  Thus we
11645                are done with x.  */
11646             if (ARITHMETIC_P (x1)
11647                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11648               break;
11649
11650             /* If x1 is identical to a subexpression of x0 then we
11651                still have to process the rest of x0.  */
11652             if (ARITHMETIC_P (x0)
11653                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11654               {
11655                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11656                 break;
11657               }
11658           }
11659
11660         update_table_tick (XEXP (x, i));
11661       }
11662     else if (fmt[i] == 'E')
11663       for (j = 0; j < XVECLEN (x, i); j++)
11664         update_table_tick (XVECEXP (x, i, j));
11665 }
11666
11667 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
11668    are saying that the register is clobbered and we no longer know its
11669    value.  If INSN is zero, don't update reg_stat[].last_set; this is
11670    only permitted with VALUE also zero and is used to invalidate the
11671    register.  */
11672
11673 static void
11674 record_value_for_reg (rtx reg, rtx insn, rtx value)
11675 {
11676   unsigned int regno = REGNO (reg);
11677   unsigned int endregno = END_REGNO (reg);
11678   unsigned int i;
11679   reg_stat_type *rsp;
11680
11681   /* If VALUE contains REG and we have a previous value for REG, substitute
11682      the previous value.  */
11683   if (value && insn && reg_overlap_mentioned_p (reg, value))
11684     {
11685       rtx tem;
11686
11687       /* Set things up so get_last_value is allowed to see anything set up to
11688          our insn.  */
11689       subst_low_luid = DF_INSN_LUID (insn);
11690       tem = get_last_value (reg);
11691
11692       /* If TEM is simply a binary operation with two CLOBBERs as operands,
11693          it isn't going to be useful and will take a lot of time to process,
11694          so just use the CLOBBER.  */
11695
11696       if (tem)
11697         {
11698           if (ARITHMETIC_P (tem)
11699               && GET_CODE (XEXP (tem, 0)) == CLOBBER
11700               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11701             tem = XEXP (tem, 0);
11702           else if (count_occurrences (value, reg, 1) >= 2)
11703             {
11704               /* If there are two or more occurrences of REG in VALUE,
11705                  prevent the value from growing too much.  */
11706               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11707                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11708             }
11709
11710           value = replace_rtx (copy_rtx (value), reg, tem);
11711         }
11712     }
11713
11714   /* For each register modified, show we don't know its value, that
11715      we don't know about its bitwise content, that its value has been
11716      updated, and that we don't know the location of the death of the
11717      register.  */
11718   for (i = regno; i < endregno; i++)
11719     {
11720       rsp = VEC_index (reg_stat_type, reg_stat, i);
11721
11722       if (insn)
11723         rsp->last_set = insn;
11724
11725       rsp->last_set_value = 0;
11726       rsp->last_set_mode = VOIDmode;
11727       rsp->last_set_nonzero_bits = 0;
11728       rsp->last_set_sign_bit_copies = 0;
11729       rsp->last_death = 0;
11730       rsp->truncated_to_mode = VOIDmode;
11731     }
11732
11733   /* Mark registers that are being referenced in this value.  */
11734   if (value)
11735     update_table_tick (value);
11736
11737   /* Now update the status of each register being set.
11738      If someone is using this register in this block, set this register
11739      to invalid since we will get confused between the two lives in this
11740      basic block.  This makes using this register always invalid.  In cse, we
11741      scan the table to invalidate all entries using this register, but this
11742      is too much work for us.  */
11743
11744   for (i = regno; i < endregno; i++)
11745     {
11746       rsp = VEC_index (reg_stat_type, reg_stat, i);
11747       rsp->last_set_label = label_tick;
11748       if (!insn
11749           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11750         rsp->last_set_invalid = 1;
11751       else
11752         rsp->last_set_invalid = 0;
11753     }
11754
11755   /* The value being assigned might refer to X (like in "x++;").  In that
11756      case, we must replace it with (clobber (const_int 0)) to prevent
11757      infinite loops.  */
11758   rsp = VEC_index (reg_stat_type, reg_stat, regno);
11759   if (value && ! get_last_value_validate (&value, insn,
11760                                           rsp->last_set_label, 0))
11761     {
11762       value = copy_rtx (value);
11763       if (! get_last_value_validate (&value, insn,
11764                                      rsp->last_set_label, 1))
11765         value = 0;
11766     }
11767
11768   /* For the main register being modified, update the value, the mode, the
11769      nonzero bits, and the number of sign bit copies.  */
11770
11771   rsp->last_set_value = value;
11772
11773   if (value)
11774     {
11775       enum machine_mode mode = GET_MODE (reg);
11776       subst_low_luid = DF_INSN_LUID (insn);
11777       rsp->last_set_mode = mode;
11778       if (GET_MODE_CLASS (mode) == MODE_INT
11779           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11780         mode = nonzero_bits_mode;
11781       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11782       rsp->last_set_sign_bit_copies
11783         = num_sign_bit_copies (value, GET_MODE (reg));
11784     }
11785 }
11786
11787 /* Called via note_stores from record_dead_and_set_regs to handle one
11788    SET or CLOBBER in an insn.  DATA is the instruction in which the
11789    set is occurring.  */
11790
11791 static void
11792 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11793 {
11794   rtx record_dead_insn = (rtx) data;
11795
11796   if (GET_CODE (dest) == SUBREG)
11797     dest = SUBREG_REG (dest);
11798
11799   if (!record_dead_insn)
11800     {
11801       if (REG_P (dest))
11802         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11803       return;
11804     }
11805
11806   if (REG_P (dest))
11807     {
11808       /* If we are setting the whole register, we know its value.  Otherwise
11809          show that we don't know the value.  We can handle SUBREG in
11810          some cases.  */
11811       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11812         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11813       else if (GET_CODE (setter) == SET
11814                && GET_CODE (SET_DEST (setter)) == SUBREG
11815                && SUBREG_REG (SET_DEST (setter)) == dest
11816                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11817                && subreg_lowpart_p (SET_DEST (setter)))
11818         record_value_for_reg (dest, record_dead_insn,
11819                               gen_lowpart (GET_MODE (dest),
11820                                                        SET_SRC (setter)));
11821       else
11822         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11823     }
11824   else if (MEM_P (dest)
11825            /* Ignore pushes, they clobber nothing.  */
11826            && ! push_operand (dest, GET_MODE (dest)))
11827     mem_last_set = DF_INSN_LUID (record_dead_insn);
11828 }
11829
11830 /* Update the records of when each REG was most recently set or killed
11831    for the things done by INSN.  This is the last thing done in processing
11832    INSN in the combiner loop.
11833
11834    We update reg_stat[], in particular fields last_set, last_set_value,
11835    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11836    last_death, and also the similar information mem_last_set (which insn
11837    most recently modified memory) and last_call_luid (which insn was the
11838    most recent subroutine call).  */
11839
11840 static void
11841 record_dead_and_set_regs (rtx insn)
11842 {
11843   rtx link;
11844   unsigned int i;
11845
11846   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11847     {
11848       if (REG_NOTE_KIND (link) == REG_DEAD
11849           && REG_P (XEXP (link, 0)))
11850         {
11851           unsigned int regno = REGNO (XEXP (link, 0));
11852           unsigned int endregno = END_REGNO (XEXP (link, 0));
11853
11854           for (i = regno; i < endregno; i++)
11855             {
11856               reg_stat_type *rsp;
11857
11858               rsp = VEC_index (reg_stat_type, reg_stat, i);
11859               rsp->last_death = insn;
11860             }
11861         }
11862       else if (REG_NOTE_KIND (link) == REG_INC)
11863         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11864     }
11865
11866   if (CALL_P (insn))
11867     {
11868       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11869         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11870           {
11871             reg_stat_type *rsp;
11872
11873             rsp = VEC_index (reg_stat_type, reg_stat, i);
11874             rsp->last_set_invalid = 1;
11875             rsp->last_set = insn;
11876             rsp->last_set_value = 0;
11877             rsp->last_set_mode = VOIDmode;
11878             rsp->last_set_nonzero_bits = 0;
11879             rsp->last_set_sign_bit_copies = 0;
11880             rsp->last_death = 0;
11881             rsp->truncated_to_mode = VOIDmode;
11882           }
11883
11884       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11885
11886       /* We can't combine into a call pattern.  Remember, though, that
11887          the return value register is set at this LUID.  We could
11888          still replace a register with the return value from the
11889          wrong subroutine call!  */
11890       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11891     }
11892   else
11893     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11894 }
11895
11896 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11897    register present in the SUBREG, so for each such SUBREG go back and
11898    adjust nonzero and sign bit information of the registers that are
11899    known to have some zero/sign bits set.
11900
11901    This is needed because when combine blows the SUBREGs away, the
11902    information on zero/sign bits is lost and further combines can be
11903    missed because of that.  */
11904
11905 static void
11906 record_promoted_value (rtx insn, rtx subreg)
11907 {
11908   rtx links, set;
11909   unsigned int regno = REGNO (SUBREG_REG (subreg));
11910   enum machine_mode mode = GET_MODE (subreg);
11911
11912   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11913     return;
11914
11915   for (links = LOG_LINKS (insn); links;)
11916     {
11917       reg_stat_type *rsp;
11918
11919       insn = XEXP (links, 0);
11920       set = single_set (insn);
11921
11922       if (! set || !REG_P (SET_DEST (set))
11923           || REGNO (SET_DEST (set)) != regno
11924           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11925         {
11926           links = XEXP (links, 1);
11927           continue;
11928         }
11929
11930       rsp = VEC_index (reg_stat_type, reg_stat, regno);
11931       if (rsp->last_set == insn)
11932         {
11933           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11934             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11935         }
11936
11937       if (REG_P (SET_SRC (set)))
11938         {
11939           regno = REGNO (SET_SRC (set));
11940           links = LOG_LINKS (insn);
11941         }
11942       else
11943         break;
11944     }
11945 }
11946
11947 /* Check if X, a register, is known to contain a value already
11948    truncated to MODE.  In this case we can use a subreg to refer to
11949    the truncated value even though in the generic case we would need
11950    an explicit truncation.  */
11951
11952 static bool
11953 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11954 {
11955   reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11956   enum machine_mode truncated = rsp->truncated_to_mode;
11957
11958   if (truncated == 0
11959       || rsp->truncation_label < label_tick_ebb_start)
11960     return false;
11961   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11962     return true;
11963   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11964                              GET_MODE_BITSIZE (truncated)))
11965     return true;
11966   return false;
11967 }
11968
11969 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
11970    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
11971    might be able to turn a truncate into a subreg using this information.
11972    Return -1 if traversing *P is complete or 0 otherwise.  */
11973
11974 static int
11975 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11976 {
11977   rtx x = *p;
11978   enum machine_mode truncated_mode;
11979   reg_stat_type *rsp;
11980
11981   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11982     {
11983       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11984       truncated_mode = GET_MODE (x);
11985
11986       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11987         return -1;
11988
11989       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11990                                  GET_MODE_BITSIZE (original_mode)))
11991         return -1;
11992
11993       x = SUBREG_REG (x);
11994     }
11995   /* ??? For hard-regs we now record everything.  We might be able to
11996      optimize this using last_set_mode.  */
11997   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11998     truncated_mode = GET_MODE (x);
11999   else
12000     return 0;
12001
12002   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12003   if (rsp->truncated_to_mode == 0
12004       || rsp->truncation_label < label_tick_ebb_start
12005       || (GET_MODE_SIZE (truncated_mode)
12006           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12007     {
12008       rsp->truncated_to_mode = truncated_mode;
12009       rsp->truncation_label = label_tick;
12010     }
12011
12012   return -1;
12013 }
12014
12015 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12016    the modes they are used in.  This can help truning TRUNCATEs into
12017    SUBREGs.  */
12018
12019 static void
12020 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12021 {
12022   for_each_rtx (x, record_truncated_value, NULL);
12023 }
12024
12025 /* Scan X for promoted SUBREGs.  For each one found,
12026    note what it implies to the registers used in it.  */
12027
12028 static void
12029 check_promoted_subreg (rtx insn, rtx x)
12030 {
12031   if (GET_CODE (x) == SUBREG
12032       && SUBREG_PROMOTED_VAR_P (x)
12033       && REG_P (SUBREG_REG (x)))
12034     record_promoted_value (insn, x);
12035   else
12036     {
12037       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12038       int i, j;
12039
12040       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12041         switch (format[i])
12042           {
12043           case 'e':
12044             check_promoted_subreg (insn, XEXP (x, i));
12045             break;
12046           case 'V':
12047           case 'E':
12048             if (XVEC (x, i) != 0)
12049               for (j = 0; j < XVECLEN (x, i); j++)
12050                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12051             break;
12052           }
12053     }
12054 }
12055 \f
12056 /* Utility routine for the following function.  Verify that all the registers
12057    mentioned in *LOC are valid when *LOC was part of a value set when
12058    label_tick == TICK.  Return 0 if some are not.
12059
12060    If REPLACE is nonzero, replace the invalid reference with
12061    (clobber (const_int 0)) and return 1.  This replacement is useful because
12062    we often can get useful information about the form of a value (e.g., if
12063    it was produced by a shift that always produces -1 or 0) even though
12064    we don't know exactly what registers it was produced from.  */
12065
12066 static int
12067 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12068 {
12069   rtx x = *loc;
12070   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12071   int len = GET_RTX_LENGTH (GET_CODE (x));
12072   int i, j;
12073
12074   if (REG_P (x))
12075     {
12076       unsigned int regno = REGNO (x);
12077       unsigned int endregno = END_REGNO (x);
12078       unsigned int j;
12079
12080       for (j = regno; j < endregno; j++)
12081         {
12082           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12083           if (rsp->last_set_invalid
12084               /* If this is a pseudo-register that was only set once and not
12085                  live at the beginning of the function, it is always valid.  */
12086               || (! (regno >= FIRST_PSEUDO_REGISTER
12087                      && REG_N_SETS (regno) == 1
12088                      && (!REGNO_REG_SET_P
12089                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12090                   && rsp->last_set_label > tick))
12091           {
12092             if (replace)
12093               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12094             return replace;
12095           }
12096         }
12097
12098       return 1;
12099     }
12100   /* If this is a memory reference, make sure that there were
12101      no stores after it that might have clobbered the value.  We don't
12102      have alias info, so we assume any store invalidates it.  */
12103   else if (MEM_P (x) && !MEM_READONLY_P (x)
12104            && DF_INSN_LUID (insn) <= mem_last_set)
12105     {
12106       if (replace)
12107         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12108       return replace;
12109     }
12110
12111   for (i = 0; i < len; i++)
12112     {
12113       if (fmt[i] == 'e')
12114         {
12115           /* Check for identical subexpressions.  If x contains
12116              identical subexpression we only have to traverse one of
12117              them.  */
12118           if (i == 1 && ARITHMETIC_P (x))
12119             {
12120               /* Note that at this point x0 has already been checked
12121                  and found valid.  */
12122               rtx x0 = XEXP (x, 0);
12123               rtx x1 = XEXP (x, 1);
12124
12125               /* If x0 and x1 are identical then x is also valid.  */
12126               if (x0 == x1)
12127                 return 1;
12128
12129               /* If x1 is identical to a subexpression of x0 then
12130                  while checking x0, x1 has already been checked.  Thus
12131                  it is valid and so as x.  */
12132               if (ARITHMETIC_P (x0)
12133                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12134                 return 1;
12135
12136               /* If x0 is identical to a subexpression of x1 then x is
12137                  valid iff the rest of x1 is valid.  */
12138               if (ARITHMETIC_P (x1)
12139                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12140                 return
12141                   get_last_value_validate (&XEXP (x1,
12142                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12143                                            insn, tick, replace);
12144             }
12145
12146           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12147                                        replace) == 0)
12148             return 0;
12149         }
12150       else if (fmt[i] == 'E')
12151         for (j = 0; j < XVECLEN (x, i); j++)
12152           if (get_last_value_validate (&XVECEXP (x, i, j),
12153                                        insn, tick, replace) == 0)
12154             return 0;
12155     }
12156
12157   /* If we haven't found a reason for it to be invalid, it is valid.  */
12158   return 1;
12159 }
12160
12161 /* Get the last value assigned to X, if known.  Some registers
12162    in the value may be replaced with (clobber (const_int 0)) if their value
12163    is known longer known reliably.  */
12164
12165 static rtx
12166 get_last_value (const_rtx x)
12167 {
12168   unsigned int regno;
12169   rtx value;
12170   reg_stat_type *rsp;
12171
12172   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12173      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12174      we cannot predict what values the "extra" bits might have.  */
12175   if (GET_CODE (x) == SUBREG
12176       && subreg_lowpart_p (x)
12177       && (GET_MODE_SIZE (GET_MODE (x))
12178           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12179       && (value = get_last_value (SUBREG_REG (x))) != 0)
12180     return gen_lowpart (GET_MODE (x), value);
12181
12182   if (!REG_P (x))
12183     return 0;
12184
12185   regno = REGNO (x);
12186   rsp = VEC_index (reg_stat_type, reg_stat, regno);
12187   value = rsp->last_set_value;
12188
12189   /* If we don't have a value, or if it isn't for this basic block and
12190      it's either a hard register, set more than once, or it's a live
12191      at the beginning of the function, return 0.
12192
12193      Because if it's not live at the beginning of the function then the reg
12194      is always set before being used (is never used without being set).
12195      And, if it's set only once, and it's always set before use, then all
12196      uses must have the same last value, even if it's not from this basic
12197      block.  */
12198
12199   if (value == 0
12200       || (rsp->last_set_label < label_tick_ebb_start
12201           && (regno < FIRST_PSEUDO_REGISTER
12202               || REG_N_SETS (regno) != 1
12203               || REGNO_REG_SET_P
12204                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12205     return 0;
12206
12207   /* If the value was set in a later insn than the ones we are processing,
12208      we can't use it even if the register was only set once.  */
12209   if (rsp->last_set_label == label_tick
12210       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12211     return 0;
12212
12213   /* If the value has all its registers valid, return it.  */
12214   if (get_last_value_validate (&value, rsp->last_set,
12215                                rsp->last_set_label, 0))
12216     return value;
12217
12218   /* Otherwise, make a copy and replace any invalid register with
12219      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12220
12221   value = copy_rtx (value);
12222   if (get_last_value_validate (&value, rsp->last_set,
12223                                rsp->last_set_label, 1))
12224     return value;
12225
12226   return 0;
12227 }
12228 \f
12229 /* Return nonzero if expression X refers to a REG or to memory
12230    that is set in an instruction more recent than FROM_LUID.  */
12231
12232 static int
12233 use_crosses_set_p (const_rtx x, int from_luid)
12234 {
12235   const char *fmt;
12236   int i;
12237   enum rtx_code code = GET_CODE (x);
12238
12239   if (code == REG)
12240     {
12241       unsigned int regno = REGNO (x);
12242       unsigned endreg = END_REGNO (x);
12243
12244 #ifdef PUSH_ROUNDING
12245       /* Don't allow uses of the stack pointer to be moved,
12246          because we don't know whether the move crosses a push insn.  */
12247       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12248         return 1;
12249 #endif
12250       for (; regno < endreg; regno++)
12251         {
12252           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12253           if (rsp->last_set
12254               && rsp->last_set_label == label_tick
12255               && DF_INSN_LUID (rsp->last_set) > from_luid)
12256             return 1;
12257         }
12258       return 0;
12259     }
12260
12261   if (code == MEM && mem_last_set > from_luid)
12262     return 1;
12263
12264   fmt = GET_RTX_FORMAT (code);
12265
12266   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12267     {
12268       if (fmt[i] == 'E')
12269         {
12270           int j;
12271           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12272             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12273               return 1;
12274         }
12275       else if (fmt[i] == 'e'
12276                && use_crosses_set_p (XEXP (x, i), from_luid))
12277         return 1;
12278     }
12279   return 0;
12280 }
12281 \f
12282 /* Define three variables used for communication between the following
12283    routines.  */
12284
12285 static unsigned int reg_dead_regno, reg_dead_endregno;
12286 static int reg_dead_flag;
12287
12288 /* Function called via note_stores from reg_dead_at_p.
12289
12290    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12291    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12292
12293 static void
12294 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12295 {
12296   unsigned int regno, endregno;
12297
12298   if (!REG_P (dest))
12299     return;
12300
12301   regno = REGNO (dest);
12302   endregno = END_REGNO (dest);
12303   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12304     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12305 }
12306
12307 /* Return nonzero if REG is known to be dead at INSN.
12308
12309    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12310    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12311    live.  Otherwise, see if it is live or dead at the start of the basic
12312    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12313    must be assumed to be always live.  */
12314
12315 static int
12316 reg_dead_at_p (rtx reg, rtx insn)
12317 {
12318   basic_block block;
12319   unsigned int i;
12320
12321   /* Set variables for reg_dead_at_p_1.  */
12322   reg_dead_regno = REGNO (reg);
12323   reg_dead_endregno = END_REGNO (reg);
12324
12325   reg_dead_flag = 0;
12326
12327   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12328      we allow the machine description to decide whether use-and-clobber
12329      patterns are OK.  */
12330   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12331     {
12332       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12333         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12334           return 0;
12335     }
12336
12337   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12338      beginning of basic block.  */
12339   block = BLOCK_FOR_INSN (insn);
12340   for (;;)
12341     {
12342       if (INSN_P (insn))
12343         {
12344           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12345           if (reg_dead_flag)
12346             return reg_dead_flag == 1 ? 1 : 0;
12347
12348           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12349             return 1;
12350         }
12351
12352       if (insn == BB_HEAD (block))
12353         break;
12354
12355       insn = PREV_INSN (insn);
12356     }
12357
12358   /* Look at live-in sets for the basic block that we were in.  */
12359   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12360     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12361       return 0;
12362
12363   return 1;
12364 }
12365 \f
12366 /* Note hard registers in X that are used.  */
12367
12368 static void
12369 mark_used_regs_combine (rtx x)
12370 {
12371   RTX_CODE code = GET_CODE (x);
12372   unsigned int regno;
12373   int i;
12374
12375   switch (code)
12376     {
12377     case LABEL_REF:
12378     case SYMBOL_REF:
12379     case CONST_INT:
12380     case CONST:
12381     case CONST_DOUBLE:
12382     case CONST_VECTOR:
12383     case PC:
12384     case ADDR_VEC:
12385     case ADDR_DIFF_VEC:
12386     case ASM_INPUT:
12387 #ifdef HAVE_cc0
12388     /* CC0 must die in the insn after it is set, so we don't need to take
12389        special note of it here.  */
12390     case CC0:
12391 #endif
12392       return;
12393
12394     case CLOBBER:
12395       /* If we are clobbering a MEM, mark any hard registers inside the
12396          address as used.  */
12397       if (MEM_P (XEXP (x, 0)))
12398         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12399       return;
12400
12401     case REG:
12402       regno = REGNO (x);
12403       /* A hard reg in a wide mode may really be multiple registers.
12404          If so, mark all of them just like the first.  */
12405       if (regno < FIRST_PSEUDO_REGISTER)
12406         {
12407           /* None of this applies to the stack, frame or arg pointers.  */
12408           if (regno == STACK_POINTER_REGNUM
12409 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12410               || regno == HARD_FRAME_POINTER_REGNUM
12411 #endif
12412 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12413               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12414 #endif
12415               || regno == FRAME_POINTER_REGNUM)
12416             return;
12417
12418           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12419         }
12420       return;
12421
12422     case SET:
12423       {
12424         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12425            the address.  */
12426         rtx testreg = SET_DEST (x);
12427
12428         while (GET_CODE (testreg) == SUBREG
12429                || GET_CODE (testreg) == ZERO_EXTRACT
12430                || GET_CODE (testreg) == STRICT_LOW_PART)
12431           testreg = XEXP (testreg, 0);
12432
12433         if (MEM_P (testreg))
12434           mark_used_regs_combine (XEXP (testreg, 0));
12435
12436         mark_used_regs_combine (SET_SRC (x));
12437       }
12438       return;
12439
12440     default:
12441       break;
12442     }
12443
12444   /* Recursively scan the operands of this expression.  */
12445
12446   {
12447     const char *fmt = GET_RTX_FORMAT (code);
12448
12449     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12450       {
12451         if (fmt[i] == 'e')
12452           mark_used_regs_combine (XEXP (x, i));
12453         else if (fmt[i] == 'E')
12454           {
12455             int j;
12456
12457             for (j = 0; j < XVECLEN (x, i); j++)
12458               mark_used_regs_combine (XVECEXP (x, i, j));
12459           }
12460       }
12461   }
12462 }
12463 \f
12464 /* Remove register number REGNO from the dead registers list of INSN.
12465
12466    Return the note used to record the death, if there was one.  */
12467
12468 rtx
12469 remove_death (unsigned int regno, rtx insn)
12470 {
12471   rtx note = find_regno_note (insn, REG_DEAD, regno);
12472
12473   if (note)
12474     remove_note (insn, note);
12475
12476   return note;
12477 }
12478
12479 /* For each register (hardware or pseudo) used within expression X, if its
12480    death is in an instruction with luid between FROM_LUID (inclusive) and
12481    TO_INSN (exclusive), put a REG_DEAD note for that register in the
12482    list headed by PNOTES.
12483
12484    That said, don't move registers killed by maybe_kill_insn.
12485
12486    This is done when X is being merged by combination into TO_INSN.  These
12487    notes will then be distributed as needed.  */
12488
12489 static void
12490 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12491              rtx *pnotes)
12492 {
12493   const char *fmt;
12494   int len, i;
12495   enum rtx_code code = GET_CODE (x);
12496
12497   if (code == REG)
12498     {
12499       unsigned int regno = REGNO (x);
12500       rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12501
12502       /* Don't move the register if it gets killed in between from and to.  */
12503       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12504           && ! reg_referenced_p (x, maybe_kill_insn))
12505         return;
12506
12507       if (where_dead
12508           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12509           && DF_INSN_LUID (where_dead) >= from_luid
12510           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12511         {
12512           rtx note = remove_death (regno, where_dead);
12513
12514           /* It is possible for the call above to return 0.  This can occur
12515              when last_death points to I2 or I1 that we combined with.
12516              In that case make a new note.
12517
12518              We must also check for the case where X is a hard register
12519              and NOTE is a death note for a range of hard registers
12520              including X.  In that case, we must put REG_DEAD notes for
12521              the remaining registers in place of NOTE.  */
12522
12523           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12524               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12525                   > GET_MODE_SIZE (GET_MODE (x))))
12526             {
12527               unsigned int deadregno = REGNO (XEXP (note, 0));
12528               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12529               unsigned int ourend = END_HARD_REGNO (x);
12530               unsigned int i;
12531
12532               for (i = deadregno; i < deadend; i++)
12533                 if (i < regno || i >= ourend)
12534                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12535             }
12536
12537           /* If we didn't find any note, or if we found a REG_DEAD note that
12538              covers only part of the given reg, and we have a multi-reg hard
12539              register, then to be safe we must check for REG_DEAD notes
12540              for each register other than the first.  They could have
12541              their own REG_DEAD notes lying around.  */
12542           else if ((note == 0
12543                     || (note != 0
12544                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12545                             < GET_MODE_SIZE (GET_MODE (x)))))
12546                    && regno < FIRST_PSEUDO_REGISTER
12547                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12548             {
12549               unsigned int ourend = END_HARD_REGNO (x);
12550               unsigned int i, offset;
12551               rtx oldnotes = 0;
12552
12553               if (note)
12554                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12555               else
12556                 offset = 1;
12557
12558               for (i = regno + offset; i < ourend; i++)
12559                 move_deaths (regno_reg_rtx[i],
12560                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
12561             }
12562
12563           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12564             {
12565               XEXP (note, 1) = *pnotes;
12566               *pnotes = note;
12567             }
12568           else
12569             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12570         }
12571
12572       return;
12573     }
12574
12575   else if (GET_CODE (x) == SET)
12576     {
12577       rtx dest = SET_DEST (x);
12578
12579       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12580
12581       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12582          that accesses one word of a multi-word item, some
12583          piece of everything register in the expression is used by
12584          this insn, so remove any old death.  */
12585       /* ??? So why do we test for equality of the sizes?  */
12586
12587       if (GET_CODE (dest) == ZERO_EXTRACT
12588           || GET_CODE (dest) == STRICT_LOW_PART
12589           || (GET_CODE (dest) == SUBREG
12590               && (((GET_MODE_SIZE (GET_MODE (dest))
12591                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12592                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12593                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12594         {
12595           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12596           return;
12597         }
12598
12599       /* If this is some other SUBREG, we know it replaces the entire
12600          value, so use that as the destination.  */
12601       if (GET_CODE (dest) == SUBREG)
12602         dest = SUBREG_REG (dest);
12603
12604       /* If this is a MEM, adjust deaths of anything used in the address.
12605          For a REG (the only other possibility), the entire value is
12606          being replaced so the old value is not used in this insn.  */
12607
12608       if (MEM_P (dest))
12609         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12610                      to_insn, pnotes);
12611       return;
12612     }
12613
12614   else if (GET_CODE (x) == CLOBBER)
12615     return;
12616
12617   len = GET_RTX_LENGTH (code);
12618   fmt = GET_RTX_FORMAT (code);
12619
12620   for (i = 0; i < len; i++)
12621     {
12622       if (fmt[i] == 'E')
12623         {
12624           int j;
12625           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12626             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12627                          to_insn, pnotes);
12628         }
12629       else if (fmt[i] == 'e')
12630         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12631     }
12632 }
12633 \f
12634 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12635    pattern of an insn.  X must be a REG.  */
12636
12637 static int
12638 reg_bitfield_target_p (rtx x, rtx body)
12639 {
12640   int i;
12641
12642   if (GET_CODE (body) == SET)
12643     {
12644       rtx dest = SET_DEST (body);
12645       rtx target;
12646       unsigned int regno, tregno, endregno, endtregno;
12647
12648       if (GET_CODE (dest) == ZERO_EXTRACT)
12649         target = XEXP (dest, 0);
12650       else if (GET_CODE (dest) == STRICT_LOW_PART)
12651         target = SUBREG_REG (XEXP (dest, 0));
12652       else
12653         return 0;
12654
12655       if (GET_CODE (target) == SUBREG)
12656         target = SUBREG_REG (target);
12657
12658       if (!REG_P (target))
12659         return 0;
12660
12661       tregno = REGNO (target), regno = REGNO (x);
12662       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12663         return target == x;
12664
12665       endtregno = end_hard_regno (GET_MODE (target), tregno);
12666       endregno = end_hard_regno (GET_MODE (x), regno);
12667
12668       return endregno > tregno && regno < endtregno;
12669     }
12670
12671   else if (GET_CODE (body) == PARALLEL)
12672     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12673       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12674         return 1;
12675
12676   return 0;
12677 }
12678
12679 /* Return the next insn after INSN that is neither a NOTE nor a
12680    DEBUG_INSN.  This routine does not look inside SEQUENCEs.  */
12681
12682 static rtx
12683 next_nonnote_nondebug_insn (rtx insn)
12684 {
12685   while (insn)
12686     {
12687       insn = NEXT_INSN (insn);
12688       if (insn == 0)
12689         break;
12690       if (NOTE_P (insn))
12691         continue;
12692       if (DEBUG_INSN_P (insn))
12693         continue;
12694       break;
12695     }
12696
12697   return insn;
12698 }
12699
12700
12701 \f
12702 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12703    as appropriate.  I3 and I2 are the insns resulting from the combination
12704    insns including FROM (I2 may be zero).
12705
12706    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12707    not need REG_DEAD notes because they are being substituted for.  This
12708    saves searching in the most common cases.
12709
12710    Each note in the list is either ignored or placed on some insns, depending
12711    on the type of note.  */
12712
12713 static void
12714 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12715                   rtx elim_i1)
12716 {
12717   rtx note, next_note;
12718   rtx tem;
12719
12720   for (note = notes; note; note = next_note)
12721     {
12722       rtx place = 0, place2 = 0;
12723
12724       next_note = XEXP (note, 1);
12725       switch (REG_NOTE_KIND (note))
12726         {
12727         case REG_BR_PROB:
12728         case REG_BR_PRED:
12729           /* Doesn't matter much where we put this, as long as it's somewhere.
12730              It is preferable to keep these notes on branches, which is most
12731              likely to be i3.  */
12732           place = i3;
12733           break;
12734
12735         case REG_VALUE_PROFILE:
12736           /* Just get rid of this note, as it is unused later anyway.  */
12737           break;
12738
12739         case REG_NON_LOCAL_GOTO:
12740           if (JUMP_P (i3))
12741             place = i3;
12742           else
12743             {
12744               gcc_assert (i2 && JUMP_P (i2));
12745               place = i2;
12746             }
12747           break;
12748
12749         case REG_EH_REGION:
12750           /* These notes must remain with the call or trapping instruction.  */
12751           if (CALL_P (i3))
12752             place = i3;
12753           else if (i2 && CALL_P (i2))
12754             place = i2;
12755           else
12756             {
12757               gcc_assert (flag_non_call_exceptions);
12758               if (may_trap_p (i3))
12759                 place = i3;
12760               else if (i2 && may_trap_p (i2))
12761                 place = i2;
12762               /* ??? Otherwise assume we've combined things such that we
12763                  can now prove that the instructions can't trap.  Drop the
12764                  note in this case.  */
12765             }
12766           break;
12767
12768         case REG_NORETURN:
12769         case REG_SETJMP:
12770           /* These notes must remain with the call.  It should not be
12771              possible for both I2 and I3 to be a call.  */
12772           if (CALL_P (i3))
12773             place = i3;
12774           else
12775             {
12776               gcc_assert (i2 && CALL_P (i2));
12777               place = i2;
12778             }
12779           break;
12780
12781         case REG_UNUSED:
12782           /* Any clobbers for i3 may still exist, and so we must process
12783              REG_UNUSED notes from that insn.
12784
12785              Any clobbers from i2 or i1 can only exist if they were added by
12786              recog_for_combine.  In that case, recog_for_combine created the
12787              necessary REG_UNUSED notes.  Trying to keep any original
12788              REG_UNUSED notes from these insns can cause incorrect output
12789              if it is for the same register as the original i3 dest.
12790              In that case, we will notice that the register is set in i3,
12791              and then add a REG_UNUSED note for the destination of i3, which
12792              is wrong.  However, it is possible to have REG_UNUSED notes from
12793              i2 or i1 for register which were both used and clobbered, so
12794              we keep notes from i2 or i1 if they will turn into REG_DEAD
12795              notes.  */
12796
12797           /* If this register is set or clobbered in I3, put the note there
12798              unless there is one already.  */
12799           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12800             {
12801               if (from_insn != i3)
12802                 break;
12803
12804               if (! (REG_P (XEXP (note, 0))
12805                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12806                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12807                 place = i3;
12808             }
12809           /* Otherwise, if this register is used by I3, then this register
12810              now dies here, so we must put a REG_DEAD note here unless there
12811              is one already.  */
12812           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12813                    && ! (REG_P (XEXP (note, 0))
12814                          ? find_regno_note (i3, REG_DEAD,
12815                                             REGNO (XEXP (note, 0)))
12816                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12817             {
12818               PUT_REG_NOTE_KIND (note, REG_DEAD);
12819               place = i3;
12820             }
12821           break;
12822
12823         case REG_EQUAL:
12824         case REG_EQUIV:
12825         case REG_NOALIAS:
12826           /* These notes say something about results of an insn.  We can
12827              only support them if they used to be on I3 in which case they
12828              remain on I3.  Otherwise they are ignored.
12829
12830              If the note refers to an expression that is not a constant, we
12831              must also ignore the note since we cannot tell whether the
12832              equivalence is still true.  It might be possible to do
12833              slightly better than this (we only have a problem if I2DEST
12834              or I1DEST is present in the expression), but it doesn't
12835              seem worth the trouble.  */
12836
12837           if (from_insn == i3
12838               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12839             place = i3;
12840           break;
12841
12842         case REG_INC:
12843           /* These notes say something about how a register is used.  They must
12844              be present on any use of the register in I2 or I3.  */
12845           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12846             place = i3;
12847
12848           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12849             {
12850               if (place)
12851                 place2 = i2;
12852               else
12853                 place = i2;
12854             }
12855           break;
12856
12857         case REG_LABEL_TARGET:
12858         case REG_LABEL_OPERAND:
12859           /* This can show up in several ways -- either directly in the
12860              pattern, or hidden off in the constant pool with (or without?)
12861              a REG_EQUAL note.  */
12862           /* ??? Ignore the without-reg_equal-note problem for now.  */
12863           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12864               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12865                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12866                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12867             place = i3;
12868
12869           if (i2
12870               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12871                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12872                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12873                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12874             {
12875               if (place)
12876                 place2 = i2;
12877               else
12878                 place = i2;
12879             }
12880
12881           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12882              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12883              there.  */
12884           if (place && JUMP_P (place)
12885               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12886               && (JUMP_LABEL (place) == NULL
12887                   || JUMP_LABEL (place) == XEXP (note, 0)))
12888             {
12889               rtx label = JUMP_LABEL (place);
12890
12891               if (!label)
12892                 JUMP_LABEL (place) = XEXP (note, 0);
12893               else if (LABEL_P (label))
12894                 LABEL_NUSES (label)--;
12895             }
12896
12897           if (place2 && JUMP_P (place2)
12898               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12899               && (JUMP_LABEL (place2) == NULL
12900                   || JUMP_LABEL (place2) == XEXP (note, 0)))
12901             {
12902               rtx label = JUMP_LABEL (place2);
12903
12904               if (!label)
12905                 JUMP_LABEL (place2) = XEXP (note, 0);
12906               else if (LABEL_P (label))
12907                 LABEL_NUSES (label)--;
12908               place2 = 0;
12909             }
12910           break;
12911
12912         case REG_NONNEG:
12913           /* This note says something about the value of a register prior
12914              to the execution of an insn.  It is too much trouble to see
12915              if the note is still correct in all situations.  It is better
12916              to simply delete it.  */
12917           break;
12918
12919         case REG_DEAD:
12920           /* If we replaced the right hand side of FROM_INSN with a
12921              REG_EQUAL note, the original use of the dying register
12922              will not have been combined into I3 and I2.  In such cases,
12923              FROM_INSN is guaranteed to be the first of the combined
12924              instructions, so we simply need to search back before
12925              FROM_INSN for the previous use or set of this register,
12926              then alter the notes there appropriately.
12927
12928              If the register is used as an input in I3, it dies there.
12929              Similarly for I2, if it is nonzero and adjacent to I3.
12930
12931              If the register is not used as an input in either I3 or I2
12932              and it is not one of the registers we were supposed to eliminate,
12933              there are two possibilities.  We might have a non-adjacent I2
12934              or we might have somehow eliminated an additional register
12935              from a computation.  For example, we might have had A & B where
12936              we discover that B will always be zero.  In this case we will
12937              eliminate the reference to A.
12938
12939              In both cases, we must search to see if we can find a previous
12940              use of A and put the death note there.  */
12941
12942           if (from_insn
12943               && from_insn == i2mod
12944               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12945             tem = from_insn;
12946           else
12947             {
12948               if (from_insn
12949                   && CALL_P (from_insn)
12950                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12951                 place = from_insn;
12952               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12953                 place = i3;
12954               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12955                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12956                 place = i2;
12957               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12958                         && !(i2mod
12959                              && reg_overlap_mentioned_p (XEXP (note, 0),
12960                                                          i2mod_old_rhs)))
12961                        || rtx_equal_p (XEXP (note, 0), elim_i1))
12962                 break;
12963               tem = i3;
12964             }
12965
12966           if (place == 0)
12967             {
12968               basic_block bb = this_basic_block;
12969
12970               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12971                 {
12972                   if (!NONDEBUG_INSN_P (tem))
12973                     {
12974                       if (tem == BB_HEAD (bb))
12975                         break;
12976                       continue;
12977                     }
12978
12979                   /* If the register is being set at TEM, see if that is all
12980                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12981                      into a REG_UNUSED note instead. Don't delete sets to
12982                      global register vars.  */
12983                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12984                        || !global_regs[REGNO (XEXP (note, 0))])
12985                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12986                     {
12987                       rtx set = single_set (tem);
12988                       rtx inner_dest = 0;
12989 #ifdef HAVE_cc0
12990                       rtx cc0_setter = NULL_RTX;
12991 #endif
12992
12993                       if (set != 0)
12994                         for (inner_dest = SET_DEST (set);
12995                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12996                               || GET_CODE (inner_dest) == SUBREG
12997                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12998                              inner_dest = XEXP (inner_dest, 0))
12999                           ;
13000
13001                       /* Verify that it was the set, and not a clobber that
13002                          modified the register.
13003
13004                          CC0 targets must be careful to maintain setter/user
13005                          pairs.  If we cannot delete the setter due to side
13006                          effects, mark the user with an UNUSED note instead
13007                          of deleting it.  */
13008
13009                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13010                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13011 #ifdef HAVE_cc0
13012                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13013                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13014                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13015 #endif
13016                           )
13017                         {
13018                           /* Move the notes and links of TEM elsewhere.
13019                              This might delete other dead insns recursively.
13020                              First set the pattern to something that won't use
13021                              any register.  */
13022                           rtx old_notes = REG_NOTES (tem);
13023
13024                           PATTERN (tem) = pc_rtx;
13025                           REG_NOTES (tem) = NULL;
13026
13027                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13028                                             NULL_RTX, NULL_RTX);
13029                           distribute_links (LOG_LINKS (tem));
13030
13031                           SET_INSN_DELETED (tem);
13032                           if (tem == i2)
13033                             i2 = NULL_RTX;
13034
13035 #ifdef HAVE_cc0
13036                           /* Delete the setter too.  */
13037                           if (cc0_setter)
13038                             {
13039                               PATTERN (cc0_setter) = pc_rtx;
13040                               old_notes = REG_NOTES (cc0_setter);
13041                               REG_NOTES (cc0_setter) = NULL;
13042
13043                               distribute_notes (old_notes, cc0_setter,
13044                                                 cc0_setter, NULL_RTX,
13045                                                 NULL_RTX, NULL_RTX);
13046                               distribute_links (LOG_LINKS (cc0_setter));
13047
13048                               SET_INSN_DELETED (cc0_setter);
13049                               if (cc0_setter == i2)
13050                                 i2 = NULL_RTX;
13051                             }
13052 #endif
13053                         }
13054                       else
13055                         {
13056                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13057
13058                           /*  If there isn't already a REG_UNUSED note, put one
13059                               here.  Do not place a REG_DEAD note, even if
13060                               the register is also used here; that would not
13061                               match the algorithm used in lifetime analysis
13062                               and can cause the consistency check in the
13063                               scheduler to fail.  */
13064                           if (! find_regno_note (tem, REG_UNUSED,
13065                                                  REGNO (XEXP (note, 0))))
13066                             place = tem;
13067                           break;
13068                         }
13069                     }
13070                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13071                            || (CALL_P (tem)
13072                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13073                     {
13074                       place = tem;
13075
13076                       /* If we are doing a 3->2 combination, and we have a
13077                          register which formerly died in i3 and was not used
13078                          by i2, which now no longer dies in i3 and is used in
13079                          i2 but does not die in i2, and place is between i2
13080                          and i3, then we may need to move a link from place to
13081                          i2.  */
13082                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13083                           && from_insn
13084                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13085                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13086                         {
13087                           rtx links = LOG_LINKS (place);
13088                           LOG_LINKS (place) = 0;
13089                           distribute_links (links);
13090                         }
13091                       break;
13092                     }
13093
13094                   if (tem == BB_HEAD (bb))
13095                     break;
13096                 }
13097
13098             }
13099
13100           /* If the register is set or already dead at PLACE, we needn't do
13101              anything with this note if it is still a REG_DEAD note.
13102              We check here if it is set at all, not if is it totally replaced,
13103              which is what `dead_or_set_p' checks, so also check for it being
13104              set partially.  */
13105
13106           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13107             {
13108               unsigned int regno = REGNO (XEXP (note, 0));
13109               reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13110
13111               if (dead_or_set_p (place, XEXP (note, 0))
13112                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13113                 {
13114                   /* Unless the register previously died in PLACE, clear
13115                      last_death.  [I no longer understand why this is
13116                      being done.] */
13117                   if (rsp->last_death != place)
13118                     rsp->last_death = 0;
13119                   place = 0;
13120                 }
13121               else
13122                 rsp->last_death = place;
13123
13124               /* If this is a death note for a hard reg that is occupying
13125                  multiple registers, ensure that we are still using all
13126                  parts of the object.  If we find a piece of the object
13127                  that is unused, we must arrange for an appropriate REG_DEAD
13128                  note to be added for it.  However, we can't just emit a USE
13129                  and tag the note to it, since the register might actually
13130                  be dead; so we recourse, and the recursive call then finds
13131                  the previous insn that used this register.  */
13132
13133               if (place && regno < FIRST_PSEUDO_REGISTER
13134                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13135                 {
13136                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13137                   int all_used = 1;
13138                   unsigned int i;
13139
13140                   for (i = regno; i < endregno; i++)
13141                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13142                          && ! find_regno_fusage (place, USE, i))
13143                         || dead_or_set_regno_p (place, i))
13144                       all_used = 0;
13145
13146                   if (! all_used)
13147                     {
13148                       /* Put only REG_DEAD notes for pieces that are
13149                          not already dead or set.  */
13150
13151                       for (i = regno; i < endregno;
13152                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13153                         {
13154                           rtx piece = regno_reg_rtx[i];
13155                           basic_block bb = this_basic_block;
13156
13157                           if (! dead_or_set_p (place, piece)
13158                               && ! reg_bitfield_target_p (piece,
13159                                                           PATTERN (place)))
13160                             {
13161                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13162                                                              NULL_RTX);
13163
13164                               distribute_notes (new_note, place, place,
13165                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13166                             }
13167                           else if (! refers_to_regno_p (i, i + 1,
13168                                                         PATTERN (place), 0)
13169                                    && ! find_regno_fusage (place, USE, i))
13170                             for (tem = PREV_INSN (place); ;
13171                                  tem = PREV_INSN (tem))
13172                               {
13173                                 if (!NONDEBUG_INSN_P (tem))
13174                                   {
13175                                     if (tem == BB_HEAD (bb))
13176                                       break;
13177                                     continue;
13178                                   }
13179                                 if (dead_or_set_p (tem, piece)
13180                                     || reg_bitfield_target_p (piece,
13181                                                               PATTERN (tem)))
13182                                   {
13183                                     add_reg_note (tem, REG_UNUSED, piece);
13184                                     break;
13185                                   }
13186                               }
13187
13188                         }
13189
13190                       place = 0;
13191                     }
13192                 }
13193             }
13194           break;
13195
13196         default:
13197           /* Any other notes should not be present at this point in the
13198              compilation.  */
13199           gcc_unreachable ();
13200         }
13201
13202       if (place)
13203         {
13204           XEXP (note, 1) = REG_NOTES (place);
13205           REG_NOTES (place) = note;
13206         }
13207
13208       if (place2)
13209         add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13210     }
13211 }
13212 \f
13213 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13214    I3, I2, and I1 to new locations.  This is also called to add a link
13215    pointing at I3 when I3's destination is changed.  */
13216
13217 static void
13218 distribute_links (rtx links)
13219 {
13220   rtx link, next_link;
13221
13222   for (link = links; link; link = next_link)
13223     {
13224       rtx place = 0;
13225       rtx insn;
13226       rtx set, reg;
13227
13228       next_link = XEXP (link, 1);
13229
13230       /* If the insn that this link points to is a NOTE or isn't a single
13231          set, ignore it.  In the latter case, it isn't clear what we
13232          can do other than ignore the link, since we can't tell which
13233          register it was for.  Such links wouldn't be used by combine
13234          anyway.
13235
13236          It is not possible for the destination of the target of the link to
13237          have been changed by combine.  The only potential of this is if we
13238          replace I3, I2, and I1 by I3 and I2.  But in that case the
13239          destination of I2 also remains unchanged.  */
13240
13241       if (NOTE_P (XEXP (link, 0))
13242           || (set = single_set (XEXP (link, 0))) == 0)
13243         continue;
13244
13245       reg = SET_DEST (set);
13246       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13247              || GET_CODE (reg) == STRICT_LOW_PART)
13248         reg = XEXP (reg, 0);
13249
13250       /* A LOG_LINK is defined as being placed on the first insn that uses
13251          a register and points to the insn that sets the register.  Start
13252          searching at the next insn after the target of the link and stop
13253          when we reach a set of the register or the end of the basic block.
13254
13255          Note that this correctly handles the link that used to point from
13256          I3 to I2.  Also note that not much searching is typically done here
13257          since most links don't point very far away.  */
13258
13259       for (insn = NEXT_INSN (XEXP (link, 0));
13260            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13261                      || BB_HEAD (this_basic_block->next_bb) != insn));
13262            insn = NEXT_INSN (insn))
13263         if (DEBUG_INSN_P (insn))
13264           continue;
13265         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13266           {
13267             if (reg_referenced_p (reg, PATTERN (insn)))
13268               place = insn;
13269             break;
13270           }
13271         else if (CALL_P (insn)
13272                  && find_reg_fusage (insn, USE, reg))
13273           {
13274             place = insn;
13275             break;
13276           }
13277         else if (INSN_P (insn) && reg_set_p (reg, insn))
13278           break;
13279
13280       /* If we found a place to put the link, place it there unless there
13281          is already a link to the same insn as LINK at that point.  */
13282
13283       if (place)
13284         {
13285           rtx link2;
13286
13287           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13288             if (XEXP (link2, 0) == XEXP (link, 0))
13289               break;
13290
13291           if (link2 == 0)
13292             {
13293               XEXP (link, 1) = LOG_LINKS (place);
13294               LOG_LINKS (place) = link;
13295
13296               /* Set added_links_insn to the earliest insn we added a
13297                  link to.  */
13298               if (added_links_insn == 0
13299                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13300                 added_links_insn = place;
13301             }
13302         }
13303     }
13304 }
13305 \f
13306 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13307    Check whether the expression pointer to by LOC is a register or
13308    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13309    Otherwise return zero.  */
13310
13311 static int
13312 unmentioned_reg_p_1 (rtx *loc, void *expr)
13313 {
13314   rtx x = *loc;
13315
13316   if (x != NULL_RTX
13317       && (REG_P (x) || MEM_P (x))
13318       && ! reg_mentioned_p (x, (rtx) expr))
13319     return 1;
13320   return 0;
13321 }
13322
13323 /* Check for any register or memory mentioned in EQUIV that is not
13324    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13325    of EXPR where some registers may have been replaced by constants.  */
13326
13327 static bool
13328 unmentioned_reg_p (rtx equiv, rtx expr)
13329 {
13330   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13331 }
13332 \f
13333 void
13334 dump_combine_stats (FILE *file)
13335 {
13336   fprintf
13337     (file,
13338      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13339      combine_attempts, combine_merges, combine_extras, combine_successes);
13340 }
13341
13342 void
13343 dump_combine_total_stats (FILE *file)
13344 {
13345   fprintf
13346     (file,
13347      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13348      total_attempts, total_merges, total_extras, total_successes);
13349 }
13350 \f
13351 static bool
13352 gate_handle_combine (void)
13353 {
13354   return (optimize > 0);
13355 }
13356
13357 /* Try combining insns through substitution.  */
13358 static unsigned int
13359 rest_of_handle_combine (void)
13360 {
13361   int rebuild_jump_labels_after_combine;
13362
13363   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13364   df_note_add_problem ();
13365   df_analyze ();
13366
13367   regstat_init_n_sets_and_refs ();
13368
13369   rebuild_jump_labels_after_combine
13370     = combine_instructions (get_insns (), max_reg_num ());
13371
13372   /* Combining insns may have turned an indirect jump into a
13373      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13374      instructions.  */
13375   if (rebuild_jump_labels_after_combine)
13376     {
13377       timevar_push (TV_JUMP);
13378       rebuild_jump_labels (get_insns ());
13379       cleanup_cfg (0);
13380       timevar_pop (TV_JUMP);
13381     }
13382
13383   regstat_free_n_sets_and_refs ();
13384   return 0;
13385 }
13386
13387 struct rtl_opt_pass pass_combine =
13388 {
13389  {
13390   RTL_PASS,
13391   "combine",                            /* name */
13392   gate_handle_combine,                  /* gate */
13393   rest_of_handle_combine,               /* execute */
13394   NULL,                                 /* sub */
13395   NULL,                                 /* next */
13396   0,                                    /* static_pass_number */
13397   TV_COMBINE,                           /* tv_id */
13398   PROP_cfglayout,                       /* properties_required */
13399   0,                                    /* properties_provided */
13400   0,                                    /* properties_destroyed */
13401   0,                                    /* todo_flags_start */
13402   TODO_dump_func |
13403   TODO_df_finish | TODO_verify_rtl_sharing |
13404   TODO_ggc_collect,                     /* todo_flags_finish */
13405  }
13406 };