1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* The minimum number of integer registers that we want to save with the
74 movem instruction. Using two movel instructions instead of a single
75 moveml is about 15% faster for the 68020 and 68030 at no expense in
77 #define MIN_MOVEM_REGS 3
79 /* The minimum number of floating point registers that we want to save
80 with the fmovem instruction. */
81 #define MIN_FMOVEM_REGS 1
83 /* Structure describing stack frame layout. */
86 /* Stack pointer to frame pointer offset. */
89 /* Offset of FPU registers. */
90 HOST_WIDE_INT foffset
;
92 /* Frame size in bytes (rounded up). */
95 /* Data and address register. */
97 unsigned int reg_mask
;
101 unsigned int fpu_mask
;
103 /* Offsets relative to ARG_POINTER. */
104 HOST_WIDE_INT frame_pointer_offset
;
105 HOST_WIDE_INT stack_pointer_offset
;
107 /* Function which the above information refers to. */
111 /* Current frame information calculated by m68k_compute_frame_layout(). */
112 static struct m68k_frame current_frame
;
114 /* Structure describing an m68k address.
116 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
117 with null fields evaluating to 0. Here:
119 - BASE satisfies m68k_legitimate_base_reg_p
120 - INDEX satisfies m68k_legitimate_index_reg_p
121 - OFFSET satisfies m68k_legitimate_constant_address_p
123 INDEX is either HImode or SImode. The other fields are SImode.
125 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
126 the address is (BASE)+. */
127 struct m68k_address
{
135 static bool m68k_handle_option (size_t, const char *, int);
136 static rtx
find_addr_reg (rtx
);
137 static const char *singlemove_string (rtx
*);
138 #ifdef M68K_TARGET_COFF
139 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
140 #endif /* M68K_TARGET_COFF */
141 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
142 HOST_WIDE_INT
, tree
);
143 static rtx
m68k_struct_value_rtx (tree
, int);
144 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
145 tree args
, int flags
,
147 static void m68k_compute_frame_layout (void);
148 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
149 static bool m68k_ok_for_sibcall_p (tree
, tree
);
150 static bool m68k_rtx_costs (rtx
, int, int, int *);
153 /* Specify the identification number of the library being built */
154 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
156 /* Nonzero if the last compare/test insn had FP operands. The
157 sCC expanders peek at this to determine what to do for the
158 68060, which has no fsCC instructions. */
159 int m68k_last_compare_had_fp_operands
;
161 /* Initialize the GCC target structure. */
163 #if INT_OP_GROUP == INT_OP_DOT_WORD
164 #undef TARGET_ASM_ALIGNED_HI_OP
165 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
168 #if INT_OP_GROUP == INT_OP_NO_DOT
169 #undef TARGET_ASM_BYTE_OP
170 #define TARGET_ASM_BYTE_OP "\tbyte\t"
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
173 #undef TARGET_ASM_ALIGNED_SI_OP
174 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
177 #if INT_OP_GROUP == INT_OP_DC
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
186 #undef TARGET_ASM_UNALIGNED_HI_OP
187 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
188 #undef TARGET_ASM_UNALIGNED_SI_OP
189 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
191 #undef TARGET_ASM_OUTPUT_MI_THUNK
192 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
193 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
194 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
196 #undef TARGET_ASM_FILE_START_APP_OFF
197 #define TARGET_ASM_FILE_START_APP_OFF true
199 #undef TARGET_DEFAULT_TARGET_FLAGS
200 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
201 #undef TARGET_HANDLE_OPTION
202 #define TARGET_HANDLE_OPTION m68k_handle_option
204 #undef TARGET_RTX_COSTS
205 #define TARGET_RTX_COSTS m68k_rtx_costs
207 #undef TARGET_ATTRIBUTE_TABLE
208 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
210 #undef TARGET_PROMOTE_PROTOTYPES
211 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
213 #undef TARGET_STRUCT_VALUE_RTX
214 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
216 #undef TARGET_CANNOT_FORCE_CONST_MEM
217 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
219 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
220 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
222 static const struct attribute_spec m68k_attribute_table
[] =
224 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
225 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
226 { NULL
, 0, 0, false, false, false, NULL
}
229 struct gcc_target targetm
= TARGET_INITIALIZER
;
231 /* Base flags for 68k ISAs. */
232 #define FL_FOR_isa_00 FL_ISA_68000
233 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
234 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
235 generated 68881 code for 68020 and 68030 targets unless explicitly told
237 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
238 | FL_BITFIELD | FL_68881)
239 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
240 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
242 /* Base flags for ColdFire ISAs. */
243 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
244 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
245 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
246 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
247 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
251 /* Traditional 68000 instruction sets. */
257 /* ColdFire instruction set variants. */
265 /* Information about one of the -march, -mcpu or -mtune arguments. */
266 struct m68k_target_selection
268 /* The argument being described. */
271 /* For -mcpu, this is the device selected by the option.
272 For -mtune and -march, it is a representative device
273 for the microarchitecture or ISA respectively. */
274 enum target_device device
;
276 /* The M68K_DEVICE fields associated with DEVICE. See the comment
277 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
279 enum uarch_type microarch
;
284 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
285 static const struct m68k_target_selection all_devices
[] =
287 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
288 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
289 #include "m68k-devices.def"
291 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
294 /* A list of all ISAs, mapping each one to a representative device.
295 Used for -march selection. */
296 static const struct m68k_target_selection all_isas
[] =
298 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
299 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
300 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
301 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
302 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
303 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
304 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
305 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
307 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
309 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
310 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
313 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
316 /* A list of all microarchitectures, mapping each one to a representative
317 device. Used for -mtune selection. */
318 static const struct m68k_target_selection all_microarchs
[] =
320 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
321 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
322 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
323 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
324 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
325 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
326 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
327 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
328 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
329 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
330 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
332 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
333 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
337 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
340 /* The entries associated with the -mcpu, -march and -mtune settings,
341 or null for options that have not been used. */
342 const struct m68k_target_selection
*m68k_cpu_entry
;
343 const struct m68k_target_selection
*m68k_arch_entry
;
344 const struct m68k_target_selection
*m68k_tune_entry
;
346 /* Which CPU we are generating code for. */
347 enum target_device m68k_cpu
;
349 /* Which microarchitecture to tune for. */
350 enum uarch_type m68k_tune
;
352 /* Which FPU to use. */
353 enum fpu_type m68k_fpu
;
355 /* The set of FL_* flags that apply to the target processor. */
356 unsigned int m68k_cpu_flags
;
358 /* Asm templates for calling or jumping to an arbitrary symbolic address,
359 or NULL if such calls or jumps are not supported. The address is held
361 const char *m68k_symbolic_call
;
362 const char *m68k_symbolic_jump
;
364 /* See whether TABLE has an entry with name NAME. Return true and
365 store the entry in *ENTRY if so, otherwise return false and
366 leave *ENTRY alone. */
369 m68k_find_selection (const struct m68k_target_selection
**entry
,
370 const struct m68k_target_selection
*table
,
375 for (i
= 0; table
[i
].name
; i
++)
376 if (strcmp (table
[i
].name
, name
) == 0)
384 /* Implement TARGET_HANDLE_OPTION. */
387 m68k_handle_option (size_t code
, const char *arg
, int value
)
392 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
395 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
398 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
401 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
404 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
407 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
410 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
413 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
416 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
420 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
423 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
427 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
430 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
432 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
435 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
437 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
440 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
443 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
446 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
449 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
453 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
455 case OPT_mshared_library_id_
:
456 if (value
> MAX_LIBRARY_ID
)
457 error ("-mshared-library-id=%s is not between 0 and %d",
458 arg
, MAX_LIBRARY_ID
);
460 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
468 /* Sometimes certain combinations of command options do not make
469 sense on a particular target machine. You can define a macro
470 `OVERRIDE_OPTIONS' to take account of this. This macro, if
471 defined, is executed once just after all the command options have
474 Don't use this macro to turn on various extra optimizations for
475 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
478 override_options (void)
480 const struct m68k_target_selection
*entry
;
481 unsigned long target_mask
;
489 -march=ARCH should generate code that runs any processor
490 implementing architecture ARCH. -mcpu=CPU should override -march
491 and should generate code that runs on processor CPU, making free
492 use of any instructions that CPU understands. -mtune=UARCH applies
493 on top of -mcpu or -march and optimizes the code for UARCH. It does
494 not change the target architecture. */
497 /* Complain if the -march setting is for a different microarchitecture,
498 or includes flags that the -mcpu setting doesn't. */
500 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
501 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
502 warning (0, "-mcpu=%s conflicts with -march=%s",
503 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
505 entry
= m68k_cpu_entry
;
508 entry
= m68k_arch_entry
;
511 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
513 m68k_cpu_flags
= entry
->flags
;
515 /* Use the architecture setting to derive default values for
518 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
519 target_mask
|= MASK_BITFIELD
;
520 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
521 target_mask
|= MASK_CF_HWDIV
;
522 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
523 target_mask
|= MASK_HARD_FLOAT
;
524 target_flags
|= target_mask
& ~target_flags_explicit
;
526 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
527 m68k_cpu
= entry
->device
;
529 m68k_tune
= m68k_tune_entry
->microarch
;
530 #ifdef M68K_DEFAULT_TUNE
531 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
532 m68k_tune
= M68K_DEFAULT_TUNE
;
535 m68k_tune
= entry
->microarch
;
537 /* Set the type of FPU. */
538 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
539 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
542 if (TARGET_COLDFIRE_FPU
)
544 REAL_MODE_FORMAT (SFmode
) = &coldfire_single_format
;
545 REAL_MODE_FORMAT (DFmode
) = &coldfire_double_format
;
548 /* Sanity check to ensure that msep-data and mid-sahred-library are not
549 * both specified together. Doing so simply doesn't make sense.
551 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
552 error ("cannot specify both -msep-data and -mid-shared-library");
554 /* If we're generating code for a separate A5 relative data segment,
555 * we've got to enable -fPIC as well. This might be relaxable to
556 * -fpic but it hasn't been tested properly.
558 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
561 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
562 error if the target does not support them. */
563 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
564 error ("-mpcrel -fPIC is not currently supported on selected cpu");
566 /* ??? A historic way of turning on pic, or is this intended to
567 be an embedded thing that doesn't have the same name binding
568 significance that it does on hosted ELF systems? */
569 if (TARGET_PCREL
&& flag_pic
== 0)
574 #if MOTOROLA && !defined (USE_GAS)
575 m68k_symbolic_call
= "jsr %a0";
576 m68k_symbolic_jump
= "jmp %a0";
578 m68k_symbolic_call
= "jbsr %a0";
579 m68k_symbolic_jump
= "jra %a0";
582 else if (TARGET_ID_SHARED_LIBRARY
)
583 /* All addresses must be loaded from the GOT. */
585 else if (TARGET_68020
|| TARGET_ISAB
)
589 m68k_symbolic_call
= "bsr.l %c0";
590 m68k_symbolic_jump
= "bra.l %c0";
595 m68k_symbolic_call
= "bsr.l %p0";
596 m68k_symbolic_jump
= "bra.l %p0";
598 m68k_symbolic_call
= "bsr %p0";
599 m68k_symbolic_jump
= "bra %p0";
602 /* Turn off function cse if we are doing PIC. We always want
603 function call to be done as `bsr foo@PLTPC'. */
604 /* ??? It's traditional to do this for -mpcrel too, but it isn't
605 clear how intentional that is. */
606 flag_no_function_cse
= 1;
609 SUBTARGET_OVERRIDE_OPTIONS
;
612 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
613 given argument and NAME is the argument passed to -mcpu. Return NULL
614 if -mcpu was not passed. */
617 m68k_cpp_cpu_ident (const char *prefix
)
621 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
624 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
625 given argument and NAME is the name of the representative device for
626 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
629 m68k_cpp_cpu_family (const char *prefix
)
633 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
636 /* Return nonzero if FUNC is an interrupt function as specified by the
637 "interrupt_handler" attribute. */
639 m68k_interrupt_function_p (tree func
)
643 if (TREE_CODE (func
) != FUNCTION_DECL
)
646 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
647 return (a
!= NULL_TREE
);
650 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
651 struct attribute_spec.handler. */
653 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
654 tree args ATTRIBUTE_UNUSED
,
655 int flags ATTRIBUTE_UNUSED
,
658 if (TREE_CODE (*node
) != FUNCTION_DECL
)
660 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
661 IDENTIFIER_POINTER (name
));
662 *no_add_attrs
= true;
669 m68k_compute_frame_layout (void)
673 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
675 /* Only compute the frame once per function.
676 Don't cache information until reload has been completed. */
677 if (current_frame
.funcdef_no
== current_function_funcdef_no
681 current_frame
.size
= (get_frame_size () + 3) & -4;
684 for (regno
= 0; regno
< 16; regno
++)
685 if (m68k_save_reg (regno
, interrupt_handler
))
687 mask
|= 1 << (regno
- D0_REG
);
690 current_frame
.offset
= saved
* 4;
691 current_frame
.reg_no
= saved
;
692 current_frame
.reg_mask
= mask
;
694 current_frame
.foffset
= 0;
696 if (TARGET_HARD_FLOAT
)
698 for (regno
= 16; regno
< 24; regno
++)
699 if (m68k_save_reg (regno
, interrupt_handler
))
701 mask
|= 1 << (regno
- FP0_REG
);
704 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
705 current_frame
.offset
+= current_frame
.foffset
;
707 current_frame
.fpu_no
= saved
;
708 current_frame
.fpu_mask
= mask
;
710 /* Remember what function this frame refers to. */
711 current_frame
.funcdef_no
= current_function_funcdef_no
;
715 m68k_initial_elimination_offset (int from
, int to
)
718 /* The arg pointer points 8 bytes before the start of the arguments,
719 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
720 frame pointer in most frames. */
721 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
722 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
723 return argptr_offset
;
725 m68k_compute_frame_layout ();
727 gcc_assert (to
== STACK_POINTER_REGNUM
);
730 case ARG_POINTER_REGNUM
:
731 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
732 case FRAME_POINTER_REGNUM
:
733 return current_frame
.offset
+ current_frame
.size
;
739 /* Refer to the array `regs_ever_live' to determine which registers
740 to save; `regs_ever_live[I]' is nonzero if register number I
741 is ever used in the function. This function is responsible for
742 knowing which registers should not be saved even if used.
743 Return true if we need to save REGNO. */
746 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
748 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
750 if (current_function_uses_pic_offset_table
)
754 if (current_function_calls_eh_return
)
759 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
760 if (test
== INVALID_REGNUM
)
767 /* Fixed regs we never touch. */
768 if (fixed_regs
[regno
])
771 /* The frame pointer (if it is such) is handled specially. */
772 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
775 /* Interrupt handlers must also save call_used_regs
776 if they are live or when calling nested functions. */
777 if (interrupt_handler
)
779 if (regs_ever_live
[regno
])
782 if (!current_function_is_leaf
&& call_used_regs
[regno
])
786 /* Never need to save registers that aren't touched. */
787 if (!regs_ever_live
[regno
])
790 /* Otherwise save everything that isn't call-clobbered. */
791 return !call_used_regs
[regno
];
794 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
795 the lowest memory address. COUNT is the number of registers to be
796 moved, with register REGNO + I being moved if bit I of MASK is set.
797 STORE_P specifies the direction of the move and ADJUST_STACK_P says
798 whether or not this is pre-decrement (if STORE_P) or post-increment
799 (if !STORE_P) operation. */
802 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
803 unsigned int count
, unsigned int regno
,
804 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
807 rtx body
, addr
, src
, operands
[2];
808 enum machine_mode mode
;
810 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
811 mode
= reg_raw_mode
[regno
];
816 src
= plus_constant (base
, (count
817 * GET_MODE_SIZE (mode
)
818 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
819 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
822 for (; mask
!= 0; mask
>>= 1, regno
++)
825 addr
= plus_constant (base
, offset
);
826 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
827 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
828 XVECEXP (body
, 0, i
++)
829 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
830 offset
+= GET_MODE_SIZE (mode
);
832 gcc_assert (i
== XVECLEN (body
, 0));
834 return emit_insn (body
);
837 /* Make INSN a frame-related instruction. */
840 m68k_set_frame_related (rtx insn
)
845 RTX_FRAME_RELATED_P (insn
) = 1;
846 body
= PATTERN (insn
);
847 if (GET_CODE (body
) == PARALLEL
)
848 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
849 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
852 /* Emit RTL for the "prologue" define_expand. */
855 m68k_expand_prologue (void)
857 HOST_WIDE_INT fsize_with_regs
;
858 rtx limit
, src
, dest
, insn
;
860 m68k_compute_frame_layout ();
862 /* If the stack limit is a symbol, we can check it here,
863 before actually allocating the space. */
864 if (current_function_limit_stack
865 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
867 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
868 if (!LEGITIMATE_CONSTANT_P (limit
))
870 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
871 limit
= gen_rtx_REG (Pmode
, D0_REG
);
873 emit_insn (gen_cmpsi (stack_pointer_rtx
, limit
));
874 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
875 cc0_rtx
, const0_rtx
),
879 fsize_with_regs
= current_frame
.size
;
882 /* ColdFire's move multiple instructions do not allow pre-decrement
883 addressing. Add the size of movem saves to the initial stack
884 allocation instead. */
885 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
886 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
887 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
888 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
891 if (frame_pointer_needed
)
893 if (fsize_with_regs
== 0 && TUNE_68040
)
895 /* On the 68040, two separate moves are faster than link.w 0. */
896 dest
= gen_frame_mem (Pmode
,
897 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
898 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
899 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
902 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
903 m68k_set_frame_related
904 (emit_insn (gen_link (frame_pointer_rtx
,
905 GEN_INT (-4 - fsize_with_regs
))));
908 m68k_set_frame_related
909 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
910 m68k_set_frame_related
911 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
913 GEN_INT (-fsize_with_regs
))));
916 else if (fsize_with_regs
!= 0)
917 m68k_set_frame_related
918 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
920 GEN_INT (-fsize_with_regs
))));
922 if (current_frame
.fpu_mask
)
924 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
926 m68k_set_frame_related
927 (m68k_emit_movem (stack_pointer_rtx
,
928 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
929 current_frame
.fpu_no
, FP0_REG
,
930 current_frame
.fpu_mask
, true, true));
935 /* If we're using moveml to save the integer registers,
936 the stack pointer will point to the bottom of the moveml
937 save area. Find the stack offset of the first FP register. */
938 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
941 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
942 m68k_set_frame_related
943 (m68k_emit_movem (stack_pointer_rtx
, offset
,
944 current_frame
.fpu_no
, FP0_REG
,
945 current_frame
.fpu_mask
, true, false));
949 /* If the stack limit is not a symbol, check it here.
950 This has the disadvantage that it may be too late... */
951 if (current_function_limit_stack
)
953 if (REG_P (stack_limit_rtx
))
955 emit_insn (gen_cmpsi (stack_pointer_rtx
, stack_limit_rtx
));
956 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
957 cc0_rtx
, const0_rtx
),
960 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
961 warning (0, "stack limit expression is not supported");
964 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
966 /* Store each register separately in the same order moveml does. */
969 for (i
= 16; i
-- > 0; )
970 if (current_frame
.reg_mask
& (1 << i
))
972 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
973 dest
= gen_frame_mem (SImode
,
974 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
975 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
981 /* The required register save space has already been allocated.
982 The first register should be stored at (%sp). */
983 m68k_set_frame_related
984 (m68k_emit_movem (stack_pointer_rtx
, 0,
985 current_frame
.reg_no
, D0_REG
,
986 current_frame
.reg_mask
, true, false));
988 m68k_set_frame_related
989 (m68k_emit_movem (stack_pointer_rtx
,
990 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
991 current_frame
.reg_no
, D0_REG
,
992 current_frame
.reg_mask
, true, true));
997 && current_function_uses_pic_offset_table
)
999 insn
= emit_insn (gen_load_got (pic_offset_table_rtx
));
1000 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
1006 /* Return true if a simple (return) instruction is sufficient for this
1007 instruction (i.e. if no epilogue is needed). */
1010 m68k_use_return_insn (void)
1012 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1015 m68k_compute_frame_layout ();
1016 return current_frame
.offset
== 0;
1019 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1020 SIBCALL_P says which.
1022 The function epilogue should not depend on the current stack pointer!
1023 It should use the frame pointer only, if there is a frame pointer.
1024 This is mandatory because of alloca; we also take advantage of it to
1025 omit stack adjustments before returning. */
1028 m68k_expand_epilogue (bool sibcall_p
)
1030 HOST_WIDE_INT fsize
, fsize_with_regs
;
1031 bool big
, restore_from_sp
;
1033 m68k_compute_frame_layout ();
1035 fsize
= current_frame
.size
;
1037 restore_from_sp
= false;
1039 /* FIXME : current_function_is_leaf below is too strong.
1040 What we really need to know there is if there could be pending
1041 stack adjustment needed at that point. */
1042 restore_from_sp
= (!frame_pointer_needed
1043 || (!current_function_calls_alloca
1044 && current_function_is_leaf
));
1046 /* fsize_with_regs is the size we need to adjust the sp when
1047 popping the frame. */
1048 fsize_with_regs
= fsize
;
1049 if (TARGET_COLDFIRE
&& restore_from_sp
)
1051 /* ColdFire's move multiple instructions do not allow post-increment
1052 addressing. Add the size of movem loads to the final deallocation
1054 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1055 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1056 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1057 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1060 if (current_frame
.offset
+ fsize
>= 0x8000
1062 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1065 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1066 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1068 /* ColdFire's move multiple instructions do not support the
1069 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1070 stack-based restore. */
1071 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1072 GEN_INT (-(current_frame
.offset
+ fsize
)));
1073 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1074 gen_rtx_REG (Pmode
, A1_REG
),
1075 frame_pointer_rtx
));
1076 restore_from_sp
= true;
1080 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1086 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1088 /* Restore each register separately in the same order moveml does. */
1090 HOST_WIDE_INT offset
;
1092 offset
= current_frame
.offset
+ fsize
;
1093 for (i
= 0; i
< 16; i
++)
1094 if (current_frame
.reg_mask
& (1 << i
))
1100 /* Generate the address -OFFSET(%fp,%a1.l). */
1101 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1102 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1103 addr
= plus_constant (addr
, -offset
);
1105 else if (restore_from_sp
)
1106 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1108 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1109 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1110 gen_frame_mem (SImode
, addr
));
1111 offset
-= GET_MODE_SIZE (SImode
);
1114 else if (current_frame
.reg_mask
)
1117 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1118 gen_rtx_REG (Pmode
, A1_REG
),
1120 -(current_frame
.offset
+ fsize
),
1121 current_frame
.reg_no
, D0_REG
,
1122 current_frame
.reg_mask
, false, false);
1123 else if (restore_from_sp
)
1124 m68k_emit_movem (stack_pointer_rtx
, 0,
1125 current_frame
.reg_no
, D0_REG
,
1126 current_frame
.reg_mask
, false,
1129 m68k_emit_movem (frame_pointer_rtx
,
1130 -(current_frame
.offset
+ fsize
),
1131 current_frame
.reg_no
, D0_REG
,
1132 current_frame
.reg_mask
, false, false);
1135 if (current_frame
.fpu_no
> 0)
1138 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1139 gen_rtx_REG (Pmode
, A1_REG
),
1141 -(current_frame
.foffset
+ fsize
),
1142 current_frame
.fpu_no
, FP0_REG
,
1143 current_frame
.fpu_mask
, false, false);
1144 else if (restore_from_sp
)
1146 if (TARGET_COLDFIRE
)
1150 /* If we used moveml to restore the integer registers, the
1151 stack pointer will still point to the bottom of the moveml
1152 save area. Find the stack offset of the first FP
1154 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1157 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1158 m68k_emit_movem (stack_pointer_rtx
, offset
,
1159 current_frame
.fpu_no
, FP0_REG
,
1160 current_frame
.fpu_mask
, false, false);
1163 m68k_emit_movem (stack_pointer_rtx
, 0,
1164 current_frame
.fpu_no
, FP0_REG
,
1165 current_frame
.fpu_mask
, false, true);
1168 m68k_emit_movem (frame_pointer_rtx
,
1169 -(current_frame
.foffset
+ fsize
),
1170 current_frame
.fpu_no
, FP0_REG
,
1171 current_frame
.fpu_mask
, false, false);
1174 if (frame_pointer_needed
)
1175 emit_insn (gen_unlink (frame_pointer_rtx
));
1176 else if (fsize_with_regs
)
1177 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1179 GEN_INT (fsize_with_regs
)));
1181 if (current_function_calls_eh_return
)
1182 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1184 EH_RETURN_STACKADJ_RTX
));
1187 emit_insn (gen_rtx_RETURN (VOIDmode
));
1190 /* Return true if X is a valid comparison operator for the dbcc
1193 Note it rejects floating point comparison operators.
1194 (In the future we could use Fdbcc).
1196 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1199 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1201 switch (GET_CODE (x
))
1203 case EQ
: case NE
: case GTU
: case LTU
:
1207 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1209 case GT
: case LT
: case GE
: case LE
:
1210 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1216 /* Return nonzero if flags are currently in the 68881 flag register. */
1218 flags_in_68881 (void)
1220 /* We could add support for these in the future */
1221 return cc_status
.flags
& CC_IN_68881
;
1224 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. We cannot use sibcalls
1225 for nested functions because we use the static chain register for
1229 m68k_ok_for_sibcall_p (tree decl ATTRIBUTE_UNUSED
, tree exp
)
1231 return TREE_OPERAND (exp
, 2) == NULL
;
1234 /* Convert X to a legitimate function call memory reference and return the
1238 m68k_legitimize_call_address (rtx x
)
1240 gcc_assert (MEM_P (x
));
1241 if (call_operand (XEXP (x
, 0), VOIDmode
))
1243 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1246 /* Likewise for sibling calls. */
1249 m68k_legitimize_sibcall_address (rtx x
)
1251 gcc_assert (MEM_P (x
));
1252 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1255 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1256 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1259 /* Output a dbCC; jCC sequence. Note we do not handle the
1260 floating point version of this sequence (Fdbcc). We also
1261 do not handle alternative conditions when CC_NO_OVERFLOW is
1262 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1263 kick those out before we get here. */
1266 output_dbcc_and_branch (rtx
*operands
)
1268 switch (GET_CODE (operands
[3]))
1271 output_asm_insn (MOTOROLA
1272 ? "dbeq %0,%l1\n\tjbeq %l2"
1273 : "dbeq %0,%l1\n\tjeq %l2",
1278 output_asm_insn (MOTOROLA
1279 ? "dbne %0,%l1\n\tjbne %l2"
1280 : "dbne %0,%l1\n\tjne %l2",
1285 output_asm_insn (MOTOROLA
1286 ? "dbgt %0,%l1\n\tjbgt %l2"
1287 : "dbgt %0,%l1\n\tjgt %l2",
1292 output_asm_insn (MOTOROLA
1293 ? "dbhi %0,%l1\n\tjbhi %l2"
1294 : "dbhi %0,%l1\n\tjhi %l2",
1299 output_asm_insn (MOTOROLA
1300 ? "dblt %0,%l1\n\tjblt %l2"
1301 : "dblt %0,%l1\n\tjlt %l2",
1306 output_asm_insn (MOTOROLA
1307 ? "dbcs %0,%l1\n\tjbcs %l2"
1308 : "dbcs %0,%l1\n\tjcs %l2",
1313 output_asm_insn (MOTOROLA
1314 ? "dbge %0,%l1\n\tjbge %l2"
1315 : "dbge %0,%l1\n\tjge %l2",
1320 output_asm_insn (MOTOROLA
1321 ? "dbcc %0,%l1\n\tjbcc %l2"
1322 : "dbcc %0,%l1\n\tjcc %l2",
1327 output_asm_insn (MOTOROLA
1328 ? "dble %0,%l1\n\tjble %l2"
1329 : "dble %0,%l1\n\tjle %l2",
1334 output_asm_insn (MOTOROLA
1335 ? "dbls %0,%l1\n\tjbls %l2"
1336 : "dbls %0,%l1\n\tjls %l2",
1344 /* If the decrement is to be done in SImode, then we have
1345 to compensate for the fact that dbcc decrements in HImode. */
1346 switch (GET_MODE (operands
[0]))
1349 output_asm_insn (MOTOROLA
1350 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1351 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1364 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1367 enum rtx_code op_code
= GET_CODE (op
);
1369 /* This does not produce a useful cc. */
1372 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1373 below. Swap the operands and change the op if these requirements
1374 are not fulfilled. */
1375 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1379 operand1
= operand2
;
1381 op_code
= swap_condition (op_code
);
1383 loperands
[0] = operand1
;
1384 if (GET_CODE (operand1
) == REG
)
1385 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1387 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1388 if (operand2
!= const0_rtx
)
1390 loperands
[2] = operand2
;
1391 if (GET_CODE (operand2
) == REG
)
1392 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1394 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1396 loperands
[4] = gen_label_rtx ();
1397 if (operand2
!= const0_rtx
)
1399 output_asm_insn (MOTOROLA
1400 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1401 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1406 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1407 output_asm_insn ("tst%.l %0", loperands
);
1409 output_asm_insn ("cmp%.w #0,%0", loperands
);
1411 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1413 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1414 output_asm_insn ("tst%.l %1", loperands
);
1416 output_asm_insn ("cmp%.w #0,%1", loperands
);
1419 loperands
[5] = dest
;
1424 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1425 CODE_LABEL_NUMBER (loperands
[4]));
1426 output_asm_insn ("seq %5", loperands
);
1430 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1431 CODE_LABEL_NUMBER (loperands
[4]));
1432 output_asm_insn ("sne %5", loperands
);
1436 loperands
[6] = gen_label_rtx ();
1437 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1439 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1440 CODE_LABEL_NUMBER (loperands
[4]));
1441 output_asm_insn ("sgt %5", loperands
);
1442 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1443 CODE_LABEL_NUMBER (loperands
[6]));
1447 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1448 CODE_LABEL_NUMBER (loperands
[4]));
1449 output_asm_insn ("shi %5", loperands
);
1453 loperands
[6] = gen_label_rtx ();
1454 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1456 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1457 CODE_LABEL_NUMBER (loperands
[4]));
1458 output_asm_insn ("slt %5", loperands
);
1459 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1460 CODE_LABEL_NUMBER (loperands
[6]));
1464 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1465 CODE_LABEL_NUMBER (loperands
[4]));
1466 output_asm_insn ("scs %5", loperands
);
1470 loperands
[6] = gen_label_rtx ();
1471 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1473 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1474 CODE_LABEL_NUMBER (loperands
[4]));
1475 output_asm_insn ("sge %5", loperands
);
1476 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1477 CODE_LABEL_NUMBER (loperands
[6]));
1481 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1482 CODE_LABEL_NUMBER (loperands
[4]));
1483 output_asm_insn ("scc %5", loperands
);
1487 loperands
[6] = gen_label_rtx ();
1488 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1490 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1491 CODE_LABEL_NUMBER (loperands
[4]));
1492 output_asm_insn ("sle %5", loperands
);
1493 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1494 CODE_LABEL_NUMBER (loperands
[6]));
1498 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1499 CODE_LABEL_NUMBER (loperands
[4]));
1500 output_asm_insn ("sls %5", loperands
);
1510 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1512 operands
[0] = countop
;
1513 operands
[1] = dataop
;
1515 if (GET_CODE (countop
) == CONST_INT
)
1517 register int count
= INTVAL (countop
);
1518 /* If COUNT is bigger than size of storage unit in use,
1519 advance to the containing unit of same size. */
1520 if (count
> signpos
)
1522 int offset
= (count
& ~signpos
) / 8;
1523 count
= count
& signpos
;
1524 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1526 if (count
== signpos
)
1527 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1529 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1531 /* These three statements used to use next_insns_test_no...
1532 but it appears that this should do the same job. */
1534 && next_insn_tests_no_inequality (insn
))
1537 && next_insn_tests_no_inequality (insn
))
1540 && next_insn_tests_no_inequality (insn
))
1543 cc_status
.flags
= CC_NOT_NEGATIVE
;
1545 return "btst %0,%1";
1548 /* Return true if X is a legitimate base register. STRICT_P says
1549 whether we need strict checking. */
1552 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1554 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1555 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1560 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1561 : !DATA_REGNO_P (REGNO (x
)) && !FP_REGNO_P (REGNO (x
))));
1564 /* Return true if X is a legitimate index register. STRICT_P says
1565 whether we need strict checking. */
1568 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1570 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1575 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1576 : !FP_REGNO_P (REGNO (x
))));
1579 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1580 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1581 ADDRESS if so. STRICT_P says whether we need strict checking. */
1584 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1588 /* Check for a scale factor. */
1590 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1591 && GET_CODE (x
) == MULT
1592 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1593 && (INTVAL (XEXP (x
, 1)) == 2
1594 || INTVAL (XEXP (x
, 1)) == 4
1595 || (INTVAL (XEXP (x
, 1)) == 8
1596 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1598 scale
= INTVAL (XEXP (x
, 1));
1602 /* Check for a word extension. */
1603 if (!TARGET_COLDFIRE
1604 && GET_CODE (x
) == SIGN_EXTEND
1605 && GET_MODE (XEXP (x
, 0)) == HImode
)
1608 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1610 address
->scale
= scale
;
1618 /* Return true if X is an illegitimate symbolic constant. */
1621 m68k_illegitimate_symbolic_constant_p (rtx x
)
1625 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1627 split_const (x
, &base
, &offset
);
1628 if (GET_CODE (base
) == SYMBOL_REF
1629 && !offset_within_block_p (base
, INTVAL (offset
)))
1635 /* Return true if X is a legitimate constant address that can reach
1636 bytes in the range [X, X + REACH). STRICT_P says whether we need
1640 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1644 if (!CONSTANT_ADDRESS_P (x
))
1648 && !(strict_p
&& TARGET_PCREL
)
1649 && symbolic_operand (x
, VOIDmode
))
1652 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1654 split_const (x
, &base
, &offset
);
1655 if (GET_CODE (base
) == SYMBOL_REF
1656 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1663 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1664 labels will become jump tables. */
1667 m68k_jump_table_ref_p (rtx x
)
1669 if (GET_CODE (x
) != LABEL_REF
)
1673 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1676 x
= next_nonnote_insn (x
);
1677 return x
&& JUMP_TABLE_DATA_P (x
);
1680 /* Return true if X is a legitimate address for values of mode MODE.
1681 STRICT_P says whether strict checking is needed. If the address
1682 is valid, describe its components in *ADDRESS. */
1685 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1686 bool strict_p
, struct m68k_address
*address
)
1690 memset (address
, 0, sizeof (*address
));
1692 if (mode
== BLKmode
)
1695 reach
= GET_MODE_SIZE (mode
);
1697 /* Check for (An) (mode 2). */
1698 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1704 /* Check for -(An) and (An)+ (modes 3 and 4). */
1705 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1706 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1708 address
->code
= GET_CODE (x
);
1709 address
->base
= XEXP (x
, 0);
1713 /* Check for (d16,An) (mode 5). */
1714 if (GET_CODE (x
) == PLUS
1715 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1716 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1717 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1719 address
->base
= XEXP (x
, 0);
1720 address
->offset
= XEXP (x
, 1);
1724 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1725 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1728 && GET_CODE (x
) == PLUS
1729 && XEXP (x
, 0) == pic_offset_table_rtx
1730 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
1731 || GET_CODE (XEXP (x
, 1)) == LABEL_REF
))
1733 address
->base
= XEXP (x
, 0);
1734 address
->offset
= XEXP (x
, 1);
1738 /* The ColdFire FPU only accepts addressing modes 2-5. */
1739 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1742 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1743 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1744 All these modes are variations of mode 7. */
1745 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1747 address
->offset
= x
;
1751 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1754 ??? do_tablejump creates these addresses before placing the target
1755 label, so we have to assume that unplaced labels are jump table
1756 references. It seems unlikely that we would ever generate indexed
1757 accesses to unplaced labels in other cases. */
1758 if (GET_CODE (x
) == PLUS
1759 && m68k_jump_table_ref_p (XEXP (x
, 1))
1760 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1762 address
->offset
= XEXP (x
, 1);
1766 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1767 (bd,An,Xn.SIZE*SCALE) addresses. */
1771 /* Check for a nonzero base displacement. */
1772 if (GET_CODE (x
) == PLUS
1773 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
1775 address
->offset
= XEXP (x
, 1);
1779 /* Check for a suppressed index register. */
1780 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1786 /* Check for a suppressed base register. Do not allow this case
1787 for non-symbolic offsets as it effectively gives gcc freedom
1788 to treat data registers as base registers, which can generate
1791 && symbolic_operand (address
->offset
, VOIDmode
)
1792 && m68k_decompose_index (x
, strict_p
, address
))
1797 /* Check for a nonzero base displacement. */
1798 if (GET_CODE (x
) == PLUS
1799 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1800 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
1802 address
->offset
= XEXP (x
, 1);
1807 /* We now expect the sum of a base and an index. */
1808 if (GET_CODE (x
) == PLUS
)
1810 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
1811 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
1813 address
->base
= XEXP (x
, 0);
1817 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
1818 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1820 address
->base
= XEXP (x
, 1);
1827 /* Return true if X is a legitimate address for values of mode MODE.
1828 STRICT_P says whether strict checking is needed. */
1831 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
1833 struct m68k_address address
;
1835 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
1838 /* Return true if X is a memory, describing its address in ADDRESS if so.
1839 Apply strict checking if called during or after reload. */
1842 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
1845 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
1846 reload_in_progress
|| reload_completed
,
1850 /* Return true if X matches the 'Q' constraint. It must be a memory
1851 with a base address and no constant offset or index. */
1854 m68k_matches_q_p (rtx x
)
1856 struct m68k_address address
;
1858 return (m68k_legitimate_mem_p (x
, &address
)
1859 && address
.code
== UNKNOWN
1865 /* Return true if X matches the 'U' constraint. It must be a base address
1866 with a constant offset and no index. */
1869 m68k_matches_u_p (rtx x
)
1871 struct m68k_address address
;
1873 return (m68k_legitimate_mem_p (x
, &address
)
1874 && address
.code
== UNKNOWN
1880 /* Legitimize PIC addresses. If the address is already
1881 position-independent, we return ORIG. Newly generated
1882 position-independent addresses go to REG. If we need more
1883 than one register, we lose.
1885 An address is legitimized by making an indirect reference
1886 through the Global Offset Table with the name of the symbol
1889 The assembler and linker are responsible for placing the
1890 address of the symbol in the GOT. The function prologue
1891 is responsible for initializing a5 to the starting address
1894 The assembler is also responsible for translating a symbol name
1895 into a constant displacement from the start of the GOT.
1897 A quick example may make things a little clearer:
1899 When not generating PIC code to store the value 12345 into _foo
1900 we would generate the following code:
1904 When generating PIC two transformations are made. First, the compiler
1905 loads the address of foo into a register. So the first transformation makes:
1910 The code in movsi will intercept the lea instruction and call this
1911 routine which will transform the instructions into:
1913 movel a5@(_foo:w), a0
1917 That (in a nutshell) is how *all* symbol and label references are
1921 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1926 /* First handle a simple SYMBOL_REF or LABEL_REF */
1927 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1931 pic_ref
= gen_rtx_MEM (Pmode
,
1932 gen_rtx_PLUS (Pmode
,
1933 pic_offset_table_rtx
, orig
));
1934 current_function_uses_pic_offset_table
= 1;
1935 MEM_READONLY_P (pic_ref
) = 1;
1936 emit_move_insn (reg
, pic_ref
);
1939 else if (GET_CODE (orig
) == CONST
)
1943 /* Make sure this has not already been legitimized. */
1944 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1945 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1950 /* legitimize both operands of the PLUS */
1951 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1953 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1954 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1955 base
== reg
? 0 : reg
);
1957 if (GET_CODE (orig
) == CONST_INT
)
1958 return plus_constant (base
, INTVAL (orig
));
1959 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1960 /* Likewise, should we set special REG_NOTEs here? */
1966 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1968 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1970 /* Return the type of move that should be used for integer I. */
1973 const_method (HOST_WIDE_INT i
)
1980 /* The ColdFire doesn't have byte or word operations. */
1981 /* FIXME: This may not be useful for the m68060 either. */
1982 if (!TARGET_COLDFIRE
)
1984 /* if -256 < N < 256 but N is not in range for a moveq
1985 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1986 if (USE_MOVQ (i
^ 0xff))
1988 /* Likewise, try with not.w */
1989 if (USE_MOVQ (i
^ 0xffff))
1991 /* This is the only value where neg.w is useful */
1996 /* Try also with swap. */
1998 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2003 /* Try using MVZ/MVS with an immediate value to load constants. */
2004 if (i
>= 0 && i
<= 65535)
2006 if (i
>= -32768 && i
<= 32767)
2010 /* Otherwise, use move.l */
2014 /* Return the cost of moving constant I into a data register. */
2017 const_int_cost (HOST_WIDE_INT i
)
2019 switch (const_method (i
))
2022 /* Constants between -128 and 127 are cheap due to moveq. */
2030 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2040 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2045 /* Constant zero is super cheap due to clr instruction. */
2046 if (x
== const0_rtx
)
2049 *total
= const_int_cost (INTVAL (x
));
2059 /* Make 0.0 cheaper than other floating constants to
2060 encourage creating tstsf and tstdf insns. */
2061 if (outer_code
== COMPARE
2062 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2068 /* These are vaguely right for a 68020. */
2069 /* The costs for long multiply have been adjusted to work properly
2070 in synth_mult on the 68020, relative to an average of the time
2071 for add and the time for shift, taking away a little more because
2072 sometimes move insns are needed. */
2073 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2079 : TARGET_COLDFIRE ? 3 : 13)
2084 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2085 : TARGET_COLDFIRE ? 2 : 8)
2088 (TARGET_CF_HWDIV ? 11 \
2089 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2092 /* An lea costs about three times as much as a simple add. */
2093 if (GET_MODE (x
) == SImode
2094 && GET_CODE (XEXP (x
, 1)) == REG
2095 && GET_CODE (XEXP (x
, 0)) == MULT
2096 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2097 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2098 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2099 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2100 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2102 /* lea an@(dx:l:i),am */
2103 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2113 *total
= COSTS_N_INSNS(1);
2118 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2120 if (INTVAL (XEXP (x
, 1)) < 16)
2121 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2123 /* We're using clrw + swap for these cases. */
2124 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2127 *total
= COSTS_N_INSNS (10); /* Worst case. */
2130 /* A shift by a big integer takes an extra instruction. */
2131 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2132 && (INTVAL (XEXP (x
, 1)) == 16))
2134 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2137 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2138 && !(INTVAL (XEXP (x
, 1)) > 0
2139 && INTVAL (XEXP (x
, 1)) <= 8))
2141 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2147 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2148 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2149 && GET_MODE (x
) == SImode
)
2150 *total
= COSTS_N_INSNS (MULW_COST
);
2151 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2152 *total
= COSTS_N_INSNS (MULW_COST
);
2154 *total
= COSTS_N_INSNS (MULL_COST
);
2161 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2162 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2163 else if (TARGET_CF_HWDIV
)
2164 *total
= COSTS_N_INSNS (18);
2166 *total
= COSTS_N_INSNS (43); /* div.l */
2174 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2178 output_move_const_into_data_reg (rtx
*operands
)
2182 i
= INTVAL (operands
[1]);
2183 switch (const_method (i
))
2186 return "mvzw %1,%0";
2188 return "mvsw %1,%0";
2190 return "moveq %1,%0";
2193 operands
[1] = GEN_INT (i
^ 0xff);
2194 return "moveq %1,%0\n\tnot%.b %0";
2197 operands
[1] = GEN_INT (i
^ 0xffff);
2198 return "moveq %1,%0\n\tnot%.w %0";
2201 return "moveq #-128,%0\n\tneg%.w %0";
2206 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2207 return "moveq %1,%0\n\tswap %0";
2210 return "move%.l %1,%0";
2216 /* Return true if I can be handled by ISA B's mov3q instruction. */
2219 valid_mov3q_const (HOST_WIDE_INT i
)
2221 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2224 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2225 I is the value of OPERANDS[1]. */
2228 output_move_simode_const (rtx
*operands
)
2234 src
= INTVAL (operands
[1]);
2236 && (DATA_REG_P (dest
) || MEM_P (dest
))
2237 /* clr insns on 68000 read before writing. */
2238 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2239 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2241 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2242 return "mov3q%.l %1,%0";
2243 else if (src
== 0 && ADDRESS_REG_P (dest
))
2244 return "sub%.l %0,%0";
2245 else if (DATA_REG_P (dest
))
2246 return output_move_const_into_data_reg (operands
);
2247 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2249 if (valid_mov3q_const (src
))
2250 return "mov3q%.l %1,%0";
2251 return "move%.w %1,%0";
2253 else if (MEM_P (dest
)
2254 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2255 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2256 && IN_RANGE (src
, -0x8000, 0x7fff))
2258 if (valid_mov3q_const (src
))
2259 return "mov3q%.l %1,%-";
2262 return "move%.l %1,%0";
2266 output_move_simode (rtx
*operands
)
2268 if (GET_CODE (operands
[1]) == CONST_INT
)
2269 return output_move_simode_const (operands
);
2270 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2271 || GET_CODE (operands
[1]) == CONST
)
2272 && push_operand (operands
[0], SImode
))
2274 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2275 || GET_CODE (operands
[1]) == CONST
)
2276 && ADDRESS_REG_P (operands
[0]))
2277 return "lea %a1,%0";
2278 return "move%.l %1,%0";
2282 output_move_himode (rtx
*operands
)
2284 if (GET_CODE (operands
[1]) == CONST_INT
)
2286 if (operands
[1] == const0_rtx
2287 && (DATA_REG_P (operands
[0])
2288 || GET_CODE (operands
[0]) == MEM
)
2289 /* clr insns on 68000 read before writing. */
2290 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2291 || !(GET_CODE (operands
[0]) == MEM
2292 && MEM_VOLATILE_P (operands
[0]))))
2294 else if (operands
[1] == const0_rtx
2295 && ADDRESS_REG_P (operands
[0]))
2296 return "sub%.l %0,%0";
2297 else if (DATA_REG_P (operands
[0])
2298 && INTVAL (operands
[1]) < 128
2299 && INTVAL (operands
[1]) >= -128)
2300 return "moveq %1,%0";
2301 else if (INTVAL (operands
[1]) < 0x8000
2302 && INTVAL (operands
[1]) >= -0x8000)
2303 return "move%.w %1,%0";
2305 else if (CONSTANT_P (operands
[1]))
2306 return "move%.l %1,%0";
2307 /* Recognize the insn before a tablejump, one that refers
2308 to a table of offsets. Such an insn will need to refer
2309 to a label on the insn. So output one. Use the label-number
2310 of the table of offsets to generate this label. This code,
2311 and similar code below, assumes that there will be at most one
2312 reference to each table. */
2313 if (GET_CODE (operands
[1]) == MEM
2314 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2315 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2316 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2318 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2320 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2321 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2323 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2324 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2326 return "move%.w %1,%0";
2330 output_move_qimode (rtx
*operands
)
2332 /* 68k family always modifies the stack pointer by at least 2, even for
2333 byte pushes. The 5200 (ColdFire) does not do this. */
2335 /* This case is generated by pushqi1 pattern now. */
2336 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2337 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2338 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2339 && ! ADDRESS_REG_P (operands
[1])
2340 && ! TARGET_COLDFIRE
));
2342 /* clr and st insns on 68000 read before writing. */
2343 if (!ADDRESS_REG_P (operands
[0])
2344 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2345 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2347 if (operands
[1] == const0_rtx
)
2349 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2350 && GET_CODE (operands
[1]) == CONST_INT
2351 && (INTVAL (operands
[1]) & 255) == 255)
2357 if (GET_CODE (operands
[1]) == CONST_INT
2358 && DATA_REG_P (operands
[0])
2359 && INTVAL (operands
[1]) < 128
2360 && INTVAL (operands
[1]) >= -128)
2361 return "moveq %1,%0";
2362 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2363 return "sub%.l %0,%0";
2364 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2365 return "move%.l %1,%0";
2366 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2367 from address registers. */
2368 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2369 return "move%.w %1,%0";
2370 return "move%.b %1,%0";
2374 output_move_stricthi (rtx
*operands
)
2376 if (operands
[1] == const0_rtx
2377 /* clr insns on 68000 read before writing. */
2378 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2379 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2381 return "move%.w %1,%0";
2385 output_move_strictqi (rtx
*operands
)
2387 if (operands
[1] == const0_rtx
2388 /* clr insns on 68000 read before writing. */
2389 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2390 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2392 return "move%.b %1,%0";
2395 /* Return the best assembler insn template
2396 for moving operands[1] into operands[0] as a fullword. */
2399 singlemove_string (rtx
*operands
)
2401 if (GET_CODE (operands
[1]) == CONST_INT
)
2402 return output_move_simode_const (operands
);
2403 return "move%.l %1,%0";
2407 /* Output assembler code to perform a doubleword move insn
2408 with operands OPERANDS. */
2411 output_move_double (rtx
*operands
)
2415 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2420 rtx addreg0
= 0, addreg1
= 0;
2421 int dest_overlapped_low
= 0;
2422 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2427 /* First classify both operands. */
2429 if (REG_P (operands
[0]))
2431 else if (offsettable_memref_p (operands
[0]))
2433 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2435 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2437 else if (GET_CODE (operands
[0]) == MEM
)
2442 if (REG_P (operands
[1]))
2444 else if (CONSTANT_P (operands
[1]))
2446 else if (offsettable_memref_p (operands
[1]))
2448 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2450 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2452 else if (GET_CODE (operands
[1]) == MEM
)
2457 /* Check for the cases that the operand constraints are not supposed
2458 to allow to happen. Generating code for these cases is
2460 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2462 /* If one operand is decrementing and one is incrementing
2463 decrement the former register explicitly
2464 and change that operand into ordinary indexing. */
2466 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2468 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2470 output_asm_insn ("sub%.l #12,%0", operands
);
2472 output_asm_insn ("subq%.l #8,%0", operands
);
2473 if (GET_MODE (operands
[1]) == XFmode
)
2474 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2475 else if (GET_MODE (operands
[0]) == DFmode
)
2476 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2478 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2481 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2483 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2485 output_asm_insn ("sub%.l #12,%1", operands
);
2487 output_asm_insn ("subq%.l #8,%1", operands
);
2488 if (GET_MODE (operands
[1]) == XFmode
)
2489 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2490 else if (GET_MODE (operands
[1]) == DFmode
)
2491 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2493 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2497 /* If an operand is an unoffsettable memory ref, find a register
2498 we can increment temporarily to make it refer to the second word. */
2500 if (optype0
== MEMOP
)
2501 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2503 if (optype1
== MEMOP
)
2504 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2506 /* Ok, we can do one word at a time.
2507 Normally we do the low-numbered word first,
2508 but if either operand is autodecrementing then we
2509 do the high-numbered word first.
2511 In either case, set up in LATEHALF the operands to use
2512 for the high-numbered word and in some cases alter the
2513 operands in OPERANDS to be suitable for the low-numbered word. */
2517 if (optype0
== REGOP
)
2519 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2520 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2522 else if (optype0
== OFFSOP
)
2524 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2525 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2529 middlehalf
[0] = operands
[0];
2530 latehalf
[0] = operands
[0];
2533 if (optype1
== REGOP
)
2535 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2536 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2538 else if (optype1
== OFFSOP
)
2540 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2541 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2543 else if (optype1
== CNSTOP
)
2545 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2550 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2551 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2552 operands
[1] = GEN_INT (l
[0]);
2553 middlehalf
[1] = GEN_INT (l
[1]);
2554 latehalf
[1] = GEN_INT (l
[2]);
2558 /* No non-CONST_DOUBLE constant should ever appear
2560 gcc_assert (!CONSTANT_P (operands
[1]));
2565 middlehalf
[1] = operands
[1];
2566 latehalf
[1] = operands
[1];
2570 /* size is not 12: */
2572 if (optype0
== REGOP
)
2573 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2574 else if (optype0
== OFFSOP
)
2575 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2577 latehalf
[0] = operands
[0];
2579 if (optype1
== REGOP
)
2580 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2581 else if (optype1
== OFFSOP
)
2582 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2583 else if (optype1
== CNSTOP
)
2584 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2586 latehalf
[1] = operands
[1];
2589 /* If insn is effectively movd N(sp),-(sp) then we will do the
2590 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2591 for the low word as well, to compensate for the first decrement of sp. */
2592 if (optype0
== PUSHOP
2593 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2594 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2595 operands
[1] = middlehalf
[1] = latehalf
[1];
2597 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2598 if the upper part of reg N does not appear in the MEM, arrange to
2599 emit the move late-half first. Otherwise, compute the MEM address
2600 into the upper part of N and use that as a pointer to the memory
2602 if (optype0
== REGOP
2603 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2605 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2607 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2608 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2610 /* If both halves of dest are used in the src memory address,
2611 compute the address into latehalf of dest.
2612 Note that this can't happen if the dest is two data regs. */
2614 xops
[0] = latehalf
[0];
2615 xops
[1] = XEXP (operands
[1], 0);
2616 output_asm_insn ("lea %a1,%0", xops
);
2617 if (GET_MODE (operands
[1]) == XFmode
)
2619 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2620 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2621 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2625 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2626 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2630 && reg_overlap_mentioned_p (middlehalf
[0],
2631 XEXP (operands
[1], 0)))
2633 /* Check for two regs used by both source and dest.
2634 Note that this can't happen if the dest is all data regs.
2635 It can happen if the dest is d6, d7, a0.
2636 But in that case, latehalf is an addr reg, so
2637 the code at compadr does ok. */
2639 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2640 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2643 /* JRV says this can't happen: */
2644 gcc_assert (!addreg0
&& !addreg1
);
2646 /* Only the middle reg conflicts; simply put it last. */
2647 output_asm_insn (singlemove_string (operands
), operands
);
2648 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2649 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2652 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2653 /* If the low half of dest is mentioned in the source memory
2654 address, the arrange to emit the move late half first. */
2655 dest_overlapped_low
= 1;
2658 /* If one or both operands autodecrementing,
2659 do the two words, high-numbered first. */
2661 /* Likewise, the first move would clobber the source of the second one,
2662 do them in the other order. This happens only for registers;
2663 such overlap can't happen in memory unless the user explicitly
2664 sets it up, and that is an undefined circumstance. */
2666 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2667 || (optype0
== REGOP
&& optype1
== REGOP
2668 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2669 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2670 || dest_overlapped_low
)
2672 /* Make any unoffsettable addresses point at high-numbered word. */
2676 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2678 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2683 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2685 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2689 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2691 /* Undo the adds we just did. */
2693 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2695 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2699 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2701 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2703 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2706 /* Do low-numbered word. */
2707 return singlemove_string (operands
);
2710 /* Normal case: do the two words, low-numbered first. */
2712 output_asm_insn (singlemove_string (operands
), operands
);
2714 /* Do the middle one of the three words for long double */
2718 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2720 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2722 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2725 /* Make any unoffsettable addresses point at high-numbered word. */
2727 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2729 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2732 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2734 /* Undo the adds we just did. */
2738 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2740 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2745 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2747 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2754 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2755 new rtx with the correct mode. */
2758 force_mode (enum machine_mode mode
, rtx orig
)
2760 if (mode
== GET_MODE (orig
))
2763 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2766 return gen_rtx_REG (mode
, REGNO (orig
));
2770 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2772 return reg_renumber
&& FP_REG_P (op
);
2775 /* Emit insns to move operands[1] into operands[0].
2777 Return 1 if we have written out everything that needs to be done to
2778 do the move. Otherwise, return 0 and the caller will emit the move
2781 Note SCRATCH_REG may not be in the proper mode depending on how it
2782 will be used. This routine is responsible for creating a new copy
2783 of SCRATCH_REG in the proper mode. */
2786 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2788 register rtx operand0
= operands
[0];
2789 register rtx operand1
= operands
[1];
2793 && reload_in_progress
&& GET_CODE (operand0
) == REG
2794 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2795 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2796 else if (scratch_reg
2797 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2798 && GET_CODE (SUBREG_REG (operand0
)) == REG
2799 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2801 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2802 the code which tracks sets/uses for delete_output_reload. */
2803 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2804 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2805 SUBREG_BYTE (operand0
));
2806 operand0
= alter_subreg (&temp
);
2810 && reload_in_progress
&& GET_CODE (operand1
) == REG
2811 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2812 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2813 else if (scratch_reg
2814 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2815 && GET_CODE (SUBREG_REG (operand1
)) == REG
2816 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2818 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2819 the code which tracks sets/uses for delete_output_reload. */
2820 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2821 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2822 SUBREG_BYTE (operand1
));
2823 operand1
= alter_subreg (&temp
);
2826 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2827 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2828 != XEXP (operand0
, 0)))
2829 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2830 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2831 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2832 != XEXP (operand1
, 0)))
2833 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2835 /* Handle secondary reloads for loads/stores of FP registers where
2836 the address is symbolic by using the scratch register */
2837 if (fp_reg_operand (operand0
, mode
)
2838 && ((GET_CODE (operand1
) == MEM
2839 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2840 || ((GET_CODE (operand1
) == SUBREG
2841 && GET_CODE (XEXP (operand1
, 0)) == MEM
2842 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2845 if (GET_CODE (operand1
) == SUBREG
)
2846 operand1
= XEXP (operand1
, 0);
2848 /* SCRATCH_REG will hold an address. We want
2849 it in SImode regardless of what mode it was originally given
2851 scratch_reg
= force_mode (SImode
, scratch_reg
);
2853 /* D might not fit in 14 bits either; for such cases load D into
2855 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2857 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2858 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2860 XEXP (XEXP (operand1
, 0), 0),
2864 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2865 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2866 gen_rtx_MEM (mode
, scratch_reg
)));
2869 else if (fp_reg_operand (operand1
, mode
)
2870 && ((GET_CODE (operand0
) == MEM
2871 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2872 || ((GET_CODE (operand0
) == SUBREG
)
2873 && GET_CODE (XEXP (operand0
, 0)) == MEM
2874 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2877 if (GET_CODE (operand0
) == SUBREG
)
2878 operand0
= XEXP (operand0
, 0);
2880 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2881 it in SIMODE regardless of what mode it was originally given
2883 scratch_reg
= force_mode (SImode
, scratch_reg
);
2885 /* D might not fit in 14 bits either; for such cases load D into
2887 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2889 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2890 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2893 XEXP (XEXP (operand0
, 0),
2898 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2899 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2903 /* Handle secondary reloads for loads of FP registers from constant
2904 expressions by forcing the constant into memory.
2906 use scratch_reg to hold the address of the memory location.
2908 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2909 NO_REGS when presented with a const_int and an register class
2910 containing only FP registers. Doing so unfortunately creates
2911 more problems than it solves. Fix this for 2.5. */
2912 else if (fp_reg_operand (operand0
, mode
)
2913 && CONSTANT_P (operand1
)
2918 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2919 it in SIMODE regardless of what mode it was originally given
2921 scratch_reg
= force_mode (SImode
, scratch_reg
);
2923 /* Force the constant into memory and put the address of the
2924 memory location into scratch_reg. */
2925 xoperands
[0] = scratch_reg
;
2926 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2927 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2929 /* Now load the destination register. */
2930 emit_insn (gen_rtx_SET (mode
, operand0
,
2931 gen_rtx_MEM (mode
, scratch_reg
)));
2935 /* Now have insn-emit do whatever it normally does. */
2939 /* Split one or more DImode RTL references into pairs of SImode
2940 references. The RTL can be REG, offsettable MEM, integer constant, or
2941 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
2942 split and "num" is its length. lo_half and hi_half are output arrays
2943 that parallel "operands". */
2946 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
2950 rtx op
= operands
[num
];
2952 /* simplify_subreg refuses to split volatile memory addresses,
2953 but we still have to handle it. */
2954 if (GET_CODE (op
) == MEM
)
2956 lo_half
[num
] = adjust_address (op
, SImode
, 4);
2957 hi_half
[num
] = adjust_address (op
, SImode
, 0);
2961 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
2962 GET_MODE (op
) == VOIDmode
2963 ? DImode
: GET_MODE (op
), 4);
2964 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
2965 GET_MODE (op
) == VOIDmode
2966 ? DImode
: GET_MODE (op
), 0);
2971 /* Split X into a base and a constant offset, storing them in *BASE
2972 and *OFFSET respectively. */
2975 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
2978 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2980 *offset
+= INTVAL (XEXP (x
, 1));
2986 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
2987 instruction. STORE_P says whether the move is a load or store.
2989 If the instruction uses post-increment or pre-decrement addressing,
2990 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
2991 adjustment. This adjustment will be made by the first element of
2992 PARALLEL, with the loads or stores starting at element 1. If the
2993 instruction does not use post-increment or pre-decrement addressing,
2994 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
2995 start at element 0. */
2998 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
2999 HOST_WIDE_INT automod_offset
, bool store_p
)
3001 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3002 HOST_WIDE_INT offset
, mem_offset
;
3004 enum reg_class rclass
;
3006 len
= XVECLEN (pattern
, 0);
3007 first
= (automod_base
!= NULL
);
3011 /* Stores must be pre-decrement and loads must be post-increment. */
3012 if (store_p
!= (automod_offset
< 0))
3015 /* Work out the base and offset for lowest memory location. */
3016 base
= automod_base
;
3017 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3021 /* Allow any valid base and offset in the first access. */
3028 for (i
= first
; i
< len
; i
++)
3030 /* We need a plain SET. */
3031 set
= XVECEXP (pattern
, 0, i
);
3032 if (GET_CODE (set
) != SET
)
3035 /* Check that we have a memory location... */
3036 mem
= XEXP (set
, !store_p
);
3037 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3040 /* ...with the right address. */
3043 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3044 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3045 There are no mode restrictions for 680x0 besides the
3046 automodification rules enforced above. */
3048 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3053 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3054 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3058 /* Check that we have a register of the required mode and class. */
3059 reg
= XEXP (set
, store_p
);
3061 || !HARD_REGISTER_P (reg
)
3062 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3067 /* The register must belong to RCLASS and have a higher number
3068 than the register in the previous SET. */
3069 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3070 || REGNO (last_reg
) >= REGNO (reg
))
3075 /* Work out which register class we need. */
3076 if (INT_REGNO_P (REGNO (reg
)))
3077 rclass
= GENERAL_REGS
;
3078 else if (FP_REGNO_P (REGNO (reg
)))
3085 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3088 /* If we have an automodification, check whether the final offset is OK. */
3089 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3092 /* Reject unprofitable cases. */
3093 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3099 /* Return the assembly code template for a movem or fmovem instruction
3100 whose pattern is given by PATTERN. Store the template's operands
3103 If the instruction uses post-increment or pre-decrement addressing,
3104 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3105 is true if this is a store instruction. */
3108 m68k_output_movem (rtx
*operands
, rtx pattern
,
3109 HOST_WIDE_INT automod_offset
, bool store_p
)
3114 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3116 first
= (automod_offset
!= 0);
3117 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3119 /* When using movem with pre-decrement addressing, register X + D0_REG
3120 is controlled by bit 15 - X. For all other addressing modes,
3121 register X + D0_REG is controlled by bit X. Confusingly, the
3122 register mask for fmovem is in the opposite order to that for
3126 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3127 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3128 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3129 if (automod_offset
< 0)
3131 if (FP_REGNO_P (regno
))
3132 mask
|= 1 << (regno
- FP0_REG
);
3134 mask
|= 1 << (15 - (regno
- D0_REG
));
3138 if (FP_REGNO_P (regno
))
3139 mask
|= 1 << (7 - (regno
- FP0_REG
));
3141 mask
|= 1 << (regno
- D0_REG
);
3146 if (automod_offset
== 0)
3147 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3148 else if (automod_offset
< 0)
3149 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3151 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3152 operands
[1] = GEN_INT (mask
);
3153 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
3156 return MOTOROLA
? "fmovm %1,%a0" : "fmovem %1,%a0";
3158 return MOTOROLA
? "fmovm %a0,%1" : "fmovem %a0,%1";
3163 return MOTOROLA
? "movm.l %1,%a0" : "moveml %1,%a0";
3165 return MOTOROLA
? "movm.l %a0,%1" : "moveml %a0,%1";
3169 /* Return a REG that occurs in ADDR with coefficient 1.
3170 ADDR can be effectively incremented by incrementing REG. */
3173 find_addr_reg (rtx addr
)
3175 while (GET_CODE (addr
) == PLUS
)
3177 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3178 addr
= XEXP (addr
, 0);
3179 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3180 addr
= XEXP (addr
, 1);
3181 else if (CONSTANT_P (XEXP (addr
, 0)))
3182 addr
= XEXP (addr
, 1);
3183 else if (CONSTANT_P (XEXP (addr
, 1)))
3184 addr
= XEXP (addr
, 0);
3188 gcc_assert (GET_CODE (addr
) == REG
);
3192 /* Output assembler code to perform a 32-bit 3-operand add. */
3195 output_addsi3 (rtx
*operands
)
3197 if (! operands_match_p (operands
[0], operands
[1]))
3199 if (!ADDRESS_REG_P (operands
[1]))
3201 rtx tmp
= operands
[1];
3203 operands
[1] = operands
[2];
3207 /* These insns can result from reloads to access
3208 stack slots over 64k from the frame pointer. */
3209 if (GET_CODE (operands
[2]) == CONST_INT
3210 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
3211 return "move%.l %2,%0\n\tadd%.l %1,%0";
3212 if (GET_CODE (operands
[2]) == REG
)
3213 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3214 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3216 if (GET_CODE (operands
[2]) == CONST_INT
)
3218 if (INTVAL (operands
[2]) > 0
3219 && INTVAL (operands
[2]) <= 8)
3220 return "addq%.l %2,%0";
3221 if (INTVAL (operands
[2]) < 0
3222 && INTVAL (operands
[2]) >= -8)
3224 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
3225 return "subq%.l %2,%0";
3227 /* On the CPU32 it is faster to use two addql instructions to
3228 add a small integer (8 < N <= 16) to a register.
3229 Likewise for subql. */
3230 if (TUNE_CPU32
&& REG_P (operands
[0]))
3232 if (INTVAL (operands
[2]) > 8
3233 && INTVAL (operands
[2]) <= 16)
3235 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
3236 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3238 if (INTVAL (operands
[2]) < -8
3239 && INTVAL (operands
[2]) >= -16)
3241 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
3242 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3245 if (ADDRESS_REG_P (operands
[0])
3246 && INTVAL (operands
[2]) >= -0x8000
3247 && INTVAL (operands
[2]) < 0x8000)
3250 return "add%.w %2,%0";
3252 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3255 return "add%.l %2,%0";
3258 /* Store in cc_status the expressions that the condition codes will
3259 describe after execution of an instruction whose pattern is EXP.
3260 Do not alter them if the instruction would not alter the cc's. */
3262 /* On the 68000, all the insns to store in an address register fail to
3263 set the cc's. However, in some cases these instructions can make it
3264 possibly invalid to use the saved cc's. In those cases we clear out
3265 some or all of the saved cc's so they won't be used. */
3268 notice_update_cc (rtx exp
, rtx insn
)
3270 if (GET_CODE (exp
) == SET
)
3272 if (GET_CODE (SET_SRC (exp
)) == CALL
)
3274 else if (ADDRESS_REG_P (SET_DEST (exp
)))
3276 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
3277 cc_status
.value1
= 0;
3278 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
3279 cc_status
.value2
= 0;
3281 /* fmoves to memory or data registers do not set the condition
3282 codes. Normal moves _do_ set the condition codes, but not in
3283 a way that is appropriate for comparison with 0, because -0.0
3284 would be treated as a negative nonzero number. Note that it
3285 isn't appropriate to conditionalize this restriction on
3286 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3287 we care about the difference between -0.0 and +0.0. */
3288 else if (!FP_REG_P (SET_DEST (exp
))
3289 && SET_DEST (exp
) != cc0_rtx
3290 && (FP_REG_P (SET_SRC (exp
))
3291 || GET_CODE (SET_SRC (exp
)) == FIX
3292 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
3294 /* A pair of move insns doesn't produce a useful overall cc. */
3295 else if (!FP_REG_P (SET_DEST (exp
))
3296 && !FP_REG_P (SET_SRC (exp
))
3297 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
3298 && (GET_CODE (SET_SRC (exp
)) == REG
3299 || GET_CODE (SET_SRC (exp
)) == MEM
3300 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
3302 else if (SET_DEST (exp
) != pc_rtx
)
3304 cc_status
.flags
= 0;
3305 cc_status
.value1
= SET_DEST (exp
);
3306 cc_status
.value2
= SET_SRC (exp
);
3309 else if (GET_CODE (exp
) == PARALLEL
3310 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
3312 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
3313 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
3315 if (ADDRESS_REG_P (dest
))
3317 else if (dest
!= pc_rtx
)
3319 cc_status
.flags
= 0;
3320 cc_status
.value1
= dest
;
3321 cc_status
.value2
= src
;
3326 if (cc_status
.value2
!= 0
3327 && ADDRESS_REG_P (cc_status
.value2
)
3328 && GET_MODE (cc_status
.value2
) == QImode
)
3330 if (cc_status
.value2
!= 0)
3331 switch (GET_CODE (cc_status
.value2
))
3333 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
3334 case ROTATE
: case ROTATERT
:
3335 /* These instructions always clear the overflow bit, and set
3336 the carry to the bit shifted out. */
3337 /* ??? We don't currently have a way to signal carry not valid,
3338 nor do we check for it in the branch insns. */
3342 case PLUS
: case MINUS
: case MULT
:
3343 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
3344 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3345 cc_status
.flags
|= CC_NO_OVERFLOW
;
3348 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3349 ends with a move insn moving r2 in r2's mode.
3350 Thus, the cc's are set for r2.
3351 This can set N bit spuriously. */
3352 cc_status
.flags
|= CC_NOT_NEGATIVE
;
3357 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3359 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3360 cc_status
.value2
= 0;
3361 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
3362 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
3363 cc_status
.flags
= CC_IN_68881
;
3367 output_move_const_double (rtx
*operands
)
3369 int code
= standard_68881_constant_p (operands
[1]);
3373 static char buf
[40];
3375 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3378 return "fmove%.d %1,%0";
3382 output_move_const_single (rtx
*operands
)
3384 int code
= standard_68881_constant_p (operands
[1]);
3388 static char buf
[40];
3390 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3393 return "fmove%.s %f1,%0";
3396 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3397 from the "fmovecr" instruction.
3398 The value, anded with 0xff, gives the code to use in fmovecr
3399 to get the desired constant. */
3401 /* This code has been fixed for cross-compilation. */
3403 static int inited_68881_table
= 0;
3405 static const char *const strings_68881
[7] = {
3415 static const int codes_68881
[7] = {
3425 REAL_VALUE_TYPE values_68881
[7];
3427 /* Set up values_68881 array by converting the decimal values
3428 strings_68881 to binary. */
3431 init_68881_table (void)
3435 enum machine_mode mode
;
3438 for (i
= 0; i
< 7; i
++)
3442 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3443 values_68881
[i
] = r
;
3445 inited_68881_table
= 1;
3449 standard_68881_constant_p (rtx x
)
3454 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3455 used at all on those chips. */
3459 if (! inited_68881_table
)
3460 init_68881_table ();
3462 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3464 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3466 for (i
= 0; i
< 6; i
++)
3468 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3469 return (codes_68881
[i
]);
3472 if (GET_MODE (x
) == SFmode
)
3475 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3476 return (codes_68881
[6]);
3478 /* larger powers of ten in the constants ram are not used
3479 because they are not equal to a `double' C constant. */
3483 /* If X is a floating-point constant, return the logarithm of X base 2,
3484 or 0 if X is not a power of 2. */
3487 floating_exact_log2 (rtx x
)
3489 REAL_VALUE_TYPE r
, r1
;
3492 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3494 if (REAL_VALUES_LESS (r
, dconst1
))
3497 exp
= real_exponent (&r
);
3498 real_2expN (&r1
, exp
);
3499 if (REAL_VALUES_EQUAL (r1
, r
))
3505 /* A C compound statement to output to stdio stream STREAM the
3506 assembler syntax for an instruction operand X. X is an RTL
3509 CODE is a value that can be used to specify one of several ways
3510 of printing the operand. It is used when identical operands
3511 must be printed differently depending on the context. CODE
3512 comes from the `%' specification that was used to request
3513 printing of the operand. If the specification was just `%DIGIT'
3514 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3515 is the ASCII code for LTR.
3517 If X is a register, this macro should print the register's name.
3518 The names can be found in an array `reg_names' whose type is
3519 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3521 When the machine description has a specification `%PUNCT' (a `%'
3522 followed by a punctuation character), this macro is called with
3523 a null pointer for X and the punctuation character for CODE.
3525 The m68k specific codes are:
3527 '.' for dot needed in Motorola-style opcode names.
3528 '-' for an operand pushing on the stack:
3529 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3530 '+' for an operand pushing on the stack:
3531 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3532 '@' for a reference to the top word on the stack:
3533 sp@, (sp) or (%sp) depending on the style of syntax.
3534 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3535 but & in SGS syntax).
3536 '!' for the cc register (used in an `and to cc' insn).
3537 '$' for the letter `s' in an op code, but only on the 68040.
3538 '&' for the letter `d' in an op code, but only on the 68040.
3539 '/' for register prefix needed by longlong.h.
3540 '?' for m68k_library_id_string
3542 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3543 'd' to force memory addressing to be absolute, not relative.
3544 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3545 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3546 or print pair of registers as rx:ry.
3547 'p' print an address with @PLTPC attached, but only if the operand
3548 is not locally-bound. */
3551 print_operand (FILE *file
, rtx op
, int letter
)
3556 fprintf (file
, ".");
3558 else if (letter
== '#')
3559 asm_fprintf (file
, "%I");
3560 else if (letter
== '-')
3561 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3562 else if (letter
== '+')
3563 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3564 else if (letter
== '@')
3565 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3566 else if (letter
== '!')
3567 asm_fprintf (file
, "%Rfpcr");
3568 else if (letter
== '$')
3571 fprintf (file
, "s");
3573 else if (letter
== '&')
3576 fprintf (file
, "d");
3578 else if (letter
== '/')
3579 asm_fprintf (file
, "%R");
3580 else if (letter
== '?')
3581 asm_fprintf (file
, m68k_library_id_string
);
3582 else if (letter
== 'p')
3584 output_addr_const (file
, op
);
3585 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3586 fprintf (file
, "@PLTPC");
3588 else if (GET_CODE (op
) == REG
)
3591 /* Print out the second register name of a register pair.
3592 I.e., R (6) => 7. */
3593 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3595 fputs (M68K_REGNAME(REGNO (op
)), file
);
3597 else if (GET_CODE (op
) == MEM
)
3599 output_address (XEXP (op
, 0));
3600 if (letter
== 'd' && ! TARGET_68020
3601 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3602 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3603 && INTVAL (XEXP (op
, 0)) < 0x8000
3604 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3605 fprintf (file
, MOTOROLA
? ".l" : ":l");
3607 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3610 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3611 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3613 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3616 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3617 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3619 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3622 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3623 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3627 /* Use `print_operand_address' instead of `output_addr_const'
3628 to ensure that we print relevant PIC stuff. */
3629 asm_fprintf (file
, "%I");
3631 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3632 print_operand_address (file
, op
);
3634 output_addr_const (file
, op
);
3639 /* A C compound statement to output to stdio stream STREAM the
3640 assembler syntax for an instruction operand that is a memory
3641 reference whose address is ADDR. ADDR is an RTL expression.
3643 Note that this contains a kludge that knows that the only reason
3644 we have an address (plus (label_ref...) (reg...)) when not generating
3645 PIC code is in the insn before a tablejump, and we know that m68k.md
3646 generates a label LInnn: on such an insn.
3648 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3649 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3651 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3652 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3653 we want. This difference can be accommodated by using an assembler
3654 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3655 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3656 macro. See m68k/sgs.h for an example; for versions without the bug.
3657 Some assemblers refuse all the above solutions. The workaround is to
3658 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3661 They also do not like things like "pea 1.w", so we simple leave off
3662 the .w on small constants.
3664 This routine is responsible for distinguishing between -fpic and -fPIC
3665 style relocations in an address. When generating -fpic code the
3666 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3667 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3670 print_operand_address (FILE *file
, rtx addr
)
3672 struct m68k_address address
;
3674 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
3677 if (address
.code
== PRE_DEC
)
3678 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3679 M68K_REGNAME (REGNO (address
.base
)));
3680 else if (address
.code
== POST_INC
)
3681 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3682 M68K_REGNAME (REGNO (address
.base
)));
3683 else if (!address
.base
&& !address
.index
)
3685 /* A constant address. */
3686 gcc_assert (address
.offset
== addr
);
3687 if (GET_CODE (addr
) == CONST_INT
)
3689 /* (xxx).w or (xxx).l. */
3690 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
3691 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3693 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3695 else if (TARGET_PCREL
)
3697 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3699 output_addr_const (file
, addr
);
3700 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3704 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3705 name ends in `.<letter>', as the last 2 characters can be
3706 mistaken as a size suffix. Put the name in parentheses. */
3707 if (GET_CODE (addr
) == SYMBOL_REF
3708 && strlen (XSTR (addr
, 0)) > 2
3709 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3712 output_addr_const (file
, addr
);
3716 output_addr_const (file
, addr
);
3723 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3724 label being acceesed, otherwise it is -1. */
3725 labelno
= (address
.offset
3727 && GET_CODE (address
.offset
) == LABEL_REF
3728 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
3732 /* Print the "offset(base" component. */
3734 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,", labelno
, labelno
);
3739 output_addr_const (file
, address
.offset
);
3740 if (flag_pic
&& address
.base
== pic_offset_table_rtx
)
3742 fprintf (file
, "@GOT");
3743 if (flag_pic
== 1 && TARGET_68020
)
3744 fprintf (file
, ".w");
3749 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3751 /* Print the ",index" component, if any. */
3756 fprintf (file
, "%s.%c",
3757 M68K_REGNAME (REGNO (address
.index
)),
3758 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3759 if (address
.scale
!= 1)
3760 fprintf (file
, "*%d", address
.scale
);
3764 else /* !MOTOROLA */
3766 if (!address
.offset
&& !address
.index
)
3767 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
3770 /* Print the "base@(offset" component. */
3772 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b", labelno
, labelno
);
3776 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3777 fprintf (file
, "@(");
3780 output_addr_const (file
, address
.offset
);
3781 if (address
.base
== pic_offset_table_rtx
&& TARGET_68020
)
3785 fprintf (file
, ":w"); break;
3787 fprintf (file
, ":l"); break;
3793 /* Print the ",index" component, if any. */
3796 fprintf (file
, ",%s:%c",
3797 M68K_REGNAME (REGNO (address
.index
)),
3798 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3799 if (address
.scale
!= 1)
3800 fprintf (file
, ":%d", address
.scale
);
3808 /* Check for cases where a clr insns can be omitted from code using
3809 strict_low_part sets. For example, the second clrl here is not needed:
3810 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3812 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3813 insn we are checking for redundancy. TARGET is the register set by the
3817 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3822 p
= prev_nonnote_insn (first_insn
);
3826 /* If it isn't an insn, then give up. */
3827 if (GET_CODE (p
) != INSN
)
3830 if (reg_set_p (target
, p
))
3832 rtx set
= single_set (p
);
3835 /* If it isn't an easy to recognize insn, then give up. */
3839 dest
= SET_DEST (set
);
3841 /* If this sets the entire target register to zero, then our
3842 first_insn is redundant. */
3843 if (rtx_equal_p (dest
, target
)
3844 && SET_SRC (set
) == const0_rtx
)
3846 else if (GET_CODE (dest
) == STRICT_LOW_PART
3847 && GET_CODE (XEXP (dest
, 0)) == REG
3848 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3849 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3850 <= GET_MODE_SIZE (mode
)))
3851 /* This is a strict low part set which modifies less than
3852 we are using, so it is safe. */
3858 p
= prev_nonnote_insn (p
);
3864 /* Operand predicates for implementing asymmetric pc-relative addressing
3865 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3866 when used as a source operand, but not as a destination operand.
3868 We model this by restricting the meaning of the basic predicates
3869 (general_operand, memory_operand, etc) to forbid the use of this
3870 addressing mode, and then define the following predicates that permit
3871 this addressing mode. These predicates can then be used for the
3872 source operands of the appropriate instructions.
3874 n.b. While it is theoretically possible to change all machine patterns
3875 to use this addressing more where permitted by the architecture,
3876 it has only been implemented for "common" cases: SImode, HImode, and
3877 QImode operands, and only for the principle operations that would
3878 require this addressing mode: data movement and simple integer operations.
3880 In parallel with these new predicates, two new constraint letters
3881 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3882 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3883 In the pcrel case 's' is only valid in combination with 'a' registers.
3884 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3885 of how these constraints are used.
3887 The use of these predicates is strictly optional, though patterns that
3888 don't will cause an extra reload register to be allocated where one
3891 lea (abc:w,%pc),%a0 ; need to reload address
3892 moveq &1,%d1 ; since write to pc-relative space
3893 movel %d1,%a0@ ; is not allowed
3895 lea (abc:w,%pc),%a1 ; no need to reload address here
3896 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3898 For more info, consult tiemann@cygnus.com.
3901 All of the ugliness with predicates and constraints is due to the
3902 simple fact that the m68k does not allow a pc-relative addressing
3903 mode as a destination. gcc does not distinguish between source and
3904 destination addresses. Hence, if we claim that pc-relative address
3905 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3906 end up with invalid code. To get around this problem, we left
3907 pc-relative modes as invalid addresses, and then added special
3908 predicates and constraints to accept them.
3910 A cleaner way to handle this is to modify gcc to distinguish
3911 between source and destination addresses. We can then say that
3912 pc-relative is a valid source address but not a valid destination
3913 address, and hopefully avoid a lot of the predicate and constraint
3914 hackery. Unfortunately, this would be a pretty big change. It would
3915 be a useful change for a number of ports, but there aren't any current
3916 plans to undertake this.
3918 ***************************************************************************/
3922 output_andsi3 (rtx
*operands
)
3925 if (GET_CODE (operands
[2]) == CONST_INT
3926 && (INTVAL (operands
[2]) | 0xffff) == -1
3927 && (DATA_REG_P (operands
[0])
3928 || offsettable_memref_p (operands
[0]))
3929 && !TARGET_COLDFIRE
)
3931 if (GET_CODE (operands
[0]) != REG
)
3932 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3933 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3934 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3936 if (operands
[2] == const0_rtx
)
3938 return "and%.w %2,%0";
3940 if (GET_CODE (operands
[2]) == CONST_INT
3941 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3942 && (DATA_REG_P (operands
[0])
3943 || offsettable_memref_p (operands
[0])))
3945 if (DATA_REG_P (operands
[0]))
3946 operands
[1] = GEN_INT (logval
);
3949 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3950 operands
[1] = GEN_INT (logval
% 8);
3952 /* This does not set condition codes in a standard way. */
3954 return "bclr %1,%0";
3956 return "and%.l %2,%0";
3960 output_iorsi3 (rtx
*operands
)
3962 register int logval
;
3963 if (GET_CODE (operands
[2]) == CONST_INT
3964 && INTVAL (operands
[2]) >> 16 == 0
3965 && (DATA_REG_P (operands
[0])
3966 || offsettable_memref_p (operands
[0]))
3967 && !TARGET_COLDFIRE
)
3969 if (GET_CODE (operands
[0]) != REG
)
3970 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3971 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3973 if (INTVAL (operands
[2]) == 0xffff)
3974 return "mov%.w %2,%0";
3975 return "or%.w %2,%0";
3977 if (GET_CODE (operands
[2]) == CONST_INT
3978 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3979 && (DATA_REG_P (operands
[0])
3980 || offsettable_memref_p (operands
[0])))
3982 if (DATA_REG_P (operands
[0]))
3983 operands
[1] = GEN_INT (logval
);
3986 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3987 operands
[1] = GEN_INT (logval
% 8);
3990 return "bset %1,%0";
3992 return "or%.l %2,%0";
3996 output_xorsi3 (rtx
*operands
)
3998 register int logval
;
3999 if (GET_CODE (operands
[2]) == CONST_INT
4000 && INTVAL (operands
[2]) >> 16 == 0
4001 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4002 && !TARGET_COLDFIRE
)
4004 if (! DATA_REG_P (operands
[0]))
4005 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4006 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4008 if (INTVAL (operands
[2]) == 0xffff)
4010 return "eor%.w %2,%0";
4012 if (GET_CODE (operands
[2]) == CONST_INT
4013 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4014 && (DATA_REG_P (operands
[0])
4015 || offsettable_memref_p (operands
[0])))
4017 if (DATA_REG_P (operands
[0]))
4018 operands
[1] = GEN_INT (logval
);
4021 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4022 operands
[1] = GEN_INT (logval
% 8);
4025 return "bchg %1,%0";
4027 return "eor%.l %2,%0";
4030 /* Return the instruction that should be used for a call to address X,
4031 which is known to be in operand 0. */
4036 if (symbolic_operand (x
, VOIDmode
))
4037 return m68k_symbolic_call
;
4042 /* Likewise sibling calls. */
4045 output_sibcall (rtx x
)
4047 if (symbolic_operand (x
, VOIDmode
))
4048 return m68k_symbolic_jump
;
4053 #ifdef M68K_TARGET_COFF
4055 /* Output assembly to switch to section NAME with attribute FLAGS. */
4058 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
4059 tree decl ATTRIBUTE_UNUSED
)
4063 if (flags
& SECTION_WRITE
)
4068 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
4071 #endif /* M68K_TARGET_COFF */
4074 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
4075 HOST_WIDE_INT delta
,
4076 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
4082 if (delta
> 0 && delta
<= 8)
4083 asm_fprintf (file
, (MOTOROLA
4084 ? "\taddq.l %I%d,4(%Rsp)\n"
4085 : "\taddql %I%d,%Rsp@(4)\n"),
4087 else if (delta
< 0 && delta
>= -8)
4088 asm_fprintf (file
, (MOTOROLA
4089 ? "\tsubq.l %I%d,4(%Rsp)\n"
4090 : "\tsubql %I%d,%Rsp@(4)\n"),
4092 else if (TARGET_COLDFIRE
)
4094 /* ColdFire can't add/sub a constant to memory unless it is in
4095 the range of addq/subq. So load the value into %d0 and
4096 then add it to 4(%sp). */
4097 if (delta
>= -128 && delta
<= 127)
4098 asm_fprintf (file
, (MOTOROLA
4099 ? "\tmoveq.l %I%wd,%Rd0\n"
4100 : "\tmoveql %I%wd,%Rd0\n"),
4103 asm_fprintf (file
, (MOTOROLA
4104 ? "\tmove.l %I%wd,%Rd0\n"
4105 : "\tmovel %I%wd,%Rd0\n"),
4107 asm_fprintf (file
, (MOTOROLA
4108 ? "\tadd.l %Rd0,4(%Rsp)\n"
4109 : "\taddl %Rd0,%Rsp@(4)\n"));
4112 asm_fprintf (file
, (MOTOROLA
4113 ? "\tadd.l %I%wd,4(%Rsp)\n"
4114 : "\taddl %I%wd,%Rsp@(4)\n"),
4117 xops
[0] = DECL_RTL (function
);
4119 gcc_assert (MEM_P (xops
[0])
4120 && symbolic_operand (XEXP (xops
[0], 0), VOIDmode
));
4121 xops
[0] = XEXP (xops
[0], 0);
4123 fmt
= m68k_symbolic_jump
;
4124 if (m68k_symbolic_jump
== NULL
)
4125 fmt
= "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)";
4127 output_asm_insn (fmt
, xops
);
4130 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4133 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4134 int incoming ATTRIBUTE_UNUSED
)
4136 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
4139 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4141 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
4142 unsigned int new_reg
)
4145 /* Interrupt functions can only use registers that have already been
4146 saved by the prologue, even if they would normally be
4149 if (m68k_interrupt_function_p (current_function_decl
)
4150 && !regs_ever_live
[new_reg
])
4156 /* Value is true if hard register REGNO can hold a value of machine-mode
4157 MODE. On the 68000, we let the cpu registers can hold any mode, but
4158 restrict the 68881 registers to floating-point modes. */
4161 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
4163 if (DATA_REGNO_P (regno
))
4165 /* Data Registers, can hold aggregate if fits in. */
4166 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
4169 else if (ADDRESS_REGNO_P (regno
))
4171 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
4174 else if (FP_REGNO_P (regno
))
4176 /* FPU registers, hold float or complex float of long double or
4178 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4179 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4180 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
4186 /* Implement SECONDARY_RELOAD_CLASS. */
4189 m68k_secondary_reload_class (enum reg_class rclass
,
4190 enum machine_mode mode
, rtx x
)
4194 regno
= true_regnum (x
);
4196 /* If one operand of a movqi is an address register, the other
4197 operand must be a general register or constant. Other types
4198 of operand must be reloaded through a data register. */
4199 if (GET_MODE_SIZE (mode
) == 1
4200 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
4201 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
4204 /* PC-relative addresses must be loaded into an address register first. */
4206 && !reg_class_subset_p (rclass
, ADDR_REGS
)
4207 && symbolic_operand (x
, VOIDmode
))
4213 /* Implement PREFERRED_RELOAD_CLASS. */
4216 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
4218 enum reg_class secondary_class
;
4220 /* If RCLASS might need a secondary reload, try restricting it to
4221 a class that doesn't. */
4222 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
4223 if (secondary_class
!= NO_REGS
4224 && reg_class_subset_p (secondary_class
, rclass
))
4225 return secondary_class
;
4227 /* Prefer to use moveq for in-range constants. */
4228 if (GET_CODE (x
) == CONST_INT
4229 && reg_class_subset_p (DATA_REGS
, rclass
)
4230 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
4233 /* ??? Do we really need this now? */
4234 if (GET_CODE (x
) == CONST_DOUBLE
4235 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
4237 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
4246 /* Return floating point values in a 68881 register. This makes 68881 code
4247 a little bit faster. It also makes -msoft-float code incompatible with
4248 hard-float code, so people have to be careful not to mix the two.
4249 For ColdFire it was decided the ABI incompatibility is undesirable.
4250 If there is need for a hard-float ABI it is probably worth doing it
4251 properly and also passing function arguments in FP registers. */
4253 m68k_libcall_value (enum machine_mode mode
)
4260 return gen_rtx_REG (mode
, 16);
4265 return gen_rtx_REG (mode
, 0);
4269 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
4271 enum machine_mode mode
;
4273 mode
= TYPE_MODE (valtype
);
4279 return gen_rtx_REG (mode
, 16);
4285 /* If the function returns a pointer, push that into %a0. */
4286 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
4287 /* For compatibility with the large body of existing code which
4288 does not always properly declare external functions returning
4289 pointer types, the m68k/SVR4 convention is to copy the value
4290 returned for pointer functions from a0 to d0 in the function
4291 epilogue, so that callers that have neglected to properly
4292 declare the callee can still find the correct return value in
4294 return gen_rtx_PARALLEL
4297 gen_rtx_EXPR_LIST (VOIDmode
,
4298 gen_rtx_REG (mode
, A0_REG
),
4300 gen_rtx_EXPR_LIST (VOIDmode
,
4301 gen_rtx_REG (mode
, D0_REG
),
4303 else if (POINTER_TYPE_P (valtype
))
4304 return gen_rtx_REG (mode
, A0_REG
);
4306 return gen_rtx_REG (mode
, D0_REG
);