| blob | a2c1aef3975b9223b94639cbfe53710619dfaea0 |
1 ;; Machine description for Tilera TILE-Gx chip for GCC.
2 ;; Copyright (C) 2011-2015 Free Software Foundation, Inc.
3 ;; Contributed by Walter Lee (walt@tilera.com)
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_constants [
22 ;;
23 ;; The following represent intrinsic insns, organized by latency.
24 ;;
26 ;; single cycle
27 (UNSPEC_INSN_ADDR_SHL16INSLI 1)
28 (UNSPEC_INSN_BFEXTS 2)
29 (UNSPEC_INSN_BFEXTU 3)
30 (UNSPEC_INSN_BFINS 4)
31 (UNSPEC_INSN_CRC32_32 5)
32 (UNSPEC_INSN_CRC32_8 6)
33 (UNSPEC_INSN_DBLALIGN 7)
34 (UNSPEC_INSN_DBLALIGN2 8)
35 (UNSPEC_INSN_DBLALIGN4 9)
36 (UNSPEC_INSN_DBLALIGN6 10)
37 (UNSPEC_INSN_DRAIN 11)
38 (UNSPEC_INSN_DTLBPR 12)
39 (UNSPEC_INSN_FINV 13)
40 (UNSPEC_INSN_FLUSH 14)
41 (UNSPEC_INSN_FLUSHWB 15)
42 (UNSPEC_INSN_FNOP 16)
43 (UNSPEC_INSN_ICOH 17)
44 (UNSPEC_INSN_ILL 18)
45 (UNSPEC_INSN_INFO 19)
46 (UNSPEC_INSN_INFOL 20)
47 (UNSPEC_INSN_INV 21)
48 (UNSPEC_INSN_LNK 22)
49 (UNSPEC_INSN_MFSPR 23)
50 (UNSPEC_INSN_MM 24)
51 (UNSPEC_INSN_MTSPR 25)
52 (UNSPEC_INSN_NAP 26)
53 (UNSPEC_INSN_PREFETCH_L1_FAULT 27)
54 (UNSPEC_INSN_PREFETCH_L2_FAULT 28)
55 (UNSPEC_INSN_PREFETCH_L3_FAULT 29)
56 (UNSPEC_INSN_REVBITS 30)
57 (UNSPEC_INSN_SHUFFLEBYTES 31)
58 (UNSPEC_INSN_TBLIDXB0 32)
59 (UNSPEC_INSN_TBLIDXB1 33)
60 (UNSPEC_INSN_TBLIDXB2 34)
61 (UNSPEC_INSN_TBLIDXB3 35)
62 (UNSPEC_INSN_V1AVGU 36)
63 (UNSPEC_INSN_V2AVGS 37)
64 (UNSPEC_INSN_WH64 38)
66 ;; 2 cycles
67 (UNSPEC_INSN_CMUL 100)
68 (UNSPEC_INSN_CMULA 101)
69 (UNSPEC_INSN_CMULAF 102)
70 (UNSPEC_INSN_CMULFR 103)
71 (UNSPEC_INSN_CMULHR 104)
72 (UNSPEC_INSN_CMULF 105)
73 (UNSPEC_INSN_CMULH 106)
74 (UNSPEC_INSN_EXCH 107)
75 (UNSPEC_INSN_FDOUBLE_ADDSUB 108)
76 (UNSPEC_INSN_FDOUBLE_ADD_FLAGS 109)
77 (UNSPEC_INSN_FDOUBLE_MUL_FLAGS 110)
78 (UNSPEC_INSN_FDOUBLE_PACK1 111)
79 (UNSPEC_INSN_FDOUBLE_PACK2 112)
80 (UNSPEC_INSN_FDOUBLE_SUB_FLAGS 113)
81 (UNSPEC_INSN_FDOUBLE_UNPACK_MAX 114)
82 (UNSPEC_INSN_FDOUBLE_UNPACK_MIN 115)
83 (UNSPEC_INSN_FETCHADDGEZ 116)
84 (UNSPEC_INSN_FSINGLE_ADD1 117)
85 (UNSPEC_INSN_FSINGLE_ADDSUB2 118)
86 (UNSPEC_INSN_FSINGLE_MUL1 119)
87 (UNSPEC_INSN_FSINGLE_MUL2 120)
88 (UNSPEC_INSN_FSINGLE_PACK1 121)
89 (UNSPEC_INSN_FSINGLE_PACK2 122)
90 (UNSPEC_INSN_FSINGLE_SUB1 123)
91 (UNSPEC_INSN_MULAX 124)
92 (UNSPEC_INSN_MULA_HS_HS 125)
93 (UNSPEC_INSN_MULA_HS_HU 126)
94 (UNSPEC_INSN_MULA_HS_LS 127)
95 (UNSPEC_INSN_MULA_HS_LU 128)
96 (UNSPEC_INSN_MULA_HU_HU 129)
97 (UNSPEC_INSN_MULA_HU_LS 130)
98 (UNSPEC_INSN_MULA_HU_LU 131)
99 (UNSPEC_INSN_MULA_LS_LS 132)
100 (UNSPEC_INSN_MULA_LS_LU 133)
101 (UNSPEC_INSN_MULA_LU_LU 134)
102 (UNSPEC_INSN_MUL_HS_HS 135)
103 (UNSPEC_INSN_MUL_HS_HU 136)
104 (UNSPEC_INSN_MUL_HS_LS 137)
105 (UNSPEC_INSN_MUL_HS_LU 138)
106 (UNSPEC_INSN_MUL_HU_HU 139)
107 (UNSPEC_INSN_MUL_HU_LS 140)
108 (UNSPEC_INSN_MUL_HU_LU 141)
109 (UNSPEC_INSN_MUL_LS_LS 142)
110 (UNSPEC_INSN_MUL_LS_LU 143)
111 (UNSPEC_INSN_MUL_LU_LU 144)
112 (UNSPEC_INSN_V1ADIFFU 145)
113 (UNSPEC_INSN_V1DDOTPU 146)
114 (UNSPEC_INSN_V1DDOTPUA 147)
115 (UNSPEC_INSN_V1DDOTPUS 148)
116 (UNSPEC_INSN_V1DDOTPUSA 149)
117 (UNSPEC_INSN_V1DOTP 150)
118 (UNSPEC_INSN_V1DOTPA 151)
119 (UNSPEC_INSN_V1DOTPU 152)
120 (UNSPEC_INSN_V1DOTPUA 153)
121 (UNSPEC_INSN_V1DOTPUS 154)
122 (UNSPEC_INSN_V1DOTPUSA 155)
123 (UNSPEC_INSN_V1SADAU 156)
124 (UNSPEC_INSN_V1SADU 157)
125 (UNSPEC_INSN_V2ADIFFS 158)
126 (UNSPEC_INSN_V2DOTP 159)
127 (UNSPEC_INSN_V2DOTPA 160)
128 (UNSPEC_INSN_V2MULFSC 161)
129 (UNSPEC_INSN_V2SADAS 162)
130 (UNSPEC_INSN_V2SADAU 163)
131 (UNSPEC_INSN_V2SADS 164)
132 (UNSPEC_INSN_V2SADU 165)
134 ;; 11 cycles
135 (UNSPEC_INSN_CMPEXCH 200)
137 ;;
138 ;; The following are special insns.
139 ;;
141 ;; Blockage
142 (UNSPEC_BLOCKAGE 201)
144 ;; Lnk and its label
145 (UNSPEC_LNK_AND_LABEL 202)
147 ;; Memory fence
148 (UNSPEC_MF 203)
150 ;; Insns generating difference of two labels
151 (UNSPEC_MOV_PCREL_STEP3 204)
152 (UNSPEC_MOV_LARGE_PCREL_STEP4 205)
154 ;; Latency specifying loads.
155 (UNSPEC_LATENCY_L2 206)
156 (UNSPEC_LATENCY_MISS 207)
158 ;; A pseudo-op that prevents network operations from being ordered.
159 (UNSPEC_NETWORK_BARRIER 208)
161 ;; Operations that access network registers.
162 (UNSPEC_NETWORK_RECEIVE 209)
163 (UNSPEC_NETWORK_SEND 210)
165 ;; Stack protector operations
166 (UNSPEC_SP_SET 211)
167 (UNSPEC_SP_TEST 212)
169 ;; This is used to move a value to a SPR.
170 (UNSPEC_SPR_MOVE 213)
172 ;; A call to __tls_get_addr
173 (UNSPEC_TLS_GD_CALL 214)
175 ;; An opaque TLS "add" operation for TLS general dynamic model
176 ;; access.
177 (UNSPEC_TLS_GD_ADD 215)
179 ;; An opaque TLS "load" operation for TLS initial exec model access.
180 (UNSPEC_TLS_IE_LOAD 216)
182 ;; An opaque TLS "add" operation for TLS access.
183 (UNSPEC_TLS_ADD 217)
185 ;; Atomics
186 (UNSPEC_ATOMIC 218)
187 (UNSPEC_CMPXCHG 219)
188 (UNSPEC_XCHG 220)
190 ;;
191 ;; The following are operands.
192 ;;
193 (UNSPEC_HW0 300)
194 (UNSPEC_HW1 301)
195 (UNSPEC_HW2 302)
196 (UNSPEC_HW3 303)
197 (UNSPEC_HW0_LAST 304)
198 (UNSPEC_HW1_LAST 305)
199 (UNSPEC_HW2_LAST 306)
201 (UNSPEC_HW0_PCREL 307)
202 (UNSPEC_HW1_PCREL 308)
203 (UNSPEC_HW1_LAST_PCREL 309)
204 (UNSPEC_HW2_LAST_PCREL 310)
206 (UNSPEC_HW0_GOT 311)
207 (UNSPEC_HW0_LAST_GOT 312)
208 (UNSPEC_HW1_LAST_GOT 313)
210 (UNSPEC_HW0_TLS_GD 314)
211 (UNSPEC_HW1_LAST_TLS_GD 315)
213 (UNSPEC_HW0_TLS_IE 316)
214 (UNSPEC_HW1_LAST_TLS_IE 317)
216 (UNSPEC_HW0_TLS_LE 318)
217 (UNSPEC_HW1_LAST_TLS_LE 319)
219 (UNSPEC_HW0_PLT_PCREL 320)
220 (UNSPEC_HW1_PLT_PCREL 321)
222 (UNSPEC_HW1_LAST_PLT_PCREL 322)
223 (UNSPEC_HW2_LAST_PLT_PCREL 323)
225 ;; This is used to wrap around the addresses of non-temporal load/store
226 ;; intrinsics.
227 (UNSPEC_NON_TEMPORAL 324)
228 ])
230 ;; Mark the last instruction of various latencies, used to
231 ;; determine the rtx costs of unspec insns.
232 (define_constants [
233 (TILEGX_LAST_LATENCY_1_INSN 99)
234 (TILEGX_LAST_LATENCY_2_INSN 199)
235 (TILEGX_LAST_LATENCY_INSN 299)
236 ])
238 (define_constants [
239 (TILEGX_NETREG_IDN0 0)
240 (TILEGX_NETREG_IDN1 1)
241 (TILEGX_NETREG_UDN0 2)
242 (TILEGX_NETREG_UDN1 3)
243 (TILEGX_NETREG_UDN2 4)
244 (TILEGX_NETREG_UDN3 5)
245 ])
247 (define_constants [
248 (TILEGX_CMPEXCH_REG 66)
249 (TILEGX_NETORDER_REG 67)
250 ])
253 ;; Operand and operator predicates and constraints
255 (include "predicates.md")
256 (include "constraints.md")
257 (include "tilegx-generic.md")
259 ;; Define an insn type attribute. This defines what pipes things can go in.
260 (define_attr "type"
261 "X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_remote,X1_miss,X01,Y0,Y0_2cycle,Y1,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing"
262 (const_string "Y01"))
264 (define_attr "length" ""
265 (cond [(eq_attr "type" "X1_branch")
266 (if_then_else
267 (and (le (minus (match_dup 0) (pc)) (const_int 524280))
268 (le (minus (pc) (match_dup 0)) (const_int 524288)))
269 (const_int 8)
270 (const_int 16))
271 ]
272 (const_int 8)))
275 ;; Define some iterators.
276 (define_mode_iterator IVMODE [SI DI V8QI V4HI V2SI])
277 (define_mode_iterator IVNMODE [SI V8QI V4HI V2SI])
278 (define_mode_iterator I48MODE [SI DI])
279 (define_mode_iterator I48MODE2 [SI DI])
280 (define_mode_iterator I124MODE [QI HI SI])
281 (define_mode_iterator FI48MODE [SF DF SI DI])
282 (define_mode_iterator VEC48MODE [V8QI V4HI])
283 (define_mode_iterator VEC248MODE [V8QI V4HI V2SI])
285 (define_mode_attr n [(QI "1") (HI "2") (SI "4") (DI "")
286 (V8QI "1") (V4HI "2") (V2SI "4")])
287 (define_mode_attr x [(SI "x") (DI "")])
288 (define_mode_attr bitsuffix [(SI "_32bit") (DI "")])
289 (define_mode_attr four_if_si [(SI "4") (DI "")])
290 (define_mode_attr four_s_if_si [(SI "4s") (DI "")])
291 (define_mode_attr nbits [(SI "5") (DI "6")])
292 (define_mode_attr shift_pipe [(SI "X01") (DI "*")])
294 ;; Code iterator for either extend.
295 (define_code_iterator any_extend [sign_extend zero_extend])
297 ;; Code iterator for all three shifts.
298 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
300 ;; Code iterator for all byte ops without immediate variants.
301 (define_code_iterator v1op [us_minus us_plus minus ne le leu mult])
303 ;; Code iterator for all 2-byte vector ops without immediate variants.
304 (define_code_iterator v2op [ss_minus ss_plus minus ne le leu])
306 ;; Code iterator for all 4-byte vector ops without immediate variants.
307 (define_code_iterator v4op [ss_minus ss_plus minus plus])
309 ;; Code iterator for all byte vector ops with immediate variants.
310 (define_code_iterator v1op_immed [plus umax umin eq lt ltu])
312 ;; Code iterator for all 2-byte vector ops with immediate variants.
313 (define_code_iterator v2op_immed [plus smax smin eq lt ltu])
315 ;; Code iterator for all 2-byte vector shifts without immediate variants.
316 (define_code_iterator v2shift [ss_ashift])
318 ;; Code iterator for all 4-byte vector shifts without immediate variants.
319 (define_code_iterator v4shift [ashift ashiftrt lshiftrt ss_ashift])
321 ;; <optab> expands to the name of the optab for a particular code.
322 (define_code_attr optab [(ashift "ashl")
323 (ashiftrt "ashr")
324 (lshiftrt "lshr")
325 (ss_ashift "ssashl")
326 (eq "seq")
327 (ne "sne")
328 (lt "slt")
329 (ltu "sltu")
330 (le "sle")
331 (leu "sleu")
332 (minus "sub")
333 (plus "add")
334 (mult "mul")
335 (smax "smax")
336 (smin "smin")
337 (ss_minus "sssub")
338 (ss_plus "ssadd")
339 (umax "umax")
340 (umin "umin")
341 (us_minus "ussub")
342 (us_plus "usadd")
343 ])
345 ;; <insn> expands to the name of the insn that implements a particular
346 ;; code.
347 (define_code_attr insn [(ashift "shl")
348 (ashiftrt "shrs")
349 (lshiftrt "shru")
350 (ss_ashift "shlsc")
351 (eq "cmpeq")
352 (ne "cmpne")
353 (lt "cmplts")
354 (ltu "cmpltu")
355 (le "cmples")
356 (leu "cmpleu")
357 (minus "sub")
358 (plus "add")
359 (mult "multu")
360 (smax "maxs")
361 (smin "mins")
362 (umax "maxu")
363 (umin "minu")
364 (ss_minus "subsc")
365 (ss_plus "addsc")
366 (us_minus "subuc")
367 (us_plus "adduc")
368 ])
370 ;; <pipe> expands to the pipeline resource that contains the
371 ;; particular code.
372 (define_code_attr pipe [(ashift "X01")
373 (ashiftrt "X01")
374 (lshiftrt "X01")
375 (ss_ashift "X01")
376 (eq "X01")
377 (ne "X01")
378 (lt "X01")
379 (ltu "X01")
380 (le "X01")
381 (leu "X01")
382 (minus "X01")
383 (plus "X01")
384 (mult "X0_2cycle")
385 (smax "X01")
386 (smin "X01")
387 (umax "X01")
388 (umin "X01")
389 (ss_minus "X01")
390 (ss_plus "X01")
391 (us_minus "X01")
392 (us_plus "X01")
393 ])
395 ;; <comm> indicates whether a particular code is commutative, using
396 ;; the "%" commutative opterator constraint.
397 (define_code_attr comm [(ashift "")
398 (ashiftrt "")
399 (lshiftrt "")
400 (ss_ashift "")
401 (eq "%")
402 (ne "%")
403 (lt "")
404 (ltu "")
405 (le "")
406 (leu "")
407 (minus "")
408 (plus "%")
409 (mult "%")
410 (smin "%")
411 (umin "%")
412 (smax "%")
413 (umax "%")
414 (ss_plus "%")
415 (us_plus "%")
416 (ss_minus "")
417 (us_minus "")
418 ])
420 ;; <s> is the load/store extension suffix.
421 (define_code_attr s [(zero_extend "u")
422 (sign_extend "s")])
424 ;; Code for packing two 2-byte vectors.
425 (define_code_iterator v2pack [truncate us_truncate])
427 ;; <pack_optab> expands to the part of the optab name describing how
428 ;; two vectors are packed.
429 (define_code_attr pack_optab [(truncate "trunc")
430 (us_truncate "usat")
431 (ss_truncate "ssat")])
433 ;; <pack_insn> expands to the insn that implements a particular vector
434 ;; packing code.
435 (define_code_attr pack_insn [(truncate "packl")
436 (us_truncate "packuc")
437 (ss_truncate "packsc")])
438 \f
439 ;;
440 ;; The basic data move insns.
441 ;;
443 (define_expand "movqi"
444 [(set (match_operand:QI 0 "nonimmediate_operand" "")
445 (match_operand:QI 1 "nonautoinc_operand" ""))]
446 ""
447 {
448 if (tilegx_expand_mov (QImode, operands))
449 DONE;
450 })
452 (define_insn "*movqi_insn"
453 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,U,m")
454 (match_operand:QI 1 "move_operand" "r,I,U,m,rO,rO"))]
455 "(register_operand (operands[0], QImode)
456 || reg_or_0_operand (operands[1], QImode))"
457 "@
458 move\t%0, %r1
459 movei\t%0, %1
460 ld1u\t%0, %1
461 ld1u_add\t%0, %I1, %i1
462 st1\t%0, %r1
463 st1_add\t%I0, %r1, %i0"
464 [(set_attr "type" "*,*,Y2_2cycle,X1_2cycle,Y2,X1")])
466 (define_expand "movhi"
467 [(set (match_operand:HI 0 "nonimmediate_operand" "")
468 (match_operand:HI 1 "nonautoinc_operand" ""))]
469 ""
470 {
471 if (tilegx_expand_mov (HImode, operands))
472 DONE;
473 })
475 (define_insn "*movhi_insn"
476 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,r,U,m")
477 (match_operand:HI 1 "move_operand" "r,I,JT,U,m,rO,rO"))]
478 "(register_operand (operands[0], HImode)
479 || reg_or_0_operand (operands[1], HImode))"
480 "@
481 move\t%0, %r1
482 movei\t%0, %1
483 moveli\t%0, %H1
484 ld2u\t%0, %1
485 ld2u_add\t%0, %I1, %i1
486 st2\t%0, %r1
487 st2_add\t%I0, %r1, %i0"
488 [(set_attr "type" "*,*,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
490 (define_expand "movsi"
491 [(set (match_operand:SI 0 "nonimmediate_operand" "")
492 (match_operand:SI 1 "nonautoinc_operand" ""))]
493 ""
494 {
495 if (tilegx_expand_mov (SImode, operands))
496 DONE;
497 })
499 (define_insn "*movsi_insn"
500 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,U,m")
501 (match_operand:SI 1 "move_operand" "r,I,JT,K,U,m,rO,rO"))]
502 "(register_operand (operands[0], SImode)
503 || reg_or_0_operand (operands[1], SImode))"
504 "@
505 move\t%0, %r1
506 movei\t%0, %1
507 moveli\t%0, %H1
508 shl16insli\t%0, zero, %h1
509 ld4s\t%0, %1
510 ld4s_add\t%0, %I1, %i1
511 st4\t%0, %r1
512 st4_add\t%I0, %r1, %i0"
513 [(set_attr "type" "*,*,X01,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
515 (define_expand "movdi"
516 [(set (match_operand:DI 0 "nonimmediate_operand" "")
517 (match_operand:DI 1 "nonautoinc_operand" ""))]
518 ""
519 {
520 if (tilegx_expand_mov (DImode, operands))
521 DONE;
522 })
524 (define_insn "*movdi_insn"
525 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,r,U,m")
526 (match_operand:DI 1 "move_operand" "r,I,JT,K,N,P,U,m,rO,rO"))]
527 "(register_operand (operands[0], DImode)
528 || reg_or_0_operand (operands[1], DImode))"
529 "@
530 move\t%0, %r1
531 movei\t%0, %1
532 moveli\t%0, %H1
533 shl16insli\t%0, zero, %h1
534 v1addi\t%0, zero, %j1
535 v2addi\t%0, zero, %h1
536 ld\t%0, %1
537 ld_add\t%0, %I1, %i1
538 st\t%0, %r1
539 st_add\t%I0, %r1, %i0"
540 [(set_attr "type" "*,*,X01,X01,X01,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
542 (define_expand "movmisalign<mode>"
543 [(set (match_operand:VEC248MODE 0 "nonautoincmem_nonimmediate_operand" "")
544 (match_operand:VEC248MODE 1 "nonautoincmem_general_operand" ""))]
545 ""
546 {
547 tilegx_expand_movmisalign (<MODE>mode, operands);
548 DONE;
549 })
551 (define_expand "movsf"
552 [(set (match_operand:SF 0 "nonimmediate_operand" "")
553 (match_operand:SF 1 "general_operand" ""))]
554 ""
555 {
556 /* Materialize immediates using clever SImode code, but don't
557 do this after reload starts, since gen_lowpart will choke
558 during reload if given an illegitimate address. */
559 if (immediate_operand (operands[1], SFmode)
560 && operands[1] != const0_rtx
561 && (register_operand (operands[0], SFmode)
562 || (!reload_in_progress && !reload_completed)))
563 {
564 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
565 gen_lowpart (SImode, operands[1])));
566 DONE;
567 }
568 })
570 (define_insn "*movsf"
571 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,U,m")
572 (match_operand:SF 1 "general_operand" "rO,U,m,rO,rO"))]
573 ""
574 "@
575 move\t%0, %r1
576 ld4s\t%0, %1
577 ld4s_add\t%0, %I1, %i1
578 st4\t%0, %r1
579 st4_add\t%I0, %r1, %i0"
580 [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
582 (define_expand "movdf"
583 [(set (match_operand:DF 0 "nonimmediate_operand" "")
584 (match_operand:DF 1 "general_operand" ""))]
585 ""
586 {
587 /* Materialize immediates using clever DImode code, but don't
588 do this after reload starts, since gen_lowpart will choke
589 during reload if given an illegitimate address. */
590 if (immediate_operand (operands[1], DFmode)
591 && operands[1] != const0_rtx
592 && (register_operand (operands[0], DFmode)
593 || (!reload_in_progress && !reload_completed)))
594 {
595 emit_insn (gen_movdi (gen_lowpart (DImode, operands[0]),
596 gen_lowpart (DImode, operands[1])));
597 DONE;
598 }
599 })
601 (define_insn "*movdf"
602 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,r,U,m")
603 (match_operand:DF 1 "general_operand" "rO,U,m,rO,rO"))]
604 ""
605 "@
606 move\t%0, %r1
607 ld\t%0, %1
608 ld_add\t%0, %I1, %i1
609 st\t%0, %r1
610 st_add\t%I0, %r1, %i0"
611 [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
613 (define_expand "mov<mode>"
614 [(set (match_operand:VEC248MODE 0 "nonimmediate_operand" "")
615 (match_operand:VEC248MODE 1 "general_operand" ""))]
616 ""
617 {
618 /* Materialize immediates using clever DImode code, but don't
619 do this after reload starts, since gen_lowpart will choke
620 during reload if given an illegitimate address. */
621 if (immediate_operand (operands[1], <MODE>mode)
622 && operands[1] != const0_rtx
623 && (register_operand (operands[0], <MODE>mode)
624 || (!reload_in_progress && !reload_completed)))
625 {
626 emit_insn (gen_movdi (gen_lowpart (DImode, operands[0]),
627 gen_lowpart (DImode, operands[1])));
628 DONE;
629 }
630 })
632 (define_insn "*mov<mode>"
633 [(set (match_operand:VEC248MODE 0 "nonimmediate_operand" "=r,r,r,U,m")
634 (match_operand:VEC248MODE 1 "general_operand" "rO,U,m,rO,rO"))]
635 ""
636 "@
637 move\t%0, %r1
638 ld\t%0, %1
639 ld_add\t%0, %I1, %i1
640 st\t%0, %r1
641 st_add\t%I0, %r1, %i0"
642 [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
644 (define_insn "movstrictqi"
645 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
646 (match_operand:QI 1 "reg_or_0_operand" "rO"))]
647 ""
648 "bfins\t%0, %r1, 0, 7"
649 [(set_attr "type" "X0")])
651 (define_insn "movstricthi"
652 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
653 (match_operand:HI 1 "reg_or_0_operand" "rO"))]
654 ""
655 "bfins\t%0, %r1, 0, 15"
656 [(set_attr "type" "X0")])
658 (define_insn "movstrictsi"
659 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+r"))
660 (match_operand:SI 1 "reg_or_0_operand" "rO"))]
661 ""
662 "bfins\t%0, %r1, 0, 31"
663 [(set_attr "type" "X0")])
665 \f
666 ;;
667 ;; Bit-field extracts/inserts
668 ;;
670 (define_expand "insv"
671 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
672 (match_operand:DI 1 "u6bit_cint_operand" "")
673 (match_operand:DI 2 "u6bit_cint_operand" ""))
674 (match_operand:DI 3 "reg_or_cint_operand" ""))]
675 ""
676 {
677 rtx first_rtx = operands[2];
678 HOST_WIDE_INT first = INTVAL (first_rtx);
679 HOST_WIDE_INT width = INTVAL (operands[1]);
680 rtx v = operands[3];
682 if (CONST_INT_P (v))
683 {
684 /* Which bits are we affecting? */
685 HOST_WIDE_INT mask = ((((HOST_WIDE_INT) 1) << width) - 1) << first;
687 /* Extract just the bits we need, sign extending them to make the
688 constant easier to materialize in a register. */
689 int shift = sizeof(HOST_WIDE_INT) * 8 - width;
690 HOST_WIDE_INT n = (INTVAL (v) << shift) >> shift;
692 if (n == 0)
693 {
694 /* We are setting every bit in the bitfield to zero. Try to use
695 andi instead, since that is more efficient. */
696 rtx mask_rtx = GEN_INT (~mask);
697 if (satisfies_constraint_I (mask_rtx))
698 {
699 emit_insn (gen_anddi3 (operands[0], operands[0], mask_rtx));
700 DONE;
701 }
703 operands[3] = const0_rtx;
704 }
705 else
706 {
707 if (n == -1)
708 {
709 /* We are setting every bit in the bitfield to one. Try to use
710 ori instead, since that is more efficient. */
711 rtx mask_rtx = GEN_INT (mask);
712 if (satisfies_constraint_I (mask_rtx))
713 {
714 emit_insn (gen_iordi3 (operands[0], operands[0], mask_rtx));
715 DONE;
716 }
717 }
719 if (!can_create_pseudo_p ())
720 FAIL;
722 operands[3] = force_reg (DImode, GEN_INT (n));
723 }
724 }
725 })
727 (define_insn "*insv_tblidxb0"
728 [(set (zero_extract:DI
729 (match_operand:DI 0 "register_operand" "+r")
730 (const_int 8)
731 (const_int 2))
732 (match_operand:DI 1 "register_operand" "rO"))]
733 ""
734 "tblidxb0\t%0, %r1"
735 [(set_attr "type" "Y0")])
737 (define_insn "*insv_tblidxb1"
738 [(set (zero_extract:DI
739 (match_operand:DI 0 "register_operand" "+r")
740 (const_int 8)
741 (const_int 2))
742 (zero_extract:DI
743 (const_int 8)
744 (const_int 8)
745 (match_operand:DI 1 "register_operand" "rO")))]
746 ""
747 "tblidxb1\t%0, %r1"
748 [(set_attr "type" "Y0")])
750 (define_insn "*insv_tblidxb2"
751 [(set (zero_extract:DI
752 (match_operand:DI 0 "register_operand" "+r")
753 (const_int 8)
754 (const_int 2))
755 (zero_extract:DI
756 (const_int 8)
757 (const_int 16)
758 (match_operand:DI 1 "register_operand" "rO")))]
759 ""
760 "tblidxb2\t%0, %r1"
761 [(set_attr "type" "Y0")])
763 (define_insn "*insv_tblidxb3"
764 [(set (zero_extract:DI
765 (match_operand:DI 0 "register_operand" "+r")
766 (const_int 8)
767 (const_int 2))
768 (zero_extract:DI
769 (const_int 8)
770 (const_int 24)
771 (match_operand:DI 1 "register_operand" "rO")))]
772 ""
773 "tblidxb3\t%0, %r1"
774 [(set_attr "type" "Y0")])
776 (define_insn "*insv_bfins"
777 [(set (zero_extract:DI
778 (match_operand:DI 0 "register_operand" "+r")
779 (match_operand:DI 1 "u6bit_cint_operand" "n")
780 (match_operand:DI 2 "u6bit_cint_operand" "n"))
781 (match_operand:DI 3 "reg_or_cint_operand" "rO"))]
782 ""
783 "bfins\t%0, %r3, %2, %2+%1-1"
784 [(set_attr "type" "X0")])
786 (define_insn "*insv_mm"
787 [(set (zero_extract:DI
788 (match_operand:DI 0 "register_operand" "+r")
789 (match_operand:DI 1 "u6bit_cint_operand" "n")
790 (match_operand:DI 2 "u6bit_cint_operand" "n"))
791 (zero_extract:DI
792 (match_operand:DI 3 "register_operand" "rO")
793 (match_dup 1)
794 (match_dup 2)))]
795 ""
796 {
797 int n;
799 operands[1] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[2]));
801 n = INTVAL (operands[2]);
802 n = (n == 0) ? 63 : n - 1;
803 operands[2] = GEN_INT (n);
805 return "mm\t%0, %r3, %1, %2";
806 }
807 [(set_attr "type" "X0")])
809 (define_expand "extv"
810 [(set (match_operand:DI 0 "register_operand" "")
811 (sign_extract:DI (match_operand 1 "nonautoincmem_general_operand" "")
812 (match_operand:DI 2 "immediate_operand" "")
813 (match_operand:DI 3 "immediate_operand" "")))]
814 ""
815 {
816 if (MEM_P (operands[1]))
817 {
818 HOST_WIDE_INT bit_offset, bit_width;
819 HOST_WIDE_INT first_byte_offset, last_byte_offset;
821 if (GET_MODE (operands[1]) != QImode)
822 FAIL;
824 bit_width = INTVAL (operands[2]);
825 bit_offset = INTVAL (operands[3]);
827 /* NOTE: bit_offset is relative to the mode of operand
828 1 (QImode). It will be negative in big-endian mode
829 here. Convert that back to the real offset. */
830 if (BYTES_BIG_ENDIAN)
831 bit_offset = GET_MODE_BITSIZE (QImode) - bit_width - bit_offset;
833 /* Reject bitfields that can be done with a normal load. */
834 if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
835 FAIL;
837 /* The value in memory cannot span more than 8 bytes. */
838 first_byte_offset = bit_offset / BITS_PER_UNIT;
839 last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
840 if (last_byte_offset - first_byte_offset > 7)
841 FAIL;
843 tilegx_expand_unaligned_load (operands[0], operands[1],
844 bit_width, bit_offset, 1);
846 DONE;
847 }
849 operands[1] = force_reg (DImode, operands[1]);
850 })
852 (define_expand "extzv"
853 [(set (match_operand:DI 0 "register_operand" "")
854 (zero_extract:DI (match_operand 1 "nonautoincmem_general_operand" "")
855 (match_operand:DI 2 "immediate_operand" "")
856 (match_operand:DI 3 "immediate_operand" "")))]
857 ""
858 {
859 HOST_WIDE_INT bit_width = INTVAL (operands[2]);
860 HOST_WIDE_INT bit_offset = INTVAL (operands[3]);
862 if (MEM_P (operands[1]))
863 {
864 HOST_WIDE_INT first_byte_offset, last_byte_offset;
866 if (GET_MODE (operands[1]) != QImode)
867 FAIL;
869 /* NOTE: bit_offset is relative to the mode of operand
870 1 (QImode). It will be negative in big-endian mode
871 here. */
872 if (BYTES_BIG_ENDIAN)
873 bit_offset = GET_MODE_BITSIZE (QImode) - bit_width - bit_offset;
875 /* Reject bitfields that can be done with a normal load. */
876 if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
877 FAIL;
879 /* The value in memory cannot span more than 8 bytes. */
880 first_byte_offset = bit_offset / BITS_PER_UNIT;
881 last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
882 if (last_byte_offset - first_byte_offset > 7)
883 FAIL;
885 tilegx_expand_unaligned_load (operands[0], operands[1],
886 bit_width, bit_offset, 0);
888 DONE;
889 }
891 operands[1] = force_reg (DImode, operands[1]);
893 if (bit_offset == 0)
894 {
895 /* Extracting the low bits is just a bitwise AND. */
896 HOST_WIDE_INT mask = ((HOST_WIDE_INT)1 << bit_width) - 1;
897 emit_insn (gen_anddi3 (operands[0], operands[1], GEN_INT (mask)));
898 DONE;
899 }
900 })
902 \f
903 ;;
904 ;; Addresses
905 ;;
907 ;; The next three patterns are used to materialize a position
908 ;; independent address by adding the difference of two labels to a base
909 ;; label in the text segment, assuming that the difference fits in 32
910 ;; signed bits.
911 (define_expand "mov_address_step1"
912 [(set (match_operand:DI 0 "register_operand" "")
913 (const:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
914 UNSPEC_HW2_LAST)))])
916 (define_expand "mov_address_step2"
917 [(set (match_operand:DI 0 "register_operand" "")
918 (unspec:DI
919 [(match_operand:DI 1 "reg_or_0_operand" "")
920 (const:DI (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
921 UNSPEC_HW1))]
922 UNSPEC_INSN_ADDR_SHL16INSLI))])
924 (define_expand "mov_address_step3"
925 [(set (match_operand:DI 0 "register_operand" "")
926 (unspec:DI
927 [(match_operand:DI 1 "reg_or_0_operand" "")
928 (const:DI (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
929 UNSPEC_HW0))]
930 UNSPEC_INSN_ADDR_SHL16INSLI))])
932 ;; First step of the 2-insn sequence to materialize a 32-bit symbolic
933 ;; address.
934 (define_expand "mov_address_32bit_step1"
935 [(set (match_operand:SI 0 "register_operand" "")
936 (const:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "")]
937 UNSPEC_HW1_LAST)))])
939 ;; Second step of the 2-insn sequence to materialize a 32-bit symbolic
940 ;; address.
941 (define_expand "mov_address_32bit_step2"
942 [(set (match_operand:SI 0 "register_operand" "")
943 (unspec:SI
944 [(match_operand:SI 1 "reg_or_0_operand" "")
945 (const:SI (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")]
946 UNSPEC_HW0))]
947 UNSPEC_INSN_ADDR_SHL16INSLI))])
949 \f
950 ;;
951 ;; pic related instructions
952 ;;
954 ;; NOTE: We compute the label in this unusual way because if we place
955 ;; the label after the lnk, whether it is at the same address as the
956 ;; lnk will vary depending on whether the optimization level chooses
957 ;; to insert bundling braces.
958 (define_insn "insn_lnk_and_label<bitsuffix>"
959 [(set (match_operand:I48MODE 0 "register_operand" "=r")
960 (unspec_volatile:I48MODE
961 [(match_operand:I48MODE 1 "symbolic_operand" "")]
962 UNSPEC_LNK_AND_LABEL))]
963 ""
964 "%1 = . + 8\n\tlnk\t%0"
965 [(set_attr "type" "Y1")])
967 ;; The next three patterns are used to materialize a position
968 ;; independent address by adding the difference of two labels to a
969 ;; base label in the text segment, assuming that the difference fits
970 ;; in 32 signed bits.
971 (define_expand "mov_pcrel_step1<bitsuffix>"
972 [(set (match_operand:I48MODE 0 "register_operand" "")
973 (const:I48MODE (unspec:I48MODE
974 [(match_operand:I48MODE 1 "symbolic_operand" "")
975 (match_operand:I48MODE 2 "symbolic_operand" "")]
976 UNSPEC_HW1_LAST_PCREL)))]
977 "flag_pic")
979 (define_expand "mov_pcrel_step2<bitsuffix>"
980 [(set (match_operand:I48MODE 0 "register_operand" "")
981 (unspec:I48MODE
982 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
983 (const:I48MODE
984 (unspec:I48MODE [(match_operand:I48MODE 2 "symbolic_operand" "")
985 (match_operand:I48MODE 3 "symbolic_operand" "")]
986 UNSPEC_HW0_PCREL))]
987 UNSPEC_INSN_ADDR_SHL16INSLI))]
988 "flag_pic")
990 (define_insn "mov_pcrel_step3<bitsuffix>"
991 [(set (match_operand:I48MODE 0 "register_operand" "=r")
992 (unspec:I48MODE [(match_operand:I48MODE 1 "reg_or_0_operand" "rO")
993 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")
994 (match_operand:I48MODE 3 "symbolic_operand" "in")
995 (match_operand:I48MODE 4 "symbolic_operand" "in")]
996 UNSPEC_MOV_PCREL_STEP3))]
997 "flag_pic"
998 "add<x>\t%0, %r1, %r2")
1000 ;; The next three patterns are used to materialize a position
1001 ;; independent 64-bit address by adding the difference of two labels to
1002 ;; a base label in the text segment, without any limitation on the size
1003 ;; of the difference.
1004 (define_expand "mov_large_pcrel_step1"
1005 [(set (match_operand:DI 0 "register_operand" "")
1006 (const:DI (unspec:DI
1007 [(match_operand:DI 1 "symbolic_operand" "")
1008 (match_operand:DI 2 "symbolic_operand" "")]
1009 UNSPEC_HW2_LAST_PCREL)))]
1010 "flag_pic")
1012 (define_expand "mov_large_pcrel_step2"
1013 [(set (match_operand:DI 0 "register_operand" "")
1014 (unspec:DI
1015 [(match_operand:DI 1 "reg_or_0_operand" "")
1016 (const:DI
1017 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")
1018 (match_operand:DI 3 "symbolic_operand" "")]
1019 UNSPEC_HW1_PCREL))]
1020 UNSPEC_INSN_ADDR_SHL16INSLI))]
1021 "flag_pic")
1023 ;; Note: step 3 is same as move_pcrel_step2.
1024 (define_expand "mov_large_pcrel_step3"
1025 [(set (match_operand:DI 0 "register_operand" "")
1026 (unspec:DI
1027 [(match_operand:DI 1 "reg_or_0_operand" "")
1028 (const:DI
1029 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")
1030 (match_operand:DI 3 "symbolic_operand" "")]
1031 UNSPEC_HW0_PCREL))]
1032 UNSPEC_INSN_ADDR_SHL16INSLI))]
1033 "flag_pic")
1035 (define_insn "mov_large_pcrel_step4"
1036 [(set (match_operand:DI 0 "register_operand" "=r")
1037 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
1038 (match_operand:DI 2 "reg_or_0_operand" "rO")
1039 (match_operand:DI 3 "symbolic_operand" "in")
1040 (match_operand:DI 4 "symbolic_operand" "in")]
1041 UNSPEC_MOV_LARGE_PCREL_STEP4))]
1042 "flag_pic"
1043 "add\t%0, %r1, %r2")
1045 ;; The next three patterns are used to materialize a position
1046 ;; independent 64-bit plt address by adding the difference of two
1047 ;; labels to a base label in the text segment.
1048 (define_expand "mov_plt_pcrel_step1"
1049 [(set (match_operand:DI 0 "register_operand" "")
1050 (const:DI (unspec:DI
1051 [(match_operand:DI 1 "symbolic_operand" "")
1052 (match_operand:DI 2 "symbolic_operand" "")]
1053 UNSPEC_HW2_LAST_PLT_PCREL)))]
1054 "flag_pic")
1056 (define_expand "mov_plt_pcrel_step2"
1057 [(set (match_operand:DI 0 "register_operand" "")
1058 (unspec:DI
1059 [(match_operand:DI 1 "reg_or_0_operand" "")
1060 (const:DI
1061 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")
1062 (match_operand:DI 3 "symbolic_operand" "")]
1063 UNSPEC_HW1_PLT_PCREL))]
1064 UNSPEC_INSN_ADDR_SHL16INSLI))]
1065 "flag_pic")
1067 (define_expand "mov_plt_pcrel_step3"
1068 [(set (match_operand:DI 0 "register_operand" "")
1069 (unspec:DI
1070 [(match_operand:DI 1 "reg_or_0_operand" "")
1071 (const:DI
1072 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")
1073 (match_operand:DI 3 "symbolic_operand" "")]
1074 UNSPEC_HW0_PLT_PCREL))]
1075 UNSPEC_INSN_ADDR_SHL16INSLI))]
1076 "flag_pic")
1078 ;; The next two patterns are used to materialize a position independent
1079 ;; 32-bit plt address by adding the difference of two labels to a base
1080 ;; label in the text segment.
1081 (define_expand "mov_plt_pcrel_step1_32bit"
1082 [(set (match_operand:SI 0 "register_operand" "")
1083 (const:SI (unspec:SI
1084 [(match_operand:SI 1 "symbolic_operand" "")
1085 (match_operand:SI 2 "symbolic_operand" "")]
1086 UNSPEC_HW1_LAST_PLT_PCREL)))]
1087 "flag_pic")
1089 (define_expand "mov_plt_pcrel_step2_32bit"
1090 [(set (match_operand:SI 0 "register_operand" "")
1091 (unspec:SI
1092 [(match_operand:SI 1 "reg_or_0_operand" "")
1093 (const:SI
1094 (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")
1095 (match_operand:SI 3 "symbolic_operand" "")]
1096 UNSPEC_HW0_PLT_PCREL))]
1097 UNSPEC_INSN_ADDR_SHL16INSLI))]
1098 "flag_pic")
1100 (define_expand "add_got16<bitsuffix>"
1101 [(set (match_operand:I48MODE 0 "register_operand" "")
1102 (plus:I48MODE
1103 (match_operand:I48MODE 1 "reg_or_0_operand" "")
1104 (const:I48MODE
1105 (unspec:I48MODE [(match_operand:I48MODE 2 "symbolic_operand" "")]
1106 UNSPEC_HW0_LAST_GOT))))]
1107 "flag_pic == 1")
1109 (define_expand "mov_got32_step1<bitsuffix>"
1110 [(set (match_operand:I48MODE 0 "register_operand" "")
1111 (const:I48MODE
1112 (unspec:I48MODE [(match_operand:I48MODE 1 "symbolic_operand" "")]
1113 UNSPEC_HW1_LAST_GOT)))]
1114 "flag_pic == 2")
1116 (define_expand "mov_got32_step2<bitsuffix>"
1117 [(set (match_operand:I48MODE 0 "register_operand" "")
1118 (unspec:I48MODE
1119 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1120 (const:I48MODE
1121 (unspec:I48MODE [(match_operand:I48MODE 2 "symbolic_operand" "")]
1122 UNSPEC_HW0_GOT))]
1123 UNSPEC_INSN_ADDR_SHL16INSLI))]
1124 "flag_pic == 2")
1126 \f
1127 ;;
1128 ;; TLS
1129 ;;
1131 (define_expand "mov_tls_gd_step1<bitsuffix>"
1132 [(set (match_operand:I48MODE 0 "register_operand" "")
1133 (const:I48MODE
1134 (unspec:I48MODE [(match_operand:I48MODE 1 "tls_symbolic_operand" "")]
1135 UNSPEC_HW1_LAST_TLS_GD)))]
1136 "HAVE_AS_TLS")
1138 (define_expand "mov_tls_gd_step2<bitsuffix>"
1139 [(set (match_operand:I48MODE 0 "register_operand" "")
1140 (unspec:I48MODE
1141 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1142 (const:I48MODE
1143 (unspec:I48MODE [(match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1144 UNSPEC_HW0_TLS_GD))]
1145 UNSPEC_INSN_ADDR_SHL16INSLI))]
1146 "HAVE_AS_TLS")
1148 (define_expand "mov_tls_ie_step1<bitsuffix>"
1149 [(set (match_operand:I48MODE 0 "register_operand" "")
1150 (const:I48MODE
1151 (unspec:I48MODE [(match_operand:I48MODE 1 "tls_symbolic_operand" "")]
1152 UNSPEC_HW1_LAST_TLS_IE)))]
1153 "HAVE_AS_TLS")
1155 (define_expand "mov_tls_ie_step2<bitsuffix>"
1156 [(set (match_operand:I48MODE 0 "register_operand" "")
1157 (unspec:I48MODE
1158 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1159 (const:I48MODE
1160 (unspec:I48MODE [(match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1161 UNSPEC_HW0_TLS_IE))]
1162 UNSPEC_INSN_ADDR_SHL16INSLI))]
1163 "HAVE_AS_TLS")
1165 (define_expand "mov_tls_le_step1<bitsuffix>"
1166 [(set (match_operand:I48MODE 0 "register_operand" "")
1167 (const:I48MODE
1168 (unspec:I48MODE [(match_operand:I48MODE 1 "tls_symbolic_operand" "")]
1169 UNSPEC_HW1_LAST_TLS_LE)))]
1170 "HAVE_AS_TLS")
1172 (define_expand "mov_tls_le_step2<bitsuffix>"
1173 [(set (match_operand:I48MODE 0 "register_operand" "")
1174 (unspec:I48MODE
1175 [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1176 (const:I48MODE
1177 (unspec:I48MODE [(match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1178 UNSPEC_HW0_TLS_LE))]
1179 UNSPEC_INSN_ADDR_SHL16INSLI))]
1180 "HAVE_AS_TLS")
1182 (define_expand "tls_gd_call<bitsuffix>"
1183 [(parallel
1184 [(set (reg:I48MODE 0)
1185 (unspec:I48MODE [(match_operand:I48MODE 0 "tls_symbolic_operand" "")
1186 (reg:I48MODE 0)]
1187 UNSPEC_TLS_GD_CALL))
1188 (clobber (reg:I48MODE 25))
1189 (clobber (reg:I48MODE 26))
1190 (clobber (reg:I48MODE 27))
1191 (clobber (reg:I48MODE 28))
1192 (clobber (reg:I48MODE 29))
1193 (clobber (reg:I48MODE 55))])]
1194 ""
1195 {
1196 cfun->machine->calls_tls_get_addr = true;
1197 })
1199 (define_insn "*tls_gd_call<bitsuffix>"
1200 [(set (reg:I48MODE 0)
1201 (unspec:I48MODE [(match_operand:I48MODE 0 "tls_symbolic_operand" "")
1202 (reg:I48MODE 0)]
1203 UNSPEC_TLS_GD_CALL))
1204 (clobber (reg:I48MODE 25))
1205 (clobber (reg:I48MODE 26))
1206 (clobber (reg:I48MODE 27))
1207 (clobber (reg:I48MODE 28))
1208 (clobber (reg:I48MODE 29))
1209 (clobber (reg:I48MODE 55))]
1210 ""
1211 "jal\ttls_gd_call(%0)"
1212 [(set_attr "type" "X1")])
1214 (define_insn "tls_gd_add<bitsuffix>"
1215 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1216 (unspec:I48MODE [(match_operand:I48MODE 1 "register_operand" "r")
1217 (match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1218 UNSPEC_TLS_GD_ADD))]
1219 "HAVE_AS_TLS"
1220 "add<x>i\t%0, %1, tls_gd_add(%2)")
1222 (define_insn "tls_add<bitsuffix>"
1223 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1224 (unspec:I48MODE [(match_operand:I48MODE 1 "register_operand" "r")
1225 (match_operand:I48MODE 2 "register_operand" "0")
1226 (match_operand:I48MODE 3 "tls_symbolic_operand" "")]
1227 UNSPEC_TLS_ADD))]
1228 "HAVE_AS_TLS"
1229 "add<x>i\t%0, %1, tls_add(%3)")
1231 (define_insn "tls_ie_load<bitsuffix>"
1232 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1233 (unspec:I48MODE [(match_operand:I48MODE 1 "register_operand" "r")
1234 (match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1235 UNSPEC_TLS_IE_LOAD))]
1236 "HAVE_AS_TLS"
1237 "ld<four_s_if_si>_tls\t%0, %1, tls_ie_load(%2)"
1238 [(set_attr "type" "X1_2cycle")])
1240 (define_insn "*zero_extract<mode>"
1241 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1242 (zero_extract:I48MODE
1243 (match_operand:I48MODE 1 "reg_or_0_operand" "r")
1244 (match_operand:I48MODE 2 "u6bit_cint_operand" "n")
1245 (match_operand:I48MODE 3 "u6bit_cint_operand" "n")))]
1246 ""
1247 "bfextu\t%0, %r1, %3, %3+%2-1"
1248 [(set_attr "type" "X0")])
1250 (define_insn "*sign_extract_low32"
1251 [(set (match_operand:DI 0 "register_operand" "=r")
1252 (sign_extract:DI
1253 (match_operand:DI 1 "reg_or_0_operand" "r")
1254 (match_operand:DI 2 "u6bit_cint_operand" "n")
1255 (match_operand:DI 3 "u6bit_cint_operand" "n")))]
1256 "INTVAL (operands[3]) == 0 && INTVAL (operands[2]) == 32"
1257 "addxi\t%0, %r1, 0")
1259 (define_insn "*sign_extract"
1260 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1261 (sign_extract:I48MODE
1262 (match_operand:I48MODE 1 "reg_or_0_operand" "r")
1263 (match_operand:I48MODE 2 "u6bit_cint_operand" "n")
1264 (match_operand:I48MODE 3 "u6bit_cint_operand" "n")))]
1265 ""
1266 "bfexts\t%0, %r1, %3, %3+%2-1"
1267 [(set_attr "type" "X0")])
1269 \f
1270 ;;
1271 ;; Arithmetic ops
1272 ;;
1274 (define_insn "add<mode>3"
1275 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1276 (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rO,rO,rO")
1277 (match_operand:I48MODE 2 "add_operand" "r,I,JT")))]
1278 ""
1279 "@
1280 add<x>\t%0, %r1, %r2
1281 add<x>i\t%0, %r1, %2
1282 add<x>li\t%0, %r1, %H2"
1283 [(set_attr "type" "*,*,X01")])
1285 (define_insn "*addsi3_sext"
1286 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1287 (sign_extend:DI
1288 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO,rO")
1289 (match_operand:SI 2 "add_operand" "r,I,JT"))))]
1290 ""
1291 "@
1292 addx\t%0, %r1, %r2
1293 addxi\t%0, %r1, %2
1294 addxli\t%0, %r1, %H2"
1295 [(set_attr "type" "*,*,X01")])
1297 (define_insn "sub<mode>3"
1298 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1299 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
1300 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
1301 ""
1302 "sub<x>\t%0, %r1, %r2")
1304 (define_insn "*subsi3_sext"
1305 [(set (match_operand:DI 0 "register_operand" "=r")
1306 (sign_extend:DI
1307 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1308 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
1309 ""
1310 "subx\t%0, %r1, %r2")
1312 (define_insn "neg<mode>2"
1313 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1314 (neg:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rO")))]
1315 ""
1316 "sub<x>\t%0, zero, %r1")
1318 (define_insn "*negsi2_sext"
1319 [(set (match_operand:DI 0 "register_operand" "=r")
1320 (sign_extend:DI
1321 (neg:SI (match_operand:SI 1 "reg_or_0_operand" "rO"))))]
1322 ""
1323 "subx\t%0, zero, %r1")
1325 (define_insn "ssaddsi3"
1326 [(set (match_operand:SI 0 "register_operand" "=r")
1327 (ss_plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1328 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
1329 ""
1330 "addxsc\t%0, %r1, %r2"
1331 [(set_attr "type" "X01")])
1333 (define_insn "*ssaddsi3_sext"
1334 [(set (match_operand:DI 0 "register_operand" "=r")
1335 (sign_extend:DI
1336 (ss_plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1337 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
1338 ""
1339 "addxsc\t%0, %r1, %r2"
1340 [(set_attr "type" "X01")])
1342 (define_insn "sssubsi3"
1343 [(set (match_operand:SI 0 "register_operand" "=r")
1344 (ss_minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1345 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
1346 ""
1347 "subxsc\t%0, %r1, %r2"
1348 [(set_attr "type" "X01")])
1350 (define_insn "*sssubsi3_sext"
1351 [(set (match_operand:DI 0 "register_operand" "=r")
1352 (sign_extend:DI
1353 (ss_minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1354 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
1355 ""
1356 "subxsc\t%0, %r1, %r2"
1357 [(set_attr "type" "X01")])
1359 (define_expand "addsf3"
1360 [(set (match_operand:SF 0 "register_operand" "")
1361 (plus:SF (match_operand:SF 1 "register_operand" "")
1362 (match_operand:SF 2 "register_operand" "")))]
1363 ""
1364 {
1365 rtx result = gen_lowpart (DImode, operands[0]);
1366 rtx a = gen_lowpart (DImode, operands[1]);
1367 rtx b = gen_lowpart (DImode, operands[2]);
1369 rtx tmp = gen_reg_rtx (DImode);
1370 rtx flags = gen_reg_rtx (DImode);
1372 emit_insn (gen_insn_fsingle_add1 (tmp, a, b));
1373 emit_insn (gen_insn_fsingle_addsub2 (tmp, tmp, a, b));
1374 emit_insn (gen_insn_fsingle_pack1 (flags, tmp));
1375 emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags));
1377 DONE;
1378 })
1380 (define_expand "subsf3"
1381 [(set (match_operand:SF 0 "register_operand" "")
1382 (minus:SF (match_operand:SF 1 "register_operand" "")
1383 (match_operand:SF 2 "register_operand" "")))]
1384 ""
1385 {
1386 rtx result = gen_lowpart (DImode, operands[0]);
1387 rtx a = gen_lowpart (DImode, operands[1]);
1388 rtx b = gen_lowpart (DImode, operands[2]);
1390 rtx tmp = gen_reg_rtx (DImode);
1391 rtx flags = gen_reg_rtx (DImode);
1393 emit_insn (gen_insn_fsingle_sub1 (tmp, a, b));
1394 emit_insn (gen_insn_fsingle_addsub2 (tmp, tmp, a, b));
1395 emit_insn (gen_insn_fsingle_pack1 (flags, tmp));
1396 emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags));
1398 DONE;
1399 })
1401 (define_expand "mulsf3"
1402 [(set (match_operand:SF 0 "register_operand" "")
1403 (mult:SF (match_operand:SF 1 "register_operand" "")
1404 (match_operand:SF 2 "register_operand" "")))]
1405 ""
1406 {
1407 rtx result = gen_lowpart (DImode, operands[0]);
1408 rtx a = gen_lowpart (DImode, operands[1]);
1409 rtx b = gen_lowpart (DImode, operands[2]);
1411 rtx tmp1 = gen_reg_rtx (DImode);
1412 rtx tmp2 = gen_reg_rtx (DImode);
1413 rtx flags = gen_reg_rtx (DImode);
1415 emit_insn (gen_insn_fsingle_mul1 (tmp1, a, b));
1416 emit_insn (gen_insn_fsingle_mul2 (tmp2, tmp1, b));
1417 emit_insn (gen_insn_fsingle_pack1 (flags, tmp2));
1418 emit_insn (gen_insn_fsingle_pack2 (result, tmp2, flags));
1420 DONE;
1421 })
1423 (define_expand "adddf3"
1424 [(set (match_operand:DF 0 "register_operand" "")
1425 (plus:DF (match_operand:DF 1 "register_operand" "")
1426 (match_operand:DF 2 "register_operand" "")))]
1427 ""
1428 {
1429 rtx result = gen_lowpart (DImode, operands[0]);
1430 rtx a = gen_lowpart (DImode, operands[1]);
1431 rtx b = gen_lowpart (DImode, operands[2]);
1433 rtx min = gen_reg_rtx (DImode);
1434 rtx max = gen_reg_rtx (DImode);
1435 rtx flags = gen_reg_rtx (DImode);
1437 emit_insn (gen_insn_fdouble_unpack_min (min, a, b));
1438 emit_insn (gen_insn_fdouble_unpack_max (max, a, b));
1439 emit_insn (gen_insn_fdouble_add_flags (flags, a, b));
1440 emit_insn (gen_insn_fdouble_addsub (max, max, min, flags));
1441 emit_insn (gen_insn_fdouble_pack1 (result, max, flags));
1442 emit_insn (gen_insn_fdouble_pack2 (result, result, max, const0_rtx));
1444 DONE;
1445 })
1447 (define_expand "subdf3"
1448 [(set (match_operand:DF 0 "register_operand" "")
1449 (minus:DF (match_operand:DF 1 "register_operand" "")
1450 (match_operand:DF 2 "register_operand" "")))]
1451 ""
1452 {
1453 rtx result = gen_lowpart (DImode, operands[0]);
1454 rtx a = gen_lowpart (DImode, operands[1]);
1455 rtx b = gen_lowpart (DImode, operands[2]);
1457 rtx min = gen_reg_rtx (DImode);
1458 rtx max = gen_reg_rtx (DImode);
1459 rtx flags = gen_reg_rtx (DImode);
1461 emit_insn (gen_insn_fdouble_unpack_min (min, a, b));
1462 emit_insn (gen_insn_fdouble_unpack_max (max, a, b));
1463 emit_insn (gen_insn_fdouble_sub_flags (flags, a, b));
1464 emit_insn (gen_insn_fdouble_addsub (max, max, min, flags));
1465 emit_insn (gen_insn_fdouble_pack1 (result, max, flags));
1466 emit_insn (gen_insn_fdouble_pack2 (result, result, max, const0_rtx));
1468 DONE;
1469 })
1471 (define_expand "muldf3"
1472 [(set (match_operand:DF 0 "register_operand" "")
1473 (mult:DF (match_operand:DF 1 "register_operand" "")
1474 (match_operand:DF 2 "register_operand" "")))]
1475 ""
1476 ;; TODO: Decide if we should not inline this with -Os.
1477 ;; "optimize_function_for_speed_p (cfun)"
1478 {
1479 rtx result = gen_lowpart (DImode, operands[0]);
1480 rtx a = gen_lowpart (DImode, operands[1]);
1481 rtx b = gen_lowpart (DImode, operands[2]);
1483 rtx a_unpacked = gen_reg_rtx (DImode);
1484 rtx b_unpacked = gen_reg_rtx (DImode);
1485 rtx flags = gen_reg_rtx (DImode);
1487 rtx low1 = gen_reg_rtx (DImode);
1488 rtx low = gen_reg_rtx (DImode);
1489 rtx low_carry = gen_reg_rtx (DImode);
1491 rtx mid = gen_reg_rtx (DImode);
1492 rtx mid_l32 = gen_reg_rtx (DImode);
1493 rtx mid_r32 = gen_reg_rtx (DImode);
1495 rtx high1 = gen_reg_rtx (DImode);
1496 rtx high = gen_reg_rtx (DImode);
1497 rtx high1_plus_mid_r32 = gen_reg_rtx (DImode);
1499 /* NOTE: We compute using max(a, 0) and max(b, 0) rather than
1500 min(a, b) and max(a, b) because for multiply we just need to unpack,
1501 we don't actually care which is min and which is max. And this
1502 formulation gives the scheduler more freedom in case one of a or b
1503 would stall at the start of this code sequence. */
1504 emit_insn (gen_insn_fdouble_unpack_max (a_unpacked, a, const0_rtx));
1505 emit_insn (gen_insn_fdouble_unpack_max (b_unpacked, b, const0_rtx));
1506 emit_insn (gen_insn_fdouble_mul_flags (flags, a, b));
1508 /* This depends on the fact that the high few bits of the unpacked
1509 mantissa are zero, so we can't have a carry out from the mid sum. */
1510 emit_insn (gen_insn_mul_lu_lu (low1, a_unpacked, b_unpacked));
1511 emit_insn (gen_insn_mul_hu_lu (mid, a_unpacked, b_unpacked));
1512 emit_insn (gen_insn_mula_hu_lu (mid, mid, b_unpacked, a_unpacked));
1513 emit_insn (gen_insn_mul_hu_hu (high1, a_unpacked, b_unpacked));
1515 emit_insn (gen_ashldi3 (mid_l32, mid, GEN_INT (32)));
1516 emit_insn (gen_lshrdi3 (mid_r32, mid, GEN_INT (32)));
1518 emit_insn (gen_adddi3 (high1_plus_mid_r32, high1, mid_r32));
1520 emit_insn (gen_adddi3 (low, low1, mid_l32));
1521 emit_insn (gen_insn_cmpltu_didi (low_carry, low, mid_l32));
1523 emit_insn (gen_adddi3 (high, high1_plus_mid_r32, low_carry));
1525 emit_insn (gen_insn_fdouble_pack1 (result, high, flags));
1526 emit_insn (gen_insn_fdouble_pack2 (result, result, high, low));
1528 DONE;
1529 })
1531 \f
1532 ;;
1533 ;; Shifts
1534 ;;
1536 (define_insn "ashl<mode>3"
1537 [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
1538 (ashift:I48MODE
1539 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1540 (match_operand:SI 2 "reg_or_u<nbits>bit_operand" "I,rO")))]
1541 ""
1542 "@
1543 shl<x>i\t%0, %r1, %2
1544 shl<x>\t%0, %r1, %r2"
1545 [(set_attr "type" "<shift_pipe>,<shift_pipe>")])
1547 (define_insn "*ashlsi3_sext"
1548 [(set (match_operand:DI 0 "register_operand" "=r,r")
1549 (sign_extend:DI
1550 (ashift:SI
1551 (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1552 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO"))))]
1553 ""
1554 "@
1555 shlxi\t%0, %r1, %2
1556 shlx\t%0, %r1, %r2"
1557 [(set_attr "type" "X01,X01")])
1559 (define_insn "ashr<mode>3"
1560 [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
1561 (ashiftrt:I48MODE
1562 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1563 (match_operand:SI 2 "reg_or_u<nbits>bit_operand" "I,rO")))]
1564 ""
1565 "@
1566 shrsi\t%0, %r1, %2
1567 shrs\t%0, %r1, %r2")
1569 (define_insn "*ashrsi3_sext"
1570 [(set (match_operand:DI 0 "register_operand" "=r,r")
1571 (sign_extend:DI
1572 (ashiftrt:SI (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1573 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO"))))]
1574 ""
1575 "@
1576 shrsi\t%0, %r1, %2
1577 shrs\t%0, %r1, %r2")
1579 (define_insn "lshr<mode>3"
1580 [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
1581 (lshiftrt:I48MODE
1582 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1583 (match_operand:SI 2 "reg_or_u<nbits>bit_operand" "I,rO")))]
1584 ""
1585 "@
1586 shru<x>i\t%0, %r1, %2
1587 shru<x>\t%0, %r1, %r2"
1588 [(set_attr "type" "<shift_pipe>,<shift_pipe>")])
1590 (define_insn "*lshrsi3_sext"
1591 [(set (match_operand:DI 0 "register_operand" "=r,r")
1592 (sign_extend:DI
1593 (lshiftrt:SI
1594 (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1595 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO"))))]
1596 ""
1597 "@
1598 shruxi\t%0, %r1, %2
1599 shrux\t%0, %r1, %r2"
1600 [(set_attr "type" "X01,X01")])
1602 (define_insn "rotldi3"
1603 [(set (match_operand:DI 0 "register_operand" "=r,r")
1604 (rotate:DI (match_operand:DI 1 "reg_or_0_operand" "rO,rO")
1605 (match_operand:SI 2 "reg_or_u6bit_operand" "I,rO")))]
1606 ""
1607 "@
1608 rotli\t%0, %r1, %2
1609 rotl\t%0, %r1, %r2")
1611 (define_insn "insn_shl16insli"
1612 [(set (match_operand:DI 0 "register_operand" "=r,r")
1613 (ior:DI
1614 (ashift:DI
1615 (match_operand:DI 1 "reg_or_0_operand" "rO,rO")
1616 (const_int 16))
1617 (match_operand:DI 2 "u16bit_or_const_symbolic_operand" "O,KT")))]
1618 ""
1619 "@
1620 shli\t%0, %r1, 16
1621 shl16insli\t%0, %r1, %H2"
1622 [(set_attr "type" "*,X01")])
1624 (define_insn "insn_addr_shl16insli<bitsuffix>"
1625 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1626 (unspec:I48MODE
1627 [(match_operand:I48MODE 1 "reg_or_0_operand" "rO")
1628 (match_operand:I48MODE 2 "const_symbolic_operand" "T")]
1629 UNSPEC_INSN_ADDR_SHL16INSLI))]
1630 ""
1631 "shl16insli\t%0, %r1, %H2"
1632 [(set_attr "type" "X01")])
1634 \f
1635 ;;
1636 ;; Compares
1637 ;;
1639 (define_expand "cstore<mode>4"
1640 [(set (match_operand:DI 0 "register_operand" "")
1641 (match_operator:DI 1 "ordered_comparison_operator"
1642 [(match_operand:FI48MODE 2 "reg_or_cint_operand" "")
1643 (match_operand:FI48MODE 3 "reg_or_cint_operand" "")]))]
1644 ""
1645 {
1646 if (!tilegx_emit_setcc (operands, GET_MODE (operands[2])))
1647 FAIL;
1648 else
1649 DONE;
1650 })
1653 (define_insn "insn_cmpne_<I48MODE:mode><I48MODE2:mode>"
1654 [(set (match_operand:I48MODE2 0 "register_operand" "=r")
1655 (ne:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
1656 (match_operand:I48MODE 2 "reg_or_cint_operand" "rO")))]
1657 ""
1658 "cmpne\t%0, %r1, %r2")
1660 (define_insn "insn_cmpeq_<I48MODE:mode><I48MODE2:mode>"
1661 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1662 (eq:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "%rO,rO")
1663 (match_operand:I48MODE 2 "reg_or_cint_operand" "I,rO")))]
1664 ""
1665 "@
1666 cmpeqi\t%0, %r1, %2
1667 cmpeq\t%0, %r1, %r2")
1669 (define_insn "insn_cmplts_<I48MODE:mode><I48MODE2:mode>"
1670 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1671 (lt:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1672 (match_operand:I48MODE 2 "reg_or_cint_operand" "I,rO")))]
1673 ""
1674 "@
1675 cmpltsi\t%0, %r1, %2
1676 cmplts\t%0, %r1, %r2")
1678 (define_insn "insn_cmpltu_<I48MODE:mode><I48MODE2:mode>"
1679 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1680 (ltu:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1681 (match_operand:I48MODE 2 "reg_or_cint_operand" "I,rO")))]
1682 ""
1683 "@
1684 cmpltui\t%0, %r1, %2
1685 cmpltu\t%0, %r1, %r2"
1686 [(set_attr "type" "X01,*")])
1688 (define_insn "insn_cmples_<I48MODE:mode><I48MODE2:mode>"
1689 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1690 (le:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1691 (match_operand:I48MODE 2 "reg_or_cint_operand" "L,rO")))]
1692 ""
1693 "@
1694 cmpltsi\t%0, %r1, %P2
1695 cmples\t%0, %r1, %r2")
1697 (define_insn "insn_cmpleu_<I48MODE:mode><I48MODE2:mode>"
1698 [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1699 (leu:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1700 (match_operand:I48MODE 2 "reg_or_cint_operand" "Q,rO")))]
1701 ""
1702 "@
1703 cmpltui\t%0, %r1, %P2
1704 cmpleu\t%0, %r1, %r2"
1705 [(set_attr "type" "X01,*")])
1707 \f
1708 ;;
1709 ;; Logical ops
1710 ;;
1712 (define_insn "and<mode>3"
1713 [(set (match_operand:IVNMODE 0 "register_operand" "=r,r,r,r")
1714 (and:IVNMODE (match_operand:IVNMODE 1 "reg_or_0_operand" "%rO,rO,0,rO")
1715 (match_operand:IVNMODE 2 "and_operand" "I,S,M,rO")))]
1716 ""
1717 "@
1718 andi\t%0, %r1, %2
1719 bfextu\t%0, %r1, %M2
1720 bfins\t%0, zero, %m2
1721 and\t%0, %r1, %r2"
1722 [(set_attr "type" "*,X0,X0,*")])
1724 (define_insn "*andsi3_sext"
1725 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
1726 (sign_extend:DI
1727 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO,0,rO")
1728 (match_operand:SI 2 "and_operand" "I,S,M,rO"))))]
1729 ""
1730 "@
1731 andi\t%0, %r1, %2
1732 bfextu\t%0, %r1, %M2
1733 bfins\t%0, zero, %m2
1734 and\t%0, %r1, %r2"
1735 [(set_attr "type" "*,X0,X0,*")])
1737 (define_insn "anddi3"
1738 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
1739 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rO,rO,rO,rO,0,rO")
1740 (match_operand:DI 2 "and_operand" "I,Z0,Z1,S,M,rO")))]
1741 ""
1742 "@
1743 andi\t%0, %r1, %2
1744 v4int_l\t%0, zero, %r1
1745 v4int_h\t%0, %r1, zero
1746 bfextu\t%0, %r1, %M2
1747 bfins\t%0, zero, %m2
1748 and\t%0, %r1, %r2"
1749 [(set_attr "type" "*,X01,X01,X0,X0,*")])
1751 (define_insn "ior<mode>3"
1752 [(set (match_operand:IVMODE 0 "register_operand" "=r,r")
1753 (ior:IVMODE (match_operand:IVMODE 1 "reg_or_0_operand" "%rO,rO")
1754 (match_operand:IVMODE 2 "reg_or_s8bit_operand" "rO,I")))]
1755 ""
1756 "@
1757 or\t%0, %r1, %r2
1758 ori\t%0, %r1, %2"
1759 [(set_attr "type" "*,X01")])
1761 (define_insn "*iorsi3_sext"
1762 [(set (match_operand:DI 0 "register_operand" "=r,r")
1763 (sign_extend:DI
1764 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO")
1765 (match_operand:SI 2 "reg_or_s8bit_operand" "rO,I"))))]
1766 ""
1767 "@
1768 or\t%0, %r1, %r2
1769 ori\t%0, %r1, %2"
1770 [(set_attr "type" "*,X01")])
1772 (define_insn "xor<mode>3"
1773 [(set (match_operand:IVMODE 0 "register_operand" "=r,r")
1774 (xor:IVMODE (match_operand:IVMODE 1 "reg_or_0_operand" "%rO,rO")
1775 (match_operand:IVMODE 2 "reg_or_s8bit_operand" "rO,I")))]
1776 ""
1777 "@
1778 xor\t%0, %r1, %r2
1779 xori\t%0, %r1, %2"
1780 [(set_attr "type" "*,X01")])
1782 (define_insn "*xorsi3_sext"
1783 [(set (match_operand:DI 0 "register_operand" "=r,r")
1784 (sign_extend:DI
1785 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO")
1786 (match_operand:SI 2 "reg_or_s8bit_operand" "rO,I"))))]
1787 ""
1788 "@
1789 xor\t%0, %r1, %r2
1790 xori\t%0, %r1, %2"
1791 [(set_attr "type" "*,X01")])
1793 (define_insn "clzdi2"
1794 [(set (match_operand:DI 0 "register_operand" "=r")
1795 (clz:DI (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1796 ""
1797 "clz\t%0, %r1"
1798 [(set_attr "type" "Y0")])
1800 (define_expand "clzsi2"
1801 [(set (match_dup 2)
1802 (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" "")))
1803 (set (match_dup 2)
1804 (ashift:DI (match_dup 2)
1805 (const_int 32)))
1806 (set (match_dup 2)
1807 (clz:DI (match_dup 2)))
1808 (set (match_operand:SI 0 "register_operand" "")
1809 (subreg:SI (match_dup 2) 0))]
1810 ""
1811 {
1812 operands[2] = gen_reg_rtx (DImode);
1813 })
1815 (define_insn "ctz<mode>2"
1816 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1817 (ctz:I48MODE (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1818 ""
1819 "ctz\t%0, %r1"
1820 [(set_attr "type" "Y0")])
1822 (define_insn "popcount<mode>2"
1823 [(set (match_operand:I48MODE 0 "register_operand" "=r")
1824 (popcount:I48MODE (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1825 ""
1826 "pcnt\t%0, %r1"
1827 [(set_attr "type" "Y0")])
1829 (define_expand "parity<mode>2"
1830 [(set (match_operand:I48MODE 0 "register_operand" "")
1831 (parity:I48MODE (match_operand:DI 1 "reg_or_0_operand" "")))]
1832 ""
1833 {
1834 rtx tmp = gen_reg_rtx (<MODE>mode);
1835 emit_insn (gen_popcount<mode>2 (tmp, operands[1]));
1836 emit_insn (gen_and<mode>3 (operands[0], tmp, const1_rtx));
1837 DONE;
1838 })
1840 (define_insn "bswapdi2"
1841 [(set (match_operand:DI 0 "register_operand" "=r")
1842 (bswap:DI (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1843 ""
1844 "revbytes\t%0, %r1"
1845 [(set_attr "type" "Y0")])
1847 (define_expand "bswapsi2"
1848 [(set (match_operand:SI 0 "register_operand" "")
1849 (bswap:SI (match_operand:SI 1 "reg_or_0_operand" "")))]
1850 ""
1851 {
1852 rtx tmp = gen_reg_rtx (DImode);
1853 emit_insn (gen_bswapdi2 (tmp, gen_lowpart (DImode, operands[1])));
1854 emit_insn (gen_ashrdi3 (gen_lowpart (DImode, operands[0]),
1855 tmp, GEN_INT (32)));
1856 DONE;
1857 })
1859 (define_insn "one_cmpl<mode>2"
1860 [(set (match_operand:IVMODE 0 "register_operand" "=r")
1861 (not:IVMODE (match_operand:IVMODE 1 "reg_or_0_operand" "rO")))]
1862 ""
1863 "nor\t%0, %r1, zero")
1865 \f
1866 ;;
1867 ;; Conditional moves
1868 ;;
1870 (define_expand "mov<mode>cc"
1871 [(set (match_operand:I48MODE 0 "register_operand" "")
1872 (if_then_else:I48MODE
1873 (match_operand 1 "comparison_operator" "")
1874 (match_operand:I48MODE 2 "reg_or_0_operand" "")
1875 (match_operand:I48MODE 3 "reg_or_0_operand" "")))]
1876 ""
1877 { operands[1] = tilegx_emit_conditional_move (operands[1]); })
1879 (define_insn "movcc_insn_<I48MODE2:mode><I48MODE:mode>"
1880 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r,r")
1881 (if_then_else:I48MODE
1882 (match_operator 4 "eqne_operator"
1883 [(match_operand:I48MODE2 1 "reg_or_0_operand" "rO,rO,rO,rO")
1884 (const_int 0)])
1885 (match_operand:I48MODE 2 "reg_or_0_operand" "rO,O,rO,0")
1886 (match_operand:I48MODE 3 "reg_or_0_operand" "O,rO,0,rO")))]
1887 ""
1888 "@
1889 m%c4\t%0, %r1, %r2
1890 m%C4\t%0, %r1, %r3
1891 cmov%d4z\t%0, %r1, %r2
1892 cmov%D4z\t%0, %r1, %r3"
1893 [(set_attr "type" "*,*,Y0,Y0")])
1895 (define_expand "insn_mz"
1896 [(set (match_operand:DI 0 "register_operand" "")
1897 (if_then_else:DI
1898 (eq (match_operand:DI 1 "reg_or_0_operand" "")
1899 (const_int 0))
1900 (match_operand:DI 2 "reg_or_0_operand" "")
1901 (const_int 0)))])
1903 (define_expand "insn_mnz"
1904 [(set (match_operand:DI 0 "register_operand" "")
1905 (if_then_else:DI
1906 (ne (match_operand:DI 1 "reg_or_0_operand" "")
1907 (const_int 0))
1908 (match_operand:DI 2 "reg_or_0_operand" "")
1909 (const_int 0)))])
1911 (define_expand "insn_cmoveqz"
1912 [(set (match_operand:DI 0 "register_operand" "")
1913 (if_then_else:DI
1914 (eq (match_operand:DI 2 "reg_or_0_operand" "")
1915 (const_int 0))
1916 (match_operand:DI 3 "reg_or_0_operand" "")
1917 (match_operand:DI 1 "reg_or_0_operand" "")))])
1919 (define_expand "insn_cmovnez"
1920 [(set (match_operand:DI 0 "register_operand" "")
1921 (if_then_else:DI
1922 (ne (match_operand:DI 2 "reg_or_0_operand" "")
1923 (const_int 0))
1924 (match_operand:DI 3 "reg_or_0_operand" "")
1925 (match_operand:DI 1 "reg_or_0_operand" "")))])
1927 \f
1928 ;;
1929 ;; Conversions
1930 ;;
1932 (define_insn "zero_extendqi<mode>2"
1933 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1934 (zero_extend:I48MODE (match_operand:QI 1 "move_operand" "rO,U,m")))]
1935 ""
1936 "@
1937 bfextu\t%0, %r1, 0, 7
1938 ld1u\t%0, %1
1939 ld1u_add\t%0, %I1, %i1"
1940 [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1942 (define_insn "zero_extendhi<mode>2"
1943 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1944 (zero_extend:I48MODE (match_operand:HI 1 "move_operand" "rO,U,m")))]
1945 ""
1946 "@
1947 bfextu\t%0, %r1, 0, 15
1948 ld2u\t%0, %1
1949 ld2u_add\t%0, %I1, %i1"
1950 [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1952 (define_insn "zero_extendsidi2"
1953 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1954 (zero_extend:DI (match_operand:SI 1 "move_operand" "rO,U,m")))]
1955 ""
1956 "@
1957 v4int_l\t%0, zero, %r1
1958 ld4u\t%0, %1
1959 ld4u_add\t%0, %I1, %i1"
1960 [(set_attr "type" "X01,Y2_2cycle,X1_2cycle")])
1962 (define_insn "extendqi<mode>2"
1963 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1964 (sign_extend:I48MODE (match_operand:QI 1 "move_operand" "rO,U,m")))]
1965 ""
1966 "@
1967 bfexts\t%0, %r1, 0, 7
1968 ld1s\t%0, %1
1969 ld1s_add\t%0, %I1, %i1"
1970 [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1972 (define_insn "extendhi<mode>2"
1973 [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1974 (sign_extend:I48MODE (match_operand:HI 1 "move_operand" "rO,U,m")))]
1975 ""
1976 "@
1977 bfexts\t%0, %r1, 0, 15
1978 ld2s\t%0, %1
1979 ld2s_add\t%0, %I1, %i1"
1980 [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1982 ;; All SImode integer registers should already be in sign-extended
1983 ;; form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can therefore
1984 ;; get rid of register->register instructions if we constrain the
1985 ;; source to be in the same register as the destination.
1986 (define_insn_and_split "extendsidi2"
1987 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1988 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,U,m")))]
1989 ""
1990 "@
1991 #
1992 ld4s\t%0, %1
1993 ld4s_add\t%0, %I1, %i1"
1994 "&& reload_completed && register_operand (operands[1], VOIDmode)"
1995 [(const_int 0)]
1996 {
1997 emit_note (NOTE_INSN_DELETED);
1998 DONE;
1999 }
2000 [(set_attr "type" "*,Y2_2cycle,X1_2cycle")])
2002 ;; Integer truncation patterns. Truncating SImode values to smaller
2003 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2004 ;; DImode values to SImode is not a no-op since we
2005 ;; need to make sure that the lower 32 bits are properly sign-extended
2006 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2007 ;; smaller than SImode is equivalent to two separate truncations:
2008 ;;
2009 ;; A B
2010 ;; DI ---> HI == DI ---> SI ---> HI
2011 ;; DI ---> QI == DI ---> SI ---> QI
2012 ;;
2013 ;; Step A needs a real instruction but step B does not.
2015 (define_insn "truncdisi2"
2016 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,U,m")
2017 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO,rO,rO")))]
2018 ""
2019 "@
2020 addxi\t%0, %r1, 0
2021 st4\t%0, %r1
2022 st4_add\t%I0, %r1, %i0"
2023 [(set_attr "type" "Y01,Y2,X1")])
2025 (define_insn "truncdihi2"
2026 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,U,m")
2027 (truncate:HI (match_operand:DI 1 "reg_or_0_operand" "rO,rO,rO")))]
2028 ""
2029 "@
2030 addxi\t%0, %r1, 0
2031 st2\t%0, %r1
2032 st2_add\t%I0, %r1, %i0"
2033 [(set_attr "type" "Y01,Y2,X1")])
2035 (define_insn "truncdiqi2"
2036 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,U,m")
2037 (truncate:QI (match_operand:DI 1 "reg_or_0_operand" "rO,rO,rO")))]
2038 ""
2039 "@
2040 addxi\t%0, %r1, 0
2041 st1\t%0, %r1
2042 st1_add\t%I0, %r1, %i0"
2043 [(set_attr "type" "Y01,Y2,X1")])
2045 ;; Combiner patterns to optimize away unnecessary truncates.
2047 (define_insn "*zero_extendsidi_truncdisi"
2048 [(set (match_operand:DI 0 "register_operand" "=r")
2049 (zero_extend:DI
2050 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))))]
2051 ""
2052 "v4int_l\t%0, zero, %r1"
2053 [(set_attr "type" "X01")])
2055 (define_insn "*addsi_truncdisi"
2056 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2057 (plus:SI
2058 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "%rO,rO,rO"))
2059 (match_operand:SI 2 "add_operand" "r,I,JT")))]
2060 ""
2061 "@
2062 addx\t%0, %r1, %r2
2063 addxi\t%0, %r1, %2
2064 addxli\t%0, %r1, %H2"
2065 [(set_attr "type" "*,*,X01")])
2067 (define_insn "*addsi_truncdisi2"
2068 [(set (match_operand:SI 0 "register_operand" "=r")
2069 (plus:SI
2070 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))
2071 (truncate:SI (match_operand:DI 2 "reg_or_0_operand" "rO"))))]
2072 ""
2073 "addx\t%0, %r1, %r2")
2075 (define_insn "*ashldi_truncdisi"
2076 [(set (match_operand:DI 0 "register_operand" "=r")
2077 (ashift:DI
2078 (match_operand:DI 1 "reg_or_0_operand" "rO")
2079 (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2080 ""
2081 "shl\t%0, %r1, %r2")
2083 (define_insn "*ashlsi_truncdisi"
2084 [(set (match_operand:SI 0 "register_operand" "=r,r")
2085 (ashift:SI
2086 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO,rO"))
2087 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO")))]
2088 ""
2089 "@
2090 shlxi\t%0, %r1, %2
2091 shlx\t%0, %r1, %r2"
2092 [(set_attr "type" "X01,X01")])
2094 (define_insn "*ashlsi_truncdisi2"
2095 [(set (match_operand:SI 0 "register_operand" "=r")
2096 (ashift:SI
2097 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))
2098 (truncate:SI (match_operand:DI 2 "reg_or_0_operand" "rO"))))]
2099 ""
2100 "shlx\t%0, %r1, %r2"
2101 [(set_attr "type" "X01")])
2103 (define_insn "*ashrdi3_truncdisi"
2104 [(set (match_operand:DI 0 "register_operand" "=r")
2105 (ashiftrt:DI
2106 (match_operand:DI 1 "reg_or_0_operand" "rO")
2107 (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2108 ""
2109 "shrs\t%0, %r1, %r2")
2111 (define_insn "*lshrsi_truncdisi"
2112 [(set (match_operand:SI 0 "register_operand" "=r,r")
2113 (lshiftrt:SI
2114 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO,rO"))
2115 (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO")))]
2116 ""
2117 "@
2118 shruxi\t%0, %r1, %2
2119 shrux\t%0, %r1, %r2"
2120 [(set_attr "type" "X01,X01")])
2122 (define_insn "*lshrsi_truncdisi2"
2123 [(set (match_operand:SI 0 "register_operand" "=r")
2124 (lshiftrt:SI
2125 (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))
2126 (truncate:SI (match_operand:DI 2 "reg_or_0_operand" "rO"))))]
2127 ""
2128 "shrux\t%0, %r1, %r2"
2129 [(set_attr "type" "X01")])
2131 (define_insn "*lshrdi_truncdisi"
2132 [(set (match_operand:DI 0 "register_operand" "=r")
2133 (lshiftrt:DI
2134 (match_operand:DI 1 "reg_or_0_operand" "rO")
2135 (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2136 ""
2137 "shru\t%0, %r1, %r2")
2139 (define_insn "*rotldi_truncdisi"
2140 [(set (match_operand:DI 0 "register_operand" "=r")
2141 (rotate:DI
2142 (match_operand:DI 1 "reg_or_0_operand" "rO")
2143 (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2144 ""
2145 "rotl\t%0, %r1, %r2")
2147 ;; Integer to floating point conversions
2149 (define_expand "floatsisf2"
2150 [(set (match_operand:SF 0 "register_operand" "")
2151 (float:SI (match_operand:SI 1 "register_operand" "")))]
2152 ""
2153 {
2154 rtx result = gen_lowpart (DImode, operands[0]);
2155 rtx a = operands[1];
2157 rtx nega = gen_reg_rtx (SImode);
2158 rtx exp = gen_reg_rtx (DImode);
2159 rtx sign = gen_reg_rtx (DImode);
2160 rtx abs = gen_reg_rtx (DImode);
2161 rtx flags = gen_reg_rtx (DImode);
2162 rtx tmp1 = gen_reg_rtx (DImode);
2163 rtx tmp2 = gen_reg_rtx (DImode);
2165 emit_move_insn (exp, GEN_INT (0x9e));
2167 emit_insn (gen_negsi2 (nega, a));
2169 emit_insn (gen_insn_cmplts_sisi (gen_lowpart (SImode, sign), a, const0_rtx));
2170 emit_insn (gen_insn_cmoveqz (abs, gen_lowpart (DImode, nega), sign,
2171 gen_lowpart (DImode, a)));
2173 emit_insn (gen_insn_bfins (tmp1, exp, sign, GEN_INT (10), GEN_INT (10)));
2174 emit_insn (gen_insn_bfins (tmp2, tmp1, abs, GEN_INT (32), GEN_INT (63)));
2175 emit_insn (gen_insn_fsingle_pack1 (flags, tmp2));
2176 emit_insn (gen_insn_fsingle_pack2 (result, tmp2, flags));
2177 DONE;
2178 })
2180 (define_expand "floatunssisf2"
2181 [(set (match_operand:SF 0 "register_operand" "")
2182 (float:SI (match_operand:SI 1 "register_operand" "")))]
2183 ""
2184 {
2185 rtx result = gen_lowpart (DImode, operands[0]);
2186 rtx a = operands[1];
2188 rtx exp = gen_reg_rtx (DImode);
2189 rtx flags = gen_reg_rtx (DImode);
2190 rtx tmp = gen_reg_rtx (DImode);
2192 emit_move_insn (exp, GEN_INT (0x9e));
2193 emit_insn (gen_insn_bfins (tmp, exp, gen_lowpart (DImode, a),
2194 GEN_INT (32), GEN_INT (63)));
2195 emit_insn (gen_insn_fsingle_pack1 (flags, tmp));
2196 emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags));
2197 DONE;
2198 })
2200 (define_expand "floatsidf2"
2201 [(set (match_operand:DF 0 "register_operand" "")
2202 (float:SI (match_operand:SI 1 "register_operand" "")))]
2203 ""
2204 {
2205 rtx result = gen_lowpart (DImode, operands[0]);
2206 rtx a = gen_lowpart (DImode, operands[1]);
2208 rtx nega = gen_reg_rtx (DImode);
2209 rtx exp = gen_reg_rtx (DImode);
2210 rtx sign = gen_reg_rtx (DImode);
2211 rtx abs = gen_reg_rtx (DImode);
2212 rtx tmp1 = gen_reg_rtx (DImode);
2213 rtx tmp2 = gen_reg_rtx (DImode);
2214 rtx tmp3 = gen_reg_rtx (DImode);
2216 emit_move_insn (exp, GEN_INT (0x21b00));
2218 emit_insn (gen_negdi2 (nega, a));
2220 emit_insn (gen_insn_cmplts_didi (sign, a, const0_rtx));
2221 emit_insn (gen_insn_cmovnez (abs, a, sign, nega));
2223 emit_insn (gen_ashldi3 (tmp1, abs, GEN_INT (4)));
2224 emit_insn (gen_insn_bfins (tmp2, exp, sign, GEN_INT (20), GEN_INT (20)));
2225 emit_insn (gen_insn_fdouble_pack1 (tmp3, tmp1, tmp2));
2226 emit_insn (gen_insn_fdouble_pack2 (result, tmp3, tmp1, const0_rtx));
2227 DONE;
2228 })
2230 (define_expand "floatunssidf2"
2231 [(set (match_operand:DF 0 "register_operand" "")
2232 (float:SI (match_operand:SI 1 "register_operand" "")))]
2233 ""
2234 {
2235 rtx result = gen_lowpart (DImode, operands[0]);
2236 rtx a = gen_lowpart (DImode, operands[1]);
2238 rtx exp = gen_reg_rtx (DImode);
2239 rtx tmp1 = gen_reg_rtx (DImode);
2240 rtx tmp2 = gen_reg_rtx (DImode);
2242 emit_move_insn (exp, GEN_INT (0x21b00));
2243 emit_insn (gen_insn_bfins (tmp1, const0_rtx, a, GEN_INT (4), GEN_INT (35)));
2244 emit_insn (gen_insn_fdouble_pack1 (tmp2, tmp1, exp));
2245 emit_insn (gen_insn_fdouble_pack2 (result, tmp2, tmp1, const0_rtx));
2246 DONE;
2247 })
2249 \f
2250 ;;
2251 ;; Multiplies
2252 ;;
2254 (define_insn "mulsi3"
2255 [(set (match_operand:SI 0 "register_operand" "=r")
2256 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rO")
2257 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
2258 ""
2259 "mulx\t%0, %r1, %r2"
2260 [(set_attr "type" "Y0_2cycle")])
2262 (define_insn "mulsidi3"
2263 [(set (match_operand:DI 0 "register_operand" "=r")
2264 (mult:DI (sign_extend:DI
2265 (match_operand:SI 1 "reg_or_0_operand" "%rO"))
2266 (sign_extend:DI
2267 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
2268 ""
2269 "mul_ls_ls\t%0, %r1, %r2"
2270 [(set_attr "type" "Y0_2cycle")])
2272 (define_insn "umulsidi3"
2273 [(set (match_operand:DI 0 "register_operand" "=r")
2274 (mult:DI (zero_extend:DI
2275 (match_operand:SI 1 "reg_or_0_operand" "%rO"))
2276 (zero_extend:DI
2277 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
2278 ""
2279 "mul_lu_lu\t%0, %r1, %r2"
2280 [(set_attr "type" "Y0_2cycle")])
2282 (define_expand "muldi3"
2283 [(set (match_operand:DI 0 "register_operand" "")
2284 (unspec:DI [(match_operand:DI 1 "nonmemory_operand" "")
2285 (match_operand:DI 2 "nonmemory_operand" "")]
2286 UNSPEC_INSN_MUL_HU_LU))
2287 (set (match_dup 0)
2288 (unspec:DI [(match_dup 0) (match_dup 2) (match_dup 1)]
2289 UNSPEC_INSN_MULA_HU_LU))
2290 (set (match_dup 0)
2291 (ashift:DI (match_dup 0) (const_int 32)))
2292 (set (match_dup 0)
2293 (unspec:DI [(match_dup 0) (match_dup 2) (match_dup 1)]
2294 UNSPEC_INSN_MULA_LU_LU))]
2295 ""
2296 {
2297 operands[1] = force_reg (DImode, operands[1]);
2298 operands[1] = make_safe_from (operands[1], operands[0]);
2300 if (tilegx_expand_muldi (operands[0], operands[1], operands[2]))
2301 DONE;
2302 else
2303 {
2304 operands[2] = force_reg (DImode, operands[2]);
2305 operands[2] = make_safe_from (operands[2], operands[0]);
2306 }
2307 })
2309 (define_insn "usmulsidi3"
2310 [(set (match_operand:DI 0 "register_operand" "=r")
2311 (mult:DI (zero_extend:DI
2312 (match_operand:SI 1 "reg_or_0_operand" "rO"))
2313 (sign_extend:DI
2314 (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
2315 ""
2316 "mul_ls_lu\t%0, %r2, %r1"
2317 [(set_attr "type" "X0_2cycle")])
2319 (define_insn "maddsidi4"
2320 [(set (match_operand:DI 0 "register_operand" "=r")
2321 (plus:DI
2322 (mult:DI (sign_extend:DI
2323 (match_operand:SI 1 "reg_or_0_operand" "rO"))
2324 (sign_extend:DI
2325 (match_operand:SI 2 "reg_or_0_operand" "rO")))
2326 (match_operand:DI 3 "register_operand" "0")))]
2327 ""
2328 "mula_ls_ls\t%0, %r1, %r2"
2329 [(set_attr "type" "Y0_2cycle")])
2331 (define_insn "umaddsidi4"
2332 [(set (match_operand:DI 0 "register_operand" "=r")
2333 (plus:DI
2334 (mult:DI (zero_extend:DI
2335 (match_operand:SI 1 "reg_or_0_operand" "rO"))
2336 (zero_extend:DI
2337 (match_operand:SI 2 "reg_or_0_operand" "rO")))
2338 (match_operand:DI 3 "register_operand" "0")))]
2339 ""
2340 "mula_lu_lu\t%0, %r1, %r2"
2341 [(set_attr "type" "Y0_2cycle")])
2343 (define_expand "smulsi3_highpart"
2344 [(set (match_dup 3)
2345 (mult:DI (sign_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))
2346 (sign_extend:DI (match_operand:SI 2 "reg_or_0_operand" ""))))
2347 (set (match_dup 4)
2348 (ashiftrt:DI (match_dup 3) (const_int 32)))
2349 (set (match_operand:SI 0 "register_operand" "")
2350 (truncate:SI (match_dup 4)))]
2351 ""
2352 {
2353 operands[3] = gen_reg_rtx (DImode);
2354 operands[4] = gen_reg_rtx (DImode);
2355 })
2357 (define_expand "umulsi3_highpart"
2358 [(set (match_dup 3)
2359 (mult:DI (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))
2360 (zero_extend:DI (match_operand:SI 2 "reg_or_0_operand" ""))))
2361 (set (match_dup 4)
2362 (lshiftrt:DI (match_dup 3) (const_int 32)))
2363 (set (match_operand:SI 0 "register_operand" "")
2364 (truncate:SI (match_dup 4)))]
2365 ""
2366 {
2367 operands[3] = gen_reg_rtx (DImode);
2368 operands[4] = gen_reg_rtx (DImode);
2369 })
2371 (define_expand "smuldi3_highpart"
2372 [(set (match_operand:DI 0 "register_operand" "")
2373 (truncate:DI
2374 (ashiftrt:TI
2375 (mult:TI (sign_extend:TI (match_operand:DI 1 "reg_or_0_operand" ""))
2376 (sign_extend:TI (match_operand:DI 2 "reg_or_0_operand" "")))
2377 (const_int 64))))]
2378 ""
2379 {
2380 tilegx_expand_smuldi3_highpart (operands[0], operands[1], operands[2]);
2381 DONE;
2382 })
2384 (define_expand "umuldi3_highpart"
2385 [(set (match_operand:DI 0 "register_operand" "")
2386 (truncate:DI
2387 (lshiftrt:TI
2388 (mult:TI (zero_extend:TI (match_operand:DI 1 "reg_or_0_operand" ""))
2389 (zero_extend:TI (match_operand:DI 2 "reg_or_0_operand" "")))
2390 (const_int 64))))]
2391 ""
2392 {
2393 tilegx_expand_umuldi3_highpart (operands[0], operands[1], operands[2]);
2394 DONE;
2395 })
2397 \f
2398 ;;
2399 ;; Divide stubs. These exist to work around a bug in expmed.c, which
2400 ;; will not attempt to convert a divide by constant into a multiply
2401 ;; unless there is a pattern for a divide of the same mode. The end
2402 ;; result is a 32-bit divide turns into 64-bit multiply.
2403 ;;
2405 (define_expand "divsi3"
2406 [(set (match_operand:SI 0 "register_operand" "")
2407 (div:SI (match_operand:SI 1 "reg_or_0_operand" "")
2408 (match_operand:SI 2 "reg_or_0_operand" "")))]
2409 ""
2410 {
2411 FAIL;
2412 })
2414 (define_expand "udivsi3"
2415 [(set (match_operand:SI 0 "register_operand" "")
2416 (udiv:SI (match_operand:SI 1 "reg_or_0_operand" "")
2417 (match_operand:SI 2 "reg_or_0_operand" "")))]
2418 ""
2419 {
2420 FAIL;
2421 })
2423 \f
2424 ;;
2425 ;; Loops
2426 ;;
2428 ;; Define the subtract-one-and-jump insns so loop.c knows what to
2429 ;; generate.
2430 (define_expand "doloop_end"
2431 [(use (match_operand 0 "" "")) ;; loop pseudo
2432 (use (match_operand 1 "" ""))] ;; label
2433 ""
2434 {
2435 if (optimize > 0 && flag_modulo_sched)
2436 {
2437 rtx s0;
2438 rtx bcomp;
2439 rtx loc_ref;
2440 machine_mode mode = GET_MODE (operands[0]);
2442 /* only deal with loop counters in SImode or DImode */
2443 if (mode != SImode && mode != DImode)
2444 FAIL;
2446 s0 = operands [0];
2447 emit_move_insn (s0, gen_rtx_PLUS (mode, s0, GEN_INT (-1)));
2448 bcomp = gen_rtx_NE(mode, s0, const0_rtx);
2449 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
2450 emit_jump_insn (gen_rtx_SET (pc_rtx,
2451 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
2452 loc_ref, pc_rtx)));
2453 DONE;
2454 }
2455 else
2456 FAIL;
2458 })
2460 ;;
2461 ;; Prologue/epilogue
2462 ;;
2463 (define_expand "prologue"
2464 [(const_int 0)]
2465 ""
2466 {
2467 tilegx_expand_prologue ();
2468 DONE;
2469 })
2471 (define_expand "epilogue"
2472 [(const_int 0)]
2473 ""
2474 {
2475 tilegx_expand_epilogue (false);
2476 DONE;
2477 })
2479 (define_expand "sibcall_epilogue"
2480 [(const_int 0)]
2481 ""
2482 {
2483 tilegx_expand_epilogue (true);
2484 DONE;
2485 })
2487 ;;
2488 ;; Stack manipulations
2489 ;;
2491 ;; An insn to allocate new stack space for dynamic use (e.g., alloca).
2492 (define_expand "allocate_stack"
2493 [(set (match_operand 0 "register_operand" "")
2494 (minus (reg 54) (match_operand 1 "nonmemory_operand" "")))
2495 (set (reg 54)
2496 (minus (reg 54) (match_dup 1)))]
2497 ""
2498 "tilegx_allocate_stack (operands[0], operands[1]); DONE;")
2500 ;;
2501 ;; Branches
2502 ;;
2504 (define_expand "call"
2505 [(parallel [(call (match_operand:DI 0 "call_operand" "")
2506 (match_operand 1 "" ""))
2507 (use (reg:DI 54))
2508 (clobber (reg:DI 55))])]
2509 ""
2510 {
2511 rtx orig_addr = XEXP (operands[0], 0);
2512 rtx addr;
2513 if (GET_CODE (orig_addr) == SYMBOL_REF)
2514 {
2515 if (tilegx_cmodel == CM_LARGE)
2516 {
2517 addr = gen_reg_rtx (Pmode);
2518 tilegx_expand_set_const64 (addr, orig_addr);
2519 operands[0] = gen_rtx_MEM (DImode, addr);
2520 }
2521 else if (tilegx_cmodel == CM_LARGE_PIC)
2522 {
2523 crtl->uses_pic_offset_table = 1;
2524 addr = gen_reg_rtx (Pmode);
2525 if (SYMBOL_REF_LOCAL_P (orig_addr))
2526 tilegx_compute_pcrel_address (addr, orig_addr);
2527 else
2528 tilegx_compute_pcrel_plt_address (addr, orig_addr);
2529 operands[0] = gen_rtx_MEM (DImode, addr);
2530 }
2531 }
2532 })
2534 (define_insn "*call_insn"
2535 [(call (mem:DI (match_operand:I48MODE 0 "call_address_operand" "rO,i"))
2536 (match_operand 1 "" ""))
2537 (use (reg:DI 54))
2538 (clobber (reg:DI 55))]
2539 ""
2540 "@
2541 jalr\t%r0
2542 jal\t%p0"
2543 [(set_attr "type" "Y1,X1")])
2545 (define_expand "call_value"
2546 [(parallel [(set (match_operand 0 "register_operand" "")
2547 (call (match_operand:DI 1 "call_operand" "")
2548 (match_operand 2 "" "")))
2549 (use (reg:DI 54))
2550 (clobber (reg:DI 55))])]
2551 ""
2552 {
2553 rtx orig_addr = XEXP (operands[1], 0);
2554 rtx addr;
2555 if (GET_CODE (orig_addr) == SYMBOL_REF)
2556 {
2557 if (tilegx_cmodel == CM_LARGE)
2558 {
2559 addr = gen_reg_rtx (Pmode);
2560 tilegx_expand_set_const64 (addr, orig_addr);
2561 operands[1] = gen_rtx_MEM (DImode, addr);
2562 }
2563 else if (tilegx_cmodel == CM_LARGE_PIC)
2564 {
2565 crtl->uses_pic_offset_table = 1;
2566 addr = gen_reg_rtx (Pmode);
2567 if (SYMBOL_REF_LOCAL_P (orig_addr))
2568 tilegx_compute_pcrel_address (addr, orig_addr);
2569 else
2570 tilegx_compute_pcrel_plt_address (addr, orig_addr);
2571 operands[1] = gen_rtx_MEM (DImode, addr);
2572 }
2573 }
2574 })
2576 (define_insn "*call_value_insn"
2577 [(set (match_operand 0 "register_operand" "=r,r")
2578 (call (mem:DI (match_operand:I48MODE 1 "call_address_operand" "rO,i"))
2579 (match_operand 2 "" "")))
2580 (use (reg:DI 54))
2581 (clobber (reg:DI 55))]
2582 ""
2583 "@
2584 jalr\t%r1
2585 jal\t%p1"
2586 [(set_attr "type" "Y1,X1")])
2588 (define_expand "sibcall"
2589 [(parallel [(call (match_operand:DI 0 "call_operand" "")
2590 (match_operand 1 "" ""))
2591 (use (reg:DI 54))])]
2592 ""
2593 "")
2595 (define_insn "*sibcall_insn"
2596 [(call (mem:DI (match_operand:I48MODE 0 "call_address_operand" "rO,i"))
2597 (match_operand 1 "" ""))
2598 (use (reg:DI 54))]
2599 "SIBLING_CALL_P(insn)"
2600 "@
2601 jr\t%r0
2602 j\t%p0"
2603 [(set_attr "type" "Y1,X1")])
2605 (define_expand "sibcall_value"
2606 [(parallel [(set (match_operand 0 "" "")
2607 (call (match_operand:DI 1 "call_operand" "")
2608 (match_operand 2 "" "")))
2609 (use (reg:DI 54))])]
2610 ""
2611 "")
2613 (define_insn "*sibcall_value"
2614 [(set (match_operand 0 "" "")
2615 (call (mem:DI (match_operand:I48MODE 1 "call_address_operand" "rO,i"))
2616 (match_operand 2 "" "")))
2617 (use (reg:DI 54))]
2618 "SIBLING_CALL_P(insn)"
2619 "@
2620 jr\t%r1
2621 j\t%p1"
2622 [(set_attr "type" "Y1,X1")])
2624 (define_insn "jump"
2625 [(set (pc) (label_ref (match_operand 0 "" "")))]
2626 ""
2627 "j\t%l0"
2628 [(set_attr "type" "X1")])
2630 (define_insn "indirect_jump"
2631 [(set (pc) (match_operand 0 "pointer_operand" "rO"))]
2632 ""
2633 "jr\t%r0"
2634 [(set_attr "type" "Y1")])
2636 (define_expand "return"
2637 [(parallel
2638 [(return)
2639 (use (reg:DI 55))])]
2640 "tilegx_can_use_return_insn_p ()"
2641 "")
2643 (define_insn "_return"
2644 [(return)
2645 (use (reg:DI 55))]
2646 "reload_completed"
2647 "jrp\tlr"
2648 [(set_attr "type" "Y1")])
2650 (define_expand "tablejump"
2651 [(set (pc) (match_operand 0 "pointer_operand" ""))
2652 (use (label_ref (match_operand 1 "" "")))]
2653 ""
2654 {
2655 tilegx_expand_tablejump (operands[0], operands[1]);
2656 DONE;
2657 })
2659 (define_insn "tablejump_aux"
2660 [(set (pc) (match_operand 0 "pointer_operand" "rO"))
2661 (use (label_ref (match_operand 1 "" "")))]
2662 ""
2663 "jr\t%r0"
2664 [(set_attr "type" "Y1")])
2666 ;; Call subroutine returning any type.
2667 (define_expand "untyped_call"
2668 [(parallel [(call (match_operand 0 "" "")
2669 (const_int 0))
2670 (match_operand 1 "" "")
2671 (match_operand 2 "" "")])]
2672 ""
2673 {
2674 int i;
2676 emit_call_insn (gen_call (operands[0], const0_rtx));
2678 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2679 {
2680 rtx set = XVECEXP (operands[2], 0, i);
2681 emit_move_insn (SET_DEST (set), SET_SRC (set));
2682 }
2684 /* The optimizer does not know that the call sets the function value
2685 registers we stored in the result block. We avoid problems by
2686 claiming that all hard registers are used and clobbered at this
2687 point. */
2688 emit_insn (gen_blockage ());
2690 DONE;
2691 })
2693 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers
2694 ;; and all of memory. This blocks insns from being moved across this
2695 ;; point.
2696 (define_insn "blockage"
2697 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
2698 ""
2699 "pseudo"
2700 [(set_attr "type" "nothing")
2701 (set_attr "length" "0")])
2703 ;; Internal expanders to prevent memory ops from moving around frame
2704 ;; allocation/deallocation.
2705 ;;
2706 ;; TODO: really this clobber should just clobber the frame memory. Is
2707 ;; this possibly by clobbering memory @ the sp reg (as alpha does?)
2708 ;; or by explicitly setting the alias set to the frame?
2709 (define_insn "sp_adjust"
2710 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
2711 (plus:DI
2712 (match_operand:DI 1 "register_operand" "%r,r,r")
2713 (match_operand:DI 2 "add_operand" "r,I,JT")))
2714 (clobber (mem:BLK (scratch)))]
2715 ""
2716 "@
2717 add\t%0, %1, %2
2718 addi\t%0, %1, %2
2719 addli\t%0, %1, %H2"
2720 [(set_attr "type" "*,*,X01")])
2722 (define_insn "sp_adjust_32bit"
2723 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2724 (plus:SI
2725 (match_operand:SI 1 "register_operand" "%r,r,r")
2726 (match_operand:SI 2 "add_operand" "r,I,JT")))
2727 (clobber (mem:BLK (scratch)))]
2728 ""
2729 "@
2730 addx\t%0, %1, %2
2731 addxi\t%0, %1, %2
2732 addxli\t%0, %1, %H2"
2733 [(set_attr "type" "*,*,X01")])
2735 ;; Used for move sp, r52, to pop a stack frame. We need to make sure
2736 ;; that stack frame memory operations have been issued before we do
2737 ;; this. TODO: see above TODO.
2738 (define_insn "sp_restore<bitsuffix>"
2739 [(set (match_operand:I48MODE 0 "register_operand" "=r")
2740 (match_operand:I48MODE 1 "register_operand" "r"))
2741 (clobber (mem:BLK (scratch)))]
2742 ""
2743 "move\t%0, %1")
2745 (define_insn "nop"
2746 [(const_int 0)]
2747 ""
2748 "nop"
2749 [(set_attr "type" "Y01")])
2751 \f
2752 ;;
2753 ;; Conditional branches
2754 ;;
2756 (define_expand "cbranch<mode>4"
2757 [(set (pc)
2758 (if_then_else (match_operator 0 "ordered_comparison_operator"
2759 [(match_operand:FI48MODE 1 "reg_or_cint_operand")
2760 (match_operand:FI48MODE 2 "reg_or_cint_operand")])
2761 (label_ref (match_operand 3 ""))
2762 (pc)))]
2763 ""
2764 {
2765 tilegx_emit_conditional_branch (operands, GET_MODE (operands[1]));
2766 DONE;
2767 })
2769 (define_insn "*bcc_normal<mode>"
2770 [(set (pc)
2771 (if_then_else
2772 (match_operator 1 "signed_comparison_operator"
2773 [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")
2774 (const_int 0)])
2775 (label_ref (match_operand 0 "" ""))
2776 (pc)))]
2777 ""
2778 { return tilegx_output_cbranch (insn, operands, false); }
2779 [(set_attr "type" "X1_branch")])
2781 (define_insn "*bcc_reverse<mode>"
2782 [(set (pc)
2783 (if_then_else
2784 (match_operator 1 "signed_comparison_operator"
2785 [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")
2786 (const_int 0)])
2787 (pc)
2788 (label_ref (match_operand 0 "" ""))))]
2789 ""
2790 { return tilegx_output_cbranch (insn, operands, true); }
2791 [(set_attr "type" "X1_branch")])
2793 (define_insn "*blbs_normal<mode>"
2794 [(set (pc)
2795 (if_then_else
2796 (ne (zero_extract:I48MODE
2797 (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
2798 (const_int 1)
2799 (const_int 0))
2800 (const_int 0))
2801 (label_ref (match_operand 0 "" ""))
2802 (pc)))]
2803 ""
2804 { return tilegx_output_cbranch_with_opcode (insn, operands, "blbs", "blbc",
2805 1); }
2806 [(set_attr "type" "X1_branch")])
2808 (define_insn "*blbc_normal<mode>"
2809 [(set (pc)
2810 (if_then_else
2811 (eq (zero_extract:I48MODE
2812 (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
2813 (const_int 1)
2814 (const_int 0))
2815 (const_int 0))
2816 (label_ref (match_operand 0 "" ""))
2817 (pc)))]
2818 ""
2819 { return tilegx_output_cbranch_with_opcode (insn, operands, "blbc", "blbs",
2820 1); }
2821 [(set_attr "type" "X1_branch")])
2823 ;; Note that __insn_mf() expands to this.
2824 (define_expand "memory_barrier"
2825 [(set (match_dup 0)
2826 (unspec_volatile:BLK [(match_dup 0)] UNSPEC_MF))]
2827 ""
2828 {
2829 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
2830 MEM_VOLATILE_P (operands[0]) = 1;
2831 })
2833 (define_insn "*memory_barrier"
2834 [(set (match_operand:BLK 0 "" "")
2835 (unspec_volatile:BLK [(match_dup 0)] UNSPEC_MF))]
2836 ""
2837 "mf"
2838 [(set_attr "type" "X1")])
2840 (define_insn "prefetch"
2841 [(prefetch (match_operand 0 "address_operand" "rO")
2842 (match_operand 1 "const_int_operand" "")
2843 (match_operand 2 "const_int_operand" ""))]
2844 ""
2845 {
2846 switch (INTVAL (operands[2]))
2847 {
2848 case 0:
2849 case 1: return "prefetch_l3\t%r0";
2850 case 2: return "prefetch_l2\t%r0";
2851 case 3: return "prefetch_l1\t%r0";
2852 default: gcc_unreachable ();
2853 }
2854 }
2855 [(set_attr "type" "Y2")])
2857 \f
2858 ;;
2859 ;; "__insn" Intrinsics (some expand directly to normal patterns above).
2860 ;;
2862 (define_insn "insn_bfexts"
2863 [(set (match_operand:DI 0 "register_operand" "=r")
2864 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2865 (match_operand:DI 2 "u6bit_cint_operand" "n")
2866 (match_operand:DI 3 "u6bit_cint_operand" "n")]
2867 UNSPEC_INSN_BFEXTS))]
2868 ""
2869 "bfexts\t%0, %r1, %2, %3"
2870 [(set_attr "type" "X0")])
2872 (define_insn "insn_bfextu"
2873 [(set (match_operand:DI 0 "register_operand" "=r")
2874 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2875 (match_operand:DI 2 "u6bit_cint_operand" "n")
2876 (match_operand:DI 3 "u6bit_cint_operand" "n")]
2877 UNSPEC_INSN_BFEXTU))]
2878 ""
2879 "bfextu\t%0, %r1, %2, %3"
2880 [(set_attr "type" "X0")])
2882 (define_insn "insn_bfins"
2883 [(set (match_operand:DI 0 "register_operand" "=r")
2884 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2885 (match_operand:DI 2 "reg_or_0_operand" "rO")
2886 (match_operand:DI 3 "u6bit_cint_operand" "n")
2887 (match_operand:DI 4 "u6bit_cint_operand" "n")]
2888 UNSPEC_INSN_BFINS))]
2889 ""
2890 "bfins\t%0, %r2, %3, %4"
2891 [(set_attr "type" "X0")])
2893 (define_insn "insn_cmpexch<four_if_si>"
2894 [(set (match_operand:I48MODE 0 "register_operand" "=r")
2895 (mem:I48MODE (match_operand 1 "pointer_operand" "rO")))
2896 (set (mem:I48MODE (match_dup 1))
2897 (unspec_volatile:I48MODE
2898 [(mem:I48MODE (match_dup 1))
2899 (reg:I48MODE TILEGX_CMPEXCH_REG)
2900 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")]
2901 UNSPEC_INSN_CMPEXCH))]
2902 ""
2903 "cmpexch<four_if_si>\t%0, %r1, %r2"
2904 [(set_attr "type" "X1_remote")])
2906 (define_insn "insn_cmul"
2907 [(set (match_operand:DI 0 "register_operand" "=r")
2908 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2909 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2910 UNSPEC_INSN_CMUL))]
2911 ""
2912 "cmul\t%0, %r1, %r2"
2913 [(set_attr "type" "X0_2cycle")])
2915 (define_insn "insn_cmula"
2916 [(set (match_operand:DI 0 "register_operand" "=r")
2917 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2918 (match_operand:DI 2 "reg_or_0_operand" "rO")
2919 (match_operand:DI 3 "reg_or_0_operand" "rO")]
2920 UNSPEC_INSN_CMULA))]
2921 ""
2922 "cmula\t%0, %r2, %r3"
2923 [(set_attr "type" "X0_2cycle")])
2925 (define_insn "insn_cmulaf"
2926 [(set (match_operand:DI 0 "register_operand" "=r")
2927 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2928 (match_operand:DI 2 "reg_or_0_operand" "rO")
2929 (match_operand:DI 3 "reg_or_0_operand" "rO")]
2930 UNSPEC_INSN_CMULAF))]
2931 ""
2932 "cmulaf\t%0, %r2, %r3"
2933 [(set_attr "type" "X0_2cycle")])
2935 (define_insn "insn_cmulf"
2936 [(set (match_operand:DI 0 "register_operand" "=r")
2937 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2938 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2939 UNSPEC_INSN_CMULF))]
2940 ""
2941 "cmulf\t%0, %r1, %r2"
2942 [(set_attr "type" "X0_2cycle")])
2944 (define_insn "insn_cmulfr"
2945 [(set (match_operand:DI 0 "register_operand" "=r")
2946 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2947 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2948 UNSPEC_INSN_CMULFR))]
2949 ""
2950 "cmulfr\t%0, %r1, %r2"
2951 [(set_attr "type" "X0_2cycle")])
2953 (define_insn "insn_cmulh"
2954 [(set (match_operand:DI 0 "register_operand" "=r")
2955 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2956 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2957 UNSPEC_INSN_CMULH))]
2958 ""
2959 "cmulh\t%0, %r1, %r2"
2960 [(set_attr "type" "X0_2cycle")])
2962 (define_insn "insn_cmulhr"
2963 [(set (match_operand:DI 0 "register_operand" "=r")
2964 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2965 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2966 UNSPEC_INSN_CMULHR))]
2967 ""
2968 "cmulhr\t%0, %r1, %r2"
2969 [(set_attr "type" "X0_2cycle")])
2971 (define_insn "insn_crc32_32"
2972 [(set (match_operand:DI 0 "register_operand" "=r")
2973 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2974 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2975 UNSPEC_INSN_CRC32_32))]
2976 ""
2977 "crc32_32\t%0, %r1, %r2"
2978 [(set_attr "type" "X0")])
2980 (define_insn "insn_crc32_8"
2981 [(set (match_operand:DI 0 "register_operand" "=r")
2982 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2983 (match_operand:DI 2 "reg_or_0_operand" "rO")]
2984 UNSPEC_INSN_CRC32_8))]
2985 ""
2986 "crc32_8\t%0, %r1, %r2"
2987 [(set_attr "type" "X0")])
2989 (define_insn "insn_dblalign"
2990 [(set (match_operand:DI 0 "register_operand" "=r")
2991 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2992 (match_operand:DI 2 "reg_or_0_operand" "rO")
2993 (match_operand 3 "pointer_operand" "rO")]
2994 UNSPEC_INSN_DBLALIGN))]
2995 ""
2996 "dblalign\t%0, %r2, %r3"
2997 [(set_attr "type" "X0")])
2999 (define_insn "insn_dblalign2"
3000 [(set (match_operand:DI 0 "register_operand" "=r")
3001 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3002 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3003 UNSPEC_INSN_DBLALIGN2))]
3004 ""
3005 "dblalign2\t%0, %r1, %r2"
3006 [(set_attr "type" "X01")])
3008 (define_insn "insn_dblalign4"
3009 [(set (match_operand:DI 0 "register_operand" "=r")
3010 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3011 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3012 UNSPEC_INSN_DBLALIGN4))]
3013 ""
3014 "dblalign4\t%0, %r1, %r2"
3015 [(set_attr "type" "X01")])
3017 (define_insn "insn_dblalign6"
3018 [(set (match_operand:DI 0 "register_operand" "=r")
3019 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3020 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3021 UNSPEC_INSN_DBLALIGN6))]
3022 ""
3023 "dblalign6\t%0, %r1, %r2"
3024 [(set_attr "type" "X01")])
3026 (define_insn "insn_dtlbpr"
3027 [(unspec_volatile:VOID [(match_operand:DI 0 "reg_or_0_operand" "rO")]
3028 UNSPEC_INSN_DTLBPR)]
3029 ""
3030 "dtlbpr\t%r0"
3031 [(set_attr "type" "X1")])
3033 (define_insn "insn_exch<four_if_si>"
3034 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3035 (mem:I48MODE (match_operand 1 "pointer_operand" "rO")))
3036 (set (mem:I48MODE (match_dup 1))
3037 (unspec_volatile:I48MODE
3038 [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")]
3039 UNSPEC_INSN_EXCH))]
3040 ""
3041 "exch<four_if_si>\t%0, %r1, %r2"
3042 [(set_attr "type" "X1_remote")])
3044 (define_insn "insn_fdouble_add_flags"
3045 [(set (match_operand:DI 0 "register_operand" "=r")
3046 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3047 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3048 UNSPEC_INSN_FDOUBLE_ADD_FLAGS))]
3049 ""
3050 "fdouble_add_flags\t%0, %r1, %r2"
3051 [(set_attr "type" "X0_2cycle")])
3053 (define_insn "insn_fdouble_addsub"
3054 [(set (match_operand:DI 0 "register_operand" "=r")
3055 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3056 (match_operand:DI 2 "reg_or_0_operand" "rO")
3057 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3058 UNSPEC_INSN_FDOUBLE_ADDSUB))]
3059 ""
3060 "fdouble_addsub\t%0, %r2, %r3"
3061 [(set_attr "type" "X0_2cycle")])
3063 (define_insn "insn_fdouble_mul_flags"
3064 [(set (match_operand:DI 0 "register_operand" "=r")
3065 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3066 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3067 UNSPEC_INSN_FDOUBLE_MUL_FLAGS))]
3068 ""
3069 "fdouble_mul_flags\t%0, %r1, %r2"
3070 [(set_attr "type" "X0_2cycle")])
3072 (define_insn "insn_fdouble_pack1"
3073 [(set (match_operand:DI 0 "register_operand" "=r")
3074 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3075 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3076 UNSPEC_INSN_FDOUBLE_PACK1))]
3077 ""
3078 "fdouble_pack1\t%0, %r1, %r2"
3079 [(set_attr "type" "X0_2cycle")])
3081 (define_insn "insn_fdouble_pack2"
3082 [(set (match_operand:DI 0 "register_operand" "=r")
3083 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3084 (match_operand:DI 2 "reg_or_0_operand" "rO")
3085 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3086 UNSPEC_INSN_FDOUBLE_PACK2))]
3087 ""
3088 "fdouble_pack2\t%0, %r2, %r3"
3089 [(set_attr "type" "X0_2cycle")])
3091 (define_insn "insn_fdouble_sub_flags"
3092 [(set (match_operand:DI 0 "register_operand" "=r")
3093 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3094 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3095 UNSPEC_INSN_FDOUBLE_SUB_FLAGS))]
3096 ""
3097 "fdouble_sub_flags\t%0, %r1, %r2"
3098 [(set_attr "type" "X0_2cycle")])
3100 (define_insn "insn_fdouble_unpack_max"
3101 [(set (match_operand:DI 0 "register_operand" "=r")
3102 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3103 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3104 UNSPEC_INSN_FDOUBLE_UNPACK_MAX))]
3105 ""
3106 "fdouble_unpack_max\t%0, %r1, %r2"
3107 [(set_attr "type" "X0_2cycle")])
3109 (define_insn "insn_fdouble_unpack_min"
3110 [(set (match_operand:DI 0 "register_operand" "=r")
3111 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3112 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3113 UNSPEC_INSN_FDOUBLE_UNPACK_MIN))]
3114 ""
3115 "fdouble_unpack_min\t%0, %r1, %r2"
3116 [(set_attr "type" "X0_2cycle")])
3118 (define_insn "insn_fetchadd<four_if_si>"
3119 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3120 (unspec_volatile:I48MODE
3121 [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
3122 UNSPEC_ATOMIC))
3123 (set (mem:I48MODE (match_dup 1))
3124 (plus:I48MODE (mem:I48MODE (match_dup 1))
3125 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
3126 ""
3127 "fetchadd<four_if_si>\t%0, %r1, %r2"
3128 [(set_attr "type" "X1_remote")])
3130 (define_insn "insn_fetchaddgez<four_if_si>"
3131 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3132 (unspec_volatile:I48MODE
3133 [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
3134 UNSPEC_ATOMIC))
3135 (set (mem:I48MODE (match_dup 1))
3136 (unspec:I48MODE [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")
3137 (mem:I48MODE (match_dup 1))]
3138 UNSPEC_INSN_FETCHADDGEZ))]
3139 ""
3140 "fetchaddgez<four_if_si>\t%0, %r1, %r2"
3141 [(set_attr "type" "X1_remote")])
3143 (define_insn "insn_fetchand<four_if_si>"
3144 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3145 (unspec_volatile:I48MODE
3146 [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
3147 UNSPEC_ATOMIC))
3148 (set (mem:I48MODE (match_dup 1))
3149 (and:I48MODE (mem:I48MODE (match_dup 1))
3150 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
3151 ""
3152 "fetchand<four_if_si>\t%0, %r1, %r2"
3153 [(set_attr "type" "X1_remote")])
3155 (define_insn "insn_fetchor<four_if_si>"
3156 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3157 (unspec_volatile:I48MODE
3158 [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
3159 UNSPEC_ATOMIC))
3160 (set (mem:I48MODE (match_dup 1))
3161 (ior:I48MODE (mem:I48MODE (match_dup 1))
3162 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
3163 ""
3164 "fetchor<four_if_si>\t%0, %r1, %r2"
3165 [(set_attr "type" "X1_remote")])
3167 (define_insn "insn_finv"
3168 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3169 UNSPEC_INSN_FINV)]
3170 ""
3171 "finv\t%r0"
3172 [(set_attr "type" "X1")])
3174 (define_insn "insn_flush"
3175 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3176 UNSPEC_INSN_FLUSH)]
3177 ""
3178 "flush\t%r0"
3179 [(set_attr "type" "X1")])
3181 (define_insn "insn_flushwb"
3182 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_FLUSHWB)]
3183 ""
3184 "flushwb"
3185 [(set_attr "type" "X1")])
3187 (define_insn "insn_fnop"
3188 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_FNOP)]
3189 ""
3190 "fnop")
3192 (define_insn "insn_fsingle_add1"
3193 [(set (match_operand:DI 0 "register_operand" "=r")
3194 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3195 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3196 UNSPEC_INSN_FSINGLE_ADD1))]
3197 ""
3198 "fsingle_add1\t%0, %r1, %r2"
3199 [(set_attr "type" "X0")])
3201 (define_insn "insn_fsingle_addsub2"
3202 [(set (match_operand:DI 0 "register_operand" "=r")
3203 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3204 (match_operand:DI 2 "reg_or_0_operand" "rO")
3205 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3206 UNSPEC_INSN_FSINGLE_ADDSUB2))]
3207 ""
3208 "fsingle_addsub2\t%0, %r2, %r3"
3209 [(set_attr "type" "X0_2cycle")])
3211 (define_insn "insn_fsingle_mul1"
3212 [(set (match_operand:DI 0 "register_operand" "=r")
3213 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3214 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3215 UNSPEC_INSN_FSINGLE_MUL1))]
3216 ""
3217 "fsingle_mul1\t%0, %r1, %r2"
3218 [(set_attr "type" "X0")])
3220 (define_insn "insn_fsingle_mul2"
3221 [(set (match_operand:DI 0 "register_operand" "=r")
3222 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3223 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3224 UNSPEC_INSN_FSINGLE_MUL2))]
3225 ""
3226 "fsingle_mul2\t%0, %r1, %r2"
3227 [(set_attr "type" "X0_2cycle")])
3229 (define_insn "insn_fsingle_pack1"
3230 [(set (match_operand:DI 0 "register_operand" "=r")
3231 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")]
3232 UNSPEC_INSN_FSINGLE_PACK1))]
3233 ""
3234 "fsingle_pack1\t%0, %r1"
3235 [(set_attr "type" "Y0_2cycle")])
3237 (define_insn "insn_fsingle_pack2"
3238 [(set (match_operand:DI 0 "register_operand" "=r")
3239 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3240 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3241 UNSPEC_INSN_FSINGLE_PACK2))]
3242 ""
3243 "fsingle_pack2\t%0, %r1, %r2"
3244 [(set_attr "type" "X0_2cycle")])
3246 (define_insn "insn_fsingle_sub1"
3247 [(set (match_operand:DI 0 "register_operand" "=r")
3248 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3249 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3250 UNSPEC_INSN_FSINGLE_SUB1))]
3251 ""
3252 "fsingle_sub1\t%0, %r1, %r2"
3253 [(set_attr "type" "X0")])
3255 (define_insn "insn_drain"
3256 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_DRAIN)]
3257 ""
3258 "drain"
3259 [(set_attr "type" "cannot_bundle")])
3261 (define_insn "insn_icoh"
3262 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3263 UNSPEC_INSN_ICOH)]
3264 ""
3265 "icoh\t%r0"
3266 [(set_attr "type" "X1")])
3268 (define_insn "insn_ill"
3269 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_ILL)]
3270 ""
3271 "ill"
3272 [(set_attr "type" "cannot_bundle")])
3274 (define_insn "insn_info"
3275 [(unspec_volatile:VOID [(match_operand:DI 0 "s8bit_cint_operand" "i")]
3276 UNSPEC_INSN_INFO)]
3277 ""
3278 "info\t%0")
3280 (define_insn "insn_infol"
3281 [(unspec_volatile:VOID [(match_operand:DI 0 "s16bit_cint_operand" "i")]
3282 UNSPEC_INSN_INFOL)]
3283 ""
3284 "infol\t%0"
3285 [(set_attr "type" "X01")])
3287 (define_insn "insn_inv"
3288 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3289 UNSPEC_INSN_INV)]
3290 ""
3291 "inv\t%r0"
3292 [(set_attr "type" "X1")])
3294 ;; loads
3296 (define_expand "insn_ld"
3297 [(set (match_operand:DI 0 "register_operand" "")
3298 (mem:DI (match_operand 1 "pointer_operand" "")))]
3299 "")
3301 (define_insn "insn_ld_add<bitsuffix>"
3302 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3303 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3304 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3305 (set (match_operand:DI 0 "register_operand" "=r")
3306 (mem:DI (match_dup 3)))]
3307 ""
3308 "ld_add\t%0, %1, %2"
3309 [(set_attr "type" "X1_2cycle")])
3311 (define_insn "insn_ldna"
3312 [(set (match_operand:DI 0 "register_operand" "=r")
3313 (mem:DI (and:DI (match_operand 1 "pointer_operand" "rO")
3314 (const_int -8))))]
3315 ""
3316 "ldna\t%0, %r1"
3317 [(set_attr "type" "X1_2cycle")])
3319 (define_insn "insn_ldna_add<bitsuffix>"
3320 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3321 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3322 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3323 (set (match_operand:DI 0 "register_operand" "=r")
3324 (mem:DI (and:DI (match_dup 3) (const_int -8))))]
3325 ""
3326 "ldna_add\t%0, %1, %2"
3327 [(set_attr "type" "X1_2cycle")])
3329 (define_expand "insn_ld<n><s>"
3330 [(set (match_operand:DI 0 "register_operand" "")
3331 (any_extend:DI
3332 (mem:I124MODE (match_operand 1 "pointer_operand" ""))))]
3333 "")
3335 (define_insn "insn_ld<I124MODE:n><s>_add<I48MODE:bitsuffix>"
3336 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3337 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3338 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3339 (set (match_operand:DI 0 "register_operand" "=r")
3340 (any_extend:DI (mem:I124MODE (match_dup 3))))]
3341 ""
3342 "ld<I124MODE:n><s>_add\t%0, %1, %2"
3343 [(set_attr "type" "X1_2cycle")])
3345 ;; non temporal loads
3347 (define_insn "insn_ldnt"
3348 [(set (match_operand:DI 0 "register_operand" "=r")
3349 (unspec:DI [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3350 UNSPEC_NON_TEMPORAL))]
3351 ""
3352 "ldnt\t%0, %r1"
3353 [(set_attr "type" "X1_2cycle")])
3355 (define_insn "insn_ldnt_add<bitsuffix>"
3356 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3357 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3358 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3359 (set (match_operand:DI 0 "register_operand" "=r")
3360 (unspec:DI [(mem:DI (match_dup 3))]
3361 UNSPEC_NON_TEMPORAL))]
3362 ""
3363 "ldnt_add\t%0, %1, %2"
3364 [(set_attr "type" "X1_2cycle")])
3366 (define_insn "insn_ldnt<n><s>"
3367 [(set (match_operand:DI 0 "register_operand" "=r")
3368 (any_extend:DI
3369 (unspec:I124MODE
3370 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3371 UNSPEC_NON_TEMPORAL)))]
3372 ""
3373 "ldnt<n><s>\t%0, %r1"
3374 [(set_attr "type" "X1_2cycle")])
3376 (define_insn "insn_ldnt<I124MODE:n><s>_add<I48MODE:bitsuffix>"
3377 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3378 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3379 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3380 (set (match_operand:DI 0 "register_operand" "=r")
3381 (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))]
3382 UNSPEC_NON_TEMPORAL)))]
3383 ""
3384 "ldnt<I124MODE:n><s>_add\t%0, %1, %2"
3385 [(set_attr "type" "X1_2cycle")])
3387 ;; L2 hits
3389 (define_insn "insn_ld_L2"
3390 [(set (match_operand:DI 0 "register_operand" "=r")
3391 (unspec:DI [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3392 UNSPEC_LATENCY_L2))]
3393 ""
3394 "ld\t%0, %r1"
3395 [(set_attr "type" "Y2_L2")])
3397 (define_insn "insn_ld_add_L2<bitsuffix>"
3398 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3399 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3400 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3401 (set (match_operand:DI 0 "register_operand" "=r")
3402 (unspec:DI [(mem:DI (match_dup 3))]
3403 UNSPEC_LATENCY_L2))]
3404 ""
3405 "ld_add\t%0, %1, %2"
3406 [(set_attr "type" "X1_L2")])
3408 (define_insn "insn_ldna_L2"
3409 [(set (match_operand:DI 0 "register_operand" "=r")
3410 (unspec:DI [(mem:DI (and:DI (match_operand 1 "pointer_operand" "rO")
3411 (const_int -8)))]
3412 UNSPEC_LATENCY_L2))]
3413 ""
3414 "ldna\t%0, %r1"
3415 [(set_attr "type" "X1_L2")])
3417 (define_insn "insn_ldna_add_L2<bitsuffix>"
3418 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3419 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3420 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3421 (set (match_operand:DI 0 "register_operand" "=r")
3422 (unspec:DI [(mem:DI (and:DI (match_dup 3) (const_int -8)))]
3423 UNSPEC_LATENCY_L2))]
3424 ""
3425 "ldna_add\t%0, %1, %2"
3426 [(set_attr "type" "X1_L2")])
3428 (define_insn "insn_ld<n><s>_L2"
3429 [(set (match_operand:DI 0 "register_operand" "=r")
3430 (any_extend:DI
3431 (unspec:I124MODE
3432 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3433 UNSPEC_LATENCY_L2)))]
3434 ""
3435 "ld<n><s>\t%0, %r1"
3436 [(set_attr "type" "Y2_L2")])
3438 (define_insn "insn_ld<I124MODE:n><s>_add_L2<I48MODE:bitsuffix>"
3439 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3440 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3441 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3442 (set (match_operand:DI 0 "register_operand" "=r")
3443 (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))]
3444 UNSPEC_LATENCY_L2)))]
3445 ""
3446 "ld<I124MODE:n><s>_add\t%0, %1, %2"
3447 [(set_attr "type" "X1_L2")])
3449 ;; L2 hits, non temporal loads
3451 (define_insn "insn_ldnt_L2"
3452 [(set (match_operand:DI 0 "register_operand" "=r")
3453 (unspec:DI [(unspec:DI
3454 [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3455 UNSPEC_NON_TEMPORAL)]
3456 UNSPEC_LATENCY_L2))]
3457 ""
3458 "ldnt\t%0, %r1"
3459 [(set_attr "type" "X1_L2")])
3461 (define_insn "insn_ldnt_add_L2<bitsuffix>"
3462 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3463 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3464 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3465 (set (match_operand:DI 0 "register_operand" "=r")
3466 (unspec:DI [(unspec:DI
3467 [(mem:DI (match_dup 3))]
3468 UNSPEC_NON_TEMPORAL)]
3469 UNSPEC_LATENCY_L2))]
3470 ""
3471 "ldnt_add\t%0, %1, %2"
3472 [(set_attr "type" "X1_L2")])
3474 (define_insn "insn_ldnt<n><s>_L2"
3475 [(set (match_operand:DI 0 "register_operand" "=r")
3476 (any_extend:DI
3477 (unspec:I124MODE
3478 [(unspec:I124MODE
3479 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3480 UNSPEC_NON_TEMPORAL)]
3481 UNSPEC_LATENCY_L2)))]
3482 ""
3483 "ldnt<n><s>\t%0, %r1"
3484 [(set_attr "type" "X1_L2")])
3486 (define_insn "insn_ldnt<I124MODE:n><s>_add_L2<I48MODE:bitsuffix>"
3487 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3488 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3489 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3490 (set (match_operand:DI 0 "register_operand" "=r")
3491 (any_extend:DI
3492 (unspec:I124MODE [(unspec:I124MODE
3493 [(mem:I124MODE (match_dup 3))]
3494 UNSPEC_NON_TEMPORAL)]
3495 UNSPEC_LATENCY_L2)))]
3496 ""
3497 "ldnt<I124MODE:n><s>_add\t%0, %1, %2"
3498 [(set_attr "type" "X1_L2")])
3500 ;; L2 miss
3502 (define_insn "insn_ld_miss"
3503 [(set (match_operand:DI 0 "register_operand" "=r")
3504 (unspec:DI [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3505 UNSPEC_LATENCY_MISS))]
3506 ""
3507 "ld\t%0, %r1"
3508 [(set_attr "type" "Y2_miss")])
3510 (define_insn "insn_ld_add_miss<bitsuffix>"
3511 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3512 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3513 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3514 (set (match_operand:DI 0 "register_operand" "=r")
3515 (unspec:DI [(mem:DI (match_dup 3))]
3516 UNSPEC_LATENCY_MISS))]
3517 ""
3518 "ld_add\t%0, %1, %2"
3519 [(set_attr "type" "X1_miss")])
3521 (define_insn "insn_ldna_miss"
3522 [(set (match_operand:DI 0 "register_operand" "=r")
3523 (unspec:DI [(mem:DI (and:DI (match_operand 1 "pointer_operand" "rO")
3524 (const_int -8)))]
3525 UNSPEC_LATENCY_MISS))]
3526 ""
3527 "ldna\t%0, %r1"
3528 [(set_attr "type" "X1_miss")])
3530 (define_insn "insn_ldna_add_miss<bitsuffix>"
3531 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3532 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3533 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3534 (set (match_operand:DI 0 "register_operand" "=r")
3535 (unspec:DI [(mem:DI (and:DI (match_dup 3) (const_int -8)))]
3536 UNSPEC_LATENCY_MISS))]
3537 ""
3538 "ldna_add\t%0, %1, %2"
3539 [(set_attr "type" "X1_miss")])
3541 (define_insn "insn_ld<n><s>_miss"
3542 [(set (match_operand:DI 0 "register_operand" "=r")
3543 (any_extend:DI
3544 (unspec:I124MODE
3545 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3546 UNSPEC_LATENCY_MISS)))]
3547 ""
3548 "ld<n><s>\t%0, %r1"
3549 [(set_attr "type" "Y2_miss")])
3551 (define_insn "insn_ld<I124MODE:n><s>_add_miss<I48MODE:bitsuffix>"
3552 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3553 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3554 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3555 (set (match_operand:DI 0 "register_operand" "=r")
3556 (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))]
3557 UNSPEC_LATENCY_MISS)))]
3558 ""
3559 "ld<I124MODE:n><s>_add\t%0, %1, %2"
3560 [(set_attr "type" "X1_miss")])
3562 ;; L2 miss, non temporal loads
3564 (define_insn "insn_ldnt_miss"
3565 [(set (match_operand:DI 0 "register_operand" "=r")
3566 (unspec:DI [(unspec:DI
3567 [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3568 UNSPEC_NON_TEMPORAL)]
3569 UNSPEC_LATENCY_MISS))]
3570 ""
3571 "ldnt\t%0, %r1"
3572 [(set_attr "type" "X1_miss")])
3574 (define_insn "insn_ldnt_add_miss<bitsuffix>"
3575 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3576 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3577 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3578 (set (match_operand:DI 0 "register_operand" "=r")
3579 (unspec:DI [(unspec:DI
3580 [(mem:DI (match_dup 3))]
3581 UNSPEC_NON_TEMPORAL)]
3582 UNSPEC_LATENCY_MISS))]
3583 ""
3584 "ldnt_add\t%0, %1, %2"
3585 [(set_attr "type" "X1_miss")])
3587 (define_insn "insn_ldnt<n><s>_miss"
3588 [(set (match_operand:DI 0 "register_operand" "=r")
3589 (any_extend:DI
3590 (unspec:I124MODE
3591 [(unspec:I124MODE
3592 [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3593 UNSPEC_NON_TEMPORAL)]
3594 UNSPEC_LATENCY_MISS)))]
3595 ""
3596 "ldnt<n><s>\t%0, %r1"
3597 [(set_attr "type" "X1_miss")])
3599 (define_insn "insn_ldnt<I124MODE:n><s>_add_miss<I48MODE:bitsuffix>"
3600 [(set (match_operand:I48MODE 1 "register_operand" "=r")
3601 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "1")
3602 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3603 (set (match_operand:DI 0 "register_operand" "=r")
3604 (any_extend:DI
3605 (unspec:I124MODE [(unspec:I124MODE
3606 [(mem:I124MODE (match_dup 3))]
3607 UNSPEC_NON_TEMPORAL)]
3608 UNSPEC_LATENCY_MISS)))]
3609 ""
3610 "ldnt<I124MODE:n><s>_add\t%0, %1, %2"
3611 [(set_attr "type" "X1_miss")])
3613 ;; end loads
3615 (define_insn "insn_lnk"
3616 [(set (match_operand:DI 0 "register_operand" "=r")
3617 (unspec:DI [(const_int 0)] UNSPEC_INSN_LNK))]
3618 ""
3619 "lnk\t%0"
3620 [(set_attr "type" "Y1")])
3622 (define_insn "insn_mfspr"
3623 [(set (match_operand:DI 0 "register_operand" "=r")
3624 (unspec_volatile:DI [(match_operand:DI 1 "u14bit_cint_operand" "i")]
3625 UNSPEC_INSN_MFSPR))
3626 (clobber (mem:BLK (const_int 0)))]
3627 ""
3628 "mfspr\t%0, %1"
3629 [(set_attr "type" "X1")])
3631 (define_insn "insn_mtspr"
3632 [(unspec_volatile:DI [(match_operand:DI 0 "u14bit_cint_operand" "i")
3633 (match_operand:DI 1 "reg_or_0_operand" "rO")]
3634 UNSPEC_INSN_MTSPR)
3635 (clobber (mem:BLK (const_int 0)))]
3636 ""
3637 "mtspr\t%0, %r1"
3638 [(set_attr "type" "X1")])
3640 (define_insn "insn_mm"
3641 [(set (match_operand:DI 0 "register_operand" "=r")
3642 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3643 (match_operand:DI 2 "reg_or_0_operand" "rO")
3644 (match_operand:DI 3 "u6bit_cint_operand" "i")
3645 (match_operand:DI 4 "u6bit_cint_operand" "i")]
3646 UNSPEC_INSN_MM))]
3647 ""
3648 "mm\t%0, %r2, %3, %4"
3649 [(set_attr "type" "X0")])
3651 (define_insn "insn_mul_hs_hs"
3652 [(set (match_operand:DI 0 "register_operand" "=r")
3653 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3654 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3655 UNSPEC_INSN_MUL_HS_HS))]
3656 ""
3657 "mul_hs_hs\t%0, %r1, %r2"
3658 [(set_attr "type" "Y0_2cycle")])
3660 (define_insn "insn_mul_hs_hu"
3661 [(set (match_operand:DI 0 "register_operand" "=r")
3662 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3663 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3664 UNSPEC_INSN_MUL_HS_HU))]
3665 ""
3666 "mul_hs_hu\t%0, %r1, %r2"
3667 [(set_attr "type" "X0_2cycle")])
3669 (define_insn "insn_mul_hs_ls"
3670 [(set (match_operand:DI 0 "register_operand" "=r")
3671 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3672 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3673 UNSPEC_INSN_MUL_HS_LS))]
3674 ""
3675 "mul_hs_ls\t%0, %r1, %r2"
3676 [(set_attr "type" "X0_2cycle")])
3678 (define_insn "insn_mul_hs_lu"
3679 [(set (match_operand:DI 0 "register_operand" "=r")
3680 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3681 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3682 UNSPEC_INSN_MUL_HS_LU))]
3683 ""
3684 "mul_hs_lu\t%0, %r1, %r2"
3685 [(set_attr "type" "X0_2cycle")])
3687 (define_insn "insn_mul_hu_hu"
3688 [(set (match_operand:DI 0 "register_operand" "=r")
3689 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3690 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3691 UNSPEC_INSN_MUL_HU_HU))]
3692 ""
3693 "mul_hu_hu\t%0, %r1, %r2"
3694 [(set_attr "type" "Y0_2cycle")])
3696 (define_insn "insn_mul_hu_ls"
3697 [(set (match_operand:DI 0 "register_operand" "=r")
3698 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3699 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3700 UNSPEC_INSN_MUL_HU_LS))]
3701 ""
3702 "mul_hu_ls\t%0, %r1, %r2"
3703 [(set_attr "type" "X0_2cycle")])
3705 (define_insn "insn_mul_hu_lu"
3706 [(set (match_operand:DI 0 "register_operand" "=r")
3707 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3708 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3709 UNSPEC_INSN_MUL_HU_LU))]
3710 ""
3711 "mul_hu_lu\t%0, %r1, %r2"
3712 [(set_attr "type" "X0_2cycle")])
3714 (define_insn "insn_mul_ls_ls"
3715 [(set (match_operand:DI 0 "register_operand" "=r")
3716 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3717 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3718 UNSPEC_INSN_MUL_LS_LS))]
3719 ""
3720 "mul_ls_ls\t%0, %r1, %r2"
3721 [(set_attr "type" "Y0_2cycle")])
3723 (define_insn "insn_mul_ls_lu"
3724 [(set (match_operand:DI 0 "register_operand" "=r")
3725 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3726 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3727 UNSPEC_INSN_MUL_LS_LU))]
3728 ""
3729 "mul_ls_lu\t%0, %r1, %r2"
3730 [(set_attr "type" "X0_2cycle")])
3732 (define_insn "insn_mul_lu_lu"
3733 [(set (match_operand:DI 0 "register_operand" "=r")
3734 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3735 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3736 UNSPEC_INSN_MUL_LU_LU))]
3737 ""
3738 "mul_lu_lu\t%0, %r1, %r2"
3739 [(set_attr "type" "Y0_2cycle")])
3741 (define_insn "insn_mula_hs_hs"
3742 [(set (match_operand:DI 0 "register_operand" "=r")
3743 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3744 (match_operand:DI 2 "reg_or_0_operand" "rO")
3745 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3746 UNSPEC_INSN_MULA_HS_HS))]
3747 ""
3748 "mula_hs_hs\t%0, %r2, %r3"
3749 [(set_attr "type" "Y0_2cycle")])
3751 (define_insn "insn_mula_hs_hu"
3752 [(set (match_operand:DI 0 "register_operand" "=r")
3753 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3754 (match_operand:DI 2 "reg_or_0_operand" "rO")
3755 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3756 UNSPEC_INSN_MULA_HS_HU))]
3757 ""
3758 "mula_hs_hu\t%0, %r2, %r3"
3759 [(set_attr "type" "X0_2cycle")])
3761 (define_insn "insn_mula_hs_ls"
3762 [(set (match_operand:DI 0 "register_operand" "=r")
3763 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3764 (match_operand:DI 2 "reg_or_0_operand" "rO")
3765 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3766 UNSPEC_INSN_MULA_HS_LS))]
3767 ""
3768 "mula_hs_ls\t%0, %r2, %r3"
3769 [(set_attr "type" "X0_2cycle")])
3771 (define_insn "insn_mula_hs_lu"
3772 [(set (match_operand:DI 0 "register_operand" "=r")
3773 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3774 (match_operand:DI 2 "reg_or_0_operand" "rO")
3775 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3776 UNSPEC_INSN_MULA_HS_LU))]
3777 ""
3778 "mula_hs_lu\t%0, %r2, %r3"
3779 [(set_attr "type" "X0_2cycle")])
3781 (define_insn "insn_mula_hu_hu"
3782 [(set (match_operand:DI 0 "register_operand" "=r")
3783 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3784 (match_operand:DI 2 "reg_or_0_operand" "rO")
3785 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3786 UNSPEC_INSN_MULA_HU_HU))]
3787 ""
3788 "mula_hu_hu\t%0, %r2, %r3"
3789 [(set_attr "type" "Y0_2cycle")])
3791 (define_insn "insn_mula_hu_ls"
3792 [(set (match_operand:DI 0 "register_operand" "=r")
3793 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3794 (match_operand:DI 2 "reg_or_0_operand" "rO")
3795 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3796 UNSPEC_INSN_MULA_HU_LS))]
3797 ""
3798 "mula_hu_ls\t%0, %r2, %r3"
3799 [(set_attr "type" "X0_2cycle")])
3801 (define_insn "insn_mula_hu_lu"
3802 [(set (match_operand:DI 0 "register_operand" "=r")
3803 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3804 (match_operand:DI 2 "reg_or_0_operand" "rO")
3805 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3806 UNSPEC_INSN_MULA_HU_LU))]
3807 ""
3808 "mula_hu_lu\t%0, %r2, %r3"
3809 [(set_attr "type" "X0_2cycle")])
3811 (define_insn "insn_mula_ls_ls"
3812 [(set (match_operand:DI 0 "register_operand" "=r")
3813 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3814 (match_operand:DI 2 "reg_or_0_operand" "rO")
3815 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3816 UNSPEC_INSN_MULA_LS_LS))]
3817 ""
3818 "mula_ls_ls\t%0, %r2, %r3"
3819 [(set_attr "type" "Y0_2cycle")])
3821 (define_insn "insn_mula_ls_lu"
3822 [(set (match_operand:DI 0 "register_operand" "=r")
3823 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3824 (match_operand:DI 2 "reg_or_0_operand" "rO")
3825 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3826 UNSPEC_INSN_MULA_LS_LU))]
3827 ""
3828 "mula_ls_lu\t%0, %r2, %r3"
3829 [(set_attr "type" "X0_2cycle")])
3831 (define_insn "insn_mula_lu_lu"
3832 [(set (match_operand:DI 0 "register_operand" "=r")
3833 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3834 (match_operand:DI 2 "reg_or_0_operand" "rO")
3835 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3836 UNSPEC_INSN_MULA_LU_LU))]
3837 ""
3838 "mula_lu_lu\t%0, %r2, %r3"
3839 [(set_attr "type" "Y0_2cycle")])
3841 (define_insn "insn_mulax"
3842 [(set (match_operand:SI 0 "register_operand" "=r")
3843 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3844 (match_operand:SI 2 "reg_or_0_operand" "rO")
3845 (match_operand:SI 3 "reg_or_0_operand" "rO")]
3846 UNSPEC_INSN_MULAX))]
3847 ""
3848 "mulax\t%0, %r2, %r3"
3849 [(set_attr "type" "Y0_2cycle")])
3851 (define_insn "insn_nap"
3852 [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_NAP)]
3853 ""
3854 "nap"
3855 [(set_attr "type" "cannot_bundle")])
3857 (define_insn "insn_nor_<mode>"
3858 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3859 (and:I48MODE
3860 (not:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rO"))
3861 (not:I48MODE (match_operand:I48MODE 2 "reg_or_0_operand" "rO"))))]
3862 ""
3863 "nor\t%0, %r1, %r2")
3865 (define_expand "insn_prefetch_l1"
3866 [(prefetch (match_operand 0 "pointer_operand" "")
3867 (const_int 0)
3868 (const_int 3))]
3869 "")
3871 (define_expand "insn_prefetch_l2"
3872 [(prefetch (match_operand 0 "pointer_operand" "")
3873 (const_int 0)
3874 (const_int 2))]
3875 "")
3877 (define_expand "insn_prefetch_l3"
3878 [(prefetch (match_operand 0 "pointer_operand" "")
3879 (const_int 0)
3880 (const_int 1))]
3881 "")
3883 (define_insn "insn_prefetch_l1_fault"
3884 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3885 UNSPEC_INSN_PREFETCH_L1_FAULT)]
3886 ""
3887 "prefetch_l1_fault\t%r0"
3888 [(set_attr "type" "Y2")])
3890 (define_insn "insn_prefetch_l2_fault"
3891 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3892 UNSPEC_INSN_PREFETCH_L2_FAULT)]
3893 ""
3894 "prefetch_l2_fault\t%r0"
3895 [(set_attr "type" "Y2")])
3897 (define_insn "insn_prefetch_l3_fault"
3898 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3899 UNSPEC_INSN_PREFETCH_L3_FAULT)]
3900 ""
3901 "prefetch_l3_fault\t%r0"
3902 [(set_attr "type" "Y2")])
3904 (define_insn "insn_revbits"
3905 [(set (match_operand:DI 0 "register_operand" "=r")
3906 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")]
3907 UNSPEC_INSN_REVBITS))]
3908 ""
3909 "revbits\t%0, %r1"
3910 [(set_attr "type" "Y0")])
3912 (define_insn "insn_shl1add"
3913 [(set (match_operand:DI 0 "register_operand" "=r")
3914 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rO")
3915 (const_int 2))
3916 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
3917 ""
3918 "shl1add\t%0, %r1, %r2")
3920 (define_insn "insn_shl1addx"
3921 [(set (match_operand:SI 0 "register_operand" "=r")
3922 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
3923 (const_int 2))
3924 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
3925 ""
3926 "shl1addx\t%0, %r1, %r2")
3928 (define_insn "insn_shl2add"
3929 [(set (match_operand:DI 0 "register_operand" "=r")
3930 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rO")
3931 (const_int 4))
3932 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
3933 ""
3934 "shl2add\t%0, %r1, %r2")
3936 (define_insn "insn_shl2addx"
3937 [(set (match_operand:SI 0 "register_operand" "=r")
3938 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
3939 (const_int 4))
3940 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
3941 ""
3942 "shl2addx\t%0, %r1, %r2")
3944 (define_insn "insn_shl3add"
3945 [(set (match_operand:DI 0 "register_operand" "=r")
3946 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rO")
3947 (const_int 8))
3948 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
3949 ""
3950 "shl3add\t%0, %r1, %r2")
3952 (define_insn "insn_shl3addx"
3953 [(set (match_operand:SI 0 "register_operand" "=r")
3954 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
3955 (const_int 8))
3956 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
3957 ""
3958 "shl3addx\t%0, %r1, %r2")
3960 (define_insn "insn_shufflebytes"
3961 [(set (match_operand:DI 0 "register_operand" "=r")
3962 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3963 (match_operand:DI 2 "reg_or_0_operand" "rO")
3964 (match_operand:DI 3 "reg_or_0_operand" "rO")]
3965 UNSPEC_INSN_SHUFFLEBYTES))]
3966 ""
3967 "shufflebytes\t%0, %r2, %r3"
3968 [(set_attr "type" "X0")])
3970 (define_insn "insn_shufflebytes1"
3971 [(set (match_operand:DI 0 "register_operand" "=r")
3972 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3973 (match_operand:DI 2 "reg_or_0_operand" "rO")]
3974 UNSPEC_INSN_SHUFFLEBYTES))]
3975 ""
3976 "shufflebytes\t%0, %r1, %r2"
3977 [(set_attr "type" "X0")])
3979 ;; stores
3981 (define_expand "insn_st"
3982 [(set (mem:DI (match_operand 0 "pointer_operand" ""))
3983 (match_operand:DI 1 "reg_or_0_operand" ""))]
3984 "")
3986 (define_insn "insn_st_add<bitsuffix>"
3987 [(set (match_operand:I48MODE 0 "register_operand" "=r")
3988 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "0")
3989 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
3990 (set (mem:DI (match_dup 3))
3991 (match_operand:DI 1 "reg_or_0_operand" "rO"))]
3992 ""
3993 "st_add\t%0, %r1, %2"
3994 [(set_attr "type" "X1")])
3996 (define_expand "insn_st<n>"
3997 [(set (mem:I124MODE (match_operand 0 "pointer_operand" ""))
3998 (match_operand:DI 1 "reg_or_0_operand" ""))]
3999 ""
4000 {
4001 operands[1] = simplify_gen_subreg (<MODE>mode, operands[1], DImode,
4002 BYTES_BIG_ENDIAN
4003 ? UNITS_PER_WORD - <n> : 0);
4004 })
4006 (define_expand "insn_st<I124MODE:n>_add<I48MODE:bitsuffix>"
4007 [(parallel
4008 [(set (match_operand:I48MODE 0 "register_operand" "")
4009 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "")
4010 (match_operand:I48MODE 2 "s8bit_cint_operand" "")))
4011 (set (mem:I124MODE (match_dup 3))
4012 (match_operand:DI 1 "reg_or_0_operand" ""))])]
4013 ""
4014 {
4015 operands[1] = simplify_gen_subreg (<I124MODE:MODE>mode, operands[1],
4016 DImode,
4017 BYTES_BIG_ENDIAN
4018 ? UNITS_PER_WORD - <I124MODE:n> : 0);
4019 })
4021 (define_insn "*insn_st<I124MODE:n>_add<I48MODE:bitsuffix>"
4022 [(set (match_operand:I48MODE 0 "register_operand" "=r")
4023 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "0")
4024 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
4025 (set (mem:I124MODE (match_dup 3))
4026 (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))]
4027 ""
4028 "st<I124MODE:n>_add\t%0, %r1, %2"
4029 [(set_attr "type" "X1")])
4031 ;; non-temporal stores
4033 (define_insn "insn_stnt"
4034 [(set (mem:DI (unspec [(match_operand 0 "pointer_operand" "rO")]
4035 UNSPEC_NON_TEMPORAL))
4036 (match_operand:DI 1 "reg_or_0_operand" "rO"))]
4037 ""
4038 "stnt\t%0, %r1"
4039 [(set_attr "type" "X1")])
4041 (define_insn "insn_stnt_add<bitsuffix>"
4042 [(set (match_operand:I48MODE 0 "register_operand" "=r")
4043 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "0")
4044 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
4045 (set (mem:DI (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL))
4046 (match_operand:DI 1 "reg_or_0_operand" "rO"))]
4047 ""
4048 "stnt_add\t%0, %r1, %2"
4049 [(set_attr "type" "X1")])
4051 (define_expand "insn_stnt<n>"
4052 [(set (mem:I124MODE (unspec [(match_operand 0 "pointer_operand" "")]
4053 UNSPEC_NON_TEMPORAL))
4054 (match_operand:DI 1 "reg_or_0_operand" ""))]
4055 ""
4056 {
4057 operands[1] = simplify_gen_subreg (<MODE>mode, operands[1], DImode,
4058 BYTES_BIG_ENDIAN
4059 ? UNITS_PER_WORD - <n> : 0);
4060 })
4062 (define_insn "*insn_stnt<n>"
4063 [(set (mem:I124MODE (unspec [(match_operand 0 "pointer_operand" "rO")]
4064 UNSPEC_NON_TEMPORAL))
4065 (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))]
4066 ""
4067 "stnt<n>\t%0, %r1"
4068 [(set_attr "type" "X1")])
4070 (define_expand "insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>"
4071 [(parallel
4072 [(set (match_operand:I48MODE 0 "register_operand" "")
4073 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "")
4074 (match_operand:I48MODE 2 "s8bit_cint_operand" "")))
4075 (set (mem:I124MODE (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL))
4076 (match_operand:DI 1 "reg_or_0_operand" "rO"))])]
4077 ""
4078 {
4079 operands[1] = simplify_gen_subreg (<I124MODE:MODE>mode, operands[1],
4080 DImode,
4081 BYTES_BIG_ENDIAN
4082 ? UNITS_PER_WORD - <n> : 0);
4083 })
4085 (define_insn "*insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>"
4086 [(set (match_operand:I48MODE 0 "register_operand" "=r")
4087 (plus:I48MODE (match_operand:I48MODE 3 "register_operand" "0")
4088 (match_operand:I48MODE 2 "s8bit_cint_operand" "i")))
4089 (set (mem:I124MODE (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL))
4090 (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))]
4091 ""
4092 "stnt<I124MODE:n>_add\t%0, %r1, %2"
4093 [(set_attr "type" "X1")])
4095 ;; end stores
4097 (define_insn "insn_tblidxb0"
4098 [(set (match_operand:DI 0 "register_operand" "=r")
4099 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4100 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4101 UNSPEC_INSN_TBLIDXB0))]
4102 ""
4103 "tblidxb0\t%0, %r2"
4104 [(set_attr "type" "Y0")])
4106 (define_insn "insn_tblidxb1"
4107 [(set (match_operand:DI 0 "register_operand" "=r")
4108 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4109 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4110 UNSPEC_INSN_TBLIDXB1))]
4111 ""
4112 "tblidxb1\t%0, %r2"
4113 [(set_attr "type" "Y0")])
4115 (define_insn "insn_tblidxb2"
4116 [(set (match_operand:DI 0 "register_operand" "=r")
4117 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4118 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4119 UNSPEC_INSN_TBLIDXB2))]
4120 ""
4121 "tblidxb2\t%0, %r2"
4122 [(set_attr "type" "Y0")])
4124 (define_insn "insn_tblidxb3"
4125 [(set (match_operand:DI 0 "register_operand" "=r")
4126 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4127 (match_operand:DI 2 "reg_or_0_operand" "rO")]
4128 UNSPEC_INSN_TBLIDXB3))]
4129 ""
4130 "tblidxb3\t%0, %r2"
4131 [(set_attr "type" "Y0")])
4133 ;; insn_v1add
4134 ;; insn_v1addi
4135 ;; insn_v1cmpeq
4136 ;; insn_v1cmpeqi
4137 ;; insn_v1cmplts
4138 ;; insn_v1cmpltsi
4139 ;; insn_v1cmpltu
4140 ;; insn_v1cmpltui
4141 ;; insn_v1maxu
4142 ;; insn_v1maxui
4143 ;; insn_v1minu
4144 ;; insn_v1minui
4145 (define_insn "<optab>v8qi3"
4146 [(set (match_operand:V8QI 0 "register_operand" "=r,r")
4147 (v1op_immed:V8QI
4148 (match_operand:V8QI 1 "reg_or_0_operand" "<comm>rO,rO")
4149 (match_operand:V8QI 2 "reg_or_v8s8bit_operand" "W,rO")))]
4150 ""
4151 "@
4152 v1<insn>i\t%0, %r1, %j2
4153 v1<insn>\t%0, %r1, %r2"
4154 [(set_attr "type" "<pipe>,<pipe>")])
4156 (define_expand "insn_v1<insn>"
4157 [(set (match_operand:DI 0 "register_operand" "")
4158 (v1op_immed:V8QI
4159 (match_operand:DI 1 "reg_or_0_operand" "")
4160 (match_operand:DI 2 "reg_or_0_operand" "")))]
4161 ""
4162 {
4163 tilegx_expand_builtin_vector_binop (gen_<optab>v8qi3, V8QImode, operands[0],
4164 V8QImode, operands[1], operands[2], true);
4165 DONE;
4166 })
4168 (define_expand "insn_v1<insn>i"
4169 [(set (match_operand:DI 0 "register_operand" "")
4170 (v1op_immed:V8QI
4171 (match_operand:DI 1 "reg_or_0_operand" "")
4172 (match_operand:DI 2 "s8bit_cint_operand" "")))]
4173 ""
4174 {
4175 /* Tile out immediate and expand to general case. */
4176 rtx n = tilegx_simd_int (operands[2], QImode);
4177 tilegx_expand_builtin_vector_binop (gen_<optab>v8qi3, V8QImode, operands[0],
4178 V8QImode, operands[1], n, true);
4179 DONE;
4180 })
4182 ;; insn_v1shl
4183 ;; insn_v1shli
4184 ;; insn_v1shrs
4185 ;; insn_v1shrsi
4186 ;; insn_v1shru
4187 ;; insn_v1shrui
4188 (define_insn "<optab>v8qi3"
4189 [(set (match_operand:V8QI 0 "register_operand" "=r,r")
4190 (any_shift:V8QI
4191 (match_operand:V8QI 1 "reg_or_0_operand" "rO,rO")
4192 (match_operand:DI 2 "reg_or_u5bit_operand" "I,rO")))]
4193 ""
4194 "@
4195 v1<insn>i\t%0, %r1, %2
4196 v1<insn>\t%0, %r1, %r2"
4197 [(set_attr "type" "<pipe>,<pipe>")])
4199 (define_expand "insn_v1<insn>"
4200 [(set (match_operand:DI 0 "register_operand" "")
4201 (any_shift:V8QI
4202 (match_operand:DI 1 "reg_or_0_operand" "")
4203 (match_operand:DI 2 "reg_or_u5bit_operand" "")))]
4204 ""
4205 {
4206 tilegx_expand_builtin_vector_binop (gen_<optab>v8qi3, V8QImode, operands[0],
4207 V8QImode, operands[1], operands[2], false);
4208 DONE;
4209 })
4211 ;; insn_v2add
4212 ;; insn_v2addi
4213 ;; insn_v2maxs
4214 ;; insn_v2maxsi
4215 ;; insn_v2mins
4216 ;; insn_v2minsi
4217 ;; insn_v2cmpeq
4218 ;; insn_v2cmpeqi
4219 ;; insn_v2cmplts
4220 ;; insn_v2cmpltsi
4221 ;; insn_v2cmpltu
4222 ;; insn_v2cmpltui
4223 (define_insn "<optab>v4hi3"
4224 [(set (match_operand:V4HI 0 "register_operand" "=r,r")
4225 (v2op_immed:V4HI
4226 (match_operand:V4HI 1 "reg_or_0_operand" "<comm>rO,rO")
4227 (match_operand:V4HI 2 "reg_or_v4s8bit_operand" "Y,rO")))]
4228 ""
4229 "@
4230 v2<insn>i\t%0, %r1, %j2
4231 v2<insn>\t%0, %r1, %r2"
4232 [(set_attr "type" "<pipe>,<pipe>")])
4234 (define_expand "insn_v2<insn>"
4235 [(set (match_operand:DI 0 "register_operand" "")
4236 (v2op_immed:V4HI
4237 (match_operand:DI 1 "reg_or_0_operand" "")
4238 (match_operand:DI 2 "reg_or_0_operand" "")))]
4239 ""
4240 {
4241 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4242 V4HImode, operands[1], operands[2], true);
4243 DONE;
4244 })
4246 (define_expand "insn_v2<insn>i"
4247 [(set (match_operand:DI 0 "register_operand" "")
4248 (v2op_immed:V4HI
4249 (match_operand:DI 1 "reg_or_0_operand" "")
4250 (match_operand:DI 2 "s8bit_cint_operand" "")))]
4251 ""
4252 {
4253 /* Tile out immediate and expand to general case. */
4254 rtx n = tilegx_simd_int (operands[2], HImode);
4255 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4256 V4HImode, operands[1], n, true);
4257 DONE;
4258 })
4260 ;; insn_v2shl
4261 ;; insn_v2shli
4262 ;; insn_v2shrs
4263 ;; insn_v2shrsi
4264 ;; insn_v2shru
4265 ;; insn_v2shrui
4266 (define_insn "<optab>v4hi3"
4267 [(set (match_operand:V4HI 0 "register_operand" "=r,r")
4268 (any_shift:V4HI
4269 (match_operand:V4HI 1 "reg_or_0_operand" "rO,rO")
4270 (match_operand:DI 2 "reg_or_u5bit_operand" "I,rO")))]
4271 ""
4272 "@
4273 v2<insn>i\t%0, %r1, %2
4274 v2<insn>\t%0, %r1, %r2"
4275 [(set_attr "type" "<pipe>,<pipe>")])
4277 (define_expand "insn_v2<insn>"
4278 [(set (match_operand:DI 0 "register_operand" "")
4279 (any_shift:V4HI
4280 (match_operand:DI 1 "reg_or_0_operand" "")
4281 (match_operand:DI 2 "reg_or_u5bit_operand" "")))]
4282 ""
4283 {
4284 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4285 V4HImode, operands[1], operands[2], false);
4286 DONE;
4287 })
4289 ;; insn_v1adduc
4290 ;; insn_v1subuc
4291 ;; insn_v1sub
4292 ;; insn_v1cmpne
4293 ;; insn_v1cmples
4294 ;; insn_v1cmpleu
4295 ;; insn_v1multu
4296 (define_insn "<optab>v8qi3"
4297 [(set (match_operand:V8QI 0 "register_operand" "=r")
4298 (v1op:V8QI
4299 (match_operand:V8QI 1 "reg_or_0_operand" "<comm>rO")
4300 (match_operand:V8QI 2 "reg_or_0_operand" "rO")))]
4301 ""
4302 "v1<insn>\t%0, %r1, %r2"
4303 [(set_attr "type" "<pipe>")])
4305 (define_expand "insn_v1<insn>"
4306 [(set (match_operand:DI 0 "register_operand" "")
4307 (v1op:V8QI
4308 (match_operand:DI 1 "reg_or_0_operand" "")
4309 (match_operand:DI 2 "reg_or_0_operand" "")))]
4310 ""
4311 {
4312 tilegx_expand_builtin_vector_binop (gen_<optab>v8qi3, V8QImode, operands[0],
4313 V8QImode, operands[1], operands[2], true);
4314 DONE;
4315 })
4317 ;; insn_v2addsc
4318 ;; insn_v2subsc
4319 ;; insn_v2sub
4320 ;; insn_v2cmpne
4321 ;; insn_v2cmples
4322 ;; insn_v2cmpleu
4323 (define_insn "<optab>v4hi3"
4324 [(set (match_operand:V4HI 0 "register_operand" "=r")
4325 (v2op:V4HI
4326 (match_operand:V4HI 1 "reg_or_0_operand" "<comm>rO")
4327 (match_operand:V4HI 2 "reg_or_0_operand" "rO")))]
4328 ""
4329 "v2<insn>\t%0, %r1, %r2"
4330 [(set_attr "type" "<pipe>")])
4332 (define_expand "insn_v2<insn>"
4333 [(set (match_operand:DI 0 "register_operand" "")
4334 (v2op:V4HI
4335 (match_operand:DI 1 "reg_or_0_operand" "")
4336 (match_operand:DI 2 "reg_or_0_operand" "")))]
4337 ""
4338 {
4339 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4340 V4HImode, operands[1], operands[2], true);
4341 DONE;
4342 })
4344 ;; insn_v2mults
4345 (define_insn "mulv4hi3"
4346 [(set (match_operand:V4HI 0 "register_operand" "=r")
4347 (mult:V4HI
4348 (match_operand:V4HI 1 "reg_or_0_operand" "%rO")
4349 (match_operand:V4HI 2 "reg_or_0_operand" "rO")))]
4350 ""
4351 "v2mults\t%0, %r1, %r2"
4352 [(set_attr "type" "X0_2cycle")])
4354 (define_expand "insn_v2mults"
4355 [(set (match_operand:DI 0 "register_operand" "")
4356 (mult:V4HI
4357 (match_operand:DI 1 "reg_or_0_operand" "")
4358 (match_operand:DI 2 "reg_or_0_operand" "")))]
4359 ""
4360 {
4361 tilegx_expand_builtin_vector_binop (gen_mulv4hi3, V4HImode, operands[0],
4362 V4HImode, operands[1], operands[2], true);
4363 DONE;
4364 })
4366 ;; insn_v2shlsc
4367 (define_insn "<optab>v4hi3"
4368 [(set (match_operand:V4HI 0 "register_operand" "=r")
4369 (v2shift:V4HI
4370 (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4371 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
4372 ""
4373 "v2<insn>\t%0, %r1, %r2"
4374 [(set_attr "type" "<pipe>")])
4376 (define_expand "insn_v2<insn>"
4377 [(set (match_operand:DI 0 "register_operand" "")
4378 (v2shift:V4HI
4379 (match_operand:DI 1 "reg_or_0_operand" "")
4380 (match_operand:DI 2 "reg_or_0_operand" "")))]
4381 ""
4382 {
4383 tilegx_expand_builtin_vector_binop (gen_<optab>v4hi3, V4HImode, operands[0],
4384 V4HImode, operands[1], operands[2], false);
4385 DONE;
4386 })
4388 ;; insn_v4addsc
4389 ;; insn_v4subsc
4390 ;; insn_v4add
4391 ;; insn_v4sub
4392 (define_insn "<optab>v2si3"
4393 [(set (match_operand:V2SI 0 "register_operand" "=r")
4394 (v4op:V2SI
4395 (match_operand:V2SI 1 "reg_or_0_operand" "<comm>rO")
4396 (match_operand:V2SI 2 "reg_or_0_operand" "rO")))]
4397 ""
4398 "v4<insn>\t%0, %r1, %r2"
4399 [(set_attr "type" "<pipe>")])
4401 (define_expand "insn_v4<insn>"
4402 [(set (match_operand:DI 0 "register_operand" "")
4403 (v4op:V2SI
4404 (match_operand:DI 1 "reg_or_0_operand" "")
4405 (match_operand:DI 2 "reg_or_0_operand" "")))]
4406 ""
4407 {
4408 tilegx_expand_builtin_vector_binop (gen_<optab>v2si3, V2SImode, operands[0],
4409 V2SImode, operands[1], operands[2], true);
4410 DONE;
4411 })
4413 ;; insn_v4shl
4414 ;; insn_v4shrs
4415 ;; insn_v4shru
4416 ;; insn_v4shlsc
4417 (define_insn "<optab>v2si3"
4418 [(set (match_operand:V2SI 0 "register_operand" "=r")
4419 (v4shift:V2SI
4420 (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4421 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
4422 ""
4423 "v4<insn>\t%0, %r1, %r2"
4424 [(set_attr "type" "<pipe>")])
4426 (define_expand "insn_v4<insn>"
4427 [(set (match_operand:DI 0 "register_operand" "")
4428 (v4shift:V2SI
4429 (match_operand:DI 1 "reg_or_0_operand" "")
4430 (match_operand:DI 2 "reg_or_0_operand" "")))]
4431 ""
4432 {
4433 tilegx_expand_builtin_vector_binop (gen_<optab>v2si3, V2SImode, operands[0],
4434 V2SImode, operands[1], operands[2], false);
4435 DONE;
4436 })
4438 ;; Byte ordering of these vectors is endian dependent. gcc concats
4439 ;; right-to-left for little endian, and left-to-right for big endian.
4440 ;; So we need different patterns that depend on endianness. Our
4441 ;; instructions concat and interleave the way a big-endian target would
4442 ;; work in gcc, so for little endian, we need to reverse the source
4443 ;; operands.
4445 ;; insn_v1int_h
4446 ;; {B7,B6,B5,B4,B3,B2,B1,B0} {A7,A6,A5,A4,A3,A2,A1,A0}
4447 ;; => {A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0}
4448 ;; => {A7,B7,A6,B6,A5,B5,A4,B4}
4449 (define_expand "vec_interleave_highv8qi"
4450 [(match_operand:V8QI 0 "register_operand" "")
4451 (match_operand:V8QI 1 "reg_or_0_operand" "")
4452 (match_operand:V8QI 2 "reg_or_0_operand" "")]
4453 ""
4454 {
4455 if (BYTES_BIG_ENDIAN)
4456 emit_insn (gen_vec_interleave_highv8qi_be (operands[0], operands[1],
4457 operands[2]));
4458 else
4459 emit_insn (gen_vec_interleave_highv8qi_le (operands[0], operands[1],
4460 operands[2]));
4461 DONE;
4462 })
4464 (define_insn "vec_interleave_highv8qi_be"
4465 [(set (match_operand:V8QI 0 "register_operand" "=r")
4466 (vec_select:V8QI
4467 (vec_concat:V16QI (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4468 (match_operand:V8QI 2 "reg_or_0_operand" "rO"))
4469 (parallel [(const_int 0) (const_int 8)
4470 (const_int 1) (const_int 9)
4471 (const_int 2) (const_int 10)
4472 (const_int 3) (const_int 11)])))]
4473 "BYTES_BIG_ENDIAN"
4474 "v1int_h\t%0, %r1, %r2"
4475 [(set_attr "type" "X01")])
4477 (define_insn "vec_interleave_highv8qi_le"
4478 [(set (match_operand:V8QI 0 "register_operand" "=r")
4479 (vec_select:V8QI
4480 (vec_concat:V16QI (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4481 (match_operand:V8QI 2 "reg_or_0_operand" "rO"))
4482 (parallel [(const_int 4) (const_int 12)
4483 (const_int 5) (const_int 13)
4484 (const_int 6) (const_int 14)
4485 (const_int 7) (const_int 15)])))]
4486 "!BYTES_BIG_ENDIAN"
4487 "v1int_h\t%0, %r2, %r1"
4488 [(set_attr "type" "X01")])
4490 (define_expand "insn_v1int_h"
4491 [(match_operand:DI 0 "register_operand" "")
4492 (match_operand:DI 1 "reg_or_0_operand" "")
4493 (match_operand:DI 2 "reg_or_0_operand" "")]
4494 ""
4495 {
4496 /* For little endian, our instruction interleaves opposite of the
4497 way vec_interleave works, so we need to reverse the source
4498 operands. */
4499 rtx opnd1 = BYTES_BIG_ENDIAN ? operands[1] : operands[2];
4500 rtx opnd2 = BYTES_BIG_ENDIAN ? operands[2] : operands[1];
4501 tilegx_expand_builtin_vector_binop (gen_vec_interleave_highv8qi, V8QImode,
4502 operands[0], V8QImode, opnd1, opnd2,
4503 true);
4504 DONE;
4505 })
4507 ;; insn_v1int_l
4508 ;; {B7,B6,B5,B4,B3,B2,B1,B0} {A7,A6,A5,A4,A3,A2,A1,A0}
4509 ;; => {A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0}
4510 ;; => {A3,B3,A2,B2,A1,B1,A0,B0}
4511 (define_expand "vec_interleave_lowv8qi"
4512 [(match_operand:V8QI 0 "register_operand" "")
4513 (match_operand:V8QI 1 "reg_or_0_operand" "")
4514 (match_operand:V8QI 2 "reg_or_0_operand" "")]
4515 ""
4516 {
4517 if (BYTES_BIG_ENDIAN)
4518 emit_insn (gen_vec_interleave_lowv8qi_be (operands[0], operands[1],
4519 operands[2]));
4520 else
4521 emit_insn (gen_vec_interleave_lowv8qi_le (operands[0], operands[1],
4522 operands[2]));
4523 DONE;
4524 })
4526 (define_insn "vec_interleave_lowv8qi_be"
4527 [(set (match_operand:V8QI 0 "register_operand" "=r")
4528 (vec_select:V8QI
4529 (vec_concat:V16QI (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4530 (match_operand:V8QI 2 "reg_or_0_operand" "rO"))
4531 (parallel [(const_int 4) (const_int 12)
4532 (const_int 5) (const_int 13)
4533 (const_int 6) (const_int 14)
4534 (const_int 7) (const_int 15)])))]
4535 "BYTES_BIG_ENDIAN"
4536 "v1int_l\t%0, %r1, %r2"
4537 [(set_attr "type" "X01")])
4539 (define_insn "vec_interleave_lowv8qi_le"
4540 [(set (match_operand:V8QI 0 "register_operand" "=r")
4541 (vec_select:V8QI
4542 (vec_concat:V16QI (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4543 (match_operand:V8QI 2 "reg_or_0_operand" "rO"))
4544 (parallel [(const_int 0) (const_int 8)
4545 (const_int 1) (const_int 9)
4546 (const_int 2) (const_int 10)
4547 (const_int 3) (const_int 11)])))]
4548 "!BYTES_BIG_ENDIAN"
4549 "v1int_l\t%0, %r2, %r1"
4550 [(set_attr "type" "X01")])
4552 (define_expand "insn_v1int_l"
4553 [(match_operand:DI 0 "register_operand" "")
4554 (match_operand:DI 1 "reg_or_0_operand" "")
4555 (match_operand:DI 2 "reg_or_0_operand" "")]
4556 ""
4557 {
4558 /* For little endian, our instruction interleaves opposite of the
4559 way vec_interleave works, so we need to reverse the source
4560 operands. */
4561 rtx opnd1 = BYTES_BIG_ENDIAN ? operands[1] : operands[2];
4562 rtx opnd2 = BYTES_BIG_ENDIAN ? operands[2] : operands[1];
4563 tilegx_expand_builtin_vector_binop (gen_vec_interleave_lowv8qi, V8QImode,
4564 operands[0], V8QImode, opnd1, opnd2,
4565 true);
4566 DONE;
4567 })
4569 ;; insn_v2int_h
4570 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
4571 ;; => {A3,A2,A1,A0,B3,B2,B1,B0}
4572 ;; => {A3,B3,A2,B2}
4573 (define_expand "vec_interleave_highv4hi"
4574 [(match_operand:V4HI 0 "register_operand" "")
4575 (match_operand:V4HI 1 "reg_or_0_operand" "")
4576 (match_operand:V4HI 2 "reg_or_0_operand" "")]
4577 ""
4578 {
4579 if (BYTES_BIG_ENDIAN)
4580 emit_insn (gen_vec_interleave_highv4hi_be (operands[0], operands[1],
4581 operands[2]));
4582 else
4583 emit_insn (gen_vec_interleave_highv4hi_le (operands[0], operands[1],
4584 operands[2]));
4585 DONE;
4586 })
4588 (define_insn "vec_interleave_highv4hi_be"
4589 [(set (match_operand:V4HI 0 "register_operand" "=r")
4590 (vec_select:V4HI
4591 (vec_concat:V8HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4592 (match_operand:V4HI 2 "reg_or_0_operand" "rO"))
4593 (parallel [(const_int 0) (const_int 4)
4594 (const_int 1) (const_int 5)])))]
4595 "BYTES_BIG_ENDIAN"
4596 "v2int_h\t%0, %r1, %r2"
4597 [(set_attr "type" "X01")])
4599 (define_insn "vec_interleave_highv4hi_le"
4600 [(set (match_operand:V4HI 0 "register_operand" "=r")
4601 (vec_select:V4HI
4602 (vec_concat:V8HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4603 (match_operand:V4HI 2 "reg_or_0_operand" "rO"))
4604 (parallel [(const_int 2) (const_int 6)
4605 (const_int 3) (const_int 7)])))]
4606 "!BYTES_BIG_ENDIAN"
4607 "v2int_h\t%0, %r2, %r1"
4608 [(set_attr "type" "X01")])
4610 (define_expand "insn_v2int_h"
4611 [(match_operand:DI 0 "register_operand" "")
4612 (match_operand:DI 1 "reg_or_0_operand" "")
4613 (match_operand:DI 2 "reg_or_0_operand" "")]
4614 ""
4615 {
4616 /* For little endian, our instruction interleaves opposite of the
4617 way vec_interleave works, so we need to reverse the source
4618 operands. */
4619 rtx opnd1 = BYTES_BIG_ENDIAN ? operands[1] : operands[2];
4620 rtx opnd2 = BYTES_BIG_ENDIAN ? operands[2] : operands[1];
4621 tilegx_expand_builtin_vector_binop (gen_vec_interleave_highv4hi, V4HImode,
4622 operands[0], V4HImode, opnd1, opnd2,
4623 true);
4624 DONE;
4625 })
4627 ;; insn_v2int_l
4628 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
4629 ;; => {A3,A2,A1,A0,B3,B2,B1,B0}
4630 ;; => {A1,B1,A0,B0}
4631 (define_expand "vec_interleave_lowv4hi"
4632 [(match_operand:V4HI 0 "register_operand" "")
4633 (match_operand:V4HI 1 "reg_or_0_operand" "")
4634 (match_operand:V4HI 2 "reg_or_0_operand" "")]
4635 ""
4636 {
4637 if (BYTES_BIG_ENDIAN)
4638 emit_insn (gen_vec_interleave_lowv4hi_be (operands[0], operands[1],
4639 operands[2]));
4640 else
4641 emit_insn (gen_vec_interleave_lowv4hi_le (operands[0], operands[1],
4642 operands[2]));
4643 DONE;
4644 })
4646 (define_insn "vec_interleave_lowv4hi_be"
4647 [(set (match_operand:V4HI 0 "register_operand" "=r")
4648 (vec_select:V4HI
4649 (vec_concat:V8HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4650 (match_operand:V4HI 2 "reg_or_0_operand" "rO"))
4651 (parallel [(const_int 2) (const_int 6)
4652 (const_int 3) (const_int 7)])))]
4653 "BYTES_BIG_ENDIAN"
4654 "v2int_l\t%0, %r1, %r2"
4655 [(set_attr "type" "X01")])
4657 (define_insn "vec_interleave_lowv4hi_le"
4658 [(set (match_operand:V4HI 0 "register_operand" "=r")
4659 (vec_select:V4HI
4660 (vec_concat:V8HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4661 (match_operand:V4HI 2 "reg_or_0_operand" "rO"))
4662 (parallel [(const_int 0) (const_int 4)
4663 (const_int 1) (const_int 5)])))]
4664 "!BYTES_BIG_ENDIAN"
4665 "v2int_l\t%0, %r2, %r1"
4666 [(set_attr "type" "X01")])
4668 (define_expand "insn_v2int_l"
4669 [(match_operand:DI 0 "register_operand" "")
4670 (match_operand:DI 1 "reg_or_0_operand" "")
4671 (match_operand:DI 2 "reg_or_0_operand" "")]
4672 ""
4673 {
4674 /* For little endian, our instruction interleaves opposite of the
4675 way vec_interleave works, so we need to reverse the source
4676 operands. */
4677 rtx opnd1 = BYTES_BIG_ENDIAN ? operands[1] : operands[2];
4678 rtx opnd2 = BYTES_BIG_ENDIAN ? operands[2] : operands[1];
4679 tilegx_expand_builtin_vector_binop (gen_vec_interleave_lowv4hi, V4HImode,
4680 operands[0], V4HImode, opnd1, opnd2,
4681 true);
4682 DONE;
4683 })
4685 ;; insn_v4int_h
4686 ;; {B1,B0} {A1,A0}
4687 ;; => {A1,A0,B1,B0}
4688 ;; => {A1,B1}
4689 (define_expand "vec_interleave_highv2si"
4690 [(match_operand:V2SI 0 "register_operand" "")
4691 (match_operand:V2SI 1 "reg_or_0_operand" "")
4692 (match_operand:V2SI 2 "reg_or_0_operand" "")]
4693 ""
4694 {
4695 if (BYTES_BIG_ENDIAN)
4696 emit_insn (gen_vec_interleave_highv2si_be (operands[0], operands[1],
4697 operands[2]));
4698 else
4699 emit_insn (gen_vec_interleave_highv2si_le (operands[0], operands[1],
4700 operands[2]));
4701 DONE;
4702 })
4704 (define_insn "vec_interleave_highv2si_be"
4705 [(set (match_operand:V2SI 0 "register_operand" "=r")
4706 (vec_select:V2SI
4707 (vec_concat:V4SI (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4708 (match_operand:V2SI 2 "reg_or_0_operand" "rO"))
4709 (parallel [(const_int 0) (const_int 2)])))]
4710 "BYTES_BIG_ENDIAN"
4711 "v4int_h\t%0, %r1, %r2"
4712 [(set_attr "type" "X01")])
4714 (define_insn "vec_interleave_highv2si_le"
4715 [(set (match_operand:V2SI 0 "register_operand" "=r")
4716 (vec_select:V2SI
4717 (vec_concat:V4SI (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4718 (match_operand:V2SI 2 "reg_or_0_operand" "rO"))
4719 (parallel [(const_int 1) (const_int 3)])))]
4720 "!BYTES_BIG_ENDIAN"
4721 "v4int_h\t%0, %r2, %r1"
4722 [(set_attr "type" "X01")])
4724 (define_expand "insn_v4int_h"
4725 [(match_operand:DI 0 "register_operand" "")
4726 (match_operand:DI 1 "reg_or_0_operand" "")
4727 (match_operand:DI 2 "reg_or_0_operand" "")]
4728 ""
4729 {
4730 /* For little endian, our instruction interleaves opposite of the
4731 way vec_interleave works, so we need to reverse the source
4732 operands. */
4733 rtx opnd1 = BYTES_BIG_ENDIAN ? operands[1] : operands[2];
4734 rtx opnd2 = BYTES_BIG_ENDIAN ? operands[2] : operands[1];
4735 tilegx_expand_builtin_vector_binop (gen_vec_interleave_highv2si, V2SImode,
4736 operands[0], V2SImode, opnd1, opnd2,
4737 true);
4738 DONE;
4739 })
4741 ;; insn_v4int_l
4742 ;; {B1,B0} {A1,A0}
4743 ;; => {A1,A0,B1,B0}
4744 ;; => {A0,B0}
4745 (define_expand "vec_interleave_lowv2si"
4746 [(match_operand:V2SI 0 "register_operand" "")
4747 (match_operand:V2SI 1 "reg_or_0_operand" "")
4748 (match_operand:V2SI 2 "reg_or_0_operand" "")]
4749 ""
4750 {
4751 if (BYTES_BIG_ENDIAN)
4752 emit_insn (gen_vec_interleave_lowv2si_be (operands[0], operands[1],
4753 operands[2]));
4754 else
4755 emit_insn (gen_vec_interleave_lowv2si_le (operands[0], operands[1],
4756 operands[2]));
4757 DONE;
4758 })
4760 (define_insn "vec_interleave_lowv2si_be"
4761 [(set (match_operand:V2SI 0 "register_operand" "=r")
4762 (vec_select:V2SI
4763 (vec_concat:V4SI (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4764 (match_operand:V2SI 2 "reg_or_0_operand" "rO"))
4765 (parallel [(const_int 1) (const_int 3)])))]
4766 "BYTES_BIG_ENDIAN"
4767 "v4int_l\t%0, %r1, %r2"
4768 [(set_attr "type" "X01")])
4770 (define_insn "vec_interleave_lowv2si_le"
4771 [(set (match_operand:V2SI 0 "register_operand" "=r")
4772 (vec_select:V2SI
4773 (vec_concat:V4SI (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4774 (match_operand:V2SI 2 "reg_or_0_operand" "rO"))
4775 (parallel [(const_int 0) (const_int 2)])))]
4776 "!BYTES_BIG_ENDIAN"
4777 "v4int_l\t%0, %r2, %r1"
4778 [(set_attr "type" "X01")])
4780 (define_expand "insn_v4int_l"
4781 [(match_operand:DI 0 "register_operand" "")
4782 (match_operand:DI 1 "reg_or_0_operand" "")
4783 (match_operand:DI 2 "reg_or_0_operand" "")]
4784 ""
4785 {
4786 /* For little endian, our instruction interleaves opposite of the
4787 way vec_interleave works, so we need to reverse the source
4788 operands. */
4789 rtx opnd1 = BYTES_BIG_ENDIAN ? operands[1] : operands[2];
4790 rtx opnd2 = BYTES_BIG_ENDIAN ? operands[2] : operands[1];
4791 tilegx_expand_builtin_vector_binop (gen_vec_interleave_lowv2si, V2SImode,
4792 operands[0], V2SImode, opnd1, opnd2,
4793 true);
4794 DONE;
4795 })
4797 ;; insn_v1mnz
4798 ;; insn_v1mz
4799 ;; insn_v2mnz
4800 ;; insn_v2mz
4801 (define_insn "insn_mnz_v8qi"
4802 [(set (match_operand:V8QI 0 "register_operand" "=r")
4803 (if_then_else:V8QI
4804 (ne:V8QI
4805 (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4806 (const_vector:V8QI [(const_int 0) (const_int 0)
4807 (const_int 0) (const_int 0)
4808 (const_int 0) (const_int 0)
4809 (const_int 0) (const_int 0)]))
4810 (match_operand:V8QI 2 "reg_or_0_operand" "rO")
4811 (const_vector:V8QI [(const_int 0) (const_int 0)
4812 (const_int 0) (const_int 0)
4813 (const_int 0) (const_int 0)
4814 (const_int 0) (const_int 0)])))]
4815 ""
4816 "v1mnz\t%0, %r1, %r2"
4817 [(set_attr "type" "X01")])
4819 (define_expand "insn_v1mnz"
4820 [(set (match_operand:DI 0 "register_operand" "")
4821 (if_then_else:V8QI
4822 (ne:V8QI
4823 (match_operand:DI 1 "reg_or_0_operand" "")
4824 (const_vector:V8QI [(const_int 0) (const_int 0)
4825 (const_int 0) (const_int 0)
4826 (const_int 0) (const_int 0)
4827 (const_int 0) (const_int 0)])
4828 )
4829 (match_operand:DI 2 "reg_or_0_operand" "")
4830 (const_vector:V8QI [(const_int 0) (const_int 0)
4831 (const_int 0) (const_int 0)
4832 (const_int 0) (const_int 0)
4833 (const_int 0) (const_int 0)])))]
4834 ""
4835 {
4836 tilegx_expand_builtin_vector_binop (gen_insn_mnz_v8qi, V8QImode,
4837 operands[0], V8QImode, operands[1],
4838 operands[2], true);
4839 DONE;
4840 })
4842 (define_insn "insn_mz_v8qi"
4843 [(set (match_operand:V8QI 0 "register_operand" "=r")
4844 (if_then_else:V8QI
4845 (ne:V8QI
4846 (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4847 (const_vector:V8QI [(const_int 0) (const_int 0)
4848 (const_int 0) (const_int 0)
4849 (const_int 0) (const_int 0)
4850 (const_int 0) (const_int 0)]))
4851 (const_vector:V8QI [(const_int 0) (const_int 0)
4852 (const_int 0) (const_int 0)
4853 (const_int 0) (const_int 0)
4854 (const_int 0) (const_int 0)])
4855 (match_operand:V8QI 2 "reg_or_0_operand" "rO")))]
4856 ""
4857 "v1mz\t%0, %r1, %r2"
4858 [(set_attr "type" "X01")])
4860 (define_expand "insn_v1mz"
4861 [(set (match_operand:DI 0 "register_operand" "")
4862 (if_then_else:V8QI
4863 (ne:V8QI
4864 (match_operand:DI 1 "reg_or_0_operand" "")
4865 (const_vector:V8QI [(const_int 0) (const_int 0)
4866 (const_int 0) (const_int 0)
4867 (const_int 0) (const_int 0)
4868 (const_int 0) (const_int 0)]))
4869 (const_vector:V8QI [(const_int 0) (const_int 0)
4870 (const_int 0) (const_int 0)
4871 (const_int 0) (const_int 0)
4872 (const_int 0) (const_int 0)])
4873 (match_operand:DI 2 "reg_or_0_operand" "")))]
4874 ""
4875 {
4876 tilegx_expand_builtin_vector_binop (gen_insn_mz_v8qi, V8QImode,
4877 operands[0], V8QImode, operands[1],
4878 operands[2], true);
4879 DONE;
4880 })
4882 (define_insn "insn_mnz_v4hi"
4883 [(set (match_operand:V4HI 0 "register_operand" "=r")
4884 (if_then_else:V4HI
4885 (ne:V4HI
4886 (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4887 (const_vector:V4HI [(const_int 0) (const_int 0)
4888 (const_int 0) (const_int 0)]))
4889 (match_operand:V4HI 2 "reg_or_0_operand" "rO")
4890 (const_vector:V4HI [(const_int 0) (const_int 0)
4891 (const_int 0) (const_int 0)])))]
4892 ""
4893 "v2mnz\t%0, %r1, %r2"
4894 [(set_attr "type" "X01")])
4896 (define_expand "insn_v2mnz"
4897 [(set (match_operand:DI 0 "register_operand" "")
4898 (if_then_else:V4HI
4899 (ne:V4HI
4900 (match_operand:DI 1 "reg_or_0_operand" "")
4901 (const_vector:V4HI [(const_int 0) (const_int 0)
4902 (const_int 0) (const_int 0)]))
4903 (match_operand:DI 2 "reg_or_0_operand" "")
4904 (const_vector:V4HI [(const_int 0) (const_int 0)
4905 (const_int 0) (const_int 0)])))]
4906 ""
4907 {
4908 tilegx_expand_builtin_vector_binop (gen_insn_mnz_v4hi, V4HImode,
4909 operands[0], V4HImode, operands[1],
4910 operands[2], true);
4911 DONE;
4912 })
4914 (define_insn "insn_mz_v4hi"
4915 [(set (match_operand:V4HI 0 "register_operand" "=r")
4916 (if_then_else:V4HI
4917 (ne:V4HI
4918 (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4919 (const_vector:V4HI [(const_int 0) (const_int 0)
4920 (const_int 0) (const_int 0)]))
4921 (const_vector:V4HI [(const_int 0) (const_int 0)
4922 (const_int 0) (const_int 0)])
4923 (match_operand:V4HI 2 "reg_or_0_operand" "rO")))]
4924 ""
4925 "v2mz\t%0, %r1, %r2"
4926 [(set_attr "type" "X01")])
4928 (define_expand "insn_v2mz"
4929 [(set (match_operand:DI 0 "register_operand" "")
4930 (if_then_else:V4HI
4931 (ne:V4HI
4932 (match_operand:DI 1 "reg_or_0_operand" "")
4933 (const_vector:V4HI [(const_int 0) (const_int 0)
4934 (const_int 0) (const_int 0)]))
4935 (const_vector:V4HI [(const_int 0) (const_int 0)
4936 (const_int 0) (const_int 0)])
4937 (match_operand:DI 2 "reg_or_0_operand" "")))]
4938 ""
4939 {
4940 tilegx_expand_builtin_vector_binop (gen_insn_mz_v4hi, V4HImode,
4941 operands[0], V4HImode, operands[1],
4942 operands[2], true);
4943 DONE;
4944 })
4946 ;; insn_v1mulu
4947 (define_insn "vec_widen_umult_lo_v8qi"
4948 [(set (match_operand:V4HI 0 "register_operand" "=r")
4949 (mult:V4HI
4950 (zero_extend:V4HI
4951 (vec_select:V4QI
4952 (match_operand:V8QI 1 "register_operand" "r")
4953 (parallel [(const_int 0) (const_int 1)
4954 (const_int 2) (const_int 3)])))
4955 (zero_extend:V4HI
4956 (vec_select:V4QI
4957 (match_operand:V8QI 2 "register_operand" "r")
4958 (parallel [(const_int 0) (const_int 1)
4959 (const_int 2) (const_int 3)])))))]
4960 ""
4961 "v1mulu\t%0, %r1, %r2"
4962 [(set_attr "type" "X0_2cycle")])
4964 (define_expand "insn_v1mulu"
4965 [(match_operand:DI 0 "register_operand" "")
4966 (match_operand:DI 1 "register_operand" "")
4967 (match_operand:DI 2 "register_operand" "")]
4968 ""
4969 {
4970 tilegx_expand_builtin_vector_binop (gen_vec_widen_umult_lo_v8qi, V4HImode,
4971 operands[0], V8QImode, operands[1],
4972 operands[2], true);
4973 DONE;
4974 })
4976 ;; insn_v1mulus
4977 (define_insn "vec_widen_usmult_lo_v8qi"
4978 [(set (match_operand:V4HI 0 "register_operand" "=r")
4979 (mult:V4HI
4980 (zero_extend:V4HI
4981 (vec_select:V4QI
4982 (match_operand:V8QI 1 "register_operand" "r")
4983 (parallel [(const_int 0) (const_int 1)
4984 (const_int 2) (const_int 3)])))
4985 (sign_extend:V4HI
4986 (vec_select:V4QI
4987 (match_operand:V8QI 2 "register_operand" "r")
4988 (parallel [(const_int 0) (const_int 1)
4989 (const_int 2) (const_int 3)])))))]
4990 ""
4991 "v1mulus\t%0, %r1, %r2"
4992 [(set_attr "type" "X0_2cycle")])
4994 (define_expand "insn_v1mulus"
4995 [(match_operand:DI 0 "register_operand" "")
4996 (match_operand:DI 1 "register_operand" "")
4997 (match_operand:DI 2 "register_operand" "")]
4998 ""
4999 {
5000 tilegx_expand_builtin_vector_binop (gen_vec_widen_usmult_lo_v8qi, V4HImode,
5001 operands[0], V8QImode, operands[1],
5002 operands[2], true);
5003 DONE;
5004 })
5006 ;; insn_v2muls
5007 (define_insn "vec_widen_smult_lo_v4qi"
5008 [(set (match_operand:V2SI 0 "register_operand" "=r")
5009 (mult:V2SI
5010 (sign_extend:V2SI
5011 (vec_select:V2HI
5012 (match_operand:V4HI 1 "register_operand" "r")
5013 (parallel [(const_int 0) (const_int 1)])))
5014 (sign_extend:V2SI
5015 (vec_select:V2HI
5016 (match_operand:V4HI 2 "register_operand" "r")
5017 (parallel [(const_int 0) (const_int 1)])))))]
5018 ""
5019 "v2muls\t%0, %r1, %r2"
5020 [(set_attr "type" "X0_2cycle")])
5022 (define_expand "insn_v2muls"
5023 [(match_operand:DI 0 "register_operand" "")
5024 (match_operand:DI 1 "register_operand" "")
5025 (match_operand:DI 2 "register_operand" "")]
5026 ""
5027 {
5028 tilegx_expand_builtin_vector_binop (gen_vec_widen_smult_lo_v4qi, V2SImode,
5029 operands[0], V4HImode, operands[1],
5030 operands[2], true);
5031 DONE;
5032 })
5034 ;; v2packl
5035 ;; v2packuc
5036 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
5037 ;; => {A3,A2,A1,A0,B3,B2,B1,B0}
5038 (define_insn "vec_pack_<pack_optab>_v4hi"
5039 [(set (match_operand:V8QI 0 "register_operand" "=r")
5040 (vec_concat:V8QI
5041 (v2pack:V4QI (match_operand:V4HI 1 "reg_or_0_operand" "rO"))
5042 (v2pack:V4QI (match_operand:V4HI 2 "reg_or_0_operand" "rO"))))]
5043 ""
5044 "v2<pack_insn>\t%0, %r2, %r1"
5045 [(set_attr "type" "X01")])
5047 (define_expand "insn_v2<pack_insn>"
5048 [(set (match_operand:DI 0 "register_operand" "")
5049 (vec_concat:V8QI
5050 (v2pack:V4QI (match_operand:DI 2 "reg_or_0_operand" ""))
5051 (v2pack:V4QI (match_operand:DI 1 "reg_or_0_operand" ""))))]
5052 ""
5053 {
5054 /* Our instruction concats opposite of the way vec_pack works, so we
5055 need to reverse the source operands. */
5056 tilegx_expand_builtin_vector_binop (gen_vec_pack_<pack_optab>_v4hi,
5057 V8QImode, operands[0], V4HImode,
5058 operands[2], operands[1], true);
5059 DONE;
5060 })
5062 ;; v2packh
5063 ;; {B3,B2,B1,B0} {A3,A2,A1,A0}
5064 ;; => {A3_hi,A2_hi,A1_hi,A0_hi,B3_hi,B2_hi,B1_hi,B0_hi}
5065 (define_insn "vec_pack_hipart_v4hi"
5066 [(set (match_operand:V8QI 0 "register_operand" "=r")
5067 (vec_concat:V8QI
5068 (truncate:V4QI
5069 (ashiftrt:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
5070 (const_int 8)))
5071 (truncate:V4QI
5072 (ashiftrt:V4HI (match_operand:V4HI 2 "reg_or_0_operand" "rO")
5073 (const_int 8)))))]
5074 ""
5075 "v2packh\t%0, %r2, %r1"
5076 [(set_attr "type" "X01")])
5078 (define_expand "insn_v2packh"
5079 [(set (match_operand:DI 0 "register_operand" "")
5080 (vec_concat:V8QI
5081 (truncate:V4QI
5082 (ashiftrt:V4HI (match_operand:DI 2 "reg_or_0_operand" "")
5083 (const_int 8)))
5084 (truncate:V4QI
5085 (ashiftrt:V4HI (match_operand:DI 1 "reg_or_0_operand" "")
5086 (const_int 8)))))]
5087 ""
5088 {
5089 /* Our instruction concats opposite of the way vec_pack works, so we
5090 need to reverse the source operands. */
5091 tilegx_expand_builtin_vector_binop (gen_vec_pack_hipart_v4hi, V8QImode,
5092 operands[0], V4HImode, operands[2],
5093 operands[1], true);
5094 DONE;
5095 })
5097 ;; v4packsc
5098 ;; {B1,B0} {A1,A0}
5099 ;; => {A1,A0,B1,B0}
5100 (define_insn "vec_pack_ssat_v2si"
5101 [(set (match_operand:V4HI 0 "register_operand" "=r")
5102 (vec_concat:V4HI
5103 (us_truncate:V2HI (match_operand:V2SI 1 "reg_or_0_operand" "rO"))
5104 (us_truncate:V2HI (match_operand:V2SI 2 "reg_or_0_operand" "rO"))))]
5105 ""
5106 "v4packsc\t%0, %r2, %r1"
5107 [(set_attr "type" "X01")])
5109 (define_expand "insn_v4packsc"
5110 [(set (match_operand:DI 0 "register_operand" "")
5111 (vec_concat:V4HI
5112 (us_truncate:V2HI (match_operand:DI 2 "reg_or_0_operand" ""))
5113 (us_truncate:V2HI (match_operand:DI 1 "reg_or_0_operand" ""))))]
5114 ""
5115 {
5116 /* Our instruction concats opposite of the way vec_pack works, so we
5117 need to reverse the source operands. */
5118 tilegx_expand_builtin_vector_binop (gen_vec_pack_ssat_v2si, V4HImode,
5119 operands[0], V2SImode, operands[2],
5120 operands[1], true);
5121 DONE;
5122 })
5124 ;; Rest of the vector intrinsics
5125 (define_insn "insn_v1adiffu"
5126 [(set (match_operand:DI 0 "register_operand" "=r")
5127 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5128 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5129 UNSPEC_INSN_V1ADIFFU))]
5130 ""
5131 "v1adiffu\t%0, %r1, %r2"
5132 [(set_attr "type" "X0_2cycle")])
5134 (define_insn "insn_v1avgu"
5135 [(set (match_operand:DI 0 "register_operand" "=r")
5136 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5137 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5138 UNSPEC_INSN_V1AVGU))]
5139 ""
5140 "v1avgu\t%0, %r1, %r2"
5141 [(set_attr "type" "X0")])
5143 (define_insn "insn_v1ddotpu"
5144 [(set (match_operand:DI 0 "register_operand" "=r")
5145 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5146 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5147 UNSPEC_INSN_V1DDOTPU))]
5148 ""
5149 "v1ddotpu\t%0, %r1, %r2"
5150 [(set_attr "type" "X0_2cycle")])
5152 (define_insn "insn_v1ddotpua"
5153 [(set (match_operand:DI 0 "register_operand" "=r")
5154 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
5155 (match_operand:DI 2 "reg_or_0_operand" "rO")
5156 (match_operand:DI 3 "reg_or_0_operand" "rO")]
5157 UNSPEC_INSN_V1DDOTPUA))]
5158 ""
5159 "v1ddotpua\t%0, %r2, %r3"
5160 [(set_attr "type" "X0_2cycle")])
5162 (define_insn "insn_v1ddotpus"
5163 [(set (match_operand:DI 0 "register_operand" "=r")
5164 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5165 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5166 UNSPEC_INSN_V1DDOTPUS))]
5167 ""
5168 "v1ddotpus\t%0, %r1, %r2"
5169 [(set_attr "type" "X0_2cycle")])
5171 (define_insn "insn_v1ddotpusa"
5172 [(set (match_operand:DI 0 "register_operand" "=r")
5173 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
5174 (match_operand:DI 2 "reg_or_0_operand" "rO")
5175 (match_operand:DI 3 "reg_or_0_operand" "rO")]
5176 UNSPEC_INSN_V1DDOTPUSA))]
5177 ""
5178 "v1ddotpusa\t%0, %r2, %r3"
5179 [(set_attr "type" "X0_2cycle")])
5181 (define_insn "insn_v1dotp"
5182 [(set (match_operand:DI 0 "register_operand" "=r")
5183 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5184 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5185 UNSPEC_INSN_V1DOTP))]
5186 ""
5187 "v1dotp\t%0, %r1, %r2"
5188 [(set_attr "type" "X0_2cycle")])
5190 (define_insn "insn_v1dotpa"
5191 [(set (match_operand:DI 0 "register_operand" "=r")
5192 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
5193 (match_operand:DI 2 "reg_or_0_operand" "rO")
5194 (match_operand:DI 3 "reg_or_0_operand" "rO")]
5195 UNSPEC_INSN_V1DOTPA))]
5196 ""
5197 "v1dotpa\t%0, %r2, %r3"
5198 [(set_attr "type" "X0_2cycle")])
5200 (define_insn "insn_v1dotpu"
5201 [(set (match_operand:DI 0 "register_operand" "=r")
5202 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5203 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5204 UNSPEC_INSN_V1DOTPU))]
5205 ""
5206 "v1dotpu\t%0, %r1, %r2"
5207 [(set_attr "type" "X0_2cycle")])
5209 (define_insn "insn_v1dotpua"
5210 [(set (match_operand:DI 0 "register_operand" "=r")
5211 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
5212 (match_operand:DI 2 "reg_or_0_operand" "rO")
5213 (match_operand:DI 3 "reg_or_0_operand" "rO")]
5214 UNSPEC_INSN_V1DOTPUA))]
5215 ""
5216 "v1dotpua\t%0, %r2, %r3"
5217 [(set_attr "type" "X0_2cycle")])
5219 (define_insn "insn_v1dotpus"
5220 [(set (match_operand:DI 0 "register_operand" "=r")
5221 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5222 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5223 UNSPEC_INSN_V1DOTPUS))]
5224 ""
5225 "v1dotpus\t%0, %r1, %r2"
5226 [(set_attr "type" "X0_2cycle")])
5228 (define_insn "insn_v1dotpusa"
5229 [(set (match_operand:DI 0 "register_operand" "=r")
5230 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
5231 (match_operand:DI 2 "reg_or_0_operand" "rO")
5232 (match_operand:DI 3 "reg_or_0_operand" "rO")]
5233 UNSPEC_INSN_V1DOTPUSA))]
5234 ""
5235 "v1dotpusa\t%0, %r2, %r3"
5236 [(set_attr "type" "X0_2cycle")])
5238 (define_insn "insn_v1sadau"
5239 [(set (match_operand:DI 0 "register_operand" "=r")
5240 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
5241 (match_operand:DI 2 "reg_or_0_operand" "rO")
5242 (match_operand:DI 3 "reg_or_0_operand" "rO")]
5243 UNSPEC_INSN_V1SADAU))]
5244 ""
5245 "v1sadau\t%0, %r2, %r3"
5246 [(set_attr "type" "X0_2cycle")])
5248 (define_insn "insn_v1sadu"
5249 [(set (match_operand:DI 0 "register_operand" "=r")
5250 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5251 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5252 UNSPEC_INSN_V1SADU))]
5253 ""
5254 "v1sadu\t%0, %r1, %r2"
5255 [(set_attr "type" "X0_2cycle")])
5257 (define_insn "*insn_v1sadu"
5258 [(set (match_operand:SI 0 "register_operand" "=r")
5259 (truncate:SI
5260 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5261 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5262 UNSPEC_INSN_V1SADU)))]
5263 ""
5264 "v1sadu\t%0, %r1, %r2"
5265 [(set_attr "type" "X0_2cycle")])
5267 (define_insn "insn_v2adiffs"
5268 [(set (match_operand:DI 0 "register_operand" "=r")
5269 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5270 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5271 UNSPEC_INSN_V2ADIFFS))]
5272 ""
5273 "v2adiffs\t%0, %r1, %r2"
5274 [(set_attr "type" "X0_2cycle")])
5276 (define_insn "insn_v2avgs"
5277 [(set (match_operand:DI 0 "register_operand" "=r")
5278 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5279 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5280 UNSPEC_INSN_V2AVGS))]
5281 ""
5282 "v2avgs\t%0, %r1, %r2"
5283 [(set_attr "type" "X0")])
5285 (define_insn "insn_v2dotp"
5286 [(set (match_operand:DI 0 "register_operand" "=r")
5287 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5288 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5289 UNSPEC_INSN_V2DOTP))]
5290 ""
5291 "v2dotp\t%0, %r1, %r2"
5292 [(set_attr "type" "X0_2cycle")])
5294 (define_insn "insn_v2dotpa"
5295 [(set (match_operand:DI 0 "register_operand" "=r")
5296 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
5297 (match_operand:DI 2 "reg_or_0_operand" "rO")
5298 (match_operand:DI 3 "reg_or_0_operand" "rO")]
5299 UNSPEC_INSN_V2DOTPA))]
5300 ""
5301 "v2dotpa\t%0, %r2, %r3"
5302 [(set_attr "type" "X0_2cycle")])
5304 (define_insn "insn_v2mulfsc"
5305 [(set (match_operand:DI 0 "register_operand" "=r")
5306 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5307 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5308 UNSPEC_INSN_V2MULFSC))]
5309 ""
5310 "v2mulfsc\t%0, %r1, %r2"
5311 [(set_attr "type" "X0_2cycle")])
5313 (define_insn "insn_v2sadas"
5314 [(set (match_operand:DI 0 "register_operand" "=r")
5315 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
5316 (match_operand:DI 2 "reg_or_0_operand" "rO")
5317 (match_operand:DI 3 "reg_or_0_operand" "rO")]
5318 UNSPEC_INSN_V2SADAS))]
5319 ""
5320 "v2sadas\t%0, %r2, %r3"
5321 [(set_attr "type" "X0_2cycle")])
5323 (define_insn "insn_v2sadau"
5324 [(set (match_operand:DI 0 "register_operand" "=r")
5325 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
5326 (match_operand:DI 2 "reg_or_0_operand" "rO")
5327 (match_operand:DI 3 "reg_or_0_operand" "rO")]
5328 UNSPEC_INSN_V2SADAU))]
5329 ""
5330 "v2sadau\t%0, %r2, %r3"
5331 [(set_attr "type" "X0_2cycle")])
5333 (define_insn "insn_v2sads"
5334 [(set (match_operand:DI 0 "register_operand" "=r")
5335 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5336 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5337 UNSPEC_INSN_V2SADS))]
5338 ""
5339 "v2sads\t%0, %r1, %r2"
5340 [(set_attr "type" "X0_2cycle")])
5342 (define_insn "*insn_v2sads"
5343 [(set (match_operand:SI 0 "register_operand" "=r")
5344 (truncate:SI
5345 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5346 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5347 UNSPEC_INSN_V2SADS)))]
5348 ""
5349 "v2sads\t%0, %r1, %r2"
5350 [(set_attr "type" "X0_2cycle")])
5352 (define_insn "insn_v2sadu"
5353 [(set (match_operand:DI 0 "register_operand" "=r")
5354 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5355 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5356 UNSPEC_INSN_V2SADU))]
5357 ""
5358 "v2sadu\t%0, %r1, %r2"
5359 [(set_attr "type" "X0_2cycle")])
5361 (define_insn "*insn_v2sadu"
5362 [(set (match_operand:SI 0 "register_operand" "=r")
5363 (truncate:SI
5364 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
5365 (match_operand:DI 2 "reg_or_0_operand" "rO")]
5366 UNSPEC_INSN_V2SADU)))]
5367 ""
5368 "v2sadu\t%0, %r1, %r2"
5369 [(set_attr "type" "X0_2cycle")])
5371 (define_insn "insn_wh64"
5372 [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
5373 UNSPEC_INSN_WH64)
5374 (clobber (mem:BLK (const_int 0)))]
5375 ""
5376 "wh64\t%r0"
5377 [(set_attr "type" "X1")])
5379 \f
5380 ;; Network intrinsics
5382 ;; Note the this barrier is of type "nothing," which is deleted after
5383 ;; the final scheduling pass so that nothing is emitted for it.
5384 (define_insn "tilegx_network_barrier"
5385 [(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)]
5386 ""
5387 "pseudo"
5388 [(set_attr "type" "nothing")
5389 (set_attr "length" "0")])
5391 (define_insn "*netreg_receive"
5392 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,U,m")
5393 (unspec_volatile:DI [(match_operand:DI 1 "netreg_operand" "i,i,i")
5394 (reg:DI TILEGX_NETORDER_REG)]
5395 UNSPEC_NETWORK_RECEIVE))
5396 (clobber (reg:DI TILEGX_NETORDER_REG))]
5398 ""
5399 "@
5400 move\t%0, %N1
5401 st\t%0, %N1
5402 st_add\t%I0, %N1, %i0"
5403 [(set_attr "type" "*,Y2,X1")])
5405 (define_insn "*netreg_send"
5406 [(unspec_volatile:DI
5407 [(match_operand:DI 0 "netreg_operand" "i,i,i,i,i,i")
5408 (match_operand:DI 1 "reg_or_cint_operand" "r,I,J,K,N,P")
5409 (reg:DI TILEGX_NETORDER_REG)]
5410 UNSPEC_NETWORK_SEND)
5411 (clobber (reg:DI TILEGX_NETORDER_REG))]
5412 ""
5413 "@
5414 move\t%N0, %r1
5415 movei\t%N0, %1
5416 moveli\t%N0, %1
5417 shl16insli\t%N0, zero, %h1
5418 v1addi\t%N0, zero, %j1
5419 v2addi\t%N0, zero, %h1"
5420 [(set_attr "type" "*,*,X01,X01,X01,X01")])
5422 (define_expand "tilegx_idn0_receive"
5423 [(parallel
5424 [(set (match_operand:DI 0 "register_operand" "")
5425 (unspec_volatile:DI [(const_int TILEGX_NETREG_IDN0)
5426 (reg:DI TILEGX_NETORDER_REG)]
5427 UNSPEC_NETWORK_RECEIVE))
5428 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5429 "")
5431 (define_expand "tilegx_idn1_receive"
5432 [(parallel
5433 [(set (match_operand:DI 0 "register_operand" "")
5434 (unspec_volatile:DI [(const_int TILEGX_NETREG_IDN1)
5435 (reg:DI TILEGX_NETORDER_REG)]
5436 UNSPEC_NETWORK_RECEIVE))
5437 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5438 "")
5440 (define_expand "tilegx_idn_send"
5441 [(parallel
5442 [(unspec_volatile:DI [(const_int TILEGX_NETREG_IDN0)
5443 (match_operand:DI 0 "reg_or_cint_operand" "")
5444 (reg:DI TILEGX_NETORDER_REG)]
5445 UNSPEC_NETWORK_SEND)
5446 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5447 "")
5449 (define_expand "tilegx_udn0_receive"
5450 [(parallel
5451 [(set (match_operand:DI 0 "register_operand" "")
5452 (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN0)
5453 (reg:DI TILEGX_NETORDER_REG)]
5454 UNSPEC_NETWORK_RECEIVE))
5455 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5456 "")
5458 (define_expand "tilegx_udn1_receive"
5459 [(parallel
5460 [(set (match_operand:DI 0 "register_operand" "")
5461 (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN1)
5462 (reg:DI TILEGX_NETORDER_REG)]
5463 UNSPEC_NETWORK_RECEIVE))
5464 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5465 "")
5467 (define_expand "tilegx_udn2_receive"
5468 [(parallel
5469 [(set (match_operand:DI 0 "register_operand" "")
5470 (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN2)
5471 (reg:DI TILEGX_NETORDER_REG)]
5472 UNSPEC_NETWORK_RECEIVE))
5473 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5474 "")
5476 (define_expand "tilegx_udn3_receive"
5477 [(parallel
5478 [(set (match_operand:DI 0 "register_operand" "")
5479 (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN3)
5480 (reg:DI TILEGX_NETORDER_REG)]
5481 UNSPEC_NETWORK_RECEIVE))
5482 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5483 "")
5485 (define_expand "tilegx_udn_send"
5486 [(parallel
5487 [(unspec_volatile:DI [(const_int TILEGX_NETREG_UDN0)
5488 (match_operand:DI 0 "reg_or_cint_operand" "")
5489 (reg:DI TILEGX_NETORDER_REG)]
5490 UNSPEC_NETWORK_SEND)
5491 (clobber (reg:DI TILEGX_NETORDER_REG))])]
5492 "")
5494 (define_insn "*netreg_adddi_to_network"
5495 [(unspec_volatile:DI
5496 [(match_operand:DI 0 "netreg_operand" "i,i,i")
5497 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rO,rO,rO")
5498 (match_operand:DI 2 "add_operand" "r,I,JT"))
5499 (reg:DI TILEGX_NETORDER_REG)]
5500 UNSPEC_NETWORK_SEND)
5501 (clobber (reg:DI TILEGX_NETORDER_REG))]
5502 ""
5503 "@
5504 add\t%N0, %r1, %2
5505 addi\t%N0, %r1, %2
5506 addli\t%N0, %r1, %H2"
5507 [(set_attr "type" "*,*,X01")])
5509 (define_insn "*netreg_adddi_from_network"
5510 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
5511 (plus:DI (unspec_volatile:DI
5512 [(match_operand:DI 1 "netreg_operand" "%i,i,i")
5513 (reg:DI TILEGX_NETORDER_REG)]
5514 UNSPEC_NETWORK_RECEIVE)
5515 (match_operand:DI 2 "add_operand" "rO,I,JT")))
5516 (clobber (reg:DI TILEGX_NETORDER_REG))]
5517 ""
5518 "@
5519 add\t%0, %N1, %r2
5520 addi\t%0, %N1, %2
5521 addli\t%0, %N1, %H2"
5522 [(set_attr "type" "*,*,X01")])
5524 \f
5525 ;;
5526 ;; Stack protector instructions.
5527 ;;
5529 (define_expand "stack_protect_set"
5530 [(set (match_operand 0 "nonautoincmem_operand" "")
5531 (match_operand 1 "nonautoincmem_operand" ""))]
5532 ""
5533 {
5534 #ifdef TARGET_THREAD_SSP_OFFSET
5535 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
5536 rtx ssp_addr = gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET));
5537 rtx ssp = gen_reg_rtx (Pmode);
5539 emit_insn (gen_rtx_SET (ssp, ssp_addr));
5541 operands[1] = gen_rtx_MEM (Pmode, ssp);
5542 #endif
5544 if (TARGET_32BIT)
5545 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
5546 else
5547 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
5549 DONE;
5550 })
5552 (define_insn "stack_protect_setsi"
5553 [(set (match_operand:SI 0 "nonautoincmem_operand" "=U")
5554 (unspec:SI [(match_operand:SI 1 "nonautoincmem_operand" "U")]
5555 UNSPEC_SP_SET))
5556 (set (match_scratch:SI 2 "=&r") (const_int 0))]
5557 ""
5558 "ld4s\t%2, %1; { st4\t%0, %2; move\t%2, zero }"
5559 [(set_attr "length" "16")
5560 (set_attr "type" "cannot_bundle_3cycle")])
5562 (define_insn "stack_protect_setdi"
5563 [(set (match_operand:DI 0 "nonautoincmem_operand" "=U")
5564 (unspec:DI [(match_operand:DI 1 "nonautoincmem_operand" "U")]
5565 UNSPEC_SP_SET))
5566 (set (match_scratch:DI 2 "=&r") (const_int 0))]
5567 ""
5568 "ld\t%2, %1; { st\t%0, %2; move\t%2, zero }"
5569 [(set_attr "length" "16")
5570 (set_attr "type" "cannot_bundle_3cycle")])
5572 (define_expand "stack_protect_test"
5573 [(match_operand 0 "nonautoincmem_operand" "")
5574 (match_operand 1 "nonautoincmem_operand" "")
5575 (match_operand 2 "" "")]
5576 ""
5577 {
5578 rtx compare_result;
5579 rtx bcomp, loc_ref;
5581 #ifdef TARGET_THREAD_SSP_OFFSET
5582 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
5583 rtx ssp_addr = gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET));
5584 rtx ssp = gen_reg_rtx (Pmode);
5586 emit_insn (gen_rtx_SET (ssp, ssp_addr));
5588 operands[1] = gen_rtx_MEM (Pmode, ssp);
5589 #endif
5591 compare_result = gen_reg_rtx (Pmode);
5593 if (TARGET_32BIT)
5594 emit_insn (gen_stack_protect_testsi (compare_result, operands[0],
5595 operands[1]));
5596 else
5597 emit_insn (gen_stack_protect_testdi (compare_result, operands[0],
5598 operands[1]));
5600 bcomp = gen_rtx_NE (SImode, compare_result, const0_rtx);
5602 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[2]);
5604 emit_jump_insn (gen_rtx_SET (pc_rtx,
5605 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
5606 loc_ref, pc_rtx)));
5608 DONE;
5609 })
5611 (define_insn "stack_protect_testsi"
5612 [(set (match_operand:SI 0 "register_operand" "=&r")
5613 (unspec:SI [(match_operand:SI 1 "nonautoincmem_operand" "U")
5614 (match_operand:SI 2 "nonautoincmem_operand" "U")]
5615 UNSPEC_SP_TEST))
5616 (set (match_scratch:SI 3 "=&r") (const_int 0))]
5617 ""
5618 "ld4s\t%0, %1; ld4s\t%3, %2; { cmpeq\t%0, %0, %3; move\t%3, zero }"
5619 [(set_attr "length" "24")
5620 (set_attr "type" "cannot_bundle_4cycle")])
5622 (define_insn "stack_protect_testdi"
5623 [(set (match_operand:DI 0 "register_operand" "=&r")
5624 (unspec:DI [(match_operand:DI 1 "nonautoincmem_operand" "U")
5625 (match_operand:DI 2 "nonautoincmem_operand" "U")]
5626 UNSPEC_SP_TEST))
5627 (set (match_scratch:DI 3 "=&r") (const_int 0))]
5628 ""
5629 "ld\t%0, %1; ld\t%3, %2; { cmpeq\t%0, %0, %3; move\t%3, zero }"
5630 [(set_attr "length" "24")
5631 (set_attr "type" "cannot_bundle_4cycle")])
5633 (include "sync.md")