gcc/config/rs6000/rs6000-c.c

   1 /* Subroutines for the C front end on the PowerPC architecture.
   2    Copyright (C) 2002-2017 Free Software Foundation, Inc.
   3
   4    Contributed by Zack Weinberg <zack@codesourcery.com>
   5    and Paolo Bonzini <bonzini@gnu.org>
   6
   7    This file is part of GCC.
   8
   9    GCC is free software; you can redistribute it and/or modify it
  10    under the terms of the GNU General Public License as published
  11    by the Free Software Foundation; either version 3, or (at your
  12    option) any later version.
  13
  14    GCC is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GCC; see the file COPYING3.  If not see
  21    <http://www.gnu.org/licenses/>.  */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "coretypes.h"
  26 #include "target.h"
  27 #include "c-family/c-common.h"
  28 #include "memmodel.h"
  29 #include "tm_p.h"
  30 #include "stringpool.h"
  31 #include "stor-layout.h"
  32 #include "c-family/c-pragma.h"
  33 #include "langhooks.h"
  34 #include "c/c-tree.h"
  35
  36
  37
  38 /* Handle the machine specific pragma longcall.  Its syntax is
  39
  40    # pragma longcall ( TOGGLE )
  41
  42    where TOGGLE is either 0 or 1.
  43
  44    rs6000_default_long_calls is set to the value of TOGGLE, changing
  45    whether or not new function declarations receive a longcall
  46    attribute by default.  */
  47
  48 #define SYNTAX_ERROR(gmsgid) do {                                       \
  49   warning (OPT_Wpragmas, gmsgid);                                       \
  50   warning (OPT_Wpragmas, "ignoring malformed #pragma longcall");        \
  51   return;                                                               \
  52 } while (0)
  53
  54 void
  55 rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED)
  56 {
  57   tree x, n;
  58
  59   /* If we get here, generic code has already scanned the directive
  60      leader and the word "longcall".  */
  61
  62   if (pragma_lex (&x) != CPP_OPEN_PAREN)
  63     SYNTAX_ERROR ("missing open paren");
  64   if (pragma_lex (&n) != CPP_NUMBER)
  65     SYNTAX_ERROR ("missing number");
  66   if (pragma_lex (&x) != CPP_CLOSE_PAREN)
  67     SYNTAX_ERROR ("missing close paren");
  68
  69   if (n != integer_zero_node && n != integer_one_node)
  70     SYNTAX_ERROR ("number must be 0 or 1");
  71
  72   if (pragma_lex (&x) != CPP_EOF)
  73     warning (OPT_Wpragmas, "junk at end of #pragma longcall");
  74
  75   rs6000_default_long_calls = (n == integer_one_node);
  76 }
  77
  78 /* Handle defining many CPP flags based on TARGET_xxx.  As a general
  79    policy, rather than trying to guess what flags a user might want a
  80    #define for, it's better to define a flag for everything.  */
  81
  82 #define builtin_define(TXT) cpp_define (pfile, TXT)
  83 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
  84
  85 /* Keep the AltiVec keywords handy for fast comparisons.  */
  86 static GTY(()) tree __vector_keyword;
  87 static GTY(()) tree vector_keyword;
  88 static GTY(()) tree __pixel_keyword;
  89 static GTY(()) tree pixel_keyword;
  90 static GTY(()) tree __bool_keyword;
  91 static GTY(()) tree bool_keyword;
  92 static GTY(()) tree _Bool_keyword;
  93 static GTY(()) tree __int128_type;
  94 static GTY(()) tree __uint128_type;
  95
  96 /* Preserved across calls.  */
  97 static tree expand_bool_pixel;
  98
  99 static cpp_hashnode *
 100 altivec_categorize_keyword (const cpp_token *tok)
 101 {
 102   if (tok->type == CPP_NAME)
 103     {
 104       cpp_hashnode *ident = tok->val.node.node;
 105
 106       if (ident == C_CPP_HASHNODE (vector_keyword))
 107         return C_CPP_HASHNODE (__vector_keyword);
 108
 109       if (ident == C_CPP_HASHNODE (pixel_keyword))
 110         return C_CPP_HASHNODE (__pixel_keyword);
 111
 112       if (ident == C_CPP_HASHNODE (bool_keyword))
 113         return C_CPP_HASHNODE (__bool_keyword);
 114
 115       if (ident == C_CPP_HASHNODE (_Bool_keyword))
 116         return C_CPP_HASHNODE (__bool_keyword);
 117
 118       return ident;
 119     }
 120
 121   return 0;
 122 }
 123
 124 static void
 125 init_vector_keywords (void)
 126 {
 127   /* Keywords without two leading underscores are context-sensitive, and hence
 128      implemented as conditional macros, controlled by the
 129      rs6000_macro_to_expand() function below.  If we have ISA 2.07 64-bit
 130      support, record the __int128_t and __uint128_t types.  */
 131
 132   __vector_keyword = get_identifier ("__vector");
 133   C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
 134
 135   __pixel_keyword = get_identifier ("__pixel");
 136   C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL;
 137
 138   __bool_keyword = get_identifier ("__bool");
 139   C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL;
 140
 141   vector_keyword = get_identifier ("vector");
 142   C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL;
 143
 144   pixel_keyword = get_identifier ("pixel");
 145   C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL;
 146
 147   bool_keyword = get_identifier ("bool");
 148   C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL;
 149
 150   _Bool_keyword = get_identifier ("_Bool");
 151   C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL;
 152
 153   if (TARGET_VADDUQM)
 154     {
 155       __int128_type = get_identifier ("__int128_t");
 156       __uint128_type = get_identifier ("__uint128_t");
 157     }
 158 }
 159
 160 /* Helper function to find out which RID_INT_N_* code is the one for
 161    __int128, if any.  Returns RID_MAX+1 if none apply, which is safe
 162    (for our purposes, since we always expect to have __int128) to
 163    compare against.  */
 164 static int
 165 rid_int128(void)
 166 {
 167   int i;
 168
 169   for (i = 0; i < NUM_INT_N_ENTS; i ++)
 170     if (int_n_enabled_p[i]
 171         && int_n_data[i].bitsize == 128)
 172       return RID_INT_N_0 + i;
 173
 174   return RID_MAX + 1;
 175 }
 176
 177 /* Called to decide whether a conditional macro should be expanded.
 178    Since we have exactly one such macro (i.e, 'vector'), we do not
 179    need to examine the 'tok' parameter.  */
 180
 181 static cpp_hashnode *
 182 rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
 183 {
 184   cpp_hashnode *expand_this = tok->val.node.node;
 185   cpp_hashnode *ident;
 186
 187   /* If the current machine does not have altivec, don't look for the
 188      keywords.  */
 189   if (!TARGET_ALTIVEC)
 190     return NULL;
 191
 192   ident = altivec_categorize_keyword (tok);
 193
 194   if (ident != expand_this)
 195     expand_this = NULL;
 196
 197   if (ident == C_CPP_HASHNODE (__vector_keyword))
 198     {
 199       int idx = 0;
 200       do
 201         tok = cpp_peek_token (pfile, idx++);
 202       while (tok->type == CPP_PADDING);
 203       ident = altivec_categorize_keyword (tok);
 204
 205       if (ident == C_CPP_HASHNODE (__pixel_keyword))
 206         {
 207           expand_this = C_CPP_HASHNODE (__vector_keyword);
 208           expand_bool_pixel = __pixel_keyword;
 209         }
 210       else if (ident == C_CPP_HASHNODE (__bool_keyword))
 211         {
 212           expand_this = C_CPP_HASHNODE (__vector_keyword);
 213           expand_bool_pixel = __bool_keyword;
 214         }
 215       /* The boost libraries have code with Iterator::vector vector in it.  If
 216          we allow the normal handling, this module will be called recursively,
 217          and the vector will be skipped.; */
 218       else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword)))
 219         {
 220           enum rid rid_code = (enum rid)(ident->rid_code);
 221           enum node_type itype = ident->type;
 222           /* If there is a function-like macro, check if it is going to be
 223              invoked with or without arguments.  Without following ( treat
 224              it like non-macro, otherwise the following cpp_get_token eats
 225              what should be preserved.  */
 226           if (itype == NT_MACRO && cpp_fun_like_macro_p (ident))
 227             {
 228               int idx2 = idx;
 229               do
 230                 tok = cpp_peek_token (pfile, idx2++);
 231               while (tok->type == CPP_PADDING);
 232               if (tok->type != CPP_OPEN_PAREN)
 233                 itype = NT_VOID;
 234             }
 235           if (itype == NT_MACRO)
 236             {
 237               do
 238                 (void) cpp_get_token (pfile);
 239               while (--idx > 0);
 240               do
 241                 tok = cpp_peek_token (pfile, idx++);
 242               while (tok->type == CPP_PADDING);
 243               ident = altivec_categorize_keyword (tok);
 244               if (ident == C_CPP_HASHNODE (__pixel_keyword))
 245                 {
 246                   expand_this = C_CPP_HASHNODE (__vector_keyword);
 247                   expand_bool_pixel = __pixel_keyword;
 248                   rid_code = RID_MAX;
 249                 }
 250               else if (ident == C_CPP_HASHNODE (__bool_keyword))
 251                 {
 252                   expand_this = C_CPP_HASHNODE (__vector_keyword);
 253                   expand_bool_pixel = __bool_keyword;
 254                   rid_code = RID_MAX;
 255                 }
 256               else if (ident)
 257                 rid_code = (enum rid)(ident->rid_code);
 258             }
 259
 260           if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
 261               || rid_code == RID_SHORT || rid_code == RID_SIGNED
 262               || rid_code == RID_INT || rid_code == RID_CHAR
 263               || rid_code == RID_FLOAT
 264               || (rid_code == RID_DOUBLE && TARGET_VSX)
 265               || (rid_code == rid_int128 () && TARGET_VADDUQM))
 266             {
 267               expand_this = C_CPP_HASHNODE (__vector_keyword);
 268               /* If the next keyword is bool or pixel, it
 269                  will need to be expanded as well.  */
 270               do
 271                 tok = cpp_peek_token (pfile, idx++);
 272               while (tok->type == CPP_PADDING);
 273               ident = altivec_categorize_keyword (tok);
 274
 275               if (ident == C_CPP_HASHNODE (__pixel_keyword))
 276                 expand_bool_pixel = __pixel_keyword;
 277               else if (ident == C_CPP_HASHNODE (__bool_keyword))
 278                 expand_bool_pixel = __bool_keyword;
 279               else
 280                 {
 281                   /* Try two tokens down, too.  */
 282                   do
 283                     tok = cpp_peek_token (pfile, idx++);
 284                   while (tok->type == CPP_PADDING);
 285                   ident = altivec_categorize_keyword (tok);
 286                   if (ident == C_CPP_HASHNODE (__pixel_keyword))
 287                     expand_bool_pixel = __pixel_keyword;
 288                   else if (ident == C_CPP_HASHNODE (__bool_keyword))
 289                     expand_bool_pixel = __bool_keyword;
 290                 }
 291             }
 292
 293           /* Support vector __int128_t, but we don't need to worry about bool
 294              or pixel on this type.  */
 295           else if (TARGET_VADDUQM
 296                    && (ident == C_CPP_HASHNODE (__int128_type)
 297                        || ident == C_CPP_HASHNODE (__uint128_type)))
 298             expand_this = C_CPP_HASHNODE (__vector_keyword);
 299         }
 300     }
 301   else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword))
 302     {
 303       expand_this = C_CPP_HASHNODE (__pixel_keyword);
 304       expand_bool_pixel = 0;
 305     }
 306   else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword))
 307     {
 308       expand_this = C_CPP_HASHNODE (__bool_keyword);
 309       expand_bool_pixel = 0;
 310     }
 311
 312   return expand_this;
 313 }
 314
 315
 316 /* Define or undefine a single macro.  */
 317
 318 static void
 319 rs6000_define_or_undefine_macro (bool define_p, const char *name)
 320 {
 321   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 322     fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name);
 323
 324   if (define_p)
 325     cpp_define (parse_in, name);
 326   else
 327     cpp_undef (parse_in, name);
 328 }
 329
 330 /* Define or undefine macros based on the current target.  If the user does
 331    #pragma GCC target, we need to adjust the macros dynamically.  Note, some of
 332    the options needed for builtins have been moved to separate variables, so
 333    have both the target flags and the builtin flags as arguments.  */
 334
 335 void
 336 rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
 337                              HOST_WIDE_INT bu_mask)
 338 {
 339   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 340     fprintf (stderr,
 341              "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX
 342              ", " HOST_WIDE_INT_PRINT_HEX ")\n",
 343              (define_p) ? "define" : "undef",
 344              flags, bu_mask);
 345
 346   /* Each of the flags mentioned below controls whether certain
 347      preprocessor macros will be automatically defined when
 348      preprocessing source files for compilation by this compiler.
 349      While most of these flags can be enabled or disabled
 350      explicitly by specifying certain command-line options when
 351      invoking the compiler, there are also many ways in which these
 352      flags are enabled or disabled implicitly, based on compiler
 353      defaults, configuration choices, and on the presence of certain
 354      related command-line options.  Many, but not all, of these
 355      implicit behaviors can be found in file "rs6000.c", the
 356      rs6000_option_override_internal() function.
 357
 358      In general, each of the flags may be automatically enabled in
 359      any of the following conditions:
 360
 361      1. If no -mcpu target is specified on the command line and no
 362         --with-cpu target is specified to the configure command line
 363         and the TARGET_DEFAULT macro for this default cpu host
 364         includes the flag, and the flag has not been explicitly disabled
 365         by command-line options.
 366
 367      2. If the target specified with -mcpu=target on the command line, or
 368         in the absence of a -mcpu=target command-line option, if the
 369         target specified using --with-cpu=target on the configure
 370         command line, is disqualified because the associated binary
 371         tools (e.g. the assembler) lack support for the requested cpu,
 372         and the TARGET_DEFAULT macro for this default cpu host
 373         includes the flag, and the flag has not been explicitly disabled
 374         by command-line options.
 375
 376      3. If either of the above two conditions apply except that the
 377         TARGET_DEFAULT macro is defined to equal zero, and
 378         TARGET_POWERPC64 and
 379         a) BYTES_BIG_ENDIAN and the flag to be enabled is either
 380            MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64"
 381            target), or
 382         b) !BYTES_BIG_ENDIAN and the flag to be enabled is either
 383            MASK_POWERPC64 or it is one of the flags included in
 384            ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target).
 385
 386      4. If a cpu has been requested with a -mcpu=target command-line option
 387         and this cpu has not been disqualified due to shortcomings of the
 388         binary tools, and the set of flags associated with the requested cpu
 389         include the flag to be enabled.  See rs6000-cpus.def for macro
 390         definitions that represent various ABI standards
 391         (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of
 392         the specific flags that are associated with each of the cpu
 393         choices that can be specified as the target of a -mcpu=target
 394         compile option, or as the the target of a --with-cpu=target
 395         configure option.  Target flags that are specified in either
 396         of these two ways are considered "implicit" since the flags
 397         are not mentioned specifically by name.
 398
 399         Additional documentation describing behavior specific to
 400         particular flags is provided below, immediately preceding the
 401         use of each relevant flag.
 402
 403      5. If there is no -mcpu=target command-line option, and the cpu
 404         requested by a --with-cpu=target command-line option has not
 405         been disqualified due to shortcomings of the binary tools, and
 406         the set of flags associated with the specified target include
 407         the flag to be enabled.  See the notes immediately above for a
 408         summary of the flags associated with particular cpu
 409         definitions.  */
 410
 411   /* rs6000_isa_flags based options.  */
 412   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
 413   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 414     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
 415   if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
 416     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
 417   if ((flags & OPTION_MASK_POWERPC64) != 0)
 418     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
 419   if ((flags & OPTION_MASK_MFCRF) != 0)
 420     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
 421   if ((flags & OPTION_MASK_POPCNTB) != 0)
 422     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
 423   if ((flags & OPTION_MASK_FPRND) != 0)
 424     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
 425   if ((flags & OPTION_MASK_CMPB) != 0)
 426     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
 427   if ((flags & OPTION_MASK_MFPGPR) != 0)
 428     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
 429   if ((flags & OPTION_MASK_POPCNTD) != 0)
 430     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
 431   /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
 432      turned on in the following condition:
 433      1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not
 434         explicitly disabled.
 435         Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to
 436         have been turned on explicitly.
 437      Note that the OPTION_MASK_DIRECT_MOVE flag is automatically
 438      turned off in any of the following conditions:
 439      1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly
 440         disabled and OPTION_MASK_DIRECT_MOVE was not explicitly
 441         enabled.
 442      2. TARGET_VSX is off.  */
 443   if ((flags & OPTION_MASK_DIRECT_MOVE) != 0)
 444     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
 445   if ((flags & OPTION_MASK_MODULO) != 0)
 446     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
 447   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
 448     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
 449   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
 450     rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
 451   /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on
 452      in any of the following conditions:
 453      1. The command line specifies either -maltivec=le or -maltivec=be.
 454      2. The operating system is Darwin and it is configured for 64
 455         bit.  (See darwin_rs6000_override_options.)
 456      3. The operating system is Darwin and the operating system
 457         version is 10.5 or higher and the user has not explicitly
 458         disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and
 459         the compiler is not producing code for integration within the
 460         kernel.  (See darwin_rs6000_override_options.)
 461      Note that the OPTION_MASK_ALTIVEC flag is automatically turned
 462      off in any of the following conditions:
 463      1. The operating system does not support saving of AltiVec
 464         registers (OS_MISSING_ALTIVEC).
 465      2. If an inner context (as introduced by
 466         __attribute__((__target__())) or #pragma GCC target()
 467         requests a target that normally enables the
 468         OPTION_MASK_ALTIVEC flag but the outer-most "main target"
 469         does not support the rs6000_altivec_abi, this flag is
 470         turned off for the inner context unless OPTION_MASK_ALTIVEC
 471         was explicitly enabled for the inner context.  */
 472   if ((flags & OPTION_MASK_ALTIVEC) != 0)
 473     {
 474       const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
 475       rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
 476       rs6000_define_or_undefine_macro (define_p, vec_str);
 477
 478           /* Define this when supporting context-sensitive keywords.  */
 479       if (!flag_iso)
 480         rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
 481     }
 482   /* Note that the OPTION_MASK_VSX flag is automatically turned on in
 483      the following conditions:
 484      1. TARGET_P8_VECTOR is explicitly turned on and the OPTION_MASK_VSX
 485         was not explicitly turned off.  Hereafter, the OPTION_MASK_VSX
 486         flag is considered to have been explicitly turned on.
 487      Note that the OPTION_MASK_VSX flag is automatically turned off in
 488      the following conditions:
 489      1. The operating system does not support saving of AltiVec
 490         registers (OS_MISSING_ALTIVEC).
 491      2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT,
 492         or TARGET_DOUBLE_FLOAT are turned off.  Hereafter, the
 493         OPTION_MASK_VSX flag is considered to have been turned off
 494         explicitly.
 495      3. If TARGET_PAIRED_FLOAT was enabled.  Hereafter, the
 496         OPTION_MASK_VSX flag is considered to have been turned off
 497         explicitly.
 498      4. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
 499         compilation context, or if it is turned on by any means in an
 500         inner compilation context.  Hereafter, the OPTION_MASK_VSX
 501         flag is considered to have been turned off explicitly.
 502      5. If TARGET_ALTIVEC was explicitly disabled.  Hereafter, the
 503         OPTION_MASK_VSX flag is considered to have been turned off
 504         explicitly.
 505      6. If an inner context (as introduced by
 506         __attribute__((__target__())) or #pragma GCC target()
 507         requests a target that normally enables the
 508         OPTION_MASK_VSX flag but the outer-most "main target"
 509         does not support the rs6000_altivec_abi, this flag is
 510         turned off for the inner context unless OPTION_MASK_VSX
 511         was explicitly enabled for the inner context.  */
 512   if ((flags & OPTION_MASK_VSX) != 0)
 513     rs6000_define_or_undefine_macro (define_p, "__VSX__");
 514   if ((flags & OPTION_MASK_HTM) != 0)
 515     {
 516       rs6000_define_or_undefine_macro (define_p, "__HTM__");
 517       /* Tell the user that our HTM insn patterns act as memory barriers.  */
 518       rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__");
 519     }
 520   /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
 521      on in the following conditions:
 522      1. TARGET_P9_VECTOR is explicitly turned on and
 523         OPTION_MASK_P8_VECTOR is not explicitly turned off.
 524         Hereafter, the OPTION_MASK_P8_VECTOR flag is considered to
 525         have been turned off explicitly.
 526      Note that the OPTION_MASK_P8_VECTOR flag is automatically turned
 527      off in the following conditions:
 528      1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX
 529         were turned off explicitly and OPTION_MASK_P8_VECTOR flag was
 530         not turned on explicitly.
 531      2. If TARGET_ALTIVEC is turned off.  Hereafter, the
 532         OPTION_MASK_P8_VECTOR flag is considered to have been turned off
 533         explicitly.
 534      3. If TARGET_VSX is turned off and OPTION_MASK_P8_VECTOR was not
 535         explicitly enabled.  If TARGET_VSX is explicitly enabled, the
 536         OPTION_MASK_P8_VECTOR flag is hereafter also considered to
 537         have been turned off explicitly.  */
 538   if ((flags & OPTION_MASK_P8_VECTOR) != 0)
 539     rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__");
 540   /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned
 541      off in the following conditions:
 542      1. If TARGET_P8_VECTOR is turned off and OPTION_MASK_P9_VECTOR is
 543         not turned on explicitly. Hereafter, if OPTION_MASK_P8_VECTOR
 544         was turned on explicitly, the OPTION_MASK_P9_VECTOR flag is
 545         also considered to have been turned off explicitly.
 546      Note that the OPTION_MASK_P9_VECTOR is automatically turned on
 547      in the following conditions:
 548      1. If TARGET_P9_MINMAX was turned on explicitly.
 549         Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to
 550         have been turned on explicitly.  */
 551   if ((flags & OPTION_MASK_P9_VECTOR) != 0)
 552     rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__");
 553   /* Note that the OPTION_MASK_QUAD_MEMORY flag is automatically
 554      turned off in the following conditions:
 555      1. If TARGET_POWERPC64 is turned off.
 556      2. If WORDS_BIG_ENDIAN is false (non-atomic quad memory
 557         load/store are disabled on little endian).  */
 558   if ((flags & OPTION_MASK_QUAD_MEMORY) != 0)
 559     rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__");
 560   /* Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is automatically
 561      turned off in the following conditions:
 562      1. If TARGET_POWERPC64 is turned off.
 563      Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is
 564      automatically turned on in the following conditions:
 565      1. If TARGET_QUAD_MEMORY and this flag was not explicitly
 566         disabled.  */
 567   if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
 568     rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__");
 569   /* Note that the OPTION_MASK_CRYPTO flag is automatically turned off
 570      in the following conditions:
 571      1. If any of TARGET_HARD_FLOAT or TARGET_ALTIVEC or TARGET_VSX
 572         are turned off explicitly and OPTION_MASK_CRYPTO is not turned
 573         on explicitly.
 574      2. If TARGET_ALTIVEC is turned off.  */
 575   if ((flags & OPTION_MASK_CRYPTO) != 0)
 576     rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
 577   if ((flags & OPTION_MASK_FLOAT128_KEYWORD) != 0)
 578     {
 579       rs6000_define_or_undefine_macro (define_p, "__FLOAT128__");
 580       if (define_p)
 581         rs6000_define_or_undefine_macro (true, "__float128=__ieee128");
 582       else
 583         rs6000_define_or_undefine_macro (false, "__float128");
 584     }
 585   /* OPTION_MASK_FLOAT128_HARDWARE can be turned on if -mcpu=power9 is used or
 586      via the target attribute/pragma.  */
 587   if ((flags & OPTION_MASK_FLOAT128_HW) != 0)
 588     rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__");
 589
 590   /* options from the builtin masks.  */
 591   /* Note that RS6000_BTM_PAIRED is enabled only if
 592      TARGET_PAIRED_FLOAT is enabled (e.g. -mpaired).  */
 593   if ((bu_mask & RS6000_BTM_PAIRED) != 0)
 594     rs6000_define_or_undefine_macro (define_p, "__PAIRED__");
 595   /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
 596      PROCESSOR_CELL) (e.g. -mcpu=cell).  */
 597   if ((bu_mask & RS6000_BTM_CELL) != 0)
 598     rs6000_define_or_undefine_macro (define_p, "__PPU__");
 599 }
 600
 601 void
 602 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 603 {
 604   /* Define all of the common macros.  */
 605   rs6000_target_modify_macros (true, rs6000_isa_flags,
 606                                rs6000_builtin_mask_calculate ());
 607
 608   if (TARGET_FRE)
 609     builtin_define ("__RECIP__");
 610   if (TARGET_FRES)
 611     builtin_define ("__RECIPF__");
 612   if (TARGET_FRSQRTE)
 613     builtin_define ("__RSQRTE__");
 614   if (TARGET_FRSQRTES)
 615     builtin_define ("__RSQRTEF__");
 616   if (TARGET_FLOAT128_TYPE)
 617     builtin_define ("__FLOAT128_TYPE__");
 618   if (TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (TFmode))
 619     builtin_define ("__ibm128=long double");
 620 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
 621   builtin_define ("__BUILTIN_CPU_SUPPORTS__");
 622 #endif
 623
 624   if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM)
 625     {
 626       /* Define the AltiVec syntactic elements.  */
 627       builtin_define ("__vector=__attribute__((altivec(vector__)))");
 628       builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short");
 629       builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned");
 630
 631       if (!flag_iso)
 632         {
 633           builtin_define ("vector=vector");
 634           builtin_define ("pixel=pixel");
 635           builtin_define ("bool=bool");
 636           builtin_define ("_Bool=_Bool");
 637           init_vector_keywords ();
 638
 639           /* Enable context-sensitive macros.  */
 640           cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
 641         }
 642     }
 643   if (!TARGET_HARD_FLOAT
 644       || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
 645     builtin_define ("_SOFT_DOUBLE");
 646   /* Used by lwarx/stwcx. errata work-around.  */
 647   if (rs6000_cpu == PROCESSOR_PPC405)
 648     builtin_define ("__PPC405__");
 649   /* Used by libstdc++.  */
 650   if (TARGET_NO_LWSYNC)
 651     builtin_define ("__NO_LWSYNC__");
 652
 653   if (TARGET_EXTRA_BUILTINS)
 654     {
 655       /* For the VSX builtin functions identical to Altivec functions, just map
 656          the altivec builtin into the vsx version (the altivec functions
 657          generate VSX code if -mvsx).  */
 658       builtin_define ("__builtin_vsx_xxland=__builtin_vec_and");
 659       builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc");
 660       builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor");
 661       builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or");
 662       builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor");
 663       builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel");
 664       builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm");
 665
 666       /* Also map the a and m versions of the multiply/add instructions to the
 667          builtin for people blindly going off the instruction manual.  */
 668       builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp");
 669       builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp");
 670       builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp");
 671       builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp");
 672       builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp");
 673       builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp");
 674       builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp");
 675       builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp");
 676       builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp");
 677       builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp");
 678       builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp");
 679       builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp");
 680       builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp");
 681       builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp");
 682       builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp");
 683       builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp");
 684     }
 685
 686   /* Tell users they can use __builtin_bswap{16,64}.  */
 687   builtin_define ("__HAVE_BSWAP__");
 688
 689   /* May be overridden by target configuration.  */
 690   RS6000_CPU_CPP_ENDIAN_BUILTINS();
 691
 692   if (TARGET_LONG_DOUBLE_128)
 693     {
 694       builtin_define ("__LONG_DOUBLE_128__");
 695       builtin_define ("__LONGDOUBLE128");
 696
 697       if (TARGET_IEEEQUAD)
 698         builtin_define ("__LONG_DOUBLE_IEEE128__");
 699       else
 700         builtin_define ("__LONG_DOUBLE_IBM128__");
 701     }
 702
 703   switch (TARGET_CMODEL)
 704     {
 705       /* Deliberately omit __CMODEL_SMALL__ since that was the default
 706          before --mcmodel support was added.  */
 707     case CMODEL_MEDIUM:
 708       builtin_define ("__CMODEL_MEDIUM__");
 709       break;
 710     case CMODEL_LARGE:
 711       builtin_define ("__CMODEL_LARGE__");
 712       break;
 713     default:
 714       break;
 715     }
 716
 717   switch (rs6000_current_abi)
 718     {
 719     case ABI_V4:
 720       builtin_define ("_CALL_SYSV");
 721       break;
 722     case ABI_AIX:
 723       builtin_define ("_CALL_AIXDESC");
 724       builtin_define ("_CALL_AIX");
 725       builtin_define ("_CALL_ELF=1");
 726       break;
 727     case ABI_ELFv2:
 728       builtin_define ("_CALL_ELF=2");
 729       break;
 730     case ABI_DARWIN:
 731       builtin_define ("_CALL_DARWIN");
 732       break;
 733     default:
 734       break;
 735     }
 736
 737   /* Vector element order.  */
 738   if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
 739     builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__");
 740   else
 741     builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
 742
 743   /* Let the compiled code know if 'f' class registers will not be available.  */
 744   if (TARGET_SOFT_FLOAT)
 745     builtin_define ("__NO_FPRS__");
 746
 747   /* Whether aggregates passed by value are aligned to a 16 byte boundary
 748      if their alignment is 16 bytes or larger.  */
 749   if ((TARGET_MACHO && rs6000_darwin64_abi)
 750       || DEFAULT_ABI == ABI_ELFv2
 751       || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
 752     builtin_define ("__STRUCT_PARM_ALIGN__=16");
 753
 754   /* Generate defines for Xilinx FPU. */
 755   if (rs6000_xilinx_fpu)
 756     {
 757       builtin_define ("_XFPU");
 758       if (rs6000_single_float && ! rs6000_double_float)
 759         {
 760           if (rs6000_simple_fpu)
 761             builtin_define ("_XFPU_SP_LITE");
 762           else
 763             builtin_define ("_XFPU_SP_FULL");
 764         }
 765       if (rs6000_double_float)
 766         {
 767           if (rs6000_simple_fpu)
 768             builtin_define ("_XFPU_DP_LITE");
 769           else
 770             builtin_define ("_XFPU_DP_FULL");
 771         }
 772     }
 773 }
 774
 775 \f
 776 struct altivec_builtin_types
 777 {
 778   enum rs6000_builtins code;
 779   enum rs6000_builtins overloaded_code;
 780   signed char ret_type;
 781   signed char op1;
 782   signed char op2;
 783   signed char op3;
 784 };
 785
 786 const struct altivec_builtin_types altivec_overloaded_builtins[] = {
 787   /* Unary AltiVec/VSX builtins.  */
 788   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI,
 789     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
 790   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI,
 791     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
 792   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI,
 793     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
 794   { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI,
 795     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
 796   { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF,
 797     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 798   { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP,
 799     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 800   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI,
 801     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
 802   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI,
 803     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
 804   { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI,
 805     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
 806   { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP,
 807     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 808   { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP,
 809     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 810   { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP,
 811     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 812   { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM,
 813     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 814   { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM,
 815     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 816   { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP,
 817     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 818   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 819     RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 },
 820   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 821     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 },
 822   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 823     RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 },
 824   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 825     RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 },
 826   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 827     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 },
 828   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 829     RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 },
 830   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 831     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 },
 832   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 833     RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 },
 834   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 835     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 },
 836   { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR,
 837     RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 },
 838   { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP,
 839     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 840   { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP,
 841     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 842   { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN,
 843     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 844   { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI,
 845     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 846   { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP,
 847     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 848   { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF,
 849     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 850   { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP,
 851     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 852   { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF,
 853     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 854   { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP,
 855     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 856   { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP,
 857     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 858   { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ,
 859     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
 860   { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ,
 861     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
 862   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
 863     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 864   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB,
 865     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 866   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
 867     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 868   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH,
 869     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 870   { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
 871     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 872   { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW,
 873     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 874   { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX,
 875     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 876   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
 877     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 878   { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH,
 879     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 880   { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
 881     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 882   { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW,
 883     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 884   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
 885     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
 886   { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX,
 887     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 888   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
 889     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 890   { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB,
 891     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 892   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
 893     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 894   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB,
 895     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 896   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX,
 897     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 898   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
 899     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 900   { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH,
 901     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 902   { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
 903     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
 904   { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW,
 905     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
 906   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
 907     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 },
 908   { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX,
 909     RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 },
 910   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
 911     RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 },
 912   { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH,
 913     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 },
 914   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
 915     RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 },
 916   { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB,
 917     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 },
 918
 919   /* Binary AltiVec/VSX builtins.  */
 920   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 921     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
 922   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 923     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
 924   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 925     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
 926   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 927     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
 928   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 929     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
 930   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM,
 931     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
 932   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 933     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
 934   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 935     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
 936   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 937     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
 938   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 939     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 940   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 941     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
 942   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM,
 943     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 944   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 945     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
 946   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 947     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
 948   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 949     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
 950   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 951     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 952   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 953     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
 954   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM,
 955     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 956   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 957     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
 958   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 959     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
 960   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 961     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
 962   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 963     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
 964   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 965     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
 966   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM,
 967     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
 968   { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP,
 969     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 970   { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP,
 971     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
 972   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
 973     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
 974   { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM,
 975     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
 976     RS6000_BTI_unsigned_V1TI, 0 },
 977   { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP,
 978     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
 979   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 980     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
 981   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 982     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 983   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 984     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
 985   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 986     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 987   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 988     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
 989   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 990     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
 991   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 992     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
 993   { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM,
 994     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
 995   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
 996     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
 997   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
 998     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
 999   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1000     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1001   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1002     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1003   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1004     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1005   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1006     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1007   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1008     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1009   { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM,
1010     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1011   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1012     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1013   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1014     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1015   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1016     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1017   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1018     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1019   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1020     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1021   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1022     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1023   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1024     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1025   { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
1026     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1027   { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1028     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1029   { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
1030     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
1031     RS6000_BTI_unsigned_V4SI, 0 },
1032   { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1033     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1034     RS6000_BTI_unsigned_V1TI, 0 },
1035   { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
1036     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
1037   { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1038     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
1039     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
1040   { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
1041     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
1042   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1043     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1044   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1045     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1046   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
1047     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1048   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1049     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1050   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1051     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1052   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS,
1053     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1054   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1055     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1056   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1057     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1058   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS,
1059     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1060   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1061     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1062   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1063     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1064   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS,
1065     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1066   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1067     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1068   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1069     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1070   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS,
1071     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1072   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1073     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1074   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1075     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1076   { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS,
1077     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1078   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1079     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1080   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1081     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1082   { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS,
1083     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1084   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1085     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1086   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1087     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1088   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1089     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1090   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1091     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1092   { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS,
1093     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1094   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1095     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1096   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1097     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1098   { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS,
1099     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1100   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1101     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1102   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1103     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1104   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1105     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1106   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1107     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1108   { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS,
1109     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1110   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1111     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1112   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1113     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1114   { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS,
1115     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1116   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1117     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1118   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1119     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1120   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1121     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1122   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1123     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1124   { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS,
1125     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1126   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1127     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1128   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1129     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1130   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1131     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1132   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1133     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1134   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1135     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1136   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1137     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1138   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1139     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1140   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1141     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1142   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1143     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1144   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1145     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1146   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1147     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1148   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1149     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1150   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1151     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1152   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1153     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1154   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1155     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1156   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1157     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1158   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1159     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1160   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1161     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1162   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1163     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1164   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1165     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1166   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1167     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1168   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1169     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1170   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1171     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1172   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1173     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1174   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1175     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1176   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1177     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1178   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1179     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1180   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1181     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1182   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1183     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1184   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1185     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1186   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1187     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1188   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1189     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1190   { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND,
1191     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1192   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1193     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1194   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1195     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
1196   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1197     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
1198   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1199     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1200   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1201     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
1202   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1203     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
1204   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1205     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1206   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1207     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1208   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1209     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1210   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1211     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1212   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1213     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1214   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1215     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1216   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1217     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1218   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1219     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1220   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1221     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1222   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1223     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1224   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1225     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1226   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1227     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1228   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1229     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1230   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1231     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1232   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1233     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1234   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1235     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1236   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1237     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1238   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1239     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1240   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1241     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1242   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1243     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1244   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1245     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1246   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1247     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1248   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1249     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1250   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1251     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1252   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1253     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1254   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1255     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1256   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1257     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1258   { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
1259     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1260   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB,
1261     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1262   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB,
1263     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1264   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH,
1265     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1266   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH,
1267     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1268   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW,
1269     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1270   { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW,
1271     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1272   { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW,
1273     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1274   { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW,
1275     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1276   { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH,
1277     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1278   { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH,
1279     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1280   { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB,
1281     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1282   { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB,
1283     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1284   { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP,
1285     RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1286   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1287     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1288   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1289     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1290   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB,
1291     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1292   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1293     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1294   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1295     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1296   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH,
1297     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1298   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1299     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1300   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1301     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1302   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW,
1303     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1304   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1305     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
1306   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1307     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1308   { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD,
1309     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1310   { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP,
1311     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1312   { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP,
1313     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1314   { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP,
1315     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1316
1317   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1318     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1319   { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW,
1320     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1321
1322   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1323     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1324   { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH,
1325     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1326
1327   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1328     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1329   { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB,
1330     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1331
1332   { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP,
1333     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1334   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP,
1335     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1336   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI,
1337     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1338   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI,
1339     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1340     RS6000_BTI_unsigned_V16QI, 0},
1341   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI,
1342     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1343   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI,
1344     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1345     RS6000_BTI_unsigned_V8HI, 0},
1346   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI,
1347     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1348   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI,
1349     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1350     RS6000_BTI_unsigned_V4SI, 0},
1351   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI,
1352     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1353   { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI,
1354     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1355     RS6000_BTI_unsigned_V2DI, 0},
1356   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB,
1357     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1358   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB,
1359     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1360   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH,
1361     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1362   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH,
1363     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1364   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW,
1365     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1366   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW,
1367     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1368   { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD,
1369     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1370   { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD,
1371     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1372   { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP,
1373     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1374   { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP,
1375     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1376   { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP,
1377     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1378   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1379     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1380   { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW,
1381     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1382   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1383     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1384   { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW,
1385     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1386   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1387     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1388   { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH,
1389     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1390   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1391     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1392   { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH,
1393     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1394   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1395     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1396   { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB,
1397     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1398   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1399     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1400   { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB,
1401     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1402   { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP,
1403     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1404   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP,
1405     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1406   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI,
1407     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0},
1408   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI,
1409     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
1410     RS6000_BTI_unsigned_V16QI, 0},
1411   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI,
1412     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0},
1413   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI,
1414     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
1415     RS6000_BTI_unsigned_V8HI, 0},
1416   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI,
1417     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0},
1418   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI,
1419     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
1420     RS6000_BTI_unsigned_V4SI, 0},
1421   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI,
1422     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0},
1423   { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI,
1424     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI,
1425     RS6000_BTI_unsigned_V2DI, 0},
1426   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB,
1427     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1428   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB,
1429     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1430   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH,
1431     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1432   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH,
1433     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1434   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW,
1435     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1436   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW,
1437     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1438   { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD,
1439     RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1440   { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD,
1441     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1442   { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP,
1443     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1444   { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP,
1445     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1446   { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP,
1447     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1448   { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF,
1449     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1450   { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX,
1451     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1452   { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX,
1453     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1454   { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE,
1455     RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0},
1456   { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE,
1457     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0},
1458   { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX,
1459     RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
1460   { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX,
1461     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
1462   { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS,
1463     RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1464   { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE,
1465     RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1466   { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS,
1467     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
1468   { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE,
1469     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
1470   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP,
1471     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1472   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
1473     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1474   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI,
1475     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1476   { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
1477     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1478   { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
1479     RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
1480   { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
1481     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1482
1483   { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
1484     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1485   { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
1486     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1487   { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
1488     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1489
1490   { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
1491     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1492   { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
1493     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1494   { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
1495     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1496
1497   { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI,
1498     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1499   { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI,
1500     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1501   { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF,
1502     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1503
1504   { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI,
1505     RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
1506   { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI,
1507     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1508   { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF,
1509     RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
1510
1511   { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF,
1512     RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 },
1513   { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF,
1514     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 },
1515   { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_FLOAT2_V2DI,
1516     RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1517   { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_UNS_FLOAT2_V2DI,
1518     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI,
1519     RS6000_BTI_unsigned_V2DI, 0 },
1520   { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF,
1521     RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1522   { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI,
1523     RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1524   { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI,
1525     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1526   { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF,
1527     RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 },
1528   { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI,
1529     RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 },
1530   { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI,
1531     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 },
1532
1533   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
1534     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1535   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1536     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1537   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1538     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1539     ~RS6000_BTI_unsigned_V2DI, 0 },
1540   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
1541     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1542   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1543     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1544   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF,
1545     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1546   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1547     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1548   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1549     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1550   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1551     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1552   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1553     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1554   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1555     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1556   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1557     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1558   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI,
1559     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1560   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1561     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1562   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1563     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1564   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1565     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1566   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1567     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1568   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1569     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1570   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI,
1571     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1572   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1573     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1574   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1575     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1576   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1577     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1578   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1579     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1580   { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI,
1581     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1582   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1583     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1584   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX,
1585     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1586   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1587     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1588   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX,
1589     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1590   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1591     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1592   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1593     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1594   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1595     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1596   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1597     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1598   { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX,
1599     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1600   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1601     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1602   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1603     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1604   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1605     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1606   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1607     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1608   { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX,
1609     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1610   { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1611     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1612   { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX,
1613     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1614   { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1615     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1616   { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX,
1617     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1618   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1619     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1620   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF,
1621     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1622   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1623     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1624   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1625     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1626   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1627     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1628   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1629     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1630   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1631     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1632   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1633     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1634   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI,
1635     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1636   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1637     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1638   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1639     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1640   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1641     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1642   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1643     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1644   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1645     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1646   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI,
1647     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1648   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1649     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1650   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1651     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1652   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1653     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1654   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1655     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1656     ~RS6000_BTI_unsigned_V16QI, 0 },
1657   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI,
1658     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1659   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF,
1660     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
1661   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1662     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
1663   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1664     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
1665     ~RS6000_BTI_unsigned_V2DI, 0 },
1666   { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI,
1667     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
1668   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1669     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1670   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1671     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1672   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1673     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1674   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1675     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1676   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1677     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1678   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1679     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1680   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1681     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1682   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1683     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1684   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1685     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1686   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1687     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1688   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1689     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1690   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1691     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1692   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1693     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1694   { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
1695     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1696     ~RS6000_BTI_unsigned_long_long, 0 },
1697   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1698     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1699   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1700     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1701   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1702     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1703   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1704     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1705   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1706     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1707   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1708     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1709   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1710     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 },
1711   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1712     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
1713   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1714     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1715   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1716     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
1717   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1718     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
1719   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1720     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
1721   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1722     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
1723   { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
1724     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
1725     ~RS6000_BTI_unsigned_long_long, 0 },
1726   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1727     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1728   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1729     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1730   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1731     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1732   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1733     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1734   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1735     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1736   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1737     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1738   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1739     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1740   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1741     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1742   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1743     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1744   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1745     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1746   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1747     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1748   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1749     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1750   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1751     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1752   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1753     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1754   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1755     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1756   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1757     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1758   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1759     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1760   { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
1761     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1762   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1763     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1764   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1765     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1766   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1767     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1768   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1769     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1770   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1771     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1772   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1773     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1774   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1775     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1776   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1777     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1778   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1779     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1780   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1781     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1782   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1783     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1784   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1785     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1786   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1787     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1788   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1789     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1790   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1791     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1792   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1793     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1794   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1795     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1796   { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL,
1797     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1798   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1799     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1800   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1801     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1802   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1803     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1804   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1805     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1806   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1807     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1808   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1809     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1810   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1811     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1812   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1813     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1814   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1815     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1816   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1817     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1818   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1819     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1820   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1821     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1822   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1823     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1824   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1825     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1826   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1827     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1828   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1829     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1830   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1831     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1832   { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX,
1833     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1834   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1835     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
1836   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1837     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
1838   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1839     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
1840   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1841     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
1842   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1843     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
1844   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1845     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
1846   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1847     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
1848   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1849     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
1850   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1851     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
1852   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1853     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
1854   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1855     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
1856   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1857     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
1858   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1859     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
1860   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1861     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
1862   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1863     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
1864   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1865     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
1866   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1867     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
1868   { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL,
1869     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
1870   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1871     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1872   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1873     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1874   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB,
1875     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1876   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1877     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1878   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1879     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1880   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB,
1881     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1882   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1883     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1884   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1885     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1886   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH,
1887     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1888   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1889     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1890   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1891     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1892   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH,
1893     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1894   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1895     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1896   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1897     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1898   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW,
1899     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1900   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1901     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1902   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1903     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1904   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW,
1905     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1906   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1907     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1908   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1909     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
1910   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD,
1911     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
1912   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1913     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
1914   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1915     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
1916   { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD,
1917     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1918   { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP,
1919     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1920   { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP,
1921     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1922   { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP,
1923     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1924   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1925     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1926   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1927     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
1928   { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW,
1929     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
1930   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1931     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1932   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1933     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
1934   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1935     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1936   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1937     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1938   { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW,
1939     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
1940   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1941     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1942   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1943     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
1944   { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH,
1945     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
1946   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1947     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1948   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1949     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
1950   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1951     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1952   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1953     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1954   { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH,
1955     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
1956   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1957     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1958   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1959     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
1960   { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB,
1961     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
1962   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1963     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1964   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1965     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
1966   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1967     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1968   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1969     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1970   { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB,
1971     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
1972   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1973     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
1974   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1975     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
1976   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB,
1977     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
1978   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1979     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
1980   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1981     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
1982   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1983     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
1984   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH,
1985     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
1986   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1987     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
1988   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1989     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
1990   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1991     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
1992   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
1993     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
1994   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
1995     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
1996   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1997     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
1998   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
1999     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2000   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2001     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2002   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2003     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2004   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2005     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2006   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2007     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2008   { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
2009     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2010   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2011     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2012   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2013     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2014   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2015     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2016   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
2017     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2018   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2019     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2020   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2021     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2022   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2023     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2024   { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH,
2025     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2026   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2027     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2028   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2029     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2030   { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB,
2031     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2032   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2033     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2034   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2035     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2036   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB,
2037     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2038   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2039     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2040   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2041     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2042   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2043     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2044   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH,
2045     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2046   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2047     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2048   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2049     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2050   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2051     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2052   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
2053     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2054   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
2055     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2056   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2057     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2058   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2059     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2060   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2061     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2062   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2063     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2064   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2065     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2066   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2067     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2068   { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
2069     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2070   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2071     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2072   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2073     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2074   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2075     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2076   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
2077     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2078   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2079     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2080   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2081     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 },
2082   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2083     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2084   { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH,
2085     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2086   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2087     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2088   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2089     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2090   { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB,
2091     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2092   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2093     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2094   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2095     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2096   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB,
2097     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2098   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2099     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2100   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2101     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2102   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB,
2103     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2104   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2105     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2106   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2107     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2108   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH,
2109     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2110   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2111     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2112   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2113     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2114   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH,
2115     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2116   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2117     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2118   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2119     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2120   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW,
2121     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2122   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2123     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2124   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2125     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2126   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW,
2127     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2128   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2129     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2130   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2131     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2132   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD,
2133     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2134   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2135     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2136   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2137     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2138   { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD,
2139     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2140   { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP,
2141     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2142   { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP,
2143     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2144   { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP,
2145     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2146   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2147     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2148   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2149     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2150   { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW,
2151     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2152   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2153     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2154   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2155     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2156   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2157     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2158   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2159     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2160   { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW,
2161     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2162   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2163     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2164   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2165     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2166   { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH,
2167     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2168   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2169     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2170   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2171     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2172   { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB,
2173     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2174   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2175     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2176   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2177     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2178   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2179     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2180   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2181     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2182   { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH,
2183     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2184   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2185     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2186   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2187     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2188   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2189     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2190   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2191     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2192   { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB,
2193     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2194   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB,
2195     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2196   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB,
2197     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2198   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
2199     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2200   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
2201     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2202   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESW,
2203     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2204   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUW,
2205     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2206     RS6000_BTI_unsigned_V4SI, 0 },
2207   { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
2208     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2209   { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB,
2210     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2211   { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH,
2212     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2213   { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH,
2214     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2215   { ALTIVEC_BUILTIN_VEC_VMULEUW, ALTIVEC_BUILTIN_VMULEUW,
2216     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2217   { ALTIVEC_BUILTIN_VEC_VMULESW, ALTIVEC_BUILTIN_VMULESW,
2218     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2219   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB,
2220     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2221   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB,
2222     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2223   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
2224     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2225   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSW,
2226     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2227   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUW,
2228     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
2229     RS6000_BTI_unsigned_V4SI, 0 },
2230   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
2231     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2232   { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH,
2233     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2234   { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH,
2235     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2236   { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB,
2237     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2238   { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB,
2239     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2240   { ALTIVEC_BUILTIN_VEC_VMULOUW, ALTIVEC_BUILTIN_VMULOUW,
2241     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2242   { ALTIVEC_BUILTIN_VEC_VMULOSW, ALTIVEC_BUILTIN_VMULOSW,
2243     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2244
2245   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI,
2246     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2247   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI,
2248     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2249   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI,
2250     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2251   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI,
2252     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2253   { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF,
2254     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2255   { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP,
2256     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2257   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI,
2258     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2259   { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI,
2260     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2261
2262   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V16QI,
2263     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
2264   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V8HI,
2265     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
2266   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SI,
2267     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
2268   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DI,
2269     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
2270   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V4SF,
2271     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2272   { ALTIVEC_BUILTIN_VEC_NEG, ALTIVEC_BUILTIN_NEG_V2DF,
2273     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2274
2275   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2276     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2277   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2278     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2279   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2280     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2281   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2282     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2283   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2284     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2285   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2286     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2287   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2288     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2289   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2290     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2291   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2292     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2293   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2294     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2295   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2296     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2297   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2298     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2299   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2300     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2301   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2302     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2303   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2304     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2305   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2306     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2307   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2308     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2309   { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
2310     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2311   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2312     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2313   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2314     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
2315   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2316     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
2317   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2318     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2319   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2320     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
2321   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2322     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
2323   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2324     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2325   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2326     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2327   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2328     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2329   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2330     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2331   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2332     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2333   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2334     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2335   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2336     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2337   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2338     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2339   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2340     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2341   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2342     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2343   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2344     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2345   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2346     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2347   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2348     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2349   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2350     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2351   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2352     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2353   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2354     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2355   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2356     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2357   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2358     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2359   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2360     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2361   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2362     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2363   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2364     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2365   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2366     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2367   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2368     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
2369   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2370     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2371   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2372     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2373   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2374     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2375   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2376     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2377   { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
2378     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2379   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2380     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2381   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2382     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2383   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM,
2384     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2385   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2386     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2387   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2388     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2389   { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM,
2390     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2391   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2392     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2393   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2394     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2395   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2396     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
2397   { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM,
2398     RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2399
2400   { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16,
2401     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2402
2403   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2404     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2405   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2406     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2407   { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM,
2408     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
2409   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2410     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2411   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2412     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2413   { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM,
2414     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
2415   { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX,
2416     RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2417   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS,
2418     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2419   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS,
2420     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2421   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS,
2422     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2423   { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
2424     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2425   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
2426     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2427   { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
2428     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2429   { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
2430     RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2431   { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
2432     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2433   { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
2434     RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2435   { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
2436     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2437   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS,
2438     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2439   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS,
2440     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2441   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS,
2442     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2443   { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS,
2444     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2445   { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2446     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2447   { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS,
2448     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2449   { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS,
2450     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2451   { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS,
2452     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2453   { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC,
2454     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2455   { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC,
2456     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2457   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2458     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2459   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB,
2460     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2461   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2462     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2463   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH,
2464     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2465   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2466     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2467   { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW,
2468     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2469   { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2470     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2471   { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD,
2472     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2473   { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2474     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2475   { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW,
2476     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2477   { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2478     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2479   { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH,
2480     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2481   { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2482     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2483   { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB,
2484     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2485   { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI,
2486     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2487     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
2488   { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI,
2489     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2490     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
2491   { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM,
2492     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
2493     RS6000_BTI_unsigned_V4SI, 0 },
2494   { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM,
2495     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
2496     RS6000_BTI_unsigned_V2DI, 0 },
2497   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2498     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2499   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB,
2500     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2501   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2502     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2503   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH,
2504     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2505   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2506     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2507   { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW,
2508     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2509   { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2510     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2511   { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD,
2512     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2513   { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP,
2514     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
2515   { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP,
2516     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
2517   { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2518     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2519   { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW,
2520     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2521   { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2522     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2523   { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH,
2524     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2525   { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2526     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2527   { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB,
2528     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2529   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2530     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2531   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2532     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2533   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2534     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2535   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2536     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2537   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2538     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2539   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2540     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2541   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2542     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2543   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2544     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2545   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2546     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2547   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2548     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2549   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2550     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2551   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2552     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2553   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2554     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2555   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2556     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2557   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2558     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2559   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2560     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2561   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2562     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2563   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2564     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2565   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2566     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2567   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2568     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2569   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2570     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2571   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2572     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2573   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2574     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2575   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2576     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2577   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2578     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2579   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2580     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2581   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2582     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2583   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2584     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2585   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2586     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2587   { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL,
2588     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2589   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2590     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2591   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2592     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2593   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2594     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2595   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2596     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2597   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2598     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2599   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2600     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2601   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2602     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2603   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2604     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2605   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2606     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2607   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2608     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2609   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2610     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2611   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2612     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2613   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2614     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2615   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2616     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2617   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2618     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2619   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2620     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2621   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2622     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 },
2623   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2624     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2625   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2626     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 },
2627   { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO,
2628     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 },
2629   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2630     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2631   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2632     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2633   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB,
2634     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2635   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2636     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2637   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2638     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2639   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2640     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2641   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH,
2642     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2643   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2644     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2645   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2646     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2647   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2648     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2649   { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW,
2650     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2651   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF,
2652     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
2653   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2654     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 },
2655   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2656     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
2657   { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI,
2658     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 },
2659   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2660     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
2661   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2662     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 },
2663   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2664     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
2665   { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW,
2666     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 },
2667   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2668     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 },
2669   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2670     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
2671   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2672     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 },
2673   { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH,
2674     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 },
2675   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2676     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 },
2677   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2678     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 },
2679   { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB,
2680     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 },
2681   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2682     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2683   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB,
2684     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2685   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2686     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2687   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH,
2688     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2689   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2690     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2691   { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW,
2692     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2693   { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2694     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2695   { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD,
2696     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2697   { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2698     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2699   { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW,
2700     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2701   { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2702     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2703   { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH,
2704     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2705   { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2706     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2707   { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB,
2708     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2709   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2710     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2711   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB,
2712     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2713   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2714     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2715   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH,
2716     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2717   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2718     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2719   { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW,
2720     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2721   { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2722     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2723   { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD,
2724     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2725   { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2726     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2727   { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW,
2728     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2729   { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2730     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2731   { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH,
2732     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2733   { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2734     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2735   { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB,
2736     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2737   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2738     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2739   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2740     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2741   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2742     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2743   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2744     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2745   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2746     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2747   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2748     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2749   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2750     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2751   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2752     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 },
2753   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2754     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2755   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2756     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2757   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2758     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2759   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2760     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2761   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2762     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2763   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2764     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2765   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2766     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2767   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2768     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2769   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2770     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2771   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2772     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2773   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2774     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 },
2775   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2776     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2777   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2778     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2779   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2780     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2781   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2782     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2783   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2784     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2785   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2786     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2787   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2788     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2789   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2790     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2791   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2792     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
2793   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2794     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 },
2795   { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR,
2796     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2797   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2798     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 },
2799   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2800     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 },
2801   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2802     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 },
2803   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2804     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2805   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2806     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 },
2807   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2808     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 },
2809   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2810     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 },
2811   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2812     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2813   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2814     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 },
2815   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2816     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2817   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2818     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 },
2819   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2820     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 },
2821   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2822     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2823   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2824     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2825   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2826     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2827   { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO,
2828     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2829   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2830     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2831   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2832     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2833   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2834     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2835   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2836     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2837   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2838     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2839   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM,
2840     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2841   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2842     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2843   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2844     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2845   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2846     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2847   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2848     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2849   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2850     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2851   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM,
2852     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2853   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2854     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2855   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2856     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2857   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2858     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2859   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2860     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2861   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2862     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2863   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM,
2864     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2865   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2866     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
2867   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2868     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
2869   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2870     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
2871   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2872     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2873   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2874     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
2875   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM,
2876     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
2877   { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP,
2878     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2879   { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP,
2880     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
2881   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2882     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2883   { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM,
2884     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2885     RS6000_BTI_unsigned_V1TI, 0 },
2886   { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP,
2887     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
2888   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2889     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2890   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2891     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2892   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2893     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2894   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2895     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2896   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2897     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2898   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2899     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2900   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2901     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2902   { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM,
2903     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2904   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2905     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2906   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2907     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2908   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2909     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
2910   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2911     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2912   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2913     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2914   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2915     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2916   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2917     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2918   { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM,
2919     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2920   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2921     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2922   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2923     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2924   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2925     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
2926   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2927     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2928   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2929     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2930   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2931     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2932   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2933     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2934   { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM,
2935     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2936
2937   { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2938     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2939   { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW,
2940     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2941   { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2942     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
2943     RS6000_BTI_unsigned_V1TI, 0 },
2944   { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ,
2945     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
2946
2947   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2948     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2949   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2950     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
2951   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS,
2952     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
2953   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2954     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
2955   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2956     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
2957   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS,
2958     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
2959   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2960     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2961   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2962     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
2963   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS,
2964     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
2965   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2966     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
2967   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2968     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
2969   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS,
2970     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
2971   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2972     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2973   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2974     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2975   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS,
2976     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2977   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2978     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2979   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2980     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2981   { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS,
2982     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2983   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2984     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
2985   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2986     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
2987   { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS,
2988     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
2989   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2990     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2991   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2992     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 },
2993   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2994     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2995   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2996     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
2997   { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS,
2998     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
2999   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3000     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3001   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3002     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3003   { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS,
3004     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3005   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3006     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3007   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3008     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 },
3009   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3010     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3011   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3012     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3013   { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS,
3014     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3015   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3016     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3017   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3018     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3019   { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS,
3020     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3021   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3022     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3023   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3024     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 },
3025   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3026     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3027   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3028     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3029   { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS,
3030     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3031   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS,
3032     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3033   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS,
3034     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3035   { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS,
3036     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3037   { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS,
3038     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 },
3039   { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS,
3040     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 },
3041   { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS,
3042     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 },
3043   { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS,
3044     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3045   { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS,
3046     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3047   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF,
3048     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3049   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DF,
3050     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3051   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3052     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3053   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3054     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3055   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3056     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3057     ~RS6000_BTI_unsigned_V2DI, 0 },
3058   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V2DI,
3059     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3060     ~RS6000_BTI_unsigned_long_long, 0 },
3061   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF,
3062     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3063   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SF,
3064     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3065   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3066     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
3067   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3068     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3069   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3070     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 },
3071   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V4SI,
3072     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3073   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3074     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
3075   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3076     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3077   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3078     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 },
3079   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V8HI,
3080     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3081   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3082     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
3083   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3084     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3085   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3086     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3087     ~RS6000_BTI_unsigned_V16QI, 0 },
3088   { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LD_ELEMREV_V16QI,
3089     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3090   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V16QI,
3091     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
3092   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V16QI,
3093     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
3094   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V8HI,
3095     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
3096   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V8HI,
3097     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
3098   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V4SI,
3099     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
3100   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V4SI,
3101     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
3102   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V2DI,
3103     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
3104   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V2DI,
3105     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 },
3106   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V4SF,
3107     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3108   { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_XL_BE_V2DF,
3109     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3110   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3111     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
3112   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3113     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 },
3114   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3115     RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 },
3116   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3117     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
3118   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3119     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 },
3120   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3121     RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 },
3122   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3123     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
3124   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3125     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
3126   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3127     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
3128   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3129     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3130   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3131     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
3132   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3133     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
3134   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3135     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
3136   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3137     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
3138   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3139     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
3140   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3141     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
3142   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3143     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
3144   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3145     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3146   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3147     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 },
3148   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3149     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
3150   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3151     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
3152   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3153     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
3154   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3155     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
3156   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3157     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
3158   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3159     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3160   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3161     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 },
3162   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3163     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
3164   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3165     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
3166   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3167     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
3168   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3169     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
3170   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3171     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
3172   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3173     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3174   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3175     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
3176   { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
3177     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
3178
3179   /* Ternary AltiVec/VSX builtins.  */
3180   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3181     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3182   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3183     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3184   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3185     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3186   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3187     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3188   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3189     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3190   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3191     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3192   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3193     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3194   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3195     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3196   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3197     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3198   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3199     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3200   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3201     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3202   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3203     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3204   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3205     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3206   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3207     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3208   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3209     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3210   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3211     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3212   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3213     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3214   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3215     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3216   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3217     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3218   { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST,
3219     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3220   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3221     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3222   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3223     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3224   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3225     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3226   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3227     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3228   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3229     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3230   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3231     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3232   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3233     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3234   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3235     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3236   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3237     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3238   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3239     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3240   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3241     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3242   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3243     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3244   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3245     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3246   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3247     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3248   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3249     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3250   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3251     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3252   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3253     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3254   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3255     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3256   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3257     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3258   { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST,
3259     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3260   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3261     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3262   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3263     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3264   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3265     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3266   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3267     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3268   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3269     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3270   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3271     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3272   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3273     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3274   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3275     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3276   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3277     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3278   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3279     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3280   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3281     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3282   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3283     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3284   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3285     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3286   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3287     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3288   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3289     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3290   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3291     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3292   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3293     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3294   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3295     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3296   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3297     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3298   { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT,
3299     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3300   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3301     RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3302   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3303     RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3304   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3305     RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3306   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3307     RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3308   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3309     RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3310   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3311     RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3312   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3313     RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3314   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3315     RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3316   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3317     RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3318   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3319     RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3320   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3321     RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3322   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3323     RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3324   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3325     RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3326   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3327     RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3328   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3329     RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3330   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3331     RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3332   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3333     RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3334   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3335     RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3336   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3337     RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3338   { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT,
3339     RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI },
3340   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP,
3341     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3342   { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP,
3343     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3344   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3345     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3346   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3347     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3348   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3349     RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3350   { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM,
3351     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3352   { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS,
3353     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3354   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3355     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3356   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3357     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3358   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3359     RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3360   { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM,
3361     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3362   { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS,
3363     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
3364   { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP,
3365     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3366   { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP,
3367     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3368   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM,
3369     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3370   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM,
3371     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3372   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM,
3373     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3374   { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM,
3375     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3376   { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM,
3377     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3378   { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM,
3379     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3380   { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM,
3381     RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI },
3382   { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM,
3383     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI },
3384   { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS,
3385     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3386   { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS,
3387     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3388   { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS,
3389     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI },
3390   { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS,
3391     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI },
3392   { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP,
3393     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3394   { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP,
3395     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3396   { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP,
3397     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3398   { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP,
3399     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3400   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF,
3401     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI },
3402   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3403     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
3404   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3405     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
3406   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
3407     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3408     RS6000_BTI_unsigned_V16QI },
3409   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
3410     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
3411   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3412     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI },
3413   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3414     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
3415   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
3416     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI },
3417   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3418     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI },
3419   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3420     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
3421   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3422     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI },
3423   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI,
3424     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI },
3425   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3426     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3427   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3428     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3429   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3430     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3431   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3432     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3433   { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI,
3434     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3435   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3436     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI },
3437   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3438     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI },
3439   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3440     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI },
3441   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF,
3442     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
3443   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3444     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
3445   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3446     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI },
3447   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3448     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
3449   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3450     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
3451   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3452     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
3453   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3454     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
3455   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3456     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3457     RS6000_BTI_bool_V2DI },
3458   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
3459     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
3460     RS6000_BTI_unsigned_V2DI },
3461   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3462     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
3463   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
3464     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI },
3465   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3466     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
3467   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3468     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI },
3469   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3470     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
3471   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3472     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI },
3473   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3474     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
3475   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3476     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
3477   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3478     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
3479   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI,
3480     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
3481   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3482     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
3483   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3484     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI },
3485   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3486     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
3487   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3488     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
3489   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3490     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
3491   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI,
3492     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
3493   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3494     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
3495   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3496     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI },
3497   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3498     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
3499   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3500     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
3501   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3502     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
3503   { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI,
3504     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
3505   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF,
3506     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3507   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3508     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3509   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3510     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_NOT_OPAQUE },
3511   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI,
3512     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE },
3513   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3514     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3515   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3516     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE },
3517   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3518     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_NOT_OPAQUE },
3519   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI,
3520     RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_NOT_OPAQUE },
3521   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3522     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3523   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3524     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
3525   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
3526     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
3527   { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF,
3528     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3529   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3530     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
3531     RS6000_BTI_NOT_OPAQUE },
3532   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI,
3533     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3534     RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE },
3535   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3536     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
3537     RS6000_BTI_NOT_OPAQUE },
3538   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI,
3539     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3540     RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE },
3541   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3542     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
3543     RS6000_BTI_NOT_OPAQUE },
3544   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI,
3545     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3546     RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE },
3547   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3548     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
3549     RS6000_BTI_NOT_OPAQUE },
3550   { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI,
3551     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3552     RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE },
3553   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF,
3554     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3555   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3556     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3557   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3558     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3559     ~RS6000_BTI_unsigned_V2DI },
3560   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI,
3561     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3562     ~RS6000_BTI_bool_V2DI },
3563   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3564     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3565   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF,
3566     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3567   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3568     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3569   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3570     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3571   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3572     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3573   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3574     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3575   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3576     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3577   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3578     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3579   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI,
3580     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3581   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3582     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3583   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3584     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3585   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3586     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3587   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3588     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3589   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3590     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3591   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3592     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3593   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3594     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3595   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3596     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3597   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3598     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3599   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3600     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3601   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3602     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3603   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3604     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3605   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3606     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3607   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI,
3608     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3609   { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI,
3610     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3611   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3612     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3613   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3614     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3615   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3616     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3617   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX,
3618     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3619   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3620     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3621   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3622     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3623   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3624     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3625   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3626     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3627   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3628     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3629   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX,
3630     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3631   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3632     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3633   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3634     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3635   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3636     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3637   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3638     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3639   { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX,
3640     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3641   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3642     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3643   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3644     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3645   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3646     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3647   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3648     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3649   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3650     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3651   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3652     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3653   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3654     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3655   { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX,
3656     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3657   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3658     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3659   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3660     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3661   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3662     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3663   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3664     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3665   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3666     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3667   { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX,
3668     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3669   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3670     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3671   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3672     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3673   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3674     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3675   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3676     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3677   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3678     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3679   { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX,
3680     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void },
3681   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3682     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3683   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF,
3684     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3685   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3686     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3687   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3688     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3689   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3690     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3691   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3692     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3693   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3694     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3695   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3696     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3697   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI,
3698     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3699   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3700     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3701   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3702     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3703   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3704     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3705   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3706     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3707   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3708     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3709   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3710     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3711   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3712     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3713   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3714     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3715   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3716     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3717   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3718     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3719   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3720     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3721   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3722     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3723   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3724     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3725   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI,
3726     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3727   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI,
3728     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3729   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3730     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3731   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF,
3732     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3733   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3734     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3735   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3736     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3737     ~RS6000_BTI_unsigned_V2DI },
3738   { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI,
3739     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
3740     ~RS6000_BTI_bool_V2DI },
3741   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3742     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3743   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3744     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3745   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3746     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3747   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3748     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3749   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3750     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3751   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3752     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3753   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3754     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3755   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3756     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3757   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3758     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3759   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3760     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3761   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3762     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3763   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3764     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3765   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3766     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3767   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3768     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3769   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3770     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3771   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3772     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3773   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3774     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3775   { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
3776     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3777   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3778     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3779   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3780     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3781   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3782     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3783   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3784     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3785   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3786     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3787   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3788     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3789   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3790     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3791   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3792     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3793   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3794     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3795   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3796     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3797   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3798     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3799   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3800     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3801   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3802     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3803   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3804     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3805   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3806     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3807   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3808     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3809   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3810     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3811   { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL,
3812     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3813   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3814     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3815   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3816     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3817   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3818     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3819   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3820     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3821   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3822     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3823   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3824     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3825   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3826     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3827   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3828     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3829   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3830     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3831   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3832     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3833   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3834     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3835   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3836     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3837   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3838     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3839   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3840     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3841   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3842     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3843   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3844     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3845   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3846     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3847   { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX,
3848     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3849   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3850     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3851   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3852     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3853   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3854     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI },
3855   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3856     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3857   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3858     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3859   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3860     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI },
3861   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3862     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI },
3863   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3864     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI },
3865   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3866     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
3867   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3868     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3869   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3870     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3871   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3872     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI },
3873   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3874     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI },
3875   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3876     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI },
3877   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3878     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3879   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3880     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3881   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3882     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI },
3883   { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL,
3884     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI },
3885   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF,
3886     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
3887   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DF,
3888     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
3889   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3890     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
3891   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3892     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI,
3893     ~RS6000_BTI_long_long },
3894   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3895     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3896     ~RS6000_BTI_unsigned_V2DI },
3897   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V2DI,
3898     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3899     ~RS6000_BTI_unsigned_long_long },
3900   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF,
3901     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
3902   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SF,
3903     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
3904   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3905     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
3906   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3907     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
3908   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3909     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3910     ~RS6000_BTI_unsigned_V4SI },
3911   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V4SI,
3912     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
3913     ~RS6000_BTI_UINTSI },
3914   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3915     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
3916   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3917     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
3918   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3919     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3920     ~RS6000_BTI_unsigned_V8HI },
3921   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V8HI,
3922     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
3923     ~RS6000_BTI_UINTHI },
3924   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3925     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
3926   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3927     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
3928   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3929     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3930     ~RS6000_BTI_unsigned_V16QI },
3931   { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_ST_ELEMREV_V16QI,
3932     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
3933     ~RS6000_BTI_UINTQI },
3934   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3935     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3936   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
3937     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3938     RS6000_BTI_NOT_OPAQUE },
3939   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3940     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3941   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI,
3942     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3943     RS6000_BTI_NOT_OPAQUE },
3944   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3945     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3946   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI,
3947     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3948     RS6000_BTI_NOT_OPAQUE },
3949   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3950     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
3951   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI,
3952     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3953     RS6000_BTI_NOT_OPAQUE },
3954   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF,
3955     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3956   { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF,
3957     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3958   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF,
3959     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE },
3960   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3961     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE },
3962   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI,
3963     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
3964     RS6000_BTI_NOT_OPAQUE },
3965   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF,
3966     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE },
3967   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3968     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE },
3969   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI,
3970     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
3971     RS6000_BTI_NOT_OPAQUE },
3972   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3973     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE },
3974   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI,
3975     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
3976     RS6000_BTI_NOT_OPAQUE },
3977   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3978     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
3979   { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI,
3980     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
3981     RS6000_BTI_NOT_OPAQUE },
3982
3983   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3984     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
3985   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
3986     RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
3987   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3988     RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
3989   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3990     RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
3991     ~RS6000_BTI_unsigned_V2DI, 0 },
3992   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
3993     RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
3994   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3995     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
3996   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
3997     RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
3998   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
3999     RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
4000   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4001     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
4002   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4003     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
4004   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4005     RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
4006   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4007     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4008     ~RS6000_BTI_unsigned_V4SI, 0 },
4009   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4010     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
4011   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
4012     RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4013     ~RS6000_BTI_unsigned_long, 0 },
4014   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4015     RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
4016   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4017     RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
4018   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4019     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
4020   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4021     RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
4022   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4023     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4024     ~RS6000_BTI_unsigned_V8HI, 0 },
4025   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
4026     RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
4027   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4028     RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
4029   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4030     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
4031   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4032     RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
4033   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4034     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4035     ~RS6000_BTI_unsigned_V16QI, 0 },
4036   { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
4037     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
4038
4039   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4040     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
4041   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
4042     RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
4043   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4044     RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
4045   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4046     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
4047     ~RS6000_BTI_unsigned_V2DI },
4048   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
4049     RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
4050     ~RS6000_BTI_bool_V2DI },
4051   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4052     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
4053   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
4054     RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
4055   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4056     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
4057   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4058     RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
4059   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4060     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4061     ~RS6000_BTI_unsigned_V4SI },
4062   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4063     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
4064     ~RS6000_BTI_UINTSI },
4065   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4066     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4067     ~RS6000_BTI_bool_V4SI },
4068   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4069     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4070     ~RS6000_BTI_UINTSI },
4071   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
4072     RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
4073     ~RS6000_BTI_INTSI },
4074   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4075     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
4076   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4077     RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
4078   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4079     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4080     ~RS6000_BTI_unsigned_V8HI },
4081   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4082     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
4083     ~RS6000_BTI_UINTHI },
4084   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4085     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4086     ~RS6000_BTI_bool_V8HI },
4087   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4088     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4089     ~RS6000_BTI_UINTHI },
4090   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
4091     RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
4092     ~RS6000_BTI_INTHI },
4093   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4094     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
4095   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4096     RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
4097   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4098     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4099     ~RS6000_BTI_unsigned_V16QI },
4100   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4101     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
4102     ~RS6000_BTI_UINTQI },
4103   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4104     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4105     ~RS6000_BTI_bool_V16QI },
4106   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4107     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4108     ~RS6000_BTI_UINTQI },
4109   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4110     RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
4111     ~RS6000_BTI_INTQI },
4112   { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
4113     RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
4114     ~RS6000_BTI_pixel_V8HI },
4115
4116   /* Predicates.  */
4117   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4118     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4119   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4120     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4121   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4122     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4123   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4124     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4125   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4126     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4127   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4128     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4129   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4130     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4131   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4132     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4133   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4134     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4135   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4136     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4137   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4138     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4139   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4140     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4141   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4142     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4143   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4144     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4145   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4146     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4147   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4148     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4149   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4150     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4151   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4152     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4153   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4154     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4155   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4156     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4157   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P,
4158     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4159   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4160     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4161   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4162     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4163   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P,
4164     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4165   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P,
4166     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4167   { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P,
4168     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4169
4170
4171   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4172     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4173   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4174     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4175   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4176     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4177   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4178     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4179   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4180     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4181   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4182     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4183   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P,
4184     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI },
4185   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4186     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4187   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4188     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4189   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4190     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4191   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4192     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4193   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4194     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4195   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4196     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4197   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4198     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI },
4199   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P,
4200     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI },
4201   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4202     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4203   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4204     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4205   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4206     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4207   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4208     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4209   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4210     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4211   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4212     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4213   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P,
4214     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI },
4215   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4216     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4217   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4218     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4219   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4220     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4221   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4222     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4223   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4224     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4225   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4226     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4227   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P,
4228     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI },
4229   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P,
4230     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4231   { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P,
4232     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4233
4234
4235   /* cmpge is the same as cmpgt for all cases except floating point.
4236      There is further code to deal with this special case in
4237      altivec_build_resolved_builtin.  */
4238   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4239     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
4240   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4241     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI },
4242   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
4243     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
4244   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4245     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI },
4246   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4247     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI },
4248   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P,
4249     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
4250   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4251     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI },
4252   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4253     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI },
4254   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P,
4255     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
4256   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4257     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
4258   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4259     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI },
4260   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P,
4261     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI },
4262   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4263     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI },
4264   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4265     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI },
4266   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P,
4267     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
4268   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4269     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI },
4270   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4271     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI },
4272   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P,
4273     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
4274   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4275     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI },
4276   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4277     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI },
4278   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P,
4279     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
4280   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4281     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI },
4282   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4283     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI },
4284   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P,
4285     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI },
4286   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P,
4287     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF },
4288   { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P,
4289     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF },
4290
4291   /* Power8 vector overloaded functions.  */
4292   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4293     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4294   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4295     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4296   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4297     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4298   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4299     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4300   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4301     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4302     RS6000_BTI_unsigned_V16QI, 0 },
4303   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4304     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4305     RS6000_BTI_bool_V16QI, 0 },
4306   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
4307     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4308     RS6000_BTI_unsigned_V16QI, 0 },
4309   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4310     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4311   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4312     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4313   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4314     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4315   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4316     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4317   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4318     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4319     RS6000_BTI_unsigned_V8HI, 0 },
4320   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4321     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4322     RS6000_BTI_bool_V8HI, 0 },
4323   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
4324     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4325     RS6000_BTI_unsigned_V8HI, 0 },
4326   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4327     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4328   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4329     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4330   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4331     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4332   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4333     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4334   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4335     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4336     RS6000_BTI_unsigned_V4SI, 0 },
4337   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4338     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4339     RS6000_BTI_bool_V4SI, 0 },
4340   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
4341     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4342     RS6000_BTI_unsigned_V4SI, 0 },
4343   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4344     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4345   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4346     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4347   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4348     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4349   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4350     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4351   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4352     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4353     RS6000_BTI_unsigned_V2DI, 0 },
4354   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4355     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4356     RS6000_BTI_bool_V2DI, 0 },
4357   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
4358     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4359     RS6000_BTI_unsigned_V2DI, 0 },
4360   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF,
4361     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4362   { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF,
4363     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4364
4365   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4366     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4367   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4368     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4369   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4370     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4371   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4372     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4373     RS6000_BTI_unsigned_V16QI, 0 },
4374   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4375     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4376     RS6000_BTI_bool_V16QI, 0 },
4377   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4378     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4379     RS6000_BTI_unsigned_V16QI, 0 },
4380   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
4381     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4382   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4383     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4384   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4385     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4386   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4387     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4388   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4389     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4390     RS6000_BTI_unsigned_V8HI, 0 },
4391   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4392     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4393     RS6000_BTI_bool_V8HI, 0 },
4394   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4395     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4396     RS6000_BTI_unsigned_V8HI, 0 },
4397   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
4398     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4399   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4400     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4401   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4402     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4403   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4404     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4405   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4406     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4407     RS6000_BTI_unsigned_V4SI, 0 },
4408   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4409     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4410     RS6000_BTI_bool_V4SI, 0 },
4411   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4412     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4413     RS6000_BTI_unsigned_V4SI, 0 },
4414   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
4415     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4416   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4417     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4418   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4419     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4420   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4421     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4422   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4423     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4424     RS6000_BTI_unsigned_V2DI, 0 },
4425   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4426     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4427     RS6000_BTI_bool_V2DI, 0 },
4428   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4429     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4430     RS6000_BTI_unsigned_V2DI, 0 },
4431   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
4432     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4433   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
4434     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4435   { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
4436     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4437
4438   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4439     RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 },
4440   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4441     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
4442   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4443     RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4444   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4445     RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
4446     RS6000_BTI_unsigned_V16QI, 0 },
4447   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4448     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4449     RS6000_BTI_bool_V16QI, 0 },
4450   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4451     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4452     RS6000_BTI_unsigned_V16QI, 0 },
4453   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
4454     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
4455   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4456     RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
4457   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4458     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
4459   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4460     RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4461   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4462     RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
4463     RS6000_BTI_unsigned_V8HI, 0 },
4464   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4465     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4466     RS6000_BTI_bool_V8HI, 0 },
4467   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4468     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4469     RS6000_BTI_unsigned_V8HI, 0 },
4470   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
4471     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
4472   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4473     RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
4474   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4475     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
4476   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4477     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4478   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4479     RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
4480     RS6000_BTI_unsigned_V4SI, 0 },
4481   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4482     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4483     RS6000_BTI_bool_V4SI, 0 },
4484   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4485     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4486     RS6000_BTI_unsigned_V4SI, 0 },
4487   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
4488     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
4489   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4490     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4491   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4492     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4493   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4494     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4495   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4496     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
4497     RS6000_BTI_unsigned_V2DI, 0 },
4498   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4499     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4500     RS6000_BTI_bool_V2DI, 0 },
4501   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4502     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4503     RS6000_BTI_unsigned_V2DI, 0 },
4504   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
4505     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
4506   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
4507     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
4508   { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
4509     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
4510
4511   { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4512     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4513   { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ,
4514     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4515     RS6000_BTI_unsigned_V1TI, 0 },
4516
4517   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4518     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
4519   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4520     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
4521   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4522     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
4523   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4524     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4525   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4526     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
4527   { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM,
4528     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4529
4530   { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4531     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
4532   { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM,
4533     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
4534     RS6000_BTI_unsigned_V1TI, 0 },
4535
4536   { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD,
4537     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4538     RS6000_BTI_unsigned_V16QI, 0 },
4539   { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ,
4540     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4541     RS6000_BTI_unsigned_V16QI, 0 },
4542   { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2,
4543     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4544     RS6000_BTI_unsigned_V16QI, 0 },
4545
4546   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4547     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
4548     RS6000_BTI_unsigned_V16QI, 0 },
4549   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4550     RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4551   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4552     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
4553     RS6000_BTI_unsigned_V16QI, 0 },
4554   { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
4555     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
4556     RS6000_BTI_unsigned_V16QI, 0 },
4557
4558   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4559     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4560   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
4561     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4562   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4563     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4564   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH,
4565     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4566   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4567     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4568   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW,
4569     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4570   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4571     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4572   { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD,
4573     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4574
4575   { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4576     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4577   { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB,
4578     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4579
4580   { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4581     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4582   { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH,
4583     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4584
4585   { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4586     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4587   { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW,
4588     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4589
4590   { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4591     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4592   { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
4593     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4594
4595   { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD,
4596     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4597   { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD,
4598     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4599
4600   { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD,
4601     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4602   { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD,
4603     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4604
4605   { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD,
4606     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4607   { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD,
4608     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4609
4610   { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD,
4611     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4612   { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD,
4613     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4614
4615   { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD,
4616     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4617   { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD,
4618     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4619
4620   { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD,
4621     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4622   { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD,
4623     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4624
4625   { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD,
4626     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4627   { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD,
4628     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4629
4630   { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD,
4631     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 },
4632   { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD,
4633     RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 },
4634
4635   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4636     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4637   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB,
4638     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4639   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4640     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4641   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH,
4642     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4643   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4644     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4645   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW,
4646     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4647   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4648     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4649   { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD,
4650     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4651
4652   { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4653     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
4654   { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB,
4655     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
4656
4657   { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4658     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
4659   { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH,
4660     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
4661
4662   { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4663     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
4664   { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW,
4665     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
4666
4667   { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4668     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
4669   { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
4670     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
4671
4672   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
4673     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4674     RS6000_BTI_unsigned_V16QI, 0 },
4675   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
4676     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4677     RS6000_BTI_unsigned_V8HI, 0 },
4678   { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
4679     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4680     RS6000_BTI_unsigned_V4SI, 0 },
4681
4682   { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
4683     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
4684     RS6000_BTI_unsigned_V16QI, 0 },
4685
4686   { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
4687     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
4688     RS6000_BTI_unsigned_V8HI, 0 },
4689
4690   { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
4691     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
4692     RS6000_BTI_unsigned_V4SI, 0 },
4693
4694   { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP,
4695     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4696   { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP,
4697     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4698
4699   { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP,
4700     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4701   { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP,
4702     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4703
4704   { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP,
4705     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4706   { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP,
4707     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4708
4709   { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP,
4710     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
4711   { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP,
4712     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
4713
4714   { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP,
4715     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4716   { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP,
4717     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4718
4719   { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP,
4720     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 },
4721   { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP,
4722     RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 },
4723
4724   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4725     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4726   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP,
4727     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4728
4729   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4730     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4731   { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP,
4732     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4733
4734   { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4735     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
4736   { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP,
4737     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 },
4738
4739   { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4740     RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
4741   { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP,
4742     RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 },
4743
4744   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP,
4745     RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4746   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP,
4747     RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4748   { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP,
4749     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4750
4751   { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP,
4752     RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 },
4753   { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP,
4754     RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 },
4755   { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP,
4756     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 },
4757
4758   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP,
4759     RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4760   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP,
4761     RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4762   { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP,
4763     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4764
4765   { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP,
4766     RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 },
4767   { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP,
4768     RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 },
4769   { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP,
4770     RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 },
4771
4772   { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP,
4773     RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 },
4774   { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP,
4775     RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 },
4776
4777   { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP,
4778     RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 },
4779   { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP,
4780     RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 },
4781
4782   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP,
4783     RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
4784   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF,
4785     RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 },
4786
4787   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP,
4788     RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 },
4789   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
4790     RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
4791
4792   { P9V_BUILTIN_VEC_VSCEDPGT, P9V_BUILTIN_VSCEDPGT,
4793     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4794   { P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VSCEDPLT,
4795     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4796   { P9V_BUILTIN_VEC_VSCEDPEQ, P9V_BUILTIN_VSCEDPEQ,
4797     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4798   { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,
4799     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
4800
4801   { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
4802     RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4803     RS6000_BTI_unsigned_long_long, 0 },
4804
4805   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4806     RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4807     RS6000_BTI_unsigned_long_long, 0 },
4808   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4809     RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4810     RS6000_BTI_unsigned_long_long, 0 },
4811
4812   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4813     RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4814     RS6000_BTI_unsigned_long_long, 0 },
4815   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4816     RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4817     RS6000_BTI_unsigned_long_long, 0 },
4818
4819   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4820     RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4821     RS6000_BTI_unsigned_long_long, 0 },
4822   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4823     RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4824     RS6000_BTI_unsigned_long_long, 0 },
4825
4826   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4827     RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4828     RS6000_BTI_unsigned_long_long, 0 },
4829   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4830     RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4831     RS6000_BTI_unsigned_long_long, 0 },
4832
4833   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4834     RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4835     RS6000_BTI_unsigned_long_long, 0 },
4836   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4837     RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4838     RS6000_BTI_unsigned_long_long, 0 },
4839
4840   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4841     RS6000_BTI_V2DF, ~RS6000_BTI_double,
4842     RS6000_BTI_unsigned_long_long, 0 },
4843   { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL,
4844     RS6000_BTI_V4SF, ~RS6000_BTI_float,
4845     RS6000_BTI_unsigned_long_long, 0 },
4846   /* At an appropriate future time, add support for the
4847      RS6000_BTI_Float16 (exact name to be determined) type here.  */
4848
4849   { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R,
4850     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI,
4851     ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long},
4852
4853   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4854     RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI,
4855     RS6000_BTI_unsigned_long_long },
4856   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4857     RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
4858     RS6000_BTI_unsigned_long_long },
4859
4860   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4861     RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI,
4862     RS6000_BTI_unsigned_long_long },
4863   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4864     RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI,
4865     RS6000_BTI_unsigned_long_long },
4866
4867   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4868     RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI,
4869     RS6000_BTI_unsigned_long_long },
4870   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4871     RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI,
4872     RS6000_BTI_unsigned_long_long },
4873
4874   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4875     RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long,
4876     RS6000_BTI_unsigned_long_long },
4877   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4878     RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long,
4879     RS6000_BTI_unsigned_long_long },
4880
4881   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4882     RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI,
4883     RS6000_BTI_unsigned_long_long },
4884   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4885     RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI,
4886     RS6000_BTI_unsigned_long_long },
4887
4888   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4889     RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double,
4890     RS6000_BTI_unsigned_long_long },
4891   { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL,
4892     RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float,
4893     RS6000_BTI_unsigned_long_long },
4894   /* At an appropriate future time, add support for the
4895      RS6000_BTI_Float16 (exact name to be determined) type here.  */
4896
4897   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4898     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI,
4899     RS6000_BTI_bool_V16QI, 0 },
4900   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4901     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
4902     RS6000_BTI_V16QI, 0 },
4903   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB,
4904     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
4905     RS6000_BTI_unsigned_V16QI, 0 },
4906
4907   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4908     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI,
4909     RS6000_BTI_bool_V8HI, 0 },
4910   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4911     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
4912     RS6000_BTI_V8HI, 0 },
4913   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH,
4914     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
4915     RS6000_BTI_unsigned_V8HI, 0 },
4916
4917   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4918     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI,
4919     RS6000_BTI_bool_V4SI, 0 },
4920   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4921     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
4922     RS6000_BTI_V4SI, 0 },
4923   { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW,
4924     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
4925     RS6000_BTI_unsigned_V4SI, 0 },
4926
4927   /* The following 2 entries have been deprecated.  */
4928   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4929     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4930     RS6000_BTI_unsigned_V16QI, 0 },
4931   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4932     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4933     RS6000_BTI_bool_V16QI, 0 },
4934   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4935     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
4936     RS6000_BTI_unsigned_V16QI, 0 },
4937
4938   /* The following 2 entries have been deprecated.  */
4939   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4940     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4941     RS6000_BTI_V16QI, 0 },
4942   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4943     RS6000_BTI_INTSI, RS6000_BTI_V16QI,
4944     RS6000_BTI_bool_V16QI, 0 },
4945   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4946     RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
4947   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P,
4948     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
4949     RS6000_BTI_bool_V16QI, 0 },
4950
4951   /* The following 2 entries have been deprecated.  */
4952   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4953     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4954     RS6000_BTI_unsigned_V8HI, 0 },
4955   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4956     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4957     RS6000_BTI_bool_V8HI, 0 },
4958   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4959     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
4960     RS6000_BTI_unsigned_V8HI, 0 },
4961   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4962     RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
4963
4964   /* The following 2 entries have been deprecated.  */
4965   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4966     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4967     RS6000_BTI_V8HI, 0 },
4968   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4969     RS6000_BTI_INTSI, RS6000_BTI_V8HI,
4970     RS6000_BTI_bool_V8HI, 0 },
4971   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4972     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
4973     RS6000_BTI_bool_V8HI, 0 },
4974   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P,
4975     RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
4976     RS6000_BTI_pixel_V8HI, 0 },
4977
4978   /* The following 2 entries have been deprecated.  */
4979   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4980     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4981     RS6000_BTI_unsigned_V4SI, 0 },
4982   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4983     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4984     RS6000_BTI_bool_V4SI, 0 },
4985   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4986     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
4987     RS6000_BTI_unsigned_V4SI, 0 },
4988
4989   /* The following 2 entries have been deprecated.  */
4990   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4991     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
4992     RS6000_BTI_V4SI, 0 },
4993   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4994     RS6000_BTI_INTSI, RS6000_BTI_V4SI,
4995     RS6000_BTI_bool_V4SI, 0 },
4996   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4997     RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
4998   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
4999     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5000     RS6000_BTI_bool_V4SI, 0 },
5001
5002   /* The following 2 entries have been deprecated.  */
5003   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5004     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5005     RS6000_BTI_unsigned_V2DI, 0 },
5006   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5007     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5008     RS6000_BTI_bool_V2DI, 0 },
5009   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5010     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5011     RS6000_BTI_unsigned_V2DI, 0
5012   },
5013
5014   /* The following 2 entries have been deprecated.  */
5015   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5016     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5017     RS6000_BTI_V2DI, 0 },
5018   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5019     RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5020     RS6000_BTI_bool_V2DI, 0 },
5021   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5022     RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5023   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
5024     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5025     RS6000_BTI_bool_V2DI, 0 },
5026
5027   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P,
5028     RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5029   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P,
5030     RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5031
5032   /* The following 2 entries have been deprecated.  */
5033   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5034     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5035     RS6000_BTI_unsigned_V16QI, 0 },
5036   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5037     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5038     RS6000_BTI_bool_V16QI, 0 },
5039   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5040     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5041     RS6000_BTI_unsigned_V16QI, 0 },
5042
5043   /* The following 2 entries have been deprecated.  */
5044   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5045     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5046     RS6000_BTI_V16QI, 0 },
5047   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5048     RS6000_BTI_INTSI, RS6000_BTI_V16QI,
5049     RS6000_BTI_bool_V16QI, 0 },
5050   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5051     RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
5052   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P,
5053     RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI,
5054     RS6000_BTI_bool_V16QI, 0 },
5055
5056   /* The following 2 entries have been deprecated.  */
5057   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5058     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5059     RS6000_BTI_unsigned_V8HI, 0 },
5060   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5061     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5062     RS6000_BTI_bool_V8HI, 0 },
5063   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5064     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5065     RS6000_BTI_unsigned_V8HI, 0 },
5066   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5067     RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
5068
5069   /* The following 2 entries have been deprecated.  */
5070   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5071     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5072     RS6000_BTI_V8HI, 0 },
5073   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5074     RS6000_BTI_INTSI, RS6000_BTI_V8HI,
5075     RS6000_BTI_bool_V8HI, 0 },
5076   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5077     RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI,
5078     RS6000_BTI_bool_V8HI, 0 },
5079   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P,
5080     RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI,
5081     RS6000_BTI_pixel_V8HI, 0 },
5082
5083   /* The following 2 entries have been deprecated.  */
5084   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5085     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5086     RS6000_BTI_unsigned_V4SI, 0 },
5087   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5088     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5089     RS6000_BTI_bool_V4SI, 0 },
5090   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5091     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5092     RS6000_BTI_unsigned_V4SI, 0 },
5093
5094   /* The following 2 entries have been deprecated.  */
5095   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5096     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5097     RS6000_BTI_V4SI, 0 },
5098   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5099     RS6000_BTI_INTSI, RS6000_BTI_V4SI,
5100     RS6000_BTI_bool_V4SI, 0 },
5101   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5102     RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5103   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P,
5104     RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
5105     RS6000_BTI_bool_V4SI, 0 },
5106
5107   /* The following 2 entries have been deprecated.  */
5108   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5109     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5110     RS6000_BTI_unsigned_V2DI, 0 },
5111   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5112     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5113     RS6000_BTI_bool_V2DI, 0 },
5114   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5115     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
5116     RS6000_BTI_unsigned_V2DI, 0
5117   },
5118
5119   /* The following 2 entries have been deprecated.  */
5120   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5121     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5122     RS6000_BTI_V2DI, 0 },
5123   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5124     RS6000_BTI_INTSI, RS6000_BTI_V2DI,
5125     RS6000_BTI_bool_V2DI, 0 },
5126   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5127     RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5128   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P,
5129     RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
5130     RS6000_BTI_bool_V2DI, 0 },
5131
5132   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P,
5133     RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
5134   { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P,
5135     RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5136
5137   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5138     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI,
5139     RS6000_BTI_unsigned_V16QI },
5140   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P,
5141     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI },
5142
5143   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5144     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI,
5145     RS6000_BTI_unsigned_V8HI },
5146   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P,
5147     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI },
5148
5149   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5150     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI,
5151     RS6000_BTI_unsigned_V4SI },
5152   { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P,
5153     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
5154
5155   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5156     RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI,
5157     RS6000_BTI_V16QI, 0 },
5158   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB,
5159     RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI,
5160     RS6000_BTI_unsigned_V16QI, 0 },
5161
5162   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5163     RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI,
5164     RS6000_BTI_V8HI, 0 },
5165   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH,
5166     RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI,
5167     RS6000_BTI_unsigned_V8HI, 0 },
5168
5169   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5170     RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI,
5171     RS6000_BTI_V4SI, 0 },
5172   { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW,
5173     RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI,
5174     RS6000_BTI_unsigned_V4SI, 0 },
5175
5176   { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5177     RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5178   { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB,
5179     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5180
5181   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
5182     RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
5183   { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB,
5184     RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5185
5186   { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
5187     RS6000_BTI_INTDI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
5188   { P9V_BUILTIN_VEC_VEXTRACT4B, P9V_BUILTIN_VEXTRACT4B,
5189     RS6000_BTI_INTDI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI, 0 },
5190
5191   { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH,
5192     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5193   { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL,
5194     RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 },
5195
5196   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5197     RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5198     RS6000_BTI_V16QI, 0 },
5199   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX,
5200     RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5201     RS6000_BTI_unsigned_V16QI, 0 },
5202
5203   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5204     RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5205     RS6000_BTI_V8HI, 0 },
5206   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX,
5207     RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5208     RS6000_BTI_unsigned_V8HI, 0 },
5209
5210   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5211     RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5212     RS6000_BTI_V4SI, 0 },
5213   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5214     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5215     RS6000_BTI_unsigned_V4SI, 0 },
5216   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
5217     RS6000_BTI_float, RS6000_BTI_UINTSI,
5218     RS6000_BTI_V4SF, 0 },
5219
5220   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5221     RS6000_BTI_INTQI, RS6000_BTI_UINTSI,
5222     RS6000_BTI_V16QI, 0 },
5223   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX,
5224     RS6000_BTI_UINTQI, RS6000_BTI_UINTSI,
5225     RS6000_BTI_unsigned_V16QI, 0 },
5226
5227   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5228     RS6000_BTI_INTHI, RS6000_BTI_UINTSI,
5229     RS6000_BTI_V8HI, 0 },
5230   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX,
5231     RS6000_BTI_UINTHI, RS6000_BTI_UINTSI,
5232     RS6000_BTI_unsigned_V8HI, 0 },
5233
5234   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5235     RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
5236     RS6000_BTI_V4SI, 0 },
5237   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5238     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
5239     RS6000_BTI_unsigned_V4SI, 0 },
5240   { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX,
5241     RS6000_BTI_float, RS6000_BTI_UINTSI,
5242     RS6000_BTI_V4SF, 0 },
5243
5244   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5245     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5246   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
5247     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5248
5249   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5250     RS6000_BTI_V16QI, RS6000_BTI_V4SI,
5251     RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
5252   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5253     RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI,
5254     RS6000_BTI_V16QI, RS6000_BTI_UINTSI },
5255   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B,
5256     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI,
5257     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
5258   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5259     RS6000_BTI_V16QI, RS6000_BTI_INTDI,
5260     RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5261   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5262     RS6000_BTI_V16QI, RS6000_BTI_UINTDI,
5263     RS6000_BTI_V16QI, RS6000_BTI_UINTDI },
5264   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5265     RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTDI,
5266     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5267   { P9V_BUILTIN_VEC_VINSERT4B, P9V_BUILTIN_VINSERT4B_DI,
5268     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI,
5269     RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI },
5270
5271   { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5272     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5273   { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ,
5274     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5275     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5276
5277   { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5278     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5279   { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM,
5280     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5281     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5282
5283   { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5284     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5285   { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ,
5286     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5287     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5288
5289   { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5290     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
5291   { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM,
5292     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5293     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
5294
5295   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5296     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5297   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5298     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5299   { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD,
5300     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5301
5302   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5303     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5304   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5305     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5306   { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD,
5307     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5308
5309   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5310     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5311     RS6000_BTI_unsigned_V2DI, 0 },
5312   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5313     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5314     RS6000_BTI_bool_V2DI, 0 },
5315   { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD,
5316     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5317     RS6000_BTI_unsigned_V2DI, 0 },
5318
5319   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5320     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
5321     RS6000_BTI_unsigned_V2DI, 0 },
5322   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5323     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5324     RS6000_BTI_bool_V2DI, 0 },
5325   { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD,
5326     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5327     RS6000_BTI_unsigned_V2DI, 0 },
5328
5329   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5330     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5331   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5332     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5333     RS6000_BTI_unsigned_V4SI, 0 },
5334   { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI,
5335     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5336
5337   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5338     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
5339   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5340     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5341     RS6000_BTI_unsigned_V4SI, 0 },
5342   { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW,
5343     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
5344
5345   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB,
5346     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI,
5347     RS6000_BTI_unsigned_V16QI, 0 },
5348   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH,
5349     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI,
5350     RS6000_BTI_unsigned_V8HI, 0 },
5351   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW,
5352     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
5353     RS6000_BTI_unsigned_V4SI, 0 },
5354   { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD,
5355     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI,
5356     RS6000_BTI_unsigned_V2DI, 0 },
5357
5358   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5359     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5360   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB,
5361     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5362   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5363     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5364   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH,
5365     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5366   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5367     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5368   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW,
5369     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5370   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5371     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5372   { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD,
5373     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5374
5375   { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5376     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5377   { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB,
5378     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5379
5380   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5381     RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 },
5382   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB,
5383     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5384
5385   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5386     RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 },
5387   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH,
5388     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5389
5390   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5391     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5392   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW,
5393     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5394
5395   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5396     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5397   { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD,
5398     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5399
5400   { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5401     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5402   { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH,
5403     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5404
5405   { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5406     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5407   { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW,
5408     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5409
5410   { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5411     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5412   { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
5413     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5414
5415   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5416     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5417   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW,
5418     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5419   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5420     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5421   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD,
5422     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5423   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5424     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5425   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5426     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5427   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5428     RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5429   { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ,
5430     RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5431
5432   { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5433     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5434   { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW,
5435     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5436
5437   { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5438     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5439   { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD,
5440     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5441
5442   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5443     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5444   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5445     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5446   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5447     RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 },
5448   { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ,
5449     RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 },
5450
5451   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5452     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 },
5453   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW,
5454     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5455   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5456     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 },
5457   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD,
5458     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5459   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5460     RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 },
5461   { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ,
5462     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5463
5464   { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB,
5465     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5466   { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2,
5467     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 },
5468   { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB,
5469     RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 },
5470
5471   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5472     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5473   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5474     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5475   { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
5476     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
5477
5478   { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS,
5479     RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5480
5481   { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS,
5482     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5483
5484   { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS,
5485     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5486
5487   { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5488     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5489   { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD,
5490     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5491
5492   { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5493     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5494   { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD,
5495     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5496
5497   { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5498     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5499   { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD,
5500     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5501
5502   { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5503     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5504   { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD,
5505     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5506
5507   { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5508     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5509   { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ,
5510     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5511     RS6000_BTI_unsigned_V1TI, 0 },
5512
5513   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5514     RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
5515   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5516     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
5517   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5518     RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
5519   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5520     RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5521   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5522     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
5523   { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM,
5524     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
5525
5526   { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5527     RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
5528   { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM,
5529     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
5530     RS6000_BTI_unsigned_V1TI, 0 },
5531
5532   { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32,
5533     RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 },
5534   { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB,
5535     RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 },
5536
5537   { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5538     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5539   { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW,
5540     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5541
5542   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5543     RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 },
5544   { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
5545     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
5546
5547   { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
5548     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5549     RS6000_BTI_unsigned_V16QI, 0 },
5550   { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
5551     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5552     RS6000_BTI_unsigned_V16QI, 0 },
5553
5554   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5555     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5556   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5557     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5558   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
5559     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5560   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
5561     RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
5562   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
5563     RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
5564   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5565     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5566   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
5567     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5568   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DF,
5569     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5570   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5571     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5572   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5573     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5574   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
5575     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5576   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SF,
5577     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5578   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5579     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5580   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5581     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5582   { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
5583     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5584
5585   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5586     RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
5587   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5588     RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
5589   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5590     RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
5591   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5592     RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
5593   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5594     RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 },
5595   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5596     RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 },
5597   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5598     RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 },
5599   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5600     RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 },
5601   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF,
5602     RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
5603   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF,
5604     RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
5605   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI,
5606     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
5607   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI,
5608     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
5609   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI,
5610     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
5611   { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI,
5612     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
5613
5614   { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF,
5615     RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 },
5616   { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF,
5617     RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 },
5618   { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF,
5619     RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5620   { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF,
5621     RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 },
5622   { VSX_BUILTIN_VEC_VSIGNED2, VSX_BUILTIN_VEC_VSIGNED2_V2DF,
5623     RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
5624
5625   { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF,
5626     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 },
5627   { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF,
5628     RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 },
5629   { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF,
5630     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5631   { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF,
5632     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 },
5633   { VSX_BUILTIN_VEC_VUNSIGNED2, VSX_BUILTIN_VEC_VUNSIGNED2_V2DF,
5634     RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF,
5635     RS6000_BTI_V2DF, 0 },
5636
5637   /* Crypto builtins.  */
5638   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
5639     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5640     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
5641   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI,
5642     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5643     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
5644   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI,
5645     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5646     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
5647   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI,
5648     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5649     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
5650
5651   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB,
5652     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
5653     RS6000_BTI_unsigned_V16QI, 0 },
5654   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH,
5655     RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
5656     RS6000_BTI_unsigned_V8HI, 0 },
5657   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW,
5658     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5659     RS6000_BTI_unsigned_V4SI, 0 },
5660   { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD,
5661     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5662     RS6000_BTI_unsigned_V2DI, 0 },
5663
5664   { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW,
5665     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
5666     RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5667   { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD,
5668     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
5669     RS6000_BTI_INTSI, RS6000_BTI_INTSI },
5670
5671   { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 }
5672 };
5673 \f
5674
5675 /* Convert a type stored into a struct altivec_builtin_types as ID,
5676    into a tree.  The types are in rs6000_builtin_types: negative values
5677    create a pointer type for the type associated to ~ID.  Note it is
5678    a logical NOT, rather than a negation, otherwise you cannot represent
5679    a pointer type for ID 0.  */
5680
5681 static inline tree
5682 rs6000_builtin_type (int id)
5683 {
5684   tree t;
5685   t = rs6000_builtin_types[id < 0 ? ~id : id];
5686   return id < 0 ? build_pointer_type (t) : t;
5687 }
5688
5689 /* Check whether the type of an argument, T, is compatible with a
5690    type ID stored into a struct altivec_builtin_types.  Integer
5691    types are considered compatible; otherwise, the language hook
5692    lang_hooks.types_compatible_p makes the decision.  */
5693
5694 static inline bool
5695 rs6000_builtin_type_compatible (tree t, int id)
5696 {
5697   tree builtin_type;
5698   builtin_type = rs6000_builtin_type (id);
5699   if (t == error_mark_node)
5700     return false;
5701   if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type))
5702     return true;
5703   else
5704     return lang_hooks.types_compatible_p (t, builtin_type);
5705 }
5706
5707
5708 /* In addition to calling fold_convert for EXPR of type TYPE, also
5709    call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be
5710    hiding there (PR47197).  */
5711
5712 static tree
5713 fully_fold_convert (tree type, tree expr)
5714 {
5715   tree result = fold_convert (type, expr);
5716   bool maybe_const = true;
5717
5718   if (!c_dialect_cxx ())
5719     result = c_fully_fold (result, false, &maybe_const);
5720
5721   return result;
5722 }
5723
5724 /* Build a tree for a function call to an Altivec non-overloaded builtin.
5725    The overloaded builtin that matched the types and args is described
5726    by DESC.  The N arguments are given in ARGS, respectively.
5727
5728    Actually the only thing it does is calling fold_convert on ARGS, with
5729    a small exception for vec_{all,any}_{ge,le} predicates. */
5730
5731 static tree
5732 altivec_build_resolved_builtin (tree *args, int n,
5733                                 const struct altivec_builtin_types *desc)
5734 {
5735   tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code];
5736   tree ret_type = rs6000_builtin_type (desc->ret_type);
5737   tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl));
5738   tree arg_type[3];
5739   tree call;
5740
5741   int i;
5742   for (i = 0; i < n; i++)
5743     arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes);
5744
5745   /* The AltiVec overloading implementation is overall gross, but this
5746      is particularly disgusting.  The vec_{all,any}_{ge,le} builtins
5747      are completely different for floating-point vs. integer vector
5748      types, because the former has vcmpgefp, but the latter should use
5749      vcmpgtXX.
5750
5751      In practice, the second and third arguments are swapped, and the
5752      condition (LT vs. EQ, which is recognizable by bit 1 of the first
5753      argument) is reversed.  Patch the arguments here before building
5754      the resolved CALL_EXPR.  */
5755   if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P
5756       && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P
5757       && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P)
5758     {
5759       tree t;
5760       t = args[2], args[2] = args[1], args[1] = t;
5761       t = arg_type[2], arg_type[2] = arg_type[1], arg_type[1] = t;
5762
5763       args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0],
5764                              build_int_cst (NULL_TREE, 2));
5765     }
5766
5767   switch (n)
5768     {
5769     case 0:
5770       call = build_call_expr (impl_fndecl, 0);
5771       break;
5772     case 1:
5773       call = build_call_expr (impl_fndecl, 1,
5774                               fully_fold_convert (arg_type[0], args[0]));
5775       break;
5776     case 2:
5777       call = build_call_expr (impl_fndecl, 2,
5778                               fully_fold_convert (arg_type[0], args[0]),
5779                               fully_fold_convert (arg_type[1], args[1]));
5780       break;
5781     case 3:
5782       call = build_call_expr (impl_fndecl, 3,
5783                               fully_fold_convert (arg_type[0], args[0]),
5784                               fully_fold_convert (arg_type[1], args[1]),
5785                               fully_fold_convert (arg_type[2], args[2]));
5786       break;
5787     default:
5788       gcc_unreachable ();
5789     }
5790   return fold_convert (ret_type, call);
5791 }
5792
5793 /* Implementation of the resolve_overloaded_builtin target hook, to
5794    support Altivec's overloaded builtins.  */
5795
5796 tree
5797 altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
5798                                     void *passed_arglist)
5799 {
5800   vec<tree, va_gc> *arglist = static_cast<vec<tree, va_gc> *> (passed_arglist);
5801   unsigned int nargs = vec_safe_length (arglist);
5802   enum rs6000_builtins fcode
5803     = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
5804   tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl));
5805   tree types[3], args[3];
5806   const struct altivec_builtin_types *desc;
5807   unsigned int n;
5808
5809   if (!rs6000_overloaded_builtin_p (fcode))
5810     return NULL_TREE;
5811
5812   if (TARGET_DEBUG_BUILTIN)
5813     fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n",
5814              (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)));
5815
5816   /* vec_lvsl and vec_lvsr are deprecated for use with LE element order.  */
5817   if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG)
5818     warning (OPT_Wdeprecated,
5819              "vec_lvsl is deprecated for little endian; use "
5820              "assignment for unaligned loads and stores");
5821   else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG)
5822     warning (OPT_Wdeprecated,
5823              "vec_lvsr is deprecated for little endian; use "
5824              "assignment for unaligned loads and stores");
5825
5826   if (fcode == ALTIVEC_BUILTIN_VEC_MUL)
5827     {
5828       /* vec_mul needs to be special cased because there are no instructions
5829          for it for the {un}signed char, {un}signed short, and {un}signed int
5830          types.  */
5831       if (nargs != 2)
5832         {
5833           error ("builtin %qs only accepts 2 arguments", "vec_mul");
5834           return error_mark_node;
5835         }
5836
5837       tree arg0 = (*arglist)[0];
5838       tree arg0_type = TREE_TYPE (arg0);
5839       tree arg1 = (*arglist)[1];
5840       tree arg1_type = TREE_TYPE (arg1);
5841
5842       /* Both arguments must be vectors and the types must be compatible.  */
5843       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5844         goto bad;
5845       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
5846         goto bad;
5847
5848       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5849         {
5850           case E_QImode:
5851           case E_HImode:
5852           case E_SImode:
5853           case E_DImode:
5854           case E_TImode:
5855             {
5856               /* For scalar types just use a multiply expression.  */
5857               return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0,
5858                                       fold_convert (TREE_TYPE (arg0), arg1));
5859             }
5860           case E_SFmode:
5861             {
5862               /* For floats use the xvmulsp instruction directly.  */
5863               tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP];
5864               return build_call_expr (call, 2, arg0, arg1);
5865             }
5866           case E_DFmode:
5867             {
5868               /* For doubles use the xvmuldp instruction directly.  */
5869               tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP];
5870               return build_call_expr (call, 2, arg0, arg1);
5871             }
5872           /* Other types are errors.  */
5873           default:
5874             goto bad;
5875         }
5876     }
5877
5878   if (fcode == ALTIVEC_BUILTIN_VEC_CMPNE)
5879     {
5880       /* vec_cmpne needs to be special cased because there are no instructions
5881          for it (prior to power 9).  */
5882       if (nargs != 2)
5883         {
5884           error ("builtin %qs only accepts 2 arguments", "vec_cmpne");
5885           return error_mark_node;
5886         }
5887
5888       tree arg0 = (*arglist)[0];
5889       tree arg0_type = TREE_TYPE (arg0);
5890       tree arg1 = (*arglist)[1];
5891       tree arg1_type = TREE_TYPE (arg1);
5892
5893       /* Both arguments must be vectors and the types must be compatible.  */
5894       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5895         goto bad;
5896       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type))
5897         goto bad;
5898
5899       /* Power9 instructions provide the most efficient implementation of
5900          ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode
5901          or SFmode or DFmode.  */
5902       if (!TARGET_P9_VECTOR
5903           || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
5904           || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode)
5905           || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode)
5906           || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode))
5907         {
5908           switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5909             {
5910               /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
5911                  vec_cmpeq (va, vb)).  */
5912               /* Note:  vec_nand also works but opt changes vec_nand's
5913                  to vec_nor's anyway.  */
5914             case E_QImode:
5915             case E_HImode:
5916             case E_SImode:
5917             case E_DImode:
5918             case E_TImode:
5919             case E_SFmode:
5920             case E_DFmode:
5921               {
5922                 /* call = vec_cmpeq (va, vb)
5923                    result = vec_nor (call, call).  */
5924                 vec<tree, va_gc> *params = make_tree_vector ();
5925                 vec_safe_push (params, arg0);
5926                 vec_safe_push (params, arg1);
5927                 tree call = altivec_resolve_overloaded_builtin
5928                   (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ],
5929                    params);
5930                 /* Use save_expr to ensure that operands used more than once
5931                    that may have side effects (like calls) are only evaluated
5932                    once.  */
5933                 call = save_expr (call);
5934                 params = make_tree_vector ();
5935                 vec_safe_push (params, call);
5936                 vec_safe_push (params, call);
5937                 return altivec_resolve_overloaded_builtin
5938                   (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params);
5939               }
5940               /* Other types are errors.  */
5941             default:
5942               goto bad;
5943             }
5944         }
5945       /* else, fall through and process the Power9 alternative below */
5946     }
5947
5948   if (fcode == ALTIVEC_BUILTIN_VEC_ADDE
5949       || fcode == ALTIVEC_BUILTIN_VEC_SUBE)
5950     {
5951       /* vec_adde needs to be special cased because there is no instruction
5952           for the {un}signed int version.  */
5953       if (nargs != 3)
5954         {
5955           const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDE ?
5956             "vec_adde": "vec_sube";
5957           error ("builtin %qs only accepts 3 arguments", name);
5958           return error_mark_node;
5959         }
5960
5961       tree arg0 = (*arglist)[0];
5962       tree arg0_type = TREE_TYPE (arg0);
5963       tree arg1 = (*arglist)[1];
5964       tree arg1_type = TREE_TYPE (arg1);
5965       tree arg2 = (*arglist)[2];
5966       tree arg2_type = TREE_TYPE (arg2);
5967
5968       /* All 3 arguments must be vectors of (signed or unsigned) (int or
5969          __int128) and the types must be compatible.  */
5970       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
5971         goto bad;
5972       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)
5973           || !lang_hooks.types_compatible_p (arg1_type, arg2_type))
5974         goto bad;
5975
5976       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
5977         {
5978           /* For {un}signed ints,
5979              vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb),
5980                                                    vec_and (carryv, 1)).
5981              vec_sube (va, vb, carryv) == vec_sub (vec_sub (va, vb),
5982                                                    vec_and (carryv, 1)).  */
5983           case E_SImode:
5984             {
5985               tree add_sub_builtin;
5986
5987               vec<tree, va_gc> *params = make_tree_vector ();
5988               vec_safe_push (params, arg0);
5989               vec_safe_push (params, arg1);
5990
5991               if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
5992                 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
5993               else
5994                 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
5995
5996               tree call = altivec_resolve_overloaded_builtin (loc,
5997                                                               add_sub_builtin,
5998                                                               params);
5999               tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
6000               tree ones_vector = build_vector_from_val (arg0_type, const1);
6001               tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
6002                                                arg2, ones_vector);
6003               params = make_tree_vector ();
6004               vec_safe_push (params, call);
6005               vec_safe_push (params, and_expr);
6006               return altivec_resolve_overloaded_builtin (loc, add_sub_builtin,
6007                                                          params);
6008             }
6009           /* For {un}signed __int128s use the vaddeuqm instruction
6010                 directly.  */
6011           case E_TImode:
6012             {
6013                tree bii;
6014
6015                if (fcode == ALTIVEC_BUILTIN_VEC_ADDE)
6016                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM];
6017
6018                else
6019                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBEUQM];
6020
6021                return altivec_resolve_overloaded_builtin (loc, bii, arglist);
6022             }
6023
6024           /* Types other than {un}signed int and {un}signed __int128
6025                 are errors.  */
6026           default:
6027             goto bad;
6028         }
6029     }
6030
6031   if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC
6032       || fcode == ALTIVEC_BUILTIN_VEC_SUBEC)
6033     {
6034       /* vec_addec and vec_subec needs to be special cased because there is
6035          no instruction for the {un}signed int version.  */
6036       if (nargs != 3)
6037         {
6038           const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDEC ?
6039             "vec_addec": "vec_subec";
6040           error ("builtin %qs only accepts 3 arguments", name);
6041           return error_mark_node;
6042         }
6043
6044       tree arg0 = (*arglist)[0];
6045       tree arg0_type = TREE_TYPE (arg0);
6046       tree arg1 = (*arglist)[1];
6047       tree arg1_type = TREE_TYPE (arg1);
6048       tree arg2 = (*arglist)[2];
6049       tree arg2_type = TREE_TYPE (arg2);
6050
6051       /* All 3 arguments must be vectors of (signed or unsigned) (int or
6052          __int128) and the types must be compatible.  */
6053       if (TREE_CODE (arg0_type) != VECTOR_TYPE)
6054         goto bad;
6055       if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)
6056           || !lang_hooks.types_compatible_p (arg1_type, arg2_type))
6057         goto bad;
6058
6059       switch (TYPE_MODE (TREE_TYPE (arg0_type)))
6060         {
6061           /* For {un}signed ints,
6062               vec_addec (va, vb, carryv) ==
6063                                 vec_or (vec_addc (va, vb),
6064                                         vec_addc (vec_add (va, vb),
6065                                                   vec_and (carryv, 0x1))).  */
6066           case E_SImode:
6067             {
6068             /* Use save_expr to ensure that operands used more than once
6069                 that may have side effects (like calls) are only evaluated
6070                 once.  */
6071             tree as_builtin;
6072             tree as_c_builtin;
6073
6074             arg0 = save_expr (arg0);
6075             arg1 = save_expr (arg1);
6076             vec<tree, va_gc> *params = make_tree_vector ();
6077             vec_safe_push (params, arg0);
6078             vec_safe_push (params, arg1);
6079
6080             if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6081               as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADDC];
6082             else
6083               as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUBC];
6084
6085             tree call1 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
6086                                                              params);
6087             params = make_tree_vector ();
6088             vec_safe_push (params, arg0);
6089             vec_safe_push (params, arg1);
6090
6091
6092             if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6093               as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD];
6094             else
6095               as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB];
6096
6097             tree call2 = altivec_resolve_overloaded_builtin (loc, as_builtin,
6098                                                              params);
6099             tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1);
6100             tree ones_vector = build_vector_from_val (arg0_type, const1);
6101             tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type,
6102                                              arg2, ones_vector);
6103             params = make_tree_vector ();
6104             vec_safe_push (params, call2);
6105             vec_safe_push (params, and_expr);
6106             call2 = altivec_resolve_overloaded_builtin (loc, as_c_builtin,
6107                                                         params);
6108             params = make_tree_vector ();
6109             vec_safe_push (params, call1);
6110             vec_safe_push (params, call2);
6111             tree or_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_OR];
6112             return altivec_resolve_overloaded_builtin (loc, or_builtin,
6113                                                        params);
6114             }
6115           /* For {un}signed __int128s use the vaddecuq/vsubbecuq
6116              instructions.  */
6117           case E_TImode:
6118             {
6119                tree bii;
6120
6121                if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC)
6122                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ];
6123
6124                else
6125                  bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBECUQ];
6126
6127                return altivec_resolve_overloaded_builtin (loc, bii, arglist);
6128             }
6129           /* Types other than {un}signed int and {un}signed __int128
6130                 are errors.  */
6131           default:
6132             goto bad;
6133         }
6134     }
6135
6136   /* For now treat vec_splats and vec_promote as the same.  */
6137   if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS
6138       || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)
6139     {
6140       tree type, arg;
6141       int size;
6142       int i;
6143       bool unsigned_p;
6144       vec<constructor_elt, va_gc> *vec;
6145       const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote";
6146
6147       if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1)
6148         {
6149           error ("builtin %qs only accepts 1 argument", name);
6150           return error_mark_node;
6151         }
6152       if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2)
6153         {
6154           error ("builtin %qs only accepts 2 arguments", name);
6155           return error_mark_node;
6156         }
6157       /* Ignore promote's element argument.  */
6158       if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE
6159           && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1])))
6160         goto bad;
6161
6162       arg = (*arglist)[0];
6163       type = TREE_TYPE (arg);
6164       if (!SCALAR_FLOAT_TYPE_P (type)
6165           && !INTEGRAL_TYPE_P (type))
6166         goto bad;
6167       unsigned_p = TYPE_UNSIGNED (type);
6168       switch (TYPE_MODE (type))
6169         {
6170           case E_TImode:
6171             type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
6172             size = 1;
6173             break;
6174           case E_DImode:
6175             type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
6176             size = 2;
6177             break;
6178           case E_SImode:
6179             type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
6180             size = 4;
6181             break;
6182           case E_HImode:
6183             type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
6184             size = 8;
6185             break;
6186           case E_QImode:
6187             type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
6188             size = 16;
6189             break;
6190           case E_SFmode: type = V4SF_type_node; size = 4; break;
6191           case E_DFmode: type = V2DF_type_node; size = 2; break;
6192           default:
6193             goto bad;
6194         }
6195       arg = save_expr (fold_convert (TREE_TYPE (type), arg));
6196       vec_alloc (vec, size);
6197       for(i = 0; i < size; i++)
6198         {
6199           constructor_elt elt = {NULL_TREE, arg};
6200           vec->quick_push (elt);
6201         }
6202         return build_constructor (type, vec);
6203     }
6204
6205   /* For now use pointer tricks to do the extraction, unless we are on VSX
6206      extracting a double from a constant offset.  */
6207   if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT)
6208     {
6209       tree arg1;
6210       tree arg1_type;
6211       tree arg2;
6212       tree arg1_inner_type;
6213       tree decl, stmt;
6214       tree innerptrtype;
6215       machine_mode mode;
6216
6217       /* No second argument. */
6218       if (nargs != 2)
6219         {
6220           error ("builtin %qs only accepts 2 arguments", "vec_extract");
6221           return error_mark_node;
6222         }
6223
6224       arg2 = (*arglist)[1];
6225       arg1 = (*arglist)[0];
6226       arg1_type = TREE_TYPE (arg1);
6227
6228       if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6229         goto bad;
6230       if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6231         goto bad;
6232
6233       /* If we are targeting little-endian, but -maltivec=be has been
6234          specified to override the element order, adjust the element
6235          number accordingly.  */
6236       if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6237         {
6238           unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6239           arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6240                                   build_int_cstu (TREE_TYPE (arg2), last_elem),
6241                                   arg2);
6242         }
6243
6244       /* See if we can optimize vec_extracts with the current VSX instruction
6245          set.  */
6246       mode = TYPE_MODE (arg1_type);
6247       if (VECTOR_MEM_VSX_P (mode))
6248
6249         {
6250           tree call = NULL_TREE;
6251           int nunits = GET_MODE_NUNITS (mode);
6252
6253           /* If the second argument is an integer constant, if the value is in
6254              the expected range, generate the built-in code if we can.  We need
6255              64-bit and direct move to extract the small integer vectors.  */
6256           if (TREE_CODE (arg2) == INTEGER_CST
6257               && wi::ltu_p (wi::to_wide (arg2), nunits))
6258             {
6259               switch (mode)
6260                 {
6261                 default:
6262                   break;
6263
6264                 case E_V1TImode:
6265                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI];
6266                   break;
6267
6268                 case E_V2DFmode:
6269                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6270                   break;
6271
6272                 case E_V2DImode:
6273                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6274                   break;
6275
6276                 case E_V4SFmode:
6277                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6278                   break;
6279
6280                 case E_V4SImode:
6281                   if (TARGET_DIRECT_MOVE_64BIT)
6282                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6283                   break;
6284
6285                 case E_V8HImode:
6286                   if (TARGET_DIRECT_MOVE_64BIT)
6287                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6288                   break;
6289
6290                 case E_V16QImode:
6291                   if (TARGET_DIRECT_MOVE_64BIT)
6292                     call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6293                   break;
6294                 }
6295             }
6296
6297           /* If the second argument is variable, we can optimize it if we are
6298              generating 64-bit code on a machine with direct move.  */
6299           else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT)
6300             {
6301               switch (mode)
6302                 {
6303                 default:
6304                   break;
6305
6306                 case E_V2DFmode:
6307                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF];
6308                   break;
6309
6310                 case E_V2DImode:
6311                   call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI];
6312                   break;
6313
6314                 case E_V4SFmode:
6315                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF];
6316                   break;
6317
6318                 case E_V4SImode:
6319                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI];
6320                   break;
6321
6322                 case E_V8HImode:
6323                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI];
6324                   break;
6325
6326                 case E_V16QImode:
6327                   call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI];
6328                   break;
6329                 }
6330             }
6331
6332           if (call)
6333             return build_call_expr (call, 2, arg1, arg2);
6334         }
6335
6336       /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */
6337       arg1_inner_type = TREE_TYPE (arg1_type);
6338       arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6339                               build_int_cst (TREE_TYPE (arg2),
6340                                              TYPE_VECTOR_SUBPARTS (arg1_type)
6341                                              - 1), 0);
6342       decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6343       DECL_EXTERNAL (decl) = 0;
6344       TREE_PUBLIC (decl) = 0;
6345       DECL_CONTEXT (decl) = current_function_decl;
6346       TREE_USED (decl) = 1;
6347       TREE_TYPE (decl) = arg1_type;
6348       TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6349       if (c_dialect_cxx ())
6350         {
6351           stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6352                          NULL_TREE, NULL_TREE);
6353           SET_EXPR_LOCATION (stmt, loc);
6354         }
6355       else
6356         {
6357           DECL_INITIAL (decl) = arg1;
6358           stmt = build1 (DECL_EXPR, arg1_type, decl);
6359           TREE_ADDRESSABLE (decl) = 1;
6360           SET_EXPR_LOCATION (stmt, loc);
6361           stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6362         }
6363
6364       innerptrtype = build_pointer_type (arg1_inner_type);
6365
6366       stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6367       stmt = convert (innerptrtype, stmt);
6368       stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6369       stmt = build_indirect_ref (loc, stmt, RO_NULL);
6370
6371       return stmt;
6372     }
6373
6374   /* For now use pointer tricks to do the insertion, unless we are on VSX
6375      inserting a double to a constant offset..  */
6376   if (fcode == ALTIVEC_BUILTIN_VEC_INSERT)
6377     {
6378       tree arg0;
6379       tree arg1;
6380       tree arg2;
6381       tree arg1_type;
6382       tree arg1_inner_type;
6383       tree decl, stmt;
6384       tree innerptrtype;
6385       machine_mode mode;
6386
6387       /* No second or third arguments. */
6388       if (nargs != 3)
6389         {
6390           error ("builtin %qs only accepts 3 arguments", "vec_insert");
6391           return error_mark_node;
6392         }
6393
6394       arg0 = (*arglist)[0];
6395       arg1 = (*arglist)[1];
6396       arg1_type = TREE_TYPE (arg1);
6397       arg2 = (*arglist)[2];
6398
6399       if (TREE_CODE (arg1_type) != VECTOR_TYPE)
6400         goto bad;
6401       if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2)))
6402         goto bad;
6403
6404       /* If we are targeting little-endian, but -maltivec=be has been
6405          specified to override the element order, adjust the element
6406          number accordingly.  */
6407       if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2)
6408         {
6409           unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1;
6410           arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2),
6411                                   build_int_cstu (TREE_TYPE (arg2), last_elem),
6412                                   arg2);
6413         }
6414
6415       /* If we can use the VSX xxpermdi instruction, use that for insert.  */
6416       mode = TYPE_MODE (arg1_type);
6417       if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode)
6418           && TREE_CODE (arg2) == INTEGER_CST
6419           && wi::ltu_p (wi::to_wide (arg2), 2))
6420         {
6421           tree call = NULL_TREE;
6422
6423           if (mode == V2DFmode)
6424             call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF];
6425           else if (mode == V2DImode)
6426             call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI];
6427
6428           /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6429              reversed.  */
6430           if (call)
6431             return build_call_expr (call, 3, arg1, arg0, arg2);
6432         }
6433       else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode)
6434                && TREE_CODE (arg2) == INTEGER_CST
6435                && wi::eq_p (wi::to_wide (arg2), 0))
6436         {
6437           tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI];
6438
6439           /* Note, __builtin_vec_insert_<xxx> has vector and scalar types
6440              reversed.  */
6441           return build_call_expr (call, 3, arg1, arg0, arg2);
6442         }
6443
6444       /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */
6445       arg1_inner_type = TREE_TYPE (arg1_type);
6446       arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2,
6447                               build_int_cst (TREE_TYPE (arg2),
6448                                              TYPE_VECTOR_SUBPARTS (arg1_type)
6449                                              - 1), 0);
6450       decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type);
6451       DECL_EXTERNAL (decl) = 0;
6452       TREE_PUBLIC (decl) = 0;
6453       DECL_CONTEXT (decl) = current_function_decl;
6454       TREE_USED (decl) = 1;
6455       TREE_TYPE (decl) = arg1_type;
6456       TREE_READONLY (decl) = TYPE_READONLY (arg1_type);
6457       if (c_dialect_cxx ())
6458         {
6459           stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1,
6460                          NULL_TREE, NULL_TREE);
6461           SET_EXPR_LOCATION (stmt, loc);
6462         }
6463       else
6464         {
6465           DECL_INITIAL (decl) = arg1;
6466           stmt = build1 (DECL_EXPR, arg1_type, decl);
6467           TREE_ADDRESSABLE (decl) = 1;
6468           SET_EXPR_LOCATION (stmt, loc);
6469           stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
6470         }
6471
6472       innerptrtype = build_pointer_type (arg1_inner_type);
6473
6474       stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0);
6475       stmt = convert (innerptrtype, stmt);
6476       stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1);
6477       stmt = build_indirect_ref (loc, stmt, RO_NULL);
6478       stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt,
6479                      convert (TREE_TYPE (stmt), arg0));
6480       stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl);
6481       return stmt;
6482     }
6483
6484   for (n = 0;
6485        !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs;
6486        fnargs = TREE_CHAIN (fnargs), n++)
6487     {
6488       tree decl_type = TREE_VALUE (fnargs);
6489       tree arg = (*arglist)[n];
6490       tree type;
6491
6492       if (arg == error_mark_node)
6493         return error_mark_node;
6494
6495       if (n >= 3)
6496         abort ();
6497
6498       arg = default_conversion (arg);
6499
6500       /* The C++ front-end converts float * to const void * using
6501          NOP_EXPR<const void *> (NOP_EXPR<void *> (x)).  */
6502       type = TREE_TYPE (arg);
6503       if (POINTER_TYPE_P (type)
6504           && TREE_CODE (arg) == NOP_EXPR
6505           && lang_hooks.types_compatible_p (TREE_TYPE (arg),
6506                                             const_ptr_type_node)
6507           && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)),
6508                                             ptr_type_node))
6509         {
6510           arg = TREE_OPERAND (arg, 0);
6511           type = TREE_TYPE (arg);
6512         }
6513
6514       /* Remove the const from the pointers to simplify the overload
6515          matching further down.  */
6516       if (POINTER_TYPE_P (decl_type)
6517           && POINTER_TYPE_P (type)
6518           && TYPE_QUALS (TREE_TYPE (type)) != 0)
6519         {
6520           if (TYPE_READONLY (TREE_TYPE (type))
6521               && !TYPE_READONLY (TREE_TYPE (decl_type)))
6522             warning (0, "passing arg %d of %qE discards qualifiers from "
6523                         "pointer target type", n + 1, fndecl);
6524           type = build_pointer_type (build_qualified_type (TREE_TYPE (type),
6525                                                            0));
6526           arg = fold_convert (type, arg);
6527         }
6528
6529       args[n] = arg;
6530       types[n] = type;
6531     }
6532
6533   /* If the number of arguments did not match the prototype, return NULL
6534      and the generic code will issue the appropriate error message.  */
6535   if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs)
6536     return NULL;
6537
6538   if (n == 0)
6539     abort ();
6540
6541   if (fcode == ALTIVEC_BUILTIN_VEC_STEP)
6542     {
6543       if (TREE_CODE (types[0]) != VECTOR_TYPE)
6544         goto bad;
6545
6546       return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0]));
6547     }
6548
6549   {
6550     bool unsupported_builtin = false;
6551     for (desc = altivec_overloaded_builtins;
6552          desc->code && desc->code != fcode; desc++)
6553       continue;
6554
6555     /* Need to special case __builtin_cmp because the overloaded forms
6556        of this function take (unsigned int, unsigned int) or (unsigned
6557        long long int, unsigned long long int).  Since C conventions
6558        allow the respective argument types to be implicitly coerced into
6559        each other, the default handling does not provide adequate
6560        discrimination between the desired forms of the function.  */
6561     if (fcode == P6_OV_BUILTIN_CMPB)
6562       {
6563         int overloaded_code;
6564         machine_mode arg1_mode = TYPE_MODE (types[0]);
6565         machine_mode arg2_mode = TYPE_MODE (types[1]);
6566
6567         if (nargs != 2)
6568           {
6569             error ("builtin %qs only accepts 2 arguments", "__builtin_cmpb");
6570             return error_mark_node;
6571           }
6572
6573         /* If any supplied arguments are wider than 32 bits, resolve to
6574            64-bit variant of built-in function.  */
6575         if ((GET_MODE_PRECISION (arg1_mode) > 32)
6576             || (GET_MODE_PRECISION (arg2_mode) > 32))
6577           {
6578             /* Assure all argument and result types are compatible with
6579                the built-in function represented by P6_BUILTIN_CMPB.  */
6580             overloaded_code = P6_BUILTIN_CMPB;
6581           }
6582         else
6583           {
6584             /* Assure all argument and result types are compatible with
6585                the built-in function represented by P6_BUILTIN_CMPB_32.  */
6586             overloaded_code = P6_BUILTIN_CMPB_32;
6587           }
6588
6589         while (desc->code && desc->code == fcode
6590                && desc->overloaded_code != overloaded_code)
6591           desc++;
6592
6593         if (desc->code && (desc->code == fcode)
6594             && rs6000_builtin_type_compatible (types[0], desc->op1)
6595             && rs6000_builtin_type_compatible (types[1], desc->op2))
6596           {
6597             if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6598               return altivec_build_resolved_builtin (args, n, desc);
6599             else
6600               unsupported_builtin = true;
6601           }
6602       }
6603     else if (fcode == P9V_BUILTIN_VEC_VSIEDP)
6604       {
6605         int overloaded_code;
6606         machine_mode arg1_mode = TYPE_MODE (types[0]);
6607
6608         if (nargs != 2)
6609           {
6610             error ("builtin %qs only accepts 2 arguments",
6611                    "scalar_insert_exp");
6612             return error_mark_node;
6613           }
6614
6615         /* If supplied first argument is wider than 64 bits, resolve to
6616            128-bit variant of built-in function.  */
6617         if (GET_MODE_PRECISION (arg1_mode) > 64)
6618           {
6619             /* If first argument is of float variety, choose variant
6620                that expects __ieee128 argument.  Otherwise, expect
6621                __int128 argument.  */
6622             if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
6623               overloaded_code = P9V_BUILTIN_VSIEQPF;
6624             else
6625               overloaded_code = P9V_BUILTIN_VSIEQP;
6626           }
6627         else
6628           {
6629             /* If first argument is of float variety, choose variant
6630                that expects double argument.  Otherwise, expect
6631                long long int argument.  */
6632             if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
6633               overloaded_code = P9V_BUILTIN_VSIEDPF;
6634             else
6635               overloaded_code = P9V_BUILTIN_VSIEDP;
6636           }
6637         while (desc->code && desc->code == fcode
6638                && desc->overloaded_code != overloaded_code)
6639           desc++;
6640         if (desc->code && (desc->code == fcode)
6641             && rs6000_builtin_type_compatible (types[0], desc->op1)
6642             && rs6000_builtin_type_compatible (types[1], desc->op2))
6643           {
6644             if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6645               return altivec_build_resolved_builtin (args, n, desc);
6646             else
6647               unsupported_builtin = true;
6648           }
6649       }
6650     else
6651       {
6652         /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in
6653            the opX fields.  */
6654         for (; desc->code == fcode; desc++)
6655           {
6656             if ((desc->op1 == RS6000_BTI_NOT_OPAQUE
6657                  || rs6000_builtin_type_compatible (types[0], desc->op1))
6658                 && (desc->op2 == RS6000_BTI_NOT_OPAQUE
6659                     || rs6000_builtin_type_compatible (types[1], desc->op2))
6660                 && (desc->op3 == RS6000_BTI_NOT_OPAQUE
6661                     || rs6000_builtin_type_compatible (types[2], desc->op3)))
6662               {
6663                 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE)
6664                   return altivec_build_resolved_builtin (args, n, desc);
6665                 else
6666                   unsupported_builtin = true;
6667               }
6668           }
6669       }
6670
6671     if (unsupported_builtin)
6672       {
6673         const char *name = rs6000_overloaded_builtin_name (fcode);
6674         error ("builtin function %qs not supported in this compiler "
6675                "configuration", name);
6676         return error_mark_node;
6677       }
6678   }
6679  bad:
6680   {
6681     const char *name = rs6000_overloaded_builtin_name (fcode);
6682     error ("invalid parameter combination for AltiVec intrinsic %qs", name);
6683     return error_mark_node;
6684   }
6685 }