gcc/config/powerpcspe/htmintrin.h

   1 /* Hardware Transactional Memory (HTM) intrinsics.
   2    Copyright (C) 2013-2017 Free Software Foundation, Inc.
   3    Contributed by Peter Bergner <bergner@vnet.ibm.com>.
   4
   5    This file is free software; you can redistribute it and/or modify it under
   6    the terms of the GNU General Public License as published by the Free
   7    Software Foundation; either version 3 of the License, or (at your option)
   8    any later version.
   9
  10    This file is distributed in the hope that it will be useful, but WITHOUT
  11    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13    for more details.
  14
  15    Under Section 7 of GPL version 3, you are granted additional
  16    permissions described in the GCC Runtime Library Exception, version
  17    3.1, as published by the Free Software Foundation.
  18
  19    You should have received a copy of the GNU General Public License and
  20    a copy of the GCC Runtime Library Exception along with this program;
  21    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  22    <http://www.gnu.org/licenses/>.  */
  23
  24 #ifndef __HTM__
  25 # error "HTM instruction set not enabled"
  26 #endif /* __HTM__ */
  27
  28 #ifndef _HTMINTRIN_H
  29 #define _HTMINTRIN_H
  30
  31 #include <stdint.h>
  32
  33 typedef uint64_t texasr_t;
  34 typedef uint32_t texasru_t;
  35 typedef uint32_t texasrl_t;
  36 typedef uintptr_t tfiar_t;
  37 typedef uintptr_t tfhar_t;
  38
  39 #define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3)
  40 #define _HTM_NONTRANSACTIONAL 0x0
  41 #define _HTM_SUSPENDED        0x1
  42 #define _HTM_TRANSACTIONAL    0x2
  43
  44 /* The following macros use the IBM bit numbering for BITNUM
  45    as used in the ISA documentation.  */
  46
  47 #define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
  48   (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1))
  49 #define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
  50   (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1))
  51
  52 #define _TEXASR_FAILURE_CODE(TEXASR) \
  53   _TEXASR_EXTRACT_BITS(TEXASR, 7, 8)
  54 #define _TEXASRU_FAILURE_CODE(TEXASRU) \
  55   _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8)
  56
  57 #define _TEXASR_FAILURE_PERSISTENT(TEXASR) \
  58   _TEXASR_EXTRACT_BITS(TEXASR, 7, 1)
  59 #define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \
  60   _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1)
  61
  62 #define _TEXASR_DISALLOWED(TEXASR) \
  63   _TEXASR_EXTRACT_BITS(TEXASR, 8, 1)
  64 #define _TEXASRU_DISALLOWED(TEXASRU) \
  65   _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1)
  66
  67 #define _TEXASR_NESTING_OVERFLOW(TEXASR) \
  68   _TEXASR_EXTRACT_BITS(TEXASR, 9, 1)
  69 #define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \
  70   _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1)
  71
  72 #define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \
  73   _TEXASR_EXTRACT_BITS(TEXASR, 10, 1)
  74 #define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \
  75   _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1)
  76
  77 #define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \
  78   _TEXASR_EXTRACT_BITS(TEXASR, 11, 1)
  79 #define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \
  80   _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1)
  81
  82 #define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \
  83   _TEXASR_EXTRACT_BITS(TEXASR, 12, 1)
  84 #define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \
  85   _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1)
  86
  87 #define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \
  88   _TEXASR_EXTRACT_BITS(TEXASR, 13, 1)
  89 #define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \
  90   _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1)
  91
  92 #define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \
  93   _TEXASR_EXTRACT_BITS(TEXASR, 14, 1)
  94 #define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \
  95   _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1)
  96
  97 #define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \
  98   _TEXASR_EXTRACT_BITS(TEXASR, 15, 1)
  99 #define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \
 100   _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1)
 101
 102 #define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \
 103   _TEXASR_EXTRACT_BITS(TEXASR, 16, 1)
 104 #define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \
 105   _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1)
 106
 107 #define _TEXASR_ABORT(TEXASR) \
 108   _TEXASR_EXTRACT_BITS(TEXASR, 31, 1)
 109 #define _TEXASRU_ABORT(TEXASRU) \
 110   _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1)
 111
 112
 113 #define _TEXASR_SUSPENDED(TEXASR) \
 114   _TEXASR_EXTRACT_BITS(TEXASR, 32, 1)
 115
 116 #define _TEXASR_PRIVILEGE(TEXASR) \
 117   _TEXASR_EXTRACT_BITS(TEXASR, 35, 2)
 118
 119 #define _TEXASR_FAILURE_SUMMARY(TEXASR) \
 120   _TEXASR_EXTRACT_BITS(TEXASR, 36, 1)
 121
 122 #define _TEXASR_TFIAR_EXACT(TEXASR) \
 123   _TEXASR_EXTRACT_BITS(TEXASR, 37, 1)
 124
 125 #define _TEXASR_ROT(TEXASR) \
 126   _TEXASR_EXTRACT_BITS(TEXASR, 38, 1)
 127
 128 #define _TEXASR_TRANSACTION_LEVEL(TEXASR) \
 129   _TEXASR_EXTRACT_BITS(TEXASR, 63, 12)
 130
 131 #endif /* _HTMINTRIN_H */