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mips.h (GR_REG_CLASS_P, [...]): Delete.
[official-gcc.git] / gcc / config / mips / mips.c
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1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING. If not, write to
24 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
26
27 #include "config.h"
28 #include "system.h"
29 #include "coretypes.h"
30 #include "tm.h"
31 #include <signal.h>
32 #include "rtl.h"
33 #include "regs.h"
34 #include "hard-reg-set.h"
35 #include "real.h"
36 #include "insn-config.h"
37 #include "conditions.h"
38 #include "insn-attr.h"
39 #include "recog.h"
40 #include "toplev.h"
41 #include "output.h"
42 #include "tree.h"
43 #include "function.h"
44 #include "expr.h"
45 #include "optabs.h"
46 #include "flags.h"
47 #include "reload.h"
48 #include "tm_p.h"
49 #include "ggc.h"
50 #include "gstab.h"
51 #include "hashtab.h"
52 #include "debug.h"
53 #include "target.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
59 #include "tree-gimple.h"
60 #include "bitmap.h"
61
62 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
70 XVECEXP (X, 0, 0)
71
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
78
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
82
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
87
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
91 part of the frame. */
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
96
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
104
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
110 : (INSN))
111
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
116 : (INSN))
117
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
124
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
127
128 /* Classifies an address.
129
130 ADDRESS_REG
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
133
134 ADDRESS_LO_SUM
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
137
138 ADDRESS_CONST_INT
139 A signed 16-bit constant address.
140
141 ADDRESS_SYMBOLIC:
142 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
143 enum mips_address_type {
144 ADDRESS_REG,
145 ADDRESS_LO_SUM,
146 ADDRESS_CONST_INT,
147 ADDRESS_SYMBOLIC
148 };
149
150 /* Classifies the prototype of a builtin function. */
151 enum mips_function_type
152 {
153 MIPS_V2SF_FTYPE_V2SF,
154 MIPS_V2SF_FTYPE_V2SF_V2SF,
155 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
156 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
157 MIPS_V2SF_FTYPE_SF_SF,
158 MIPS_INT_FTYPE_V2SF_V2SF,
159 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
160 MIPS_INT_FTYPE_SF_SF,
161 MIPS_INT_FTYPE_DF_DF,
162 MIPS_SF_FTYPE_V2SF,
163 MIPS_SF_FTYPE_SF,
164 MIPS_SF_FTYPE_SF_SF,
165 MIPS_DF_FTYPE_DF,
166 MIPS_DF_FTYPE_DF_DF,
167
168 /* For MIPS DSP ASE */
169 MIPS_DI_FTYPE_DI_SI,
170 MIPS_DI_FTYPE_DI_SI_SI,
171 MIPS_DI_FTYPE_DI_V2HI_V2HI,
172 MIPS_DI_FTYPE_DI_V4QI_V4QI,
173 MIPS_SI_FTYPE_DI_SI,
174 MIPS_SI_FTYPE_PTR_SI,
175 MIPS_SI_FTYPE_SI,
176 MIPS_SI_FTYPE_SI_SI,
177 MIPS_SI_FTYPE_V2HI,
178 MIPS_SI_FTYPE_V2HI_V2HI,
179 MIPS_SI_FTYPE_V4QI,
180 MIPS_SI_FTYPE_V4QI_V4QI,
181 MIPS_SI_FTYPE_VOID,
182 MIPS_V2HI_FTYPE_SI,
183 MIPS_V2HI_FTYPE_SI_SI,
184 MIPS_V2HI_FTYPE_V2HI,
185 MIPS_V2HI_FTYPE_V2HI_SI,
186 MIPS_V2HI_FTYPE_V2HI_V2HI,
187 MIPS_V2HI_FTYPE_V4QI,
188 MIPS_V2HI_FTYPE_V4QI_V2HI,
189 MIPS_V4QI_FTYPE_SI,
190 MIPS_V4QI_FTYPE_V2HI_V2HI,
191 MIPS_V4QI_FTYPE_V4QI_SI,
192 MIPS_V4QI_FTYPE_V4QI_V4QI,
193 MIPS_VOID_FTYPE_SI_SI,
194 MIPS_VOID_FTYPE_V2HI_V2HI,
195 MIPS_VOID_FTYPE_V4QI_V4QI,
196
197 /* For MIPS DSP REV 2 ASE. */
198 MIPS_V4QI_FTYPE_V4QI,
199 MIPS_SI_FTYPE_SI_SI_SI,
200 MIPS_DI_FTYPE_DI_USI_USI,
201 MIPS_DI_FTYPE_SI_SI,
202 MIPS_DI_FTYPE_USI_USI,
203 MIPS_V2HI_FTYPE_SI_SI_SI,
204
205 /* The last type. */
206 MIPS_MAX_FTYPE_MAX
207 };
208
209 /* Specifies how a builtin function should be converted into rtl. */
210 enum mips_builtin_type
211 {
212 /* The builtin corresponds directly to an .md pattern. The return
213 value is mapped to operand 0 and the arguments are mapped to
214 operands 1 and above. */
215 MIPS_BUILTIN_DIRECT,
216
217 /* The builtin corresponds directly to an .md pattern. There is no return
218 value and the arguments are mapped to operands 0 and above. */
219 MIPS_BUILTIN_DIRECT_NO_TARGET,
220
221 /* The builtin corresponds to a comparison instruction followed by
222 a mips_cond_move_tf_ps pattern. The first two arguments are the
223 values to compare and the second two arguments are the vector
224 operands for the movt.ps or movf.ps instruction (in assembly order). */
225 MIPS_BUILTIN_MOVF,
226 MIPS_BUILTIN_MOVT,
227
228 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
229 of this instruction is the result of the comparison, which has mode
230 CCV2 or CCV4. The function arguments are mapped to operands 1 and
231 above. The function's return value is an SImode boolean that is
232 true under the following conditions:
233
234 MIPS_BUILTIN_CMP_ANY: one of the registers is true
235 MIPS_BUILTIN_CMP_ALL: all of the registers are true
236 MIPS_BUILTIN_CMP_LOWER: the first register is true
237 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
238 MIPS_BUILTIN_CMP_ANY,
239 MIPS_BUILTIN_CMP_ALL,
240 MIPS_BUILTIN_CMP_UPPER,
241 MIPS_BUILTIN_CMP_LOWER,
242
243 /* As above, but the instruction only sets a single $fcc register. */
244 MIPS_BUILTIN_CMP_SINGLE,
245
246 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
247 MIPS_BUILTIN_BPOSGE32
248 };
249
250 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
251 #define MIPS_FP_CONDITIONS(MACRO) \
252 MACRO (f), \
253 MACRO (un), \
254 MACRO (eq), \
255 MACRO (ueq), \
256 MACRO (olt), \
257 MACRO (ult), \
258 MACRO (ole), \
259 MACRO (ule), \
260 MACRO (sf), \
261 MACRO (ngle), \
262 MACRO (seq), \
263 MACRO (ngl), \
264 MACRO (lt), \
265 MACRO (nge), \
266 MACRO (le), \
267 MACRO (ngt)
268
269 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
270 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
271 enum mips_fp_condition {
272 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
273 };
274
275 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
276 #define STRINGIFY(X) #X
277 static const char *const mips_fp_conditions[] = {
278 MIPS_FP_CONDITIONS (STRINGIFY)
279 };
280
281 /* A function to save or store a register. The first argument is the
282 register and the second is the stack slot. */
283 typedef void (*mips_save_restore_fn) (rtx, rtx);
284
285 struct mips16_constant;
286 struct mips_arg_info;
287 struct mips_address_info;
288 struct mips_integer_op;
289 struct mips_sim;
290
291 static enum mips_symbol_type mips_classify_symbol (rtx);
292 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
293 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
294 static bool mips_classify_address (struct mips_address_info *, rtx,
295 enum machine_mode, int);
296 static bool mips_cannot_force_const_mem (rtx);
297 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
298 static int mips_symbol_insns (enum mips_symbol_type);
299 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
300 static rtx mips_force_temporary (rtx, rtx);
301 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
302 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
303 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
304 static unsigned int mips_build_lower (struct mips_integer_op *,
305 unsigned HOST_WIDE_INT);
306 static unsigned int mips_build_integer (struct mips_integer_op *,
307 unsigned HOST_WIDE_INT);
308 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
309 static int m16_check_op (rtx, int, int, int);
310 static bool mips_rtx_costs (rtx, int, int, int *);
311 static int mips_address_cost (rtx);
312 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
313 static void mips_load_call_address (rtx, rtx, int);
314 static bool mips_function_ok_for_sibcall (tree, tree);
315 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
316 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
317 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
318 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
319 tree, int, struct mips_arg_info *);
320 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
321 static void mips_set_architecture (const struct mips_cpu_info *);
322 static void mips_set_tune (const struct mips_cpu_info *);
323 static bool mips_handle_option (size_t, const char *, int);
324 static struct machine_function *mips_init_machine_status (void);
325 static void print_operand_reloc (FILE *, rtx, const char **);
326 static void mips_file_start (void);
327 static bool mips_rewrite_small_data_p (rtx);
328 static int mips_small_data_pattern_1 (rtx *, void *);
329 static int mips_rewrite_small_data_1 (rtx *, void *);
330 static bool mips_function_has_gp_insn (void);
331 static unsigned int mips_global_pointer (void);
332 static bool mips_save_reg_p (unsigned int);
333 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
334 mips_save_restore_fn);
335 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
336 static void mips_output_cplocal (void);
337 static void mips_emit_loadgp (void);
338 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
339 static void mips_set_frame_expr (rtx);
340 static rtx mips_frame_set (rtx, rtx);
341 static void mips_save_reg (rtx, rtx);
342 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
343 static void mips_restore_reg (rtx, rtx);
344 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
345 HOST_WIDE_INT, tree);
346 static int symbolic_expression_p (rtx);
347 static section *mips_select_rtx_section (enum machine_mode, rtx,
348 unsigned HOST_WIDE_INT);
349 static section *mips_function_rodata_section (tree);
350 static bool mips_in_small_data_p (tree);
351 static bool mips_use_anchors_for_symbol_p (rtx);
352 static int mips_fpr_return_fields (tree, tree *);
353 static bool mips_return_in_msb (tree);
354 static rtx mips_return_fpr_pair (enum machine_mode mode,
355 enum machine_mode mode1, HOST_WIDE_INT,
356 enum machine_mode mode2, HOST_WIDE_INT);
357 static rtx mips16_gp_pseudo_reg (void);
358 static void mips16_fp_args (FILE *, int, int);
359 static void build_mips16_function_stub (FILE *);
360 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
361 static void dump_constants (struct mips16_constant *, rtx);
362 static int mips16_insn_length (rtx);
363 static int mips16_rewrite_pool_refs (rtx *, void *);
364 static void mips16_lay_out_constants (void);
365 static void mips_sim_reset (struct mips_sim *);
366 static void mips_sim_init (struct mips_sim *, state_t);
367 static void mips_sim_next_cycle (struct mips_sim *);
368 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
369 static int mips_sim_wait_regs_2 (rtx *, void *);
370 static void mips_sim_wait_regs_1 (rtx *, void *);
371 static void mips_sim_wait_regs (struct mips_sim *, rtx);
372 static void mips_sim_wait_units (struct mips_sim *, rtx);
373 static void mips_sim_wait_insn (struct mips_sim *, rtx);
374 static void mips_sim_record_set (rtx, rtx, void *);
375 static void mips_sim_issue_insn (struct mips_sim *, rtx);
376 static void mips_sim_issue_nop (struct mips_sim *);
377 static void mips_sim_finish_insn (struct mips_sim *, rtx);
378 static void vr4130_avoid_branch_rt_conflict (rtx);
379 static void vr4130_align_insns (void);
380 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
381 static void mips_avoid_hazards (void);
382 static void mips_reorg (void);
383 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
384 static bool mips_matching_cpu_name_p (const char *, const char *);
385 static const struct mips_cpu_info *mips_parse_cpu (const char *);
386 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
387 static bool mips_return_in_memory (tree, tree);
388 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
389 static void mips_macc_chains_record (rtx);
390 static void mips_macc_chains_reorder (rtx *, int);
391 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
392 static bool vr4130_true_reg_dependence_p (rtx);
393 static bool vr4130_swap_insns_p (rtx, rtx);
394 static void vr4130_reorder (rtx *, int);
395 static void mips_promote_ready (rtx *, int, int);
396 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
397 static int mips_variable_issue (FILE *, int, rtx, int);
398 static int mips_adjust_cost (rtx, rtx, rtx, int);
399 static int mips_issue_rate (void);
400 static int mips_multipass_dfa_lookahead (void);
401 static void mips_init_libfuncs (void);
402 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
403 tree, int *, int);
404 static tree mips_build_builtin_va_list (void);
405 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
406 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
407 tree, bool);
408 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
409 tree, bool);
410 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
411 tree, bool);
412 static bool mips_valid_pointer_mode (enum machine_mode);
413 static bool mips_vector_mode_supported_p (enum machine_mode);
414 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree, unsigned int);
415 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
416 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
417 static void mips_init_builtins (void);
418 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
419 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
420 enum insn_code, enum mips_fp_condition,
421 rtx, tree);
422 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
423 enum insn_code, enum mips_fp_condition,
424 rtx, tree);
425 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
426 static void mips_encode_section_info (tree, rtx, int);
427 static void mips_extra_live_on_entry (bitmap);
428 static int mips_comp_type_attributes (tree, tree);
429 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
430 static bool mips_offset_within_alignment_p (rtx, HOST_WIDE_INT);
431 static void mips_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
432
433 /* Structure to be filled in by compute_frame_size with register
434 save masks, and offsets for the current function. */
435
436 struct mips_frame_info GTY(())
437 {
438 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
439 HOST_WIDE_INT var_size; /* # bytes that variables take up */
440 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
441 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
442 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
443 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
444 unsigned int mask; /* mask of saved gp registers */
445 unsigned int fmask; /* mask of saved fp registers */
446 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
447 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
448 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
449 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
450 bool initialized; /* true if frame size already calculated */
451 int num_gp; /* number of gp registers saved */
452 int num_fp; /* number of fp registers saved */
453 };
454
455 struct machine_function GTY(()) {
456 /* Pseudo-reg holding the value of $28 in a mips16 function which
457 refers to GP relative global variables. */
458 rtx mips16_gp_pseudo_rtx;
459
460 /* The number of extra stack bytes taken up by register varargs.
461 This area is allocated by the callee at the very top of the frame. */
462 int varargs_size;
463
464 /* Current frame information, calculated by compute_frame_size. */
465 struct mips_frame_info frame;
466
467 /* The register to use as the global pointer within this function. */
468 unsigned int global_pointer;
469
470 /* True if mips_adjust_insn_length should ignore an instruction's
471 hazard attribute. */
472 bool ignore_hazard_length_p;
473
474 /* True if the whole function is suitable for .set noreorder and
475 .set nomacro. */
476 bool all_noreorder_p;
477
478 /* True if the function is known to have an instruction that needs $gp. */
479 bool has_gp_insn_p;
480 };
481
482 /* Information about a single argument. */
483 struct mips_arg_info
484 {
485 /* True if the argument is passed in a floating-point register, or
486 would have been if we hadn't run out of registers. */
487 bool fpr_p;
488
489 /* The number of words passed in registers, rounded up. */
490 unsigned int reg_words;
491
492 /* For EABI, the offset of the first register from GP_ARG_FIRST or
493 FP_ARG_FIRST. For other ABIs, the offset of the first register from
494 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
495 comment for details).
496
497 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
498 on the stack. */
499 unsigned int reg_offset;
500
501 /* The number of words that must be passed on the stack, rounded up. */
502 unsigned int stack_words;
503
504 /* The offset from the start of the stack overflow area of the argument's
505 first stack word. Only meaningful when STACK_WORDS is nonzero. */
506 unsigned int stack_offset;
507 };
508
509
510 /* Information about an address described by mips_address_type.
511
512 ADDRESS_CONST_INT
513 No fields are used.
514
515 ADDRESS_REG
516 REG is the base register and OFFSET is the constant offset.
517
518 ADDRESS_LO_SUM
519 REG is the register that contains the high part of the address,
520 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
521 is the type of OFFSET's symbol.
522
523 ADDRESS_SYMBOLIC
524 SYMBOL_TYPE is the type of symbol being referenced. */
525
526 struct mips_address_info
527 {
528 enum mips_address_type type;
529 rtx reg;
530 rtx offset;
531 enum mips_symbol_type symbol_type;
532 };
533
534
535 /* One stage in a constant building sequence. These sequences have
536 the form:
537
538 A = VALUE[0]
539 A = A CODE[1] VALUE[1]
540 A = A CODE[2] VALUE[2]
541 ...
542
543 where A is an accumulator, each CODE[i] is a binary rtl operation
544 and each VALUE[i] is a constant integer. */
545 struct mips_integer_op {
546 enum rtx_code code;
547 unsigned HOST_WIDE_INT value;
548 };
549
550
551 /* The largest number of operations needed to load an integer constant.
552 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
553 When the lowest bit is clear, we can try, but reject a sequence with
554 an extra SLL at the end. */
555 #define MIPS_MAX_INTEGER_OPS 7
556
557 /* Information about a MIPS16e SAVE or RESTORE instruction. */
558 struct mips16e_save_restore_info {
559 /* The number of argument registers saved by a SAVE instruction.
560 0 for RESTORE instructions. */
561 unsigned int nargs;
562
563 /* Bit X is set if the instruction saves or restores GPR X. */
564 unsigned int mask;
565
566 /* The total number of bytes to allocate. */
567 HOST_WIDE_INT size;
568 };
569
570 /* Global variables for machine-dependent things. */
571
572 /* Threshold for data being put into the small data/bss area, instead
573 of the normal data area. */
574 int mips_section_threshold = -1;
575
576 /* Count the number of .file directives, so that .loc is up to date. */
577 int num_source_filenames = 0;
578
579 /* Count the number of sdb related labels are generated (to find block
580 start and end boundaries). */
581 int sdb_label_count = 0;
582
583 /* Next label # for each statement for Silicon Graphics IRIS systems. */
584 int sym_lineno = 0;
585
586 /* Name of the file containing the current function. */
587 const char *current_function_file = "";
588
589 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
590 int set_noreorder;
591 int set_noat;
592 int set_nomacro;
593 int set_volatile;
594
595 /* The next branch instruction is a branch likely, not branch normal. */
596 int mips_branch_likely;
597
598 /* The operands passed to the last cmpMM expander. */
599 rtx cmp_operands[2];
600
601 /* The target cpu for code generation. */
602 enum processor_type mips_arch;
603 const struct mips_cpu_info *mips_arch_info;
604
605 /* The target cpu for optimization and scheduling. */
606 enum processor_type mips_tune;
607 const struct mips_cpu_info *mips_tune_info;
608
609 /* Which instruction set architecture to use. */
610 int mips_isa;
611
612 /* Which ABI to use. */
613 int mips_abi = MIPS_ABI_DEFAULT;
614
615 /* Cost information to use. */
616 const struct mips_rtx_cost_data *mips_cost;
617
618 /* Whether we are generating mips16 hard float code. In mips16 mode
619 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
620 -msoft-float was not specified by the user, which means that we
621 should arrange to call mips32 hard floating point code. */
622 int mips16_hard_float;
623
624 /* The architecture selected by -mipsN. */
625 static const struct mips_cpu_info *mips_isa_info;
626
627 /* If TRUE, we split addresses into their high and low parts in the RTL. */
628 int mips_split_addresses;
629
630 /* Mode used for saving/restoring general purpose registers. */
631 static enum machine_mode gpr_mode;
632
633 /* Array giving truth value on whether or not a given hard register
634 can support a given mode. */
635 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
636
637 /* List of all MIPS punctuation characters used by print_operand. */
638 char mips_print_operand_punct[256];
639
640 /* Map GCC register number to debugger register number. */
641 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
642 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
643
644 /* A copy of the original flag_delayed_branch: see override_options. */
645 static int mips_flag_delayed_branch;
646
647 static GTY (()) int mips_output_filename_first_time = 1;
648
649 /* mips_split_p[X] is true if symbols of type X can be split by
650 mips_split_symbol(). */
651 bool mips_split_p[NUM_SYMBOL_TYPES];
652
653 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
654 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
655 if they are matched by a special .md file pattern. */
656 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
657
658 /* Likewise for HIGHs. */
659 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
660
661 /* Map hard register number to register class */
662 const enum reg_class mips_regno_to_class[] =
663 {
664 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
665 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
666 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
667 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
668 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
669 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
670 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
671 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
672 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
673 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
674 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
675 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
676 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
677 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
678 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
679 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
680 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
681 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
682 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
683 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
684 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
685 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
686 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
687 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
688 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
689 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
690 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
691 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
692 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
693 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
694 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
695 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
696 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
697 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
698 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
699 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
700 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
701 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
702 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
703 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
704 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
705 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
706 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
707 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
708 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
709 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
710 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
711 };
712
713 /* Table of machine dependent attributes. */
714 const struct attribute_spec mips_attribute_table[] =
715 {
716 { "long_call", 0, 0, false, true, true, NULL },
717 { "far", 0, 0, false, true, true, NULL },
718 { "near", 0, 0, false, true, true, NULL },
719 { NULL, 0, 0, false, false, false, NULL }
720 };
721 \f
722 /* A table describing all the processors gcc knows about. Names are
723 matched in the order listed. The first mention of an ISA level is
724 taken as the canonical name for that ISA.
725
726 To ease comparison, please keep this table in the same order as
727 gas's mips_cpu_info_table[]. Please also make sure that
728 MIPS_ISA_LEVEL_SPEC handles all -march options correctly. */
729 const struct mips_cpu_info mips_cpu_info_table[] = {
730 /* Entries for generic ISAs */
731 { "mips1", PROCESSOR_R3000, 1 },
732 { "mips2", PROCESSOR_R6000, 2 },
733 { "mips3", PROCESSOR_R4000, 3 },
734 { "mips4", PROCESSOR_R8000, 4 },
735 { "mips32", PROCESSOR_4KC, 32 },
736 { "mips32r2", PROCESSOR_M4K, 33 },
737 { "mips64", PROCESSOR_5KC, 64 },
738
739 /* MIPS I */
740 { "r3000", PROCESSOR_R3000, 1 },
741 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
742 { "r3900", PROCESSOR_R3900, 1 },
743
744 /* MIPS II */
745 { "r6000", PROCESSOR_R6000, 2 },
746
747 /* MIPS III */
748 { "r4000", PROCESSOR_R4000, 3 },
749 { "vr4100", PROCESSOR_R4100, 3 },
750 { "vr4111", PROCESSOR_R4111, 3 },
751 { "vr4120", PROCESSOR_R4120, 3 },
752 { "vr4130", PROCESSOR_R4130, 3 },
753 { "vr4300", PROCESSOR_R4300, 3 },
754 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
755 { "r4600", PROCESSOR_R4600, 3 },
756 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
757 { "r4650", PROCESSOR_R4650, 3 },
758
759 /* MIPS IV */
760 { "r8000", PROCESSOR_R8000, 4 },
761 { "vr5000", PROCESSOR_R5000, 4 },
762 { "vr5400", PROCESSOR_R5400, 4 },
763 { "vr5500", PROCESSOR_R5500, 4 },
764 { "rm7000", PROCESSOR_R7000, 4 },
765 { "rm9000", PROCESSOR_R9000, 4 },
766
767 /* MIPS32 */
768 { "4kc", PROCESSOR_4KC, 32 },
769 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
770 { "4kp", PROCESSOR_4KP, 32 },
771 { "4ksc", PROCESSOR_4KC, 32 },
772
773 /* MIPS32 Release 2 */
774 { "m4k", PROCESSOR_M4K, 33 },
775 { "4kec", PROCESSOR_4KC, 33 },
776 { "4kem", PROCESSOR_4KC, 33 },
777 { "4kep", PROCESSOR_4KP, 33 },
778 { "4ksd", PROCESSOR_4KC, 33 },
779
780 { "24kc", PROCESSOR_24KC, 33 },
781 { "24kf2_1", PROCESSOR_24KF2_1, 33 },
782 { "24kf", PROCESSOR_24KF2_1, 33 },
783 { "24kf1_1", PROCESSOR_24KF1_1, 33 },
784 { "24kfx", PROCESSOR_24KF1_1, 33 },
785 { "24kx", PROCESSOR_24KF1_1, 33 },
786
787 { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
788 { "24kef2_1", PROCESSOR_24KF2_1, 33 },
789 { "24kef", PROCESSOR_24KF2_1, 33 },
790 { "24kef1_1", PROCESSOR_24KF1_1, 33 },
791 { "24kefx", PROCESSOR_24KF1_1, 33 },
792 { "24kex", PROCESSOR_24KF1_1, 33 },
793
794 { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
795 { "34kf2_1", PROCESSOR_24KF2_1, 33 },
796 { "34kf", PROCESSOR_24KF2_1, 33 },
797 { "34kf1_1", PROCESSOR_24KF1_1, 33 },
798 { "34kfx", PROCESSOR_24KF1_1, 33 },
799 { "34kx", PROCESSOR_24KF1_1, 33 },
800
801 { "74kc", PROCESSOR_74KC, 33 }, /* 74K with DSPr2 */
802 { "74kf2_1", PROCESSOR_74KF2_1, 33 },
803 { "74kf", PROCESSOR_74KF2_1, 33 },
804 { "74kf1_1", PROCESSOR_74KF1_1, 33 },
805 { "74kfx", PROCESSOR_74KF1_1, 33 },
806 { "74kx", PROCESSOR_74KF1_1, 33 },
807 { "74kf3_2", PROCESSOR_74KF3_2, 33 },
808
809 /* MIPS64 */
810 { "5kc", PROCESSOR_5KC, 64 },
811 { "5kf", PROCESSOR_5KF, 64 },
812 { "20kc", PROCESSOR_20KC, 64 },
813 { "sb1", PROCESSOR_SB1, 64 },
814 { "sb1a", PROCESSOR_SB1A, 64 },
815 { "sr71000", PROCESSOR_SR71000, 64 },
816
817 /* End marker */
818 { 0, 0, 0 }
819 };
820
821 /* Default costs. If these are used for a processor we should look
822 up the actual costs. */
823 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
824 COSTS_N_INSNS (7), /* fp_mult_sf */ \
825 COSTS_N_INSNS (8), /* fp_mult_df */ \
826 COSTS_N_INSNS (23), /* fp_div_sf */ \
827 COSTS_N_INSNS (36), /* fp_div_df */ \
828 COSTS_N_INSNS (10), /* int_mult_si */ \
829 COSTS_N_INSNS (10), /* int_mult_di */ \
830 COSTS_N_INSNS (69), /* int_div_si */ \
831 COSTS_N_INSNS (69), /* int_div_di */ \
832 2, /* branch_cost */ \
833 4 /* memory_latency */
834
835 /* Need to replace these with the costs of calling the appropriate
836 libgcc routine. */
837 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
838 COSTS_N_INSNS (256), /* fp_mult_sf */ \
839 COSTS_N_INSNS (256), /* fp_mult_df */ \
840 COSTS_N_INSNS (256), /* fp_div_sf */ \
841 COSTS_N_INSNS (256) /* fp_div_df */
842
843 static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
844 {
845 COSTS_N_INSNS (1), /* fp_add */
846 COSTS_N_INSNS (1), /* fp_mult_sf */
847 COSTS_N_INSNS (1), /* fp_mult_df */
848 COSTS_N_INSNS (1), /* fp_div_sf */
849 COSTS_N_INSNS (1), /* fp_div_df */
850 COSTS_N_INSNS (1), /* int_mult_si */
851 COSTS_N_INSNS (1), /* int_mult_di */
852 COSTS_N_INSNS (1), /* int_div_si */
853 COSTS_N_INSNS (1), /* int_div_di */
854 2, /* branch_cost */
855 4 /* memory_latency */
856 };
857
858 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
859 {
860 { /* R3000 */
861 COSTS_N_INSNS (2), /* fp_add */
862 COSTS_N_INSNS (4), /* fp_mult_sf */
863 COSTS_N_INSNS (5), /* fp_mult_df */
864 COSTS_N_INSNS (12), /* fp_div_sf */
865 COSTS_N_INSNS (19), /* fp_div_df */
866 COSTS_N_INSNS (12), /* int_mult_si */
867 COSTS_N_INSNS (12), /* int_mult_di */
868 COSTS_N_INSNS (35), /* int_div_si */
869 COSTS_N_INSNS (35), /* int_div_di */
870 1, /* branch_cost */
871 4 /* memory_latency */
872
873 },
874 { /* 4KC */
875 SOFT_FP_COSTS,
876 COSTS_N_INSNS (6), /* int_mult_si */
877 COSTS_N_INSNS (6), /* int_mult_di */
878 COSTS_N_INSNS (36), /* int_div_si */
879 COSTS_N_INSNS (36), /* int_div_di */
880 1, /* branch_cost */
881 4 /* memory_latency */
882 },
883 { /* 4KP */
884 SOFT_FP_COSTS,
885 COSTS_N_INSNS (36), /* int_mult_si */
886 COSTS_N_INSNS (36), /* int_mult_di */
887 COSTS_N_INSNS (37), /* int_div_si */
888 COSTS_N_INSNS (37), /* int_div_di */
889 1, /* branch_cost */
890 4 /* memory_latency */
891 },
892 { /* 5KC */
893 SOFT_FP_COSTS,
894 COSTS_N_INSNS (4), /* int_mult_si */
895 COSTS_N_INSNS (11), /* int_mult_di */
896 COSTS_N_INSNS (36), /* int_div_si */
897 COSTS_N_INSNS (68), /* int_div_di */
898 1, /* branch_cost */
899 4 /* memory_latency */
900 },
901 { /* 5KF */
902 COSTS_N_INSNS (4), /* fp_add */
903 COSTS_N_INSNS (4), /* fp_mult_sf */
904 COSTS_N_INSNS (5), /* fp_mult_df */
905 COSTS_N_INSNS (17), /* fp_div_sf */
906 COSTS_N_INSNS (32), /* fp_div_df */
907 COSTS_N_INSNS (4), /* int_mult_si */
908 COSTS_N_INSNS (11), /* int_mult_di */
909 COSTS_N_INSNS (36), /* int_div_si */
910 COSTS_N_INSNS (68), /* int_div_di */
911 1, /* branch_cost */
912 4 /* memory_latency */
913 },
914 { /* 20KC */
915 COSTS_N_INSNS (4), /* fp_add */
916 COSTS_N_INSNS (4), /* fp_mult_sf */
917 COSTS_N_INSNS (5), /* fp_mult_df */
918 COSTS_N_INSNS (17), /* fp_div_sf */
919 COSTS_N_INSNS (32), /* fp_div_df */
920 COSTS_N_INSNS (4), /* int_mult_si */
921 COSTS_N_INSNS (7), /* int_mult_di */
922 COSTS_N_INSNS (42), /* int_div_si */
923 COSTS_N_INSNS (72), /* int_div_di */
924 1, /* branch_cost */
925 4 /* memory_latency */
926 },
927 { /* 24KC */
928 SOFT_FP_COSTS,
929 COSTS_N_INSNS (5), /* int_mult_si */
930 COSTS_N_INSNS (5), /* int_mult_di */
931 COSTS_N_INSNS (41), /* int_div_si */
932 COSTS_N_INSNS (41), /* int_div_di */
933 1, /* branch_cost */
934 4 /* memory_latency */
935 },
936 { /* 24KF2_1 */
937 COSTS_N_INSNS (8), /* fp_add */
938 COSTS_N_INSNS (8), /* fp_mult_sf */
939 COSTS_N_INSNS (10), /* fp_mult_df */
940 COSTS_N_INSNS (34), /* fp_div_sf */
941 COSTS_N_INSNS (64), /* fp_div_df */
942 COSTS_N_INSNS (5), /* int_mult_si */
943 COSTS_N_INSNS (5), /* int_mult_di */
944 COSTS_N_INSNS (41), /* int_div_si */
945 COSTS_N_INSNS (41), /* int_div_di */
946 1, /* branch_cost */
947 4 /* memory_latency */
948 },
949 { /* 24KF1_1 */
950 COSTS_N_INSNS (4), /* fp_add */
951 COSTS_N_INSNS (4), /* fp_mult_sf */
952 COSTS_N_INSNS (5), /* fp_mult_df */
953 COSTS_N_INSNS (17), /* fp_div_sf */
954 COSTS_N_INSNS (32), /* fp_div_df */
955 COSTS_N_INSNS (5), /* int_mult_si */
956 COSTS_N_INSNS (5), /* int_mult_di */
957 COSTS_N_INSNS (41), /* int_div_si */
958 COSTS_N_INSNS (41), /* int_div_di */
959 1, /* branch_cost */
960 4 /* memory_latency */
961 },
962 { /* 74KC */
963 SOFT_FP_COSTS,
964 COSTS_N_INSNS (5), /* int_mult_si */
965 COSTS_N_INSNS (5), /* int_mult_di */
966 COSTS_N_INSNS (41), /* int_div_si */
967 COSTS_N_INSNS (41), /* int_div_di */
968 1, /* branch_cost */
969 4 /* memory_latency */
970 },
971 { /* 74KF2_1 */
972 COSTS_N_INSNS (8), /* fp_add */
973 COSTS_N_INSNS (8), /* fp_mult_sf */
974 COSTS_N_INSNS (10), /* fp_mult_df */
975 COSTS_N_INSNS (34), /* fp_div_sf */
976 COSTS_N_INSNS (64), /* fp_div_df */
977 COSTS_N_INSNS (5), /* int_mult_si */
978 COSTS_N_INSNS (5), /* int_mult_di */
979 COSTS_N_INSNS (41), /* int_div_si */
980 COSTS_N_INSNS (41), /* int_div_di */
981 1, /* branch_cost */
982 4 /* memory_latency */
983 },
984 { /* 74KF1_1 */
985 COSTS_N_INSNS (4), /* fp_add */
986 COSTS_N_INSNS (4), /* fp_mult_sf */
987 COSTS_N_INSNS (5), /* fp_mult_df */
988 COSTS_N_INSNS (17), /* fp_div_sf */
989 COSTS_N_INSNS (32), /* fp_div_df */
990 COSTS_N_INSNS (5), /* int_mult_si */
991 COSTS_N_INSNS (5), /* int_mult_di */
992 COSTS_N_INSNS (41), /* int_div_si */
993 COSTS_N_INSNS (41), /* int_div_di */
994 1, /* branch_cost */
995 4 /* memory_latency */
996 },
997 { /* 74KF3_2 */
998 COSTS_N_INSNS (6), /* fp_add */
999 COSTS_N_INSNS (6), /* fp_mult_sf */
1000 COSTS_N_INSNS (7), /* fp_mult_df */
1001 COSTS_N_INSNS (25), /* fp_div_sf */
1002 COSTS_N_INSNS (48), /* fp_div_df */
1003 COSTS_N_INSNS (5), /* int_mult_si */
1004 COSTS_N_INSNS (5), /* int_mult_di */
1005 COSTS_N_INSNS (41), /* int_div_si */
1006 COSTS_N_INSNS (41), /* int_div_di */
1007 1, /* branch_cost */
1008 4 /* memory_latency */
1009 },
1010 { /* M4k */
1011 DEFAULT_COSTS
1012 },
1013 { /* R3900 */
1014 COSTS_N_INSNS (2), /* fp_add */
1015 COSTS_N_INSNS (4), /* fp_mult_sf */
1016 COSTS_N_INSNS (5), /* fp_mult_df */
1017 COSTS_N_INSNS (12), /* fp_div_sf */
1018 COSTS_N_INSNS (19), /* fp_div_df */
1019 COSTS_N_INSNS (2), /* int_mult_si */
1020 COSTS_N_INSNS (2), /* int_mult_di */
1021 COSTS_N_INSNS (35), /* int_div_si */
1022 COSTS_N_INSNS (35), /* int_div_di */
1023 1, /* branch_cost */
1024 4 /* memory_latency */
1025 },
1026 { /* R6000 */
1027 COSTS_N_INSNS (3), /* fp_add */
1028 COSTS_N_INSNS (5), /* fp_mult_sf */
1029 COSTS_N_INSNS (6), /* fp_mult_df */
1030 COSTS_N_INSNS (15), /* fp_div_sf */
1031 COSTS_N_INSNS (16), /* fp_div_df */
1032 COSTS_N_INSNS (17), /* int_mult_si */
1033 COSTS_N_INSNS (17), /* int_mult_di */
1034 COSTS_N_INSNS (38), /* int_div_si */
1035 COSTS_N_INSNS (38), /* int_div_di */
1036 2, /* branch_cost */
1037 6 /* memory_latency */
1038 },
1039 { /* R4000 */
1040 COSTS_N_INSNS (6), /* fp_add */
1041 COSTS_N_INSNS (7), /* fp_mult_sf */
1042 COSTS_N_INSNS (8), /* fp_mult_df */
1043 COSTS_N_INSNS (23), /* fp_div_sf */
1044 COSTS_N_INSNS (36), /* fp_div_df */
1045 COSTS_N_INSNS (10), /* int_mult_si */
1046 COSTS_N_INSNS (10), /* int_mult_di */
1047 COSTS_N_INSNS (69), /* int_div_si */
1048 COSTS_N_INSNS (69), /* int_div_di */
1049 2, /* branch_cost */
1050 6 /* memory_latency */
1051 },
1052 { /* R4100 */
1053 DEFAULT_COSTS
1054 },
1055 { /* R4111 */
1056 DEFAULT_COSTS
1057 },
1058 { /* R4120 */
1059 DEFAULT_COSTS
1060 },
1061 { /* R4130 */
1062 /* The only costs that appear to be updated here are
1063 integer multiplication. */
1064 SOFT_FP_COSTS,
1065 COSTS_N_INSNS (4), /* int_mult_si */
1066 COSTS_N_INSNS (6), /* int_mult_di */
1067 COSTS_N_INSNS (69), /* int_div_si */
1068 COSTS_N_INSNS (69), /* int_div_di */
1069 1, /* branch_cost */
1070 4 /* memory_latency */
1071 },
1072 { /* R4300 */
1073 DEFAULT_COSTS
1074 },
1075 { /* R4600 */
1076 DEFAULT_COSTS
1077 },
1078 { /* R4650 */
1079 DEFAULT_COSTS
1080 },
1081 { /* R5000 */
1082 COSTS_N_INSNS (6), /* fp_add */
1083 COSTS_N_INSNS (4), /* fp_mult_sf */
1084 COSTS_N_INSNS (5), /* fp_mult_df */
1085 COSTS_N_INSNS (23), /* fp_div_sf */
1086 COSTS_N_INSNS (36), /* fp_div_df */
1087 COSTS_N_INSNS (5), /* int_mult_si */
1088 COSTS_N_INSNS (5), /* int_mult_di */
1089 COSTS_N_INSNS (36), /* int_div_si */
1090 COSTS_N_INSNS (36), /* int_div_di */
1091 1, /* branch_cost */
1092 4 /* memory_latency */
1093 },
1094 { /* R5400 */
1095 COSTS_N_INSNS (6), /* fp_add */
1096 COSTS_N_INSNS (5), /* fp_mult_sf */
1097 COSTS_N_INSNS (6), /* fp_mult_df */
1098 COSTS_N_INSNS (30), /* fp_div_sf */
1099 COSTS_N_INSNS (59), /* fp_div_df */
1100 COSTS_N_INSNS (3), /* int_mult_si */
1101 COSTS_N_INSNS (4), /* int_mult_di */
1102 COSTS_N_INSNS (42), /* int_div_si */
1103 COSTS_N_INSNS (74), /* int_div_di */
1104 1, /* branch_cost */
1105 4 /* memory_latency */
1106 },
1107 { /* R5500 */
1108 COSTS_N_INSNS (6), /* fp_add */
1109 COSTS_N_INSNS (5), /* fp_mult_sf */
1110 COSTS_N_INSNS (6), /* fp_mult_df */
1111 COSTS_N_INSNS (30), /* fp_div_sf */
1112 COSTS_N_INSNS (59), /* fp_div_df */
1113 COSTS_N_INSNS (5), /* int_mult_si */
1114 COSTS_N_INSNS (9), /* int_mult_di */
1115 COSTS_N_INSNS (42), /* int_div_si */
1116 COSTS_N_INSNS (74), /* int_div_di */
1117 1, /* branch_cost */
1118 4 /* memory_latency */
1119 },
1120 { /* R7000 */
1121 /* The only costs that are changed here are
1122 integer multiplication. */
1123 COSTS_N_INSNS (6), /* fp_add */
1124 COSTS_N_INSNS (7), /* fp_mult_sf */
1125 COSTS_N_INSNS (8), /* fp_mult_df */
1126 COSTS_N_INSNS (23), /* fp_div_sf */
1127 COSTS_N_INSNS (36), /* fp_div_df */
1128 COSTS_N_INSNS (5), /* int_mult_si */
1129 COSTS_N_INSNS (9), /* int_mult_di */
1130 COSTS_N_INSNS (69), /* int_div_si */
1131 COSTS_N_INSNS (69), /* int_div_di */
1132 1, /* branch_cost */
1133 4 /* memory_latency */
1134 },
1135 { /* R8000 */
1136 DEFAULT_COSTS
1137 },
1138 { /* R9000 */
1139 /* The only costs that are changed here are
1140 integer multiplication. */
1141 COSTS_N_INSNS (6), /* fp_add */
1142 COSTS_N_INSNS (7), /* fp_mult_sf */
1143 COSTS_N_INSNS (8), /* fp_mult_df */
1144 COSTS_N_INSNS (23), /* fp_div_sf */
1145 COSTS_N_INSNS (36), /* fp_div_df */
1146 COSTS_N_INSNS (3), /* int_mult_si */
1147 COSTS_N_INSNS (8), /* int_mult_di */
1148 COSTS_N_INSNS (69), /* int_div_si */
1149 COSTS_N_INSNS (69), /* int_div_di */
1150 1, /* branch_cost */
1151 4 /* memory_latency */
1152 },
1153 { /* SB1 */
1154 /* These costs are the same as the SB-1A below. */
1155 COSTS_N_INSNS (4), /* fp_add */
1156 COSTS_N_INSNS (4), /* fp_mult_sf */
1157 COSTS_N_INSNS (4), /* fp_mult_df */
1158 COSTS_N_INSNS (24), /* fp_div_sf */
1159 COSTS_N_INSNS (32), /* fp_div_df */
1160 COSTS_N_INSNS (3), /* int_mult_si */
1161 COSTS_N_INSNS (4), /* int_mult_di */
1162 COSTS_N_INSNS (36), /* int_div_si */
1163 COSTS_N_INSNS (68), /* int_div_di */
1164 1, /* branch_cost */
1165 4 /* memory_latency */
1166 },
1167 { /* SB1-A */
1168 /* These costs are the same as the SB-1 above. */
1169 COSTS_N_INSNS (4), /* fp_add */
1170 COSTS_N_INSNS (4), /* fp_mult_sf */
1171 COSTS_N_INSNS (4), /* fp_mult_df */
1172 COSTS_N_INSNS (24), /* fp_div_sf */
1173 COSTS_N_INSNS (32), /* fp_div_df */
1174 COSTS_N_INSNS (3), /* int_mult_si */
1175 COSTS_N_INSNS (4), /* int_mult_di */
1176 COSTS_N_INSNS (36), /* int_div_si */
1177 COSTS_N_INSNS (68), /* int_div_di */
1178 1, /* branch_cost */
1179 4 /* memory_latency */
1180 },
1181 { /* SR71000 */
1182 DEFAULT_COSTS
1183 },
1184 };
1185
1186 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
1187 mips16e_s2_s8_regs[X], it must also save the registers in indexes
1188 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
1189 static const unsigned char mips16e_s2_s8_regs[] = {
1190 30, 23, 22, 21, 20, 19, 18
1191 };
1192 static const unsigned char mips16e_a0_a3_regs[] = {
1193 4, 5, 6, 7
1194 };
1195
1196 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
1197 ordered from the uppermost in memory to the lowest in memory. */
1198 static const unsigned char mips16e_save_restore_regs[] = {
1199 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
1200 };
1201 \f
1202 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1203 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1204 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1205 #endif
1206 \f
1207 /* Initialize the GCC target structure. */
1208 #undef TARGET_ASM_ALIGNED_HI_OP
1209 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1210 #undef TARGET_ASM_ALIGNED_SI_OP
1211 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1212 #undef TARGET_ASM_ALIGNED_DI_OP
1213 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1214
1215 #undef TARGET_ASM_FUNCTION_PROLOGUE
1216 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1217 #undef TARGET_ASM_FUNCTION_EPILOGUE
1218 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1219 #undef TARGET_ASM_SELECT_RTX_SECTION
1220 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1221 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1222 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1223
1224 #undef TARGET_SCHED_REORDER
1225 #define TARGET_SCHED_REORDER mips_sched_reorder
1226 #undef TARGET_SCHED_VARIABLE_ISSUE
1227 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1228 #undef TARGET_SCHED_ADJUST_COST
1229 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1230 #undef TARGET_SCHED_ISSUE_RATE
1231 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1232 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1233 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1234 mips_multipass_dfa_lookahead
1235
1236 #undef TARGET_DEFAULT_TARGET_FLAGS
1237 #define TARGET_DEFAULT_TARGET_FLAGS \
1238 (TARGET_DEFAULT \
1239 | TARGET_CPU_DEFAULT \
1240 | TARGET_ENDIAN_DEFAULT \
1241 | TARGET_FP_EXCEPTIONS_DEFAULT \
1242 | MASK_CHECK_ZERO_DIV \
1243 | MASK_FUSED_MADD)
1244 #undef TARGET_HANDLE_OPTION
1245 #define TARGET_HANDLE_OPTION mips_handle_option
1246
1247 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1248 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1249
1250 #undef TARGET_VALID_POINTER_MODE
1251 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1252 #undef TARGET_RTX_COSTS
1253 #define TARGET_RTX_COSTS mips_rtx_costs
1254 #undef TARGET_ADDRESS_COST
1255 #define TARGET_ADDRESS_COST mips_address_cost
1256
1257 #undef TARGET_IN_SMALL_DATA_P
1258 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1259
1260 #undef TARGET_MACHINE_DEPENDENT_REORG
1261 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1262
1263 #undef TARGET_ASM_FILE_START
1264 #define TARGET_ASM_FILE_START mips_file_start
1265 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1266 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1267
1268 #undef TARGET_INIT_LIBFUNCS
1269 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1270
1271 #undef TARGET_BUILD_BUILTIN_VA_LIST
1272 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1273 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1274 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1275
1276 #undef TARGET_PROMOTE_FUNCTION_ARGS
1277 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1278 #undef TARGET_PROMOTE_FUNCTION_RETURN
1279 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1280 #undef TARGET_PROMOTE_PROTOTYPES
1281 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1282
1283 #undef TARGET_RETURN_IN_MEMORY
1284 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1285 #undef TARGET_RETURN_IN_MSB
1286 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1287
1288 #undef TARGET_ASM_OUTPUT_MI_THUNK
1289 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1290 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1291 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1292
1293 #undef TARGET_SETUP_INCOMING_VARARGS
1294 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1295 #undef TARGET_STRICT_ARGUMENT_NAMING
1296 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1297 #undef TARGET_MUST_PASS_IN_STACK
1298 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1299 #undef TARGET_PASS_BY_REFERENCE
1300 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1301 #undef TARGET_CALLEE_COPIES
1302 #define TARGET_CALLEE_COPIES mips_callee_copies
1303 #undef TARGET_ARG_PARTIAL_BYTES
1304 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1305
1306 #undef TARGET_MODE_REP_EXTENDED
1307 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1308
1309 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1310 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1311
1312 #undef TARGET_INIT_BUILTINS
1313 #define TARGET_INIT_BUILTINS mips_init_builtins
1314 #undef TARGET_EXPAND_BUILTIN
1315 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1316
1317 #undef TARGET_HAVE_TLS
1318 #define TARGET_HAVE_TLS HAVE_AS_TLS
1319
1320 #undef TARGET_CANNOT_FORCE_CONST_MEM
1321 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1322
1323 #undef TARGET_ENCODE_SECTION_INFO
1324 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1325
1326 #undef TARGET_ATTRIBUTE_TABLE
1327 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1328
1329 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1330 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1331
1332 #undef TARGET_MIN_ANCHOR_OFFSET
1333 #define TARGET_MIN_ANCHOR_OFFSET -32768
1334 #undef TARGET_MAX_ANCHOR_OFFSET
1335 #define TARGET_MAX_ANCHOR_OFFSET 32767
1336 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1337 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1338 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1339 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1340
1341 #undef TARGET_COMP_TYPE_ATTRIBUTES
1342 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
1343
1344 #ifdef HAVE_AS_DTPRELWORD
1345 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1346 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
1347 #endif
1348
1349 struct gcc_target targetm = TARGET_INITIALIZER;
1350
1351
1352 /* Predicates to test for presence of "near" and "far"/"long_call"
1353 attributes on the given TYPE. */
1354
1355 static bool
1356 mips_near_type_p (tree type)
1357 {
1358 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1359 }
1360
1361 static bool
1362 mips_far_type_p (tree type)
1363 {
1364 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1365 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1366 }
1367
1368
1369 /* Return 0 if the attributes for two types are incompatible, 1 if they
1370 are compatible, and 2 if they are nearly compatible (which causes a
1371 warning to be generated). */
1372
1373 static int
1374 mips_comp_type_attributes (tree type1, tree type2)
1375 {
1376 /* Check for mismatch of non-default calling convention. */
1377 if (TREE_CODE (type1) != FUNCTION_TYPE)
1378 return 1;
1379
1380 /* Disallow mixed near/far attributes. */
1381 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1382 return 0;
1383 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1384 return 0;
1385
1386 return 1;
1387 }
1388 \f
1389 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1390 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1391
1392 static void
1393 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1394 {
1395 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1396 {
1397 *base_ptr = XEXP (x, 0);
1398 *offset_ptr = INTVAL (XEXP (x, 1));
1399 }
1400 else
1401 {
1402 *base_ptr = x;
1403 *offset_ptr = 0;
1404 }
1405 }
1406 \f
1407 /* Return true if SYMBOL_REF X is associated with a global symbol
1408 (in the STB_GLOBAL sense). */
1409
1410 static bool
1411 mips_global_symbol_p (rtx x)
1412 {
1413 tree decl;
1414
1415 decl = SYMBOL_REF_DECL (x);
1416 if (!decl)
1417 return !SYMBOL_REF_LOCAL_P (x);
1418
1419 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1420 or weak symbols. Relocations in the object file will be against
1421 the target symbol, so it's that symbol's binding that matters here. */
1422 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1423 }
1424
1425 /* Return true if SYMBOL_REF X binds locally. */
1426
1427 static bool
1428 mips_symbol_binds_local_p (rtx x)
1429 {
1430 return (SYMBOL_REF_DECL (x)
1431 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1432 : SYMBOL_REF_LOCAL_P (x));
1433 }
1434
1435 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1436
1437 static enum mips_symbol_type
1438 mips_classify_symbol (rtx x)
1439 {
1440 if (TARGET_RTP_PIC)
1441 return SYMBOL_GOT_DISP;
1442
1443 if (GET_CODE (x) == LABEL_REF)
1444 {
1445 if (TARGET_MIPS16)
1446 return SYMBOL_CONSTANT_POOL;
1447 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1448 return SYMBOL_GOT_PAGE_OFST;
1449 return SYMBOL_GENERAL;
1450 }
1451
1452 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1453
1454 if (SYMBOL_REF_TLS_MODEL (x))
1455 return SYMBOL_TLS;
1456
1457 if (CONSTANT_POOL_ADDRESS_P (x))
1458 {
1459 if (TARGET_MIPS16)
1460 return SYMBOL_CONSTANT_POOL;
1461
1462 if (!TARGET_EMBEDDED_DATA
1463 && GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1464 return SYMBOL_SMALL_DATA;
1465 }
1466
1467 /* Do not use small-data accesses for weak symbols; they may end up
1468 being zero. */
1469 if (SYMBOL_REF_SMALL_P (x)
1470 && !SYMBOL_REF_WEAK (x))
1471 return SYMBOL_SMALL_DATA;
1472
1473 if (TARGET_ABICALLS)
1474 {
1475 /* Don't use GOT accesses for locally-binding symbols; we can use
1476 %hi and %lo instead. */
1477 if (TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))
1478 return SYMBOL_GENERAL;
1479
1480 /* There are three cases to consider:
1481
1482 - o32 PIC (either with or without explicit relocs)
1483 - n32/n64 PIC without explicit relocs
1484 - n32/n64 PIC with explicit relocs
1485
1486 In the first case, both local and global accesses will use an
1487 R_MIPS_GOT16 relocation. We must correctly predict which of
1488 the two semantics (local or global) the assembler and linker
1489 will apply. The choice depends on the symbol's binding rather
1490 than its visibility.
1491
1492 In the second case, the assembler will not use R_MIPS_GOT16
1493 relocations, but it chooses between local and global accesses
1494 in the same way as for o32 PIC.
1495
1496 In the third case we have more freedom since both forms of
1497 access will work for any kind of symbol. However, there seems
1498 little point in doing things differently. */
1499 if (mips_global_symbol_p (x))
1500 return SYMBOL_GOT_DISP;
1501
1502 return SYMBOL_GOT_PAGE_OFST;
1503 }
1504
1505 return SYMBOL_GENERAL;
1506 }
1507
1508 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1509 is the alignment (in bytes) of SYMBOL_REF X. */
1510
1511 static bool
1512 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1513 {
1514 /* If for some reason we can't get the alignment for the
1515 symbol, initializing this to one means we will only accept
1516 a zero offset. */
1517 HOST_WIDE_INT align = 1;
1518 tree t;
1519
1520 /* Get the alignment of the symbol we're referring to. */
1521 t = SYMBOL_REF_DECL (x);
1522 if (t)
1523 align = DECL_ALIGN_UNIT (t);
1524
1525 return offset >= 0 && offset < align;
1526 }
1527
1528 /* Return true if X is a symbolic constant that can be calculated in
1529 the same way as a bare symbol. If it is, store the type of the
1530 symbol in *SYMBOL_TYPE. */
1531
1532 bool
1533 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1534 {
1535 rtx offset;
1536
1537 split_const (x, &x, &offset);
1538 if (UNSPEC_ADDRESS_P (x))
1539 {
1540 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1541 x = UNSPEC_ADDRESS (x);
1542 }
1543 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1544 {
1545 *symbol_type = mips_classify_symbol (x);
1546 if (*symbol_type == SYMBOL_TLS)
1547 return false;
1548 }
1549 else
1550 return false;
1551
1552 if (offset == const0_rtx)
1553 return true;
1554
1555 /* Check whether a nonzero offset is valid for the underlying
1556 relocations. */
1557 switch (*symbol_type)
1558 {
1559 case SYMBOL_GENERAL:
1560 case SYMBOL_64_HIGH:
1561 case SYMBOL_64_MID:
1562 case SYMBOL_64_LOW:
1563 /* If the target has 64-bit pointers and the object file only
1564 supports 32-bit symbols, the values of those symbols will be
1565 sign-extended. In this case we can't allow an arbitrary offset
1566 in case the 32-bit value X + OFFSET has a different sign from X. */
1567 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1568 return offset_within_block_p (x, INTVAL (offset));
1569
1570 /* In other cases the relocations can handle any offset. */
1571 return true;
1572
1573 case SYMBOL_CONSTANT_POOL:
1574 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1575 In this case, we no longer have access to the underlying constant,
1576 but the original symbol-based access was known to be valid. */
1577 if (GET_CODE (x) == LABEL_REF)
1578 return true;
1579
1580 /* Fall through. */
1581
1582 case SYMBOL_SMALL_DATA:
1583 /* Make sure that the offset refers to something within the
1584 same object block. This should guarantee that the final
1585 PC- or GP-relative offset is within the 16-bit limit. */
1586 return offset_within_block_p (x, INTVAL (offset));
1587
1588 case SYMBOL_GOT_PAGE_OFST:
1589 case SYMBOL_GOTOFF_PAGE:
1590 /* If the symbol is global, the GOT entry will contain the symbol's
1591 address, and we will apply a 16-bit offset after loading it.
1592 If the symbol is local, the linker should provide enough local
1593 GOT entries for a 16-bit offset, but larger offsets may lead
1594 to GOT overflow. */
1595 return SMALL_INT (offset);
1596
1597 case SYMBOL_TPREL:
1598 case SYMBOL_DTPREL:
1599 /* There is no carry between the HI and LO REL relocations, so the
1600 offset is only valid if we know it won't lead to such a carry. */
1601 return mips_offset_within_alignment_p (x, INTVAL (offset));
1602
1603 case SYMBOL_GOT_DISP:
1604 case SYMBOL_GOTOFF_DISP:
1605 case SYMBOL_GOTOFF_CALL:
1606 case SYMBOL_GOTOFF_LOADGP:
1607 case SYMBOL_TLSGD:
1608 case SYMBOL_TLSLDM:
1609 case SYMBOL_GOTTPREL:
1610 case SYMBOL_TLS:
1611 case SYMBOL_HALF:
1612 return false;
1613 }
1614 gcc_unreachable ();
1615 }
1616
1617
1618 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1619
1620 int
1621 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1622 {
1623 if (!HARD_REGISTER_NUM_P (regno))
1624 {
1625 if (!strict)
1626 return true;
1627 regno = reg_renumber[regno];
1628 }
1629
1630 /* These fake registers will be eliminated to either the stack or
1631 hard frame pointer, both of which are usually valid base registers.
1632 Reload deals with the cases where the eliminated form isn't valid. */
1633 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1634 return true;
1635
1636 /* In mips16 mode, the stack pointer can only address word and doubleword
1637 values, nothing smaller. There are two problems here:
1638
1639 (a) Instantiating virtual registers can introduce new uses of the
1640 stack pointer. If these virtual registers are valid addresses,
1641 the stack pointer should be too.
1642
1643 (b) Most uses of the stack pointer are not made explicit until
1644 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1645 We don't know until that stage whether we'll be eliminating to the
1646 stack pointer (which needs the restriction) or the hard frame
1647 pointer (which doesn't).
1648
1649 All in all, it seems more consistent to only enforce this restriction
1650 during and after reload. */
1651 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1652 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1653
1654 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1655 }
1656
1657
1658 /* Return true if X is a valid base register for the given mode.
1659 Allow only hard registers if STRICT. */
1660
1661 static bool
1662 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1663 {
1664 if (!strict && GET_CODE (x) == SUBREG)
1665 x = SUBREG_REG (x);
1666
1667 return (REG_P (x)
1668 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1669 }
1670
1671
1672 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1673 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1674
1675 static bool
1676 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1677 enum machine_mode mode)
1678 {
1679 switch (symbol_type)
1680 {
1681 case SYMBOL_GENERAL:
1682 return !TARGET_MIPS16;
1683
1684 case SYMBOL_SMALL_DATA:
1685 return true;
1686
1687 case SYMBOL_CONSTANT_POOL:
1688 /* PC-relative addressing is only available for lw and ld. */
1689 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1690
1691 case SYMBOL_GOT_PAGE_OFST:
1692 return true;
1693
1694 case SYMBOL_GOT_DISP:
1695 /* The address will have to be loaded from the GOT first. */
1696 return false;
1697
1698 case SYMBOL_GOTOFF_PAGE:
1699 case SYMBOL_GOTOFF_DISP:
1700 case SYMBOL_GOTOFF_CALL:
1701 case SYMBOL_GOTOFF_LOADGP:
1702 case SYMBOL_TLS:
1703 case SYMBOL_TLSGD:
1704 case SYMBOL_TLSLDM:
1705 case SYMBOL_DTPREL:
1706 case SYMBOL_GOTTPREL:
1707 case SYMBOL_TPREL:
1708 case SYMBOL_64_HIGH:
1709 case SYMBOL_64_MID:
1710 case SYMBOL_64_LOW:
1711 case SYMBOL_HALF:
1712 return true;
1713 }
1714 gcc_unreachable ();
1715 }
1716
1717
1718 /* Return true if X is a valid address for machine mode MODE. If it is,
1719 fill in INFO appropriately. STRICT is true if we should only accept
1720 hard base registers. */
1721
1722 static bool
1723 mips_classify_address (struct mips_address_info *info, rtx x,
1724 enum machine_mode mode, int strict)
1725 {
1726 switch (GET_CODE (x))
1727 {
1728 case REG:
1729 case SUBREG:
1730 info->type = ADDRESS_REG;
1731 info->reg = x;
1732 info->offset = const0_rtx;
1733 return mips_valid_base_register_p (info->reg, mode, strict);
1734
1735 case PLUS:
1736 info->type = ADDRESS_REG;
1737 info->reg = XEXP (x, 0);
1738 info->offset = XEXP (x, 1);
1739 return (mips_valid_base_register_p (info->reg, mode, strict)
1740 && const_arith_operand (info->offset, VOIDmode));
1741
1742 case LO_SUM:
1743 info->type = ADDRESS_LO_SUM;
1744 info->reg = XEXP (x, 0);
1745 info->offset = XEXP (x, 1);
1746 return (mips_valid_base_register_p (info->reg, mode, strict)
1747 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1748 && mips_symbolic_address_p (info->symbol_type, mode)
1749 && mips_lo_relocs[info->symbol_type] != 0);
1750
1751 case CONST_INT:
1752 /* Small-integer addresses don't occur very often, but they
1753 are legitimate if $0 is a valid base register. */
1754 info->type = ADDRESS_CONST_INT;
1755 return !TARGET_MIPS16 && SMALL_INT (x);
1756
1757 case CONST:
1758 case LABEL_REF:
1759 case SYMBOL_REF:
1760 info->type = ADDRESS_SYMBOLIC;
1761 return (mips_symbolic_constant_p (x, &info->symbol_type)
1762 && mips_symbolic_address_p (info->symbol_type, mode)
1763 && !mips_split_p[info->symbol_type]);
1764
1765 default:
1766 return false;
1767 }
1768 }
1769
1770 /* Return true if X is a thread-local symbol. */
1771
1772 static bool
1773 mips_tls_operand_p (rtx x)
1774 {
1775 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1776 }
1777
1778 /* Return true if X can not be forced into a constant pool. */
1779
1780 static int
1781 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1782 {
1783 return mips_tls_operand_p (*x);
1784 }
1785
1786 /* Return true if X can not be forced into a constant pool. */
1787
1788 static bool
1789 mips_cannot_force_const_mem (rtx x)
1790 {
1791 rtx base, offset;
1792
1793 if (!TARGET_MIPS16)
1794 {
1795 /* As an optimization, reject constants that mips_legitimize_move
1796 can expand inline.
1797
1798 Suppose we have a multi-instruction sequence that loads constant C
1799 into register R. If R does not get allocated a hard register, and
1800 R is used in an operand that allows both registers and memory
1801 references, reload will consider forcing C into memory and using
1802 one of the instruction's memory alternatives. Returning false
1803 here will force it to use an input reload instead. */
1804 if (GET_CODE (x) == CONST_INT)
1805 return true;
1806
1807 split_const (x, &base, &offset);
1808 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1809 return true;
1810 }
1811
1812 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1813 return true;
1814
1815 return false;
1816 }
1817
1818 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1819 constant pools, but normal-mode code doesn't need to. */
1820
1821 static bool
1822 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1823 rtx x ATTRIBUTE_UNUSED)
1824 {
1825 return !TARGET_MIPS16;
1826 }
1827 \f
1828 /* Return the number of instructions needed to load a symbol of the
1829 given type into a register. If valid in an address, the same number
1830 of instructions are needed for loads and stores. Treat extended
1831 mips16 instructions as two instructions. */
1832
1833 static int
1834 mips_symbol_insns (enum mips_symbol_type type)
1835 {
1836 switch (type)
1837 {
1838 case SYMBOL_GENERAL:
1839 /* In mips16 code, general symbols must be fetched from the
1840 constant pool. */
1841 if (TARGET_MIPS16)
1842 return 0;
1843
1844 /* When using 64-bit symbols, we need 5 preparatory instructions,
1845 such as:
1846
1847 lui $at,%highest(symbol)
1848 daddiu $at,$at,%higher(symbol)
1849 dsll $at,$at,16
1850 daddiu $at,$at,%hi(symbol)
1851 dsll $at,$at,16
1852
1853 The final address is then $at + %lo(symbol). With 32-bit
1854 symbols we just need a preparatory lui. */
1855 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1856
1857 case SYMBOL_SMALL_DATA:
1858 case SYMBOL_HALF:
1859 return 1;
1860
1861 case SYMBOL_CONSTANT_POOL:
1862 /* This case is for mips16 only. Assume we'll need an
1863 extended instruction. */
1864 return 2;
1865
1866 case SYMBOL_GOT_PAGE_OFST:
1867 case SYMBOL_GOT_DISP:
1868 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1869 the local/global classification is accurate. See override_options
1870 for details.
1871
1872 The worst cases are:
1873
1874 (1) For local symbols when generating o32 or o64 code. The assembler
1875 will use:
1876
1877 lw $at,%got(symbol)
1878 nop
1879
1880 ...and the final address will be $at + %lo(symbol).
1881
1882 (2) For global symbols when -mxgot. The assembler will use:
1883
1884 lui $at,%got_hi(symbol)
1885 (d)addu $at,$at,$gp
1886
1887 ...and the final address will be $at + %got_lo(symbol). */
1888 return 3;
1889
1890 case SYMBOL_GOTOFF_PAGE:
1891 case SYMBOL_GOTOFF_DISP:
1892 case SYMBOL_GOTOFF_CALL:
1893 case SYMBOL_GOTOFF_LOADGP:
1894 case SYMBOL_64_HIGH:
1895 case SYMBOL_64_MID:
1896 case SYMBOL_64_LOW:
1897 case SYMBOL_TLSGD:
1898 case SYMBOL_TLSLDM:
1899 case SYMBOL_DTPREL:
1900 case SYMBOL_GOTTPREL:
1901 case SYMBOL_TPREL:
1902 /* Check whether the offset is a 16- or 32-bit value. */
1903 return mips_split_p[type] ? 2 : 1;
1904
1905 case SYMBOL_TLS:
1906 /* We don't treat a bare TLS symbol as a constant. */
1907 return 0;
1908 }
1909 gcc_unreachable ();
1910 }
1911
1912 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1913
1914 bool
1915 mips_stack_address_p (rtx x, enum machine_mode mode)
1916 {
1917 struct mips_address_info addr;
1918
1919 return (mips_classify_address (&addr, x, mode, false)
1920 && addr.type == ADDRESS_REG
1921 && addr.reg == stack_pointer_rtx);
1922 }
1923
1924 /* Return true if a value at OFFSET bytes from BASE can be accessed
1925 using an unextended mips16 instruction. MODE is the mode of the
1926 value.
1927
1928 Usually the offset in an unextended instruction is a 5-bit field.
1929 The offset is unsigned and shifted left once for HIs, twice
1930 for SIs, and so on. An exception is SImode accesses off the
1931 stack pointer, which have an 8-bit immediate field. */
1932
1933 static bool
1934 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1935 {
1936 if (TARGET_MIPS16
1937 && GET_CODE (offset) == CONST_INT
1938 && INTVAL (offset) >= 0
1939 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1940 {
1941 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1942 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1943 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1944 }
1945 return false;
1946 }
1947
1948
1949 /* Return the number of instructions needed to load or store a value
1950 of mode MODE at X. Return 0 if X isn't valid for MODE.
1951
1952 For mips16 code, count extended instructions as two instructions. */
1953
1954 int
1955 mips_address_insns (rtx x, enum machine_mode mode)
1956 {
1957 struct mips_address_info addr;
1958 int factor;
1959
1960 if (mode == BLKmode)
1961 /* BLKmode is used for single unaligned loads and stores. */
1962 factor = 1;
1963 else
1964 /* Each word of a multi-word value will be accessed individually. */
1965 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1966
1967 if (mips_classify_address (&addr, x, mode, false))
1968 switch (addr.type)
1969 {
1970 case ADDRESS_REG:
1971 if (TARGET_MIPS16
1972 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1973 return factor * 2;
1974 return factor;
1975
1976 case ADDRESS_LO_SUM:
1977 return (TARGET_MIPS16 ? factor * 2 : factor);
1978
1979 case ADDRESS_CONST_INT:
1980 return factor;
1981
1982 case ADDRESS_SYMBOLIC:
1983 return factor * mips_symbol_insns (addr.symbol_type);
1984 }
1985 return 0;
1986 }
1987
1988
1989 /* Likewise for constant X. */
1990
1991 int
1992 mips_const_insns (rtx x)
1993 {
1994 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1995 enum mips_symbol_type symbol_type;
1996 rtx offset;
1997
1998 switch (GET_CODE (x))
1999 {
2000 case HIGH:
2001 if (TARGET_MIPS16
2002 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
2003 || !mips_split_p[symbol_type])
2004 return 0;
2005
2006 return 1;
2007
2008 case CONST_INT:
2009 if (TARGET_MIPS16)
2010 /* Unsigned 8-bit constants can be loaded using an unextended
2011 LI instruction. Unsigned 16-bit constants can be loaded
2012 using an extended LI. Negative constants must be loaded
2013 using LI and then negated. */
2014 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
2015 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2016 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
2017 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2018 : 0);
2019
2020 return mips_build_integer (codes, INTVAL (x));
2021
2022 case CONST_DOUBLE:
2023 case CONST_VECTOR:
2024 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
2025
2026 case CONST:
2027 if (CONST_GP_P (x))
2028 return 1;
2029
2030 /* See if we can refer to X directly. */
2031 if (mips_symbolic_constant_p (x, &symbol_type))
2032 return mips_symbol_insns (symbol_type);
2033
2034 /* Otherwise try splitting the constant into a base and offset.
2035 16-bit offsets can be added using an extra addiu. Larger offsets
2036 must be calculated separately and then added to the base. */
2037 split_const (x, &x, &offset);
2038 if (offset != 0)
2039 {
2040 int n = mips_const_insns (x);
2041 if (n != 0)
2042 {
2043 if (SMALL_INT (offset))
2044 return n + 1;
2045 else
2046 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2047 }
2048 }
2049 return 0;
2050
2051 case SYMBOL_REF:
2052 case LABEL_REF:
2053 return mips_symbol_insns (mips_classify_symbol (x));
2054
2055 default:
2056 return 0;
2057 }
2058 }
2059
2060
2061 /* Return the number of instructions needed for memory reference X.
2062 Count extended mips16 instructions as two instructions. */
2063
2064 int
2065 mips_fetch_insns (rtx x)
2066 {
2067 gcc_assert (MEM_P (x));
2068 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
2069 }
2070
2071
2072 /* Return the number of instructions needed for an integer division. */
2073
2074 int
2075 mips_idiv_insns (void)
2076 {
2077 int count;
2078
2079 count = 1;
2080 if (TARGET_CHECK_ZERO_DIV)
2081 {
2082 if (GENERATE_DIVIDE_TRAPS)
2083 count++;
2084 else
2085 count += 2;
2086 }
2087
2088 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2089 count++;
2090 return count;
2091 }
2092 \f
2093 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
2094 returns a nonzero value if X is a legitimate address for a memory
2095 operand of the indicated MODE. STRICT is nonzero if this function
2096 is called during reload. */
2097
2098 bool
2099 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
2100 {
2101 struct mips_address_info addr;
2102
2103 return mips_classify_address (&addr, x, mode, strict);
2104 }
2105
2106
2107 /* Copy VALUE to a register and return that register. If new psuedos
2108 are allowed, copy it into a new register, otherwise use DEST. */
2109
2110 static rtx
2111 mips_force_temporary (rtx dest, rtx value)
2112 {
2113 if (can_create_pseudo_p ())
2114 return force_reg (Pmode, value);
2115 else
2116 {
2117 emit_move_insn (copy_rtx (dest), value);
2118 return dest;
2119 }
2120 }
2121
2122
2123 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
2124 and is used to load the high part into a register. */
2125
2126 rtx
2127 mips_split_symbol (rtx temp, rtx addr)
2128 {
2129 rtx high;
2130
2131 if (!TARGET_MIPS16)
2132 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
2133 else if (!can_create_pseudo_p ())
2134 {
2135 emit_insn (gen_load_const_gp (copy_rtx (temp)));
2136 high = temp;
2137 }
2138 else
2139 high = mips16_gp_pseudo_reg ();
2140 return gen_rtx_LO_SUM (Pmode, high, addr);
2141 }
2142
2143
2144 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2145 type SYMBOL_TYPE. */
2146
2147 rtx
2148 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2149 {
2150 rtx base, offset;
2151
2152 split_const (address, &base, &offset);
2153 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2154 UNSPEC_ADDRESS_FIRST + symbol_type);
2155 if (offset != const0_rtx)
2156 base = gen_rtx_PLUS (Pmode, base, offset);
2157 return gen_rtx_CONST (Pmode, base);
2158 }
2159
2160
2161 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2162 high part to BASE and return the result. Just return BASE otherwise.
2163 TEMP is available as a temporary register if needed.
2164
2165 The returned expression can be used as the first operand to a LO_SUM. */
2166
2167 static rtx
2168 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2169 enum mips_symbol_type symbol_type)
2170 {
2171 if (mips_split_p[symbol_type])
2172 {
2173 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2174 addr = mips_force_temporary (temp, addr);
2175 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2176 }
2177 return base;
2178 }
2179
2180
2181 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2182 mips_force_temporary; it is only needed when OFFSET is not a
2183 SMALL_OPERAND. */
2184
2185 static rtx
2186 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2187 {
2188 if (!SMALL_OPERAND (offset))
2189 {
2190 rtx high;
2191 if (TARGET_MIPS16)
2192 {
2193 /* Load the full offset into a register so that we can use
2194 an unextended instruction for the address itself. */
2195 high = GEN_INT (offset);
2196 offset = 0;
2197 }
2198 else
2199 {
2200 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2201 high = GEN_INT (CONST_HIGH_PART (offset));
2202 offset = CONST_LOW_PART (offset);
2203 }
2204 high = mips_force_temporary (temp, high);
2205 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2206 }
2207 return plus_constant (reg, offset);
2208 }
2209
2210 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2211 referencing, and TYPE is the symbol type to use (either global
2212 dynamic or local dynamic). V0 is an RTX for the return value
2213 location. The entire insn sequence is returned. */
2214
2215 static GTY(()) rtx mips_tls_symbol;
2216
2217 static rtx
2218 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2219 {
2220 rtx insn, loc, tga, a0;
2221
2222 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2223
2224 if (!mips_tls_symbol)
2225 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2226
2227 loc = mips_unspec_address (sym, type);
2228
2229 start_sequence ();
2230
2231 emit_insn (gen_rtx_SET (Pmode, a0,
2232 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2233 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2234 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2235 CONST_OR_PURE_CALL_P (insn) = 1;
2236 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2237 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2238 insn = get_insns ();
2239
2240 end_sequence ();
2241
2242 return insn;
2243 }
2244
2245 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2246 return value will be a valid address and move_operand (either a REG
2247 or a LO_SUM). */
2248
2249 static rtx
2250 mips_legitimize_tls_address (rtx loc)
2251 {
2252 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2253 enum tls_model model;
2254
2255 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2256 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2257
2258 model = SYMBOL_REF_TLS_MODEL (loc);
2259 /* Only TARGET_ABICALLS code can have more than one module; other
2260 code must be be static and should not use a GOT. All TLS models
2261 reduce to local exec in this situation. */
2262 if (!TARGET_ABICALLS)
2263 model = TLS_MODEL_LOCAL_EXEC;
2264
2265 switch (model)
2266 {
2267 case TLS_MODEL_GLOBAL_DYNAMIC:
2268 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2269 dest = gen_reg_rtx (Pmode);
2270 emit_libcall_block (insn, dest, v0, loc);
2271 break;
2272
2273 case TLS_MODEL_LOCAL_DYNAMIC:
2274 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2275 tmp1 = gen_reg_rtx (Pmode);
2276
2277 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2278 share the LDM result with other LD model accesses. */
2279 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2280 UNSPEC_TLS_LDM);
2281 emit_libcall_block (insn, tmp1, v0, eqv);
2282
2283 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2284 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2285 mips_unspec_address (loc, SYMBOL_DTPREL));
2286 break;
2287
2288 case TLS_MODEL_INITIAL_EXEC:
2289 tmp1 = gen_reg_rtx (Pmode);
2290 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2291 if (Pmode == DImode)
2292 {
2293 emit_insn (gen_tls_get_tp_di (v1));
2294 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2295 }
2296 else
2297 {
2298 emit_insn (gen_tls_get_tp_si (v1));
2299 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2300 }
2301 dest = gen_reg_rtx (Pmode);
2302 emit_insn (gen_add3_insn (dest, tmp1, v1));
2303 break;
2304
2305 case TLS_MODEL_LOCAL_EXEC:
2306 if (Pmode == DImode)
2307 emit_insn (gen_tls_get_tp_di (v1));
2308 else
2309 emit_insn (gen_tls_get_tp_si (v1));
2310
2311 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2312 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2313 mips_unspec_address (loc, SYMBOL_TPREL));
2314 break;
2315
2316 default:
2317 gcc_unreachable ();
2318 }
2319
2320 return dest;
2321 }
2322
2323 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2324 be legitimized in a way that the generic machinery might not expect,
2325 put the new address in *XLOC and return true. MODE is the mode of
2326 the memory being accessed. */
2327
2328 bool
2329 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2330 {
2331 enum mips_symbol_type symbol_type;
2332
2333 if (mips_tls_operand_p (*xloc))
2334 {
2335 *xloc = mips_legitimize_tls_address (*xloc);
2336 return true;
2337 }
2338
2339 /* See if the address can split into a high part and a LO_SUM. */
2340 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2341 && mips_symbolic_address_p (symbol_type, mode)
2342 && mips_split_p[symbol_type])
2343 {
2344 *xloc = mips_split_symbol (0, *xloc);
2345 return true;
2346 }
2347
2348 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2349 {
2350 /* Handle REG + CONSTANT using mips_add_offset. */
2351 rtx reg;
2352
2353 reg = XEXP (*xloc, 0);
2354 if (!mips_valid_base_register_p (reg, mode, 0))
2355 reg = copy_to_mode_reg (Pmode, reg);
2356 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2357 return true;
2358 }
2359
2360 return false;
2361 }
2362
2363
2364 /* Subroutine of mips_build_integer (with the same interface).
2365 Assume that the final action in the sequence should be a left shift. */
2366
2367 static unsigned int
2368 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2369 {
2370 unsigned int i, shift;
2371
2372 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2373 since signed numbers are easier to load than unsigned ones. */
2374 shift = 0;
2375 while ((value & 1) == 0)
2376 value /= 2, shift++;
2377
2378 i = mips_build_integer (codes, value);
2379 codes[i].code = ASHIFT;
2380 codes[i].value = shift;
2381 return i + 1;
2382 }
2383
2384
2385 /* As for mips_build_shift, but assume that the final action will be
2386 an IOR or PLUS operation. */
2387
2388 static unsigned int
2389 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2390 {
2391 unsigned HOST_WIDE_INT high;
2392 unsigned int i;
2393
2394 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2395 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2396 {
2397 /* The constant is too complex to load with a simple lui/ori pair
2398 so our goal is to clear as many trailing zeros as possible.
2399 In this case, we know bit 16 is set and that the low 16 bits
2400 form a negative number. If we subtract that number from VALUE,
2401 we will clear at least the lowest 17 bits, maybe more. */
2402 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2403 codes[i].code = PLUS;
2404 codes[i].value = CONST_LOW_PART (value);
2405 }
2406 else
2407 {
2408 i = mips_build_integer (codes, high);
2409 codes[i].code = IOR;
2410 codes[i].value = value & 0xffff;
2411 }
2412 return i + 1;
2413 }
2414
2415
2416 /* Fill CODES with a sequence of rtl operations to load VALUE.
2417 Return the number of operations needed. */
2418
2419 static unsigned int
2420 mips_build_integer (struct mips_integer_op *codes,
2421 unsigned HOST_WIDE_INT value)
2422 {
2423 if (SMALL_OPERAND (value)
2424 || SMALL_OPERAND_UNSIGNED (value)
2425 || LUI_OPERAND (value))
2426 {
2427 /* The value can be loaded with a single instruction. */
2428 codes[0].code = UNKNOWN;
2429 codes[0].value = value;
2430 return 1;
2431 }
2432 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2433 {
2434 /* Either the constant is a simple LUI/ORI combination or its
2435 lowest bit is set. We don't want to shift in this case. */
2436 return mips_build_lower (codes, value);
2437 }
2438 else if ((value & 0xffff) == 0)
2439 {
2440 /* The constant will need at least three actions. The lowest
2441 16 bits are clear, so the final action will be a shift. */
2442 return mips_build_shift (codes, value);
2443 }
2444 else
2445 {
2446 /* The final action could be a shift, add or inclusive OR.
2447 Rather than use a complex condition to select the best
2448 approach, try both mips_build_shift and mips_build_lower
2449 and pick the one that gives the shortest sequence.
2450 Note that this case is only used once per constant. */
2451 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2452 unsigned int cost, alt_cost;
2453
2454 cost = mips_build_shift (codes, value);
2455 alt_cost = mips_build_lower (alt_codes, value);
2456 if (alt_cost < cost)
2457 {
2458 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2459 cost = alt_cost;
2460 }
2461 return cost;
2462 }
2463 }
2464
2465
2466 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2467
2468 void
2469 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2470 {
2471 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2472 enum machine_mode mode;
2473 unsigned int i, cost;
2474 rtx x;
2475
2476 mode = GET_MODE (dest);
2477 cost = mips_build_integer (codes, value);
2478
2479 /* Apply each binary operation to X. Invariant: X is a legitimate
2480 source operand for a SET pattern. */
2481 x = GEN_INT (codes[0].value);
2482 for (i = 1; i < cost; i++)
2483 {
2484 if (!can_create_pseudo_p ())
2485 {
2486 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2487 x = temp;
2488 }
2489 else
2490 x = force_reg (mode, x);
2491 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2492 }
2493
2494 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2495 }
2496
2497
2498 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2499 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2500 move_operand. */
2501
2502 static void
2503 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2504 {
2505 rtx base, offset;
2506
2507 /* Split moves of big integers into smaller pieces. */
2508 if (splittable_const_int_operand (src, mode))
2509 {
2510 mips_move_integer (dest, dest, INTVAL (src));
2511 return;
2512 }
2513
2514 /* Split moves of symbolic constants into high/low pairs. */
2515 if (splittable_symbolic_operand (src, mode))
2516 {
2517 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2518 return;
2519 }
2520
2521 if (mips_tls_operand_p (src))
2522 {
2523 emit_move_insn (dest, mips_legitimize_tls_address (src));
2524 return;
2525 }
2526
2527 /* If we have (const (plus symbol offset)), load the symbol first
2528 and then add in the offset. This is usually better than forcing
2529 the constant into memory, at least in non-mips16 code. */
2530 split_const (src, &base, &offset);
2531 if (!TARGET_MIPS16
2532 && offset != const0_rtx
2533 && (can_create_pseudo_p () || SMALL_INT (offset)))
2534 {
2535 base = mips_force_temporary (dest, base);
2536 emit_move_insn (dest, mips_add_offset (0, base, INTVAL (offset)));
2537 return;
2538 }
2539
2540 src = force_const_mem (mode, src);
2541
2542 /* When using explicit relocs, constant pool references are sometimes
2543 not legitimate addresses. */
2544 if (!memory_operand (src, VOIDmode))
2545 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2546 emit_move_insn (dest, src);
2547 }
2548
2549
2550 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2551 sequence that is valid. */
2552
2553 bool
2554 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2555 {
2556 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2557 {
2558 emit_move_insn (dest, force_reg (mode, src));
2559 return true;
2560 }
2561
2562 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2563 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2564 && REG_P (src) && MD_REG_P (REGNO (src))
2565 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2566 {
2567 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2568 if (GET_MODE_SIZE (mode) <= 4)
2569 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2570 gen_rtx_REG (SImode, REGNO (src)),
2571 gen_rtx_REG (SImode, other_regno)));
2572 else
2573 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2574 gen_rtx_REG (DImode, REGNO (src)),
2575 gen_rtx_REG (DImode, other_regno)));
2576 return true;
2577 }
2578
2579 /* We need to deal with constants that would be legitimate
2580 immediate_operands but not legitimate move_operands. */
2581 if (CONSTANT_P (src) && !move_operand (src, mode))
2582 {
2583 mips_legitimize_const_move (mode, dest, src);
2584 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2585 return true;
2586 }
2587 return false;
2588 }
2589 \f
2590 /* We need a lot of little routines to check constant values on the
2591 mips16. These are used to figure out how long the instruction will
2592 be. It would be much better to do this using constraints, but
2593 there aren't nearly enough letters available. */
2594
2595 static int
2596 m16_check_op (rtx op, int low, int high, int mask)
2597 {
2598 return (GET_CODE (op) == CONST_INT
2599 && INTVAL (op) >= low
2600 && INTVAL (op) <= high
2601 && (INTVAL (op) & mask) == 0);
2602 }
2603
2604 int
2605 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2606 {
2607 return m16_check_op (op, 0x1, 0x8, 0);
2608 }
2609
2610 int
2611 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2612 {
2613 return m16_check_op (op, - 0x8, 0x7, 0);
2614 }
2615
2616 int
2617 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2618 {
2619 return m16_check_op (op, - 0x7, 0x8, 0);
2620 }
2621
2622 int
2623 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2624 {
2625 return m16_check_op (op, - 0x10, 0xf, 0);
2626 }
2627
2628 int
2629 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2630 {
2631 return m16_check_op (op, - 0xf, 0x10, 0);
2632 }
2633
2634 int
2635 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2636 {
2637 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2638 }
2639
2640 int
2641 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2642 {
2643 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2644 }
2645
2646 int
2647 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2648 {
2649 return m16_check_op (op, - 0x80, 0x7f, 0);
2650 }
2651
2652 int
2653 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2654 {
2655 return m16_check_op (op, - 0x7f, 0x80, 0);
2656 }
2657
2658 int
2659 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2660 {
2661 return m16_check_op (op, 0x0, 0xff, 0);
2662 }
2663
2664 int
2665 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2666 {
2667 return m16_check_op (op, - 0xff, 0x0, 0);
2668 }
2669
2670 int
2671 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2672 {
2673 return m16_check_op (op, - 0x1, 0xfe, 0);
2674 }
2675
2676 int
2677 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2678 {
2679 return m16_check_op (op, 0x0, 0xff << 2, 3);
2680 }
2681
2682 int
2683 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2684 {
2685 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2686 }
2687
2688 int
2689 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2690 {
2691 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2692 }
2693
2694 int
2695 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2696 {
2697 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2698 }
2699 \f
2700 /* Return true if ADDR matches the pattern for the lwxs load scaled indexed
2701 address instruction. */
2702
2703 static bool
2704 mips_lwxs_address_p (rtx addr)
2705 {
2706 if (ISA_HAS_LWXS
2707 && GET_CODE (addr) == PLUS
2708 && REG_P (XEXP (addr, 1)))
2709 {
2710 rtx offset = XEXP (addr, 0);
2711 if (GET_CODE (offset) == MULT
2712 && REG_P (XEXP (offset, 0))
2713 && GET_CODE (XEXP (offset, 1)) == CONST_INT
2714 && INTVAL (XEXP (offset, 1)) == 4)
2715 return true;
2716 }
2717 return false;
2718 }
2719
2720 static bool
2721 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2722 {
2723 enum machine_mode mode = GET_MODE (x);
2724 bool float_mode_p = FLOAT_MODE_P (mode);
2725
2726 switch (code)
2727 {
2728 case CONST_INT:
2729 if (TARGET_MIPS16)
2730 {
2731 /* A number between 1 and 8 inclusive is efficient for a shift.
2732 Otherwise, we will need an extended instruction. */
2733 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2734 || (outer_code) == LSHIFTRT)
2735 {
2736 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2737 *total = 0;
2738 else
2739 *total = COSTS_N_INSNS (1);
2740 return true;
2741 }
2742
2743 /* We can use cmpi for an xor with an unsigned 16-bit value. */
2744 if ((outer_code) == XOR
2745 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2746 {
2747 *total = 0;
2748 return true;
2749 }
2750
2751 /* We may be able to use slt or sltu for a comparison with a
2752 signed 16-bit value. (The boundary conditions aren't quite
2753 right, but this is just a heuristic anyhow.) */
2754 if (((outer_code) == LT || (outer_code) == LE
2755 || (outer_code) == GE || (outer_code) == GT
2756 || (outer_code) == LTU || (outer_code) == LEU
2757 || (outer_code) == GEU || (outer_code) == GTU)
2758 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2759 {
2760 *total = 0;
2761 return true;
2762 }
2763
2764 /* Equality comparisons with 0 are cheap. */
2765 if (((outer_code) == EQ || (outer_code) == NE)
2766 && INTVAL (x) == 0)
2767 {
2768 *total = 0;
2769 return true;
2770 }
2771
2772 /* Constants in the range 0...255 can be loaded with an unextended
2773 instruction. They are therefore as cheap as a register move.
2774
2775 Given the choice between "li R1,0...255" and "move R1,R2"
2776 (where R2 is a known constant), it is usually better to use "li",
2777 since we do not want to unnecessarily extend the lifetime
2778 of R2. */
2779 if (outer_code == SET
2780 && INTVAL (x) >= 0
2781 && INTVAL (x) < 256)
2782 {
2783 *total = 0;
2784 return true;
2785 }
2786 }
2787 else
2788 {
2789 /* These can be used anywhere. */
2790 *total = 0;
2791 return true;
2792 }
2793
2794 /* Otherwise fall through to the handling below because
2795 we'll need to construct the constant. */
2796
2797 case CONST:
2798 case SYMBOL_REF:
2799 case LABEL_REF:
2800 case CONST_DOUBLE:
2801 if (LEGITIMATE_CONSTANT_P (x))
2802 {
2803 *total = COSTS_N_INSNS (1);
2804 return true;
2805 }
2806 else
2807 {
2808 /* The value will need to be fetched from the constant pool. */
2809 *total = CONSTANT_POOL_COST;
2810 return true;
2811 }
2812
2813 case MEM:
2814 {
2815 /* If the address is legitimate, return the number of
2816 instructions it needs. */
2817 rtx addr = XEXP (x, 0);
2818 int n = mips_address_insns (addr, GET_MODE (x));
2819 if (n > 0)
2820 {
2821 *total = COSTS_N_INSNS (n + 1);
2822 return true;
2823 }
2824 /* Check for scaled indexed address. */
2825 if (mips_lwxs_address_p (addr))
2826 {
2827 *total = COSTS_N_INSNS (2);
2828 return true;
2829 }
2830 /* Otherwise use the default handling. */
2831 return false;
2832 }
2833
2834 case FFS:
2835 *total = COSTS_N_INSNS (6);
2836 return true;
2837
2838 case NOT:
2839 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2840 return true;
2841
2842 case AND:
2843 case IOR:
2844 case XOR:
2845 if (mode == DImode && !TARGET_64BIT)
2846 {
2847 *total = COSTS_N_INSNS (2);
2848 return true;
2849 }
2850 return false;
2851
2852 case ASHIFT:
2853 case ASHIFTRT:
2854 case LSHIFTRT:
2855 if (mode == DImode && !TARGET_64BIT)
2856 {
2857 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2858 ? 4 : 12);
2859 return true;
2860 }
2861 return false;
2862
2863 case ABS:
2864 if (float_mode_p)
2865 *total = COSTS_N_INSNS (1);
2866 else
2867 *total = COSTS_N_INSNS (4);
2868 return true;
2869
2870 case LO_SUM:
2871 *total = COSTS_N_INSNS (1);
2872 return true;
2873
2874 case PLUS:
2875 case MINUS:
2876 if (float_mode_p)
2877 {
2878 *total = mips_cost->fp_add;
2879 return true;
2880 }
2881
2882 else if (mode == DImode && !TARGET_64BIT)
2883 {
2884 *total = COSTS_N_INSNS (4);
2885 return true;
2886 }
2887 return false;
2888
2889 case NEG:
2890 if (mode == DImode && !TARGET_64BIT)
2891 {
2892 *total = COSTS_N_INSNS (4);
2893 return true;
2894 }
2895 return false;
2896
2897 case MULT:
2898 if (mode == SFmode)
2899 *total = mips_cost->fp_mult_sf;
2900
2901 else if (mode == DFmode)
2902 *total = mips_cost->fp_mult_df;
2903
2904 else if (mode == SImode)
2905 *total = mips_cost->int_mult_si;
2906
2907 else
2908 *total = mips_cost->int_mult_di;
2909
2910 return true;
2911
2912 case DIV:
2913 case MOD:
2914 if (float_mode_p)
2915 {
2916 if (mode == SFmode)
2917 *total = mips_cost->fp_div_sf;
2918 else
2919 *total = mips_cost->fp_div_df;
2920
2921 return true;
2922 }
2923 /* Fall through. */
2924
2925 case UDIV:
2926 case UMOD:
2927 if (mode == DImode)
2928 *total = mips_cost->int_div_di;
2929 else
2930 *total = mips_cost->int_div_si;
2931
2932 return true;
2933
2934 case SIGN_EXTEND:
2935 /* A sign extend from SImode to DImode in 64-bit mode is often
2936 zero instructions, because the result can often be used
2937 directly by another instruction; we'll call it one. */
2938 if (TARGET_64BIT && mode == DImode
2939 && GET_MODE (XEXP (x, 0)) == SImode)
2940 *total = COSTS_N_INSNS (1);
2941 else
2942 *total = COSTS_N_INSNS (2);
2943 return true;
2944
2945 case ZERO_EXTEND:
2946 if (TARGET_64BIT && mode == DImode
2947 && GET_MODE (XEXP (x, 0)) == SImode)
2948 *total = COSTS_N_INSNS (2);
2949 else
2950 *total = COSTS_N_INSNS (1);
2951 return true;
2952
2953 case FLOAT:
2954 case UNSIGNED_FLOAT:
2955 case FIX:
2956 case FLOAT_EXTEND:
2957 case FLOAT_TRUNCATE:
2958 case SQRT:
2959 *total = mips_cost->fp_add;
2960 return true;
2961
2962 default:
2963 return false;
2964 }
2965 }
2966
2967 /* Provide the costs of an addressing mode that contains ADDR.
2968 If ADDR is not a valid address, its cost is irrelevant. */
2969
2970 static int
2971 mips_address_cost (rtx addr)
2972 {
2973 return mips_address_insns (addr, SImode);
2974 }
2975 \f
2976 /* Return one word of double-word value OP, taking into account the fixed
2977 endianness of certain registers. HIGH_P is true to select the high part,
2978 false to select the low part. */
2979
2980 rtx
2981 mips_subword (rtx op, int high_p)
2982 {
2983 unsigned int byte;
2984 enum machine_mode mode;
2985
2986 mode = GET_MODE (op);
2987 if (mode == VOIDmode)
2988 mode = DImode;
2989
2990 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2991 byte = UNITS_PER_WORD;
2992 else
2993 byte = 0;
2994
2995 if (FP_REG_RTX_P (op))
2996 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2997
2998 if (MEM_P (op))
2999 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3000
3001 return simplify_gen_subreg (word_mode, op, mode, byte);
3002 }
3003
3004
3005 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3006
3007 bool
3008 mips_split_64bit_move_p (rtx dest, rtx src)
3009 {
3010 if (TARGET_64BIT)
3011 return false;
3012
3013 /* FP->FP moves can be done in a single instruction. */
3014 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3015 return false;
3016
3017 /* Check for floating-point loads and stores. They can be done using
3018 ldc1 and sdc1 on MIPS II and above. */
3019 if (mips_isa > 1)
3020 {
3021 if (FP_REG_RTX_P (dest) && MEM_P (src))
3022 return false;
3023 if (FP_REG_RTX_P (src) && MEM_P (dest))
3024 return false;
3025 }
3026 return true;
3027 }
3028
3029
3030 /* Split a 64-bit move from SRC to DEST assuming that
3031 mips_split_64bit_move_p holds.
3032
3033 Moves into and out of FPRs cause some difficulty here. Such moves
3034 will always be DFmode, since paired FPRs are not allowed to store
3035 DImode values. The most natural representation would be two separate
3036 32-bit moves, such as:
3037
3038 (set (reg:SI $f0) (mem:SI ...))
3039 (set (reg:SI $f1) (mem:SI ...))
3040
3041 However, the second insn is invalid because odd-numbered FPRs are
3042 not allowed to store independent values. Use the patterns load_df_low,
3043 load_df_high and store_df_high instead. */
3044
3045 void
3046 mips_split_64bit_move (rtx dest, rtx src)
3047 {
3048 if (FP_REG_RTX_P (dest))
3049 {
3050 /* Loading an FPR from memory or from GPRs. */
3051 if (ISA_HAS_MXHC1)
3052 {
3053 dest = gen_lowpart (DFmode, dest);
3054 emit_insn (gen_load_df_low (dest, mips_subword (src, 0)));
3055 emit_insn (gen_mthc1 (dest, mips_subword (src, 1),
3056 copy_rtx (dest)));
3057 }
3058 else
3059 {
3060 emit_insn (gen_load_df_low (copy_rtx (dest),
3061 mips_subword (src, 0)));
3062 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
3063 copy_rtx (dest)));
3064 }
3065 }
3066 else if (FP_REG_RTX_P (src))
3067 {
3068 /* Storing an FPR into memory or GPRs. */
3069 if (ISA_HAS_MXHC1)
3070 {
3071 src = gen_lowpart (DFmode, src);
3072 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
3073 emit_insn (gen_mfhc1 (mips_subword (dest, 1), src));
3074 }
3075 else
3076 {
3077 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
3078 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
3079 }
3080 }
3081 else
3082 {
3083 /* The operation can be split into two normal moves. Decide in
3084 which order to do them. */
3085 rtx low_dest;
3086
3087 low_dest = mips_subword (dest, 0);
3088 if (REG_P (low_dest)
3089 && reg_overlap_mentioned_p (low_dest, src))
3090 {
3091 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
3092 emit_move_insn (low_dest, mips_subword (src, 0));
3093 }
3094 else
3095 {
3096 emit_move_insn (low_dest, mips_subword (src, 0));
3097 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
3098 }
3099 }
3100 }
3101 \f
3102 /* Return the appropriate instructions to move SRC into DEST. Assume
3103 that SRC is operand 1 and DEST is operand 0. */
3104
3105 const char *
3106 mips_output_move (rtx dest, rtx src)
3107 {
3108 enum rtx_code dest_code, src_code;
3109 bool dbl_p;
3110
3111 dest_code = GET_CODE (dest);
3112 src_code = GET_CODE (src);
3113 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
3114
3115 if (dbl_p && mips_split_64bit_move_p (dest, src))
3116 return "#";
3117
3118 if ((src_code == REG && GP_REG_P (REGNO (src)))
3119 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
3120 {
3121 if (dest_code == REG)
3122 {
3123 if (GP_REG_P (REGNO (dest)))
3124 return "move\t%0,%z1";
3125
3126 if (MD_REG_P (REGNO (dest)))
3127 return "mt%0\t%z1";
3128
3129 if (DSP_ACC_REG_P (REGNO (dest)))
3130 {
3131 static char retval[] = "mt__\t%z1,%q0";
3132 retval[2] = reg_names[REGNO (dest)][4];
3133 retval[3] = reg_names[REGNO (dest)][5];
3134 return retval;
3135 }
3136
3137 if (FP_REG_P (REGNO (dest)))
3138 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
3139
3140 if (ALL_COP_REG_P (REGNO (dest)))
3141 {
3142 static char retval[] = "dmtc_\t%z1,%0";
3143
3144 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3145 return (dbl_p ? retval : retval + 1);
3146 }
3147 }
3148 if (dest_code == MEM)
3149 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
3150 }
3151 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3152 {
3153 if (src_code == REG)
3154 {
3155 if (DSP_ACC_REG_P (REGNO (src)))
3156 {
3157 static char retval[] = "mf__\t%0,%q1";
3158 retval[2] = reg_names[REGNO (src)][4];
3159 retval[3] = reg_names[REGNO (src)][5];
3160 return retval;
3161 }
3162
3163 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3164 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3165
3166 if (FP_REG_P (REGNO (src)))
3167 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
3168
3169 if (ALL_COP_REG_P (REGNO (src)))
3170 {
3171 static char retval[] = "dmfc_\t%0,%1";
3172
3173 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3174 return (dbl_p ? retval : retval + 1);
3175 }
3176 }
3177
3178 if (src_code == MEM)
3179 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
3180
3181 if (src_code == CONST_INT)
3182 {
3183 /* Don't use the X format, because that will give out of
3184 range numbers for 64-bit hosts and 32-bit targets. */
3185 if (!TARGET_MIPS16)
3186 return "li\t%0,%1\t\t\t# %X1";
3187
3188 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
3189 return "li\t%0,%1";
3190
3191 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
3192 return "#";
3193 }
3194
3195 if (src_code == HIGH)
3196 return "lui\t%0,%h1";
3197
3198 if (CONST_GP_P (src))
3199 return "move\t%0,%1";
3200
3201 if (symbolic_operand (src, VOIDmode))
3202 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
3203 }
3204 if (src_code == REG && FP_REG_P (REGNO (src)))
3205 {
3206 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3207 {
3208 if (GET_MODE (dest) == V2SFmode)
3209 return "mov.ps\t%0,%1";
3210 else
3211 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
3212 }
3213
3214 if (dest_code == MEM)
3215 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
3216 }
3217 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3218 {
3219 if (src_code == MEM)
3220 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
3221 }
3222 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3223 {
3224 static char retval[] = "l_c_\t%0,%1";
3225
3226 retval[1] = (dbl_p ? 'd' : 'w');
3227 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3228 return retval;
3229 }
3230 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3231 {
3232 static char retval[] = "s_c_\t%1,%0";
3233
3234 retval[1] = (dbl_p ? 'd' : 'w');
3235 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3236 return retval;
3237 }
3238 gcc_unreachable ();
3239 }
3240 \f
3241 /* Restore $gp from its save slot. Valid only when using o32 or
3242 o64 abicalls. */
3243
3244 void
3245 mips_restore_gp (void)
3246 {
3247 rtx address, slot;
3248
3249 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
3250
3251 address = mips_add_offset (pic_offset_table_rtx,
3252 frame_pointer_needed
3253 ? hard_frame_pointer_rtx
3254 : stack_pointer_rtx,
3255 current_function_outgoing_args_size);
3256 slot = gen_rtx_MEM (Pmode, address);
3257
3258 emit_move_insn (pic_offset_table_rtx, slot);
3259 if (!TARGET_EXPLICIT_RELOCS)
3260 emit_insn (gen_blockage ());
3261 }
3262 \f
3263 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3264
3265 static void
3266 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3267 {
3268 emit_insn (gen_rtx_SET (VOIDmode, target,
3269 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3270 }
3271
3272 /* Return true if CMP1 is a suitable second operand for relational
3273 operator CODE. See also the *sCC patterns in mips.md. */
3274
3275 static bool
3276 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3277 {
3278 switch (code)
3279 {
3280 case GT:
3281 case GTU:
3282 return reg_or_0_operand (cmp1, VOIDmode);
3283
3284 case GE:
3285 case GEU:
3286 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3287
3288 case LT:
3289 case LTU:
3290 return arith_operand (cmp1, VOIDmode);
3291
3292 case LE:
3293 return sle_operand (cmp1, VOIDmode);
3294
3295 case LEU:
3296 return sleu_operand (cmp1, VOIDmode);
3297
3298 default:
3299 gcc_unreachable ();
3300 }
3301 }
3302
3303 /* Canonicalize LE or LEU comparisons into LT comparisons when
3304 possible to avoid extra instructions or inverting the
3305 comparison. */
3306
3307 static bool
3308 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3309 enum machine_mode mode)
3310 {
3311 HOST_WIDE_INT original, plus_one;
3312
3313 if (GET_CODE (*cmp1) != CONST_INT)
3314 return false;
3315
3316 original = INTVAL (*cmp1);
3317 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3318
3319 switch (*code)
3320 {
3321 case LE:
3322 if (original < plus_one)
3323 {
3324 *code = LT;
3325 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3326 return true;
3327 }
3328 break;
3329
3330 case LEU:
3331 if (plus_one != 0)
3332 {
3333 *code = LTU;
3334 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3335 return true;
3336 }
3337 break;
3338
3339 default:
3340 return false;
3341 }
3342
3343 return false;
3344
3345 }
3346
3347 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3348 result in TARGET. CMP0 and TARGET are register_operands that have
3349 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3350 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3351
3352 static void
3353 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3354 rtx target, rtx cmp0, rtx cmp1)
3355 {
3356 /* First see if there is a MIPS instruction that can do this operation
3357 with CMP1 in its current form. If not, try to canonicalize the
3358 comparison to LT. If that fails, try doing the same for the
3359 inverse operation. If that also fails, force CMP1 into a register
3360 and try again. */
3361 if (mips_relational_operand_ok_p (code, cmp1))
3362 mips_emit_binary (code, target, cmp0, cmp1);
3363 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3364 mips_emit_binary (code, target, cmp0, cmp1);
3365 else
3366 {
3367 enum rtx_code inv_code = reverse_condition (code);
3368 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3369 {
3370 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3371 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3372 }
3373 else if (invert_ptr == 0)
3374 {
3375 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3376 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3377 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3378 }
3379 else
3380 {
3381 *invert_ptr = !*invert_ptr;
3382 mips_emit_binary (inv_code, target, cmp0, cmp1);
3383 }
3384 }
3385 }
3386
3387 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3388 The register will have the same mode as CMP0. */
3389
3390 static rtx
3391 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3392 {
3393 if (cmp1 == const0_rtx)
3394 return cmp0;
3395
3396 if (uns_arith_operand (cmp1, VOIDmode))
3397 return expand_binop (GET_MODE (cmp0), xor_optab,
3398 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3399
3400 return expand_binop (GET_MODE (cmp0), sub_optab,
3401 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3402 }
3403
3404 /* Convert *CODE into a code that can be used in a floating-point
3405 scc instruction (c.<cond>.<fmt>). Return true if the values of
3406 the condition code registers will be inverted, with 0 indicating
3407 that the condition holds. */
3408
3409 static bool
3410 mips_reverse_fp_cond_p (enum rtx_code *code)
3411 {
3412 switch (*code)
3413 {
3414 case NE:
3415 case LTGT:
3416 case ORDERED:
3417 *code = reverse_condition_maybe_unordered (*code);
3418 return true;
3419
3420 default:
3421 return false;
3422 }
3423 }
3424
3425 /* Convert a comparison into something that can be used in a branch or
3426 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3427 being compared and *CODE is the code used to compare them.
3428
3429 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3430 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3431 otherwise any standard branch condition can be used. The standard branch
3432 conditions are:
3433
3434 - EQ/NE between two registers.
3435 - any comparison between a register and zero. */
3436
3437 static void
3438 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3439 {
3440 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3441 {
3442 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3443 {
3444 *op0 = cmp_operands[0];
3445 *op1 = cmp_operands[1];
3446 }
3447 else if (*code == EQ || *code == NE)
3448 {
3449 if (need_eq_ne_p)
3450 {
3451 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3452 *op1 = const0_rtx;
3453 }
3454 else
3455 {
3456 *op0 = cmp_operands[0];
3457 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3458 }
3459 }
3460 else
3461 {
3462 /* The comparison needs a separate scc instruction. Store the
3463 result of the scc in *OP0 and compare it against zero. */
3464 bool invert = false;
3465 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3466 *op1 = const0_rtx;
3467 mips_emit_int_relational (*code, &invert, *op0,
3468 cmp_operands[0], cmp_operands[1]);
3469 *code = (invert ? EQ : NE);
3470 }
3471 }
3472 else
3473 {
3474 enum rtx_code cmp_code;
3475
3476 /* Floating-point tests use a separate c.cond.fmt comparison to
3477 set a condition code register. The branch or conditional move
3478 will then compare that register against zero.
3479
3480 Set CMP_CODE to the code of the comparison instruction and
3481 *CODE to the code that the branch or move should use. */
3482 cmp_code = *code;
3483 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3484 *op0 = (ISA_HAS_8CC
3485 ? gen_reg_rtx (CCmode)
3486 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3487 *op1 = const0_rtx;
3488 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3489 }
3490 }
3491 \f
3492 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3493 Store the result in TARGET and return true if successful.
3494
3495 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3496
3497 bool
3498 mips_emit_scc (enum rtx_code code, rtx target)
3499 {
3500 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3501 return false;
3502
3503 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3504 if (code == EQ || code == NE)
3505 {
3506 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3507 mips_emit_binary (code, target, zie, const0_rtx);
3508 }
3509 else
3510 mips_emit_int_relational (code, 0, target,
3511 cmp_operands[0], cmp_operands[1]);
3512 return true;
3513 }
3514
3515 /* Emit the common code for doing conditional branches.
3516 operand[0] is the label to jump to.
3517 The comparison operands are saved away by cmp{si,di,sf,df}. */
3518
3519 void
3520 gen_conditional_branch (rtx *operands, enum rtx_code code)
3521 {
3522 rtx op0, op1, condition;
3523
3524 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3525 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3526 emit_jump_insn (gen_condjump (condition, operands[0]));
3527 }
3528
3529 /* Implement:
3530
3531 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3532 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3533
3534 void
3535 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3536 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3537 {
3538 rtx cmp_result;
3539 bool reversed_p;
3540
3541 reversed_p = mips_reverse_fp_cond_p (&cond);
3542 cmp_result = gen_reg_rtx (CCV2mode);
3543 emit_insn (gen_scc_ps (cmp_result,
3544 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3545 if (reversed_p)
3546 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3547 cmp_result));
3548 else
3549 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3550 cmp_result));
3551 }
3552
3553 /* Emit the common code for conditional moves. OPERANDS is the array
3554 of operands passed to the conditional move define_expand. */
3555
3556 void
3557 gen_conditional_move (rtx *operands)
3558 {
3559 enum rtx_code code;
3560 rtx op0, op1;
3561
3562 code = GET_CODE (operands[1]);
3563 mips_emit_compare (&code, &op0, &op1, true);
3564 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3565 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3566 gen_rtx_fmt_ee (code,
3567 GET_MODE (op0),
3568 op0, op1),
3569 operands[2], operands[3])));
3570 }
3571
3572 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3573 the conditional_trap expander. */
3574
3575 void
3576 mips_gen_conditional_trap (rtx *operands)
3577 {
3578 rtx op0, op1;
3579 enum rtx_code cmp_code = GET_CODE (operands[0]);
3580 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3581
3582 /* MIPS conditional trap machine instructions don't have GT or LE
3583 flavors, so we must invert the comparison and convert to LT and
3584 GE, respectively. */
3585 switch (cmp_code)
3586 {
3587 case GT: cmp_code = LT; break;
3588 case LE: cmp_code = GE; break;
3589 case GTU: cmp_code = LTU; break;
3590 case LEU: cmp_code = GEU; break;
3591 default: break;
3592 }
3593 if (cmp_code == GET_CODE (operands[0]))
3594 {
3595 op0 = cmp_operands[0];
3596 op1 = cmp_operands[1];
3597 }
3598 else
3599 {
3600 op0 = cmp_operands[1];
3601 op1 = cmp_operands[0];
3602 }
3603 op0 = force_reg (mode, op0);
3604 if (!arith_operand (op1, mode))
3605 op1 = force_reg (mode, op1);
3606
3607 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3608 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3609 operands[1]));
3610 }
3611 \f
3612 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
3613
3614 static bool
3615 mips_ok_for_lazy_binding_p (rtx x)
3616 {
3617 return (TARGET_USE_GOT
3618 && GET_CODE (x) == SYMBOL_REF
3619 && !mips_symbol_binds_local_p (x));
3620 }
3621
3622 /* Load function address ADDR into register DEST. SIBCALL_P is true
3623 if the address is needed for a sibling call. */
3624
3625 static void
3626 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3627 {
3628 /* If we're generating PIC, and this call is to a global function,
3629 try to allow its address to be resolved lazily. This isn't
3630 possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
3631 to the stub would be our caller's gp, not ours. */
3632 if (TARGET_EXPLICIT_RELOCS
3633 && !(sibcall_p && TARGET_CALL_SAVED_GP)
3634 && mips_ok_for_lazy_binding_p (addr))
3635 {
3636 rtx high, lo_sum_symbol;
3637
3638 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3639 addr, SYMBOL_GOTOFF_CALL);
3640 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3641 if (Pmode == SImode)
3642 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3643 else
3644 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3645 }
3646 else
3647 emit_move_insn (dest, addr);
3648 }
3649
3650
3651 /* Expand a call or call_value instruction. RESULT is where the
3652 result will go (null for calls), ADDR is the address of the
3653 function, ARGS_SIZE is the size of the arguments and AUX is
3654 the value passed to us by mips_function_arg. SIBCALL_P is true
3655 if we are expanding a sibling call, false if we're expanding
3656 a normal call. */
3657
3658 void
3659 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3660 {
3661 rtx orig_addr, pattern, insn;
3662
3663 orig_addr = addr;
3664 if (!call_insn_operand (addr, VOIDmode))
3665 {
3666 addr = gen_reg_rtx (Pmode);
3667 mips_load_call_address (addr, orig_addr, sibcall_p);
3668 }
3669
3670 if (mips16_hard_float
3671 && build_mips16_call_stub (result, addr, args_size,
3672 aux == 0 ? 0 : (int) GET_MODE (aux)))
3673 return;
3674
3675 if (result == 0)
3676 pattern = (sibcall_p
3677 ? gen_sibcall_internal (addr, args_size)
3678 : gen_call_internal (addr, args_size));
3679 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3680 {
3681 rtx reg1, reg2;
3682
3683 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3684 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3685 pattern =
3686 (sibcall_p
3687 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3688 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3689 }
3690 else
3691 pattern = (sibcall_p
3692 ? gen_sibcall_value_internal (result, addr, args_size)
3693 : gen_call_value_internal (result, addr, args_size));
3694
3695 insn = emit_call_insn (pattern);
3696
3697 /* Lazy-binding stubs require $gp to be valid on entry. */
3698 if (mips_ok_for_lazy_binding_p (orig_addr))
3699 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3700 }
3701
3702
3703 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3704
3705 static bool
3706 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3707 tree exp ATTRIBUTE_UNUSED)
3708 {
3709 return TARGET_SIBCALLS;
3710 }
3711 \f
3712 /* Emit code to move general operand SRC into condition-code
3713 register DEST. SCRATCH is a scratch TFmode float register.
3714 The sequence is:
3715
3716 FP1 = SRC
3717 FP2 = 0.0f
3718 DEST = FP2 < FP1
3719
3720 where FP1 and FP2 are single-precision float registers
3721 taken from SCRATCH. */
3722
3723 void
3724 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3725 {
3726 rtx fp1, fp2;
3727
3728 /* Change the source to SFmode. */
3729 if (MEM_P (src))
3730 src = adjust_address (src, SFmode, 0);
3731 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3732 src = gen_rtx_REG (SFmode, true_regnum (src));
3733
3734 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3735 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
3736
3737 emit_move_insn (copy_rtx (fp1), src);
3738 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3739 emit_insn (gen_slt_sf (dest, fp2, fp1));
3740 }
3741 \f
3742 /* Emit code to change the current function's return address to
3743 ADDRESS. SCRATCH is available as a scratch register, if needed.
3744 ADDRESS and SCRATCH are both word-mode GPRs. */
3745
3746 void
3747 mips_set_return_address (rtx address, rtx scratch)
3748 {
3749 rtx slot_address;
3750
3751 compute_frame_size (get_frame_size ());
3752 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3753 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3754 cfun->machine->frame.gp_sp_offset);
3755
3756 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3757 }
3758 \f
3759 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3760 Assume that the areas do not overlap. */
3761
3762 static void
3763 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3764 {
3765 HOST_WIDE_INT offset, delta;
3766 unsigned HOST_WIDE_INT bits;
3767 int i;
3768 enum machine_mode mode;
3769 rtx *regs;
3770
3771 /* Work out how many bits to move at a time. If both operands have
3772 half-word alignment, it is usually better to move in half words.
3773 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3774 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3775 Otherwise move word-sized chunks. */
3776 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3777 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3778 bits = BITS_PER_WORD / 2;
3779 else
3780 bits = BITS_PER_WORD;
3781
3782 mode = mode_for_size (bits, MODE_INT, 0);
3783 delta = bits / BITS_PER_UNIT;
3784
3785 /* Allocate a buffer for the temporary registers. */
3786 regs = alloca (sizeof (rtx) * length / delta);
3787
3788 /* Load as many BITS-sized chunks as possible. Use a normal load if
3789 the source has enough alignment, otherwise use left/right pairs. */
3790 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3791 {
3792 regs[i] = gen_reg_rtx (mode);
3793 if (MEM_ALIGN (src) >= bits)
3794 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3795 else
3796 {
3797 rtx part = adjust_address (src, BLKmode, offset);
3798 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3799 gcc_unreachable ();
3800 }
3801 }
3802
3803 /* Copy the chunks to the destination. */
3804 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3805 if (MEM_ALIGN (dest) >= bits)
3806 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3807 else
3808 {
3809 rtx part = adjust_address (dest, BLKmode, offset);
3810 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3811 gcc_unreachable ();
3812 }
3813
3814 /* Mop up any left-over bytes. */
3815 if (offset < length)
3816 {
3817 src = adjust_address (src, BLKmode, offset);
3818 dest = adjust_address (dest, BLKmode, offset);
3819 move_by_pieces (dest, src, length - offset,
3820 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3821 }
3822 }
3823 \f
3824 #define MAX_MOVE_REGS 4
3825 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3826
3827
3828 /* Helper function for doing a loop-based block operation on memory
3829 reference MEM. Each iteration of the loop will operate on LENGTH
3830 bytes of MEM.
3831
3832 Create a new base register for use within the loop and point it to
3833 the start of MEM. Create a new memory reference that uses this
3834 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3835
3836 static void
3837 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3838 rtx *loop_reg, rtx *loop_mem)
3839 {
3840 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3841
3842 /* Although the new mem does not refer to a known location,
3843 it does keep up to LENGTH bytes of alignment. */
3844 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3845 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3846 }
3847
3848
3849 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3850 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3851 memory regions do not overlap. */
3852
3853 static void
3854 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3855 {
3856 rtx label, src_reg, dest_reg, final_src;
3857 HOST_WIDE_INT leftover;
3858
3859 leftover = length % MAX_MOVE_BYTES;
3860 length -= leftover;
3861
3862 /* Create registers and memory references for use within the loop. */
3863 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3864 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3865
3866 /* Calculate the value that SRC_REG should have after the last iteration
3867 of the loop. */
3868 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3869 0, 0, OPTAB_WIDEN);
3870
3871 /* Emit the start of the loop. */
3872 label = gen_label_rtx ();
3873 emit_label (label);
3874
3875 /* Emit the loop body. */
3876 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3877
3878 /* Move on to the next block. */
3879 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3880 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3881
3882 /* Emit the loop condition. */
3883 if (Pmode == DImode)
3884 emit_insn (gen_cmpdi (src_reg, final_src));
3885 else
3886 emit_insn (gen_cmpsi (src_reg, final_src));
3887 emit_jump_insn (gen_bne (label));
3888
3889 /* Mop up any left-over bytes. */
3890 if (leftover)
3891 mips_block_move_straight (dest, src, leftover);
3892 }
3893 \f
3894
3895 /* Expand a loop of synci insns for the address range [BEGIN, END). */
3896
3897 void
3898 mips_expand_synci_loop (rtx begin, rtx end)
3899 {
3900 rtx inc, label, cmp, cmp_result;
3901
3902 /* Load INC with the cache line size (rdhwr INC,$1). */
3903 inc = gen_reg_rtx (SImode);
3904 emit_insn (gen_rdhwr (inc, const1_rtx));
3905
3906 /* Loop back to here. */
3907 label = gen_label_rtx ();
3908 emit_label (label);
3909
3910 emit_insn (gen_synci (begin));
3911
3912 cmp = gen_reg_rtx (Pmode);
3913 mips_emit_binary (GTU, cmp, begin, end);
3914
3915 mips_emit_binary (PLUS, begin, begin, inc);
3916
3917 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
3918 emit_jump_insn (gen_condjump (cmp_result, label));
3919 }
3920 \f
3921 /* Expand a movmemsi instruction. */
3922
3923 bool
3924 mips_expand_block_move (rtx dest, rtx src, rtx length)
3925 {
3926 if (GET_CODE (length) == CONST_INT)
3927 {
3928 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3929 {
3930 mips_block_move_straight (dest, src, INTVAL (length));
3931 return true;
3932 }
3933 else if (optimize)
3934 {
3935 mips_block_move_loop (dest, src, INTVAL (length));
3936 return true;
3937 }
3938 }
3939 return false;
3940 }
3941 \f
3942 /* Argument support functions. */
3943
3944 /* Initialize CUMULATIVE_ARGS for a function. */
3945
3946 void
3947 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3948 rtx libname ATTRIBUTE_UNUSED)
3949 {
3950 static CUMULATIVE_ARGS zero_cum;
3951 tree param, next_param;
3952
3953 *cum = zero_cum;
3954 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3955
3956 /* Determine if this function has variable arguments. This is
3957 indicated by the last argument being 'void_type_mode' if there
3958 are no variable arguments. The standard MIPS calling sequence
3959 passes all arguments in the general purpose registers in this case. */
3960
3961 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3962 param != 0; param = next_param)
3963 {
3964 next_param = TREE_CHAIN (param);
3965 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3966 cum->gp_reg_found = 1;
3967 }
3968 }
3969
3970
3971 /* Fill INFO with information about a single argument. CUM is the
3972 cumulative state for earlier arguments. MODE is the mode of this
3973 argument and TYPE is its type (if known). NAMED is true if this
3974 is a named (fixed) argument rather than a variable one. */
3975
3976 static void
3977 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3978 tree type, int named, struct mips_arg_info *info)
3979 {
3980 bool doubleword_aligned_p;
3981 unsigned int num_bytes, num_words, max_regs;
3982
3983 /* Work out the size of the argument. */
3984 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3985 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3986
3987 /* Decide whether it should go in a floating-point register, assuming
3988 one is free. Later code checks for availability.
3989
3990 The checks against UNITS_PER_FPVALUE handle the soft-float and
3991 single-float cases. */
3992 switch (mips_abi)
3993 {
3994 case ABI_EABI:
3995 /* The EABI conventions have traditionally been defined in terms
3996 of TYPE_MODE, regardless of the actual type. */
3997 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3998 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3999 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4000 break;
4001
4002 case ABI_32:
4003 case ABI_O64:
4004 /* Only leading floating-point scalars are passed in
4005 floating-point registers. We also handle vector floats the same
4006 say, which is OK because they are not covered by the standard ABI. */
4007 info->fpr_p = (!cum->gp_reg_found
4008 && cum->arg_number < 2
4009 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
4010 || VECTOR_FLOAT_TYPE_P (type))
4011 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4012 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4013 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4014 break;
4015
4016 case ABI_N32:
4017 case ABI_64:
4018 /* Scalar and complex floating-point types are passed in
4019 floating-point registers. */
4020 info->fpr_p = (named
4021 && (type == 0 || FLOAT_TYPE_P (type))
4022 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4023 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4024 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4025 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4026
4027 /* ??? According to the ABI documentation, the real and imaginary
4028 parts of complex floats should be passed in individual registers.
4029 The real and imaginary parts of stack arguments are supposed
4030 to be contiguous and there should be an extra word of padding
4031 at the end.
4032
4033 This has two problems. First, it makes it impossible to use a
4034 single "void *" va_list type, since register and stack arguments
4035 are passed differently. (At the time of writing, MIPSpro cannot
4036 handle complex float varargs correctly.) Second, it's unclear
4037 what should happen when there is only one register free.
4038
4039 For now, we assume that named complex floats should go into FPRs
4040 if there are two FPRs free, otherwise they should be passed in the
4041 same way as a struct containing two floats. */
4042 if (info->fpr_p
4043 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4044 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4045 {
4046 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4047 info->fpr_p = false;
4048 else
4049 num_words = 2;
4050 }
4051 break;
4052
4053 default:
4054 gcc_unreachable ();
4055 }
4056
4057 /* See whether the argument has doubleword alignment. */
4058 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4059
4060 /* Set REG_OFFSET to the register count we're interested in.
4061 The EABI allocates the floating-point registers separately,
4062 but the other ABIs allocate them like integer registers. */
4063 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4064 ? cum->num_fprs
4065 : cum->num_gprs);
4066
4067 /* Advance to an even register if the argument is doubleword-aligned. */
4068 if (doubleword_aligned_p)
4069 info->reg_offset += info->reg_offset & 1;
4070
4071 /* Work out the offset of a stack argument. */
4072 info->stack_offset = cum->stack_words;
4073 if (doubleword_aligned_p)
4074 info->stack_offset += info->stack_offset & 1;
4075
4076 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4077
4078 /* Partition the argument between registers and stack. */
4079 info->reg_words = MIN (num_words, max_regs);
4080 info->stack_words = num_words - info->reg_words;
4081 }
4082
4083
4084 /* INFO describes an argument that is passed in a single-register value.
4085 Return the register it uses, assuming that FPRs are available if
4086 HARD_FLOAT_P. */
4087
4088 static unsigned int
4089 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4090 {
4091 if (!info->fpr_p || !hard_float_p)
4092 return GP_ARG_FIRST + info->reg_offset;
4093 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4094 /* In o32, the second argument is always passed in $f14
4095 for TARGET_DOUBLE_FLOAT, regardless of whether the
4096 first argument was a word or doubleword. */
4097 return FP_ARG_FIRST + 2;
4098 else
4099 return FP_ARG_FIRST + info->reg_offset;
4100 }
4101
4102 /* Implement FUNCTION_ARG_ADVANCE. */
4103
4104 void
4105 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4106 tree type, int named)
4107 {
4108 struct mips_arg_info info;
4109
4110 mips_arg_info (cum, mode, type, named, &info);
4111
4112 if (!info.fpr_p)
4113 cum->gp_reg_found = true;
4114
4115 /* See the comment above the cumulative args structure in mips.h
4116 for an explanation of what this code does. It assumes the O32
4117 ABI, which passes at most 2 arguments in float registers. */
4118 if (cum->arg_number < 2 && info.fpr_p)
4119 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4120
4121 if (mips_abi != ABI_EABI || !info.fpr_p)
4122 cum->num_gprs = info.reg_offset + info.reg_words;
4123 else if (info.reg_words > 0)
4124 cum->num_fprs += MAX_FPRS_PER_FMT;
4125
4126 if (info.stack_words > 0)
4127 cum->stack_words = info.stack_offset + info.stack_words;
4128
4129 cum->arg_number++;
4130 }
4131
4132 /* Implement FUNCTION_ARG. */
4133
4134 struct rtx_def *
4135 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4136 tree type, int named)
4137 {
4138 struct mips_arg_info info;
4139
4140 /* We will be called with a mode of VOIDmode after the last argument
4141 has been seen. Whatever we return will be passed to the call
4142 insn. If we need a mips16 fp_code, return a REG with the code
4143 stored as the mode. */
4144 if (mode == VOIDmode)
4145 {
4146 if (TARGET_MIPS16 && cum->fp_code != 0)
4147 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4148
4149 else
4150 return 0;
4151 }
4152
4153 mips_arg_info (cum, mode, type, named, &info);
4154
4155 /* Return straight away if the whole argument is passed on the stack. */
4156 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4157 return 0;
4158
4159 if (type != 0
4160 && TREE_CODE (type) == RECORD_TYPE
4161 && TARGET_NEWABI
4162 && TYPE_SIZE_UNIT (type)
4163 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4164 && named)
4165 {
4166 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
4167 structure contains a double in its entirety, then that 64-bit
4168 chunk is passed in a floating point register. */
4169 tree field;
4170
4171 /* First check to see if there is any such field. */
4172 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4173 if (TREE_CODE (field) == FIELD_DECL
4174 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4175 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4176 && host_integerp (bit_position (field), 0)
4177 && int_bit_position (field) % BITS_PER_WORD == 0)
4178 break;
4179
4180 if (field != 0)
4181 {
4182 /* Now handle the special case by returning a PARALLEL
4183 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4184 chunks are passed in registers. */
4185 unsigned int i;
4186 HOST_WIDE_INT bitpos;
4187 rtx ret;
4188
4189 /* assign_parms checks the mode of ENTRY_PARM, so we must
4190 use the actual mode here. */
4191 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4192
4193 bitpos = 0;
4194 field = TYPE_FIELDS (type);
4195 for (i = 0; i < info.reg_words; i++)
4196 {
4197 rtx reg;
4198
4199 for (; field; field = TREE_CHAIN (field))
4200 if (TREE_CODE (field) == FIELD_DECL
4201 && int_bit_position (field) >= bitpos)
4202 break;
4203
4204 if (field
4205 && int_bit_position (field) == bitpos
4206 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4207 && !TARGET_SOFT_FLOAT
4208 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4209 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4210 else
4211 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4212
4213 XVECEXP (ret, 0, i)
4214 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4215 GEN_INT (bitpos / BITS_PER_UNIT));
4216
4217 bitpos += BITS_PER_WORD;
4218 }
4219 return ret;
4220 }
4221 }
4222
4223 /* Handle the n32/n64 conventions for passing complex floating-point
4224 arguments in FPR pairs. The real part goes in the lower register
4225 and the imaginary part goes in the upper register. */
4226 if (TARGET_NEWABI
4227 && info.fpr_p
4228 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4229 {
4230 rtx real, imag;
4231 enum machine_mode inner;
4232 int reg;
4233
4234 inner = GET_MODE_INNER (mode);
4235 reg = FP_ARG_FIRST + info.reg_offset;
4236 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4237 {
4238 /* Real part in registers, imaginary part on stack. */
4239 gcc_assert (info.stack_words == info.reg_words);
4240 return gen_rtx_REG (inner, reg);
4241 }
4242 else
4243 {
4244 gcc_assert (info.stack_words == 0);
4245 real = gen_rtx_EXPR_LIST (VOIDmode,
4246 gen_rtx_REG (inner, reg),
4247 const0_rtx);
4248 imag = gen_rtx_EXPR_LIST (VOIDmode,
4249 gen_rtx_REG (inner,
4250 reg + info.reg_words / 2),
4251 GEN_INT (GET_MODE_SIZE (inner)));
4252 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4253 }
4254 }
4255
4256 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4257 }
4258
4259
4260 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4261
4262 static int
4263 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4264 enum machine_mode mode, tree type, bool named)
4265 {
4266 struct mips_arg_info info;
4267
4268 mips_arg_info (cum, mode, type, named, &info);
4269 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4270 }
4271
4272
4273 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4274 PARM_BOUNDARY bits of alignment, but will be given anything up
4275 to STACK_BOUNDARY bits if the type requires it. */
4276
4277 int
4278 function_arg_boundary (enum machine_mode mode, tree type)
4279 {
4280 unsigned int alignment;
4281
4282 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4283 if (alignment < PARM_BOUNDARY)
4284 alignment = PARM_BOUNDARY;
4285 if (alignment > STACK_BOUNDARY)
4286 alignment = STACK_BOUNDARY;
4287 return alignment;
4288 }
4289
4290 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4291 upward rather than downward. In other words, return true if the
4292 first byte of the stack slot has useful data, false if the last
4293 byte does. */
4294
4295 bool
4296 mips_pad_arg_upward (enum machine_mode mode, tree type)
4297 {
4298 /* On little-endian targets, the first byte of every stack argument
4299 is passed in the first byte of the stack slot. */
4300 if (!BYTES_BIG_ENDIAN)
4301 return true;
4302
4303 /* Otherwise, integral types are padded downward: the last byte of a
4304 stack argument is passed in the last byte of the stack slot. */
4305 if (type != 0
4306 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
4307 : GET_MODE_CLASS (mode) == MODE_INT)
4308 return false;
4309
4310 /* Big-endian o64 pads floating-point arguments downward. */
4311 if (mips_abi == ABI_O64)
4312 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4313 return false;
4314
4315 /* Other types are padded upward for o32, o64, n32 and n64. */
4316 if (mips_abi != ABI_EABI)
4317 return true;
4318
4319 /* Arguments smaller than a stack slot are padded downward. */
4320 if (mode != BLKmode)
4321 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4322 else
4323 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4324 }
4325
4326
4327 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4328 if the least significant byte of the register has useful data. Return
4329 the opposite if the most significant byte does. */
4330
4331 bool
4332 mips_pad_reg_upward (enum machine_mode mode, tree type)
4333 {
4334 /* No shifting is required for floating-point arguments. */
4335 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4336 return !BYTES_BIG_ENDIAN;
4337
4338 /* Otherwise, apply the same padding to register arguments as we do
4339 to stack arguments. */
4340 return mips_pad_arg_upward (mode, type);
4341 }
4342 \f
4343 static void
4344 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4345 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4346 int no_rtl)
4347 {
4348 CUMULATIVE_ARGS local_cum;
4349 int gp_saved, fp_saved;
4350
4351 /* The caller has advanced CUM up to, but not beyond, the last named
4352 argument. Advance a local copy of CUM past the last "real" named
4353 argument, to find out how many registers are left over. */
4354
4355 local_cum = *cum;
4356 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4357
4358 /* Found out how many registers we need to save. */
4359 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4360 fp_saved = (EABI_FLOAT_VARARGS_P
4361 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4362 : 0);
4363
4364 if (!no_rtl)
4365 {
4366 if (gp_saved > 0)
4367 {
4368 rtx ptr, mem;
4369
4370 ptr = plus_constant (virtual_incoming_args_rtx,
4371 REG_PARM_STACK_SPACE (cfun->decl)
4372 - gp_saved * UNITS_PER_WORD);
4373 mem = gen_rtx_MEM (BLKmode, ptr);
4374 set_mem_alias_set (mem, get_varargs_alias_set ());
4375
4376 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4377 mem, gp_saved);
4378 }
4379 if (fp_saved > 0)
4380 {
4381 /* We can't use move_block_from_reg, because it will use
4382 the wrong mode. */
4383 enum machine_mode mode;
4384 int off, i;
4385
4386 /* Set OFF to the offset from virtual_incoming_args_rtx of
4387 the first float register. The FP save area lies below
4388 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4389 off = -gp_saved * UNITS_PER_WORD;
4390 off &= ~(UNITS_PER_FPVALUE - 1);
4391 off -= fp_saved * UNITS_PER_FPREG;
4392
4393 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4394
4395 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4396 i += MAX_FPRS_PER_FMT)
4397 {
4398 rtx ptr, mem;
4399
4400 ptr = plus_constant (virtual_incoming_args_rtx, off);
4401 mem = gen_rtx_MEM (mode, ptr);
4402 set_mem_alias_set (mem, get_varargs_alias_set ());
4403 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4404 off += UNITS_PER_HWFPVALUE;
4405 }
4406 }
4407 }
4408 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4409 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4410 + fp_saved * UNITS_PER_FPREG);
4411 }
4412
4413 /* Create the va_list data type.
4414 We keep 3 pointers, and two offsets.
4415 Two pointers are to the overflow area, which starts at the CFA.
4416 One of these is constant, for addressing into the GPR save area below it.
4417 The other is advanced up the stack through the overflow region.
4418 The third pointer is to the GPR save area. Since the FPR save area
4419 is just below it, we can address FPR slots off this pointer.
4420 We also keep two one-byte offsets, which are to be subtracted from the
4421 constant pointers to yield addresses in the GPR and FPR save areas.
4422 These are downcounted as float or non-float arguments are used,
4423 and when they get to zero, the argument must be obtained from the
4424 overflow region.
4425 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4426 pointer is enough. It's started at the GPR save area, and is
4427 advanced, period.
4428 Note that the GPR save area is not constant size, due to optimization
4429 in the prologue. Hence, we can't use a design with two pointers
4430 and two offsets, although we could have designed this with two pointers
4431 and three offsets. */
4432
4433 static tree
4434 mips_build_builtin_va_list (void)
4435 {
4436 if (EABI_FLOAT_VARARGS_P)
4437 {
4438 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4439 tree array, index;
4440
4441 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4442
4443 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4444 ptr_type_node);
4445 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4446 ptr_type_node);
4447 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4448 ptr_type_node);
4449 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4450 unsigned_char_type_node);
4451 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4452 unsigned_char_type_node);
4453 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4454 warn on every user file. */
4455 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4456 array = build_array_type (unsigned_char_type_node,
4457 build_index_type (index));
4458 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4459
4460 DECL_FIELD_CONTEXT (f_ovfl) = record;
4461 DECL_FIELD_CONTEXT (f_gtop) = record;
4462 DECL_FIELD_CONTEXT (f_ftop) = record;
4463 DECL_FIELD_CONTEXT (f_goff) = record;
4464 DECL_FIELD_CONTEXT (f_foff) = record;
4465 DECL_FIELD_CONTEXT (f_res) = record;
4466
4467 TYPE_FIELDS (record) = f_ovfl;
4468 TREE_CHAIN (f_ovfl) = f_gtop;
4469 TREE_CHAIN (f_gtop) = f_ftop;
4470 TREE_CHAIN (f_ftop) = f_goff;
4471 TREE_CHAIN (f_goff) = f_foff;
4472 TREE_CHAIN (f_foff) = f_res;
4473
4474 layout_type (record);
4475 return record;
4476 }
4477 else if (TARGET_IRIX && TARGET_IRIX6)
4478 /* On IRIX 6, this type is 'char *'. */
4479 return build_pointer_type (char_type_node);
4480 else
4481 /* Otherwise, we use 'void *'. */
4482 return ptr_type_node;
4483 }
4484
4485 /* Implement va_start. */
4486
4487 void
4488 mips_va_start (tree valist, rtx nextarg)
4489 {
4490 if (EABI_FLOAT_VARARGS_P)
4491 {
4492 const CUMULATIVE_ARGS *cum;
4493 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4494 tree ovfl, gtop, ftop, goff, foff;
4495 tree t;
4496 int gpr_save_area_size;
4497 int fpr_save_area_size;
4498 int fpr_offset;
4499
4500 cum = &current_function_args_info;
4501 gpr_save_area_size
4502 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4503 fpr_save_area_size
4504 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4505
4506 f_ovfl = TYPE_FIELDS (va_list_type_node);
4507 f_gtop = TREE_CHAIN (f_ovfl);
4508 f_ftop = TREE_CHAIN (f_gtop);
4509 f_goff = TREE_CHAIN (f_ftop);
4510 f_foff = TREE_CHAIN (f_goff);
4511
4512 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4513 NULL_TREE);
4514 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4515 NULL_TREE);
4516 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4517 NULL_TREE);
4518 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4519 NULL_TREE);
4520 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4521 NULL_TREE);
4522
4523 /* Emit code to initialize OVFL, which points to the next varargs
4524 stack argument. CUM->STACK_WORDS gives the number of stack
4525 words used by named arguments. */
4526 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4527 if (cum->stack_words > 0)
4528 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4529 size_int (cum->stack_words * UNITS_PER_WORD));
4530 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4531 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4532
4533 /* Emit code to initialize GTOP, the top of the GPR save area. */
4534 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4535 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4536 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4537
4538 /* Emit code to initialize FTOP, the top of the FPR save area.
4539 This address is gpr_save_area_bytes below GTOP, rounded
4540 down to the next fp-aligned boundary. */
4541 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4542 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4543 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4544 if (fpr_offset)
4545 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4546 size_int (-fpr_offset));
4547 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4548 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4549
4550 /* Emit code to initialize GOFF, the offset from GTOP of the
4551 next GPR argument. */
4552 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4553 build_int_cst (NULL_TREE, gpr_save_area_size));
4554 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4555
4556 /* Likewise emit code to initialize FOFF, the offset from FTOP
4557 of the next FPR argument. */
4558 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4559 build_int_cst (NULL_TREE, fpr_save_area_size));
4560 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4561 }
4562 else
4563 {
4564 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4565 std_expand_builtin_va_start (valist, nextarg);
4566 }
4567 }
4568 \f
4569 /* Implement va_arg. */
4570
4571 static tree
4572 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4573 {
4574 HOST_WIDE_INT size, rsize;
4575 tree addr;
4576 bool indirect;
4577
4578 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4579
4580 if (indirect)
4581 type = build_pointer_type (type);
4582
4583 size = int_size_in_bytes (type);
4584 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4585
4586 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4587 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4588 else
4589 {
4590 /* Not a simple merged stack. */
4591
4592 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4593 tree ovfl, top, off, align;
4594 HOST_WIDE_INT osize;
4595 tree t, u;
4596
4597 f_ovfl = TYPE_FIELDS (va_list_type_node);
4598 f_gtop = TREE_CHAIN (f_ovfl);
4599 f_ftop = TREE_CHAIN (f_gtop);
4600 f_goff = TREE_CHAIN (f_ftop);
4601 f_foff = TREE_CHAIN (f_goff);
4602
4603 /* We maintain separate pointers and offsets for floating-point
4604 and integer arguments, but we need similar code in both cases.
4605 Let:
4606
4607 TOP be the top of the register save area;
4608 OFF be the offset from TOP of the next register;
4609 ADDR_RTX be the address of the argument;
4610 RSIZE be the number of bytes used to store the argument
4611 when it's in the register save area;
4612 OSIZE be the number of bytes used to store it when it's
4613 in the stack overflow area; and
4614 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4615
4616 The code we want is:
4617
4618 1: off &= -rsize; // round down
4619 2: if (off != 0)
4620 3: {
4621 4: addr_rtx = top - off;
4622 5: off -= rsize;
4623 6: }
4624 7: else
4625 8: {
4626 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4627 10: addr_rtx = ovfl + PADDING;
4628 11: ovfl += osize;
4629 14: }
4630
4631 [1] and [9] can sometimes be optimized away. */
4632
4633 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4634 NULL_TREE);
4635
4636 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4637 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4638 {
4639 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4640 NULL_TREE);
4641 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4642 NULL_TREE);
4643
4644 /* When floating-point registers are saved to the stack,
4645 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4646 of the float's precision. */
4647 rsize = UNITS_PER_HWFPVALUE;
4648
4649 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4650 (= PARM_BOUNDARY bits). This can be different from RSIZE
4651 in two cases:
4652
4653 (1) On 32-bit targets when TYPE is a structure such as:
4654
4655 struct s { float f; };
4656
4657 Such structures are passed in paired FPRs, so RSIZE
4658 will be 8 bytes. However, the structure only takes
4659 up 4 bytes of memory, so OSIZE will only be 4.
4660
4661 (2) In combinations such as -mgp64 -msingle-float
4662 -fshort-double. Doubles passed in registers
4663 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4664 but those passed on the stack take up
4665 UNITS_PER_WORD bytes. */
4666 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4667 }
4668 else
4669 {
4670 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4671 NULL_TREE);
4672 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4673 NULL_TREE);
4674 if (rsize > UNITS_PER_WORD)
4675 {
4676 /* [1] Emit code for: off &= -rsize. */
4677 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4678 build_int_cst (NULL_TREE, -rsize));
4679 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4680 gimplify_and_add (t, pre_p);
4681 }
4682 osize = rsize;
4683 }
4684
4685 /* [2] Emit code to branch if off == 0. */
4686 t = build2 (NE_EXPR, boolean_type_node, off,
4687 build_int_cst (TREE_TYPE (off), 0));
4688 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4689
4690 /* [5] Emit code for: off -= rsize. We do this as a form of
4691 post-increment not available to C. Also widen for the
4692 coming pointer arithmetic. */
4693 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4694 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4695 t = fold_convert (sizetype, t);
4696 t = fold_build1 (NEGATE_EXPR, sizetype, t);
4697
4698 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4699 the argument has RSIZE - SIZE bytes of leading padding. */
4700 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
4701 if (BYTES_BIG_ENDIAN && rsize > size)
4702 {
4703 u = size_int (rsize - size);
4704 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4705 }
4706 COND_EXPR_THEN (addr) = t;
4707
4708 if (osize > UNITS_PER_WORD)
4709 {
4710 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4711 u = size_int (osize - 1);
4712 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4713 t = fold_convert (sizetype, t);
4714 u = size_int (-osize);
4715 t = build2 (BIT_AND_EXPR, sizetype, t, u);
4716 t = fold_convert (TREE_TYPE (ovfl), t);
4717 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4718 }
4719 else
4720 align = NULL;
4721
4722 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4723 post-increment ovfl by osize. On big-endian machines,
4724 the argument has OSIZE - SIZE bytes of leading padding. */
4725 u = fold_convert (TREE_TYPE (ovfl),
4726 build_int_cst (NULL_TREE, osize));
4727 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4728 if (BYTES_BIG_ENDIAN && osize > size)
4729 {
4730 u = size_int (osize - size);
4731 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4732 }
4733
4734 /* String [9] and [10,11] together. */
4735 if (align)
4736 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4737 COND_EXPR_ELSE (addr) = t;
4738
4739 addr = fold_convert (build_pointer_type (type), addr);
4740 addr = build_va_arg_indirect_ref (addr);
4741 }
4742
4743 if (indirect)
4744 addr = build_va_arg_indirect_ref (addr);
4745
4746 return addr;
4747 }
4748 \f
4749 /* Return true if it is possible to use left/right accesses for a
4750 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4751 returning true, update *OP, *LEFT and *RIGHT as follows:
4752
4753 *OP is a BLKmode reference to the whole field.
4754
4755 *LEFT is a QImode reference to the first byte if big endian or
4756 the last byte if little endian. This address can be used in the
4757 left-side instructions (lwl, swl, ldl, sdl).
4758
4759 *RIGHT is a QImode reference to the opposite end of the field and
4760 can be used in the patterning right-side instruction. */
4761
4762 static bool
4763 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4764 rtx *left, rtx *right)
4765 {
4766 rtx first, last;
4767
4768 /* Check that the operand really is a MEM. Not all the extv and
4769 extzv predicates are checked. */
4770 if (!MEM_P (*op))
4771 return false;
4772
4773 /* Check that the size is valid. */
4774 if (width != 32 && (!TARGET_64BIT || width != 64))
4775 return false;
4776
4777 /* We can only access byte-aligned values. Since we are always passed
4778 a reference to the first byte of the field, it is not necessary to
4779 do anything with BITPOS after this check. */
4780 if (bitpos % BITS_PER_UNIT != 0)
4781 return false;
4782
4783 /* Reject aligned bitfields: we want to use a normal load or store
4784 instead of a left/right pair. */
4785 if (MEM_ALIGN (*op) >= width)
4786 return false;
4787
4788 /* Adjust *OP to refer to the whole field. This also has the effect
4789 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4790 *op = adjust_address (*op, BLKmode, 0);
4791 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4792
4793 /* Get references to both ends of the field. We deliberately don't
4794 use the original QImode *OP for FIRST since the new BLKmode one
4795 might have a simpler address. */
4796 first = adjust_address (*op, QImode, 0);
4797 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4798
4799 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4800 be the upper word and RIGHT the lower word. */
4801 if (TARGET_BIG_ENDIAN)
4802 *left = first, *right = last;
4803 else
4804 *left = last, *right = first;
4805
4806 return true;
4807 }
4808
4809
4810 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4811 Return true on success. We only handle cases where zero_extract is
4812 equivalent to sign_extract. */
4813
4814 bool
4815 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4816 {
4817 rtx left, right, temp;
4818
4819 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4820 paradoxical word_mode subreg. This is the only case in which
4821 we allow the destination to be larger than the source. */
4822 if (GET_CODE (dest) == SUBREG
4823 && GET_MODE (dest) == DImode
4824 && SUBREG_BYTE (dest) == 0
4825 && GET_MODE (SUBREG_REG (dest)) == SImode)
4826 dest = SUBREG_REG (dest);
4827
4828 /* After the above adjustment, the destination must be the same
4829 width as the source. */
4830 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4831 return false;
4832
4833 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4834 return false;
4835
4836 temp = gen_reg_rtx (GET_MODE (dest));
4837 if (GET_MODE (dest) == DImode)
4838 {
4839 emit_insn (gen_mov_ldl (temp, src, left));
4840 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4841 }
4842 else
4843 {
4844 emit_insn (gen_mov_lwl (temp, src, left));
4845 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4846 }
4847 return true;
4848 }
4849
4850
4851 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4852 true on success. */
4853
4854 bool
4855 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4856 {
4857 rtx left, right;
4858 enum machine_mode mode;
4859
4860 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4861 return false;
4862
4863 mode = mode_for_size (width, MODE_INT, 0);
4864 src = gen_lowpart (mode, src);
4865
4866 if (mode == DImode)
4867 {
4868 emit_insn (gen_mov_sdl (dest, src, left));
4869 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4870 }
4871 else
4872 {
4873 emit_insn (gen_mov_swl (dest, src, left));
4874 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4875 }
4876 return true;
4877 }
4878
4879 /* Return true if X is a MEM with the same size as MODE. */
4880
4881 bool
4882 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4883 {
4884 rtx size;
4885
4886 if (!MEM_P (x))
4887 return false;
4888
4889 size = MEM_SIZE (x);
4890 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4891 }
4892
4893 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4894 source of an "ext" instruction or the destination of an "ins"
4895 instruction. OP must be a register operand and the following
4896 conditions must hold:
4897
4898 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4899 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4900 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4901
4902 Also reject lengths equal to a word as they are better handled
4903 by the move patterns. */
4904
4905 bool
4906 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4907 {
4908 HOST_WIDE_INT len, pos;
4909
4910 if (!ISA_HAS_EXT_INS
4911 || !register_operand (op, VOIDmode)
4912 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4913 return false;
4914
4915 len = INTVAL (size);
4916 pos = INTVAL (position);
4917
4918 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4919 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4920 return false;
4921
4922 return true;
4923 }
4924
4925 /* Set up globals to generate code for the ISA or processor
4926 described by INFO. */
4927
4928 static void
4929 mips_set_architecture (const struct mips_cpu_info *info)
4930 {
4931 if (info != 0)
4932 {
4933 mips_arch_info = info;
4934 mips_arch = info->cpu;
4935 mips_isa = info->isa;
4936 }
4937 }
4938
4939
4940 /* Likewise for tuning. */
4941
4942 static void
4943 mips_set_tune (const struct mips_cpu_info *info)
4944 {
4945 if (info != 0)
4946 {
4947 mips_tune_info = info;
4948 mips_tune = info->cpu;
4949 }
4950 }
4951
4952 /* Implement TARGET_HANDLE_OPTION. */
4953
4954 static bool
4955 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4956 {
4957 switch (code)
4958 {
4959 case OPT_mabi_:
4960 if (strcmp (arg, "32") == 0)
4961 mips_abi = ABI_32;
4962 else if (strcmp (arg, "o64") == 0)
4963 mips_abi = ABI_O64;
4964 else if (strcmp (arg, "n32") == 0)
4965 mips_abi = ABI_N32;
4966 else if (strcmp (arg, "64") == 0)
4967 mips_abi = ABI_64;
4968 else if (strcmp (arg, "eabi") == 0)
4969 mips_abi = ABI_EABI;
4970 else
4971 return false;
4972 return true;
4973
4974 case OPT_march_:
4975 case OPT_mtune_:
4976 return mips_parse_cpu (arg) != 0;
4977
4978 case OPT_mips:
4979 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4980 return mips_isa_info != 0;
4981
4982 case OPT_mno_flush_func:
4983 mips_cache_flush_func = NULL;
4984 return true;
4985
4986 default:
4987 return true;
4988 }
4989 }
4990
4991 /* Set up the threshold for data to go into the small data area, instead
4992 of the normal data area, and detect any conflicts in the switches. */
4993
4994 void
4995 override_options (void)
4996 {
4997 int i, start, regno;
4998 enum machine_mode mode;
4999
5000 #ifdef SUBTARGET_OVERRIDE_OPTIONS
5001 SUBTARGET_OVERRIDE_OPTIONS;
5002 #endif
5003
5004 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
5005
5006 /* The following code determines the architecture and register size.
5007 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
5008 The GAS and GCC code should be kept in sync as much as possible. */
5009
5010 if (mips_arch_string != 0)
5011 mips_set_architecture (mips_parse_cpu (mips_arch_string));
5012
5013 if (mips_isa_info != 0)
5014 {
5015 if (mips_arch_info == 0)
5016 mips_set_architecture (mips_isa_info);
5017 else if (mips_arch_info->isa != mips_isa_info->isa)
5018 error ("-%s conflicts with the other architecture options, "
5019 "which specify a %s processor",
5020 mips_isa_info->name,
5021 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
5022 }
5023
5024 if (mips_arch_info == 0)
5025 {
5026 #ifdef MIPS_CPU_STRING_DEFAULT
5027 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
5028 #else
5029 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
5030 #endif
5031 }
5032
5033 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
5034 error ("-march=%s is not compatible with the selected ABI",
5035 mips_arch_info->name);
5036
5037 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5038 if (mips_tune_string != 0)
5039 mips_set_tune (mips_parse_cpu (mips_tune_string));
5040
5041 if (mips_tune_info == 0)
5042 mips_set_tune (mips_arch_info);
5043
5044 /* Set cost structure for the processor. */
5045 if (optimize_size)
5046 mips_cost = &mips_rtx_cost_optimize_size;
5047 else
5048 mips_cost = &mips_rtx_cost_data[mips_tune];
5049
5050 if ((target_flags_explicit & MASK_64BIT) != 0)
5051 {
5052 /* The user specified the size of the integer registers. Make sure
5053 it agrees with the ABI and ISA. */
5054 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
5055 error ("-mgp64 used with a 32-bit processor");
5056 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
5057 error ("-mgp32 used with a 64-bit ABI");
5058 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
5059 error ("-mgp64 used with a 32-bit ABI");
5060 }
5061 else
5062 {
5063 /* Infer the integer register size from the ABI and processor.
5064 Restrict ourselves to 32-bit registers if that's all the
5065 processor has, or if the ABI cannot handle 64-bit registers. */
5066 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
5067 target_flags &= ~MASK_64BIT;
5068 else
5069 target_flags |= MASK_64BIT;
5070 }
5071
5072 if ((target_flags_explicit & MASK_FLOAT64) != 0)
5073 {
5074 /* Really, -mfp32 and -mfp64 are ornamental options. There's
5075 only one right answer here. */
5076 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
5077 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
5078 else if (!TARGET_64BIT && TARGET_FLOAT64
5079 && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
5080 error ("-mgp32 and -mfp64 can only be combined if the target"
5081 " supports the mfhc1 and mthc1 instructions");
5082 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
5083 error ("unsupported combination: %s", "-mfp64 -msingle-float");
5084 }
5085 else
5086 {
5087 /* -msingle-float selects 32-bit float registers. Otherwise the
5088 float registers should be the same size as the integer ones. */
5089 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
5090 target_flags |= MASK_FLOAT64;
5091 else
5092 target_flags &= ~MASK_FLOAT64;
5093 }
5094
5095 /* End of code shared with GAS. */
5096
5097 if ((target_flags_explicit & MASK_LONG64) == 0)
5098 {
5099 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
5100 target_flags |= MASK_LONG64;
5101 else
5102 target_flags &= ~MASK_LONG64;
5103 }
5104
5105 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
5106 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
5107 {
5108 /* For some configurations, it is useful to have -march control
5109 the default setting of MASK_SOFT_FLOAT. */
5110 switch ((int) mips_arch)
5111 {
5112 case PROCESSOR_R4100:
5113 case PROCESSOR_R4111:
5114 case PROCESSOR_R4120:
5115 case PROCESSOR_R4130:
5116 target_flags |= MASK_SOFT_FLOAT;
5117 break;
5118
5119 default:
5120 target_flags &= ~MASK_SOFT_FLOAT;
5121 break;
5122 }
5123 }
5124
5125 if (!TARGET_OLDABI)
5126 flag_pcc_struct_return = 0;
5127
5128 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
5129 {
5130 /* If neither -mbranch-likely nor -mno-branch-likely was given
5131 on the command line, set MASK_BRANCHLIKELY based on the target
5132 architecture.
5133
5134 By default, we enable use of Branch Likely instructions on
5135 all architectures which support them with the following
5136 exceptions: when creating MIPS32 or MIPS64 code, and when
5137 tuning for architectures where their use tends to hurt
5138 performance.
5139
5140 The MIPS32 and MIPS64 architecture specifications say "Software
5141 is strongly encouraged to avoid use of Branch Likely
5142 instructions, as they will be removed from a future revision
5143 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
5144 issue those instructions unless instructed to do so by
5145 -mbranch-likely. */
5146 if (ISA_HAS_BRANCHLIKELY
5147 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
5148 && !(TUNE_MIPS5500 || TUNE_SB1))
5149 target_flags |= MASK_BRANCHLIKELY;
5150 else
5151 target_flags &= ~MASK_BRANCHLIKELY;
5152 }
5153 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
5154 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
5155
5156 /* The effect of -mabicalls isn't defined for the EABI. */
5157 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
5158 {
5159 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
5160 target_flags &= ~MASK_ABICALLS;
5161 }
5162
5163 if (TARGET_ABICALLS)
5164 {
5165 /* We need to set flag_pic for executables as well as DSOs
5166 because we may reference symbols that are not defined in
5167 the final executable. (MIPS does not use things like
5168 copy relocs, for example.)
5169
5170 Also, there is a body of code that uses __PIC__ to distinguish
5171 between -mabicalls and -mno-abicalls code. */
5172 flag_pic = 1;
5173 if (mips_section_threshold > 0)
5174 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
5175 }
5176
5177 if (TARGET_VXWORKS_RTP && mips_section_threshold > 0)
5178 warning (0, "-G and -mrtp are incompatible");
5179
5180 /* mips_split_addresses is a half-way house between explicit
5181 relocations and the traditional assembler macros. It can
5182 split absolute 32-bit symbolic constants into a high/lo_sum
5183 pair but uses macros for other sorts of access.
5184
5185 Like explicit relocation support for REL targets, it relies
5186 on GNU extensions in the assembler and the linker.
5187
5188 Although this code should work for -O0, it has traditionally
5189 been treated as an optimization. */
5190 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
5191 && optimize && !flag_pic
5192 && !ABI_HAS_64BIT_SYMBOLS)
5193 mips_split_addresses = 1;
5194 else
5195 mips_split_addresses = 0;
5196
5197 /* -mvr4130-align is a "speed over size" optimization: it usually produces
5198 faster code, but at the expense of more nops. Enable it at -O3 and
5199 above. */
5200 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
5201 target_flags |= MASK_VR4130_ALIGN;
5202
5203 /* When compiling for the mips16, we cannot use floating point. We
5204 record the original hard float value in mips16_hard_float. */
5205 if (TARGET_MIPS16)
5206 {
5207 if (TARGET_SOFT_FLOAT)
5208 mips16_hard_float = 0;
5209 else
5210 mips16_hard_float = 1;
5211 target_flags |= MASK_SOFT_FLOAT;
5212
5213 /* Don't run the scheduler before reload, since it tends to
5214 increase register pressure. */
5215 flag_schedule_insns = 0;
5216
5217 /* Don't do hot/cold partitioning. The constant layout code expects
5218 the whole function to be in a single section. */
5219 flag_reorder_blocks_and_partition = 0;
5220
5221 /* Silently disable -mexplicit-relocs since it doesn't apply
5222 to mips16 code. Even so, it would overly pedantic to warn
5223 about "-mips16 -mexplicit-relocs", especially given that
5224 we use a %gprel() operator. */
5225 target_flags &= ~MASK_EXPLICIT_RELOCS;
5226 }
5227
5228 /* When using explicit relocs, we call dbr_schedule from within
5229 mips_reorg. */
5230 if (TARGET_EXPLICIT_RELOCS)
5231 {
5232 mips_flag_delayed_branch = flag_delayed_branch;
5233 flag_delayed_branch = 0;
5234 }
5235
5236 #ifdef MIPS_TFMODE_FORMAT
5237 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
5238 #endif
5239
5240 /* Make sure that the user didn't turn off paired single support when
5241 MIPS-3D support is requested. */
5242 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
5243 && !TARGET_PAIRED_SINGLE_FLOAT)
5244 error ("-mips3d requires -mpaired-single");
5245
5246 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
5247 if (TARGET_MIPS3D)
5248 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
5249
5250 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
5251 and TARGET_HARD_FLOAT are both true. */
5252 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
5253 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
5254
5255 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
5256 enabled. */
5257 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
5258 error ("-mips3d/-mpaired-single must be used with -mips64");
5259
5260 /* If TARGET_DSPR2, enable MASK_DSP. */
5261 if (TARGET_DSPR2)
5262 target_flags |= MASK_DSP;
5263
5264 if (TARGET_MIPS16 && TARGET_DSP)
5265 error ("-mips16 and -mdsp cannot be used together");
5266
5267 mips_print_operand_punct['?'] = 1;
5268 mips_print_operand_punct['#'] = 1;
5269 mips_print_operand_punct['/'] = 1;
5270 mips_print_operand_punct['&'] = 1;
5271 mips_print_operand_punct['!'] = 1;
5272 mips_print_operand_punct['*'] = 1;
5273 mips_print_operand_punct['@'] = 1;
5274 mips_print_operand_punct['.'] = 1;
5275 mips_print_operand_punct['('] = 1;
5276 mips_print_operand_punct[')'] = 1;
5277 mips_print_operand_punct['['] = 1;
5278 mips_print_operand_punct[']'] = 1;
5279 mips_print_operand_punct['<'] = 1;
5280 mips_print_operand_punct['>'] = 1;
5281 mips_print_operand_punct['{'] = 1;
5282 mips_print_operand_punct['}'] = 1;
5283 mips_print_operand_punct['^'] = 1;
5284 mips_print_operand_punct['$'] = 1;
5285 mips_print_operand_punct['+'] = 1;
5286 mips_print_operand_punct['~'] = 1;
5287
5288 /* Set up array to map GCC register number to debug register number.
5289 Ignore the special purpose register numbers. */
5290
5291 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5292 {
5293 mips_dbx_regno[i] = INVALID_REGNUM;
5294 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
5295 mips_dwarf_regno[i] = i;
5296 else
5297 mips_dwarf_regno[i] = INVALID_REGNUM;
5298 }
5299
5300 start = GP_DBX_FIRST - GP_REG_FIRST;
5301 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5302 mips_dbx_regno[i] = i + start;
5303
5304 start = FP_DBX_FIRST - FP_REG_FIRST;
5305 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5306 mips_dbx_regno[i] = i + start;
5307
5308 /* HI and LO debug registers use big-endian ordering. */
5309 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5310 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5311 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
5312 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
5313 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
5314 {
5315 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
5316 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
5317 }
5318
5319 /* Set up array giving whether a given register can hold a given mode. */
5320
5321 for (mode = VOIDmode;
5322 mode != MAX_MACHINE_MODE;
5323 mode = (enum machine_mode) ((int)mode + 1))
5324 {
5325 register int size = GET_MODE_SIZE (mode);
5326 register enum mode_class class = GET_MODE_CLASS (mode);
5327
5328 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5329 {
5330 register int temp;
5331
5332 if (mode == CCV2mode)
5333 temp = (ISA_HAS_8CC
5334 && ST_REG_P (regno)
5335 && (regno - ST_REG_FIRST) % 2 == 0);
5336
5337 else if (mode == CCV4mode)
5338 temp = (ISA_HAS_8CC
5339 && ST_REG_P (regno)
5340 && (regno - ST_REG_FIRST) % 4 == 0);
5341
5342 else if (mode == CCmode)
5343 {
5344 if (! ISA_HAS_8CC)
5345 temp = (regno == FPSW_REGNUM);
5346 else
5347 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5348 || FP_REG_P (regno));
5349 }
5350
5351 else if (GP_REG_P (regno))
5352 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5353
5354 else if (FP_REG_P (regno))
5355 temp = ((((regno % MAX_FPRS_PER_FMT) == 0)
5356 || (MIN_FPRS_PER_FMT == 1
5357 && size <= UNITS_PER_FPREG))
5358 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5359 || class == MODE_VECTOR_FLOAT)
5360 && size <= UNITS_PER_FPVALUE)
5361 /* Allow integer modes that fit into a single
5362 register. We need to put integers into FPRs
5363 when using instructions like cvt and trunc.
5364 We can't allow sizes smaller than a word,
5365 the FPU has no appropriate load/store
5366 instructions for those. */
5367 || (class == MODE_INT
5368 && size >= MIN_UNITS_PER_WORD
5369 && size <= UNITS_PER_FPREG)
5370 /* Allow TFmode for CCmode reloads. */
5371 || (ISA_HAS_8CC && mode == TFmode)));
5372
5373 else if (ACC_REG_P (regno))
5374 temp = (INTEGRAL_MODE_P (mode)
5375 && size <= UNITS_PER_WORD * 2
5376 && (size <= UNITS_PER_WORD
5377 || regno == MD_REG_FIRST
5378 || (DSP_ACC_REG_P (regno)
5379 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)));
5380
5381 else if (ALL_COP_REG_P (regno))
5382 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5383 else
5384 temp = 0;
5385
5386 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5387 }
5388 }
5389
5390 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5391 initialized yet, so we can't use that here. */
5392 gpr_mode = TARGET_64BIT ? DImode : SImode;
5393
5394 /* Provide default values for align_* for 64-bit targets. */
5395 if (TARGET_64BIT && !TARGET_MIPS16)
5396 {
5397 if (align_loops == 0)
5398 align_loops = 8;
5399 if (align_jumps == 0)
5400 align_jumps = 8;
5401 if (align_functions == 0)
5402 align_functions = 8;
5403 }
5404
5405 /* Function to allocate machine-dependent function status. */
5406 init_machine_status = &mips_init_machine_status;
5407
5408 if (ABI_HAS_64BIT_SYMBOLS)
5409 {
5410 if (TARGET_EXPLICIT_RELOCS)
5411 {
5412 mips_split_p[SYMBOL_64_HIGH] = true;
5413 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5414 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5415
5416 mips_split_p[SYMBOL_64_MID] = true;
5417 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5418 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5419
5420 mips_split_p[SYMBOL_64_LOW] = true;
5421 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5422 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5423
5424 mips_split_p[SYMBOL_GENERAL] = true;
5425 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5426 }
5427 }
5428 else
5429 {
5430 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5431 {
5432 mips_split_p[SYMBOL_GENERAL] = true;
5433 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5434 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5435 }
5436 }
5437
5438 if (TARGET_MIPS16)
5439 {
5440 /* The high part is provided by a pseudo copy of $gp. */
5441 mips_split_p[SYMBOL_SMALL_DATA] = true;
5442 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5443 }
5444
5445 if (TARGET_EXPLICIT_RELOCS)
5446 {
5447 /* Small data constants are kept whole until after reload,
5448 then lowered by mips_rewrite_small_data. */
5449 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5450
5451 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
5452 if (TARGET_NEWABI)
5453 {
5454 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5455 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
5456 }
5457 else
5458 {
5459 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5460 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
5461 }
5462
5463 if (TARGET_XGOT)
5464 {
5465 /* The HIGH and LO_SUM are matched by special .md patterns. */
5466 mips_split_p[SYMBOL_GOT_DISP] = true;
5467
5468 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
5469 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
5470 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
5471
5472 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5473 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5474 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5475 }
5476 else
5477 {
5478 if (TARGET_NEWABI)
5479 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
5480 else
5481 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
5482 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5483 }
5484 }
5485
5486 if (TARGET_NEWABI)
5487 {
5488 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5489 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5490 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5491 }
5492
5493 /* Thread-local relocation operators. */
5494 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5495 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5496 mips_split_p[SYMBOL_DTPREL] = 1;
5497 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5498 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5499 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5500 mips_split_p[SYMBOL_TPREL] = 1;
5501 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5502 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5503
5504 mips_lo_relocs[SYMBOL_HALF] = "%half(";
5505
5506 /* We don't have a thread pointer access instruction on MIPS16, or
5507 appropriate TLS relocations. */
5508 if (TARGET_MIPS16)
5509 targetm.have_tls = false;
5510
5511 /* Default to working around R4000 errata only if the processor
5512 was selected explicitly. */
5513 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5514 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5515 target_flags |= MASK_FIX_R4000;
5516
5517 /* Default to working around R4400 errata only if the processor
5518 was selected explicitly. */
5519 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5520 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5521 target_flags |= MASK_FIX_R4400;
5522 }
5523
5524 /* Swap the register information for registers I and I + 1, which
5525 currently have the wrong endianness. Note that the registers'
5526 fixedness and call-clobberedness might have been set on the
5527 command line. */
5528
5529 static void
5530 mips_swap_registers (unsigned int i)
5531 {
5532 int tmpi;
5533 const char *tmps;
5534
5535 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
5536 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
5537
5538 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
5539 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
5540 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
5541 SWAP_STRING (reg_names[i], reg_names[i + 1]);
5542
5543 #undef SWAP_STRING
5544 #undef SWAP_INT
5545 }
5546
5547 /* Implement CONDITIONAL_REGISTER_USAGE. */
5548
5549 void
5550 mips_conditional_register_usage (void)
5551 {
5552 if (!TARGET_DSP)
5553 {
5554 int regno;
5555
5556 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5557 fixed_regs[regno] = call_used_regs[regno] = 1;
5558 }
5559 if (!TARGET_HARD_FLOAT)
5560 {
5561 int regno;
5562
5563 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5564 fixed_regs[regno] = call_used_regs[regno] = 1;
5565 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5566 fixed_regs[regno] = call_used_regs[regno] = 1;
5567 }
5568 else if (! ISA_HAS_8CC)
5569 {
5570 int regno;
5571
5572 /* We only have a single condition code register. We
5573 implement this by hiding all the condition code registers,
5574 and generating RTL that refers directly to ST_REG_FIRST. */
5575 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5576 fixed_regs[regno] = call_used_regs[regno] = 1;
5577 }
5578 /* In mips16 mode, we permit the $t temporary registers to be used
5579 for reload. We prohibit the unused $s registers, since they
5580 are caller saved, and saving them via a mips16 register would
5581 probably waste more time than just reloading the value. */
5582 if (TARGET_MIPS16)
5583 {
5584 fixed_regs[18] = call_used_regs[18] = 1;
5585 fixed_regs[19] = call_used_regs[19] = 1;
5586 fixed_regs[20] = call_used_regs[20] = 1;
5587 fixed_regs[21] = call_used_regs[21] = 1;
5588 fixed_regs[22] = call_used_regs[22] = 1;
5589 fixed_regs[23] = call_used_regs[23] = 1;
5590 fixed_regs[26] = call_used_regs[26] = 1;
5591 fixed_regs[27] = call_used_regs[27] = 1;
5592 fixed_regs[30] = call_used_regs[30] = 1;
5593 }
5594 /* fp20-23 are now caller saved. */
5595 if (mips_abi == ABI_64)
5596 {
5597 int regno;
5598 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5599 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5600 }
5601 /* Odd registers from fp21 to fp31 are now caller saved. */
5602 if (mips_abi == ABI_N32)
5603 {
5604 int regno;
5605 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5606 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5607 }
5608 /* Make sure that double-register accumulator values are correctly
5609 ordered for the current endianness. */
5610 if (TARGET_LITTLE_ENDIAN)
5611 {
5612 int regno;
5613 mips_swap_registers (MD_REG_FIRST);
5614 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
5615 mips_swap_registers (regno);
5616 }
5617 }
5618
5619 /* Allocate a chunk of memory for per-function machine-dependent data. */
5620 static struct machine_function *
5621 mips_init_machine_status (void)
5622 {
5623 return ((struct machine_function *)
5624 ggc_alloc_cleared (sizeof (struct machine_function)));
5625 }
5626
5627 /* On the mips16, we want to allocate $24 (T_REG) before other
5628 registers for instructions for which it is possible. This helps
5629 avoid shuffling registers around in order to set up for an xor,
5630 encouraging the compiler to use a cmp instead. */
5631
5632 void
5633 mips_order_regs_for_local_alloc (void)
5634 {
5635 register int i;
5636
5637 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5638 reg_alloc_order[i] = i;
5639
5640 if (TARGET_MIPS16)
5641 {
5642 /* It really doesn't matter where we put register 0, since it is
5643 a fixed register anyhow. */
5644 reg_alloc_order[0] = 24;
5645 reg_alloc_order[24] = 0;
5646 }
5647 }
5648
5649 \f
5650 /* The MIPS debug format wants all automatic variables and arguments
5651 to be in terms of the virtual frame pointer (stack pointer before
5652 any adjustment in the function), while the MIPS 3.0 linker wants
5653 the frame pointer to be the stack pointer after the initial
5654 adjustment. So, we do the adjustment here. The arg pointer (which
5655 is eliminated) points to the virtual frame pointer, while the frame
5656 pointer (which may be eliminated) points to the stack pointer after
5657 the initial adjustments. */
5658
5659 HOST_WIDE_INT
5660 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5661 {
5662 rtx offset2 = const0_rtx;
5663 rtx reg = eliminate_constant_term (addr, &offset2);
5664
5665 if (offset == 0)
5666 offset = INTVAL (offset2);
5667
5668 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5669 || reg == hard_frame_pointer_rtx)
5670 {
5671 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5672 ? compute_frame_size (get_frame_size ())
5673 : cfun->machine->frame.total_size;
5674
5675 /* MIPS16 frame is smaller */
5676 if (frame_pointer_needed && TARGET_MIPS16)
5677 frame_size -= cfun->machine->frame.args_size;
5678
5679 offset = offset - frame_size;
5680 }
5681
5682 /* sdbout_parms does not want this to crash for unrecognized cases. */
5683 #if 0
5684 else if (reg != arg_pointer_rtx)
5685 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5686 addr);
5687 #endif
5688
5689 return offset;
5690 }
5691 \f
5692 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5693
5694 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5695 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5696 'h' OP is HIGH, prints %hi(X),
5697 'd' output integer constant in decimal,
5698 'z' if the operand is 0, use $0 instead of normal operand.
5699 'D' print second part of double-word register or memory operand.
5700 'L' print low-order register of double-word register operand.
5701 'M' print high-order register of double-word register operand.
5702 'C' print part of opcode for a branch condition.
5703 'F' print part of opcode for a floating-point branch condition.
5704 'N' print part of opcode for a branch condition, inverted.
5705 'W' print part of opcode for a floating-point branch condition, inverted.
5706 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5707 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5708 't' like 'T', but with the EQ/NE cases reversed
5709 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5710 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5711 'R' print the reloc associated with LO_SUM
5712 'q' print DSP accumulator registers
5713
5714 The punctuation characters are:
5715
5716 '(' Turn on .set noreorder
5717 ')' Turn on .set reorder
5718 '[' Turn on .set noat
5719 ']' Turn on .set at
5720 '<' Turn on .set nomacro
5721 '>' Turn on .set macro
5722 '{' Turn on .set volatile (not GAS)
5723 '}' Turn on .set novolatile (not GAS)
5724 '&' Turn on .set noreorder if filling delay slots
5725 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5726 '!' Turn on .set nomacro if filling delay slots
5727 '#' Print nop if in a .set noreorder section.
5728 '/' Like '#', but does nothing within a delayed branch sequence
5729 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5730 '@' Print the name of the assembler temporary register (at or $1).
5731 '.' Print the name of the register with a hard-wired zero (zero or $0).
5732 '^' Print the name of the pic call-through register (t9 or $25).
5733 '$' Print the name of the stack pointer register (sp or $29).
5734 '+' Print the name of the gp register (usually gp or $28).
5735 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5736
5737 void
5738 print_operand (FILE *file, rtx op, int letter)
5739 {
5740 register enum rtx_code code;
5741
5742 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5743 {
5744 switch (letter)
5745 {
5746 case '?':
5747 if (mips_branch_likely)
5748 putc ('l', file);
5749 break;
5750
5751 case '@':
5752 fputs (reg_names [GP_REG_FIRST + 1], file);
5753 break;
5754
5755 case '^':
5756 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5757 break;
5758
5759 case '.':
5760 fputs (reg_names [GP_REG_FIRST + 0], file);
5761 break;
5762
5763 case '$':
5764 fputs (reg_names[STACK_POINTER_REGNUM], file);
5765 break;
5766
5767 case '+':
5768 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5769 break;
5770
5771 case '&':
5772 if (final_sequence != 0 && set_noreorder++ == 0)
5773 fputs (".set\tnoreorder\n\t", file);
5774 break;
5775
5776 case '*':
5777 if (final_sequence != 0)
5778 {
5779 if (set_noreorder++ == 0)
5780 fputs (".set\tnoreorder\n\t", file);
5781
5782 if (set_nomacro++ == 0)
5783 fputs (".set\tnomacro\n\t", file);
5784 }
5785 break;
5786
5787 case '!':
5788 if (final_sequence != 0 && set_nomacro++ == 0)
5789 fputs ("\n\t.set\tnomacro", file);
5790 break;
5791
5792 case '#':
5793 if (set_noreorder != 0)
5794 fputs ("\n\tnop", file);
5795 break;
5796
5797 case '/':
5798 /* Print an extra newline so that the delayed insn is separated
5799 from the following ones. This looks neater and is consistent
5800 with non-nop delayed sequences. */
5801 if (set_noreorder != 0 && final_sequence == 0)
5802 fputs ("\n\tnop\n", file);
5803 break;
5804
5805 case '(':
5806 if (set_noreorder++ == 0)
5807 fputs (".set\tnoreorder\n\t", file);
5808 break;
5809
5810 case ')':
5811 if (set_noreorder == 0)
5812 error ("internal error: %%) found without a %%( in assembler pattern");
5813
5814 else if (--set_noreorder == 0)
5815 fputs ("\n\t.set\treorder", file);
5816
5817 break;
5818
5819 case '[':
5820 if (set_noat++ == 0)
5821 fputs (".set\tnoat\n\t", file);
5822 break;
5823
5824 case ']':
5825 if (set_noat == 0)
5826 error ("internal error: %%] found without a %%[ in assembler pattern");
5827 else if (--set_noat == 0)
5828 fputs ("\n\t.set\tat", file);
5829
5830 break;
5831
5832 case '<':
5833 if (set_nomacro++ == 0)
5834 fputs (".set\tnomacro\n\t", file);
5835 break;
5836
5837 case '>':
5838 if (set_nomacro == 0)
5839 error ("internal error: %%> found without a %%< in assembler pattern");
5840 else if (--set_nomacro == 0)
5841 fputs ("\n\t.set\tmacro", file);
5842
5843 break;
5844
5845 case '{':
5846 if (set_volatile++ == 0)
5847 fputs ("#.set\tvolatile\n\t", file);
5848 break;
5849
5850 case '}':
5851 if (set_volatile == 0)
5852 error ("internal error: %%} found without a %%{ in assembler pattern");
5853 else if (--set_volatile == 0)
5854 fputs ("\n\t#.set\tnovolatile", file);
5855
5856 break;
5857
5858 case '~':
5859 {
5860 if (align_labels_log > 0)
5861 ASM_OUTPUT_ALIGN (file, align_labels_log);
5862 }
5863 break;
5864
5865 default:
5866 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5867 break;
5868 }
5869
5870 return;
5871 }
5872
5873 if (! op)
5874 {
5875 error ("PRINT_OPERAND null pointer");
5876 return;
5877 }
5878
5879 code = GET_CODE (op);
5880
5881 if (letter == 'C')
5882 switch (code)
5883 {
5884 case EQ: fputs ("eq", file); break;
5885 case NE: fputs ("ne", file); break;
5886 case GT: fputs ("gt", file); break;
5887 case GE: fputs ("ge", file); break;
5888 case LT: fputs ("lt", file); break;
5889 case LE: fputs ("le", file); break;
5890 case GTU: fputs ("gtu", file); break;
5891 case GEU: fputs ("geu", file); break;
5892 case LTU: fputs ("ltu", file); break;
5893 case LEU: fputs ("leu", file); break;
5894 default:
5895 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5896 }
5897
5898 else if (letter == 'N')
5899 switch (code)
5900 {
5901 case EQ: fputs ("ne", file); break;
5902 case NE: fputs ("eq", file); break;
5903 case GT: fputs ("le", file); break;
5904 case GE: fputs ("lt", file); break;
5905 case LT: fputs ("ge", file); break;
5906 case LE: fputs ("gt", file); break;
5907 case GTU: fputs ("leu", file); break;
5908 case GEU: fputs ("ltu", file); break;
5909 case LTU: fputs ("geu", file); break;
5910 case LEU: fputs ("gtu", file); break;
5911 default:
5912 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5913 }
5914
5915 else if (letter == 'F')
5916 switch (code)
5917 {
5918 case EQ: fputs ("c1f", file); break;
5919 case NE: fputs ("c1t", file); break;
5920 default:
5921 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5922 }
5923
5924 else if (letter == 'W')
5925 switch (code)
5926 {
5927 case EQ: fputs ("c1t", file); break;
5928 case NE: fputs ("c1f", file); break;
5929 default:
5930 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5931 }
5932
5933 else if (letter == 'h')
5934 {
5935 if (GET_CODE (op) == HIGH)
5936 op = XEXP (op, 0);
5937
5938 print_operand_reloc (file, op, mips_hi_relocs);
5939 }
5940
5941 else if (letter == 'R')
5942 print_operand_reloc (file, op, mips_lo_relocs);
5943
5944 else if (letter == 'Y')
5945 {
5946 if (GET_CODE (op) == CONST_INT
5947 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5948 < ARRAY_SIZE (mips_fp_conditions)))
5949 fputs (mips_fp_conditions[INTVAL (op)], file);
5950 else
5951 output_operand_lossage ("invalid %%Y value");
5952 }
5953
5954 else if (letter == 'Z')
5955 {
5956 if (ISA_HAS_8CC)
5957 {
5958 print_operand (file, op, 0);
5959 fputc (',', file);
5960 }
5961 }
5962
5963 else if (letter == 'q')
5964 {
5965 int regnum;
5966
5967 if (code != REG)
5968 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5969
5970 regnum = REGNO (op);
5971 if (MD_REG_P (regnum))
5972 fprintf (file, "$ac0");
5973 else if (DSP_ACC_REG_P (regnum))
5974 fprintf (file, "$ac%c", reg_names[regnum][3]);
5975 else
5976 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5977 }
5978
5979 else if (code == REG || code == SUBREG)
5980 {
5981 register int regnum;
5982
5983 if (code == REG)
5984 regnum = REGNO (op);
5985 else
5986 regnum = true_regnum (op);
5987
5988 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5989 || (letter == 'L' && WORDS_BIG_ENDIAN)
5990 || letter == 'D')
5991 regnum++;
5992
5993 fprintf (file, "%s", reg_names[regnum]);
5994 }
5995
5996 else if (code == MEM)
5997 {
5998 if (letter == 'D')
5999 output_address (plus_constant (XEXP (op, 0), 4));
6000 else
6001 output_address (XEXP (op, 0));
6002 }
6003
6004 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
6005 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
6006
6007 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
6008 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
6009
6010 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
6011 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
6012
6013 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
6014 fputs (reg_names[GP_REG_FIRST], file);
6015
6016 else if (letter == 'd' || letter == 'x' || letter == 'X')
6017 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
6018
6019 else if (letter == 'T' || letter == 't')
6020 {
6021 int truth = (code == NE) == (letter == 'T');
6022 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
6023 }
6024
6025 else if (CONST_GP_P (op))
6026 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
6027
6028 else
6029 output_addr_const (file, op);
6030 }
6031
6032
6033 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
6034 RELOCS is the array of relocations to use. */
6035
6036 static void
6037 print_operand_reloc (FILE *file, rtx op, const char **relocs)
6038 {
6039 enum mips_symbol_type symbol_type;
6040 const char *p;
6041 rtx base, offset;
6042
6043 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
6044 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
6045
6046 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
6047 split_const (op, &base, &offset);
6048 if (UNSPEC_ADDRESS_P (base))
6049 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6050
6051 fputs (relocs[symbol_type], file);
6052 output_addr_const (file, op);
6053 for (p = relocs[symbol_type]; *p != 0; p++)
6054 if (*p == '(')
6055 fputc (')', file);
6056 }
6057 \f
6058 /* Output address operand X to FILE. */
6059
6060 void
6061 print_operand_address (FILE *file, rtx x)
6062 {
6063 struct mips_address_info addr;
6064
6065 if (mips_classify_address (&addr, x, word_mode, true))
6066 switch (addr.type)
6067 {
6068 case ADDRESS_REG:
6069 print_operand (file, addr.offset, 0);
6070 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6071 return;
6072
6073 case ADDRESS_LO_SUM:
6074 print_operand (file, addr.offset, 'R');
6075 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6076 return;
6077
6078 case ADDRESS_CONST_INT:
6079 output_addr_const (file, x);
6080 fprintf (file, "(%s)", reg_names[0]);
6081 return;
6082
6083 case ADDRESS_SYMBOLIC:
6084 output_addr_const (file, x);
6085 return;
6086 }
6087 gcc_unreachable ();
6088 }
6089 \f
6090 /* When using assembler macros, keep track of all of small-data externs
6091 so that mips_file_end can emit the appropriate declarations for them.
6092
6093 In most cases it would be safe (though pointless) to emit .externs
6094 for other symbols too. One exception is when an object is within
6095 the -G limit but declared by the user to be in a section other
6096 than .sbss or .sdata. */
6097
6098 void
6099 mips_output_external (FILE *file, tree decl, const char *name)
6100 {
6101 default_elf_asm_output_external (file, decl, name);
6102
6103 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6104 set in order to avoid putting out names that are never really
6105 used. */
6106 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
6107 {
6108 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
6109 {
6110 fputs ("\t.extern\t", file);
6111 assemble_name (file, name);
6112 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
6113 int_size_in_bytes (TREE_TYPE (decl)));
6114 }
6115 else if (TARGET_IRIX
6116 && mips_abi == ABI_32
6117 && TREE_CODE (decl) == FUNCTION_DECL)
6118 {
6119 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6120 `.global name .text' directive for every used but
6121 undefined function. If we don't, the linker may perform
6122 an optimization (skipping over the insns that set $gp)
6123 when it is unsafe. */
6124 fputs ("\t.globl ", file);
6125 assemble_name (file, name);
6126 fputs (" .text\n", file);
6127 }
6128 }
6129 }
6130 \f
6131 /* Emit a new filename to a stream. If we are smuggling stabs, try to
6132 put out a MIPS ECOFF file and a stab. */
6133
6134 void
6135 mips_output_filename (FILE *stream, const char *name)
6136 {
6137
6138 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6139 directives. */
6140 if (write_symbols == DWARF2_DEBUG)
6141 return;
6142 else if (mips_output_filename_first_time)
6143 {
6144 mips_output_filename_first_time = 0;
6145 num_source_filenames += 1;
6146 current_function_file = name;
6147 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6148 output_quoted_string (stream, name);
6149 putc ('\n', stream);
6150 }
6151
6152 /* If we are emitting stabs, let dbxout.c handle this (except for
6153 the mips_output_filename_first_time case). */
6154 else if (write_symbols == DBX_DEBUG)
6155 return;
6156
6157 else if (name != current_function_file
6158 && strcmp (name, current_function_file) != 0)
6159 {
6160 num_source_filenames += 1;
6161 current_function_file = name;
6162 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6163 output_quoted_string (stream, name);
6164 putc ('\n', stream);
6165 }
6166 }
6167 \f
6168 /* Output an ASCII string, in a space-saving way. PREFIX is the string
6169 that should be written before the opening quote, such as "\t.ascii\t"
6170 for real string data or "\t# " for a comment. */
6171
6172 void
6173 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
6174 const char *prefix)
6175 {
6176 size_t i;
6177 int cur_pos = 17;
6178 register const unsigned char *string =
6179 (const unsigned char *)string_param;
6180
6181 fprintf (stream, "%s\"", prefix);
6182 for (i = 0; i < len; i++)
6183 {
6184 register int c = string[i];
6185
6186 if (ISPRINT (c))
6187 {
6188 if (c == '\\' || c == '\"')
6189 {
6190 putc ('\\', stream);
6191 cur_pos++;
6192 }
6193 putc (c, stream);
6194 cur_pos++;
6195 }
6196 else
6197 {
6198 fprintf (stream, "\\%03o", c);
6199 cur_pos += 4;
6200 }
6201
6202 if (cur_pos > 72 && i+1 < len)
6203 {
6204 cur_pos = 17;
6205 fprintf (stream, "\"\n%s\"", prefix);
6206 }
6207 }
6208 fprintf (stream, "\"\n");
6209 }
6210 \f
6211 /* Implement TARGET_ASM_FILE_START. */
6212
6213 static void
6214 mips_file_start (void)
6215 {
6216 default_file_start ();
6217
6218 if (!TARGET_IRIX)
6219 {
6220 /* Generate a special section to describe the ABI switches used to
6221 produce the resultant binary. This used to be done by the assembler
6222 setting bits in the ELF header's flags field, but we have run out of
6223 bits. GDB needs this information in order to be able to correctly
6224 debug these binaries. See the function mips_gdbarch_init() in
6225 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6226 causes unnecessary IRIX 6 ld warnings. */
6227 const char * abi_string = NULL;
6228
6229 switch (mips_abi)
6230 {
6231 case ABI_32: abi_string = "abi32"; break;
6232 case ABI_N32: abi_string = "abiN32"; break;
6233 case ABI_64: abi_string = "abi64"; break;
6234 case ABI_O64: abi_string = "abiO64"; break;
6235 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6236 default:
6237 gcc_unreachable ();
6238 }
6239 /* Note - we use fprintf directly rather than calling switch_to_section
6240 because in this way we can avoid creating an allocated section. We
6241 do not want this section to take up any space in the running
6242 executable. */
6243 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
6244
6245 /* There is no ELF header flag to distinguish long32 forms of the
6246 EABI from long64 forms. Emit a special section to help tools
6247 such as GDB. Do the same for o64, which is sometimes used with
6248 -mlong64. */
6249 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
6250 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
6251 TARGET_LONG64 ? 64 : 32);
6252
6253 /* Restore the default section. */
6254 fprintf (asm_out_file, "\t.previous\n");
6255
6256 #ifdef HAVE_AS_GNU_ATTRIBUTE
6257 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
6258 TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT ? 1 : 2) : 3);
6259 #endif
6260 }
6261
6262 /* Generate the pseudo ops that System V.4 wants. */
6263 if (TARGET_ABICALLS)
6264 fprintf (asm_out_file, "\t.abicalls\n");
6265
6266 if (TARGET_MIPS16)
6267 fprintf (asm_out_file, "\t.set\tmips16\n");
6268
6269 if (flag_verbose_asm)
6270 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6271 ASM_COMMENT_START,
6272 mips_section_threshold, mips_arch_info->name, mips_isa);
6273 }
6274
6275 #ifdef BSS_SECTION_ASM_OP
6276 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
6277 in the use of sbss. */
6278
6279 void
6280 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
6281 unsigned HOST_WIDE_INT size, int align)
6282 {
6283 extern tree last_assemble_variable_decl;
6284
6285 if (mips_in_small_data_p (decl))
6286 switch_to_section (get_named_section (NULL, ".sbss", 0));
6287 else
6288 switch_to_section (bss_section);
6289 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6290 last_assemble_variable_decl = decl;
6291 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
6292 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
6293 }
6294 #endif
6295 \f
6296 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
6297 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
6298
6299 void
6300 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6301 unsigned HOST_WIDE_INT size,
6302 unsigned int align)
6303 {
6304 /* If the target wants uninitialized const declarations in
6305 .rdata then don't put them in .comm. */
6306 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6307 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6308 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6309 {
6310 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6311 targetm.asm_out.globalize_label (stream, name);
6312
6313 switch_to_section (readonly_data_section);
6314 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6315 mips_declare_object (stream, name, "",
6316 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6317 size);
6318 }
6319 else
6320 mips_declare_common_object (stream, name, "\n\t.comm\t",
6321 size, align, true);
6322 }
6323
6324 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6325 NAME is the name of the object and ALIGN is the required alignment
6326 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6327 alignment argument. */
6328
6329 void
6330 mips_declare_common_object (FILE *stream, const char *name,
6331 const char *init_string,
6332 unsigned HOST_WIDE_INT size,
6333 unsigned int align, bool takes_alignment_p)
6334 {
6335 if (!takes_alignment_p)
6336 {
6337 size += (align / BITS_PER_UNIT) - 1;
6338 size -= size % (align / BITS_PER_UNIT);
6339 mips_declare_object (stream, name, init_string,
6340 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6341 }
6342 else
6343 mips_declare_object (stream, name, init_string,
6344 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6345 size, align / BITS_PER_UNIT);
6346 }
6347
6348 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6349 macros, mark the symbol as written so that mips_file_end won't emit an
6350 .extern for it. STREAM is the output file, NAME is the name of the
6351 symbol, INIT_STRING is the string that should be written before the
6352 symbol and FINAL_STRING is the string that should be written after it.
6353 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6354
6355 void
6356 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6357 const char *final_string, ...)
6358 {
6359 va_list ap;
6360
6361 fputs (init_string, stream);
6362 assemble_name (stream, name);
6363 va_start (ap, final_string);
6364 vfprintf (stream, final_string, ap);
6365 va_end (ap);
6366
6367 if (!TARGET_EXPLICIT_RELOCS)
6368 {
6369 tree name_tree = get_identifier (name);
6370 TREE_ASM_WRITTEN (name_tree) = 1;
6371 }
6372 }
6373
6374 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6375 extern int size_directive_output;
6376
6377 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6378 definitions except that it uses mips_declare_object() to emit the label. */
6379
6380 void
6381 mips_declare_object_name (FILE *stream, const char *name,
6382 tree decl ATTRIBUTE_UNUSED)
6383 {
6384 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6385 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6386 #endif
6387
6388 size_directive_output = 0;
6389 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6390 {
6391 HOST_WIDE_INT size;
6392
6393 size_directive_output = 1;
6394 size = int_size_in_bytes (TREE_TYPE (decl));
6395 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6396 }
6397
6398 mips_declare_object (stream, name, "", ":\n");
6399 }
6400
6401 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6402
6403 void
6404 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6405 {
6406 const char *name;
6407
6408 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6409 if (!flag_inhibit_size_directive
6410 && DECL_SIZE (decl) != 0
6411 && !at_end && top_level
6412 && DECL_INITIAL (decl) == error_mark_node
6413 && !size_directive_output)
6414 {
6415 HOST_WIDE_INT size;
6416
6417 size_directive_output = 1;
6418 size = int_size_in_bytes (TREE_TYPE (decl));
6419 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6420 }
6421 }
6422 #endif
6423 \f
6424 /* Return true if X is a small data address that can be rewritten
6425 as a LO_SUM. */
6426
6427 static bool
6428 mips_rewrite_small_data_p (rtx x)
6429 {
6430 enum mips_symbol_type symbol_type;
6431
6432 return (TARGET_EXPLICIT_RELOCS
6433 && mips_symbolic_constant_p (x, &symbol_type)
6434 && symbol_type == SYMBOL_SMALL_DATA);
6435 }
6436
6437
6438 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6439
6440 static int
6441 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6442 {
6443 if (GET_CODE (*loc) == LO_SUM)
6444 return -1;
6445
6446 return mips_rewrite_small_data_p (*loc);
6447 }
6448
6449 /* Return true if OP refers to small data symbols directly, not through
6450 a LO_SUM. */
6451
6452 bool
6453 mips_small_data_pattern_p (rtx op)
6454 {
6455 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6456 }
6457 \f
6458 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6459
6460 static int
6461 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6462 {
6463 if (mips_rewrite_small_data_p (*loc))
6464 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6465
6466 if (GET_CODE (*loc) == LO_SUM)
6467 return -1;
6468
6469 return 0;
6470 }
6471
6472 /* If possible, rewrite OP so that it refers to small data using
6473 explicit relocations. */
6474
6475 rtx
6476 mips_rewrite_small_data (rtx op)
6477 {
6478 op = copy_insn (op);
6479 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6480 return op;
6481 }
6482 \f
6483 /* Return true if the current function has an insn that implicitly
6484 refers to $gp. */
6485
6486 static bool
6487 mips_function_has_gp_insn (void)
6488 {
6489 /* Don't bother rechecking if we found one last time. */
6490 if (!cfun->machine->has_gp_insn_p)
6491 {
6492 rtx insn;
6493
6494 push_topmost_sequence ();
6495 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6496 if (INSN_P (insn)
6497 && GET_CODE (PATTERN (insn)) != USE
6498 && GET_CODE (PATTERN (insn)) != CLOBBER
6499 && (get_attr_got (insn) != GOT_UNSET
6500 || small_data_pattern (PATTERN (insn), VOIDmode)))
6501 break;
6502 pop_topmost_sequence ();
6503
6504 cfun->machine->has_gp_insn_p = (insn != 0);
6505 }
6506 return cfun->machine->has_gp_insn_p;
6507 }
6508
6509
6510 /* Return the register that should be used as the global pointer
6511 within this function. Return 0 if the function doesn't need
6512 a global pointer. */
6513
6514 static unsigned int
6515 mips_global_pointer (void)
6516 {
6517 unsigned int regno;
6518
6519 /* $gp is always available unless we're using a GOT. */
6520 if (!TARGET_USE_GOT)
6521 return GLOBAL_POINTER_REGNUM;
6522
6523 /* We must always provide $gp when it is used implicitly. */
6524 if (!TARGET_EXPLICIT_RELOCS)
6525 return GLOBAL_POINTER_REGNUM;
6526
6527 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6528 a valid gp. */
6529 if (current_function_profile)
6530 return GLOBAL_POINTER_REGNUM;
6531
6532 /* If the function has a nonlocal goto, $gp must hold the correct
6533 global pointer for the target function. */
6534 if (current_function_has_nonlocal_goto)
6535 return GLOBAL_POINTER_REGNUM;
6536
6537 /* If the gp is never referenced, there's no need to initialize it.
6538 Note that reload can sometimes introduce constant pool references
6539 into a function that otherwise didn't need them. For example,
6540 suppose we have an instruction like:
6541
6542 (set (reg:DF R1) (float:DF (reg:SI R2)))
6543
6544 If R2 turns out to be constant such as 1, the instruction may have a
6545 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6546 using this constant if R2 doesn't get allocated to a register.
6547
6548 In cases like these, reload will have added the constant to the pool
6549 but no instruction will yet refer to it. */
6550 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
6551 && !current_function_uses_const_pool
6552 && !mips_function_has_gp_insn ())
6553 return 0;
6554
6555 /* We need a global pointer, but perhaps we can use a call-clobbered
6556 register instead of $gp. */
6557 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
6558 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6559 if (!df_regs_ever_live_p (regno)
6560 && call_used_regs[regno]
6561 && !fixed_regs[regno]
6562 && regno != PIC_FUNCTION_ADDR_REGNUM)
6563 return regno;
6564
6565 return GLOBAL_POINTER_REGNUM;
6566 }
6567
6568
6569 /* Return true if the function return value MODE will get returned in a
6570 floating-point register. */
6571
6572 static bool
6573 mips_return_mode_in_fpr_p (enum machine_mode mode)
6574 {
6575 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
6576 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
6577 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6578 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
6579 }
6580
6581 /* Return a two-character string representing a function floating-point
6582 return mode, used to name MIPS16 function stubs. */
6583
6584 static const char *
6585 mips16_call_stub_mode_suffix (enum machine_mode mode)
6586 {
6587 if (mode == SFmode)
6588 return "sf";
6589 else if (mode == DFmode)
6590 return "df";
6591 else if (mode == SCmode)
6592 return "sc";
6593 else if (mode == DCmode)
6594 return "dc";
6595 else if (mode == V2SFmode)
6596 return "df";
6597 else
6598 gcc_unreachable ();
6599 }
6600
6601 /* Return true if the current function returns its value in a floating-point
6602 register in MIPS16 mode. */
6603
6604 static bool
6605 mips16_cfun_returns_in_fpr_p (void)
6606 {
6607 tree return_type = DECL_RESULT (current_function_decl);
6608 return (mips16_hard_float
6609 && !aggregate_value_p (return_type, current_function_decl)
6610 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
6611 }
6612
6613
6614 /* Return true if the current function must save REGNO. */
6615
6616 static bool
6617 mips_save_reg_p (unsigned int regno)
6618 {
6619 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
6620 if we have not chosen a call-clobbered substitute. */
6621 if (regno == GLOBAL_POINTER_REGNUM)
6622 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
6623
6624 /* Check call-saved registers. */
6625 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
6626 return true;
6627
6628 /* Save both registers in an FPR pair if either one is used. This is
6629 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
6630 register to be used without the even register. */
6631 if (FP_REG_P (regno)
6632 && MAX_FPRS_PER_FMT == 2
6633 && df_regs_ever_live_p (regno + 1)
6634 && !call_used_regs[regno + 1])
6635 return true;
6636
6637 /* We need to save the old frame pointer before setting up a new one. */
6638 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6639 return true;
6640
6641 /* We need to save the incoming return address if it is ever clobbered
6642 within the function. */
6643 if (regno == GP_REG_FIRST + 31 && df_regs_ever_live_p (regno))
6644 return true;
6645
6646 if (TARGET_MIPS16)
6647 {
6648 /* $18 is a special case in mips16 code. It may be used to call
6649 a function which returns a floating point value, but it is
6650 marked in call_used_regs. */
6651 if (regno == GP_REG_FIRST + 18 && df_regs_ever_live_p (regno))
6652 return true;
6653
6654 /* $31 is also a special case. It will be used to copy a return
6655 value into the floating point registers if the return value is
6656 floating point. */
6657 if (regno == GP_REG_FIRST + 31
6658 && mips16_cfun_returns_in_fpr_p ())
6659 return true;
6660 }
6661
6662 return false;
6663 }
6664
6665 /* Return the index of the lowest X in the range [0, SIZE) for which
6666 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
6667
6668 static unsigned int
6669 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
6670 unsigned int size)
6671 {
6672 unsigned int i;
6673
6674 for (i = 0; i < size; i++)
6675 if (BITSET_P (mask, regs[i]))
6676 break;
6677
6678 return i;
6679 }
6680
6681 /* *MASK_PTR is a mask of general purpose registers and *GP_REG_SIZE_PTR
6682 is the number of bytes that they occupy. If *MASK_PTR contains REGS[X]
6683 for some X in [0, SIZE), adjust *MASK_PTR and *GP_REG_SIZE_PTR so that
6684 the same is true for all indexes (X, SIZE). */
6685
6686 static void
6687 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
6688 unsigned int size, HOST_WIDE_INT *gp_reg_size_ptr)
6689 {
6690 unsigned int i;
6691
6692 i = mips16e_find_first_register (*mask_ptr, regs, size);
6693 for (i++; i < size; i++)
6694 if (!BITSET_P (*mask_ptr, regs[i]))
6695 {
6696 *gp_reg_size_ptr += GET_MODE_SIZE (gpr_mode);
6697 *mask_ptr |= 1 << regs[i];
6698 }
6699 }
6700
6701 /* Return the bytes needed to compute the frame pointer from the current
6702 stack pointer. SIZE is the size (in bytes) of the local variables.
6703
6704 MIPS stack frames look like:
6705
6706 Before call After call
6707 high +-----------------------+ +-----------------------+
6708 mem. | | | |
6709 | caller's temps. | | caller's temps. |
6710 | | | |
6711 +-----------------------+ +-----------------------+
6712 | | | |
6713 | arguments on stack. | | arguments on stack. |
6714 | | | |
6715 +-----------------------+ +-----------------------+
6716 | 4 words to save | | 4 words to save |
6717 | arguments passed | | arguments passed |
6718 | in registers, even | | in registers, even |
6719 | if not passed. | | if not passed. |
6720 SP->+-----------------------+ VFP->+-----------------------+
6721 (VFP = SP+fp_sp_offset) | |\
6722 | fp register save | | fp_reg_size
6723 | |/
6724 SP+gp_sp_offset->+-----------------------+
6725 /| |\
6726 | | gp register save | | gp_reg_size
6727 gp_reg_rounded | | |/
6728 | +-----------------------+
6729 \| alignment padding |
6730 +-----------------------+
6731 | |\
6732 | local variables | | var_size
6733 | |/
6734 +-----------------------+
6735 | |
6736 | alloca allocations |
6737 | |
6738 +-----------------------+
6739 /| |
6740 cprestore_size | | GP save for V.4 abi |
6741 \| |
6742 +-----------------------+
6743 | |\
6744 | arguments on stack | |
6745 | | |
6746 +-----------------------+ |
6747 | 4 words to save | | args_size
6748 | arguments passed | |
6749 | in registers, even | |
6750 | if not passed. | |
6751 low | (TARGET_OLDABI only) |/
6752 memory SP->+-----------------------+
6753
6754 */
6755
6756 HOST_WIDE_INT
6757 compute_frame_size (HOST_WIDE_INT size)
6758 {
6759 unsigned int regno;
6760 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6761 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6762 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6763 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6764 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6765 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6766 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6767 unsigned int mask; /* mask of saved gp registers */
6768 unsigned int fmask; /* mask of saved fp registers */
6769
6770 cfun->machine->global_pointer = mips_global_pointer ();
6771
6772 gp_reg_size = 0;
6773 fp_reg_size = 0;
6774 mask = 0;
6775 fmask = 0;
6776 var_size = MIPS_STACK_ALIGN (size);
6777 args_size = current_function_outgoing_args_size;
6778 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6779
6780 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6781 functions. If the function has local variables, we're committed
6782 to allocating it anyway. Otherwise reclaim it here. */
6783 if (var_size == 0 && current_function_is_leaf)
6784 cprestore_size = args_size = 0;
6785
6786 /* The MIPS 3.0 linker does not like functions that dynamically
6787 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6788 looks like we are trying to create a second frame pointer to the
6789 function, so allocate some stack space to make it happy. */
6790
6791 if (args_size == 0 && current_function_calls_alloca)
6792 args_size = 4 * UNITS_PER_WORD;
6793
6794 total_size = var_size + args_size + cprestore_size;
6795
6796 /* Calculate space needed for gp registers. */
6797 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6798 if (mips_save_reg_p (regno))
6799 {
6800 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6801 mask |= 1 << (regno - GP_REG_FIRST);
6802 }
6803
6804 /* We need to restore these for the handler. */
6805 if (current_function_calls_eh_return)
6806 {
6807 unsigned int i;
6808 for (i = 0; ; ++i)
6809 {
6810 regno = EH_RETURN_DATA_REGNO (i);
6811 if (regno == INVALID_REGNUM)
6812 break;
6813 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6814 mask |= 1 << (regno - GP_REG_FIRST);
6815 }
6816 }
6817
6818 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
6819 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
6820 save all later registers too. */
6821 if (GENERATE_MIPS16E_SAVE_RESTORE)
6822 {
6823 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
6824 ARRAY_SIZE (mips16e_s2_s8_regs), &gp_reg_size);
6825 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
6826 ARRAY_SIZE (mips16e_a0_a3_regs), &gp_reg_size);
6827 }
6828
6829 /* This loop must iterate over the same space as its companion in
6830 mips_for_each_saved_reg. */
6831 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6832 regno >= FP_REG_FIRST;
6833 regno -= MAX_FPRS_PER_FMT)
6834 {
6835 if (mips_save_reg_p (regno))
6836 {
6837 fp_reg_size += MAX_FPRS_PER_FMT * UNITS_PER_FPREG;
6838 fmask |= ((1 << MAX_FPRS_PER_FMT) - 1) << (regno - FP_REG_FIRST);
6839 }
6840 }
6841
6842 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6843 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6844
6845 /* Add in the space required for saving incoming register arguments. */
6846 total_size += current_function_pretend_args_size;
6847 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6848
6849 /* Save other computed information. */
6850 cfun->machine->frame.total_size = total_size;
6851 cfun->machine->frame.var_size = var_size;
6852 cfun->machine->frame.args_size = args_size;
6853 cfun->machine->frame.cprestore_size = cprestore_size;
6854 cfun->machine->frame.gp_reg_size = gp_reg_size;
6855 cfun->machine->frame.fp_reg_size = fp_reg_size;
6856 cfun->machine->frame.mask = mask;
6857 cfun->machine->frame.fmask = fmask;
6858 cfun->machine->frame.initialized = reload_completed;
6859 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6860 cfun->machine->frame.num_fp = (fp_reg_size
6861 / (MAX_FPRS_PER_FMT * UNITS_PER_FPREG));
6862
6863 if (mask)
6864 {
6865 HOST_WIDE_INT offset;
6866
6867 if (GENERATE_MIPS16E_SAVE_RESTORE)
6868 /* MIPS16e SAVE and RESTORE instructions require the GP save area
6869 to be aligned at the high end with any padding at the low end.
6870 It is only safe to use this calculation for o32, where we never
6871 have pretend arguments, and where any varargs will be saved in
6872 the caller-allocated area rather than at the top of the frame. */
6873 offset = (total_size - GET_MODE_SIZE (gpr_mode));
6874 else
6875 offset = (args_size + cprestore_size + var_size
6876 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6877 cfun->machine->frame.gp_sp_offset = offset;
6878 cfun->machine->frame.gp_save_offset = offset - total_size;
6879 }
6880 else
6881 {
6882 cfun->machine->frame.gp_sp_offset = 0;
6883 cfun->machine->frame.gp_save_offset = 0;
6884 }
6885
6886 if (fmask)
6887 {
6888 HOST_WIDE_INT offset;
6889
6890 offset = (args_size + cprestore_size + var_size
6891 + gp_reg_rounded + fp_reg_size
6892 - MAX_FPRS_PER_FMT * UNITS_PER_FPREG);
6893 cfun->machine->frame.fp_sp_offset = offset;
6894 cfun->machine->frame.fp_save_offset = offset - total_size;
6895 }
6896 else
6897 {
6898 cfun->machine->frame.fp_sp_offset = 0;
6899 cfun->machine->frame.fp_save_offset = 0;
6900 }
6901
6902 /* Ok, we're done. */
6903 return total_size;
6904 }
6905 \f
6906 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6907 pointer or argument pointer. TO is either the stack pointer or
6908 hard frame pointer. */
6909
6910 HOST_WIDE_INT
6911 mips_initial_elimination_offset (int from, int to)
6912 {
6913 HOST_WIDE_INT offset;
6914
6915 compute_frame_size (get_frame_size ());
6916
6917 /* Set OFFSET to the offset from the stack pointer. */
6918 switch (from)
6919 {
6920 case FRAME_POINTER_REGNUM:
6921 offset = 0;
6922 break;
6923
6924 case ARG_POINTER_REGNUM:
6925 offset = (cfun->machine->frame.total_size
6926 - current_function_pretend_args_size);
6927 break;
6928
6929 default:
6930 gcc_unreachable ();
6931 }
6932
6933 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6934 offset -= cfun->machine->frame.args_size;
6935
6936 return offset;
6937 }
6938 \f
6939 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6940 back to a previous frame. */
6941 rtx
6942 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6943 {
6944 if (count != 0)
6945 return const0_rtx;
6946
6947 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6948 }
6949 \f
6950 /* Use FN to save or restore register REGNO. MODE is the register's
6951 mode and OFFSET is the offset of its save slot from the current
6952 stack pointer. */
6953
6954 static void
6955 mips_save_restore_reg (enum machine_mode mode, int regno,
6956 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6957 {
6958 rtx mem;
6959
6960 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
6961
6962 fn (gen_rtx_REG (mode, regno), mem);
6963 }
6964
6965
6966 /* Call FN for each register that is saved by the current function.
6967 SP_OFFSET is the offset of the current stack pointer from the start
6968 of the frame. */
6969
6970 static void
6971 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6972 {
6973 enum machine_mode fpr_mode;
6974 HOST_WIDE_INT offset;
6975 int regno;
6976
6977 /* Save registers starting from high to low. The debuggers prefer at least
6978 the return register be stored at func+4, and also it allows us not to
6979 need a nop in the epilogue if at least one register is reloaded in
6980 addition to return address. */
6981 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6982 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6983 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6984 {
6985 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6986 offset -= GET_MODE_SIZE (gpr_mode);
6987 }
6988
6989 /* This loop must iterate over the same space as its companion in
6990 compute_frame_size. */
6991 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6992 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6993 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6994 regno >= FP_REG_FIRST;
6995 regno -= MAX_FPRS_PER_FMT)
6996 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6997 {
6998 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6999 offset -= GET_MODE_SIZE (fpr_mode);
7000 }
7001 }
7002 \f
7003 /* If we're generating n32 or n64 abicalls, and the current function
7004 does not use $28 as its global pointer, emit a cplocal directive.
7005 Use pic_offset_table_rtx as the argument to the directive. */
7006
7007 static void
7008 mips_output_cplocal (void)
7009 {
7010 if (!TARGET_EXPLICIT_RELOCS
7011 && cfun->machine->global_pointer > 0
7012 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
7013 output_asm_insn (".cplocal %+", 0);
7014 }
7015
7016 /* Return the style of GP load sequence that is being used for the
7017 current function. */
7018
7019 enum mips_loadgp_style
7020 mips_current_loadgp_style (void)
7021 {
7022 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
7023 return LOADGP_NONE;
7024
7025 if (TARGET_RTP_PIC)
7026 return LOADGP_RTP;
7027
7028 if (TARGET_ABSOLUTE_ABICALLS)
7029 return LOADGP_ABSOLUTE;
7030
7031 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
7032 }
7033
7034 /* The __gnu_local_gp symbol. */
7035
7036 static GTY(()) rtx mips_gnu_local_gp;
7037
7038 /* If we're generating n32 or n64 abicalls, emit instructions
7039 to set up the global pointer. */
7040
7041 static void
7042 mips_emit_loadgp (void)
7043 {
7044 rtx addr, offset, incoming_address, base, index;
7045
7046 switch (mips_current_loadgp_style ())
7047 {
7048 case LOADGP_ABSOLUTE:
7049 if (mips_gnu_local_gp == NULL)
7050 {
7051 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
7052 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
7053 }
7054 emit_insn (gen_loadgp_absolute (mips_gnu_local_gp));
7055 break;
7056
7057 case LOADGP_NEWABI:
7058 addr = XEXP (DECL_RTL (current_function_decl), 0);
7059 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
7060 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7061 emit_insn (gen_loadgp_newabi (offset, incoming_address));
7062 if (!TARGET_EXPLICIT_RELOCS)
7063 emit_insn (gen_loadgp_blockage ());
7064 break;
7065
7066 case LOADGP_RTP:
7067 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
7068 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
7069 emit_insn (gen_loadgp_rtp (base, index));
7070 if (!TARGET_EXPLICIT_RELOCS)
7071 emit_insn (gen_loadgp_blockage ());
7072 break;
7073
7074 default:
7075 break;
7076 }
7077 }
7078
7079 /* Set up the stack and frame (if desired) for the function. */
7080
7081 static void
7082 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7083 {
7084 const char *fnname;
7085 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
7086
7087 #ifdef SDB_DEBUGGING_INFO
7088 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
7089 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
7090 #endif
7091
7092 /* In mips16 mode, we may need to generate a 32 bit to handle
7093 floating point arguments. The linker will arrange for any 32-bit
7094 functions to call this stub, which will then jump to the 16-bit
7095 function proper. */
7096 if (mips16_hard_float
7097 && current_function_args_info.fp_code != 0)
7098 build_mips16_function_stub (file);
7099
7100 if (!FUNCTION_NAME_ALREADY_DECLARED)
7101 {
7102 /* Get the function name the same way that toplev.c does before calling
7103 assemble_start_function. This is needed so that the name used here
7104 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7105 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7106
7107 if (!flag_inhibit_size_directive)
7108 {
7109 fputs ("\t.ent\t", file);
7110 assemble_name (file, fnname);
7111 fputs ("\n", file);
7112 }
7113
7114 assemble_name (file, fnname);
7115 fputs (":\n", file);
7116 }
7117
7118 /* Stop mips_file_end from treating this function as external. */
7119 if (TARGET_IRIX && mips_abi == ABI_32)
7120 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
7121
7122 if (!flag_inhibit_size_directive)
7123 {
7124 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7125 fprintf (file,
7126 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
7127 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
7128 ", args= " HOST_WIDE_INT_PRINT_DEC
7129 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
7130 (reg_names[(frame_pointer_needed)
7131 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
7132 ((frame_pointer_needed && TARGET_MIPS16)
7133 ? tsize - cfun->machine->frame.args_size
7134 : tsize),
7135 reg_names[GP_REG_FIRST + 31],
7136 cfun->machine->frame.var_size,
7137 cfun->machine->frame.num_gp,
7138 cfun->machine->frame.num_fp,
7139 cfun->machine->frame.args_size,
7140 cfun->machine->frame.cprestore_size);
7141
7142 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7143 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
7144 cfun->machine->frame.mask,
7145 cfun->machine->frame.gp_save_offset);
7146 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
7147 cfun->machine->frame.fmask,
7148 cfun->machine->frame.fp_save_offset);
7149
7150 /* Require:
7151 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7152 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7153 }
7154
7155 if (mips_current_loadgp_style () == LOADGP_OLDABI)
7156 {
7157 /* Handle the initialization of $gp for SVR4 PIC. */
7158 if (!cfun->machine->all_noreorder_p)
7159 output_asm_insn ("%(.cpload\t%^%)", 0);
7160 else
7161 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
7162 }
7163 else if (cfun->machine->all_noreorder_p)
7164 output_asm_insn ("%(%<", 0);
7165
7166 /* Tell the assembler which register we're using as the global
7167 pointer. This is needed for thunks, since they can use either
7168 explicit relocs or assembler macros. */
7169 mips_output_cplocal ();
7170 }
7171 \f
7172 /* Make the last instruction frame related and note that it performs
7173 the operation described by FRAME_PATTERN. */
7174
7175 static void
7176 mips_set_frame_expr (rtx frame_pattern)
7177 {
7178 rtx insn;
7179
7180 insn = get_last_insn ();
7181 RTX_FRAME_RELATED_P (insn) = 1;
7182 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7183 frame_pattern,
7184 REG_NOTES (insn));
7185 }
7186
7187
7188 /* Return a frame-related rtx that stores REG at MEM.
7189 REG must be a single register. */
7190
7191 static rtx
7192 mips_frame_set (rtx mem, rtx reg)
7193 {
7194 rtx set;
7195
7196 /* If we're saving the return address register and the dwarf return
7197 address column differs from the hard register number, adjust the
7198 note reg to refer to the former. */
7199 if (REGNO (reg) == GP_REG_FIRST + 31
7200 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7201 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7202
7203 set = gen_rtx_SET (VOIDmode, mem, reg);
7204 RTX_FRAME_RELATED_P (set) = 1;
7205
7206 return set;
7207 }
7208
7209
7210 /* Save register REG to MEM. Make the instruction frame-related. */
7211
7212 static void
7213 mips_save_reg (rtx reg, rtx mem)
7214 {
7215 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
7216 {
7217 rtx x1, x2;
7218
7219 if (mips_split_64bit_move_p (mem, reg))
7220 mips_split_64bit_move (mem, reg);
7221 else
7222 emit_move_insn (mem, reg);
7223
7224 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
7225 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
7226 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
7227 }
7228 else
7229 {
7230 if (TARGET_MIPS16
7231 && REGNO (reg) != GP_REG_FIRST + 31
7232 && !M16_REG_P (REGNO (reg)))
7233 {
7234 /* Save a non-mips16 register by moving it through a temporary.
7235 We don't need to do this for $31 since there's a special
7236 instruction for it. */
7237 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
7238 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
7239 }
7240 else
7241 emit_move_insn (mem, reg);
7242
7243 mips_set_frame_expr (mips_frame_set (mem, reg));
7244 }
7245 }
7246
7247 /* Return a move between register REGNO and memory location SP + OFFSET.
7248 Make the move a load if RESTORE_P, otherwise make it a frame-related
7249 store. */
7250
7251 static rtx
7252 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7253 unsigned int regno)
7254 {
7255 rtx reg, mem;
7256
7257 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7258 reg = gen_rtx_REG (SImode, regno);
7259 return (restore_p
7260 ? gen_rtx_SET (VOIDmode, reg, mem)
7261 : mips_frame_set (mem, reg));
7262 }
7263
7264 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7265 The instruction must:
7266
7267 - Allocate or deallocate SIZE bytes in total; SIZE is known
7268 to be nonzero.
7269
7270 - Save or restore as many registers in *MASK_PTR as possible.
7271 The instruction saves the first registers at the top of the
7272 allocated area, with the other registers below it.
7273
7274 - Save NARGS argument registers above the allocated area.
7275
7276 (NARGS is always zero if RESTORE_P.)
7277
7278 The SAVE and RESTORE instructions cannot save and restore all general
7279 registers, so there may be some registers left over for the caller to
7280 handle. Destructively modify *MASK_PTR so that it contains the registers
7281 that still need to be saved or restored. The caller can save these
7282 registers in the memory immediately below *OFFSET_PTR, which is a
7283 byte offset from the bottom of the allocated stack area. */
7284
7285 static rtx
7286 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7287 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7288 HOST_WIDE_INT size)
7289 {
7290 rtx pattern, set;
7291 HOST_WIDE_INT offset, top_offset;
7292 unsigned int i, regno;
7293 int n;
7294
7295 gcc_assert (cfun->machine->frame.fp_reg_size == 0);
7296
7297 /* Calculate the number of elements in the PARALLEL. We need one element
7298 for the stack adjustment, one for each argument register save, and one
7299 for each additional register move. */
7300 n = 1 + nargs;
7301 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7302 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7303 n++;
7304
7305 /* Create the final PARALLEL. */
7306 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7307 n = 0;
7308
7309 /* Add the stack pointer adjustment. */
7310 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7311 plus_constant (stack_pointer_rtx,
7312 restore_p ? size : -size));
7313 RTX_FRAME_RELATED_P (set) = 1;
7314 XVECEXP (pattern, 0, n++) = set;
7315
7316 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7317 top_offset = restore_p ? size : 0;
7318
7319 /* Save the arguments. */
7320 for (i = 0; i < nargs; i++)
7321 {
7322 offset = top_offset + i * GET_MODE_SIZE (gpr_mode);
7323 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7324 XVECEXP (pattern, 0, n++) = set;
7325 }
7326
7327 /* Then fill in the other register moves. */
7328 offset = top_offset;
7329 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7330 {
7331 regno = mips16e_save_restore_regs[i];
7332 if (BITSET_P (*mask_ptr, regno))
7333 {
7334 offset -= UNITS_PER_WORD;
7335 set = mips16e_save_restore_reg (restore_p, offset, regno);
7336 XVECEXP (pattern, 0, n++) = set;
7337 *mask_ptr &= ~(1 << regno);
7338 }
7339 }
7340
7341 /* Tell the caller what offset it should use for the remaining registers. */
7342 *offset_ptr = size + (offset - top_offset) + size;
7343
7344 gcc_assert (n == XVECLEN (pattern, 0));
7345
7346 return pattern;
7347 }
7348
7349 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7350 pointer. Return true if PATTERN matches the kind of instruction
7351 generated by mips16e_build_save_restore. If INFO is nonnull,
7352 initialize it when returning true. */
7353
7354 bool
7355 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7356 struct mips16e_save_restore_info *info)
7357 {
7358 unsigned int i, nargs, mask;
7359 HOST_WIDE_INT top_offset, save_offset, offset, extra;
7360 rtx set, reg, mem, base;
7361 int n;
7362
7363 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7364 return false;
7365
7366 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7367 top_offset = adjust > 0 ? adjust : 0;
7368
7369 /* Interpret all other members of the PARALLEL. */
7370 save_offset = top_offset - GET_MODE_SIZE (gpr_mode);
7371 mask = 0;
7372 nargs = 0;
7373 i = 0;
7374 for (n = 1; n < XVECLEN (pattern, 0); n++)
7375 {
7376 /* Check that we have a SET. */
7377 set = XVECEXP (pattern, 0, n);
7378 if (GET_CODE (set) != SET)
7379 return false;
7380
7381 /* Check that the SET is a load (if restoring) or a store
7382 (if saving). */
7383 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7384 if (!MEM_P (mem))
7385 return false;
7386
7387 /* Check that the address is the sum of the stack pointer and a
7388 possibly-zero constant offset. */
7389 mips_split_plus (XEXP (mem, 0), &base, &offset);
7390 if (base != stack_pointer_rtx)
7391 return false;
7392
7393 /* Check that SET's other operand is a register. */
7394 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7395 if (!REG_P (reg))
7396 return false;
7397
7398 /* Check for argument saves. */
7399 if (offset == top_offset + nargs * GET_MODE_SIZE (gpr_mode)
7400 && REGNO (reg) == GP_ARG_FIRST + nargs)
7401 nargs++;
7402 else if (offset == save_offset)
7403 {
7404 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7405 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7406 return false;
7407
7408 mask |= 1 << REGNO (reg);
7409 save_offset -= GET_MODE_SIZE (gpr_mode);
7410 }
7411 else
7412 return false;
7413 }
7414
7415 /* Check that the restrictions on register ranges are met. */
7416 extra = 0;
7417 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7418 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7419 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7420 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7421 if (extra != 0)
7422 return false;
7423
7424 /* Make sure that the topmost argument register is not saved twice.
7425 The checks above ensure that the same is then true for the other
7426 argument registers. */
7427 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7428 return false;
7429
7430 /* Pass back information, if requested. */
7431 if (info)
7432 {
7433 info->nargs = nargs;
7434 info->mask = mask;
7435 info->size = (adjust > 0 ? adjust : -adjust);
7436 }
7437
7438 return true;
7439 }
7440
7441 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7442 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7443 the null terminator. */
7444
7445 static char *
7446 mips16e_add_register_range (char *s, unsigned int min_reg,
7447 unsigned int max_reg)
7448 {
7449 if (min_reg != max_reg)
7450 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7451 else
7452 s += sprintf (s, ",%s", reg_names[min_reg]);
7453 return s;
7454 }
7455
7456 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7457 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7458
7459 const char *
7460 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7461 {
7462 static char buffer[300];
7463
7464 struct mips16e_save_restore_info info;
7465 unsigned int i, end;
7466 char *s;
7467
7468 /* Parse the pattern. */
7469 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7470 gcc_unreachable ();
7471
7472 /* Add the mnemonic. */
7473 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7474 s += strlen (s);
7475
7476 /* Save the arguments. */
7477 if (info.nargs > 1)
7478 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7479 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7480 else if (info.nargs == 1)
7481 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7482
7483 /* Emit the amount of stack space to allocate or deallocate. */
7484 s += sprintf (s, "%d", (int) info.size);
7485
7486 /* Save or restore $16. */
7487 if (BITSET_P (info.mask, 16))
7488 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7489
7490 /* Save or restore $17. */
7491 if (BITSET_P (info.mask, 17))
7492 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7493
7494 /* Save or restore registers in the range $s2...$s8, which
7495 mips16e_s2_s8_regs lists in decreasing order. Note that this
7496 is a software register range; the hardware registers are not
7497 numbered consecutively. */
7498 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7499 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7500 if (i < end)
7501 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7502 mips16e_s2_s8_regs[i]);
7503
7504 /* Save or restore registers in the range $a0...$a3. */
7505 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7506 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7507 if (i < end)
7508 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7509 mips16e_a0_a3_regs[end - 1]);
7510
7511 /* Save or restore $31. */
7512 if (BITSET_P (info.mask, 31))
7513 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7514
7515 return buffer;
7516 }
7517
7518 /* Return a simplified form of X using the register values in REG_VALUES.
7519 REG_VALUES[R] is the last value assigned to hard register R, or null
7520 if R has not been modified.
7521
7522 This function is rather limited, but is good enough for our purposes. */
7523
7524 static rtx
7525 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7526 {
7527 rtx x0, x1;
7528
7529 x = avoid_constant_pool_reference (x);
7530
7531 if (UNARY_P (x))
7532 {
7533 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7534 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7535 x0, GET_MODE (XEXP (x, 0)));
7536 }
7537
7538 if (ARITHMETIC_P (x))
7539 {
7540 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7541 x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7542 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7543 }
7544
7545 if (REG_P (x)
7546 && reg_values[REGNO (x)]
7547 && !rtx_unstable_p (reg_values[REGNO (x)]))
7548 return reg_values[REGNO (x)];
7549
7550 return x;
7551 }
7552
7553 /* Return true if (set DEST SRC) stores an argument register into its
7554 caller-allocated save slot, storing the number of that argument
7555 register in *REGNO_PTR if so. REG_VALUES is as for
7556 mips16e_collect_propagate_value. */
7557
7558 static bool
7559 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7560 unsigned int *regno_ptr)
7561 {
7562 unsigned int argno, regno;
7563 HOST_WIDE_INT offset, required_offset;
7564 rtx addr, base;
7565
7566 /* Check that this is a word-mode store. */
7567 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7568 return false;
7569
7570 /* Check that the register being saved is an unmodified argument
7571 register. */
7572 regno = REGNO (src);
7573 if (regno < GP_ARG_FIRST || regno > GP_ARG_LAST || reg_values[regno])
7574 return false;
7575 argno = regno - GP_ARG_FIRST;
7576
7577 /* Check whether the address is an appropriate stack pointer or
7578 frame pointer access. The frame pointer is offset from the
7579 stack pointer by the size of the outgoing arguments. */
7580 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7581 mips_split_plus (addr, &base, &offset);
7582 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7583 if (base == hard_frame_pointer_rtx)
7584 required_offset -= cfun->machine->frame.args_size;
7585 else if (base != stack_pointer_rtx)
7586 return false;
7587 if (offset != required_offset)
7588 return false;
7589
7590 *regno_ptr = regno;
7591 return true;
7592 }
7593
7594 /* A subroutine of mips_expand_prologue, called only when generating
7595 MIPS16e SAVE instructions. Search the start of the function for any
7596 instructions that save argument registers into their caller-allocated
7597 save slots. Delete such instructions and return a value N such that
7598 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7599 instructions redundant. */
7600
7601 static unsigned int
7602 mips16e_collect_argument_saves (void)
7603 {
7604 rtx reg_values[FIRST_PSEUDO_REGISTER];
7605 rtx insn, next, set, dest, src;
7606 unsigned int nargs, regno;
7607
7608 push_topmost_sequence ();
7609 nargs = 0;
7610 memset (reg_values, 0, sizeof (reg_values));
7611 for (insn = get_insns (); insn; insn = next)
7612 {
7613 next = NEXT_INSN (insn);
7614 if (NOTE_P (insn))
7615 continue;
7616
7617 if (!INSN_P (insn))
7618 break;
7619
7620 set = PATTERN (insn);
7621 if (GET_CODE (set) != SET)
7622 break;
7623
7624 dest = SET_DEST (set);
7625 src = SET_SRC (set);
7626 if (mips16e_collect_argument_save_p (dest, src, reg_values, &regno))
7627 {
7628 if (!BITSET_P (cfun->machine->frame.mask, regno))
7629 {
7630 delete_insn (insn);
7631 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7632 }
7633 }
7634 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7635 reg_values[REGNO (dest)]
7636 = mips16e_collect_propagate_value (src, reg_values);
7637 else
7638 break;
7639 }
7640 pop_topmost_sequence ();
7641
7642 return nargs;
7643 }
7644
7645 /* Expand the prologue into a bunch of separate insns. */
7646
7647 void
7648 mips_expand_prologue (void)
7649 {
7650 HOST_WIDE_INT size;
7651 unsigned int nargs;
7652 rtx insn;
7653
7654 if (cfun->machine->global_pointer > 0)
7655 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
7656
7657 size = compute_frame_size (get_frame_size ());
7658
7659 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
7660 bytes beforehand; this is enough to cover the register save area
7661 without going out of range. */
7662 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7663 {
7664 HOST_WIDE_INT step1;
7665
7666 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
7667
7668 if (GENERATE_MIPS16E_SAVE_RESTORE)
7669 {
7670 HOST_WIDE_INT offset;
7671 unsigned int mask, regno;
7672
7673 /* Try to merge argument stores into the save instruction. */
7674 nargs = mips16e_collect_argument_saves ();
7675
7676 /* Build the save instruction. */
7677 mask = cfun->machine->frame.mask;
7678 insn = mips16e_build_save_restore (false, &mask, &offset,
7679 nargs, step1);
7680 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
7681 size -= step1;
7682
7683 /* Check if we need to save other registers. */
7684 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
7685 if (BITSET_P (mask, regno - GP_REG_FIRST))
7686 {
7687 offset -= GET_MODE_SIZE (gpr_mode);
7688 mips_save_restore_reg (gpr_mode, regno, offset, mips_save_reg);
7689 }
7690 }
7691 else
7692 {
7693 insn = gen_add3_insn (stack_pointer_rtx,
7694 stack_pointer_rtx,
7695 GEN_INT (-step1));
7696 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
7697 size -= step1;
7698 mips_for_each_saved_reg (size, mips_save_reg);
7699 }
7700 }
7701
7702 /* Allocate the rest of the frame. */
7703 if (size > 0)
7704 {
7705 if (SMALL_OPERAND (-size))
7706 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
7707 stack_pointer_rtx,
7708 GEN_INT (-size)))) = 1;
7709 else
7710 {
7711 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
7712 if (TARGET_MIPS16)
7713 {
7714 /* There are no instructions to add or subtract registers
7715 from the stack pointer, so use the frame pointer as a
7716 temporary. We should always be using a frame pointer
7717 in this case anyway. */
7718 gcc_assert (frame_pointer_needed);
7719 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7720 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
7721 hard_frame_pointer_rtx,
7722 MIPS_PROLOGUE_TEMP (Pmode)));
7723 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7724 }
7725 else
7726 emit_insn (gen_sub3_insn (stack_pointer_rtx,
7727 stack_pointer_rtx,
7728 MIPS_PROLOGUE_TEMP (Pmode)));
7729
7730 /* Describe the combined effect of the previous instructions. */
7731 mips_set_frame_expr
7732 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7733 plus_constant (stack_pointer_rtx, -size)));
7734 }
7735 }
7736
7737 /* Set up the frame pointer, if we're using one. In mips16 code,
7738 we point the frame pointer ahead of the outgoing argument area.
7739 This should allow more variables & incoming arguments to be
7740 accessed with unextended instructions. */
7741 if (frame_pointer_needed)
7742 {
7743 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
7744 {
7745 rtx offset = GEN_INT (cfun->machine->frame.args_size);
7746 if (SMALL_OPERAND (cfun->machine->frame.args_size))
7747 RTX_FRAME_RELATED_P
7748 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7749 stack_pointer_rtx,
7750 offset))) = 1;
7751 else
7752 {
7753 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
7754 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7755 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7756 hard_frame_pointer_rtx,
7757 MIPS_PROLOGUE_TEMP (Pmode)));
7758 mips_set_frame_expr
7759 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
7760 plus_constant (stack_pointer_rtx,
7761 cfun->machine->frame.args_size)));
7762 }
7763 }
7764 else
7765 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
7766 stack_pointer_rtx)) = 1;
7767 }
7768
7769 mips_emit_loadgp ();
7770
7771 /* If generating o32/o64 abicalls, save $gp on the stack. */
7772 if (TARGET_ABICALLS && TARGET_OLDABI && !current_function_is_leaf)
7773 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
7774
7775 /* If we are profiling, make sure no instructions are scheduled before
7776 the call to mcount. */
7777
7778 if (current_function_profile)
7779 emit_insn (gen_blockage ());
7780 }
7781 \f
7782 /* Do any necessary cleanup after a function to restore stack, frame,
7783 and regs. */
7784
7785 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7786
7787 static void
7788 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7789 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7790 {
7791 /* Reinstate the normal $gp. */
7792 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
7793 mips_output_cplocal ();
7794
7795 if (cfun->machine->all_noreorder_p)
7796 {
7797 /* Avoid using %>%) since it adds excess whitespace. */
7798 output_asm_insn (".set\tmacro", 0);
7799 output_asm_insn (".set\treorder", 0);
7800 set_noreorder = set_nomacro = 0;
7801 }
7802
7803 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
7804 {
7805 const char *fnname;
7806
7807 /* Get the function name the same way that toplev.c does before calling
7808 assemble_start_function. This is needed so that the name used here
7809 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7810 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7811 fputs ("\t.end\t", file);
7812 assemble_name (file, fnname);
7813 fputs ("\n", file);
7814 }
7815 }
7816 \f
7817 /* Emit instructions to restore register REG from slot MEM. */
7818
7819 static void
7820 mips_restore_reg (rtx reg, rtx mem)
7821 {
7822 /* There's no mips16 instruction to load $31 directly. Load into
7823 $7 instead and adjust the return insn appropriately. */
7824 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
7825 reg = gen_rtx_REG (GET_MODE (reg), 7);
7826
7827 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
7828 {
7829 /* Can't restore directly; move through a temporary. */
7830 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
7831 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
7832 }
7833 else
7834 emit_move_insn (reg, mem);
7835 }
7836
7837
7838 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
7839 if this epilogue precedes a sibling call, false if it is for a normal
7840 "epilogue" pattern. */
7841
7842 void
7843 mips_expand_epilogue (int sibcall_p)
7844 {
7845 HOST_WIDE_INT step1, step2;
7846 rtx base, target;
7847
7848 if (!sibcall_p && mips_can_use_return_insn ())
7849 {
7850 emit_jump_insn (gen_return ());
7851 return;
7852 }
7853
7854 /* In mips16 mode, if the return value should go into a floating-point
7855 register, we need to call a helper routine to copy it over. */
7856 if (mips16_cfun_returns_in_fpr_p ())
7857 {
7858 char *name;
7859 rtx func;
7860 rtx insn;
7861 rtx retval;
7862 rtx call;
7863 tree id;
7864 tree return_type;
7865 enum machine_mode return_mode;
7866
7867 return_type = DECL_RESULT (current_function_decl);
7868 return_mode = DECL_MODE (return_type);
7869
7870 name = ACONCAT (("__mips16_ret_",
7871 mips16_call_stub_mode_suffix (return_mode),
7872 NULL));
7873 id = get_identifier (name);
7874 func = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7875 retval = gen_rtx_REG (return_mode, GP_RETURN);
7876 call = gen_call_value_internal (retval, func, const0_rtx);
7877 insn = emit_call_insn (call);
7878 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
7879 }
7880
7881 /* Split the frame into two. STEP1 is the amount of stack we should
7882 deallocate before restoring the registers. STEP2 is the amount we
7883 should deallocate afterwards.
7884
7885 Start off by assuming that no registers need to be restored. */
7886 step1 = cfun->machine->frame.total_size;
7887 step2 = 0;
7888
7889 /* Work out which register holds the frame address. Account for the
7890 frame pointer offset used by mips16 code. */
7891 if (!frame_pointer_needed)
7892 base = stack_pointer_rtx;
7893 else
7894 {
7895 base = hard_frame_pointer_rtx;
7896 if (TARGET_MIPS16)
7897 step1 -= cfun->machine->frame.args_size;
7898 }
7899
7900 /* If we need to restore registers, deallocate as much stack as
7901 possible in the second step without going out of range. */
7902 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7903 {
7904 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7905 step1 -= step2;
7906 }
7907
7908 /* Set TARGET to BASE + STEP1. */
7909 target = base;
7910 if (step1 > 0)
7911 {
7912 rtx adjust;
7913
7914 /* Get an rtx for STEP1 that we can add to BASE. */
7915 adjust = GEN_INT (step1);
7916 if (!SMALL_OPERAND (step1))
7917 {
7918 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7919 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7920 }
7921
7922 /* Normal mode code can copy the result straight into $sp. */
7923 if (!TARGET_MIPS16)
7924 target = stack_pointer_rtx;
7925
7926 emit_insn (gen_add3_insn (target, base, adjust));
7927 }
7928
7929 /* Copy TARGET into the stack pointer. */
7930 if (target != stack_pointer_rtx)
7931 emit_move_insn (stack_pointer_rtx, target);
7932
7933 /* If we're using addressing macros, $gp is implicitly used by all
7934 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
7935 from the stack. */
7936 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
7937 emit_insn (gen_blockage ());
7938
7939 if (GENERATE_MIPS16E_SAVE_RESTORE && cfun->machine->frame.mask != 0)
7940 {
7941 unsigned int regno, mask;
7942 HOST_WIDE_INT offset;
7943 rtx restore;
7944
7945 /* Generate the restore instruction. */
7946 mask = cfun->machine->frame.mask;
7947 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
7948
7949 /* Restore any other registers manually. */
7950 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
7951 if (BITSET_P (mask, regno - GP_REG_FIRST))
7952 {
7953 offset -= GET_MODE_SIZE (gpr_mode);
7954 mips_save_restore_reg (gpr_mode, regno, offset, mips_restore_reg);
7955 }
7956
7957 /* Restore the remaining registers and deallocate the final bit
7958 of the frame. */
7959 emit_insn (restore);
7960 }
7961 else
7962 {
7963 /* Restore the registers. */
7964 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7965 mips_restore_reg);
7966
7967 /* Deallocate the final bit of the frame. */
7968 if (step2 > 0)
7969 emit_insn (gen_add3_insn (stack_pointer_rtx,
7970 stack_pointer_rtx,
7971 GEN_INT (step2)));
7972 }
7973
7974 /* Add in the __builtin_eh_return stack adjustment. We need to
7975 use a temporary in mips16 code. */
7976 if (current_function_calls_eh_return)
7977 {
7978 if (TARGET_MIPS16)
7979 {
7980 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7981 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7982 MIPS_EPILOGUE_TEMP (Pmode),
7983 EH_RETURN_STACKADJ_RTX));
7984 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7985 }
7986 else
7987 emit_insn (gen_add3_insn (stack_pointer_rtx,
7988 stack_pointer_rtx,
7989 EH_RETURN_STACKADJ_RTX));
7990 }
7991
7992 if (!sibcall_p)
7993 {
7994 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
7995 path will restore the return address into $7 rather than $31. */
7996 if (TARGET_MIPS16
7997 && !GENERATE_MIPS16E_SAVE_RESTORE
7998 && (cfun->machine->frame.mask & RA_MASK) != 0)
7999 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
8000 GP_REG_FIRST + 7)));
8001 else
8002 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
8003 GP_REG_FIRST + 31)));
8004 }
8005 }
8006 \f
8007 /* Return nonzero if this function is known to have a null epilogue.
8008 This allows the optimizer to omit jumps to jumps if no stack
8009 was created. */
8010
8011 int
8012 mips_can_use_return_insn (void)
8013 {
8014 if (! reload_completed)
8015 return 0;
8016
8017 if (df_regs_ever_live_p (31) || current_function_profile)
8018 return 0;
8019
8020 /* In mips16 mode, a function that returns a floating point value
8021 needs to arrange to copy the return value into the floating point
8022 registers. */
8023 if (mips16_cfun_returns_in_fpr_p ())
8024 return 0;
8025
8026 if (cfun->machine->frame.initialized)
8027 return cfun->machine->frame.total_size == 0;
8028
8029 return compute_frame_size (get_frame_size ()) == 0;
8030 }
8031 \f
8032 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
8033 in order to avoid duplicating too much logic from elsewhere. */
8034
8035 static void
8036 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8037 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8038 tree function)
8039 {
8040 rtx this, temp1, temp2, insn, fnaddr;
8041
8042 /* Pretend to be a post-reload pass while generating rtl. */
8043 reload_completed = 1;
8044
8045 /* Mark the end of the (empty) prologue. */
8046 emit_note (NOTE_INSN_PROLOGUE_END);
8047
8048 /* Pick a global pointer. Use a call-clobbered register if
8049 TARGET_CALL_SAVED_GP, so that we can use a sibcall. */
8050 if (TARGET_USE_GOT)
8051 {
8052 cfun->machine->global_pointer =
8053 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
8054
8055 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
8056
8057 }
8058
8059 /* Set up the global pointer for n32 or n64 abicalls. If
8060 LOADGP_ABSOLUTE then the thunk does not use the gp and there is
8061 no need to load it.*/
8062 if (mips_current_loadgp_style () != LOADGP_ABSOLUTE
8063 || !targetm.binds_local_p (function))
8064 mips_emit_loadgp ();
8065
8066 /* We need two temporary registers in some cases. */
8067 temp1 = gen_rtx_REG (Pmode, 2);
8068 temp2 = gen_rtx_REG (Pmode, 3);
8069
8070 /* Find out which register contains the "this" pointer. */
8071 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8072 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
8073 else
8074 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
8075
8076 /* Add DELTA to THIS. */
8077 if (delta != 0)
8078 {
8079 rtx offset = GEN_INT (delta);
8080 if (!SMALL_OPERAND (delta))
8081 {
8082 emit_move_insn (temp1, offset);
8083 offset = temp1;
8084 }
8085 emit_insn (gen_add3_insn (this, this, offset));
8086 }
8087
8088 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
8089 if (vcall_offset != 0)
8090 {
8091 rtx addr;
8092
8093 /* Set TEMP1 to *THIS. */
8094 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
8095
8096 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
8097 addr = mips_add_offset (temp2, temp1, vcall_offset);
8098
8099 /* Load the offset and add it to THIS. */
8100 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
8101 emit_insn (gen_add3_insn (this, this, temp1));
8102 }
8103
8104 /* Jump to the target function. Use a sibcall if direct jumps are
8105 allowed, otherwise load the address into a register first. */
8106 fnaddr = XEXP (DECL_RTL (function), 0);
8107 if (TARGET_MIPS16 || TARGET_USE_GOT || SYMBOL_REF_LONG_CALL_P (fnaddr))
8108 {
8109 /* This is messy. gas treats "la $25,foo" as part of a call
8110 sequence and may allow a global "foo" to be lazily bound.
8111 The general move patterns therefore reject this combination.
8112
8113 In this context, lazy binding would actually be OK
8114 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
8115 TARGET_CALL_SAVED_GP; see mips_load_call_address.
8116 We must therefore load the address via a temporary
8117 register if mips_dangerous_for_la25_p.
8118
8119 If we jump to the temporary register rather than $25, the assembler
8120 can use the move insn to fill the jump's delay slot. */
8121 if (TARGET_USE_PIC_FN_ADDR_REG
8122 && !mips_dangerous_for_la25_p (fnaddr))
8123 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8124 mips_load_call_address (temp1, fnaddr, true);
8125
8126 if (TARGET_USE_PIC_FN_ADDR_REG
8127 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
8128 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
8129 emit_jump_insn (gen_indirect_jump (temp1));
8130 }
8131 else
8132 {
8133 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
8134 SIBLING_CALL_P (insn) = 1;
8135 }
8136
8137 /* Run just enough of rest_of_compilation. This sequence was
8138 "borrowed" from alpha.c. */
8139 insn = get_insns ();
8140 insn_locators_alloc ();
8141 split_all_insns_noflow ();
8142 if (TARGET_MIPS16)
8143 mips16_lay_out_constants ();
8144 shorten_branches (insn);
8145 final_start_function (insn, file, 1);
8146 final (insn, file, 1);
8147 final_end_function ();
8148
8149 /* Clean up the vars set above. Note that final_end_function resets
8150 the global pointer for us. */
8151 reload_completed = 0;
8152 }
8153 \f
8154 /* Returns nonzero if X contains a SYMBOL_REF. */
8155
8156 static int
8157 symbolic_expression_p (rtx x)
8158 {
8159 if (GET_CODE (x) == SYMBOL_REF)
8160 return 1;
8161
8162 if (GET_CODE (x) == CONST)
8163 return symbolic_expression_p (XEXP (x, 0));
8164
8165 if (UNARY_P (x))
8166 return symbolic_expression_p (XEXP (x, 0));
8167
8168 if (ARITHMETIC_P (x))
8169 return (symbolic_expression_p (XEXP (x, 0))
8170 || symbolic_expression_p (XEXP (x, 1)));
8171
8172 return 0;
8173 }
8174
8175 /* Choose the section to use for the constant rtx expression X that has
8176 mode MODE. */
8177
8178 static section *
8179 mips_select_rtx_section (enum machine_mode mode, rtx x,
8180 unsigned HOST_WIDE_INT align)
8181 {
8182 if (TARGET_MIPS16)
8183 {
8184 /* In mips16 mode, the constant table always goes in the same section
8185 as the function, so that constants can be loaded using PC relative
8186 addressing. */
8187 return function_section (current_function_decl);
8188 }
8189 else if (TARGET_EMBEDDED_DATA)
8190 {
8191 /* For embedded applications, always put constants in read-only data,
8192 in order to reduce RAM usage. */
8193 return mergeable_constant_section (mode, align, 0);
8194 }
8195 else
8196 {
8197 /* For hosted applications, always put constants in small data if
8198 possible, as this gives the best performance. */
8199 /* ??? Consider using mergeable small data sections. */
8200
8201 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
8202 && mips_section_threshold > 0)
8203 return get_named_section (NULL, ".sdata", 0);
8204 else if (flag_pic && symbolic_expression_p (x))
8205 return get_named_section (NULL, ".data.rel.ro", 3);
8206 else
8207 return mergeable_constant_section (mode, align, 0);
8208 }
8209 }
8210
8211 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8212
8213 The complication here is that, with the combination TARGET_ABICALLS
8214 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
8215 therefore not be included in the read-only part of a DSO. Handle such
8216 cases by selecting a normal data section instead of a read-only one.
8217 The logic apes that in default_function_rodata_section. */
8218
8219 static section *
8220 mips_function_rodata_section (tree decl)
8221 {
8222 if (!TARGET_ABICALLS || TARGET_GPWORD)
8223 return default_function_rodata_section (decl);
8224
8225 if (decl && DECL_SECTION_NAME (decl))
8226 {
8227 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8228 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8229 {
8230 char *rname = ASTRDUP (name);
8231 rname[14] = 'd';
8232 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8233 }
8234 else if (flag_function_sections && flag_data_sections
8235 && strncmp (name, ".text.", 6) == 0)
8236 {
8237 char *rname = ASTRDUP (name);
8238 memcpy (rname + 1, "data", 4);
8239 return get_section (rname, SECTION_WRITE, decl);
8240 }
8241 }
8242 return data_section;
8243 }
8244
8245 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
8246 locally-defined objects go in a small data section. It also controls
8247 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
8248 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
8249
8250 static bool
8251 mips_in_small_data_p (tree decl)
8252 {
8253 HOST_WIDE_INT size;
8254
8255 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8256 return false;
8257
8258 /* We don't yet generate small-data references for -mabicalls or
8259 VxWorks RTP code. See the related -G handling in override_options. */
8260 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8261 return false;
8262
8263 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8264 {
8265 const char *name;
8266
8267 /* Reject anything that isn't in a known small-data section. */
8268 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8269 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8270 return false;
8271
8272 /* If a symbol is defined externally, the assembler will use the
8273 usual -G rules when deciding how to implement macros. */
8274 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
8275 return true;
8276 }
8277 else if (TARGET_EMBEDDED_DATA)
8278 {
8279 /* Don't put constants into the small data section: we want them
8280 to be in ROM rather than RAM. */
8281 if (TREE_CODE (decl) != VAR_DECL)
8282 return false;
8283
8284 if (TREE_READONLY (decl)
8285 && !TREE_SIDE_EFFECTS (decl)
8286 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8287 return false;
8288 }
8289
8290 size = int_size_in_bytes (TREE_TYPE (decl));
8291 return (size > 0 && size <= mips_section_threshold);
8292 }
8293
8294 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8295 anchors for small data: the GP register acts as an anchor in that
8296 case. We also don't want to use them for PC-relative accesses,
8297 where the PC acts as an anchor. */
8298
8299 static bool
8300 mips_use_anchors_for_symbol_p (rtx symbol)
8301 {
8302 switch (mips_classify_symbol (symbol))
8303 {
8304 case SYMBOL_CONSTANT_POOL:
8305 case SYMBOL_SMALL_DATA:
8306 return false;
8307
8308 default:
8309 return true;
8310 }
8311 }
8312 \f
8313 /* See whether VALTYPE is a record whose fields should be returned in
8314 floating-point registers. If so, return the number of fields and
8315 list them in FIELDS (which should have two elements). Return 0
8316 otherwise.
8317
8318 For n32 & n64, a structure with one or two fields is returned in
8319 floating-point registers as long as every field has a floating-point
8320 type. */
8321
8322 static int
8323 mips_fpr_return_fields (tree valtype, tree *fields)
8324 {
8325 tree field;
8326 int i;
8327
8328 if (!TARGET_NEWABI)
8329 return 0;
8330
8331 if (TREE_CODE (valtype) != RECORD_TYPE)
8332 return 0;
8333
8334 i = 0;
8335 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
8336 {
8337 if (TREE_CODE (field) != FIELD_DECL)
8338 continue;
8339
8340 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
8341 return 0;
8342
8343 if (i == 2)
8344 return 0;
8345
8346 fields[i++] = field;
8347 }
8348 return i;
8349 }
8350
8351
8352 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
8353 a value in the most significant part of $2/$3 if:
8354
8355 - the target is big-endian;
8356
8357 - the value has a structure or union type (we generalize this to
8358 cover aggregates from other languages too); and
8359
8360 - the structure is not returned in floating-point registers. */
8361
8362 static bool
8363 mips_return_in_msb (tree valtype)
8364 {
8365 tree fields[2];
8366
8367 return (TARGET_NEWABI
8368 && TARGET_BIG_ENDIAN
8369 && AGGREGATE_TYPE_P (valtype)
8370 && mips_fpr_return_fields (valtype, fields) == 0);
8371 }
8372
8373
8374 /* Return a composite value in a pair of floating-point registers.
8375 MODE1 and OFFSET1 are the mode and byte offset for the first value,
8376 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
8377 complete value.
8378
8379 For n32 & n64, $f0 always holds the first value and $f2 the second.
8380 Otherwise the values are packed together as closely as possible. */
8381
8382 static rtx
8383 mips_return_fpr_pair (enum machine_mode mode,
8384 enum machine_mode mode1, HOST_WIDE_INT offset1,
8385 enum machine_mode mode2, HOST_WIDE_INT offset2)
8386 {
8387 int inc;
8388
8389 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
8390 return gen_rtx_PARALLEL
8391 (mode,
8392 gen_rtvec (2,
8393 gen_rtx_EXPR_LIST (VOIDmode,
8394 gen_rtx_REG (mode1, FP_RETURN),
8395 GEN_INT (offset1)),
8396 gen_rtx_EXPR_LIST (VOIDmode,
8397 gen_rtx_REG (mode2, FP_RETURN + inc),
8398 GEN_INT (offset2))));
8399
8400 }
8401
8402
8403 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
8404 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
8405 VALTYPE is null and MODE is the mode of the return value. */
8406
8407 rtx
8408 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
8409 enum machine_mode mode)
8410 {
8411 if (valtype)
8412 {
8413 tree fields[2];
8414 int unsignedp;
8415
8416 mode = TYPE_MODE (valtype);
8417 unsignedp = TYPE_UNSIGNED (valtype);
8418
8419 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
8420 true, we must promote the mode just as PROMOTE_MODE does. */
8421 mode = promote_mode (valtype, mode, &unsignedp, 1);
8422
8423 /* Handle structures whose fields are returned in $f0/$f2. */
8424 switch (mips_fpr_return_fields (valtype, fields))
8425 {
8426 case 1:
8427 return gen_rtx_REG (mode, FP_RETURN);
8428
8429 case 2:
8430 return mips_return_fpr_pair (mode,
8431 TYPE_MODE (TREE_TYPE (fields[0])),
8432 int_byte_position (fields[0]),
8433 TYPE_MODE (TREE_TYPE (fields[1])),
8434 int_byte_position (fields[1]));
8435 }
8436
8437 /* If a value is passed in the most significant part of a register, see
8438 whether we have to round the mode up to a whole number of words. */
8439 if (mips_return_in_msb (valtype))
8440 {
8441 HOST_WIDE_INT size = int_size_in_bytes (valtype);
8442 if (size % UNITS_PER_WORD != 0)
8443 {
8444 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
8445 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
8446 }
8447 }
8448
8449 /* For EABI, the class of return register depends entirely on MODE.
8450 For example, "struct { some_type x; }" and "union { some_type x; }"
8451 are returned in the same way as a bare "some_type" would be.
8452 Other ABIs only use FPRs for scalar, complex or vector types. */
8453 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
8454 return gen_rtx_REG (mode, GP_RETURN);
8455 }
8456
8457 if (!TARGET_MIPS16)
8458 {
8459 /* Handle long doubles for n32 & n64. */
8460 if (mode == TFmode)
8461 return mips_return_fpr_pair (mode,
8462 DImode, 0,
8463 DImode, GET_MODE_SIZE (mode) / 2);
8464
8465 if (mips_return_mode_in_fpr_p (mode))
8466 {
8467 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8468 return mips_return_fpr_pair (mode,
8469 GET_MODE_INNER (mode), 0,
8470 GET_MODE_INNER (mode),
8471 GET_MODE_SIZE (mode) / 2);
8472 else
8473 return gen_rtx_REG (mode, FP_RETURN);
8474 }
8475 }
8476
8477 return gen_rtx_REG (mode, GP_RETURN);
8478 }
8479
8480 /* Return nonzero when an argument must be passed by reference. */
8481
8482 static bool
8483 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
8484 enum machine_mode mode, tree type,
8485 bool named ATTRIBUTE_UNUSED)
8486 {
8487 if (mips_abi == ABI_EABI)
8488 {
8489 int size;
8490
8491 /* ??? How should SCmode be handled? */
8492 if (mode == DImode || mode == DFmode)
8493 return 0;
8494
8495 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
8496 return size == -1 || size > UNITS_PER_WORD;
8497 }
8498 else
8499 {
8500 /* If we have a variable-sized parameter, we have no choice. */
8501 return targetm.calls.must_pass_in_stack (mode, type);
8502 }
8503 }
8504
8505 static bool
8506 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
8507 enum machine_mode mode ATTRIBUTE_UNUSED,
8508 tree type ATTRIBUTE_UNUSED, bool named)
8509 {
8510 return mips_abi == ABI_EABI && named;
8511 }
8512
8513 /* Return true if registers of class CLASS cannot change from mode FROM
8514 to mode TO. */
8515
8516 bool
8517 mips_cannot_change_mode_class (enum machine_mode from,
8518 enum machine_mode to, enum reg_class class)
8519 {
8520 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
8521 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
8522 {
8523 if (TARGET_BIG_ENDIAN)
8524 {
8525 /* When a multi-word value is stored in paired floating-point
8526 registers, the first register always holds the low word.
8527 We therefore can't allow FPRs to change between single-word
8528 and multi-word modes. */
8529 if (MAX_FPRS_PER_FMT > 1 && reg_classes_intersect_p (FP_REGS, class))
8530 return true;
8531 }
8532 }
8533
8534 /* gcc assumes that each word of a multiword register can be accessed
8535 individually using SUBREGs. This is not true for floating-point
8536 registers if they are bigger than a word. */
8537 if (UNITS_PER_FPREG > UNITS_PER_WORD
8538 && GET_MODE_SIZE (from) > UNITS_PER_WORD
8539 && GET_MODE_SIZE (to) < UNITS_PER_FPREG
8540 && reg_classes_intersect_p (FP_REGS, class))
8541 return true;
8542
8543 /* Loading a 32-bit value into a 64-bit floating-point register
8544 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8545 We can't allow 64-bit float registers to change from SImode to
8546 to a wider mode. */
8547 if (TARGET_64BIT
8548 && TARGET_FLOAT64
8549 && from == SImode
8550 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
8551 && reg_classes_intersect_p (FP_REGS, class))
8552 return true;
8553
8554 return false;
8555 }
8556
8557 /* Return true if X should not be moved directly into register $25.
8558 We need this because many versions of GAS will treat "la $25,foo" as
8559 part of a call sequence and so allow a global "foo" to be lazily bound. */
8560
8561 bool
8562 mips_dangerous_for_la25_p (rtx x)
8563 {
8564 return (!TARGET_EXPLICIT_RELOCS
8565 && TARGET_USE_GOT
8566 && GET_CODE (x) == SYMBOL_REF
8567 && mips_global_symbol_p (x));
8568 }
8569
8570 /* Implement PREFERRED_RELOAD_CLASS. */
8571
8572 enum reg_class
8573 mips_preferred_reload_class (rtx x, enum reg_class class)
8574 {
8575 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
8576 return LEA_REGS;
8577
8578 if (TARGET_HARD_FLOAT
8579 && FLOAT_MODE_P (GET_MODE (x))
8580 && reg_class_subset_p (FP_REGS, class))
8581 return FP_REGS;
8582
8583 if (reg_class_subset_p (GR_REGS, class))
8584 class = GR_REGS;
8585
8586 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
8587 class = M16_REGS;
8588
8589 return class;
8590 }
8591
8592 /* This function returns the register class required for a secondary
8593 register when copying between one of the registers in CLASS, and X,
8594 using MODE. If IN_P is nonzero, the copy is going from X to the
8595 register, otherwise the register is the source. A return value of
8596 NO_REGS means that no secondary register is required. */
8597
8598 enum reg_class
8599 mips_secondary_reload_class (enum reg_class class,
8600 enum machine_mode mode, rtx x, int in_p)
8601 {
8602 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
8603 int regno = -1;
8604 int gp_reg_p;
8605
8606 if (REG_P (x)|| GET_CODE (x) == SUBREG)
8607 regno = true_regnum (x);
8608
8609 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8610
8611 if (mips_dangerous_for_la25_p (x))
8612 {
8613 gr_regs = LEA_REGS;
8614 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
8615 return gr_regs;
8616 }
8617
8618 /* Copying from HI or LO to anywhere other than a general register
8619 requires a general register.
8620 This rule applies to both the original HI/LO pair and the new
8621 DSP accumulators. */
8622 if (reg_class_subset_p (class, ACC_REGS))
8623 {
8624 if (TARGET_MIPS16 && in_p)
8625 {
8626 /* We can't really copy to HI or LO at all in mips16 mode. */
8627 return M16_REGS;
8628 }
8629 return gp_reg_p ? NO_REGS : gr_regs;
8630 }
8631 if (ACC_REG_P (regno))
8632 {
8633 if (TARGET_MIPS16 && ! in_p)
8634 {
8635 /* We can't really copy to HI or LO at all in mips16 mode. */
8636 return M16_REGS;
8637 }
8638 return class == gr_regs ? NO_REGS : gr_regs;
8639 }
8640
8641 /* We can only copy a value to a condition code register from a
8642 floating point register, and even then we require a scratch
8643 floating point register. We can only copy a value out of a
8644 condition code register into a general register. */
8645 if (class == ST_REGS)
8646 {
8647 if (in_p)
8648 return FP_REGS;
8649 return gp_reg_p ? NO_REGS : gr_regs;
8650 }
8651 if (ST_REG_P (regno))
8652 {
8653 if (! in_p)
8654 return FP_REGS;
8655 return class == gr_regs ? NO_REGS : gr_regs;
8656 }
8657
8658 if (class == FP_REGS)
8659 {
8660 if (MEM_P (x))
8661 {
8662 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
8663 return NO_REGS;
8664 }
8665 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
8666 {
8667 /* We can use the l.s and l.d macros to load floating-point
8668 constants. ??? For l.s, we could probably get better
8669 code by returning GR_REGS here. */
8670 return NO_REGS;
8671 }
8672 else if (gp_reg_p || x == CONST0_RTX (mode))
8673 {
8674 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8675 return NO_REGS;
8676 }
8677 else if (FP_REG_P (regno))
8678 {
8679 /* In this case we can use mov.s or mov.d. */
8680 return NO_REGS;
8681 }
8682 else
8683 {
8684 /* Otherwise, we need to reload through an integer register. */
8685 return gr_regs;
8686 }
8687 }
8688
8689 /* In mips16 mode, going between memory and anything but M16_REGS
8690 requires an M16_REG. */
8691 if (TARGET_MIPS16)
8692 {
8693 if (class != M16_REGS && class != M16_NA_REGS)
8694 {
8695 if (gp_reg_p)
8696 return NO_REGS;
8697 return M16_REGS;
8698 }
8699 if (! gp_reg_p)
8700 {
8701 if (class == M16_REGS || class == M16_NA_REGS)
8702 return NO_REGS;
8703 return M16_REGS;
8704 }
8705 }
8706
8707 return NO_REGS;
8708 }
8709
8710 /* Implement CLASS_MAX_NREGS.
8711
8712 - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
8713
8714 - ST_REGS are always hold CCmode values, and CCmode values are
8715 considered to be 4 bytes wide.
8716
8717 All other register classes are covered by UNITS_PER_WORD. Note that
8718 this is true even for unions of integer and float registers when the
8719 latter are smaller than the former. The only supported combination
8720 in which case this occurs is -mgp64 -msingle-float, which has 64-bit
8721 words but 32-bit float registers. A word-based calculation is correct
8722 in that case since -msingle-float disallows multi-FPR values. */
8723
8724 int
8725 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
8726 enum machine_mode mode)
8727 {
8728 if (class == ST_REGS)
8729 return (GET_MODE_SIZE (mode) + 3) / 4;
8730 else if (class == FP_REGS)
8731 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
8732 else
8733 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8734 }
8735
8736 static bool
8737 mips_valid_pointer_mode (enum machine_mode mode)
8738 {
8739 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8740 }
8741
8742 /* Target hook for vector_mode_supported_p. */
8743
8744 static bool
8745 mips_vector_mode_supported_p (enum machine_mode mode)
8746 {
8747 switch (mode)
8748 {
8749 case V2SFmode:
8750 return TARGET_PAIRED_SINGLE_FLOAT;
8751
8752 case V2HImode:
8753 case V4QImode:
8754 return TARGET_DSP;
8755
8756 default:
8757 return false;
8758 }
8759 }
8760 \f
8761 /* If we can access small data directly (using gp-relative relocation
8762 operators) return the small data pointer, otherwise return null.
8763
8764 For each mips16 function which refers to GP relative symbols, we
8765 use a pseudo register, initialized at the start of the function, to
8766 hold the $gp value. */
8767
8768 static rtx
8769 mips16_gp_pseudo_reg (void)
8770 {
8771 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
8772 {
8773 rtx insn, scan;
8774
8775 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8776
8777 /* We want to initialize this to a value which gcc will believe
8778 is constant. */
8779 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
8780
8781 push_topmost_sequence ();
8782 /* We need to emit the initialization after the FUNCTION_BEG
8783 note, so that it will be integrated. */
8784 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8785 if (NOTE_P (scan)
8786 && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
8787 break;
8788 if (scan == NULL_RTX)
8789 scan = get_insns ();
8790 insn = emit_insn_after (insn, scan);
8791 pop_topmost_sequence ();
8792 }
8793
8794 return cfun->machine->mips16_gp_pseudo_rtx;
8795 }
8796
8797 /* Write out code to move floating point arguments in or out of
8798 general registers. Output the instructions to FILE. FP_CODE is
8799 the code describing which arguments are present (see the comment at
8800 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
8801 we are copying from the floating point registers. */
8802
8803 static void
8804 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
8805 {
8806 const char *s;
8807 int gparg, fparg;
8808 unsigned int f;
8809 CUMULATIVE_ARGS cum;
8810
8811 /* This code only works for the original 32-bit ABI and the O64 ABI. */
8812 gcc_assert (TARGET_OLDABI);
8813
8814 if (from_fp_p)
8815 s = "mfc1";
8816 else
8817 s = "mtc1";
8818
8819 init_cumulative_args (&cum, NULL, NULL);
8820
8821 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8822 {
8823 enum machine_mode mode;
8824 struct mips_arg_info info;
8825
8826 if ((f & 3) == 1)
8827 mode = SFmode;
8828 else if ((f & 3) == 2)
8829 mode = DFmode;
8830 else
8831 gcc_unreachable ();
8832
8833 mips_arg_info (&cum, mode, NULL, true, &info);
8834 gparg = mips_arg_regno (&info, false);
8835 fparg = mips_arg_regno (&info, true);
8836
8837 if (mode == SFmode)
8838 fprintf (file, "\t%s\t%s,%s\n", s,
8839 reg_names[gparg], reg_names[fparg]);
8840 else if (TARGET_64BIT)
8841 fprintf (file, "\td%s\t%s,%s\n", s,
8842 reg_names[gparg], reg_names[fparg]);
8843 else if (ISA_HAS_MXHC1)
8844 /* -mips32r2 -mfp64 */
8845 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n",
8846 s,
8847 reg_names[gparg + (WORDS_BIG_ENDIAN ? 1 : 0)],
8848 reg_names[fparg],
8849 from_fp_p ? "mfhc1" : "mthc1",
8850 reg_names[gparg + (WORDS_BIG_ENDIAN ? 0 : 1)],
8851 reg_names[fparg]);
8852 else if (TARGET_BIG_ENDIAN)
8853 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8854 reg_names[gparg], reg_names[fparg + 1], s,
8855 reg_names[gparg + 1], reg_names[fparg]);
8856 else
8857 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8858 reg_names[gparg], reg_names[fparg], s,
8859 reg_names[gparg + 1], reg_names[fparg + 1]);
8860
8861 function_arg_advance (&cum, mode, NULL, true);
8862 }
8863 }
8864
8865 /* Build a mips16 function stub. This is used for functions which
8866 take arguments in the floating point registers. It is 32-bit code
8867 that moves the floating point args into the general registers, and
8868 then jumps to the 16-bit code. */
8869
8870 static void
8871 build_mips16_function_stub (FILE *file)
8872 {
8873 const char *fnname;
8874 char *secname, *stubname;
8875 tree stubid, stubdecl;
8876 int need_comma;
8877 unsigned int f;
8878
8879 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8880 secname = (char *) alloca (strlen (fnname) + 20);
8881 sprintf (secname, ".mips16.fn.%s", fnname);
8882 stubname = (char *) alloca (strlen (fnname) + 20);
8883 sprintf (stubname, "__fn_stub_%s", fnname);
8884 stubid = get_identifier (stubname);
8885 stubdecl = build_decl (FUNCTION_DECL, stubid,
8886 build_function_type (void_type_node, NULL_TREE));
8887 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8888 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
8889
8890 fprintf (file, "\t# Stub function for %s (", current_function_name ());
8891 need_comma = 0;
8892 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8893 {
8894 fprintf (file, "%s%s",
8895 need_comma ? ", " : "",
8896 (f & 3) == 1 ? "float" : "double");
8897 need_comma = 1;
8898 }
8899 fprintf (file, ")\n");
8900
8901 fprintf (file, "\t.set\tnomips16\n");
8902 switch_to_section (function_section (stubdecl));
8903 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8904
8905 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8906 within a .ent, and we cannot emit another .ent. */
8907 if (!FUNCTION_NAME_ALREADY_DECLARED)
8908 {
8909 fputs ("\t.ent\t", file);
8910 assemble_name (file, stubname);
8911 fputs ("\n", file);
8912 }
8913
8914 assemble_name (file, stubname);
8915 fputs (":\n", file);
8916
8917 /* We don't want the assembler to insert any nops here. */
8918 fprintf (file, "\t.set\tnoreorder\n");
8919
8920 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8921
8922 fprintf (asm_out_file, "\t.set\tnoat\n");
8923 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8924 assemble_name (file, fnname);
8925 fprintf (file, "\n");
8926 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8927 fprintf (asm_out_file, "\t.set\tat\n");
8928
8929 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8930 with one of the mfc1 instructions, because the result is not
8931 available for one instruction, so if the very first instruction
8932 in the function refers to the register, it will see the wrong
8933 value. */
8934 fprintf (file, "\tnop\n");
8935
8936 fprintf (file, "\t.set\treorder\n");
8937
8938 if (!FUNCTION_NAME_ALREADY_DECLARED)
8939 {
8940 fputs ("\t.end\t", file);
8941 assemble_name (file, stubname);
8942 fputs ("\n", file);
8943 }
8944
8945 fprintf (file, "\t.set\tmips16\n");
8946
8947 switch_to_section (function_section (current_function_decl));
8948 }
8949
8950 /* We keep a list of functions for which we have already built stubs
8951 in build_mips16_call_stub. */
8952
8953 struct mips16_stub
8954 {
8955 struct mips16_stub *next;
8956 char *name;
8957 int fpret;
8958 };
8959
8960 static struct mips16_stub *mips16_stubs;
8961
8962 /* Emit code to return a double value from a mips16 stub. GPREG is the
8963 first GP reg to use, FPREG is the first FP reg to use. */
8964
8965 static void
8966 mips16_fpret_double (int gpreg, int fpreg)
8967 {
8968 if (TARGET_64BIT)
8969 fprintf (asm_out_file, "\tdmfc1\t%s,%s\n",
8970 reg_names[gpreg], reg_names[fpreg]);
8971 else if (TARGET_FLOAT64)
8972 {
8973 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8974 reg_names[gpreg + WORDS_BIG_ENDIAN],
8975 reg_names[fpreg]);
8976 fprintf (asm_out_file, "\tmfhc1\t%s,%s\n",
8977 reg_names[gpreg + !WORDS_BIG_ENDIAN],
8978 reg_names[fpreg]);
8979 }
8980 else
8981 {
8982 if (TARGET_BIG_ENDIAN)
8983 {
8984 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8985 reg_names[gpreg + 0],
8986 reg_names[fpreg + 1]);
8987 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8988 reg_names[gpreg + 1],
8989 reg_names[fpreg + 0]);
8990 }
8991 else
8992 {
8993 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8994 reg_names[gpreg + 0],
8995 reg_names[fpreg + 0]);
8996 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8997 reg_names[gpreg + 1],
8998 reg_names[fpreg + 1]);
8999 }
9000 }
9001 }
9002
9003 /* Build a call stub for a mips16 call. A stub is needed if we are
9004 passing any floating point values which should go into the floating
9005 point registers. If we are, and the call turns out to be to a
9006 32-bit function, the stub will be used to move the values into the
9007 floating point registers before calling the 32-bit function. The
9008 linker will magically adjust the function call to either the 16-bit
9009 function or the 32-bit stub, depending upon where the function call
9010 is actually defined.
9011
9012 Similarly, we need a stub if the return value might come back in a
9013 floating point register.
9014
9015 RETVAL is the location of the return value, or null if this is
9016 a call rather than a call_value. FN is the address of the
9017 function and ARG_SIZE is the size of the arguments. FP_CODE
9018 is the code built by function_arg. This function returns a nonzero
9019 value if it builds the call instruction itself. */
9020
9021 int
9022 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
9023 {
9024 int fpret = 0;
9025 const char *fnname;
9026 char *secname, *stubname;
9027 struct mips16_stub *l;
9028 tree stubid, stubdecl;
9029 int need_comma;
9030 unsigned int f;
9031
9032 /* We don't need to do anything if we aren't in mips16 mode, or if
9033 we were invoked with the -msoft-float option. */
9034 if (!mips16_hard_float)
9035 return 0;
9036
9037 /* Figure out whether the value might come back in a floating point
9038 register. */
9039 if (retval)
9040 fpret = mips_return_mode_in_fpr_p (GET_MODE (retval));
9041
9042 /* We don't need to do anything if there were no floating point
9043 arguments and the value will not be returned in a floating point
9044 register. */
9045 if (fp_code == 0 && ! fpret)
9046 return 0;
9047
9048 /* We don't need to do anything if this is a call to a special
9049 mips16 support function. */
9050 if (GET_CODE (fn) == SYMBOL_REF
9051 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
9052 return 0;
9053
9054 /* This code will only work for o32 and o64 abis. The other ABI's
9055 require more sophisticated support. */
9056 gcc_assert (TARGET_OLDABI);
9057
9058 /* If we're calling via a function pointer, then we must always call
9059 via a stub. There are magic stubs provided in libgcc.a for each
9060 of the required cases. Each of them expects the function address
9061 to arrive in register $2. */
9062
9063 if (GET_CODE (fn) != SYMBOL_REF)
9064 {
9065 char buf[30];
9066 tree id;
9067 rtx stub_fn, insn;
9068
9069 /* ??? If this code is modified to support other ABI's, we need
9070 to handle PARALLEL return values here. */
9071
9072 if (fpret)
9073 sprintf (buf, "__mips16_call_stub_%s_%d",
9074 mips16_call_stub_mode_suffix (GET_MODE (retval)),
9075 fp_code);
9076 else
9077 sprintf (buf, "__mips16_call_stub_%d",
9078 fp_code);
9079
9080 id = get_identifier (buf);
9081 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
9082
9083 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
9084
9085 if (retval == NULL_RTX)
9086 insn = gen_call_internal (stub_fn, arg_size);
9087 else
9088 insn = gen_call_value_internal (retval, stub_fn, arg_size);
9089 insn = emit_call_insn (insn);
9090
9091 /* Put the register usage information on the CALL. */
9092 CALL_INSN_FUNCTION_USAGE (insn) =
9093 gen_rtx_EXPR_LIST (VOIDmode,
9094 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
9095 CALL_INSN_FUNCTION_USAGE (insn));
9096
9097 /* If we are handling a floating point return value, we need to
9098 save $18 in the function prologue. Putting a note on the
9099 call will mean that df_regs_ever_live_p ($18) will be true if the
9100 call is not eliminated, and we can check that in the prologue
9101 code. */
9102 if (fpret)
9103 CALL_INSN_FUNCTION_USAGE (insn) =
9104 gen_rtx_EXPR_LIST (VOIDmode,
9105 gen_rtx_USE (VOIDmode,
9106 gen_rtx_REG (word_mode, 18)),
9107 CALL_INSN_FUNCTION_USAGE (insn));
9108
9109 /* Return 1 to tell the caller that we've generated the call
9110 insn. */
9111 return 1;
9112 }
9113
9114 /* We know the function we are going to call. If we have already
9115 built a stub, we don't need to do anything further. */
9116
9117 fnname = XSTR (fn, 0);
9118 for (l = mips16_stubs; l != NULL; l = l->next)
9119 if (strcmp (l->name, fnname) == 0)
9120 break;
9121
9122 if (l == NULL)
9123 {
9124 /* Build a special purpose stub. When the linker sees a
9125 function call in mips16 code, it will check where the target
9126 is defined. If the target is a 32-bit call, the linker will
9127 search for the section defined here. It can tell which
9128 symbol this section is associated with by looking at the
9129 relocation information (the name is unreliable, since this
9130 might be a static function). If such a section is found, the
9131 linker will redirect the call to the start of the magic
9132 section.
9133
9134 If the function does not return a floating point value, the
9135 special stub section is named
9136 .mips16.call.FNNAME
9137
9138 If the function does return a floating point value, the stub
9139 section is named
9140 .mips16.call.fp.FNNAME
9141 */
9142
9143 secname = (char *) alloca (strlen (fnname) + 40);
9144 sprintf (secname, ".mips16.call.%s%s",
9145 fpret ? "fp." : "",
9146 fnname);
9147 stubname = (char *) alloca (strlen (fnname) + 20);
9148 sprintf (stubname, "__call_stub_%s%s",
9149 fpret ? "fp_" : "",
9150 fnname);
9151 stubid = get_identifier (stubname);
9152 stubdecl = build_decl (FUNCTION_DECL, stubid,
9153 build_function_type (void_type_node, NULL_TREE));
9154 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
9155 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
9156
9157 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
9158 (fpret
9159 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
9160 : ""),
9161 fnname);
9162 need_comma = 0;
9163 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
9164 {
9165 fprintf (asm_out_file, "%s%s",
9166 need_comma ? ", " : "",
9167 (f & 3) == 1 ? "float" : "double");
9168 need_comma = 1;
9169 }
9170 fprintf (asm_out_file, ")\n");
9171
9172 fprintf (asm_out_file, "\t.set\tnomips16\n");
9173 assemble_start_function (stubdecl, stubname);
9174
9175 if (!FUNCTION_NAME_ALREADY_DECLARED)
9176 {
9177 fputs ("\t.ent\t", asm_out_file);
9178 assemble_name (asm_out_file, stubname);
9179 fputs ("\n", asm_out_file);
9180
9181 assemble_name (asm_out_file, stubname);
9182 fputs (":\n", asm_out_file);
9183 }
9184
9185 /* We build the stub code by hand. That's the only way we can
9186 do it, since we can't generate 32-bit code during a 16-bit
9187 compilation. */
9188
9189 /* We don't want the assembler to insert any nops here. */
9190 fprintf (asm_out_file, "\t.set\tnoreorder\n");
9191
9192 mips16_fp_args (asm_out_file, fp_code, 0);
9193
9194 if (! fpret)
9195 {
9196 fprintf (asm_out_file, "\t.set\tnoat\n");
9197 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
9198 fnname);
9199 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
9200 fprintf (asm_out_file, "\t.set\tat\n");
9201 /* Unfortunately, we can't fill the jump delay slot. We
9202 can't fill with one of the mtc1 instructions, because the
9203 result is not available for one instruction, so if the
9204 very first instruction in the function refers to the
9205 register, it will see the wrong value. */
9206 fprintf (asm_out_file, "\tnop\n");
9207 }
9208 else
9209 {
9210 fprintf (asm_out_file, "\tmove\t%s,%s\n",
9211 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
9212 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
9213 /* As above, we can't fill the delay slot. */
9214 fprintf (asm_out_file, "\tnop\n");
9215 if (GET_MODE (retval) == SFmode)
9216 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9217 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
9218 else if (GET_MODE (retval) == SCmode)
9219 {
9220 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9221 reg_names[GP_REG_FIRST + 2],
9222 reg_names[FP_REG_FIRST + 0]);
9223 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9224 reg_names[GP_REG_FIRST + 3],
9225 reg_names[FP_REG_FIRST + MAX_FPRS_PER_FMT]);
9226 }
9227 else if (GET_MODE (retval) == DFmode
9228 || GET_MODE (retval) == V2SFmode)
9229 {
9230 mips16_fpret_double (GP_REG_FIRST + 2, FP_REG_FIRST + 0);
9231 }
9232 else if (GET_MODE (retval) == DCmode)
9233 {
9234 mips16_fpret_double (GP_REG_FIRST + 2,
9235 FP_REG_FIRST + 0);
9236 mips16_fpret_double (GP_REG_FIRST + 4,
9237 FP_REG_FIRST + MAX_FPRS_PER_FMT);
9238 }
9239 else
9240 {
9241 if (TARGET_BIG_ENDIAN)
9242 {
9243 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9244 reg_names[GP_REG_FIRST + 2],
9245 reg_names[FP_REG_FIRST + 1]);
9246 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9247 reg_names[GP_REG_FIRST + 3],
9248 reg_names[FP_REG_FIRST + 0]);
9249 }
9250 else
9251 {
9252 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9253 reg_names[GP_REG_FIRST + 2],
9254 reg_names[FP_REG_FIRST + 0]);
9255 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9256 reg_names[GP_REG_FIRST + 3],
9257 reg_names[FP_REG_FIRST + 1]);
9258 }
9259 }
9260 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
9261 /* As above, we can't fill the delay slot. */
9262 fprintf (asm_out_file, "\tnop\n");
9263 }
9264
9265 fprintf (asm_out_file, "\t.set\treorder\n");
9266
9267 #ifdef ASM_DECLARE_FUNCTION_SIZE
9268 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
9269 #endif
9270
9271 if (!FUNCTION_NAME_ALREADY_DECLARED)
9272 {
9273 fputs ("\t.end\t", asm_out_file);
9274 assemble_name (asm_out_file, stubname);
9275 fputs ("\n", asm_out_file);
9276 }
9277
9278 fprintf (asm_out_file, "\t.set\tmips16\n");
9279
9280 /* Record this stub. */
9281 l = (struct mips16_stub *) xmalloc (sizeof *l);
9282 l->name = xstrdup (fnname);
9283 l->fpret = fpret;
9284 l->next = mips16_stubs;
9285 mips16_stubs = l;
9286 }
9287
9288 /* If we expect a floating point return value, but we've built a
9289 stub which does not expect one, then we're in trouble. We can't
9290 use the existing stub, because it won't handle the floating point
9291 value. We can't build a new stub, because the linker won't know
9292 which stub to use for the various calls in this object file.
9293 Fortunately, this case is illegal, since it means that a function
9294 was declared in two different ways in a single compilation. */
9295 if (fpret && ! l->fpret)
9296 error ("cannot handle inconsistent calls to %qs", fnname);
9297
9298 /* If we are calling a stub which handles a floating point return
9299 value, we need to arrange to save $18 in the prologue. We do
9300 this by marking the function call as using the register. The
9301 prologue will later see that it is used, and emit code to save
9302 it. */
9303
9304 if (l->fpret)
9305 {
9306 rtx insn;
9307
9308 if (retval == NULL_RTX)
9309 insn = gen_call_internal (fn, arg_size);
9310 else
9311 insn = gen_call_value_internal (retval, fn, arg_size);
9312 insn = emit_call_insn (insn);
9313
9314 CALL_INSN_FUNCTION_USAGE (insn) =
9315 gen_rtx_EXPR_LIST (VOIDmode,
9316 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
9317 CALL_INSN_FUNCTION_USAGE (insn));
9318
9319 /* Return 1 to tell the caller that we've generated the call
9320 insn. */
9321 return 1;
9322 }
9323
9324 /* Return 0 to let the caller generate the call insn. */
9325 return 0;
9326 }
9327
9328 /* An entry in the mips16 constant pool. VALUE is the pool constant,
9329 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
9330
9331 struct mips16_constant {
9332 struct mips16_constant *next;
9333 rtx value;
9334 rtx label;
9335 enum machine_mode mode;
9336 };
9337
9338 /* Information about an incomplete mips16 constant pool. FIRST is the
9339 first constant, HIGHEST_ADDRESS is the highest address that the first
9340 byte of the pool can have, and INSN_ADDRESS is the current instruction
9341 address. */
9342
9343 struct mips16_constant_pool {
9344 struct mips16_constant *first;
9345 int highest_address;
9346 int insn_address;
9347 };
9348
9349 /* Add constant VALUE to POOL and return its label. MODE is the
9350 value's mode (used for CONST_INTs, etc.). */
9351
9352 static rtx
9353 add_constant (struct mips16_constant_pool *pool,
9354 rtx value, enum machine_mode mode)
9355 {
9356 struct mips16_constant **p, *c;
9357 bool first_of_size_p;
9358
9359 /* See whether the constant is already in the pool. If so, return the
9360 existing label, otherwise leave P pointing to the place where the
9361 constant should be added.
9362
9363 Keep the pool sorted in increasing order of mode size so that we can
9364 reduce the number of alignments needed. */
9365 first_of_size_p = true;
9366 for (p = &pool->first; *p != 0; p = &(*p)->next)
9367 {
9368 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
9369 return (*p)->label;
9370 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
9371 break;
9372 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
9373 first_of_size_p = false;
9374 }
9375
9376 /* In the worst case, the constant needed by the earliest instruction
9377 will end up at the end of the pool. The entire pool must then be
9378 accessible from that instruction.
9379
9380 When adding the first constant, set the pool's highest address to
9381 the address of the first out-of-range byte. Adjust this address
9382 downwards each time a new constant is added. */
9383 if (pool->first == 0)
9384 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
9385 is the address of the instruction with the lowest two bits clear.
9386 The base PC value for ld has the lowest three bits clear. Assume
9387 the worst case here. */
9388 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
9389 pool->highest_address -= GET_MODE_SIZE (mode);
9390 if (first_of_size_p)
9391 /* Take into account the worst possible padding due to alignment. */
9392 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
9393
9394 /* Create a new entry. */
9395 c = (struct mips16_constant *) xmalloc (sizeof *c);
9396 c->value = value;
9397 c->mode = mode;
9398 c->label = gen_label_rtx ();
9399 c->next = *p;
9400 *p = c;
9401
9402 return c->label;
9403 }
9404
9405 /* Output constant VALUE after instruction INSN and return the last
9406 instruction emitted. MODE is the mode of the constant. */
9407
9408 static rtx
9409 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
9410 {
9411 switch (GET_MODE_CLASS (mode))
9412 {
9413 case MODE_INT:
9414 {
9415 rtx size = GEN_INT (GET_MODE_SIZE (mode));
9416 return emit_insn_after (gen_consttable_int (value, size), insn);
9417 }
9418
9419 case MODE_FLOAT:
9420 return emit_insn_after (gen_consttable_float (value), insn);
9421
9422 case MODE_VECTOR_FLOAT:
9423 case MODE_VECTOR_INT:
9424 {
9425 int i;
9426 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
9427 insn = dump_constants_1 (GET_MODE_INNER (mode),
9428 CONST_VECTOR_ELT (value, i), insn);
9429 return insn;
9430 }
9431
9432 default:
9433 gcc_unreachable ();
9434 }
9435 }
9436
9437
9438 /* Dump out the constants in CONSTANTS after INSN. */
9439
9440 static void
9441 dump_constants (struct mips16_constant *constants, rtx insn)
9442 {
9443 struct mips16_constant *c, *next;
9444 int align;
9445
9446 align = 0;
9447 for (c = constants; c != NULL; c = next)
9448 {
9449 /* If necessary, increase the alignment of PC. */
9450 if (align < GET_MODE_SIZE (c->mode))
9451 {
9452 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
9453 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
9454 }
9455 align = GET_MODE_SIZE (c->mode);
9456
9457 insn = emit_label_after (c->label, insn);
9458 insn = dump_constants_1 (c->mode, c->value, insn);
9459
9460 next = c->next;
9461 free (c);
9462 }
9463
9464 emit_barrier_after (insn);
9465 }
9466
9467 /* Return the length of instruction INSN. */
9468
9469 static int
9470 mips16_insn_length (rtx insn)
9471 {
9472 if (JUMP_P (insn))
9473 {
9474 rtx body = PATTERN (insn);
9475 if (GET_CODE (body) == ADDR_VEC)
9476 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
9477 if (GET_CODE (body) == ADDR_DIFF_VEC)
9478 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
9479 }
9480 return get_attr_length (insn);
9481 }
9482
9483 /* Rewrite *X so that constant pool references refer to the constant's
9484 label instead. DATA points to the constant pool structure. */
9485
9486 static int
9487 mips16_rewrite_pool_refs (rtx *x, void *data)
9488 {
9489 struct mips16_constant_pool *pool = data;
9490 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
9491 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
9492 get_pool_constant (*x),
9493 get_pool_mode (*x)));
9494 return 0;
9495 }
9496
9497 /* Build MIPS16 constant pools. */
9498
9499 static void
9500 mips16_lay_out_constants (void)
9501 {
9502 struct mips16_constant_pool pool;
9503 rtx insn, barrier;
9504
9505 barrier = 0;
9506 memset (&pool, 0, sizeof (pool));
9507 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9508 {
9509 /* Rewrite constant pool references in INSN. */
9510 if (INSN_P (insn))
9511 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
9512
9513 pool.insn_address += mips16_insn_length (insn);
9514
9515 if (pool.first != NULL)
9516 {
9517 /* If there are no natural barriers between the first user of
9518 the pool and the highest acceptable address, we'll need to
9519 create a new instruction to jump around the constant pool.
9520 In the worst case, this instruction will be 4 bytes long.
9521
9522 If it's too late to do this transformation after INSN,
9523 do it immediately before INSN. */
9524 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
9525 {
9526 rtx label, jump;
9527
9528 label = gen_label_rtx ();
9529
9530 jump = emit_jump_insn_before (gen_jump (label), insn);
9531 JUMP_LABEL (jump) = label;
9532 LABEL_NUSES (label) = 1;
9533 barrier = emit_barrier_after (jump);
9534
9535 emit_label_after (label, barrier);
9536 pool.insn_address += 4;
9537 }
9538
9539 /* See whether the constant pool is now out of range of the first
9540 user. If so, output the constants after the previous barrier.
9541 Note that any instructions between BARRIER and INSN (inclusive)
9542 will use negative offsets to refer to the pool. */
9543 if (pool.insn_address > pool.highest_address)
9544 {
9545 dump_constants (pool.first, barrier);
9546 pool.first = NULL;
9547 barrier = 0;
9548 }
9549 else if (BARRIER_P (insn))
9550 barrier = insn;
9551 }
9552 }
9553 dump_constants (pool.first, get_last_insn ());
9554 }
9555 \f
9556 /* A temporary variable used by for_each_rtx callbacks, etc. */
9557 static rtx mips_sim_insn;
9558
9559 /* A structure representing the state of the processor pipeline.
9560 Used by the mips_sim_* family of functions. */
9561 struct mips_sim {
9562 /* The maximum number of instructions that can be issued in a cycle.
9563 (Caches mips_issue_rate.) */
9564 unsigned int issue_rate;
9565
9566 /* The current simulation time. */
9567 unsigned int time;
9568
9569 /* How many more instructions can be issued in the current cycle. */
9570 unsigned int insns_left;
9571
9572 /* LAST_SET[X].INSN is the last instruction to set register X.
9573 LAST_SET[X].TIME is the time at which that instruction was issued.
9574 INSN is null if no instruction has yet set register X. */
9575 struct {
9576 rtx insn;
9577 unsigned int time;
9578 } last_set[FIRST_PSEUDO_REGISTER];
9579
9580 /* The pipeline's current DFA state. */
9581 state_t dfa_state;
9582 };
9583
9584 /* Reset STATE to the initial simulation state. */
9585
9586 static void
9587 mips_sim_reset (struct mips_sim *state)
9588 {
9589 state->time = 0;
9590 state->insns_left = state->issue_rate;
9591 memset (&state->last_set, 0, sizeof (state->last_set));
9592 state_reset (state->dfa_state);
9593 }
9594
9595 /* Initialize STATE before its first use. DFA_STATE points to an
9596 allocated but uninitialized DFA state. */
9597
9598 static void
9599 mips_sim_init (struct mips_sim *state, state_t dfa_state)
9600 {
9601 state->issue_rate = mips_issue_rate ();
9602 state->dfa_state = dfa_state;
9603 mips_sim_reset (state);
9604 }
9605
9606 /* Advance STATE by one clock cycle. */
9607
9608 static void
9609 mips_sim_next_cycle (struct mips_sim *state)
9610 {
9611 state->time++;
9612 state->insns_left = state->issue_rate;
9613 state_transition (state->dfa_state, 0);
9614 }
9615
9616 /* Advance simulation state STATE until instruction INSN can read
9617 register REG. */
9618
9619 static void
9620 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
9621 {
9622 unsigned int i;
9623
9624 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
9625 if (state->last_set[REGNO (reg) + i].insn != 0)
9626 {
9627 unsigned int t;
9628
9629 t = state->last_set[REGNO (reg) + i].time;
9630 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
9631 while (state->time < t)
9632 mips_sim_next_cycle (state);
9633 }
9634 }
9635
9636 /* A for_each_rtx callback. If *X is a register, advance simulation state
9637 DATA until mips_sim_insn can read the register's value. */
9638
9639 static int
9640 mips_sim_wait_regs_2 (rtx *x, void *data)
9641 {
9642 if (REG_P (*x))
9643 mips_sim_wait_reg (data, mips_sim_insn, *x);
9644 return 0;
9645 }
9646
9647 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
9648
9649 static void
9650 mips_sim_wait_regs_1 (rtx *x, void *data)
9651 {
9652 for_each_rtx (x, mips_sim_wait_regs_2, data);
9653 }
9654
9655 /* Advance simulation state STATE until all of INSN's register
9656 dependencies are satisfied. */
9657
9658 static void
9659 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
9660 {
9661 mips_sim_insn = insn;
9662 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
9663 }
9664
9665 /* Advance simulation state STATE until the units required by
9666 instruction INSN are available. */
9667
9668 static void
9669 mips_sim_wait_units (struct mips_sim *state, rtx insn)
9670 {
9671 state_t tmp_state;
9672
9673 tmp_state = alloca (state_size ());
9674 while (state->insns_left == 0
9675 || (memcpy (tmp_state, state->dfa_state, state_size ()),
9676 state_transition (tmp_state, insn) >= 0))
9677 mips_sim_next_cycle (state);
9678 }
9679
9680 /* Advance simulation state STATE until INSN is ready to issue. */
9681
9682 static void
9683 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
9684 {
9685 mips_sim_wait_regs (state, insn);
9686 mips_sim_wait_units (state, insn);
9687 }
9688
9689 /* mips_sim_insn has just set X. Update the LAST_SET array
9690 in simulation state DATA. */
9691
9692 static void
9693 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9694 {
9695 struct mips_sim *state;
9696 unsigned int i;
9697
9698 state = data;
9699 if (REG_P (x))
9700 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
9701 {
9702 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
9703 state->last_set[REGNO (x) + i].time = state->time;
9704 }
9705 }
9706
9707 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
9708 can issue immediately (i.e., that mips_sim_wait_insn has already
9709 been called). */
9710
9711 static void
9712 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
9713 {
9714 state_transition (state->dfa_state, insn);
9715 state->insns_left--;
9716
9717 mips_sim_insn = insn;
9718 note_stores (PATTERN (insn), mips_sim_record_set, state);
9719 }
9720
9721 /* Simulate issuing a NOP in state STATE. */
9722
9723 static void
9724 mips_sim_issue_nop (struct mips_sim *state)
9725 {
9726 if (state->insns_left == 0)
9727 mips_sim_next_cycle (state);
9728 state->insns_left--;
9729 }
9730
9731 /* Update simulation state STATE so that it's ready to accept the instruction
9732 after INSN. INSN should be part of the main rtl chain, not a member of a
9733 SEQUENCE. */
9734
9735 static void
9736 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
9737 {
9738 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
9739 if (JUMP_P (insn))
9740 mips_sim_issue_nop (state);
9741
9742 switch (GET_CODE (SEQ_BEGIN (insn)))
9743 {
9744 case CODE_LABEL:
9745 case CALL_INSN:
9746 /* We can't predict the processor state after a call or label. */
9747 mips_sim_reset (state);
9748 break;
9749
9750 case JUMP_INSN:
9751 /* The delay slots of branch likely instructions are only executed
9752 when the branch is taken. Therefore, if the caller has simulated
9753 the delay slot instruction, STATE does not really reflect the state
9754 of the pipeline for the instruction after the delay slot. Also,
9755 branch likely instructions tend to incur a penalty when not taken,
9756 so there will probably be an extra delay between the branch and
9757 the instruction after the delay slot. */
9758 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
9759 mips_sim_reset (state);
9760 break;
9761
9762 default:
9763 break;
9764 }
9765 }
9766 \f
9767 /* The VR4130 pipeline issues aligned pairs of instructions together,
9768 but it stalls the second instruction if it depends on the first.
9769 In order to cut down the amount of logic required, this dependence
9770 check is not based on a full instruction decode. Instead, any non-SPECIAL
9771 instruction is assumed to modify the register specified by bits 20-16
9772 (which is usually the "rt" field).
9773
9774 In beq, beql, bne and bnel instructions, the rt field is actually an
9775 input, so we can end up with a false dependence between the branch
9776 and its delay slot. If this situation occurs in instruction INSN,
9777 try to avoid it by swapping rs and rt. */
9778
9779 static void
9780 vr4130_avoid_branch_rt_conflict (rtx insn)
9781 {
9782 rtx first, second;
9783
9784 first = SEQ_BEGIN (insn);
9785 second = SEQ_END (insn);
9786 if (JUMP_P (first)
9787 && NONJUMP_INSN_P (second)
9788 && GET_CODE (PATTERN (first)) == SET
9789 && GET_CODE (SET_DEST (PATTERN (first))) == PC
9790 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
9791 {
9792 /* Check for the right kind of condition. */
9793 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
9794 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
9795 && REG_P (XEXP (cond, 0))
9796 && REG_P (XEXP (cond, 1))
9797 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
9798 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
9799 {
9800 /* SECOND mentions the rt register but not the rs register. */
9801 rtx tmp = XEXP (cond, 0);
9802 XEXP (cond, 0) = XEXP (cond, 1);
9803 XEXP (cond, 1) = tmp;
9804 }
9805 }
9806 }
9807
9808 /* Implement -mvr4130-align. Go through each basic block and simulate the
9809 processor pipeline. If we find that a pair of instructions could execute
9810 in parallel, and the first of those instruction is not 8-byte aligned,
9811 insert a nop to make it aligned. */
9812
9813 static void
9814 vr4130_align_insns (void)
9815 {
9816 struct mips_sim state;
9817 rtx insn, subinsn, last, last2, next;
9818 bool aligned_p;
9819
9820 dfa_start ();
9821
9822 /* LAST is the last instruction before INSN to have a nonzero length.
9823 LAST2 is the last such instruction before LAST. */
9824 last = 0;
9825 last2 = 0;
9826
9827 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
9828 aligned_p = true;
9829
9830 mips_sim_init (&state, alloca (state_size ()));
9831 for (insn = get_insns (); insn != 0; insn = next)
9832 {
9833 unsigned int length;
9834
9835 next = NEXT_INSN (insn);
9836
9837 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
9838 This isn't really related to the alignment pass, but we do it on
9839 the fly to avoid a separate instruction walk. */
9840 vr4130_avoid_branch_rt_conflict (insn);
9841
9842 if (USEFUL_INSN_P (insn))
9843 FOR_EACH_SUBINSN (subinsn, insn)
9844 {
9845 mips_sim_wait_insn (&state, subinsn);
9846
9847 /* If we want this instruction to issue in parallel with the
9848 previous one, make sure that the previous instruction is
9849 aligned. There are several reasons why this isn't worthwhile
9850 when the second instruction is a call:
9851
9852 - Calls are less likely to be performance critical,
9853 - There's a good chance that the delay slot can execute
9854 in parallel with the call.
9855 - The return address would then be unaligned.
9856
9857 In general, if we're going to insert a nop between instructions
9858 X and Y, it's better to insert it immediately after X. That
9859 way, if the nop makes Y aligned, it will also align any labels
9860 between X and Y. */
9861 if (state.insns_left != state.issue_rate
9862 && !CALL_P (subinsn))
9863 {
9864 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
9865 {
9866 /* SUBINSN is the first instruction in INSN and INSN is
9867 aligned. We want to align the previous instruction
9868 instead, so insert a nop between LAST2 and LAST.
9869
9870 Note that LAST could be either a single instruction
9871 or a branch with a delay slot. In the latter case,
9872 LAST, like INSN, is already aligned, but the delay
9873 slot must have some extra delay that stops it from
9874 issuing at the same time as the branch. We therefore
9875 insert a nop before the branch in order to align its
9876 delay slot. */
9877 emit_insn_after (gen_nop (), last2);
9878 aligned_p = false;
9879 }
9880 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
9881 {
9882 /* SUBINSN is the delay slot of INSN, but INSN is
9883 currently unaligned. Insert a nop between
9884 LAST and INSN to align it. */
9885 emit_insn_after (gen_nop (), last);
9886 aligned_p = true;
9887 }
9888 }
9889 mips_sim_issue_insn (&state, subinsn);
9890 }
9891 mips_sim_finish_insn (&state, insn);
9892
9893 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
9894 length = get_attr_length (insn);
9895 if (length > 0)
9896 {
9897 /* If the instruction is an asm statement or multi-instruction
9898 mips.md patern, the length is only an estimate. Insert an
9899 8 byte alignment after it so that the following instructions
9900 can be handled correctly. */
9901 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
9902 && (recog_memoized (insn) < 0 || length >= 8))
9903 {
9904 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
9905 next = NEXT_INSN (next);
9906 mips_sim_next_cycle (&state);
9907 aligned_p = true;
9908 }
9909 else if (length & 4)
9910 aligned_p = !aligned_p;
9911 last2 = last;
9912 last = insn;
9913 }
9914
9915 /* See whether INSN is an aligned label. */
9916 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
9917 aligned_p = true;
9918 }
9919 dfa_finish ();
9920 }
9921 \f
9922 /* Subroutine of mips_reorg. If there is a hazard between INSN
9923 and a previous instruction, avoid it by inserting nops after
9924 instruction AFTER.
9925
9926 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
9927 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
9928 before using the value of that register. *HILO_DELAY counts the
9929 number of instructions since the last hilo hazard (that is,
9930 the number of instructions since the last mflo or mfhi).
9931
9932 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
9933 for the next instruction.
9934
9935 LO_REG is an rtx for the LO register, used in dependence checking. */
9936
9937 static void
9938 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
9939 rtx *delayed_reg, rtx lo_reg)
9940 {
9941 rtx pattern, set;
9942 int nops, ninsns;
9943
9944 if (!INSN_P (insn))
9945 return;
9946
9947 pattern = PATTERN (insn);
9948
9949 /* Do not put the whole function in .set noreorder if it contains
9950 an asm statement. We don't know whether there will be hazards
9951 between the asm statement and the gcc-generated code. */
9952 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
9953 cfun->machine->all_noreorder_p = false;
9954
9955 /* Ignore zero-length instructions (barriers and the like). */
9956 ninsns = get_attr_length (insn) / 4;
9957 if (ninsns == 0)
9958 return;
9959
9960 /* Work out how many nops are needed. Note that we only care about
9961 registers that are explicitly mentioned in the instruction's pattern.
9962 It doesn't matter that calls use the argument registers or that they
9963 clobber hi and lo. */
9964 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
9965 nops = 2 - *hilo_delay;
9966 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
9967 nops = 1;
9968 else
9969 nops = 0;
9970
9971 /* Insert the nops between this instruction and the previous one.
9972 Each new nop takes us further from the last hilo hazard. */
9973 *hilo_delay += nops;
9974 while (nops-- > 0)
9975 emit_insn_after (gen_hazard_nop (), after);
9976
9977 /* Set up the state for the next instruction. */
9978 *hilo_delay += ninsns;
9979 *delayed_reg = 0;
9980 if (INSN_CODE (insn) >= 0)
9981 switch (get_attr_hazard (insn))
9982 {
9983 case HAZARD_NONE:
9984 break;
9985
9986 case HAZARD_HILO:
9987 *hilo_delay = 0;
9988 break;
9989
9990 case HAZARD_DELAY:
9991 set = single_set (insn);
9992 gcc_assert (set != 0);
9993 *delayed_reg = SET_DEST (set);
9994 break;
9995 }
9996 }
9997
9998
9999 /* Go through the instruction stream and insert nops where necessary.
10000 See if the whole function can then be put into .set noreorder &
10001 .set nomacro. */
10002
10003 static void
10004 mips_avoid_hazards (void)
10005 {
10006 rtx insn, last_insn, lo_reg, delayed_reg;
10007 int hilo_delay, i;
10008
10009 /* Force all instructions to be split into their final form. */
10010 split_all_insns_noflow ();
10011
10012 /* Recalculate instruction lengths without taking nops into account. */
10013 cfun->machine->ignore_hazard_length_p = true;
10014 shorten_branches (get_insns ());
10015
10016 cfun->machine->all_noreorder_p = true;
10017
10018 /* Profiled functions can't be all noreorder because the profiler
10019 support uses assembler macros. */
10020 if (current_function_profile)
10021 cfun->machine->all_noreorder_p = false;
10022
10023 /* Code compiled with -mfix-vr4120 can't be all noreorder because
10024 we rely on the assembler to work around some errata. */
10025 if (TARGET_FIX_VR4120)
10026 cfun->machine->all_noreorder_p = false;
10027
10028 /* The same is true for -mfix-vr4130 if we might generate mflo or
10029 mfhi instructions. Note that we avoid using mflo and mfhi if
10030 the VR4130 macc and dmacc instructions are available instead;
10031 see the *mfhilo_{si,di}_macc patterns. */
10032 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
10033 cfun->machine->all_noreorder_p = false;
10034
10035 last_insn = 0;
10036 hilo_delay = 2;
10037 delayed_reg = 0;
10038 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
10039
10040 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
10041 if (INSN_P (insn))
10042 {
10043 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
10044 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
10045 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
10046 &hilo_delay, &delayed_reg, lo_reg);
10047 else
10048 mips_avoid_hazard (last_insn, insn, &hilo_delay,
10049 &delayed_reg, lo_reg);
10050
10051 last_insn = insn;
10052 }
10053 }
10054
10055
10056 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
10057
10058 static void
10059 mips_reorg (void)
10060 {
10061 if (TARGET_MIPS16)
10062 mips16_lay_out_constants ();
10063 else if (TARGET_EXPLICIT_RELOCS)
10064 {
10065 if (mips_flag_delayed_branch)
10066 dbr_schedule (get_insns ());
10067 mips_avoid_hazards ();
10068 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
10069 vr4130_align_insns ();
10070 }
10071 }
10072
10073 /* This function does three things:
10074
10075 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
10076 - Register the mips16 hardware floating point stubs.
10077 - Register the gofast functions if selected using --enable-gofast. */
10078
10079 #include "config/gofast.h"
10080
10081 static void
10082 mips_init_libfuncs (void)
10083 {
10084 if (TARGET_FIX_VR4120)
10085 {
10086 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
10087 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
10088 }
10089
10090 if (mips16_hard_float)
10091 {
10092 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
10093 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
10094 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
10095 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
10096
10097 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
10098 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
10099 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
10100 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
10101 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
10102 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
10103
10104 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
10105 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
10106
10107 if (TARGET_DOUBLE_FLOAT)
10108 {
10109 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
10110 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
10111 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
10112 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
10113
10114 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
10115 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
10116 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
10117 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
10118 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
10119 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
10120
10121 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
10122 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
10123
10124 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
10125 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
10126 }
10127 }
10128 else
10129 gofast_maybe_init_libfuncs ();
10130 }
10131
10132 /* Return a number assessing the cost of moving a register in class
10133 FROM to class TO. The classes are expressed using the enumeration
10134 values such as `GENERAL_REGS'. A value of 2 is the default; other
10135 values are interpreted relative to that.
10136
10137 It is not required that the cost always equal 2 when FROM is the
10138 same as TO; on some machines it is expensive to move between
10139 registers if they are not general registers.
10140
10141 If reload sees an insn consisting of a single `set' between two
10142 hard registers, and if `REGISTER_MOVE_COST' applied to their
10143 classes returns a value of 2, reload does not check to ensure that
10144 the constraints of the insn are met. Setting a cost of other than
10145 2 will allow reload to verify that the constraints are met. You
10146 should do this if the `movM' pattern's constraints do not allow
10147 such copying.
10148
10149 ??? We make the cost of moving from HI/LO into general
10150 registers the same as for one of moving general registers to
10151 HI/LO for TARGET_MIPS16 in order to prevent allocating a
10152 pseudo to HI/LO. This might hurt optimizations though, it
10153 isn't clear if it is wise. And it might not work in all cases. We
10154 could solve the DImode LO reg problem by using a multiply, just
10155 like reload_{in,out}si. We could solve the SImode/HImode HI reg
10156 problem by using divide instructions. divu puts the remainder in
10157 the HI reg, so doing a divide by -1 will move the value in the HI
10158 reg for all values except -1. We could handle that case by using a
10159 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
10160 a compare/branch to test the input value to see which instruction
10161 we need to use. This gets pretty messy, but it is feasible. */
10162
10163 int
10164 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10165 enum reg_class to, enum reg_class from)
10166 {
10167 if (from == M16_REGS && reg_class_subset_p (to, GENERAL_REGS))
10168 return 2;
10169 else if (from == M16_NA_REGS && reg_class_subset_p (to, GENERAL_REGS))
10170 return 2;
10171 else if (reg_class_subset_p (from, GENERAL_REGS))
10172 {
10173 if (to == M16_REGS)
10174 return 2;
10175 else if (to == M16_NA_REGS)
10176 return 2;
10177 else if (reg_class_subset_p (to, GENERAL_REGS))
10178 {
10179 if (TARGET_MIPS16)
10180 return 4;
10181 else
10182 return 2;
10183 }
10184 else if (to == FP_REGS)
10185 return 4;
10186 else if (reg_class_subset_p (to, ACC_REGS))
10187 {
10188 if (TARGET_MIPS16)
10189 return 12;
10190 else
10191 return 6;
10192 }
10193 else if (reg_class_subset_p (to, ALL_COP_REGS))
10194 {
10195 return 5;
10196 }
10197 }
10198 else if (from == FP_REGS)
10199 {
10200 if (reg_class_subset_p (to, GENERAL_REGS))
10201 return 4;
10202 else if (to == FP_REGS)
10203 return 2;
10204 else if (to == ST_REGS)
10205 return 8;
10206 }
10207 else if (reg_class_subset_p (from, ACC_REGS))
10208 {
10209 if (reg_class_subset_p (to, GENERAL_REGS))
10210 {
10211 if (TARGET_MIPS16)
10212 return 12;
10213 else
10214 return 6;
10215 }
10216 }
10217 else if (from == ST_REGS && reg_class_subset_p (to, GENERAL_REGS))
10218 return 4;
10219 else if (reg_class_subset_p (from, ALL_COP_REGS))
10220 {
10221 return 5;
10222 }
10223
10224 /* Fall through.
10225 ??? What cases are these? Shouldn't we return 2 here? */
10226
10227 return 12;
10228 }
10229
10230 /* Return the length of INSN. LENGTH is the initial length computed by
10231 attributes in the machine-description file. */
10232
10233 int
10234 mips_adjust_insn_length (rtx insn, int length)
10235 {
10236 /* A unconditional jump has an unfilled delay slot if it is not part
10237 of a sequence. A conditional jump normally has a delay slot, but
10238 does not on MIPS16. */
10239 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
10240 length += 4;
10241
10242 /* See how many nops might be needed to avoid hardware hazards. */
10243 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
10244 switch (get_attr_hazard (insn))
10245 {
10246 case HAZARD_NONE:
10247 break;
10248
10249 case HAZARD_DELAY:
10250 length += 4;
10251 break;
10252
10253 case HAZARD_HILO:
10254 length += 8;
10255 break;
10256 }
10257
10258 /* All MIPS16 instructions are a measly two bytes. */
10259 if (TARGET_MIPS16)
10260 length /= 2;
10261
10262 return length;
10263 }
10264
10265
10266 /* Return an asm sequence to start a noat block and load the address
10267 of a label into $1. */
10268
10269 const char *
10270 mips_output_load_label (void)
10271 {
10272 if (TARGET_EXPLICIT_RELOCS)
10273 switch (mips_abi)
10274 {
10275 case ABI_N32:
10276 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10277
10278 case ABI_64:
10279 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10280
10281 default:
10282 if (ISA_HAS_LOAD_DELAY)
10283 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10284 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10285 }
10286 else
10287 {
10288 if (Pmode == DImode)
10289 return "%[dla\t%@,%0";
10290 else
10291 return "%[la\t%@,%0";
10292 }
10293 }
10294
10295 /* Return the assembly code for INSN, which has the operands given by
10296 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10297 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10298 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10299 version of BRANCH_IF_TRUE. */
10300
10301 const char *
10302 mips_output_conditional_branch (rtx insn, rtx *operands,
10303 const char *branch_if_true,
10304 const char *branch_if_false)
10305 {
10306 unsigned int length;
10307 rtx taken, not_taken;
10308
10309 length = get_attr_length (insn);
10310 if (length <= 8)
10311 {
10312 /* Just a simple conditional branch. */
10313 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10314 return branch_if_true;
10315 }
10316
10317 /* Generate a reversed branch around a direct jump. This fallback does
10318 not use branch-likely instructions. */
10319 mips_branch_likely = false;
10320 not_taken = gen_label_rtx ();
10321 taken = operands[1];
10322
10323 /* Generate the reversed branch to NOT_TAKEN. */
10324 operands[1] = not_taken;
10325 output_asm_insn (branch_if_false, operands);
10326
10327 /* If INSN has a delay slot, we must provide delay slots for both the
10328 branch to NOT_TAKEN and the conditional jump. We must also ensure
10329 that INSN's delay slot is executed in the appropriate cases. */
10330 if (final_sequence)
10331 {
10332 /* This first delay slot will always be executed, so use INSN's
10333 delay slot if is not annulled. */
10334 if (!INSN_ANNULLED_BRANCH_P (insn))
10335 {
10336 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10337 asm_out_file, optimize, 1, NULL);
10338 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10339 }
10340 else
10341 output_asm_insn ("nop", 0);
10342 fprintf (asm_out_file, "\n");
10343 }
10344
10345 /* Output the unconditional branch to TAKEN. */
10346 if (length <= 16)
10347 output_asm_insn ("j\t%0%/", &taken);
10348 else
10349 {
10350 output_asm_insn (mips_output_load_label (), &taken);
10351 output_asm_insn ("jr\t%@%]%/", 0);
10352 }
10353
10354 /* Now deal with its delay slot; see above. */
10355 if (final_sequence)
10356 {
10357 /* This delay slot will only be executed if the branch is taken.
10358 Use INSN's delay slot if is annulled. */
10359 if (INSN_ANNULLED_BRANCH_P (insn))
10360 {
10361 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10362 asm_out_file, optimize, 1, NULL);
10363 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10364 }
10365 else
10366 output_asm_insn ("nop", 0);
10367 fprintf (asm_out_file, "\n");
10368 }
10369
10370 /* Output NOT_TAKEN. */
10371 (*targetm.asm_out.internal_label) (asm_out_file, "L",
10372 CODE_LABEL_NUMBER (not_taken));
10373 return "";
10374 }
10375
10376 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10377 if some ordered condition is true. The condition is given by
10378 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10379 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10380 its second is always zero. */
10381
10382 const char *
10383 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
10384 {
10385 const char *branch[2];
10386
10387 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10388 Make BRANCH[0] branch on the inverse condition. */
10389 switch (GET_CODE (operands[0]))
10390 {
10391 /* These cases are equivalent to comparisons against zero. */
10392 case LEU:
10393 inverted_p = !inverted_p;
10394 /* Fall through. */
10395 case GTU:
10396 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
10397 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
10398 break;
10399
10400 /* These cases are always true or always false. */
10401 case LTU:
10402 inverted_p = !inverted_p;
10403 /* Fall through. */
10404 case GEU:
10405 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
10406 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
10407 break;
10408
10409 default:
10410 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
10411 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
10412 break;
10413 }
10414 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
10415 }
10416 \f
10417 /* Used to output div or ddiv instruction DIVISION, which has the operands
10418 given by OPERANDS. Add in a divide-by-zero check if needed.
10419
10420 When working around R4000 and R4400 errata, we need to make sure that
10421 the division is not immediately followed by a shift[1][2]. We also
10422 need to stop the division from being put into a branch delay slot[3].
10423 The easiest way to avoid both problems is to add a nop after the
10424 division. When a divide-by-zero check is needed, this nop can be
10425 used to fill the branch delay slot.
10426
10427 [1] If a double-word or a variable shift executes immediately
10428 after starting an integer division, the shift may give an
10429 incorrect result. See quotations of errata #16 and #28 from
10430 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10431 in mips.md for details.
10432
10433 [2] A similar bug to [1] exists for all revisions of the
10434 R4000 and the R4400 when run in an MC configuration.
10435 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
10436
10437 "19. In this following sequence:
10438
10439 ddiv (or ddivu or div or divu)
10440 dsll32 (or dsrl32, dsra32)
10441
10442 if an MPT stall occurs, while the divide is slipping the cpu
10443 pipeline, then the following double shift would end up with an
10444 incorrect result.
10445
10446 Workaround: The compiler needs to avoid generating any
10447 sequence with divide followed by extended double shift."
10448
10449 This erratum is also present in "MIPS R4400MC Errata, Processor
10450 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
10451 & 3.0" as errata #10 and #4, respectively.
10452
10453 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10454 (also valid for MIPS R4000MC processors):
10455
10456 "52. R4000SC: This bug does not apply for the R4000PC.
10457
10458 There are two flavors of this bug:
10459
10460 1) If the instruction just after divide takes an RF exception
10461 (tlb-refill, tlb-invalid) and gets an instruction cache
10462 miss (both primary and secondary) and the line which is
10463 currently in secondary cache at this index had the first
10464 data word, where the bits 5..2 are set, then R4000 would
10465 get a wrong result for the div.
10466
10467 ##1
10468 nop
10469 div r8, r9
10470 ------------------- # end-of page. -tlb-refill
10471 nop
10472 ##2
10473 nop
10474 div r8, r9
10475 ------------------- # end-of page. -tlb-invalid
10476 nop
10477
10478 2) If the divide is in the taken branch delay slot, where the
10479 target takes RF exception and gets an I-cache miss for the
10480 exception vector or where I-cache miss occurs for the
10481 target address, under the above mentioned scenarios, the
10482 div would get wrong results.
10483
10484 ##1
10485 j r2 # to next page mapped or unmapped
10486 div r8,r9 # this bug would be there as long
10487 # as there is an ICache miss and
10488 nop # the "data pattern" is present
10489
10490 ##2
10491 beq r0, r0, NextPage # to Next page
10492 div r8,r9
10493 nop
10494
10495 This bug is present for div, divu, ddiv, and ddivu
10496 instructions.
10497
10498 Workaround: For item 1), OS could make sure that the next page
10499 after the divide instruction is also mapped. For item 2), the
10500 compiler could make sure that the divide instruction is not in
10501 the branch delay slot."
10502
10503 These processors have PRId values of 0x00004220 and 0x00004300 for
10504 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
10505
10506 const char *
10507 mips_output_division (const char *division, rtx *operands)
10508 {
10509 const char *s;
10510
10511 s = division;
10512 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
10513 {
10514 output_asm_insn (s, operands);
10515 s = "nop";
10516 }
10517 if (TARGET_CHECK_ZERO_DIV)
10518 {
10519 if (TARGET_MIPS16)
10520 {
10521 output_asm_insn (s, operands);
10522 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
10523 }
10524 else if (GENERATE_DIVIDE_TRAPS)
10525 {
10526 output_asm_insn (s, operands);
10527 s = "teq\t%2,%.,7";
10528 }
10529 else
10530 {
10531 output_asm_insn ("%(bne\t%2,%.,1f", operands);
10532 output_asm_insn (s, operands);
10533 s = "break\t7%)\n1:";
10534 }
10535 }
10536 return s;
10537 }
10538 \f
10539 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
10540 with a final "000" replaced by "k". Ignore case.
10541
10542 Note: this function is shared between GCC and GAS. */
10543
10544 static bool
10545 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
10546 {
10547 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
10548 given++, canonical++;
10549
10550 return ((*given == 0 && *canonical == 0)
10551 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
10552 }
10553
10554
10555 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
10556 CPU name. We've traditionally allowed a lot of variation here.
10557
10558 Note: this function is shared between GCC and GAS. */
10559
10560 static bool
10561 mips_matching_cpu_name_p (const char *canonical, const char *given)
10562 {
10563 /* First see if the name matches exactly, or with a final "000"
10564 turned into "k". */
10565 if (mips_strict_matching_cpu_name_p (canonical, given))
10566 return true;
10567
10568 /* If not, try comparing based on numerical designation alone.
10569 See if GIVEN is an unadorned number, or 'r' followed by a number. */
10570 if (TOLOWER (*given) == 'r')
10571 given++;
10572 if (!ISDIGIT (*given))
10573 return false;
10574
10575 /* Skip over some well-known prefixes in the canonical name,
10576 hoping to find a number there too. */
10577 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
10578 canonical += 2;
10579 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
10580 canonical += 2;
10581 else if (TOLOWER (canonical[0]) == 'r')
10582 canonical += 1;
10583
10584 return mips_strict_matching_cpu_name_p (canonical, given);
10585 }
10586
10587
10588 /* Return the mips_cpu_info entry for the processor or ISA given
10589 by CPU_STRING. Return null if the string isn't recognized.
10590
10591 A similar function exists in GAS. */
10592
10593 static const struct mips_cpu_info *
10594 mips_parse_cpu (const char *cpu_string)
10595 {
10596 const struct mips_cpu_info *p;
10597 const char *s;
10598
10599 /* In the past, we allowed upper-case CPU names, but it doesn't
10600 work well with the multilib machinery. */
10601 for (s = cpu_string; *s != 0; s++)
10602 if (ISUPPER (*s))
10603 {
10604 warning (0, "the cpu name must be lower case");
10605 break;
10606 }
10607
10608 /* 'from-abi' selects the most compatible architecture for the given
10609 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
10610 EABIs, we have to decide whether we're using the 32-bit or 64-bit
10611 version. Look first at the -mgp options, if given, otherwise base
10612 the choice on MASK_64BIT in TARGET_DEFAULT. */
10613 if (strcasecmp (cpu_string, "from-abi") == 0)
10614 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
10615 : ABI_NEEDS_64BIT_REGS ? 3
10616 : (TARGET_64BIT ? 3 : 1));
10617
10618 /* 'default' has traditionally been a no-op. Probably not very useful. */
10619 if (strcasecmp (cpu_string, "default") == 0)
10620 return 0;
10621
10622 for (p = mips_cpu_info_table; p->name != 0; p++)
10623 if (mips_matching_cpu_name_p (p->name, cpu_string))
10624 return p;
10625
10626 return 0;
10627 }
10628
10629
10630 /* Return the processor associated with the given ISA level, or null
10631 if the ISA isn't valid. */
10632
10633 static const struct mips_cpu_info *
10634 mips_cpu_info_from_isa (int isa)
10635 {
10636 const struct mips_cpu_info *p;
10637
10638 for (p = mips_cpu_info_table; p->name != 0; p++)
10639 if (p->isa == isa)
10640 return p;
10641
10642 return 0;
10643 }
10644 \f
10645 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
10646 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
10647 they only hold condition code modes, and CCmode is always considered to
10648 be 4 bytes wide. All other registers are word sized. */
10649
10650 unsigned int
10651 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10652 {
10653 if (ST_REG_P (regno))
10654 return ((GET_MODE_SIZE (mode) + 3) / 4);
10655 else if (! FP_REG_P (regno))
10656 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10657 else
10658 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10659 }
10660
10661 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
10662 all BLKmode objects are returned in memory. Under the new (N32 and
10663 64-bit MIPS ABIs) small structures are returned in a register.
10664 Objects with varying size must still be returned in memory, of
10665 course. */
10666
10667 static bool
10668 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
10669 {
10670 if (TARGET_OLDABI)
10671 return (TYPE_MODE (type) == BLKmode);
10672 else
10673 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
10674 || (int_size_in_bytes (type) == -1));
10675 }
10676
10677 static bool
10678 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
10679 {
10680 return !TARGET_OLDABI;
10681 }
10682 \f
10683 /* Return true if INSN is a multiply-add or multiply-subtract
10684 instruction and PREV assigns to the accumulator operand. */
10685
10686 bool
10687 mips_linked_madd_p (rtx prev, rtx insn)
10688 {
10689 rtx x;
10690
10691 x = single_set (insn);
10692 if (x == 0)
10693 return false;
10694
10695 x = SET_SRC (x);
10696
10697 if (GET_CODE (x) == PLUS
10698 && GET_CODE (XEXP (x, 0)) == MULT
10699 && reg_set_p (XEXP (x, 1), prev))
10700 return true;
10701
10702 if (GET_CODE (x) == MINUS
10703 && GET_CODE (XEXP (x, 1)) == MULT
10704 && reg_set_p (XEXP (x, 0), prev))
10705 return true;
10706
10707 return false;
10708 }
10709 \f
10710 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
10711 that may clobber hi or lo. */
10712
10713 static rtx mips_macc_chains_last_hilo;
10714
10715 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
10716 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
10717
10718 static void
10719 mips_macc_chains_record (rtx insn)
10720 {
10721 if (get_attr_may_clobber_hilo (insn))
10722 mips_macc_chains_last_hilo = insn;
10723 }
10724
10725 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
10726 has NREADY elements, looking for a multiply-add or multiply-subtract
10727 instruction that is cumulative with mips_macc_chains_last_hilo.
10728 If there is one, promote it ahead of anything else that might
10729 clobber hi or lo. */
10730
10731 static void
10732 mips_macc_chains_reorder (rtx *ready, int nready)
10733 {
10734 int i, j;
10735
10736 if (mips_macc_chains_last_hilo != 0)
10737 for (i = nready - 1; i >= 0; i--)
10738 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
10739 {
10740 for (j = nready - 1; j > i; j--)
10741 if (recog_memoized (ready[j]) >= 0
10742 && get_attr_may_clobber_hilo (ready[j]))
10743 {
10744 mips_promote_ready (ready, i, j);
10745 break;
10746 }
10747 break;
10748 }
10749 }
10750 \f
10751 /* The last instruction to be scheduled. */
10752
10753 static rtx vr4130_last_insn;
10754
10755 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
10756 points to an rtx that is initially an instruction. Nullify the rtx
10757 if the instruction uses the value of register X. */
10758
10759 static void
10760 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
10761 {
10762 rtx *insn_ptr = data;
10763 if (REG_P (x)
10764 && *insn_ptr != 0
10765 && reg_referenced_p (x, PATTERN (*insn_ptr)))
10766 *insn_ptr = 0;
10767 }
10768
10769 /* Return true if there is true register dependence between vr4130_last_insn
10770 and INSN. */
10771
10772 static bool
10773 vr4130_true_reg_dependence_p (rtx insn)
10774 {
10775 note_stores (PATTERN (vr4130_last_insn),
10776 vr4130_true_reg_dependence_p_1, &insn);
10777 return insn == 0;
10778 }
10779
10780 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
10781 the ready queue and that INSN2 is the instruction after it, return
10782 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
10783 in which INSN1 and INSN2 can probably issue in parallel, but for
10784 which (INSN2, INSN1) should be less sensitive to instruction
10785 alignment than (INSN1, INSN2). See 4130.md for more details. */
10786
10787 static bool
10788 vr4130_swap_insns_p (rtx insn1, rtx insn2)
10789 {
10790 dep_link_t dep;
10791
10792 /* Check for the following case:
10793
10794 1) there is some other instruction X with an anti dependence on INSN1;
10795 2) X has a higher priority than INSN2; and
10796 3) X is an arithmetic instruction (and thus has no unit restrictions).
10797
10798 If INSN1 is the last instruction blocking X, it would better to
10799 choose (INSN1, X) over (INSN2, INSN1). */
10800 FOR_EACH_DEP_LINK (dep, INSN_FORW_DEPS (insn1))
10801 if (DEP_LINK_KIND (dep) == REG_DEP_ANTI
10802 && INSN_PRIORITY (DEP_LINK_CON (dep)) > INSN_PRIORITY (insn2)
10803 && recog_memoized (DEP_LINK_CON (dep)) >= 0
10804 && get_attr_vr4130_class (DEP_LINK_CON (dep)) == VR4130_CLASS_ALU)
10805 return false;
10806
10807 if (vr4130_last_insn != 0
10808 && recog_memoized (insn1) >= 0
10809 && recog_memoized (insn2) >= 0)
10810 {
10811 /* See whether INSN1 and INSN2 use different execution units,
10812 or if they are both ALU-type instructions. If so, they can
10813 probably execute in parallel. */
10814 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
10815 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
10816 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
10817 {
10818 /* If only one of the instructions has a dependence on
10819 vr4130_last_insn, prefer to schedule the other one first. */
10820 bool dep1 = vr4130_true_reg_dependence_p (insn1);
10821 bool dep2 = vr4130_true_reg_dependence_p (insn2);
10822 if (dep1 != dep2)
10823 return dep1;
10824
10825 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
10826 is not an ALU-type instruction and if INSN1 uses the same
10827 execution unit. (Note that if this condition holds, we already
10828 know that INSN2 uses a different execution unit.) */
10829 if (class1 != VR4130_CLASS_ALU
10830 && recog_memoized (vr4130_last_insn) >= 0
10831 && class1 == get_attr_vr4130_class (vr4130_last_insn))
10832 return true;
10833 }
10834 }
10835 return false;
10836 }
10837
10838 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
10839 queue with at least two instructions. Swap the first two if
10840 vr4130_swap_insns_p says that it could be worthwhile. */
10841
10842 static void
10843 vr4130_reorder (rtx *ready, int nready)
10844 {
10845 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
10846 mips_promote_ready (ready, nready - 2, nready - 1);
10847 }
10848 \f
10849 /* Remove the instruction at index LOWER from ready queue READY and
10850 reinsert it in front of the instruction at index HIGHER. LOWER must
10851 be <= HIGHER. */
10852
10853 static void
10854 mips_promote_ready (rtx *ready, int lower, int higher)
10855 {
10856 rtx new_head;
10857 int i;
10858
10859 new_head = ready[lower];
10860 for (i = lower; i < higher; i++)
10861 ready[i] = ready[i + 1];
10862 ready[i] = new_head;
10863 }
10864
10865 /* Implement TARGET_SCHED_REORDER. */
10866
10867 static int
10868 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10869 rtx *ready, int *nreadyp, int cycle)
10870 {
10871 if (!reload_completed && TUNE_MACC_CHAINS)
10872 {
10873 if (cycle == 0)
10874 mips_macc_chains_last_hilo = 0;
10875 if (*nreadyp > 0)
10876 mips_macc_chains_reorder (ready, *nreadyp);
10877 }
10878 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
10879 {
10880 if (cycle == 0)
10881 vr4130_last_insn = 0;
10882 if (*nreadyp > 1)
10883 vr4130_reorder (ready, *nreadyp);
10884 }
10885 return mips_issue_rate ();
10886 }
10887
10888 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10889
10890 static int
10891 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10892 rtx insn, int more)
10893 {
10894 switch (GET_CODE (PATTERN (insn)))
10895 {
10896 case USE:
10897 case CLOBBER:
10898 /* Don't count USEs and CLOBBERs against the issue rate. */
10899 break;
10900
10901 default:
10902 more--;
10903 if (!reload_completed && TUNE_MACC_CHAINS)
10904 mips_macc_chains_record (insn);
10905 vr4130_last_insn = insn;
10906 break;
10907 }
10908 return more;
10909 }
10910 \f
10911 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10912 dependencies have no cost, except on the 20Kc where output-dependence
10913 is treated like input-dependence. */
10914
10915 static int
10916 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
10917 rtx dep ATTRIBUTE_UNUSED, int cost)
10918 {
10919 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
10920 && TUNE_20KC)
10921 return cost;
10922 if (REG_NOTE_KIND (link) != 0)
10923 return 0;
10924 return cost;
10925 }
10926
10927 /* Return the number of instructions that can be issued per cycle. */
10928
10929 static int
10930 mips_issue_rate (void)
10931 {
10932 switch (mips_tune)
10933 {
10934 case PROCESSOR_74KC:
10935 case PROCESSOR_74KF2_1:
10936 case PROCESSOR_74KF1_1:
10937 case PROCESSOR_74KF3_2:
10938 /* The 74k is not strictly quad-issue cpu, but can be seen as one
10939 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
10940 but in reality only a maximum of 3 insns can be issued as the
10941 floating point load/stores also require a slot in the AGEN pipe. */
10942 return 4;
10943
10944 case PROCESSOR_20KC:
10945 case PROCESSOR_R4130:
10946 case PROCESSOR_R5400:
10947 case PROCESSOR_R5500:
10948 case PROCESSOR_R7000:
10949 case PROCESSOR_R9000:
10950 return 2;
10951
10952 case PROCESSOR_SB1:
10953 case PROCESSOR_SB1A:
10954 /* This is actually 4, but we get better performance if we claim 3.
10955 This is partly because of unwanted speculative code motion with the
10956 larger number, and partly because in most common cases we can't
10957 reach the theoretical max of 4. */
10958 return 3;
10959
10960 default:
10961 return 1;
10962 }
10963 }
10964
10965 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
10966 be as wide as the scheduling freedom in the DFA. */
10967
10968 static int
10969 mips_multipass_dfa_lookahead (void)
10970 {
10971 /* Can schedule up to 4 of the 6 function units in any one cycle. */
10972 if (TUNE_SB1)
10973 return 4;
10974
10975 return 0;
10976 }
10977
10978 /* Implements a store data bypass check. We need this because the cprestore
10979 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
10980 default routine to abort. We just return false for that case. */
10981 /* ??? Should try to give a better result here than assuming false. */
10982
10983 int
10984 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10985 {
10986 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10987 return false;
10988
10989 return ! store_data_bypass_p (out_insn, in_insn);
10990 }
10991 \f
10992 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10993 return the first operand of the associated "pref" or "prefx" insn. */
10994
10995 rtx
10996 mips_prefetch_cookie (rtx write, rtx locality)
10997 {
10998 /* store_streamed / load_streamed. */
10999 if (INTVAL (locality) <= 0)
11000 return GEN_INT (INTVAL (write) + 4);
11001
11002 /* store / load. */
11003 if (INTVAL (locality) <= 2)
11004 return write;
11005
11006 /* store_retained / load_retained. */
11007 return GEN_INT (INTVAL (write) + 6);
11008 }
11009 \f
11010 /* MIPS builtin function support. */
11011
11012 struct builtin_description
11013 {
11014 /* The code of the main .md file instruction. See mips_builtin_type
11015 for more information. */
11016 enum insn_code icode;
11017
11018 /* The floating-point comparison code to use with ICODE, if any. */
11019 enum mips_fp_condition cond;
11020
11021 /* The name of the builtin function. */
11022 const char *name;
11023
11024 /* Specifies how the function should be expanded. */
11025 enum mips_builtin_type builtin_type;
11026
11027 /* The function's prototype. */
11028 enum mips_function_type function_type;
11029
11030 /* The target flags required for this function. */
11031 int target_flags;
11032 };
11033
11034 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
11035 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
11036 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
11037 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
11038 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
11039
11040 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
11041 TARGET_FLAGS. */
11042 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
11043 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
11044 "__builtin_mips_" #INSN "_" #COND "_s", \
11045 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
11046 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
11047 "__builtin_mips_" #INSN "_" #COND "_d", \
11048 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
11049
11050 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
11051 The lower and upper forms require TARGET_FLAGS while the any and all
11052 forms require MASK_MIPS3D. */
11053 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
11054 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11055 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
11056 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
11057 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11058 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
11059 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
11060 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11061 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
11062 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
11063 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11064 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
11065 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
11066
11067 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
11068 require MASK_MIPS3D. */
11069 #define CMP_4S_BUILTINS(INSN, COND) \
11070 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
11071 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
11072 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11073 MASK_MIPS3D }, \
11074 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
11075 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
11076 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11077 MASK_MIPS3D }
11078
11079 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
11080 instruction requires TARGET_FLAGS. */
11081 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
11082 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11083 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
11084 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11085 TARGET_FLAGS }, \
11086 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11087 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
11088 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11089 TARGET_FLAGS }
11090
11091 /* Define all the builtins related to c.cond.fmt condition COND. */
11092 #define CMP_BUILTINS(COND) \
11093 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
11094 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
11095 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
11096 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
11097 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
11098 CMP_4S_BUILTINS (c, COND), \
11099 CMP_4S_BUILTINS (cabs, COND)
11100
11101 static const struct builtin_description mips_bdesc[] =
11102 {
11103 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11104 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11105 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11106 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11107 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
11108 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11109 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11110 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11111
11112 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
11113 MASK_PAIRED_SINGLE_FLOAT),
11114 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11115 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11116 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11117 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11118
11119 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
11120 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
11121 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11122 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
11123 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
11124 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11125
11126 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
11127 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
11128 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11129 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
11130 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
11131 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11132
11133 MIPS_FP_CONDITIONS (CMP_BUILTINS)
11134 };
11135
11136 /* Builtin functions for the SB-1 processor. */
11137
11138 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
11139
11140 static const struct builtin_description sb1_bdesc[] =
11141 {
11142 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
11143 };
11144
11145 /* Builtin functions for DSP ASE. */
11146
11147 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
11148 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
11149 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
11150 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
11151 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
11152
11153 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
11154 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
11155 builtin_description fields. */
11156 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
11157 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
11158 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
11159
11160 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
11161 branch instruction. TARGET_FLAGS is a builtin_description field. */
11162 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
11163 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
11164 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
11165
11166 static const struct builtin_description dsp_bdesc[] =
11167 {
11168 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11169 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11170 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11171 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11172 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11173 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11174 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11175 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11176 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11177 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11178 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11179 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11180 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11181 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
11182 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
11183 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
11184 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
11185 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
11186 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
11187 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
11188 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
11189 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
11190 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11191 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11192 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11193 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11194 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11195 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11196 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11197 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11198 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
11199 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11200 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11201 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11202 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
11203 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11204 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11205 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11206 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
11207 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
11208 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11209 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
11210 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
11211 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
11212 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11213 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
11214 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
11215 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11216 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11217 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11218 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11219 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11220 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11221 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11222 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11223 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11224 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11225 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11226 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11227 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
11228 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
11229 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11230 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11231 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11232 BPOSGE_BUILTIN (32, MASK_DSP),
11233
11234 /* The following are for the MIPS DSP ASE REV 2. */
11235 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
11236 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11237 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11238 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11239 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11240 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11241 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11242 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11243 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11244 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11245 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11246 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11247 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11248 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11249 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11250 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11251 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
11252 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
11253 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11254 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
11255 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
11256 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
11257 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11258 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11259 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11260 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11261 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11262 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11263 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11264 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11265 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11266 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11267 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11268 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
11269 };
11270
11271 static const struct builtin_description dsp_32only_bdesc[] =
11272 {
11273 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11274 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11275 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11276 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11277 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11278 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11279 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11280 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
11281 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
11282 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11283 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11284 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11285 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11286 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11287 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11288 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11289 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11290 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11291 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11292 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
11293 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
11294
11295 /* The following are for the MIPS DSP ASE REV 2. */
11296 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11297 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11298 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
11299 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
11300 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
11301 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
11302 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11303 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
11304 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
11305 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11306 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11307 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11308 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11309 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11310 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
11311 };
11312
11313 /* This helps provide a mapping from builtin function codes to bdesc
11314 arrays. */
11315
11316 struct bdesc_map
11317 {
11318 /* The builtin function table that this entry describes. */
11319 const struct builtin_description *bdesc;
11320
11321 /* The number of entries in the builtin function table. */
11322 unsigned int size;
11323
11324 /* The target processor that supports these builtin functions.
11325 PROCESSOR_MAX means we enable them for all processors. */
11326 enum processor_type proc;
11327
11328 /* If the target has these flags, this builtin function table
11329 will not be supported. */
11330 int unsupported_target_flags;
11331 };
11332
11333 static const struct bdesc_map bdesc_arrays[] =
11334 {
11335 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX, 0 },
11336 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1, 0 },
11337 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX, 0 },
11338 { dsp_32only_bdesc, ARRAY_SIZE (dsp_32only_bdesc), PROCESSOR_MAX,
11339 MASK_64BIT }
11340 };
11341
11342 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
11343 suitable for input operand OP of instruction ICODE. Return the value. */
11344
11345 static rtx
11346 mips_prepare_builtin_arg (enum insn_code icode,
11347 unsigned int op, tree exp, unsigned int argnum)
11348 {
11349 rtx value;
11350 enum machine_mode mode;
11351
11352 value = expand_normal (CALL_EXPR_ARG (exp, argnum));
11353 mode = insn_data[icode].operand[op].mode;
11354 if (!insn_data[icode].operand[op].predicate (value, mode))
11355 {
11356 value = copy_to_mode_reg (mode, value);
11357 /* Check the predicate again. */
11358 if (!insn_data[icode].operand[op].predicate (value, mode))
11359 {
11360 error ("invalid argument to builtin function");
11361 return const0_rtx;
11362 }
11363 }
11364
11365 return value;
11366 }
11367
11368 /* Return an rtx suitable for output operand OP of instruction ICODE.
11369 If TARGET is non-null, try to use it where possible. */
11370
11371 static rtx
11372 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
11373 {
11374 enum machine_mode mode;
11375
11376 mode = insn_data[icode].operand[op].mode;
11377 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
11378 target = gen_reg_rtx (mode);
11379
11380 return target;
11381 }
11382
11383 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
11384
11385 rtx
11386 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11387 enum machine_mode mode ATTRIBUTE_UNUSED,
11388 int ignore ATTRIBUTE_UNUSED)
11389 {
11390 enum insn_code icode;
11391 enum mips_builtin_type type;
11392 tree fndecl;
11393 unsigned int fcode;
11394 const struct builtin_description *bdesc;
11395 const struct bdesc_map *m;
11396
11397 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11398 fcode = DECL_FUNCTION_CODE (fndecl);
11399
11400 bdesc = NULL;
11401 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
11402 {
11403 if (fcode < m->size)
11404 {
11405 bdesc = m->bdesc;
11406 icode = bdesc[fcode].icode;
11407 type = bdesc[fcode].builtin_type;
11408 break;
11409 }
11410 fcode -= m->size;
11411 }
11412 if (bdesc == NULL)
11413 return 0;
11414
11415 switch (type)
11416 {
11417 case MIPS_BUILTIN_DIRECT:
11418 return mips_expand_builtin_direct (icode, target, exp, true);
11419
11420 case MIPS_BUILTIN_DIRECT_NO_TARGET:
11421 return mips_expand_builtin_direct (icode, target, exp, false);
11422
11423 case MIPS_BUILTIN_MOVT:
11424 case MIPS_BUILTIN_MOVF:
11425 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
11426 target, exp);
11427
11428 case MIPS_BUILTIN_CMP_ANY:
11429 case MIPS_BUILTIN_CMP_ALL:
11430 case MIPS_BUILTIN_CMP_UPPER:
11431 case MIPS_BUILTIN_CMP_LOWER:
11432 case MIPS_BUILTIN_CMP_SINGLE:
11433 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
11434 target, exp);
11435
11436 case MIPS_BUILTIN_BPOSGE32:
11437 return mips_expand_builtin_bposge (type, target);
11438
11439 default:
11440 return 0;
11441 }
11442 }
11443
11444 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
11445
11446 void
11447 mips_init_builtins (void)
11448 {
11449 const struct builtin_description *d;
11450 const struct bdesc_map *m;
11451 tree types[(int) MIPS_MAX_FTYPE_MAX];
11452 tree V2SF_type_node;
11453 tree V2HI_type_node;
11454 tree V4QI_type_node;
11455 unsigned int offset;
11456
11457 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
11458 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
11459 return;
11460
11461 if (TARGET_PAIRED_SINGLE_FLOAT)
11462 {
11463 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
11464
11465 types[MIPS_V2SF_FTYPE_V2SF]
11466 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
11467
11468 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
11469 = build_function_type_list (V2SF_type_node,
11470 V2SF_type_node, V2SF_type_node, NULL_TREE);
11471
11472 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
11473 = build_function_type_list (V2SF_type_node,
11474 V2SF_type_node, V2SF_type_node,
11475 integer_type_node, NULL_TREE);
11476
11477 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
11478 = build_function_type_list (V2SF_type_node,
11479 V2SF_type_node, V2SF_type_node,
11480 V2SF_type_node, V2SF_type_node, NULL_TREE);
11481
11482 types[MIPS_V2SF_FTYPE_SF_SF]
11483 = build_function_type_list (V2SF_type_node,
11484 float_type_node, float_type_node, NULL_TREE);
11485
11486 types[MIPS_INT_FTYPE_V2SF_V2SF]
11487 = build_function_type_list (integer_type_node,
11488 V2SF_type_node, V2SF_type_node, NULL_TREE);
11489
11490 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
11491 = build_function_type_list (integer_type_node,
11492 V2SF_type_node, V2SF_type_node,
11493 V2SF_type_node, V2SF_type_node, NULL_TREE);
11494
11495 types[MIPS_INT_FTYPE_SF_SF]
11496 = build_function_type_list (integer_type_node,
11497 float_type_node, float_type_node, NULL_TREE);
11498
11499 types[MIPS_INT_FTYPE_DF_DF]
11500 = build_function_type_list (integer_type_node,
11501 double_type_node, double_type_node, NULL_TREE);
11502
11503 types[MIPS_SF_FTYPE_V2SF]
11504 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
11505
11506 types[MIPS_SF_FTYPE_SF]
11507 = build_function_type_list (float_type_node,
11508 float_type_node, NULL_TREE);
11509
11510 types[MIPS_SF_FTYPE_SF_SF]
11511 = build_function_type_list (float_type_node,
11512 float_type_node, float_type_node, NULL_TREE);
11513
11514 types[MIPS_DF_FTYPE_DF]
11515 = build_function_type_list (double_type_node,
11516 double_type_node, NULL_TREE);
11517
11518 types[MIPS_DF_FTYPE_DF_DF]
11519 = build_function_type_list (double_type_node,
11520 double_type_node, double_type_node, NULL_TREE);
11521 }
11522
11523 if (TARGET_DSP)
11524 {
11525 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
11526 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
11527
11528 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
11529 = build_function_type_list (V2HI_type_node,
11530 V2HI_type_node, V2HI_type_node,
11531 NULL_TREE);
11532
11533 types[MIPS_SI_FTYPE_SI_SI]
11534 = build_function_type_list (intSI_type_node,
11535 intSI_type_node, intSI_type_node,
11536 NULL_TREE);
11537
11538 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
11539 = build_function_type_list (V4QI_type_node,
11540 V4QI_type_node, V4QI_type_node,
11541 NULL_TREE);
11542
11543 types[MIPS_SI_FTYPE_V4QI]
11544 = build_function_type_list (intSI_type_node,
11545 V4QI_type_node,
11546 NULL_TREE);
11547
11548 types[MIPS_V2HI_FTYPE_V2HI]
11549 = build_function_type_list (V2HI_type_node,
11550 V2HI_type_node,
11551 NULL_TREE);
11552
11553 types[MIPS_SI_FTYPE_SI]
11554 = build_function_type_list (intSI_type_node,
11555 intSI_type_node,
11556 NULL_TREE);
11557
11558 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
11559 = build_function_type_list (V4QI_type_node,
11560 V2HI_type_node, V2HI_type_node,
11561 NULL_TREE);
11562
11563 types[MIPS_V2HI_FTYPE_SI_SI]
11564 = build_function_type_list (V2HI_type_node,
11565 intSI_type_node, intSI_type_node,
11566 NULL_TREE);
11567
11568 types[MIPS_SI_FTYPE_V2HI]
11569 = build_function_type_list (intSI_type_node,
11570 V2HI_type_node,
11571 NULL_TREE);
11572
11573 types[MIPS_V2HI_FTYPE_V4QI]
11574 = build_function_type_list (V2HI_type_node,
11575 V4QI_type_node,
11576 NULL_TREE);
11577
11578 types[MIPS_V4QI_FTYPE_V4QI_SI]
11579 = build_function_type_list (V4QI_type_node,
11580 V4QI_type_node, intSI_type_node,
11581 NULL_TREE);
11582
11583 types[MIPS_V2HI_FTYPE_V2HI_SI]
11584 = build_function_type_list (V2HI_type_node,
11585 V2HI_type_node, intSI_type_node,
11586 NULL_TREE);
11587
11588 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
11589 = build_function_type_list (V2HI_type_node,
11590 V4QI_type_node, V2HI_type_node,
11591 NULL_TREE);
11592
11593 types[MIPS_SI_FTYPE_V2HI_V2HI]
11594 = build_function_type_list (intSI_type_node,
11595 V2HI_type_node, V2HI_type_node,
11596 NULL_TREE);
11597
11598 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
11599 = build_function_type_list (intDI_type_node,
11600 intDI_type_node, V4QI_type_node, V4QI_type_node,
11601 NULL_TREE);
11602
11603 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
11604 = build_function_type_list (intDI_type_node,
11605 intDI_type_node, V2HI_type_node, V2HI_type_node,
11606 NULL_TREE);
11607
11608 types[MIPS_DI_FTYPE_DI_SI_SI]
11609 = build_function_type_list (intDI_type_node,
11610 intDI_type_node, intSI_type_node, intSI_type_node,
11611 NULL_TREE);
11612
11613 types[MIPS_V4QI_FTYPE_SI]
11614 = build_function_type_list (V4QI_type_node,
11615 intSI_type_node,
11616 NULL_TREE);
11617
11618 types[MIPS_V2HI_FTYPE_SI]
11619 = build_function_type_list (V2HI_type_node,
11620 intSI_type_node,
11621 NULL_TREE);
11622
11623 types[MIPS_VOID_FTYPE_V4QI_V4QI]
11624 = build_function_type_list (void_type_node,
11625 V4QI_type_node, V4QI_type_node,
11626 NULL_TREE);
11627
11628 types[MIPS_SI_FTYPE_V4QI_V4QI]
11629 = build_function_type_list (intSI_type_node,
11630 V4QI_type_node, V4QI_type_node,
11631 NULL_TREE);
11632
11633 types[MIPS_VOID_FTYPE_V2HI_V2HI]
11634 = build_function_type_list (void_type_node,
11635 V2HI_type_node, V2HI_type_node,
11636 NULL_TREE);
11637
11638 types[MIPS_SI_FTYPE_DI_SI]
11639 = build_function_type_list (intSI_type_node,
11640 intDI_type_node, intSI_type_node,
11641 NULL_TREE);
11642
11643 types[MIPS_DI_FTYPE_DI_SI]
11644 = build_function_type_list (intDI_type_node,
11645 intDI_type_node, intSI_type_node,
11646 NULL_TREE);
11647
11648 types[MIPS_VOID_FTYPE_SI_SI]
11649 = build_function_type_list (void_type_node,
11650 intSI_type_node, intSI_type_node,
11651 NULL_TREE);
11652
11653 types[MIPS_SI_FTYPE_PTR_SI]
11654 = build_function_type_list (intSI_type_node,
11655 ptr_type_node, intSI_type_node,
11656 NULL_TREE);
11657
11658 types[MIPS_SI_FTYPE_VOID]
11659 = build_function_type (intSI_type_node, void_list_node);
11660
11661 if (TARGET_DSPR2)
11662 {
11663 types[MIPS_V4QI_FTYPE_V4QI]
11664 = build_function_type_list (V4QI_type_node,
11665 V4QI_type_node,
11666 NULL_TREE);
11667
11668 types[MIPS_SI_FTYPE_SI_SI_SI]
11669 = build_function_type_list (intSI_type_node,
11670 intSI_type_node, intSI_type_node,
11671 intSI_type_node, NULL_TREE);
11672
11673 types[MIPS_DI_FTYPE_DI_USI_USI]
11674 = build_function_type_list (intDI_type_node,
11675 intDI_type_node,
11676 unsigned_intSI_type_node,
11677 unsigned_intSI_type_node, NULL_TREE);
11678
11679 types[MIPS_DI_FTYPE_SI_SI]
11680 = build_function_type_list (intDI_type_node,
11681 intSI_type_node, intSI_type_node,
11682 NULL_TREE);
11683
11684 types[MIPS_DI_FTYPE_USI_USI]
11685 = build_function_type_list (intDI_type_node,
11686 unsigned_intSI_type_node,
11687 unsigned_intSI_type_node, NULL_TREE);
11688
11689 types[MIPS_V2HI_FTYPE_SI_SI_SI]
11690 = build_function_type_list (V2HI_type_node,
11691 intSI_type_node, intSI_type_node,
11692 intSI_type_node, NULL_TREE);
11693
11694 }
11695 }
11696
11697 /* Iterate through all of the bdesc arrays, initializing all of the
11698 builtin functions. */
11699
11700 offset = 0;
11701 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
11702 {
11703 if ((m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
11704 && (m->unsupported_target_flags & target_flags) == 0)
11705 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
11706 if ((d->target_flags & target_flags) == d->target_flags)
11707 add_builtin_function (d->name, types[d->function_type],
11708 d - m->bdesc + offset,
11709 BUILT_IN_MD, NULL, NULL);
11710 offset += m->size;
11711 }
11712 }
11713
11714 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
11715 .md pattern and CALL is the function expr with arguments. TARGET,
11716 if nonnull, suggests a good place to put the result.
11717 HAS_TARGET indicates the function must return something. */
11718
11719 static rtx
11720 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
11721 bool has_target)
11722 {
11723 rtx ops[MAX_RECOG_OPERANDS];
11724 int i = 0;
11725 int j = 0;
11726
11727 if (has_target)
11728 {
11729 /* We save target to ops[0]. */
11730 ops[0] = mips_prepare_builtin_target (icode, 0, target);
11731 i = 1;
11732 }
11733
11734 /* We need to test if the arglist is not zero. Some instructions have extra
11735 clobber registers. */
11736 for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
11737 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11738
11739 switch (i)
11740 {
11741 case 2:
11742 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
11743 break;
11744
11745 case 3:
11746 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
11747 break;
11748
11749 case 4:
11750 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
11751 break;
11752
11753 default:
11754 gcc_unreachable ();
11755 }
11756 return target;
11757 }
11758
11759 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
11760 function (TYPE says which). EXP is the tree for the function
11761 function, ICODE is the instruction that should be used to compare
11762 the first two arguments, and COND is the condition it should test.
11763 TARGET, if nonnull, suggests a good place to put the result. */
11764
11765 static rtx
11766 mips_expand_builtin_movtf (enum mips_builtin_type type,
11767 enum insn_code icode, enum mips_fp_condition cond,
11768 rtx target, tree exp)
11769 {
11770 rtx cmp_result, op0, op1;
11771
11772 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11773 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
11774 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
11775 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
11776
11777 icode = CODE_FOR_mips_cond_move_tf_ps;
11778 target = mips_prepare_builtin_target (icode, 0, target);
11779 if (type == MIPS_BUILTIN_MOVT)
11780 {
11781 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
11782 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
11783 }
11784 else
11785 {
11786 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
11787 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
11788 }
11789 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
11790 return target;
11791 }
11792
11793 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
11794 into TARGET otherwise. Return TARGET. */
11795
11796 static rtx
11797 mips_builtin_branch_and_move (rtx condition, rtx target,
11798 rtx value_if_true, rtx value_if_false)
11799 {
11800 rtx true_label, done_label;
11801
11802 true_label = gen_label_rtx ();
11803 done_label = gen_label_rtx ();
11804
11805 /* First assume that CONDITION is false. */
11806 emit_move_insn (target, value_if_false);
11807
11808 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
11809 emit_jump_insn (gen_condjump (condition, true_label));
11810 emit_jump_insn (gen_jump (done_label));
11811 emit_barrier ();
11812
11813 /* Fix TARGET if CONDITION is true. */
11814 emit_label (true_label);
11815 emit_move_insn (target, value_if_true);
11816
11817 emit_label (done_label);
11818 return target;
11819 }
11820
11821 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
11822 of the comparison instruction and COND is the condition it should test.
11823 EXP is the function call and arguments and TARGET, if nonnull,
11824 suggests a good place to put the boolean result. */
11825
11826 static rtx
11827 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
11828 enum insn_code icode, enum mips_fp_condition cond,
11829 rtx target, tree exp)
11830 {
11831 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
11832 int i;
11833 int j = 0;
11834
11835 if (target == 0 || GET_MODE (target) != SImode)
11836 target = gen_reg_rtx (SImode);
11837
11838 /* Prepare the operands to the comparison. */
11839 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11840 for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
11841 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11842
11843 switch (insn_data[icode].n_operands)
11844 {
11845 case 4:
11846 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
11847 break;
11848
11849 case 6:
11850 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
11851 ops[3], ops[4], GEN_INT (cond)));
11852 break;
11853
11854 default:
11855 gcc_unreachable ();
11856 }
11857
11858 /* If the comparison sets more than one register, we define the result
11859 to be 0 if all registers are false and -1 if all registers are true.
11860 The value of the complete result is indeterminate otherwise. */
11861 switch (builtin_type)
11862 {
11863 case MIPS_BUILTIN_CMP_ALL:
11864 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
11865 return mips_builtin_branch_and_move (condition, target,
11866 const0_rtx, const1_rtx);
11867
11868 case MIPS_BUILTIN_CMP_UPPER:
11869 case MIPS_BUILTIN_CMP_LOWER:
11870 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
11871 condition = gen_single_cc (cmp_result, offset);
11872 return mips_builtin_branch_and_move (condition, target,
11873 const1_rtx, const0_rtx);
11874
11875 default:
11876 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
11877 return mips_builtin_branch_and_move (condition, target,
11878 const1_rtx, const0_rtx);
11879 }
11880 }
11881
11882 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
11883 suggests a good place to put the boolean result. */
11884
11885 static rtx
11886 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
11887 {
11888 rtx condition, cmp_result;
11889 int cmp_value;
11890
11891 if (target == 0 || GET_MODE (target) != SImode)
11892 target = gen_reg_rtx (SImode);
11893
11894 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
11895
11896 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
11897 cmp_value = 32;
11898 else
11899 gcc_assert (0);
11900
11901 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
11902 return mips_builtin_branch_and_move (condition, target,
11903 const1_rtx, const0_rtx);
11904 }
11905 \f
11906 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
11907 FIRST is true if this is the first time handling this decl. */
11908
11909 static void
11910 mips_encode_section_info (tree decl, rtx rtl, int first)
11911 {
11912 default_encode_section_info (decl, rtl, first);
11913
11914 if (TREE_CODE (decl) == FUNCTION_DECL)
11915 {
11916 rtx symbol = XEXP (rtl, 0);
11917
11918 if ((TARGET_LONG_CALLS && !mips_near_type_p (TREE_TYPE (decl)))
11919 || mips_far_type_p (TREE_TYPE (decl)))
11920 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
11921 }
11922 }
11923
11924 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
11925 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
11926
11927 static void
11928 mips_extra_live_on_entry (bitmap regs)
11929 {
11930 if (TARGET_USE_GOT && !TARGET_ABSOLUTE_ABICALLS)
11931 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
11932 }
11933
11934 /* SImode values are represented as sign-extended to DImode. */
11935
11936 int
11937 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11938 {
11939 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11940 return SIGN_EXTEND;
11941
11942 return UNKNOWN;
11943 }
11944 \f
11945 /* MIPS implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
11946
11947 static void
11948 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
11949 {
11950 switch (size)
11951 {
11952 case 4:
11953 fputs ("\t.dtprelword\t", file);
11954 break;
11955
11956 case 8:
11957 fputs ("\t.dtpreldword\t", file);
11958 break;
11959
11960 default:
11961 gcc_unreachable ();
11962 }
11963 output_addr_const (file, x);
11964 fputs ("+0x8000", file);
11965 }
11966 \f
11967 #include "gt-mips.h"
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