gcc/config/s390/vx-builtins.md

   1 ;;- Instruction patterns for the System z vector facility builtins.
   2 ;;  Copyright (C) 2015-2017 Free Software Foundation, Inc.
   3 ;;  Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it under
   8 ;; the terms of the GNU General Public License as published by the Free
   9 ;; Software Foundation; either version 3, or (at your option) any later
  10 ;; version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 ;; for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ; The patterns in this file are enabled with -mzvector
  22
  23 (define_mode_iterator V_HW_32_64 [V4SI V2DI V2DF (V4SF "TARGET_VXE")])
  24 (define_mode_iterator VI_HW_SD [V4SI V2DI])
  25 (define_mode_iterator V_HW_HSD [V8HI V4SI V2DI V2DF])
  26 (define_mode_iterator V_HW_4 [V4SI V4SF])
  27 ; Full size vector modes with more than one element which are directly supported in vector registers by the hardware.
  28 (define_mode_iterator VEC_HW  [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")])
  29 (define_mode_iterator VECF_HW [(V4SF "TARGET_VXE") V2DF])
  30
  31 ; The element type of the vector with floating point modes translated
  32 ; to int modes of the same size.
  33 (define_mode_attr non_vec_int[(V1QI "QI") (V2QI "QI") (V4QI "QI") (V8QI "QI") (V16QI "QI")
  34                               (V1HI "HI") (V2HI "HI") (V4HI "HI") (V8HI "HI")
  35                               (V1SI "SI") (V2SI "SI") (V4SI "SI")
  36                               (V1DI "DI") (V2DI "DI")
  37                               (V1SF "SI") (V2SF "SI") (V4SF "SI")
  38                               (V1DF "DI") (V2DF "DI")])
  39
  40 ; Condition code modes generated by int comparisons
  41 (define_mode_iterator VICMP [CCVEQ CCVIH CCVIHU])
  42
  43 ; Comparisons supported by the vec_cmp* builtins
  44 (define_code_iterator intcmp [eq gt gtu ge geu lt ltu le leu])
  45 (define_code_iterator fpcmp  [eq gt ge lt le])
  46
  47 ; Comparisons supported by the vec_all/any* builtins
  48 (define_code_iterator intcmpcc [eq ne gt ge lt le gtu geu ltu leu])
  49 (define_code_iterator fpcmpcc  [eq ne gt ge unle unlt lt le])
  50
  51 ; Flags for vector string instructions (vfae all 4, vfee only ZS and CS, vstrc all 4)
  52 (define_constants
  53   [(VSTRING_FLAG_IN         8)   ; invert result
  54    (VSTRING_FLAG_RT         4)   ; result type
  55    (VSTRING_FLAG_ZS         2)   ; zero search
  56    (VSTRING_FLAG_CS         1)]) ; condition code set
  57
  58 ; Rounding modes as being used for e.g. VFI
  59 (define_constants
  60   [(VEC_RND_CURRENT                0)
  61    (VEC_RND_NEAREST_AWAY_FROM_ZERO 1)
  62    (VEC_RND_SHORT_PREC             3)
  63    (VEC_RND_NEAREST_TO_EVEN        4)
  64    (VEC_RND_TO_ZERO                5)
  65    (VEC_RND_TO_INF                 6)
  66    (VEC_RND_TO_MINF                7)])
  67
  68 ; Inexact suppression facility flag as being used for e.g. VFI
  69 (define_constants
  70   [(VEC_INEXACT                0)
  71    (VEC_NOINEXACT              4)])
  72
  73
  74 ; Vector gather element
  75
  76 ; vgef, vgeg
  77 (define_insn "vec_gather_element<mode>"
  78   [(set (match_operand:V_HW_32_64                     0 "register_operand"  "=v")
  79         (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand"   "0")
  80                             (match_operand:<tointvec> 2 "register_operand"   "v")
  81                             (match_operand:BLK        3 "memory_operand"     "R")
  82                             (match_operand:QI         4 "const_mask_operand" "C")]
  83                            UNSPEC_VEC_GATHER))]
  84   "TARGET_VX && UINTVAL (operands[4]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
  85   "vge<bhfgq>\t%0,%O3(%v2,%R3),%b4"
  86   [(set_attr "op_type" "VRV")])
  87
  88 (define_expand "vec_genmask<mode>"
  89   [(match_operand:VI_HW 0 "register_operand" "=v")
  90    (match_operand:QI    1 "const_int_operand" "C")
  91    (match_operand:QI    2 "const_int_operand" "C")]
  92   "TARGET_VX"
  93 {
  94   int nunits = GET_MODE_NUNITS (<VI_HW:MODE>mode);
  95   int bitlen = GET_MODE_UNIT_BITSIZE (<VI_HW:MODE>mode);
  96   /* To bit little endian style.  */
  97   int end = bitlen - 1 - INTVAL (operands[1]);
  98   int start = bitlen - 1 - INTVAL (operands[2]);
  99   rtx const_vec[16];
 100   int i;
 101   unsigned HOST_WIDE_INT mask;
 102   bool swapped_p = false;
 103
 104   if (start > end)
 105     {
 106       i = start - 1; start = end + 1; end = i;
 107       swapped_p = true;
 108     }
 109   if (end == 63)
 110     mask = HOST_WIDE_INT_M1U;
 111   else
 112     mask = (HOST_WIDE_INT_1U << (end + 1)) - 1;
 113
 114   mask &= ~((HOST_WIDE_INT_1U << start) - 1);
 115
 116   if (swapped_p)
 117     mask = ~mask;
 118
 119   for (i = 0; i < nunits; i++)
 120     const_vec[i] = GEN_INT (trunc_int_for_mode (mask,
 121                               GET_MODE_INNER (<VI_HW:MODE>mode)));
 122
 123   emit_insn (gen_rtx_SET (operands[0],
 124                           gen_rtx_CONST_VECTOR (<VI_HW:MODE>mode,
 125                                                 gen_rtvec_v (nunits, const_vec))));
 126   DONE;
 127 })
 128
 129 (define_expand "vec_genbytemaskv16qi"
 130   [(match_operand:V16QI 0 "register_operand"  "")
 131    (match_operand:HI    1 "const_int_operand" "")]
 132   "TARGET_VX"
 133 {
 134   int i;
 135   unsigned mask = 0x8000;
 136   rtx const_vec[16];
 137   unsigned HOST_WIDE_INT byte_mask = UINTVAL (operands[1]);
 138
 139   for (i = 0; i < 16; i++)
 140     {
 141       if (mask & byte_mask)
 142         const_vec[i] = constm1_rtx;
 143       else
 144         const_vec[i] = const0_rtx;
 145       mask = mask >> 1;
 146     }
 147   emit_insn (gen_rtx_SET (operands[0],
 148                           gen_rtx_CONST_VECTOR (V16QImode,
 149                                                 gen_rtvec_v (16, const_vec))));
 150   DONE;
 151 })
 152
 153 (define_expand "vec_splats<mode>"
 154   [(set (match_operand:VEC_HW                          0 "register_operand" "")
 155         (vec_duplicate:VEC_HW (match_operand:<non_vec> 1 "general_operand"  "")))]
 156   "TARGET_VX")
 157
 158 (define_expand "vec_insert<mode>"
 159   [(set (match_operand:VEC_HW                    0 "register_operand" "")
 160         (unspec:VEC_HW [(match_operand:<non_vec> 2 "register_operand" "")
 161                         (match_operand:SI        3 "nonmemory_operand" "")
 162                         (match_operand:VEC_HW    1 "register_operand" "")]
 163                        UNSPEC_VEC_SET))]
 164   "TARGET_VX"
 165   "")
 166
 167 ; This is vec_set + modulo arithmetic on the element selector (op 2)
 168 (define_expand "vec_promote<mode>"
 169   [(set (match_operand:VEC_HW                    0 "register_operand" "")
 170         (unspec:VEC_HW [(match_operand:<non_vec> 1 "register_operand" "")
 171                         (match_operand:SI        2 "nonmemory_operand" "")
 172                         (match_dup 0)]
 173                        UNSPEC_VEC_SET))]
 174   "TARGET_VX"
 175   "")
 176
 177 ; vec_extract is also an RTL standard name -> vector.md
 178
 179 ; vllezb, vllezh, vllezf, vllezg
 180 (define_insn "vec_insert_and_zero<mode>"
 181   [(set (match_operand:VEC_HW                    0 "register_operand" "=v")
 182         (unspec:VEC_HW [(match_operand:<non_vec> 1 "memory_operand"    "R")]
 183                        UNSPEC_VEC_INSERT_AND_ZERO))]
 184   "TARGET_VX"
 185   "vllez<bhfgq>\t%v0,%1"
 186   [(set_attr "op_type" "VRX")])
 187
 188 (define_insn "vlbb"
 189   [(set (match_operand:V16QI              0 "register_operand"   "=v")
 190         (unspec:V16QI [(match_operand:BLK 1 "memory_operand"      "R")
 191                        (match_operand:QI  2 "const_mask_operand"  "C")]
 192                       UNSPEC_VEC_LOAD_BNDRY))]
 193   "TARGET_VX && UINTVAL (operands[2]) < 7"
 194   "vlbb\t%v0,%1,%2"
 195   [(set_attr "op_type" "VRX")])
 196
 197 (define_insn "vlrlrv16qi"
 198   [(set (match_operand:V16QI              0 "register_operand"  "=v,v")
 199         (unspec:V16QI [(match_operand:BLK 2 "memory_operand"     "Q,Q")
 200                        (match_operand:SI  1 "nonmemory_operand"  "d,C")]
 201                       UNSPEC_VEC_LOAD_LEN_R))]
 202   "TARGET_VXE"
 203   "@
 204    vlrlr\t%v0,%1,%2
 205    vlrl\t%v0,%2,%1"
 206   [(set_attr "op_type" "VRS,VSI")])
 207
 208
 209 ; FIXME: The following two patterns might using vec_merge. But what is
 210 ; the canonical form: (vec_select (vec_merge op0 op1)) or (vec_merge
 211 ; (vec_select op0) (vec_select op1)
 212 ; vmrhb, vmrhh, vmrhf, vmrhg
 213 (define_insn "vec_mergeh<mode>"
 214   [(set (match_operand:VEC_HW                 0 "register_operand" "=v")
 215         (unspec:VEC_HW [(match_operand:VEC_HW 1 "register_operand"  "v")
 216                         (match_operand:VEC_HW 2 "register_operand"  "v")]
 217                        UNSPEC_VEC_MERGEH))]
 218   "TARGET_VX"
 219   "vmrh<bhfgq>\t%v0,%1,%2"
 220   [(set_attr "op_type" "VRR")])
 221
 222 ; vmrlb, vmrlh, vmrlf, vmrlg
 223 (define_insn "vec_mergel<mode>"
 224   [(set (match_operand:VEC_HW                 0 "register_operand" "=v")
 225         (unspec:VEC_HW [(match_operand:VEC_HW 1 "register_operand"  "v")
 226                         (match_operand:VEC_HW 2 "register_operand"  "v")]
 227                      UNSPEC_VEC_MERGEL))]
 228   "TARGET_VX"
 229   "vmrl<bhfgq>\t%v0,%1,%2"
 230   [(set_attr "op_type" "VRR")])
 231
 232
 233 ; Vector pack
 234
 235 ; vpkh, vpkf, vpkg
 236 (define_insn "vec_pack<mode>"
 237   [(set (match_operand:<vec_half>                    0 "register_operand" "=v")
 238         (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand"  "v")
 239                             (match_operand:VI_HW_HSD 2 "register_operand"  "v")]
 240                            UNSPEC_VEC_PACK))]
 241   "TARGET_VX"
 242   "vpk<bhfgq>\t%v0,%v1,%v2"
 243   [(set_attr "op_type" "VRR")])
 244
 245
 246 ; Vector pack saturate
 247
 248 ; vpksh, vpksf, vpksg
 249 (define_insn "vec_packs<mode>"
 250   [(set (match_operand:<vec_half>                    0 "register_operand" "=v")
 251         (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand"  "v")
 252                             (match_operand:VI_HW_HSD 2 "register_operand"  "v")]
 253                            UNSPEC_VEC_PACK_SATURATE))]
 254   "TARGET_VX"
 255   "vpks<bhfgq>\t%v0,%v1,%v2"
 256   [(set_attr "op_type" "VRR")])
 257
 258
 259 ; This is vec_packs_cc + loading cc into a caller specified memory location.
 260 (define_expand "vec_packs_cc<mode>"
 261   [(parallel
 262     [(set (reg:CCRAW CC_REGNUM)
 263           (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "")
 264                          (match_operand:VI_HW_HSD 2 "register_operand" "")]
 265                         UNSPEC_VEC_PACK_SATURATE_GENCC))
 266      (set (match_operand:<vec_half> 0 "register_operand" "")
 267           (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
 268                              UNSPEC_VEC_PACK_SATURATE_CC))])
 269    (set (match_dup 4)
 270         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
 271    (set (match_operand:SI 3 "memory_operand" "")
 272         (match_dup 4))]
 273   "TARGET_VX"
 274 {
 275   operands[4] = gen_reg_rtx (SImode);
 276 })
 277
 278 ; vpksh, vpksf, vpksg
 279 (define_insn "*vec_packs_cc<mode>"
 280   [(set (reg:CCRAW CC_REGNUM)
 281         (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v")
 282                        (match_operand:VI_HW_HSD 2 "register_operand" "v")]
 283                       UNSPEC_VEC_PACK_SATURATE_GENCC))
 284    (set (match_operand:<vec_half> 0 "register_operand" "=v")
 285         (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
 286                            UNSPEC_VEC_PACK_SATURATE_CC))]
 287   "TARGET_VX"
 288   "vpks<bhfgq>s\t%v0,%v1,%v2"
 289   [(set_attr "op_type" "VRR")])
 290
 291
 292 ; Vector pack logical saturate
 293
 294 ; vpklsh, vpklsf, vpklsg
 295 (define_insn "vec_packsu<mode>"
 296   [(set (match_operand:<vec_half>                    0 "register_operand" "=v")
 297         (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand"  "v")
 298                             (match_operand:VI_HW_HSD 2 "register_operand"  "v")]
 299                            UNSPEC_VEC_PACK_UNSIGNED_SATURATE))]
 300   "TARGET_VX"
 301   "vpkls<bhfgq>\t%v0,%v1,%v2"
 302   [(set_attr "op_type" "VRR")])
 303
 304 ; Emulate saturate unsigned pack on signed operands.
 305 ; Zero out negative elements and continue with the unsigned saturating pack.
 306 (define_expand "vec_packsu_u<mode>"
 307   [(set (match_operand:<vec_half>                    0 "register_operand" "=v")
 308         (unspec:<vec_half> [(match_operand:VI_HW_HSD 1 "register_operand"  "v")
 309                             (match_operand:VI_HW_HSD 2 "register_operand"  "v")]
 310                            UNSPEC_VEC_PACK_UNSIGNED_SATURATE))]
 311   "TARGET_VX"
 312 {
 313    rtx null_vec = CONST0_RTX(<MODE>mode);
 314    machine_mode half_mode;
 315    switch (<MODE>mode)
 316    {
 317      case V8HImode: half_mode = V16QImode; break;
 318      case V4SImode: half_mode = V8HImode; break;
 319      case V2DImode: half_mode = V4SImode; break;
 320      default: gcc_unreachable ();
 321    }
 322    s390_expand_vcond (operands[1], operands[1], null_vec,
 323                       GE, operands[1], null_vec);
 324    s390_expand_vcond (operands[2], operands[2], null_vec,
 325                       GE, operands[2], null_vec);
 326    emit_insn (gen_rtx_SET (operands[0],
 327                            gen_rtx_UNSPEC (half_mode,
 328                                            gen_rtvec (2, operands[1], operands[2]),
 329                                            UNSPEC_VEC_PACK_UNSIGNED_SATURATE)));
 330    DONE;
 331 })
 332
 333 ; This is vec_packsu_cc + loading cc into a caller specified memory location.
 334 ; FIXME: The reg to target mem copy should be issued by reload?!
 335 (define_expand "vec_packsu_cc<mode>"
 336   [(parallel
 337     [(set (reg:CCRAW CC_REGNUM)
 338           (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "")
 339                          (match_operand:VI_HW_HSD 2 "register_operand" "")]
 340                         UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC))
 341      (set (match_operand:<vec_half> 0 "register_operand" "")
 342           (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
 343                              UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC))])
 344    (set (match_dup 4)
 345         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
 346    (set (match_operand:SI 3 "memory_operand" "")
 347         (match_dup 4))]
 348   "TARGET_VX"
 349 {
 350   operands[4] = gen_reg_rtx (SImode);
 351 })
 352
 353 ; vpklsh, vpklsf, vpklsg
 354 (define_insn "*vec_packsu_cc<mode>"
 355   [(set (reg:CCRAW CC_REGNUM)
 356         (unspec:CCRAW [(match_operand:VI_HW_HSD 1 "register_operand" "v")
 357                        (match_operand:VI_HW_HSD 2 "register_operand" "v")]
 358                       UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC))
 359    (set (match_operand:<vec_half> 0 "register_operand" "=v")
 360         (unspec:<vec_half> [(match_dup 1) (match_dup 2)]
 361                            UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC))]
 362   "TARGET_VX"
 363   "vpkls<bhfgq>s\t%v0,%v1,%v2"
 364   [(set_attr "op_type" "VRR")])
 365
 366
 367 ; Vector permute
 368
 369 ; vec_perm is also RTL standard name, but we can only use it for V16QI
 370
 371 (define_insn "vec_zperm<mode>"
 372   [(set (match_operand:V_HW_HSD                   0 "register_operand" "=v")
 373         (unspec:V_HW_HSD [(match_operand:V_HW_HSD 1 "register_operand"  "v")
 374                           (match_operand:V_HW_HSD 2 "register_operand"  "v")
 375                           (match_operand:V16QI    3 "register_operand"  "v")]
 376                          UNSPEC_VEC_PERM))]
 377   "TARGET_VX"
 378   "vperm\t%v0,%v1,%v2,%v3"
 379   [(set_attr "op_type" "VRR")])
 380
 381 (define_expand "vec_permi<mode>"
 382   [(set (match_operand:V_HW_64                  0 "register_operand"   "")
 383         (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand"   "")
 384                          (match_operand:V_HW_64 2 "register_operand"   "")
 385                          (match_operand:QI      3 "const_mask_operand" "")]
 386                         UNSPEC_VEC_PERMI))]
 387   "TARGET_VX"
 388 {
 389   HOST_WIDE_INT val = INTVAL (operands[3]);
 390   operands[3] = GEN_INT ((val & 1) | (val & 2) << 1);
 391 })
 392
 393 (define_insn "*vec_permi<mode>"
 394   [(set (match_operand:V_HW_64                  0 "register_operand"  "=v")
 395         (unspec:V_HW_64 [(match_operand:V_HW_64 1 "register_operand"   "v")
 396                          (match_operand:V_HW_64 2 "register_operand"   "v")
 397                          (match_operand:QI      3 "const_mask_operand" "C")]
 398                         UNSPEC_VEC_PERMI))]
 399   "TARGET_VX && (UINTVAL (operands[3]) & 10) == 0"
 400   "vpdi\t%v0,%v1,%v2,%b3"
 401   [(set_attr "op_type" "VRR")])
 402
 403
 404 ; Vector replicate
 405
 406
 407 ; Replicate from vector element
 408 (define_expand "vec_splat<mode>"
 409   [(set (match_operand:V_HW                      0 "register_operand"  "")
 410         (vec_duplicate:V_HW (vec_select:<non_vec>
 411                              (match_operand:V_HW 1 "register_operand"  "")
 412                              (parallel
 413                               [(match_operand:QI 2 "const_mask_operand" "")]))))]
 414   "TARGET_VX")
 415
 416 ; Vector scatter element
 417
 418 ; vscef, vsceg
 419
 420 ; A 64 bit target address generated from 32 bit elements
 421 (define_insn "vec_scatter_element<V_HW_4:mode>_DI"
 422   [(set (mem:<non_vec>
 423          (plus:DI (zero_extend:DI
 424                    (unspec:SI [(match_operand:V4SI 1 "register_operand"   "v")
 425                                (match_operand:QI   3 "const_mask_operand" "C")]
 426                               UNSPEC_VEC_EXTRACT))
 427                   (match_operand:SI                2 "address_operand"   "ZQ")))
 428         (unspec:<non_vec> [(match_operand:V_HW_4          0 "register_operand"   "v")
 429                            (match_dup 3)] UNSPEC_VEC_EXTRACT))]
 430   "TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4"
 431   "vscef\t%v0,%O2(%v1,%R2),%3"
 432   [(set_attr "op_type" "VRV")])
 433
 434 ; A 31 bit target address is generated from 64 bit elements
 435 ; vsceg
 436 (define_insn "vec_scatter_element<V_HW_64:mode>_SI"
 437   [(set (mem:<non_vec>
 438          (plus:SI (subreg:SI
 439                    (unspec:<non_vec_int> [(match_operand:V_HW_64 1 "register_operand"   "v")
 440                                           (match_operand:QI      3 "const_mask_operand" "C")]
 441                                          UNSPEC_VEC_EXTRACT) 4)
 442                   (match_operand:SI                              2 "address_operand"   "ZQ")))
 443         (unspec:<non_vec> [(match_operand:V_HW_64                0 "register_operand"   "v")
 444                            (match_dup 3)] UNSPEC_VEC_EXTRACT))]
 445   "TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_64:MODE>mode)"
 446   "vsce<V_HW_64:bhfgq>\t%v0,%O2(%v1,%R2),%3"
 447   [(set_attr "op_type" "VRV")])
 448
 449 ; Element size and target address size is the same
 450 ; vscef, vsceg
 451 (define_insn "vec_scatter_element<mode>_<non_vec_int>"
 452   [(set (mem:<non_vec>
 453          (plus:<non_vec_int> (unspec:<non_vec_int>
 454                               [(match_operand:<tointvec> 1 "register_operand"   "v")
 455                                (match_operand:QI         3 "const_mask_operand" "C")]
 456                               UNSPEC_VEC_EXTRACT)
 457                              (match_operand:DI           2 "address_operand"   "ZQ")))
 458         (unspec:<non_vec> [(match_operand:V_HW_32_64     0 "register_operand"   "v")
 459                            (match_dup 3)] UNSPEC_VEC_EXTRACT))]
 460   "TARGET_VX && UINTVAL (operands[3]) < GET_MODE_NUNITS (<V_HW_32_64:MODE>mode)"
 461   "vsce<bhfgq>\t%v0,%O2(%v1,%R2),%3"
 462   [(set_attr "op_type" "VRV")])
 463
 464 ; Depending on the address size we have to expand a different pattern.
 465 ; This however cannot be represented in s390-builtins.def so we do the
 466 ; multiplexing here in the expander.
 467 (define_expand "vec_scatter_element<V_HW_32_64:mode>"
 468   [(match_operand:V_HW_32_64 0 "register_operand" "")
 469    (match_operand:<tointvec> 1 "register_operand" "")
 470    (match_operand 2 "address_operand" "")
 471    (match_operand:QI 3 "const_mask_operand" "")]
 472   "TARGET_VX"
 473 {
 474   if (TARGET_64BIT)
 475     {
 476       PUT_MODE (operands[2], DImode);
 477       emit_insn (
 478         gen_vec_scatter_element<V_HW_32_64:mode>_DI (operands[0], operands[1],
 479                                                      operands[2], operands[3]));
 480     }
 481   else
 482     {
 483       PUT_MODE (operands[2], SImode);
 484       emit_insn (
 485         gen_vec_scatter_element<V_HW_32_64:mode>_SI (operands[0], operands[1],
 486                                                      operands[2], operands[3]));
 487     }
 488   DONE;
 489 })
 490
 491
 492 ; Vector select
 493
 494 ; Operand 3 selects bits from either OP1 (0) or OP2 (1)
 495
 496 ; Comparison operator should not matter as long as we always use the same ?!
 497
 498 ; Operands 1 and 2 are swapped in order to match the altivec builtin.
 499 ; If operand 3 is a const_int bitmask this would be vec_merge
 500 (define_expand "vec_sel<mode>"
 501   [(set (match_operand:V_HW 0 "register_operand" "")
 502         (if_then_else:V_HW
 503          (eq (match_operand:<tointvec> 3 "register_operand"  "")
 504              (match_dup 4))
 505          (match_operand:V_HW 2 "register_operand"  "")
 506          (match_operand:V_HW 1 "register_operand"  "")))]
 507   "TARGET_VX"
 508 {
 509   operands[4] = CONST0_RTX (<tointvec>mode);
 510 })
 511
 512
 513 ; Vector sign extend to doubleword
 514
 515 ; Sign extend of right most vector element to respective double-word
 516 ; vsegb, vsegh, vsegf
 517 (define_insn "vec_extend<mode>"
 518   [(set (match_operand:VI_HW_QHS                    0 "register_operand" "=v")
 519         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "v")]
 520                           UNSPEC_VEC_EXTEND))]
 521   "TARGET_VX"
 522   "vseg<bhfgq>\t%v0,%1"
 523   [(set_attr "op_type" "VRR")])
 524
 525
 526 ; Vector store with length
 527
 528 ; Store bytes in OP1 from OP0 with the highest indexed byte to be
 529 ; stored from OP0 given by OP2
 530 (define_insn "vstl<mode>"
 531   [(set (match_operand:BLK             2 "memory_operand"   "=Q")
 532         (unspec:BLK [(match_operand:V  0 "register_operand"  "v")
 533                      (match_operand:SI 1 "register_operand"  "d")]
 534                     UNSPEC_VEC_STORE_LEN))]
 535   "TARGET_VX"
 536   "vstl\t%v0,%1,%2"
 537   [(set_attr "op_type" "VRS")])
 538
 539 ; Vector store rightmost with length
 540
 541 (define_insn "vstrlrv16qi"
 542   [(set (match_operand:BLK                2 "memory_operand"    "=Q,Q")
 543         (unspec:BLK [(match_operand:V16QI 0 "register_operand"   "v,v")
 544                      (match_operand:SI    1 "nonmemory_operand"  "d,C")]
 545                     UNSPEC_VEC_STORE_LEN_R))]
 546   "TARGET_VXE"
 547   "@
 548    vstrlr\t%v0,%2,%1
 549    vstrl\t%v0,%1,%2"
 550   [(set_attr "op_type" "VRS,VSI")])
 551
 552
 553
 554 ; vector bit permute
 555
 556 (define_insn "vbpermv16qi"
 557   [(set (match_operand:V2DI                0 "register_operand" "=v")
 558         (unspec:V2DI [(match_operand:V16QI 1 "register_operand"  "v")
 559                       (match_operand:V16QI 2 "register_operand"  "v")]
 560                      UNSPEC_VEC_VBPERM))]
 561   "TARGET_VXE"
 562   "vbperm\t%v0,%v1,%v2"
 563   [(set_attr "op_type" "VRR")])
 564
 565 ; Vector unpack high
 566
 567 ; vuphb, vuphh, vuphf
 568 (define_insn "vec_unpackh<mode>"
 569   [(set (match_operand:<vec_double>                    0 "register_operand" "=v")
 570         (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"  "v")]
 571                              UNSPEC_VEC_UNPACKH))]
 572   "TARGET_VX"
 573   "vuph<bhfgq>\t%v0,%v1"
 574   [(set_attr "op_type" "VRR")])
 575
 576 ; vuplhb, vuplhh, vuplhf
 577 (define_insn "vec_unpackh_l<mode>"
 578   [(set (match_operand:<vec_double>                    0 "register_operand" "=v")
 579         (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"  "v")]
 580                              UNSPEC_VEC_UNPACKH_L))]
 581   "TARGET_VX"
 582   "vuplh<bhfgq>\t%v0,%v1"
 583   [(set_attr "op_type" "VRR")])
 584
 585
 586 ; Vector unpack low
 587
 588 ; vuplb, vuplhw, vuplf
 589 (define_insn "vec_unpackl<mode>"
 590   [(set (match_operand:<vec_double>                    0 "register_operand" "=v")
 591         (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"  "v")]
 592                              UNSPEC_VEC_UNPACKL))]
 593   "TARGET_VX"
 594   "vupl<bhfgq><w>\t%v0,%v1"
 595   [(set_attr "op_type" "VRR")])
 596
 597 ; vupllb, vupllh, vupllf
 598 (define_insn "vec_unpackl_l<mode>"
 599   [(set (match_operand:<vec_double>                    0 "register_operand" "=v")
 600         (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"  "v")]
 601                              UNSPEC_VEC_UNPACKL_L))]
 602   "TARGET_VX"
 603   "vupll<bhfgq>\t%v0,%v1"
 604   [(set_attr "op_type" "VRR")])
 605
 606
 607 ; Vector add
 608
 609 ; Vector add compute carry
 610
 611 ; vaccb, vacch, vaccf, vaccg, vaccq
 612 (define_insn "vacc<bhfgq>_<mode>"
 613   [(set (match_operand:VIT_HW                 0 "register_operand" "=v")
 614         (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "%v")
 615                         (match_operand:VIT_HW 2 "register_operand"  "v")]
 616                        UNSPEC_VEC_ADDC))]
 617   "TARGET_VX"
 618   "vacc<bhfgq>\t%v0,%v1,%v2"
 619   [(set_attr "op_type" "VRR")])
 620
 621 ; Vector add with carry
 622
 623 (define_insn "vacq"
 624   [(set (match_operand:TI             0 "register_operand" "=v")
 625         (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
 626                     (match_operand:TI 2 "register_operand"  "v")
 627                     (match_operand:TI 3 "register_operand"  "v")]
 628                    UNSPEC_VEC_ADDE_U128))]
 629   "TARGET_VX"
 630   "vacq\t%v0,%v1,%v2,%v3"
 631   [(set_attr "op_type" "VRR")])
 632
 633
 634 ; Vector add with carry compute carry
 635
 636 (define_insn "vacccq"
 637   [(set (match_operand:TI             0 "register_operand" "=v")
 638         (unspec:TI [(match_operand:TI 1 "register_operand" "%v")
 639                     (match_operand:TI 2 "register_operand"  "v")
 640                     (match_operand:TI 3 "register_operand"  "v")]
 641                    UNSPEC_VEC_ADDEC_U128))]
 642   "TARGET_VX"
 643   "vacccq\t%v0,%v1,%v2,%v3"
 644   [(set_attr "op_type" "VRR")])
 645
 646
 647 ; Vector and
 648
 649 ; Vector and with complement
 650
 651 ; vnc
 652 (define_insn "vec_andc<mode>3"
 653   [(set (match_operand:VT_HW                       0 "register_operand" "=v")
 654         (and:VT_HW (not:VT_HW (match_operand:VT_HW 2 "register_operand"  "v"))
 655                   (match_operand:VT_HW             1 "register_operand"  "v")))]
 656   "TARGET_VX"
 657   "vnc\t%v0,%v1,%v2"
 658   [(set_attr "op_type" "VRR")])
 659
 660
 661 ; Vector average
 662
 663 ; vavgb, vavgh, vavgf, vavgg
 664 (define_insn "vec_avg<mode>"
 665   [(set (match_operand:VI_HW                0 "register_operand" "=v")
 666         (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
 667                        (match_operand:VI_HW 2 "register_operand"  "v")]
 668                       UNSPEC_VEC_AVG))]
 669   "TARGET_VX"
 670   "vavg<bhfgq>\t%v0,%v1,%v2"
 671   [(set_attr "op_type" "VRR")])
 672
 673 ; Vector average logical
 674
 675 ; vavglb, vavglh, vavglf, vavglg
 676 (define_insn "vec_avgu<mode>"
 677   [(set (match_operand:VI_HW                0 "register_operand" "=v")
 678         (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
 679                        (match_operand:VI_HW 2 "register_operand"  "v")]
 680                       UNSPEC_VEC_AVGU))]
 681   "TARGET_VX"
 682   "vavgl<bhfgq>\t%v0,%v1,%v2"
 683   [(set_attr "op_type" "VRR")])
 684
 685
 686 ; Vector checksum
 687
 688 (define_insn "vec_checksum"
 689   [(set (match_operand:V4SI               0 "register_operand" "=v")
 690         (unspec:V4SI [(match_operand:V4SI 1 "register_operand"  "v")
 691                       (match_operand:V4SI 2 "register_operand"  "v")]
 692                      UNSPEC_VEC_CHECKSUM))]
 693   "TARGET_VX"
 694   "vcksm\t%v0,%v1,%v2"
 695   [(set_attr "op_type" "VRR")])
 696
 697 ;;
 698 ;; Vector compare
 699 ;;
 700
 701 ; vec_all/any int compares
 702
 703 (define_expand "vec_all_<intcmpcc:code><VI_HW:mode>"
 704   [(match_operand:SI                0 "register_operand" "")
 705    (intcmpcc (match_operand:VI_HW 1 "register_operand" "")
 706              (match_operand:VI_HW 2 "register_operand" ""))]
 707   "TARGET_VX"
 708 {
 709   s390_expand_vec_compare_cc (operands[0],
 710                               <intcmpcc:CODE>,
 711                               operands[1],
 712                               operands[2],
 713                               true);
 714   DONE;
 715 })
 716
 717 (define_expand "vec_any_<intcmpcc:code><VI_HW:mode>"
 718   [(match_operand:SI                0 "register_operand" "")
 719    (intcmpcc (match_operand:VI_HW 1 "register_operand" "")
 720              (match_operand:VI_HW 2 "register_operand" ""))]
 721   "TARGET_VX"
 722 {
 723   s390_expand_vec_compare_cc (operands[0],
 724                               <intcmpcc:CODE>,
 725                               operands[1],
 726                               operands[2],
 727                               false);
 728   DONE;
 729 })
 730
 731 ; vec_all/any fp compares
 732
 733 (define_expand "vec_all_<fpcmpcc:code><mode>"
 734   [(match_operand:SI               0 "register_operand" "")
 735    (fpcmpcc (match_operand:VECF_HW 1 "register_operand" "")
 736             (match_operand:VECF_HW 2 "register_operand" ""))]
 737   "TARGET_VX"
 738 {
 739   s390_expand_vec_compare_cc (operands[0],
 740                               <fpcmpcc:CODE>,
 741                               operands[1],
 742                               operands[2],
 743                               true);
 744   DONE;
 745 })
 746
 747 (define_expand "vec_any_<fpcmpcc:code><mode>"
 748   [(match_operand:SI               0 "register_operand" "")
 749    (fpcmpcc (match_operand:VECF_HW 1 "register_operand" "")
 750             (match_operand:VECF_HW 2 "register_operand" ""))]
 751   "TARGET_VX"
 752 {
 753   s390_expand_vec_compare_cc (operands[0],
 754                               <fpcmpcc:CODE>,
 755                               operands[1],
 756                               operands[2],
 757                               false);
 758   DONE;
 759 })
 760
 761
 762 ; Compare without generating CC
 763
 764 (define_expand "vec_cmp<intcmp:code><VI_HW:mode>"
 765   [(set (match_operand:VI_HW               0 "register_operand" "=v")
 766         (intcmp:VI_HW (match_operand:VI_HW 1 "register_operand"  "v")
 767                       (match_operand:VI_HW 2 "register_operand"  "v")))]
 768   "TARGET_VX"
 769 {
 770   s390_expand_vec_compare (operands[0], <intcmp:CODE>, operands[1], operands[2]);
 771   DONE;
 772 })
 773
 774 (define_expand "vec_cmp<fpcmp:code><mode>"
 775   [(set (match_operand:<tointvec>              0 "register_operand" "=v")
 776         (fpcmp:<tointvec> (match_operand:VF_HW 1 "register_operand"  "v")
 777                        (match_operand:VF_HW 2 "register_operand"  "v")))]
 778   "TARGET_VX"
 779 {
 780   s390_expand_vec_compare (operands[0], <fpcmp:CODE>, operands[1], operands[2]);
 781   DONE;
 782 })
 783
 784
 785 ; Vector count leading zeros
 786
 787 ; vec_cntlz -> clz
 788 ; vec_cnttz -> ctz
 789
 790 ; Vector xor
 791
 792 ; vec_xor -> xor
 793
 794 ; Vector Galois field multiply sum
 795
 796 ; vgfmb, vgfmh, vgfmf
 797 (define_insn "vec_gfmsum<mode>"
 798   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
 799         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
 800                            (match_operand:VI_HW_QHS 2 "register_operand" "v")]
 801                           UNSPEC_VEC_GFMSUM))]
 802   "TARGET_VX"
 803   "vgfm<bhfgq>\t%v0,%v1,%v2"
 804   [(set_attr "op_type" "VRR")])
 805
 806 (define_insn "vec_gfmsum_128"
 807   [(set (match_operand:V16QI 0 "register_operand" "=v")
 808         (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")
 809                        (match_operand:V2DI 2 "register_operand" "v")]
 810                       UNSPEC_VEC_GFMSUM_128))]
 811   "TARGET_VX"
 812   "vgfmg\t%v0,%v1,%v2"
 813   [(set_attr "op_type" "VRR")])
 814
 815 ; vgfmab, vgfmah, vgfmaf
 816 (define_insn "vec_gfmsum_accum<mode>"
 817   [(set (match_operand:<vec_double> 0 "register_operand" "=v")
 818         (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
 819                               (match_operand:VI_HW_QHS 2 "register_operand" "v")
 820                               (match_operand:<vec_double> 3 "register_operand" "v")]
 821                              UNSPEC_VEC_GFMSUM_ACCUM))]
 822   "TARGET_VX"
 823   "vgfma<bhfgq>\t%v0,%v1,%v2,%v3"
 824   [(set_attr "op_type" "VRR")])
 825
 826 (define_insn "vec_gfmsum_accum_128"
 827   [(set (match_operand:V16QI 0 "register_operand" "=v")
 828         (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")
 829                        (match_operand:V2DI 2 "register_operand" "v")
 830                        (match_operand:V16QI 3 "register_operand" "v")]
 831                       UNSPEC_VEC_GFMSUM_ACCUM_128))]
 832   "TARGET_VX"
 833   "vgfmag\t%v0,%v1,%v2,%v3"
 834   [(set_attr "op_type" "VRR")])
 835
 836
 837 ; FIXME: vec_neg ?
 838
 839 ; Vector load positive: vec_abs -> abs
 840 ; Vector maximum vec_max -> smax, logical vec_max -> umax
 841 ; Vector maximum vec_min -> smin, logical vec_min -> umin
 842
 843
 844 ; Vector multiply and add high
 845
 846 ; vec_mladd -> vec_vmal
 847 ; vmalb, vmalh, vmalf, vmalg
 848 (define_insn "vec_vmal<mode>"
 849   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
 850         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
 851                            (match_operand:VI_HW_QHS 2 "register_operand"  "v")
 852                            (match_operand:VI_HW_QHS 3 "register_operand"  "v")]
 853                           UNSPEC_VEC_VMAL))]
 854   "TARGET_VX"
 855   "vmal<bhfgq><w>\t%v0,%v1,%v2,%v3"
 856   [(set_attr "op_type" "VRR")])
 857
 858 ; vec_mhadd -> vec_vmah/vec_vmalh
 859
 860 ; vmahb; vmahh, vmahf, vmahg
 861 (define_insn "vec_vmah<mode>"
 862   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
 863         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
 864                            (match_operand:VI_HW_QHS 2 "register_operand"  "v")
 865                            (match_operand:VI_HW_QHS 3 "register_operand"  "v")]
 866                           UNSPEC_VEC_VMAH))]
 867   "TARGET_VX"
 868   "vmah<bhfgq>\t%v0,%v1,%v2,%v3"
 869   [(set_attr "op_type" "VRR")])
 870
 871 ; vmalhb; vmalhh, vmalhf, vmalhg
 872 (define_insn "vec_vmalh<mode>"
 873   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
 874         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
 875                            (match_operand:VI_HW_QHS 2 "register_operand"  "v")
 876                            (match_operand:VI_HW_QHS 3 "register_operand"  "v")]
 877                           UNSPEC_VEC_VMALH))]
 878   "TARGET_VX"
 879   "vmalh<bhfgq>\t%v0,%v1,%v2,%v3"
 880   [(set_attr "op_type" "VRR")])
 881
 882 ; vec_meadd -> vec_vmae/vec_vmale
 883
 884 ; vmaeb; vmaeh, vmaef, vmaeg
 885 (define_insn "vec_vmae<mode>"
 886   [(set (match_operand:<vec_double> 0 "register_operand" "=v")
 887         (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand"   "%v")
 888                               (match_operand:VI_HW_QHS 2 "register_operand"    "v")
 889                               (match_operand:<vec_double> 3 "register_operand" "v")]
 890                              UNSPEC_VEC_VMAE))]
 891   "TARGET_VX"
 892   "vmae<bhfgq>\t%v0,%v1,%v2,%v3"
 893   [(set_attr "op_type" "VRR")])
 894
 895 ; vmaleb; vmaleh, vmalef, vmaleg
 896 (define_insn "vec_vmale<mode>"
 897   [(set (match_operand:<vec_double> 0 "register_operand" "=v")
 898         (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
 899                               (match_operand:VI_HW_QHS 2 "register_operand" "v")
 900                               (match_operand:<vec_double> 3 "register_operand" "v")]
 901                              UNSPEC_VEC_VMALE))]
 902   "TARGET_VX"
 903   "vmale<bhfgq>\t%v0,%v1,%v2,%v3"
 904   [(set_attr "op_type" "VRR")])
 905
 906 ; vec_moadd -> vec_vmao/vec_vmalo
 907
 908 ; vmaob; vmaoh, vmaof, vmaog
 909 (define_insn "vec_vmao<mode>"
 910   [(set (match_operand:<vec_double> 0 "register_operand" "=v")
 911         (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
 912                               (match_operand:VI_HW_QHS 2 "register_operand" "v")
 913                               (match_operand:<vec_double> 3 "register_operand" "v")]
 914                              UNSPEC_VEC_VMAO))]
 915   "TARGET_VX"
 916   "vmao<bhfgq>\t%v0,%v1,%v2,%v3"
 917   [(set_attr "op_type" "VRR")])
 918
 919 ; vmalob; vmaloh, vmalof, vmalog
 920 (define_insn "vec_vmalo<mode>"
 921   [(set (match_operand:<vec_double> 0 "register_operand" "=v")
 922         (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
 923                               (match_operand:VI_HW_QHS 2 "register_operand" "v")
 924                               (match_operand:<vec_double> 3 "register_operand" "v")]
 925                              UNSPEC_VEC_VMALO))]
 926   "TARGET_VX"
 927   "vmalo<bhfgq>\t%v0,%v1,%v2,%v3"
 928   [(set_attr "op_type" "VRR")])
 929
 930
 931 ; Vector multiply high
 932
 933 ; vec_mulh -> vec_smulh/vec_umulh
 934
 935 ; vmhb, vmhh, vmhf
 936 (define_insn "vec_smulh<mode>"
 937   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
 938         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
 939                            (match_operand:VI_HW_QHS 2 "register_operand" "v")]
 940                           UNSPEC_VEC_SMULT_HI))]
 941   "TARGET_VX"
 942   "vmh<bhfgq>\t%v0,%v1,%v2"
 943   [(set_attr "op_type" "VRR")])
 944
 945 ; vmlhb, vmlhh, vmlhf
 946 (define_insn "vec_umulh<mode>"
 947   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
 948         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
 949                            (match_operand:VI_HW_QHS 2 "register_operand" "v")]
 950                           UNSPEC_VEC_UMULT_HI))]
 951   "TARGET_VX"
 952   "vmlh<bhfgq>\t%v0,%v1,%v2"
 953   [(set_attr "op_type" "VRR")])
 954
 955
 956 ; Vector multiply low
 957
 958 ; vec_mule -> vec_widen_umult_even/vec_widen_smult_even
 959 ; vec_mulo -> vec_widen_umult_odd/vec_widen_smult_odd
 960
 961
 962 ; Vector nor
 963
 964 (define_insn "vec_nor<mode>3"
 965   [(set (match_operand:VT_HW 0 "register_operand" "=v")
 966         (not:VT_HW
 967          (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "%v")
 968                     (match_operand:VT_HW 2 "register_operand" "v"))))]
 969   "TARGET_VX"
 970   "vno\t%v0,%v1,%v2"
 971   [(set_attr "op_type" "VRR")])
 972
 973
 974 ; Vector or
 975
 976 ; Vector population count vec_popcnt -> popcount
 977 ; Vector element rotate left logical vec_rl -> vrotl, vec_rli -> rot
 978
 979 ; Vector element rotate and insert under mask
 980
 981 ; verimb, verimh, verimf, verimg
 982 (define_insn "verim<mode>"
 983   [(set (match_operand:VI_HW                0 "register_operand" "=v")
 984         (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand"  "0")
 985                        (match_operand:VI_HW 2 "register_operand"  "v")
 986                        (match_operand:VI_HW 3 "register_operand"  "v")
 987                        (match_operand:QI    4 "const_int_operand" "C")]
 988                       UNSPEC_VEC_RL_MASK))]
 989   "TARGET_VX"
 990   "verim<bhfgq>\t%v0,%v2,%v3,%b4"
 991   [(set_attr "op_type" "VRI")])
 992
 993
 994 ; Vector shift left
 995
 996 (define_insn "vec_sll<VI_HW:mode><VI_HW_QHS:mode>"
 997   [(set (match_operand:VI_HW                    0 "register_operand" "=v")
 998         (unspec:VI_HW [(match_operand:VI_HW     1 "register_operand"  "v")
 999                        (match_operand:VI_HW_QHS 2 "register_operand"  "v")]
1000                       UNSPEC_VEC_SLL))]
1001   "TARGET_VX"
1002   "vsl\t%v0,%v1,%v2"
1003   [(set_attr "op_type" "VRR")])
1004
1005
1006 ; Vector shift left by byte
1007
1008 (define_insn "vec_slb<mode>"
1009   [(set (match_operand:V_HW 0 "register_operand"                    "=v")
1010         (unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "v")
1011                       (match_operand:<tointvec> 2 "register_operand" "v")]
1012                      UNSPEC_VEC_SLB))]
1013   "TARGET_VX"
1014   "vslb\t%v0,%v1,%v2"
1015   [(set_attr "op_type" "VRR")])
1016
1017
1018 ; Vector shift left double by byte
1019
1020 (define_insn "vec_sld<mode>"
1021   [(set (match_operand:V_HW 0 "register_operand"              "=v")
1022         (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
1023                       (match_operand:V_HW 2 "register_operand" "v")
1024                       (match_operand:QI 3 "const_int_operand"  "C")]
1025                      UNSPEC_VEC_SLDB))]
1026   "TARGET_VX"
1027   "vsldb\t%v0,%v1,%v2,%b3"
1028   [(set_attr "op_type" "VRI")])
1029
1030 (define_expand "vec_sldw<mode>"
1031   [(set (match_operand:V_HW 0 "register_operand"               "")
1032         (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
1033                       (match_operand:V_HW 2 "register_operand" "")
1034                       (match_operand:QI 3 "const_int_operand"  "")]
1035                      UNSPEC_VEC_SLDB))]
1036   "TARGET_VX"
1037 {
1038   operands[3] = GEN_INT (INTVAL (operands[3]) << 2);
1039 })
1040
1041 ; Vector shift right arithmetic
1042
1043 (define_insn "vec_sral<VI_HW:mode><VI_HW_QHS:mode>"
1044   [(set (match_operand:VI_HW                    0 "register_operand" "=v")
1045         (unspec:VI_HW [(match_operand:VI_HW     1 "register_operand"  "v")
1046                        (match_operand:VI_HW_QHS 2 "register_operand"  "v")]
1047                       UNSPEC_VEC_SRAL))]
1048   "TARGET_VX"
1049   "vsra\t%v0,%v1,%v2"
1050   [(set_attr "op_type" "VRR")])
1051
1052
1053 ; Vector shift right arithmetic by byte
1054
1055 (define_insn "vec_srab<mode>"
1056   [(set (match_operand:V_HW 0 "register_operand"                    "=v")
1057         (unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "v")
1058                       (match_operand:<tointvec> 2 "register_operand" "v")]
1059                      UNSPEC_VEC_SRAB))]
1060   "TARGET_VX"
1061   "vsrab\t%v0,%v1,%v2"
1062   [(set_attr "op_type" "VRR")])
1063
1064
1065 ; Vector shift right logical
1066
1067 (define_insn "vec_srl<VI_HW:mode><VI_HW_QHS:mode>"
1068   [(set (match_operand:VI_HW                    0 "register_operand" "=v")
1069         (unspec:VI_HW [(match_operand:VI_HW     1 "register_operand"  "v")
1070                        (match_operand:VI_HW_QHS 2 "register_operand"  "v")]
1071                       UNSPEC_VEC_SRL))]
1072   "TARGET_VX"
1073   "vsrl\t%v0,%v1,%v2"
1074   [(set_attr "op_type" "VRR")])
1075
1076
1077 ; Vector shift right logical by byte
1078
1079 ; Pattern definition in vector.md
1080 (define_expand "vec_srb<mode>"
1081   [(set (match_operand:V_HW 0 "register_operand"                     "")
1082         (unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "")
1083                       (match_operand:<tointvec> 2 "register_operand" "")]
1084                      UNSPEC_VEC_SRLB))]
1085   "TARGET_VX")
1086
1087
1088 ; Vector subtract
1089
1090 ; Vector subtract compute borrow indication
1091
1092 ; vscbib, vscbih, vscbif, vscbig, vscbiq
1093 (define_insn "vscbi<bhfgq>_<mode>"
1094   [(set (match_operand:VIT_HW 0 "register_operand"                "=v")
1095         (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "v")
1096                         (match_operand:VIT_HW 2 "register_operand" "v")]
1097                       UNSPEC_VEC_SUBC))]
1098   "TARGET_VX"
1099   "vscbi<bhfgq>\t%v0,%v1,%v2"
1100   [(set_attr "op_type" "VRR")])
1101
1102 ; Vector subtract with borrow indication
1103
1104 (define_insn "vsbiq"
1105   [(set (match_operand:TI 0 "register_operand"               "=v")
1106         (unspec:TI [(match_operand:TI 1 "register_operand"    "v")
1107                        (match_operand:TI 2 "register_operand" "v")
1108                        (match_operand:TI 3 "register_operand" "v")]
1109                       UNSPEC_VEC_SUBE_U128))]
1110   "TARGET_VX"
1111   "vsbiq\t%v0,%v1,%v2,%v3"
1112   [(set_attr "op_type" "VRR")])
1113
1114
1115 ; Vector subtract with borrow compute and borrow indication
1116
1117 (define_insn "vsbcbiq"
1118   [(set (match_operand:TI 0 "register_operand"               "=v")
1119         (unspec:TI [(match_operand:TI 1 "register_operand"    "v")
1120                        (match_operand:TI 2 "register_operand" "v")
1121                        (match_operand:TI 3 "register_operand" "v")]
1122                       UNSPEC_VEC_SUBEC_U128))]
1123   "TARGET_VX"
1124   "vsbcbiq\t%v0,%v1,%v2,%v3"
1125   [(set_attr "op_type" "VRR")])
1126
1127
1128 ; Vector sum across
1129
1130 ; Sum across DImode parts of the 1st operand and add the rightmost
1131 ; element of 2nd operand
1132 ; vsumgh, vsumgf
1133 (define_expand "vec_sum2<mode>"
1134   [(set (match_operand:V2DI 0 "register_operand" "")
1135         (unspec:V2DI [(match_operand:VI_HW_HS 1 "register_operand" "")
1136                       (match_operand:VI_HW_HS 2 "register_operand" "")]
1137                      UNSPEC_VEC_VSUMG))]
1138   "TARGET_VX")
1139
1140 ; vsumqh, vsumqf
1141 (define_insn "vec_sum_u128<mode>"
1142   [(set (match_operand:V2DI 0 "register_operand" "=v")
1143         (unspec:V2DI [(match_operand:VI_HW_SD 1 "register_operand" "v")
1144                       (match_operand:VI_HW_SD 2 "register_operand" "v")]
1145                      UNSPEC_VEC_VSUMQ))]
1146   "TARGET_VX"
1147   "vsumq<bhfgq>\t%v0,%v1,%v2"
1148   [(set_attr "op_type" "VRR")])
1149
1150 ; vsumb, vsumh
1151 (define_expand "vec_sum4<mode>"
1152   [(set (match_operand:V4SI 0 "register_operand" "")
1153         (unspec:V4SI [(match_operand:VI_HW_QH 1 "register_operand" "")
1154                       (match_operand:VI_HW_QH 2 "register_operand" "")]
1155                      UNSPEC_VEC_VSUM))]
1156   "TARGET_VX")
1157
1158
1159 ; Vector test under mask
1160
1161 (define_expand "vec_test_mask_int<mode>"
1162   [(set (reg:CCRAW CC_REGNUM)
1163         (unspec:CCRAW [(match_operand:V_HW 1 "register_operand" "")
1164                        (match_operand:<tointvec> 2 "register_operand" "")]
1165                       UNSPEC_VEC_TEST_MASK))
1166    (set (match_operand:SI 0 "register_operand" "")
1167         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1168   "TARGET_VX")
1169
1170 (define_insn "*vec_test_mask<mode>"
1171   [(set (reg:CCRAW CC_REGNUM)
1172         (unspec:CCRAW [(match_operand:V_HW 0 "register_operand" "v")
1173                        (match_operand:<tointvec> 1 "register_operand" "v")]
1174                       UNSPEC_VEC_TEST_MASK))]
1175   "TARGET_VX"
1176   "vtm\t%v0,%v1"
1177   [(set_attr "op_type" "VRR")])
1178
1179
1180 ; Vector multiply sum logical
1181
1182 (define_insn "vec_msumv2di"
1183   [(set (match_operand:V16QI 0 "register_operand" "=v")
1184         (unspec:V16QI [(match_operand:V2DI  1 "register_operand"   "v")
1185                        (match_operand:V2DI  2 "register_operand"   "v")
1186                        (match_operand:V16QI 3 "register_operand"   "v")
1187                        (match_operand:QI    4 "const_mask_operand" "C")]
1188                       UNSPEC_VEC_MSUM))]
1189   "TARGET_VXE"
1190   "vmslg\t%v0,%v1,%v2,%v3"
1191   [(set_attr "op_type" "VRR")])
1192
1193 (define_insn "vmslg"
1194   [(set (match_operand:TI 0 "register_operand" "=v")
1195         (unspec:TI [(match_operand:V2DI  1 "register_operand"   "v")
1196                     (match_operand:V2DI  2 "register_operand"   "v")
1197                     (match_operand:TI    3 "register_operand"   "v")
1198                     (match_operand:QI    4 "const_mask_operand" "C")]
1199                    UNSPEC_VEC_MSUM))]
1200   "TARGET_VXE"
1201   "vmslg\t%v0,%v1,%v2,%v3"
1202   [(set_attr "op_type" "VRR")])
1203
1204
1205 ; Vector find any element equal
1206
1207 ; vfaeb, vfaeh, vfaef
1208 ; vfaezb, vfaezh, vfaezf
1209 (define_insn "vfae<mode>"
1210   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1211         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1212                            (match_operand:VI_HW_QHS 2 "register_operand" "v")
1213                            (match_operand:QI        3 "const_mask_operand" "C")]
1214                           UNSPEC_VEC_VFAE))]
1215   "TARGET_VX"
1216 {
1217   unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]);
1218
1219   if (flags & VSTRING_FLAG_ZS)
1220     {
1221       flags &= ~VSTRING_FLAG_ZS;
1222       operands[3] = GEN_INT (flags);
1223       return "vfaez<bhfgq>\t%v0,%v1,%v2,%b3";
1224     }
1225   return "vfae<bhfgq>\t%v0,%v1,%v2,%b3";
1226 }
1227 [(set_attr "op_type" "VRR")])
1228
1229 ; vfaebs, vfaehs, vfaefs
1230 ; vfaezbs, vfaezhs, vfaezfs
1231 (define_insn "*vfaes<mode>"
1232   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1233         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"   "v")
1234                            (match_operand:VI_HW_QHS 2 "register_operand"   "v")
1235                            (match_operand:QI        3 "const_mask_operand" "C")]
1236                           UNSPEC_VEC_VFAE))
1237    (set (reg:CCRAW CC_REGNUM)
1238         (unspec:CCRAW [(match_dup 1)
1239                        (match_dup 2)
1240                        (match_dup 3)]
1241                       UNSPEC_VEC_VFAECC))]
1242   "TARGET_VX"
1243 {
1244   unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]);
1245
1246   if (flags & VSTRING_FLAG_ZS)
1247     {
1248       flags &= ~VSTRING_FLAG_ZS;
1249       operands[3] = GEN_INT (flags);
1250       return "vfaez<bhfgq>s\t%v0,%v1,%v2,%b3";
1251     }
1252   return "vfae<bhfgq>s\t%v0,%v1,%v2,%b3";
1253 }
1254   [(set_attr "op_type" "VRR")])
1255
1256 (define_expand "vfaez<mode>"
1257   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1258         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "")
1259                            (match_operand:VI_HW_QHS 2 "register_operand"  "")
1260                            (match_operand:QI        3 "const_mask_operand" "")]
1261                           UNSPEC_VEC_VFAE))]
1262   "TARGET_VX"
1263 {
1264   operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_ZS);
1265 })
1266
1267 (define_expand "vfaes<mode>"
1268   [(parallel
1269     [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1270         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "")
1271                            (match_operand:VI_HW_QHS 2 "register_operand"  "")
1272                            (match_operand:QI        3 "const_mask_operand" "")]
1273                           UNSPEC_VEC_VFAE))
1274    (set (reg:CCRAW CC_REGNUM)
1275         (unspec:CCRAW [(match_dup 1)
1276                        (match_dup 2)
1277                        (match_dup 3)]
1278                       UNSPEC_VEC_VFAECC))])
1279    (set (match_operand:SI 4 "memory_operand" "")
1280         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1281   "TARGET_VX"
1282 {
1283   operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_CS);
1284 })
1285
1286 (define_expand "vfaezs<mode>"
1287   [(parallel
1288     [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1289         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "")
1290                            (match_operand:VI_HW_QHS 2 "register_operand"  "")
1291                            (match_operand:SI        3 "const_mask_operand" "")]
1292                           UNSPEC_VEC_VFAE))
1293    (set (reg:CCRAW CC_REGNUM)
1294         (unspec:CCRAW [(match_dup 1)
1295                        (match_dup 2)
1296                        (match_dup 3)]
1297                       UNSPEC_VEC_VFAECC))])
1298    (set (match_operand:SI 4 "memory_operand" "")
1299         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1300   "TARGET_VX"
1301 {
1302   operands[3] = GEN_INT (INTVAL (operands[3]) | VSTRING_FLAG_CS | VSTRING_FLAG_ZS);
1303 })
1304
1305
1306 ; Vector find element equal
1307
1308 ; vfeebs, vfeehs, vfeefs
1309 ; vfeezbs, vfeezhs, vfeezfs
1310 (define_insn "*vfees<mode>"
1311   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1312         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
1313                            (match_operand:VI_HW_QHS 2 "register_operand" "v")
1314                            (match_operand:QI 3 "const_mask_operand" "C")]
1315                           UNSPEC_VEC_VFEE))
1316    (set (reg:CCRAW CC_REGNUM)
1317         (unspec:CCRAW [(match_dup 1)
1318                        (match_dup 2)
1319                        (match_dup 3)]
1320                       UNSPEC_VEC_VFEECC))]
1321   "TARGET_VX"
1322 {
1323   unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]);
1324
1325   gcc_assert (!(flags & ~(VSTRING_FLAG_ZS | VSTRING_FLAG_CS)));
1326   flags &= ~VSTRING_FLAG_CS;
1327
1328   if (flags == VSTRING_FLAG_ZS)
1329     return "vfeez<bhfgq>s\t%v0,%v1,%v2";
1330   return "vfee<bhfgq>s\t%v0,%v1,%v2,%b3";
1331 }
1332   [(set_attr "op_type" "VRR")])
1333
1334 ; vfeeb, vfeeh, vfeef
1335 (define_insn "vfee<mode>"
1336   [(set (match_operand:VI_HW_QHS                    0 "register_operand" "=v")
1337         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "v")
1338                            (match_operand:VI_HW_QHS 2 "register_operand"  "v")
1339                            (const_int 0)]
1340                           UNSPEC_VEC_VFEE))]
1341   "TARGET_VX"
1342   "vfee<bhfgq>\t%v0,%v1,%v2,0"
1343   [(set_attr "op_type" "VRR")])
1344
1345 ; vfeezb, vfeezh, vfeezf
1346 (define_insn "vfeez<mode>"
1347   [(set (match_operand:VI_HW_QHS                    0 "register_operand" "=v")
1348         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "v")
1349                            (match_operand:VI_HW_QHS 2 "register_operand"  "v")
1350                            (const_int VSTRING_FLAG_ZS)]
1351                           UNSPEC_VEC_VFEE))]
1352   "TARGET_VX"
1353   "vfeez<bhfgq>s\t%v0,%v1,%v2,2"
1354   [(set_attr "op_type" "VRR")])
1355
1356 (define_expand "vfees<mode>"
1357   [(parallel
1358     [(set (match_operand:VI_HW_QHS                    0 "register_operand" "")
1359           (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1360                              (match_operand:VI_HW_QHS 2 "register_operand" "")
1361                              (const_int VSTRING_FLAG_CS)]
1362                             UNSPEC_VEC_VFEE))
1363    (set (reg:CCRAW CC_REGNUM)
1364         (unspec:CCRAW [(match_dup 1)
1365                        (match_dup 2)
1366                        (const_int VSTRING_FLAG_CS)]
1367                       UNSPEC_VEC_VFEECC))])
1368    (set (match_operand:SI 3 "memory_operand" "")
1369         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1370   "TARGET_VX")
1371
1372 (define_expand "vfeezs<mode>"
1373   [(parallel
1374     [(set (match_operand:VI_HW_QHS                    0 "register_operand" "")
1375           (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1376                              (match_operand:VI_HW_QHS 2 "register_operand" "")
1377                              (match_dup 4)]
1378                             UNSPEC_VEC_VFEE))
1379    (set (reg:CCRAW CC_REGNUM)
1380         (unspec:CCRAW [(match_dup 1)
1381                        (match_dup 2)
1382                        (match_dup 4)]
1383                       UNSPEC_VEC_VFEECC))])
1384    (set (match_operand:SI 3 "memory_operand" "")
1385         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1386   "TARGET_VX"
1387 {
1388   operands[4] = GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS);
1389 })
1390
1391 ; Vector find element not equal
1392
1393 ; vfeneb, vfeneh, vfenef
1394 (define_insn "vfene<mode>"
1395   [(set (match_operand:VI_HW_QHS                    0 "register_operand" "=v")
1396         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "v")
1397                            (match_operand:VI_HW_QHS 2 "register_operand"  "v")
1398                            (const_int 0)]
1399                           UNSPEC_VEC_VFENE))]
1400   "TARGET_VX"
1401   "vfene<bhfgq>\t%v0,%v1,%v2,0"
1402   [(set_attr "op_type" "VRR")])
1403
1404 ; vec_vfenes can be found in vector.md since it is used for strlen
1405
1406 ; vfenezb, vfenezh, vfenezf
1407 (define_insn "vfenez<mode>"
1408   [(set (match_operand:VI_HW_QHS                    0 "register_operand" "=v")
1409         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"  "v")
1410                            (match_operand:VI_HW_QHS 2 "register_operand"  "v")
1411                            (const_int VSTRING_FLAG_ZS)]
1412                           UNSPEC_VEC_VFENE))]
1413   "TARGET_VX"
1414   "vfenez<bhfgq>\t%v0,%v1,%v2"
1415   [(set_attr "op_type" "VRR")])
1416
1417 (define_expand "vfenes<mode>"
1418   [(parallel
1419     [(set (match_operand:VI_HW_QHS                    0 "register_operand" "")
1420           (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1421                              (match_operand:VI_HW_QHS 2 "register_operand" "")
1422                              (const_int VSTRING_FLAG_CS)]
1423                             UNSPEC_VEC_VFENE))
1424    (set (reg:CCRAW CC_REGNUM)
1425         (unspec:CCRAW [(match_dup 1)
1426                        (match_dup 2)
1427                        (const_int VSTRING_FLAG_CS)]
1428                       UNSPEC_VEC_VFENECC))])
1429    (set (match_operand:SI 3 "memory_operand" "")
1430         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1431   "TARGET_VX")
1432
1433 (define_expand "vfenezs<mode>"
1434   [(parallel
1435     [(set (match_operand:VI_HW_QHS                    0 "register_operand" "")
1436           (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1437                              (match_operand:VI_HW_QHS 2 "register_operand" "")
1438                              (match_dup 4)]
1439                             UNSPEC_VEC_VFENE))
1440      (set (reg:CCRAW CC_REGNUM)
1441           (unspec:CCRAW [(match_dup 1)
1442                          (match_dup 2)
1443                          (match_dup 4)]
1444                         UNSPEC_VEC_VFENECC))])
1445    (set (match_operand:SI 3 "memory_operand" "")
1446         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1447   "TARGET_VX"
1448 {
1449   operands[4] = GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS);
1450 })
1451
1452 ; Vector isolate string
1453
1454 ; vistrb, vistrh, vistrf
1455 (define_insn "vistr<mode>"
1456   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1457         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
1458                           UNSPEC_VEC_VISTR))]
1459   "TARGET_VX"
1460   "vistr<bhfgq>\t%v0,%v1"
1461   [(set_attr "op_type" "VRR")])
1462
1463 ; vistrbs, vistrhs, vistrfs
1464 (define_insn "*vistrs<mode>"
1465   [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
1466         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")]
1467                           UNSPEC_VEC_VISTR))
1468    (set (reg:CCRAW CC_REGNUM)
1469         (unspec:CCRAW [(match_dup 1)] UNSPEC_VEC_VISTRCC))]
1470   "TARGET_VX"
1471   "vistr<bhfgq>s\t%v0,%v1"
1472   [(set_attr "op_type" "VRR")])
1473
1474 (define_expand "vistrs<mode>"
1475   [(parallel
1476     [(set (match_operand:VI_HW_QHS                    0 "register_operand" "")
1477           (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")]
1478                             UNSPEC_VEC_VISTR))
1479      (set (reg:CCRAW CC_REGNUM)
1480           (unspec:CCRAW [(match_dup 1)]
1481                         UNSPEC_VEC_VISTRCC))])
1482    (set (match_operand:SI 2 "memory_operand" "")
1483         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1484   "TARGET_VX")
1485
1486
1487 ; Vector compare range
1488
1489 ; vstrcb, vstrch, vstrcf
1490 ; vstrczb, vstrczh, vstrczf
1491 (define_insn "vstrc<mode>"
1492   [(set (match_operand:VI_HW_QHS                    0 "register_operand"  "=v")
1493         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"   "v")
1494                            (match_operand:VI_HW_QHS 2 "register_operand"   "v")
1495                            (match_operand:VI_HW_QHS 3 "register_operand"   "v")
1496                            (match_operand:QI        4 "const_mask_operand" "C")]
1497                           UNSPEC_VEC_VSTRC))]
1498   "TARGET_VX"
1499 {
1500   unsigned HOST_WIDE_INT flags = UINTVAL (operands[4]);
1501
1502   if (flags & VSTRING_FLAG_ZS)
1503     {
1504       flags &= ~VSTRING_FLAG_ZS;
1505       operands[4] = GEN_INT (flags);
1506       return "vstrcz<bhfgq>\t%v0,%v1,%v2,%v3,%b4";
1507     }
1508   return "vstrc<bhfgq>\t%v0,%v1,%v2,%v3,%b4";
1509 }
1510 [(set_attr "op_type" "VRR")])
1511
1512 ; vstrcbs, vstrchs, vstrcfs
1513 ; vstrczbs, vstrczhs, vstrczfs
1514 (define_insn "*vstrcs<mode>"
1515   [(set (match_operand:VI_HW_QHS                    0 "register_operand"  "=v")
1516         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"   "v")
1517                            (match_operand:VI_HW_QHS 2 "register_operand"   "v")
1518                            (match_operand:VI_HW_QHS 3 "register_operand"   "v")
1519                            (match_operand:QI        4 "const_mask_operand" "C")]
1520                           UNSPEC_VEC_VSTRC))
1521    (set (reg:CCRAW CC_REGNUM)
1522         (unspec:CCRAW [(match_dup 1)
1523                        (match_dup 2)
1524                        (match_dup 3)
1525                        (match_dup 4)]
1526                       UNSPEC_VEC_VSTRCCC))]
1527   "TARGET_VX"
1528 {
1529   unsigned HOST_WIDE_INT flags = UINTVAL (operands[4]);
1530
1531   if (flags & VSTRING_FLAG_ZS)
1532     {
1533       flags &= ~VSTRING_FLAG_ZS;
1534       operands[4] = GEN_INT (flags);
1535       return "vstrcz<bhfgq>s\t%v0,%v1,%v2,%v3,%b4";
1536     }
1537   return "vstrc<bhfgq>s\t%v0,%v1,%v2,%v3,%b4";
1538 }
1539   [(set_attr "op_type" "VRR")])
1540
1541 (define_expand "vstrcz<mode>"
1542   [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1543         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand"   "")
1544                            (match_operand:VI_HW_QHS 2 "register_operand"   "")
1545                            (match_operand:VI_HW_QHS 3 "register_operand"   "")
1546                            (match_operand:QI        4 "const_mask_operand" "")]
1547                           UNSPEC_VEC_VSTRC))]
1548   "TARGET_VX"
1549 {
1550   operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_ZS);
1551 })
1552
1553 (define_expand "vstrcs<mode>"
1554   [(parallel
1555     [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1556         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1557                            (match_operand:VI_HW_QHS 2 "register_operand" "")
1558                            (match_operand:VI_HW_QHS 3 "register_operand" "")
1559                            (match_operand:QI        4 "const_mask_operand" "")]
1560                           UNSPEC_VEC_VSTRC))
1561    (set (reg:CCRAW CC_REGNUM)
1562         (unspec:CCRAW [(match_dup 1)
1563                        (match_dup 2)
1564                        (match_dup 3)
1565                        (match_dup 4)]
1566                       UNSPEC_VEC_VSTRCCC))])
1567    (set (match_operand:SI 5 "memory_operand" "")
1568         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1569   "TARGET_VX"
1570 {
1571   operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_CS);
1572 })
1573
1574 (define_expand "vstrczs<mode>"
1575   [(parallel
1576     [(set (match_operand:VI_HW_QHS 0 "register_operand" "")
1577         (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "")
1578                            (match_operand:VI_HW_QHS 2 "register_operand" "")
1579                            (match_operand:VI_HW_QHS 3 "register_operand" "")
1580                            (match_operand:QI        4 "const_mask_operand" "")]
1581                           UNSPEC_VEC_VSTRC))
1582    (set (reg:CCRAW CC_REGNUM)
1583         (unspec:CCRAW [(match_dup 1)
1584                        (match_dup 2)
1585                        (match_dup 3)
1586                        (match_dup 4)]
1587                       UNSPEC_VEC_VSTRCCC))])
1588    (set (match_operand:SI 5 "memory_operand" "")
1589         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1590   "TARGET_VX"
1591 {
1592   operands[4] = GEN_INT (INTVAL (operands[4]) | VSTRING_FLAG_CS | VSTRING_FLAG_ZS);
1593 })
1594
1595 (define_insn "vcdgb"
1596   [(set (match_operand:V2DF 0 "register_operand"                "=v")
1597         (unspec:V2DF [(match_operand:V2DI 1 "register_operand"   "v")
1598                       (match_operand:QI   2 "const_mask_operand" "C")  ; inexact suppression
1599                       (match_operand:QI   3 "const_mask_operand" "C")] ; rounding mode
1600                      UNSPEC_VEC_VCDGB))]
1601   "TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
1602   "vcdgb\t%v0,%v1,%b2,%b3"
1603   [(set_attr "op_type" "VRR")])
1604
1605
1606 ; The result needs to be multiplied with 2**-op2
1607 (define_expand "vec_ctd_s64"
1608   [(set (match_operand:V2DF               0 "register_operand" "")
1609         (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
1610                       (const_int 4) ; inexact suppressed
1611                       (const_int VEC_RND_CURRENT)]
1612                      UNSPEC_VEC_VCDGB))
1613    (use (match_operand:QI 2 "const_int_operand" ""))
1614    (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
1615   "TARGET_VX"
1616 {
1617   REAL_VALUE_TYPE f;
1618   rtx c;
1619
1620   real_2expN (&f, -INTVAL (operands[2]), DFmode);
1621   c = const_double_from_real_value (f, DFmode);
1622
1623   operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c));
1624   operands[3] = force_reg (V2DFmode, operands[3]);
1625 })
1626
1627 (define_insn "vcdlgb"
1628   [(set (match_operand:V2DF 0 "register_operand"                 "=v")
1629         (unspec:V2DF [(match_operand:V2DI 1 "register_operand"    "v")
1630                       (match_operand:QI   2 "const_mask_operand"  "C")  ; inexact suppression
1631                       (match_operand:QI   3 "const_mask_operand"  "C")] ; rounding mode
1632                      UNSPEC_VEC_VCDLGB))]
1633   "TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
1634   "vcdlgb\t%v0,%v1,%b2,%b3"
1635   [(set_attr "op_type" "VRR")])
1636
1637 ; The result needs to be multiplied with 2**-op2
1638 (define_expand "vec_ctd_u64"
1639   [(set (match_operand:V2DF               0 "register_operand" "")
1640         (unspec:V2DF [(match_operand:V2DI 1 "register_operand" "")
1641                       (const_int 4) ; inexact suppressed
1642                       (const_int VEC_RND_CURRENT)]
1643                      UNSPEC_VEC_VCDLGB))
1644    (use (match_operand:QI 2 "const_int_operand" ""))
1645    (set (match_dup 0) (mult:V2DF (match_dup 0) (match_dup 3)))]
1646   "TARGET_VX"
1647 {
1648   REAL_VALUE_TYPE f;
1649   rtx c;
1650
1651   real_2expN (&f, -INTVAL (operands[2]), DFmode);
1652   c = const_double_from_real_value (f, DFmode);
1653
1654   operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c));
1655   operands[3] = force_reg (V2DFmode, operands[3]);
1656 })
1657
1658 (define_insn "vcgdb"
1659   [(set (match_operand:V2DI 0 "register_operand"                "=v")
1660         (unspec:V2DI [(match_operand:V2DF 1 "register_operand"   "v")
1661                       (match_operand:QI   2 "const_mask_operand" "C")
1662                       (match_operand:QI   3 "const_mask_operand" "C")]
1663                      UNSPEC_VEC_VCGDB))]
1664   "TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
1665   "vcgdb\t%v0,%v1,%b2,%b3"
1666   [(set_attr "op_type" "VRR")])
1667
1668 ; The input needs to be multiplied with 2**op2
1669 (define_expand "vec_ctsl"
1670   [(use (match_operand:QI 2 "const_int_operand" ""))
1671    (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
1672                                  (match_dup 3)))
1673    (set (match_operand:V2DI 0 "register_operand" "")
1674         (unspec:V2DI [(match_dup 4)
1675                       (const_int 4) ; inexact suppressed
1676                       (const_int VEC_RND_CURRENT)]
1677                      UNSPEC_VEC_VCGDB))]
1678   "TARGET_VX"
1679 {
1680   REAL_VALUE_TYPE f;
1681   rtx c;
1682
1683   real_2expN (&f, INTVAL (operands[2]), DFmode);
1684   c = const_double_from_real_value (f, DFmode);
1685
1686   operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c));
1687   operands[3] = force_reg (V2DFmode, operands[3]);
1688   operands[4] = gen_reg_rtx (V2DFmode);
1689 })
1690
1691 (define_insn "vclgdb"
1692   [(set (match_operand:V2DI 0 "register_operand"               "=v")
1693         (unspec:V2DI [(match_operand:V2DF 1 "register_operand"  "v")
1694                       (match_operand:QI   2 "const_mask_operand" "C")
1695                       (match_operand:QI   3 "const_mask_operand" "C")]
1696                      UNSPEC_VEC_VCLGDB))]
1697   "TARGET_VX && UINTVAL (operands[3]) != 2 && UINTVAL (operands[3]) <= 7"
1698   "vclgdb\t%v0,%v1,%b2,%b3"
1699   [(set_attr "op_type" "VRR")])
1700
1701 ; The input needs to be multiplied with 2**op2
1702 (define_expand "vec_ctul"
1703   [(use (match_operand:QI 2 "const_int_operand" ""))
1704    (set (match_dup 4) (mult:V2DF (match_operand:V2DF 1 "register_operand" "")
1705                                  (match_dup 3)))
1706    (set (match_operand:V2DI 0 "register_operand" "")
1707         (unspec:V2DI [(match_dup 4)
1708                       (const_int 4) ; inexact suppressed
1709                       (const_int VEC_RND_CURRENT)]
1710                      UNSPEC_VEC_VCLGDB))]
1711   "TARGET_VX"
1712 {
1713   REAL_VALUE_TYPE f;
1714   rtx c;
1715
1716   real_2expN (&f, INTVAL (operands[2]), DFmode);
1717   c = const_double_from_real_value (f, DFmode);
1718
1719   operands[3] = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, c, c));
1720   operands[3] = force_reg (V2DFmode, operands[3]);
1721   operands[4] = gen_reg_rtx (V2DFmode);
1722 })
1723
1724 ; Vector load fp integer - IEEE inexact exception is suppressed
1725 ; vfisb, vfidb, wfisb, wfidb, wfixb
1726 (define_insn "vec_fpint<mode>"
1727   [(set (match_operand:VFT              0 "register_operand"  "=v")
1728         (unspec:VFT [(match_operand:VFT 1 "register_operand"   "v")
1729                      (match_operand:QI  2 "const_mask_operand" "C")  ; inexact suppression control
1730                      (match_operand:QI  3 "const_mask_operand" "C")] ; rounding mode
1731                      UNSPEC_VEC_VFI))]
1732   "TARGET_VX"
1733   "<vw>fi<sdx>b\t%v0,%v1,%b2,%b3"
1734   [(set_attr "op_type" "VRR")])
1735
1736
1737 ; Vector load lengthened - V4SF -> V2DF
1738
1739 (define_insn "vflls"
1740   [(set (match_operand:V2DF 0 "register_operand"               "=v")
1741         (unspec:V2DF [(match_operand:V4SF 1 "register_operand"  "v")]
1742                      UNSPEC_VEC_VFLL))]
1743   "TARGET_VX"
1744   "vldeb\t%v0,%v1"
1745   [(set_attr "op_type" "VRR")])
1746
1747 (define_expand "vec_ld2f"
1748   [; Initialize a vector to all zeroes.  FIXME: This should not be
1749    ; necessary since all elements of the vector will be set anyway.
1750    ; This is just to make it explicit to the data flow framework.
1751    (set (match_dup 2) (match_dup 3))
1752    (set (match_dup 2) (unspec:V4SF [(match_operand:SF 1 "memory_operand" "")
1753                                     (const_int 0)
1754                                     (match_dup 2)]
1755                                     UNSPEC_VEC_SET))
1756    (set (match_dup 2) (unspec:V4SF [(match_dup 4)
1757                                     (const_int 2)
1758                                     (match_dup 2)]
1759                                     UNSPEC_VEC_SET))
1760    (set (match_operand:V2DF 0 "register_operand" "")
1761         (unspec:V2DF [(match_dup 2)] UNSPEC_VEC_VFLL))]
1762   "TARGET_VX"
1763 {
1764   operands[2] = gen_reg_rtx (V4SFmode);
1765   operands[3] = CONST0_RTX (V4SFmode);
1766   operands[4] = adjust_address (operands[1], SFmode, 4);
1767 })
1768
1769
1770 ; Vector load rounded - V2DF -> V4SF
1771
1772 (define_insn "vflrd"
1773   [(set (match_operand:V4SF 0 "register_operand"                "=v")
1774         (unspec:V4SF [(match_operand:V2DF 1 "register_operand"   "v")
1775                       (match_operand:QI   2 "const_mask_operand" "C")
1776                       (match_operand:QI   3 "const_mask_operand" "C")]
1777                      UNSPEC_VEC_VFLR))]
1778   "TARGET_VX"
1779   "vledb\t%v0,%v1,%b2,%b3"
1780   [(set_attr "op_type" "VRR")])
1781
1782 (define_expand "vec_st2f"
1783   [(set (match_dup 2)
1784         (unspec:V4SF [(match_operand:V2DF 0 "register_operand" "")
1785                       (const_int VEC_INEXACT)
1786                       (const_int VEC_RND_CURRENT)]
1787                      UNSPEC_VEC_VFLR))
1788    (set (match_operand:SF 1 "memory_operand" "")
1789         (unspec:SF [(match_dup 2) (const_int 0)] UNSPEC_VEC_EXTRACT))
1790    (set (match_dup 3)
1791         (unspec:SF [(match_dup 2) (const_int 2)] UNSPEC_VEC_EXTRACT))]
1792   "TARGET_VX"
1793 {
1794   operands[2] = gen_reg_rtx (V4SFmode);
1795   operands[3] = adjust_address (operands[1], SFmode, 4);
1796 })
1797
1798
1799 ; Vector square root fp vec_sqrt -> sqrt rtx standard name
1800
1801 ;; Vector FP test data class immediate
1802
1803 ; vec_all_nan, vec_all_numeric, vec_any_nan, vec_any_numeric
1804 ; These ignore the vector result and only want CC stored to an int
1805 ; pointer.
1806
1807 ; vftcisb, vftcidb
1808 (define_insn "*vftci<mode>_cconly"
1809   [(set (reg:CCRAW CC_REGNUM)
1810         (unspec:CCRAW [(match_operand:VECF_HW 1 "register_operand")
1811                        (match_operand:HI      2 "const_int_operand")]
1812                       UNSPEC_VEC_VFTCICC))
1813    (clobber (match_scratch:<tointvec> 0))]
1814   "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
1815   "vftci<sdx>b\t%v0,%v1,%x2"
1816   [(set_attr "op_type" "VRR")])
1817
1818 (define_expand "vftci<mode>_intcconly"
1819   [(parallel
1820     [(set (reg:CCRAW CC_REGNUM)
1821           (unspec:CCRAW [(match_operand:VECF_HW 0 "register_operand")
1822                          (match_operand:HI      1 "const_int_operand")]
1823                         UNSPEC_VEC_VFTCICC))
1824      (clobber (scratch:<tointvec>))])
1825    (set (match_operand:SI 2 "register_operand" "")
1826         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1827   "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")")
1828
1829 ; vec_fp_test_data_class wants the result vector and the CC stored to
1830 ; an int pointer.
1831
1832 ; vftcisb, vftcidb
1833 (define_insn "*vftci<mode>"
1834   [(set (match_operand:VECF_HW                  0 "register_operand"  "=v")
1835         (unspec:VECF_HW [(match_operand:VECF_HW 1 "register_operand"   "v")
1836                          (match_operand:HI      2 "const_int_operand"  "J")]
1837                         UNSPEC_VEC_VFTCI))
1838    (set (reg:CCRAW CC_REGNUM)
1839         (unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCICC))]
1840   "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
1841   "vftci<sdx>b\t%v0,%v1,%x2"
1842   [(set_attr "op_type" "VRR")])
1843
1844 (define_expand "vftci<mode>_intcc"
1845   [(parallel
1846     [(set (match_operand:VECF_HW                  0 "register_operand")
1847           (unspec:VECF_HW [(match_operand:VECF_HW 1 "register_operand")
1848                            (match_operand:HI      2 "const_int_operand")]
1849                           UNSPEC_VEC_VFTCI))
1850      (set (reg:CCRAW CC_REGNUM)
1851           (unspec:CCRAW [(match_dup 1) (match_dup 2)] UNSPEC_VEC_VFTCICC))])
1852    (set (match_operand:SI 3 "memory_operand" "")
1853         (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
1854   "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")")
1855
1856 ;;
1857 ;; Integer compares
1858 ;;
1859
1860 ; All comparisons which produce a CC need fully populated (VI_HW)
1861 ; vector arguments.  Otherwise the any/all CCs would be just bogus.
1862
1863 (define_insn "*vec_cmp<VICMP:insn_cmp><VI_HW:mode>_cconly"
1864   [(set (reg:VICMP CC_REGNUM)
1865         (compare:VICMP (match_operand:VI_HW 0 "register_operand" "v")
1866                        (match_operand:VI_HW 1 "register_operand" "v")))
1867    (clobber (match_scratch:VI_HW 2 "=v"))]
1868   "TARGET_VX"
1869   "vc<VICMP:insn_cmp><VI_HW:bhfgq>s\t%v2,%v0,%v1"
1870   [(set_attr "op_type" "VRR")])
1871
1872 ; FIXME: The following 2x3 definitions should be merged into 2 with
1873 ; VICMP like above but I could not find a way to set the comparison
1874 ; operator (eq) depending on the mode CCVEQ (mode_iterator). Or the
1875 ; other way around - setting the mode depending on the code
1876 ; (code_iterator).
1877 (define_expand "vec_cmpeq<VI_HW:mode>_cc"
1878   [(parallel
1879     [(set (reg:CCVEQ CC_REGNUM)
1880         (compare:CCVEQ (match_operand:VI_HW 1 "register_operand" "v")
1881                        (match_operand:VI_HW 2 "register_operand" "v")))
1882      (set (match_operand:VI_HW 0 "register_operand" "=v")
1883           (eq:VI_HW (match_dup 1) (match_dup 2)))])
1884    (set (match_operand:SI 3 "memory_operand" "")
1885         (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))]
1886   "TARGET_VX")
1887
1888 (define_expand "vec_cmph<VI_HW:mode>_cc"
1889   [(parallel
1890     [(set (reg:CCVIH CC_REGNUM)
1891           (compare:CCVIH (match_operand:VI_HW 1 "register_operand" "v")
1892                          (match_operand:VI_HW 2 "register_operand" "v")))
1893      (set (match_operand:VI_HW 0 "register_operand" "=v")
1894           (gt:VI_HW (match_dup 1) (match_dup 2)))])
1895    (set (match_operand:SI 3 "memory_operand" "")
1896         (unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))]
1897   "TARGET_VX")
1898
1899 (define_expand "vec_cmphl<VI_HW:mode>_cc"
1900   [(parallel
1901     [(set (reg:CCVIHU CC_REGNUM)
1902           (compare:CCVIHU (match_operand:VI_HW 1 "register_operand" "v")
1903                           (match_operand:VI_HW 2 "register_operand" "v")))
1904      (set (match_operand:VI_HW 0 "register_operand" "=v")
1905           (gtu:VI_HW (match_dup 1) (match_dup 2)))])
1906    (set (match_operand:SI 3 "memory_operand" "")
1907         (unspec:SI [(reg:CCVIHU CC_REGNUM)] UNSPEC_CC_TO_INT))]
1908   "TARGET_VX")
1909
1910
1911 (define_insn "*vec_cmpeq<VI_HW:mode>_cc"
1912   [(set (reg:CCVEQ CC_REGNUM)
1913         (compare:CCVEQ (match_operand:VI_HW 0 "register_operand"  "v")
1914                        (match_operand:VI_HW 1 "register_operand"  "v")))
1915    (set (match_operand:VI_HW                2 "register_operand" "=v")
1916         (eq:VI_HW (match_dup 0) (match_dup 1)))]
1917   "TARGET_VX"
1918   "vceq<VI_HW:bhfgq>s\t%v2,%v0,%v1"
1919   [(set_attr "op_type" "VRR")])
1920
1921 (define_insn "*vec_cmph<VI_HW:mode>_cc"
1922   [(set (reg:CCVIH CC_REGNUM)
1923         (compare:CCVIH (match_operand:VI_HW 0 "register_operand"  "v")
1924                        (match_operand:VI_HW 1 "register_operand"  "v")))
1925    (set (match_operand:VI_HW               2 "register_operand" "=v")
1926         (gt:VI_HW (match_dup 0) (match_dup 1)))]
1927   "TARGET_VX"
1928   "vch<VI_HW:bhfgq>s\t%v2,%v0,%v1"
1929   [(set_attr "op_type" "VRR")])
1930
1931 (define_insn "*vec_cmphl<VI_HW:mode>_cc"
1932   [(set (reg:CCVIHU CC_REGNUM)
1933         (compare:CCVIHU (match_operand:VI_HW 0 "register_operand"  "v")
1934                         (match_operand:VI_HW 1 "register_operand"  "v")))
1935    (set (match_operand:VI_HW                2 "register_operand" "=v")
1936         (gtu:VI_HW (match_dup 0) (match_dup 1)))]
1937   "TARGET_VX"
1938   "vchl<VI_HW:bhfgq>s\t%v2,%v0,%v1"
1939   [(set_attr "op_type" "VRR")])
1940
1941 ;;
1942 ;; Floating point compares
1943 ;;
1944
1945 ; vfcesbs, vfcedbs, wfcexbs, vfchsbs, vfchdbs, wfchxbs, vfchesbs, vfchedbs, wfchexbs
1946 (define_insn "*vec_cmp<insn_cmp><mode>_cconly"
1947   [(set (reg:VFCMP CC_REGNUM)
1948         (compare:VFCMP (match_operand:VF_HW 0 "register_operand" "v")
1949                        (match_operand:VF_HW 1 "register_operand" "v")))
1950    (clobber (match_scratch:<tointvec> 2 "=v"))]
1951   "TARGET_VX"
1952   "<vw>fc<asm_fcmp><sdx>bs\t%v2,%v0,%v1"
1953   [(set_attr "op_type" "VRR")])
1954
1955 ; FIXME: Merge the following 2x3 patterns with VFCMP
1956 (define_expand "vec_cmpeq<mode>_cc"
1957   [(parallel
1958     [(set (reg:CCVEQ CC_REGNUM)
1959           (compare:CCVEQ (match_operand:VF_HW 1 "register_operand"  "v")
1960                          (match_operand:VF_HW 2 "register_operand"  "v")))
1961      (set (match_operand:<tointvec> 0 "register_operand" "=v")
1962           (eq:<tointvec> (match_dup 1) (match_dup 2)))])
1963    (set (match_operand:SI 3 "memory_operand" "")
1964         (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))]
1965   "TARGET_VX")
1966
1967 (define_expand "vec_cmph<mode>_cc"
1968   [(parallel
1969     [(set (reg:CCVFH CC_REGNUM)
1970           (compare:CCVFH (match_operand:VF_HW 1 "register_operand"  "v")
1971                          (match_operand:VF_HW 2 "register_operand"  "v")))
1972      (set (match_operand:<tointvec> 0 "register_operand" "=v")
1973           (gt:<tointvec> (match_dup 1) (match_dup 2)))])
1974    (set (match_operand:SI 3 "memory_operand" "")
1975         (unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))]
1976   "TARGET_VX")
1977
1978 (define_expand "vec_cmphe<mode>_cc"
1979   [(parallel
1980     [(set (reg:CCVFHE CC_REGNUM)
1981           (compare:CCVFHE (match_operand:VF_HW 1 "register_operand"  "v")
1982                           (match_operand:VF_HW 2 "register_operand"  "v")))
1983      (set (match_operand:<tointvec> 0 "register_operand" "=v")
1984           (ge:<tointvec> (match_dup 1) (match_dup 2)))])
1985    (set (match_operand:SI 3 "memory_operand" "")
1986         (unspec:SI [(reg:CCVFHE CC_REGNUM)] UNSPEC_CC_TO_INT))]
1987   "TARGET_VX")
1988
1989 ; These 3 cannot be merged as the insn defintion above since it also
1990 ; requires to rewrite the RTL equality operator that the same time as
1991 ; the CC mode.
1992
1993 ; vfcesbs, vfcedbs, wfcexbs
1994 (define_insn "*vec_cmpeq<mode>_cc"
1995   [(set (reg:CCVEQ CC_REGNUM)
1996         (compare:CCVEQ (match_operand:VF_HW 0 "register_operand"  "v")
1997                        (match_operand:VF_HW 1 "register_operand"  "v")))
1998    (set (match_operand:<tointvec>              2 "register_operand" "=v")
1999         (eq:<tointvec> (match_dup 0) (match_dup 1)))]
2000   "TARGET_VX"
2001   "<vw>fce<sdx>bs\t%v2,%v0,%v1"
2002   [(set_attr "op_type" "VRR")])
2003
2004 ; vfchsbs, vfchdbs, wfchxbs
2005 (define_insn "*vec_cmph<mode>_cc"
2006   [(set (reg:CCVFH CC_REGNUM)
2007         (compare:CCVFH (match_operand:VF_HW 0 "register_operand"  "v")
2008                        (match_operand:VF_HW 1 "register_operand"  "v")))
2009    (set (match_operand:<tointvec>              2 "register_operand" "=v")
2010         (gt:<tointvec> (match_dup 0) (match_dup 1)))]
2011   "TARGET_VX"
2012   "<vw>fch<sdx>bs\t%v2,%v0,%v1"
2013   [(set_attr "op_type" "VRR")])
2014
2015 ; vfchesbs, vfchedbs, wfchexbs
2016 (define_insn "*vec_cmphe<mode>_cc"
2017   [(set (reg:CCVFHE CC_REGNUM)
2018         (compare:CCVFHE (match_operand:VF_HW 0 "register_operand"  "v")
2019                         (match_operand:VF_HW 1 "register_operand"  "v")))
2020    (set (match_operand:<tointvec>               2 "register_operand" "=v")
2021         (ge:<tointvec> (match_dup 0) (match_dup 1)))]
2022   "TARGET_VX"
2023   "<vw>fche<sdx>bs\t%v2,%v0,%v1"
2024   [(set_attr "op_type" "VRR")])
2025
2026 (define_expand "vec_double_s64"
2027   [(set (match_operand:V2DF               0 "register_operand")
2028         (unspec:V2DF [(match_operand:V2DI 1 "register_operand")
2029                       (const_int 0)  ; inexact suppression disabled
2030                       (const_int VEC_RND_CURRENT)]
2031                      UNSPEC_VEC_VCDGB))]
2032   "TARGET_VX")
2033
2034 (define_expand "vec_double_u64"
2035   [(set (match_operand:V2DF               0 "register_operand")
2036         (unspec:V2DF [(match_operand:V2DI 1 "register_operand")
2037                       (const_int 0)  ; inexact suppression disabled
2038                       (const_int VEC_RND_CURRENT)]
2039                      UNSPEC_VEC_VCDLGB))]
2040   "TARGET_VX")
2041
2042
2043 (define_insn "vfmin<mode>"
2044   [(set (match_operand:VF_HW                0 "register_operand" "=v")
2045         (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v")
2046                        (match_operand:VF_HW 2 "register_operand"  "v")
2047                        (match_operand:QI    3 "const_mask_operand" "C")]
2048                       UNSPEC_VEC_VFMIN))]
2049   "TARGET_VXE"
2050   "<vw>fmin<sdx>b\t%v0,%v1,%v2,%b3"
2051   [(set_attr "op_type" "VRR")])
2052
2053 (define_insn "vfmax<mode>"
2054   [(set (match_operand:VF_HW                0 "register_operand" "=v")
2055         (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v")
2056                        (match_operand:VF_HW 2 "register_operand"  "v")
2057                        (match_operand:QI    3 "const_mask_operand" "C")]
2058                       UNSPEC_VEC_VFMAX))]
2059   "TARGET_VXE"
2060   "<vw>fmax<sdx>b\t%v0,%v1,%v2,%b3"
2061   [(set_attr "op_type" "VRR")])