1 ;; DFA scheduling description for EPIPHANY
2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
3 ;; Contributed by Embecosm on behalf of Adapteva, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Two automata are defined to reduce number of states
22 ;; which a single large automaton will have. (Factoring)
24 (define_automaton "inst_pipeline,fpu_pipe")
26 ;; This unit is basically the decode unit of the processor.
27 ;; Since epiphany is a dual issue machine, it is as if there are two
28 ;; units so that any insn can be processed by either one
29 ;; of the decoding unit.
31 (define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
33 ;; The fixed point arithmetic unit.
35 (define_cpu_unit "int" "inst_pipeline")
37 ;; The floating point unit.
39 (define_cpu_unit "F0" "fpu_pipe")
41 ;; ----------------------------------------------------
42 ;; This reservation is to simplify the dual issue description.
44 (define_reservation "issue" "pipe_01|pipe_02")
46 ;; This is to express instructions that cannot be paired.
48 (define_reservation "d_lock" "pipe_01+pipe_02")
50 ;; We don't model all pipeline stages; we model the issue stage
51 ;; inasmuch as we allow only two instructions to issue simultaneously,
52 ;; and flow instructions prevent any simultaneous issue of another instruction.
53 ;; (This uses pipe_01 and pipe_02).
54 ;; Double issue of 'other' insns is prevented by using the int unit in the
56 ;; Double issue of float instructions is prevented by using F0 in the E1 stage.
58 (define_insn_reservation "simple_arith" 2
59 (and (eq_attr "pipe_model" "epiphany")
60 (eq_attr "type" "move,cmove,compare,shift,misc,mul")
61 (eq_attr "length" "4"))
64 ; anything but fp / fp_int / v2fp has a bypass
65 (define_bypass 1 "simple_arith" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
67 (define_insn_reservation "simple_arith_2" 2
68 (and (eq_attr "pipe_model" "epiphany")
69 (eq_attr "type" "move,cmove,compare,shift,misc,mul")
70 (eq_attr "length" "8"))
71 "issue,issue+int,int")
73 (define_insn_reservation "simple_arith_4" 4
74 (and (eq_attr "pipe_model" "epiphany")
75 (eq_attr "type" "move,compare,shift,misc,mul")
76 (eq_attr "length" "12,16,20,24"))
77 "issue,issue+int,issue+int,issue+int,int")
79 ;; Loads have a latency of two.
80 ;; Note that we fix up the latency of post_modify in epiphany.c:epiphany_adjust_cost
82 (define_insn_reservation "load" 3
83 (and (eq_attr "pipe_model" "epiphany")
84 (eq_attr "type" "load"))
87 ; anything but fp / fp_int / v2fp has a bypass
88 (define_bypass 2 "load" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
90 (define_insn_reservation "store" 1
91 (and (eq_attr "pipe_model" "epiphany")
92 (eq_attr "type" "store"))
96 ;; Latency when taken: 3
98 ;; The latency is 1 when the branch is not taken.
99 ;; We can't really do much with the latency, even if we could express it,
100 ;; but the pairing restrictions are useful to take into account.
102 (define_insn_reservation "branch" 1
103 (and (eq_attr "pipe_model" "epiphany")
104 (eq_attr "type" "branch,uncond_branch"))
107 ;; calls introduce a longisch delay that is likely to flush the pipelines
108 ;; of the caller's instructions. Both the call instruction itself and
109 ;; the rts at the end of the call / sfunc incurs a three cycle penalty,
110 ;; thus also isolating the scheduling of caller and callee.
112 (define_insn_reservation "call" 8
113 (and (eq_attr "pipe_model" "epiphany")
114 (eq_attr "type" "call,sfunc,fp_sfunc"))
117 (define_insn_reservation "flow" 1
118 (and (eq_attr "pipe_model" "epiphany")
119 (eq_attr "type" "flow"))
122 (define_insn_reservation "fp_arith" 5
123 (and (eq_attr "pipe_model" "epiphany")
124 (eq_attr "type" "fp,fp_int"))
127 (define_bypass 4 "fp_arith" "store")
129 ; There are two main consumers for v2fp:
130 ; - other v2fp operation - in that case, the latencies can dovetail to
131 ; save one cycle of latency.
132 ; - 64 bit store operations - we need both registers, but OTOH the latency is
133 ; one lower to start with.
134 ; of the bypass saving one cyles then.
135 (define_insn_reservation "v2fp_arith" 5
136 (and (eq_attr "pipe_model" "epiphany")
137 (eq_attr "type" "v2fp"))
140 ; A boolean attribute for use by peephole2 patterns that try to figure out
141 ; if we overcommitted the FPU.
142 ; This is notionally a numeric attribute to avoid dependency problems.
143 (define_attr "sched_use_fpu" ""
144 (cond [(eq_attr "type" "fp,fp_int,v2fp") (const_int 1)]