1 ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler
2 ;; Copyright (C) 2007-2017 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_c_enum "unspec" [
21 ;; Va, Vb, Vc builtins
22 UNSPEC_ARC_SIMD_VADDAW
26 UNSPEC_ARC_SIMD_VDIFAW
28 UNSPEC_ARC_SIMD_VMAXAW
30 UNSPEC_ARC_SIMD_VMINAW
32 UNSPEC_ARC_SIMD_VMULAW
33 UNSPEC_ARC_SIMD_VMULFAW
34 UNSPEC_ARC_SIMD_VMULFW
36 UNSPEC_ARC_SIMD_VSUBAW
38 UNSPEC_ARC_SIMD_VSUMMW
40 UNSPEC_ARC_SIMD_VANDAW
42 UNSPEC_ARC_SIMD_VBICAW
45 UNSPEC_ARC_SIMD_VXORAW
50 UNSPEC_ARC_SIMD_VMR1AW
52 UNSPEC_ARC_SIMD_VMR2AW
54 UNSPEC_ARC_SIMD_VMR3AW
56 UNSPEC_ARC_SIMD_VMR4AW
58 UNSPEC_ARC_SIMD_VMR5AW
60 UNSPEC_ARC_SIMD_VMR6AW
62 UNSPEC_ARC_SIMD_VMR7AW
65 UNSPEC_ARC_SIMD_VH264F
66 UNSPEC_ARC_SIMD_VH264FT
67 UNSPEC_ARC_SIMD_VH264FW
69 UNSPEC_ARC_SIMD_VVC1FT
70 ;; Va, Vb, rc/limm builtins
71 UNSPEC_ARC_SIMD_VBADDW
72 UNSPEC_ARC_SIMD_VBMAXW
73 UNSPEC_ARC_SIMD_VBMINW
74 UNSPEC_ARC_SIMD_VBMULAW
75 UNSPEC_ARC_SIMD_VBMULFW
76 UNSPEC_ARC_SIMD_VBMULW
77 UNSPEC_ARC_SIMD_VBRSUBW
78 UNSPEC_ARC_SIMD_VBSUBW
80 ;; Va, Vb, Ic builtins
83 UNSPEC_ARC_SIMD_VSR8AW
85 ;; Va, Vb, Ic builtins
86 UNSPEC_ARC_SIMD_VASRRWi
87 UNSPEC_ARC_SIMD_VASRSRWi
88 UNSPEC_ARC_SIMD_VASRWi
89 UNSPEC_ARC_SIMD_VASRPWBi
90 UNSPEC_ARC_SIMD_VASRRPWBi
91 UNSPEC_ARC_SIMD_VSR8AWi
94 ;; Va, Vb, u8 (simm) builtins
98 UNSPEC_ARC_SIMD_VD6TAPF
100 ;; Va, rlimm, u8 (simm) builtins
101 UNSPEC_ARC_SIMD_VMOVAW
102 UNSPEC_ARC_SIMD_VMOVW
103 UNSPEC_ARC_SIMD_VMOVZW
106 UNSPEC_ARC_SIMD_VABSAW
107 UNSPEC_ARC_SIMD_VABSW
108 UNSPEC_ARC_SIMD_VADDSUW
109 UNSPEC_ARC_SIMD_VSIGNW
110 UNSPEC_ARC_SIMD_VEXCH1
111 UNSPEC_ARC_SIMD_VEXCH2
112 UNSPEC_ARC_SIMD_VEXCH4
113 UNSPEC_ARC_SIMD_VUPBAW
114 UNSPEC_ARC_SIMD_VUPBW
115 UNSPEC_ARC_SIMD_VUPSBAW
116 UNSPEC_ARC_SIMD_VUPSBW
118 UNSPEC_ARC_SIMD_VDIRUN
119 UNSPEC_ARC_SIMD_VDORUN
120 UNSPEC_ARC_SIMD_VDIWR
121 UNSPEC_ARC_SIMD_VDOWR
125 UNSPEC_ARC_SIMD_VRECRUN
126 UNSPEC_ARC_SIMD_VENDREC
128 UNSPEC_ARC_SIMD_VCAST
129 UNSPEC_ARC_SIMD_VINTI
132 ;; Scheduler descriptions for the simd instructions
133 (define_insn_reservation "simd_lat_0_insn" 1
134 (eq_attr "type" "simd_dma, simd_vstore, simd_vcontrol")
137 (define_insn_reservation "simd_lat_1_insn" 2
138 (eq_attr "type" "simd_vcompare, simd_vlogic,
139 simd_vmove_else_zero, simd_varith_1cycle")
140 "issue+simd_unit, nothing")
142 (define_insn_reservation "simd_lat_2_insn" 3
143 (eq_attr "type" "simd_valign, simd_vpermute,
144 simd_vpack, simd_varith_2cycle")
145 "issue+simd_unit, nothing*2")
147 (define_insn_reservation "simd_lat_3_insn" 4
148 (eq_attr "type" "simd_valign_with_acc, simd_vpack_with_acc,
149 simd_vlogic_with_acc, simd_vload128,
150 simd_vmove_with_acc, simd_vspecial_3cycle,
151 simd_varith_with_acc")
152 "issue+simd_unit, nothing*3")
154 (define_insn_reservation "simd_lat_4_insn" 5
155 (eq_attr "type" "simd_vload, simd_vmove, simd_vspecial_4cycle")
156 "issue+simd_unit, nothing*4")
158 (define_expand "movv8hi"
159 [(set (match_operand:V8HI 0 "general_operand" "")
160 (match_operand:V8HI 1 "general_operand" ""))]
164 /* Everything except mem = const or mem = mem can be done easily. */
166 if (GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)
167 operands[1] = force_reg (V8HImode, operands[1]);
170 ;; This pattern should appear before the movv8hi_insn pattern
171 (define_insn "vld128_insn"
172 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
173 (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v")
174 (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
175 (match_operand:SI 3 "immediate_operand" "P"))))]
177 "vld128 %0, [i%2, %3]"
178 [(set_attr "type" "simd_vload128")
179 (set_attr "length" "4")
180 (set_attr "cond" "nocond")]
183 (define_insn "vst128_insn"
184 [(set (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v")
185 (parallel [(match_operand:SI 1 "immediate_operand" "L")])))
186 (match_operand:SI 2 "immediate_operand" "P")))
187 (match_operand:V8HI 3 "vector_register_operand" "=v"))]
189 "vst128 %3, [i%1, %2]"
190 [(set_attr "type" "simd_vstore")
191 (set_attr "length" "4")
192 (set_attr "cond" "nocond")]
195 (define_insn "vst64_insn"
199 (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v")
201 [(match_operand:SI 1 "immediate_operand" "L")])))
202 (match_operand:SI 2 "immediate_operand" "P")))
204 (match_operand:V8HI 3 "vector_register_operand" "=v")
205 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))]
207 "vst64 %3, [i%1, %2]"
208 [(set_attr "type" "simd_vstore")
209 (set_attr "length" "4")
210 (set_attr "cond" "nocond")]
213 (define_insn "movv8hi_insn"
214 [(set (match_operand:V8HI 0 "vector_register_or_memory_operand" "=v,m,v")
215 (match_operand:V8HI 1 "vector_register_or_memory_operand" "m,v,v"))]
216 "TARGET_SIMD_SET && !(GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)"
221 [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
222 (set_attr "length" "8,8,4")
223 (set_attr "cond" "nocond, nocond, nocond")])
225 (define_insn "movti_insn"
226 [(set (match_operand:TI 0 "vector_register_or_memory_operand" "=v,m,v")
227 (match_operand:TI 1 "vector_register_or_memory_operand" "m,v,v"))]
233 [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
234 (set_attr "length" "8,8,4")
235 (set_attr "cond" "nocond, nocond, nocond")])
237 ;; (define_insn "*movv8hi_insn_rr"
238 ;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
239 ;; (match_operand:V8HI 1 "vector_register_operand" "v"))]
242 ;; [(set_attr "length" "8")
243 ;; (set_attr "type" "move")])
245 ;; (define_insn "*movv8_out"
246 ;; [(set (match_operand:V8HI 0 "memory_operand" "=m")
247 ;; (match_operand:V8HI 1 "vector_register_operand" "v"))]
250 ;; [(set_attr "length" "8")
251 ;; (set_attr "type" "move")])
254 ;; (define_insn "addv8hi3"
255 ;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
256 ;; (plus:V8HI (match_operand:V8HI 1 "vector_register_operand" "v")
257 ;; (match_operand:V8HI 2 "vector_register_operand" "v")))]
259 ;; "vaddw %0, %1, %2"
260 ;; [(set_attr "length" "8")
261 ;; (set_attr "cond" "nocond")])
263 ;; (define_insn "vaddw_insn"
264 ;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
265 ;; (unspec [(match_operand:V8HI 1 "vector_register_operand" "v")
266 ;; (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
268 ;; "vaddw %0, %1, %2"
269 ;; [(set_attr "length" "8")
270 ;; (set_attr "cond" "nocond")])
273 (define_insn "vaddaw_insn"
274 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
275 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
276 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDAW))]
279 [(set_attr "type" "simd_varith_with_acc")
280 (set_attr "length" "4")
281 (set_attr "cond" "nocond")])
283 (define_insn "vaddw_insn"
284 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
285 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
286 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
289 [(set_attr "type" "simd_varith_1cycle")
290 (set_attr "length" "4")
291 (set_attr "cond" "nocond")])
293 (define_insn "vavb_insn"
294 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
295 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
296 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVB))]
299 [(set_attr "type" "simd_varith_1cycle")
300 (set_attr "length" "4")
301 (set_attr "cond" "nocond")])
303 (define_insn "vavrb_insn"
304 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
305 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
306 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVRB))]
309 [(set_attr "type" "simd_varith_1cycle")
310 (set_attr "length" "4")
311 (set_attr "cond" "nocond")])
313 (define_insn "vdifaw_insn"
314 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
315 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
316 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFAW))]
319 [(set_attr "type" "simd_varith_with_acc")
320 (set_attr "length" "4")
321 (set_attr "cond" "nocond")])
323 (define_insn "vdifw_insn"
324 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
325 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
326 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFW))]
329 [(set_attr "type" "simd_varith_1cycle")
330 (set_attr "length" "4")
331 (set_attr "cond" "nocond")])
333 (define_insn "vmaxaw_insn"
334 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
335 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
336 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXAW))]
339 [(set_attr "type" "simd_varith_with_acc")
340 (set_attr "length" "4")
341 (set_attr "cond" "nocond")])
343 (define_insn "vmaxw_insn"
344 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
345 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
346 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXW))]
349 [(set_attr "type" "simd_varith_1cycle")
350 (set_attr "length" "4")
351 (set_attr "cond" "nocond")])
353 (define_insn "vminaw_insn"
354 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
355 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
356 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINAW))]
359 [(set_attr "type" "simd_varith_with_acc")
360 (set_attr "length" "4")
361 (set_attr "cond" "nocond")])
363 (define_insn "vminw_insn"
364 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
365 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
366 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINW))]
369 [(set_attr "type" "simd_varith_1cycle")
370 (set_attr "length" "4")
371 (set_attr "cond" "nocond")])
373 (define_insn "vmulaw_insn"
374 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
375 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
376 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULAW))]
379 [(set_attr "type" "simd_varith_with_acc")
380 (set_attr "length" "4")
381 (set_attr "cond" "nocond")])
383 (define_insn "vmulfaw_insn"
384 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
385 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
386 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFAW))]
389 [(set_attr "type" "simd_varith_with_acc")
390 (set_attr "length" "4")
391 (set_attr "cond" "nocond")])
393 (define_insn "vmulfw_insn"
394 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
395 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
396 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFW))]
399 [(set_attr "type" "simd_varith_2cycle")
400 (set_attr "length" "4")
401 (set_attr "cond" "nocond")])
403 (define_insn "vmulw_insn"
404 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
405 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
406 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULW))]
409 [(set_attr "type" "simd_varith_2cycle")
410 (set_attr "length" "4")
411 (set_attr "cond" "nocond")])
413 (define_insn "vsubaw_insn"
414 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
415 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
416 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBAW))]
419 [(set_attr "type" "simd_varith_with_acc")
420 (set_attr "length" "4")
421 (set_attr "cond" "nocond")])
423 (define_insn "vsubw_insn"
424 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
425 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
426 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBW))]
429 [(set_attr "type" "simd_varith_1cycle")
430 (set_attr "length" "4")
431 (set_attr "cond" "nocond")])
433 (define_insn "vsummw_insn"
434 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
435 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
436 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUMMW))]
439 [(set_attr "type" "simd_varith_2cycle")
440 (set_attr "length" "4")
441 (set_attr "cond" "nocond")])
443 (define_insn "vand_insn"
444 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
445 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
446 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAND))]
449 [(set_attr "type" "simd_vlogic")
450 (set_attr "length" "4")
451 (set_attr "cond" "nocond")])
453 (define_insn "vandaw_insn"
454 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
455 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
456 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VANDAW))]
459 [(set_attr "type" "simd_vlogic_with_acc")
460 (set_attr "length" "4")
461 (set_attr "cond" "nocond")])
463 (define_insn "vbic_insn"
464 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
465 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
466 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBIC))]
469 [(set_attr "type" "simd_vlogic")
470 (set_attr "length" "4")
471 (set_attr "cond" "nocond")])
473 (define_insn "vbicaw_insn"
474 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
475 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
476 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBICAW))]
479 [(set_attr "type" "simd_vlogic_with_acc")
480 (set_attr "length" "4")
481 (set_attr "cond" "nocond")])
483 (define_insn "vor_insn"
484 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
485 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
486 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VOR))]
489 [(set_attr "type" "simd_vlogic")
490 (set_attr "length" "4")
491 (set_attr "cond" "nocond")])
493 (define_insn "vxor_insn"
494 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
495 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
496 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXOR))]
499 [(set_attr "type" "simd_vlogic")
500 (set_attr "length" "4")
501 (set_attr "cond" "nocond")])
503 (define_insn "vxoraw_insn"
504 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
505 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
506 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXORAW))]
509 [(set_attr "type" "simd_vlogic_with_acc")
510 (set_attr "length" "4")
511 (set_attr "cond" "nocond")])
513 (define_insn "veqw_insn"
514 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
515 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
516 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEQW))]
519 [(set_attr "type" "simd_vcompare")
520 (set_attr "length" "4")
521 (set_attr "cond" "nocond")])
523 (define_insn "vlew_insn"
524 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
525 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
526 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLEW))]
529 [(set_attr "type" "simd_vcompare")
530 (set_attr "length" "4")
531 (set_attr "cond" "nocond")])
533 (define_insn "vltw_insn"
534 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
535 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
536 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLTW))]
539 [(set_attr "type" "simd_vcompare")
540 (set_attr "length" "4")
541 (set_attr "cond" "nocond")])
543 (define_insn "vnew_insn"
544 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
545 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
546 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VNEW))]
549 [(set_attr "type" "simd_vcompare")
550 (set_attr "length" "4")
551 (set_attr "cond" "nocond")])
553 (define_insn "vmr1aw_insn"
554 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
555 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
556 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1AW))]
559 [(set_attr "type" "simd_valign_with_acc")
560 (set_attr "length" "4")
561 (set_attr "cond" "nocond")])
563 (define_insn "vmr1w_insn"
564 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
565 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
566 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1W))]
569 [(set_attr "type" "simd_valign")
570 (set_attr "length" "4")
571 (set_attr "cond" "nocond")])
573 (define_insn "vmr2aw_insn"
574 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
575 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
576 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2AW))]
579 [(set_attr "type" "simd_valign_with_acc")
580 (set_attr "length" "4")
581 (set_attr "cond" "nocond")])
583 (define_insn "vmr2w_insn"
584 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
585 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
586 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2W))]
589 [(set_attr "type" "simd_valign")
590 (set_attr "length" "4")
591 (set_attr "cond" "nocond")])
593 (define_insn "vmr3aw_insn"
594 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
595 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
596 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3AW))]
599 [(set_attr "type" "simd_valign_with_acc")
600 (set_attr "length" "4")
601 (set_attr "cond" "nocond")])
603 (define_insn "vmr3w_insn"
604 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
605 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
606 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3W))]
609 [(set_attr "type" "simd_valign")
610 (set_attr "length" "4")
611 (set_attr "cond" "nocond")])
613 (define_insn "vmr4aw_insn"
614 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
615 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
616 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4AW))]
619 [(set_attr "type" "simd_valign_with_acc")
620 (set_attr "length" "4")
621 (set_attr "cond" "nocond")])
623 (define_insn "vmr4w_insn"
624 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
625 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
626 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4W))]
629 [(set_attr "type" "simd_valign")
630 (set_attr "length" "4")
631 (set_attr "cond" "nocond")])
633 (define_insn "vmr5aw_insn"
634 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
635 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
636 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5AW))]
639 [(set_attr "type" "simd_valign_with_acc")
640 (set_attr "length" "4")
641 (set_attr "cond" "nocond")])
643 (define_insn "vmr5w_insn"
644 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
645 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
646 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5W))]
649 [(set_attr "type" "simd_valign")
650 (set_attr "length" "4")
651 (set_attr "cond" "nocond")])
653 (define_insn "vmr6aw_insn"
654 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
655 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
656 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6AW))]
659 [(set_attr "type" "simd_valign_with_acc")
660 (set_attr "length" "4")
661 (set_attr "cond" "nocond")])
663 (define_insn "vmr6w_insn"
664 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
665 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
666 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6W))]
669 [(set_attr "type" "simd_valign")
670 (set_attr "length" "4")
671 (set_attr "cond" "nocond")])
673 (define_insn "vmr7aw_insn"
674 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
675 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
676 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7AW))]
679 [(set_attr "type" "simd_valign_with_acc")
680 (set_attr "length" "4")
681 (set_attr "cond" "nocond")])
683 (define_insn "vmr7w_insn"
684 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
685 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
686 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7W))]
689 [(set_attr "type" "simd_valign")
690 (set_attr "length" "4")
691 (set_attr "cond" "nocond")])
693 (define_insn "vmrb_insn"
694 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
695 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
696 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMRB))]
699 [(set_attr "type" "simd_valign")
700 (set_attr "length" "4")
701 (set_attr "cond" "nocond")])
703 (define_insn "vh264f_insn"
704 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
705 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
706 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264F))]
709 [(set_attr "type" "simd_vspecial_3cycle")
710 (set_attr "length" "4")
711 (set_attr "cond" "nocond")])
713 (define_insn "vh264ft_insn"
714 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
715 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
716 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FT))]
719 [(set_attr "type" "simd_vspecial_3cycle")
720 (set_attr "length" "4")
721 (set_attr "cond" "nocond")])
723 (define_insn "vh264fw_insn"
724 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
725 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
726 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FW))]
729 [(set_attr "type" "simd_vspecial_3cycle")
730 (set_attr "length" "4")
731 (set_attr "cond" "nocond")])
733 (define_insn "vvc1f_insn"
734 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
735 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
736 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1F))]
739 [(set_attr "type" "simd_vspecial_3cycle")
740 (set_attr "length" "4")
741 (set_attr "cond" "nocond")])
743 (define_insn "vvc1ft_insn"
744 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
745 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
746 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1FT))]
749 [(set_attr "type" "simd_vspecial_3cycle")
750 (set_attr "length" "4")
751 (set_attr "cond" "nocond")])
758 ;; (define_insn "vbaddw_insn"
759 ;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
760 ;; (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
761 ;; (match_operand:SI 2 "nonmemory_operand" "rCal")] UNSPEC_ARC_SIMD_VBADDW))]
763 ;; "vbaddw %0, %1, %2"
764 ;; [(set_attr "length" "4")
765 ;; (set_attr "cond" "nocond")])
767 (define_insn "vbaddw_insn"
768 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
769 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
770 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBADDW))]
773 [(set_attr "type" "simd_varith_1cycle")
774 (set_attr "length" "4")
775 (set_attr "cond" "nocond")])
777 (define_insn "vbmaxw_insn"
778 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
779 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
780 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMAXW))]
783 [(set_attr "type" "simd_varith_1cycle")
784 (set_attr "length" "4")
785 (set_attr "cond" "nocond")])
787 (define_insn "vbminw_insn"
788 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
789 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
790 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMINW))]
793 [(set_attr "type" "simd_varith_1cycle")
794 (set_attr "length" "4")
795 (set_attr "cond" "nocond")])
797 (define_insn "vbmulaw_insn"
798 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
799 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
800 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULAW))]
803 [(set_attr "type" "simd_varith_with_acc")
804 (set_attr "length" "4")
805 (set_attr "cond" "nocond")])
807 (define_insn "vbmulfw_insn"
808 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
809 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
810 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULFW))]
813 [(set_attr "type" "simd_varith_2cycle")
814 (set_attr "length" "4")
815 (set_attr "cond" "nocond")])
817 (define_insn "vbmulw_insn"
818 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
819 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
820 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULW))]
823 [(set_attr "type" "simd_varith_2cycle")
824 (set_attr "length" "4")
825 (set_attr "cond" "nocond")])
827 (define_insn "vbrsubw_insn"
828 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
829 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
830 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBRSUBW))]
833 [(set_attr "type" "simd_varith_1cycle")
834 (set_attr "length" "4")
835 (set_attr "cond" "nocond")])
837 (define_insn "vbsubw_insn"
838 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
839 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
840 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBSUBW))]
843 [(set_attr "type" "simd_varith_1cycle")
844 (set_attr "length" "4")
845 (set_attr "cond" "nocond")])
846 ; Va, Vb, Ic instructions
848 ; Va, Vb, u6 instructions
849 (define_insn "vasrrwi_insn"
850 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
851 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
852 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRWi))]
855 [(set_attr "type" "simd_varith_2cycle")
856 (set_attr "length" "4")
857 (set_attr "cond" "nocond")])
859 (define_insn "vasrsrwi_insn"
860 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
861 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
862 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRSRWi))]
864 "vasrsrwi %0, %1, %2"
865 [(set_attr "type" "simd_varith_2cycle")
866 (set_attr "length" "4")
867 (set_attr "cond" "nocond")])
869 (define_insn "vasrwi_insn"
870 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
871 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
872 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRWi))]
875 [(set_attr "type" "simd_varith_1cycle")
876 (set_attr "length" "4")
877 (set_attr "cond" "nocond")])
879 (define_insn "vasrpwbi_insn"
880 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
881 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
882 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRPWBi))]
884 "vasrpwbi %0, %1, %2"
885 [(set_attr "type" "simd_vpack")
886 (set_attr "length" "4")
887 (set_attr "cond" "nocond")])
889 (define_insn "vasrrpwbi_insn"
890 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
891 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
892 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRPWBi))]
894 "vasrrpwbi %0, %1, %2"
895 [(set_attr "type" "simd_vpack")
896 (set_attr "length" "4")
897 (set_attr "cond" "nocond")])
899 (define_insn "vsr8awi_insn"
900 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
901 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
902 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8AWi))]
905 [(set_attr "type" "simd_valign_with_acc")
906 (set_attr "length" "4")
907 (set_attr "cond" "nocond")])
909 (define_insn "vsr8i_insn"
910 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
911 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
912 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8i))]
915 [(set_attr "type" "simd_valign")
916 (set_attr "length" "4")
917 (set_attr "cond" "nocond")])
919 ;; Va, Vb, u8 (simm) insns
921 (define_insn "vmvaw_insn"
922 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
923 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
924 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVAW))]
927 [(set_attr "type" "simd_vmove_with_acc")
928 (set_attr "length" "4")
929 (set_attr "cond" "nocond")])
931 (define_insn "vmvw_insn"
932 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
933 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
934 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVW))]
937 [(set_attr "type" "simd_vmove")
938 (set_attr "length" "4")
939 (set_attr "cond" "nocond")])
941 (define_insn "vmvzw_insn"
942 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
943 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
944 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVZW))]
947 [(set_attr "type" "simd_vmove_else_zero")
948 (set_attr "length" "4")
949 (set_attr "cond" "nocond")])
951 (define_insn "vd6tapf_insn"
952 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
953 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
954 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VD6TAPF))]
957 [(set_attr "type" "simd_vspecial_4cycle")
958 (set_attr "length" "4")
959 (set_attr "cond" "nocond")])
961 ;; Va, rlimm, u8 (simm) insns
962 (define_insn "vmovaw_insn"
963 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
964 (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
965 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVAW))]
968 [(set_attr "type" "simd_vmove_with_acc")
969 (set_attr "length" "4")
970 (set_attr "cond" "nocond")])
972 (define_insn "vmovw_insn"
973 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
974 (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
975 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVW))]
978 [(set_attr "type" "simd_vmove")
979 (set_attr "length" "4")
980 (set_attr "cond" "nocond")])
982 (define_insn "vmovzw_insn"
983 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
984 (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
985 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVZW))]
988 [(set_attr "type" "simd_vmove_else_zero")
989 (set_attr "length" "4")
990 (set_attr "cond" "nocond")])
992 ;; Va, rlimm, Ic insns
993 (define_insn "vsr8_insn"
994 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
995 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
996 (match_operand:SI 2 "immediate_operand" "K")
997 (match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSR8))]
1000 [(set_attr "type" "simd_valign")
1001 (set_attr "length" "4")
1002 (set_attr "cond" "nocond")])
1004 (define_insn "vasrw_insn"
1005 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1006 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
1007 (match_operand:SI 2 "immediate_operand" "K")
1008 (match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VASRW))]
1011 [(set_attr "type" "simd_varith_1cycle")
1012 (set_attr "length" "4")
1013 (set_attr "cond" "nocond")])
1015 (define_insn "vsr8aw_insn"
1016 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1017 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
1018 (match_operand:SI 2 "immediate_operand" "K")
1019 (match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSR8AW))]
1021 "vsr8aw %0, %1, i%2"
1022 [(set_attr "type" "simd_valign_with_acc")
1023 (set_attr "length" "4")
1024 (set_attr "cond" "nocond")])
1027 (define_insn "vabsaw_insn"
1028 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1029 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VABSAW))]
1032 [(set_attr "type" "simd_varith_with_acc")
1033 (set_attr "length" "4")
1034 (set_attr "cond" "nocond")])
1036 (define_insn "vabsw_insn"
1037 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1038 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VABSW))]
1041 [(set_attr "type" "simd_varith_1cycle")
1042 (set_attr "length" "4")
1043 (set_attr "cond" "nocond")])
1045 (define_insn "vaddsuw_insn"
1046 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1047 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDSUW))]
1050 [(set_attr "type" "simd_varith_1cycle")
1051 (set_attr "length" "4")
1052 (set_attr "cond" "nocond")])
1054 (define_insn "vsignw_insn"
1055 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1056 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSIGNW))]
1059 [(set_attr "type" "simd_varith_1cycle")
1060 (set_attr "length" "4")
1061 (set_attr "cond" "nocond")])
1063 (define_insn "vexch1_insn"
1064 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1065 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEXCH1))]
1068 [(set_attr "type" "simd_vpermute")
1069 (set_attr "length" "4")
1070 (set_attr "cond" "nocond")])
1072 (define_insn "vexch2_insn"
1073 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1074 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEXCH2))]
1077 [(set_attr "type" "simd_vpermute")
1078 (set_attr "length" "4")
1079 (set_attr "cond" "nocond")])
1081 (define_insn "vexch4_insn"
1082 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1083 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEXCH4))]
1086 [(set_attr "type" "simd_vpermute")
1087 (set_attr "length" "4")
1088 (set_attr "cond" "nocond")])
1090 (define_insn "vupbaw_insn"
1091 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1092 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VUPBAW))]
1095 [(set_attr "type" "simd_vpack_with_acc")
1096 (set_attr "length" "4")
1097 (set_attr "cond" "nocond")])
1099 (define_insn "vupbw_insn"
1100 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1101 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VUPBW))]
1104 [(set_attr "type" "simd_vpack")
1105 (set_attr "length" "4")
1106 (set_attr "cond" "nocond")])
1108 (define_insn "vupsbaw_insn"
1109 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1110 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VUPSBAW))]
1113 [(set_attr "type" "simd_vpack_with_acc")
1114 (set_attr "length" "4")
1115 (set_attr "cond" "nocond")])
1117 (define_insn "vupsbw_insn"
1118 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1119 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VUPSBW))]
1122 [(set_attr "type" "simd_vpack")
1123 (set_attr "length" "4")
1124 (set_attr "cond" "nocond")])
1126 ; DMA setup instructions
1127 (define_insn "vdirun_insn"
1128 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d")
1129 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r")
1130 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDIRUN))]
1133 [(set_attr "type" "simd_dma")
1134 (set_attr "length" "4")
1135 (set_attr "cond" "nocond")])
1137 (define_insn "vdorun_insn"
1138 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d")
1139 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r")
1140 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDORUN))]
1143 [(set_attr "type" "simd_dma")
1144 (set_attr "length" "4")
1145 (set_attr "cond" "nocond")])
1147 (define_insn "vdiwr_insn"
1148 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d")
1149 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDIWR))]
1152 [(set_attr "type" "simd_dma")
1153 (set_attr "length" "4,8")
1154 (set_attr "cond" "nocond,nocond")])
1156 (define_insn "vdowr_insn"
1157 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d")
1158 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDOWR))]
1161 [(set_attr "type" "simd_dma")
1162 (set_attr "length" "4,8")
1163 (set_attr "cond" "nocond,nocond")])
1165 ;; vector record and run instructions
1166 (define_insn "vrec_insn"
1167 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VREC)]
1170 [(set_attr "type" "simd_vcontrol")
1171 (set_attr "length" "4")
1172 (set_attr "cond" "nocond")])
1174 (define_insn "vrun_insn"
1175 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VRUN)]
1178 [(set_attr "type" "simd_vcontrol")
1179 (set_attr "length" "4")
1180 (set_attr "cond" "nocond")])
1182 (define_insn "vrecrun_insn"
1183 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VRECRUN)]
1186 [(set_attr "type" "simd_vcontrol")
1187 (set_attr "length" "4")
1188 (set_attr "cond" "nocond")])
1190 (define_insn "vendrec_insn"
1191 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VENDREC)]
1194 [(set_attr "type" "simd_vcontrol")
1195 (set_attr "length" "4")
1196 (set_attr "cond" "nocond")])
1198 (define_insn "vld32wh_insn"
1199 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1204 (match_operand:SI 1 "immediate_operand" "P")
1207 (match_operand:V8HI 2 "vector_register_operand" "v")
1208 (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))
1211 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])
1214 "vld32wh %0, [i%3,%1]"
1215 [(set_attr "type" "simd_vload")
1216 (set_attr "length" "4")
1217 (set_attr "cond" "nocond")])
1219 (define_insn "vld32wl_insn"
1220 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1224 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
1228 (match_operand:SI 1 "immediate_operand" "P")
1230 (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v")
1232 [(match_operand:SI 3 "immediate_operand" "L")]))
1235 "vld32wl %0, [i%3,%1]"
1236 [(set_attr "type" "simd_vload")
1237 (set_attr "length" "4")
1238 (set_attr "cond" "nocond")])
1240 (define_insn "vld64w_insn"
1241 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1242 (zero_extend:V8HI (mem:V4HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v")
1243 (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
1244 (match_operand:SI 3 "immediate_operand" "P")))))]
1246 "vld64w %0, [i%2, %3]"
1247 [(set_attr "type" "simd_vload")
1248 (set_attr "length" "4")
1249 (set_attr "cond" "nocond")]
1252 (define_insn "vld64_insn"
1253 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1257 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
1260 (match_operand:SI 1 "immediate_operand" "P")
1263 (match_operand:V8HI 2 "vector_register_operand" "v")
1264 (parallel [(match_operand:SI 3 "immediate_operand" "L")]))
1267 "vld64 %0, [i%3,%1]"
1268 [(set_attr "type" "simd_vload")
1269 (set_attr "length" "4")
1270 (set_attr "cond" "nocond")])
1272 (define_insn "vld32_insn"
1273 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
1277 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
1281 (parallel [(const_int 2) (const_int 3)]))
1284 (match_operand:SI 1 "immediate_operand" "P")
1287 (match_operand:V8HI 2 "vector_register_operand" "v")
1288 (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))))]
1290 "vld32 %0, [i%3,%1]"
1291 [(set_attr "type" "simd_vload")
1292 (set_attr "length" "4")
1293 (set_attr "cond" "nocond")])
1295 (define_insn "vst16_n_insn"
1296 [(set (mem:HI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
1297 (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v")
1298 (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
1299 (vec_select:HI (match_operand:V8HI 3 "vector_register_operand" "v")
1300 (parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
1302 "vst16_%4 %3,[i%2, %0]"
1303 [(set_attr "type" "simd_vstore")
1304 (set_attr "length" "4")
1305 (set_attr "cond" "nocond")])
1307 (define_insn "vst32_n_insn"
1308 [(set (mem:SI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
1309 (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v")
1310 (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
1311 (vec_select:SI (unspec:V4SI [(match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VCAST)
1312 (parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
1314 "vst32_%4 %3,[i%2, %0]"
1315 [(set_attr "type" "simd_vstore")
1316 (set_attr "length" "4")
1317 (set_attr "cond" "nocond")])
1319 ;; SIMD unit interrupt
1320 (define_insn "vinti_insn"
1321 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "L")] UNSPEC_ARC_SIMD_VINTI)]
1324 [(set_attr "type" "simd_vcontrol")
1325 (set_attr "length" "4")
1326 (set_attr "cond" "nocond")])
1328 ;; New ARCv2 SIMD extensions
1330 ;;64-bit vectors of halwords and words
1331 (define_mode_iterator VWH [V4HI V2SI])
1333 ;;double element vectors
1334 (define_mode_iterator VDV [V2HI V2SI])
1335 (define_mode_attr V_addsub [(V2HI "HI") (V2SI "SI")])
1336 (define_mode_attr V_addsub_suffix [(V2HI "2h") (V2SI "")])
1339 (define_mode_iterator VCT [V2HI V4HI V2SI])
1340 (define_mode_attr V_suffix [(V2HI "2h") (V4HI "4h") (V2SI "2")])
1342 ;; Widening operations.
1343 (define_code_iterator SE [sign_extend zero_extend])
1344 (define_code_attr V_US [(sign_extend "s") (zero_extend "u")])
1345 (define_code_attr V_US_suffix [(sign_extend "") (zero_extend "u")])
1349 (define_expand "movv2hi"
1350 [(set (match_operand:V2HI 0 "move_dest_operand" "")
1351 (match_operand:V2HI 1 "general_operand" ""))]
1354 if (prepare_move_operands (operands, V2HImode))
1358 (define_insn_and_split "*movv2hi_insn"
1359 [(set (match_operand:V2HI 0 "move_dest_operand" "=r,r,r,m")
1360 (match_operand:V2HI 1 "general_operand" "i,r,m,r"))]
1361 "(register_operand (operands[0], V2HImode)
1362 || register_operand (operands[1], V2HImode))"
1368 "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
1369 [(set (match_dup 0) (match_dup 2))]
1371 HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
1372 intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF;
1374 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
1375 operands[2] = GEN_INT (trunc_int_for_mode (intval, SImode));
1377 [(set_attr "type" "move,move,load,store")
1378 (set_attr "predicable" "yes,yes,no,no")
1379 (set_attr "iscompact" "false,false,false,false")
1382 (define_expand "movmisalignv2hi"
1383 [(set (match_operand:V2HI 0 "general_operand" "")
1384 (match_operand:V2HI 1 "general_operand" ""))]
1387 if (!register_operand (operands[0], V2HImode)
1388 && !register_operand (operands[1], V2HImode))
1389 operands[1] = force_reg (V2HImode, operands[1]);
1392 (define_expand "mov<mode>"
1393 [(set (match_operand:VWH 0 "move_dest_operand" "")
1394 (match_operand:VWH 1 "general_operand" ""))]
1397 if (GET_CODE (operands[0]) == MEM)
1398 operands[1] = force_reg (<MODE>mode, operands[1]);
1401 (define_insn_and_split "*mov<mode>_insn"
1402 [(set (match_operand:VWH 0 "move_dest_operand" "=r,r,r,m")
1403 (match_operand:VWH 1 "general_operand" "i,r,m,r"))]
1405 && (register_operand (operands[0], <MODE>mode)
1406 || register_operand (operands[1], <MODE>mode))"
1409 switch (which_alternative)
1415 return \"vadd2 %0, %1, 0\";
1419 return \"ldd%U1%V1 %0,%1\";
1424 return \"std%U0%V0 %1,%0\";
1431 arc_split_move (operands);
1434 [(set_attr "type" "move,move,load,store")
1435 (set_attr "predicable" "yes,no,no,no")
1436 (set_attr "iscompact" "false,false,false,false")
1439 (define_expand "movmisalign<mode>"
1440 [(set (match_operand:VWH 0 "general_operand" "")
1441 (match_operand:VWH 1 "general_operand" ""))]
1444 if (!register_operand (operands[0], <MODE>mode)
1445 && !register_operand (operands[1], <MODE>mode))
1446 operands[1] = force_reg (<MODE>mode, operands[1]);
1449 (define_insn "bswapv2hi2"
1450 [(set (match_operand:V2HI 0 "register_operand" "=r,r")
1451 (bswap:V2HI (match_operand:V2HI 1 "nonmemory_operand" "r,i")))]
1452 "TARGET_V2 && TARGET_SWAP"
1454 [(set_attr "length" "4,8")
1455 (set_attr "type" "two_cycle_core")])
1457 ;; Simple arithmetic insns
1458 (define_insn "add<mode>3"
1459 [(set (match_operand:VCT 0 "register_operand" "=r,r")
1460 (plus:VCT (match_operand:VCT 1 "register_operand" "0,r")
1461 (match_operand:VCT 2 "register_operand" "r,r")))]
1463 "vadd<V_suffix>%? %0, %1, %2"
1464 [(set_attr "length" "4")
1465 (set_attr "type" "multi")
1466 (set_attr "predicable" "yes,no")
1467 (set_attr "cond" "canuse,nocond")])
1469 (define_insn "sub<mode>3"
1470 [(set (match_operand:VCT 0 "register_operand" "=r,r")
1471 (minus:VCT (match_operand:VCT 1 "register_operand" "0,r")
1472 (match_operand:VCT 2 "register_operand" "r,r")))]
1474 "vsub<V_suffix>%? %0, %1, %2"
1475 [(set_attr "length" "4")
1476 (set_attr "type" "multi")
1477 (set_attr "predicable" "yes,no")
1478 (set_attr "cond" "canuse,nocond")])
1480 ;; Combined arithmetic ops
1481 (define_insn "addsub<mode>3"
1482 [(set (match_operand:VDV 0 "register_operand" "=r,r")
1484 (plus:<V_addsub> (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r")
1485 (parallel [(const_int 0)]))
1486 (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r")
1487 (parallel [(const_int 0)])))
1488 (minus:<V_addsub> (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)]))
1489 (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))]
1491 "vaddsub<V_addsub_suffix>%? %0, %1, %2"
1492 [(set_attr "length" "4")
1493 (set_attr "type" "multi")
1494 (set_attr "predicable" "yes,no")
1495 (set_attr "cond" "canuse,nocond")])
1497 (define_insn "subadd<mode>3"
1498 [(set (match_operand:VDV 0 "register_operand" "=r,r")
1500 (minus:<V_addsub> (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r")
1501 (parallel [(const_int 0)]))
1502 (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r")
1503 (parallel [(const_int 0)])))
1504 (plus:<V_addsub> (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)]))
1505 (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))]
1507 "vsubadd<V_addsub_suffix>%? %0, %1, %2"
1508 [(set_attr "length" "4")
1509 (set_attr "type" "multi")
1510 (set_attr "predicable" "yes,no")
1511 (set_attr "cond" "canuse,nocond")])
1513 (define_insn "addsubv4hi3"
1514 [(set (match_operand:V4HI 0 "even_register_operand" "=r,r")
1517 (plus:HI (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r")
1518 (parallel [(const_int 0)]))
1519 (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r")
1520 (parallel [(const_int 0)])))
1521 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
1522 (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
1524 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
1525 (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
1526 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
1527 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
1530 "vaddsub4h%? %0, %1, %2"
1531 [(set_attr "length" "4")
1532 (set_attr "type" "multi")
1533 (set_attr "predicable" "yes,no")
1534 (set_attr "cond" "canuse,nocond")])
1536 (define_insn "subaddv4hi3"
1537 [(set (match_operand:V4HI 0 "even_register_operand" "=r,r")
1540 (minus:HI (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r")
1541 (parallel [(const_int 0)]))
1542 (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r")
1543 (parallel [(const_int 0)])))
1544 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
1545 (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
1547 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
1548 (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
1549 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
1550 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
1553 "vsubadd4h%? %0, %1, %2"
1554 [(set_attr "length" "4")
1555 (set_attr "type" "multi")
1556 (set_attr "predicable" "yes,no")
1557 (set_attr "cond" "canuse,nocond")])
1560 (define_insn "dmpyh<V_US_suffix>"
1561 [(set (match_operand:SI 0 "register_operand" "=r,r")
1565 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,r")
1566 (parallel [(const_int 0)])))
1568 (vec_select:HI (match_operand:V2HI 2 "register_operand" "r,r")
1569 (parallel [(const_int 0)]))))
1571 (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
1572 (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))))
1573 (set (reg:DI ARCV2_ACC)
1577 (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
1578 (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
1580 (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
1581 (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))))]
1583 "dmpyh<V_US_suffix>%? %0, %1, %2"
1584 [(set_attr "length" "4")
1585 (set_attr "type" "multi")
1586 (set_attr "predicable" "yes,no")
1587 (set_attr "cond" "canuse,nocond")])
1589 ;; We can use dmac as well here. To be investigated which version
1591 (define_expand "sdot_prodv2hi"
1592 [(match_operand:SI 0 "register_operand" "")
1593 (match_operand:V2HI 1 "register_operand" "")
1594 (match_operand:V2HI 2 "register_operand" "")
1595 (match_operand:SI 3 "register_operand" "")]
1598 rtx t = gen_reg_rtx (SImode);
1599 emit_insn (gen_dmpyh (t, operands[1], operands[2]));
1600 emit_insn (gen_addsi3 (operands[0], operands[3], t));
1604 (define_expand "udot_prodv2hi"
1605 [(match_operand:SI 0 "register_operand" "")
1606 (match_operand:V2HI 1 "register_operand" "")
1607 (match_operand:V2HI 2 "register_operand" "")
1608 (match_operand:SI 3 "register_operand" "")]
1611 rtx t = gen_reg_rtx (SImode);
1612 emit_insn (gen_dmpyhu (t, operands[1], operands[2]));
1613 emit_insn (gen_addsi3 (operands[0], operands[3], t));
1617 (define_insn "arc_vec_<V_US>mult_lo_v4hi"
1618 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
1619 (mult:V2SI (SE:V2SI (vec_select:V2HI
1620 (match_operand:V4HI 1 "even_register_operand" "0,r")
1621 (parallel [(const_int 0) (const_int 1)])))
1622 (SE:V2SI (vec_select:V2HI
1623 (match_operand:V4HI 2 "even_register_operand" "r,r")
1624 (parallel [(const_int 0) (const_int 1)])))))
1625 (set (reg:V2SI ARCV2_ACC)
1626 (mult:V2SI (SE:V2SI (vec_select:V2HI (match_dup 1)
1627 (parallel [(const_int 0) (const_int 1)])))
1628 (SE:V2SI (vec_select:V2HI (match_dup 2)
1629 (parallel [(const_int 0) (const_int 1)])))))
1632 "vmpy2h<V_US_suffix>%? %0, %1, %2"
1633 [(set_attr "length" "4")
1634 (set_attr "type" "multi")
1635 (set_attr "predicable" "yes,no")
1636 (set_attr "cond" "canuse,nocond")])
1638 (define_insn "arc_vec_<V_US>multacc_lo_v4hi"
1639 [(set (reg:V2SI ARCV2_ACC)
1640 (mult:V2SI (SE:V2SI (vec_select:V2HI
1641 (match_operand:V4HI 0 "even_register_operand" "r")
1642 (parallel [(const_int 0) (const_int 1)])))
1643 (SE:V2SI (vec_select:V2HI
1644 (match_operand:V4HI 1 "even_register_operand" "r")
1645 (parallel [(const_int 0) (const_int 1)])))))
1648 "vmpy2h<V_US_suffix>%? 0, %0, %1"
1649 [(set_attr "length" "4")
1650 (set_attr "type" "multi")
1651 (set_attr "predicable" "no")
1652 (set_attr "cond" "nocond")])
1654 (define_expand "vec_widen_<V_US>mult_lo_v4hi"
1655 [(set (match_operand:V2SI 0 "even_register_operand" "")
1656 (mult:V2SI (SE:V2SI (vec_select:V2HI
1657 (match_operand:V4HI 1 "even_register_operand" "")
1658 (parallel [(const_int 0) (const_int 1)])))
1659 (SE:V2SI (vec_select:V2HI
1660 (match_operand:V4HI 2 "even_register_operand" "")
1661 (parallel [(const_int 0) (const_int 1)])))))]
1664 emit_insn (gen_arc_vec_<V_US>mult_lo_v4hi (operands[0],
1671 (define_insn "arc_vec_<V_US>mult_hi_v4hi"
1672 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
1673 (mult:V2SI (SE:V2SI (vec_select:V2HI
1674 (match_operand:V4HI 1 "even_register_operand" "0,r")
1675 (parallel [(const_int 2) (const_int 3)])))
1676 (SE:V2SI (vec_select:V2HI
1677 (match_operand:V4HI 2 "even_register_operand" "r,r")
1678 (parallel [(const_int 2) (const_int 3)])))))
1679 (set (reg:V2SI ARCV2_ACC)
1680 (mult:V2SI (SE:V2SI (vec_select:V2HI (match_dup 1)
1681 (parallel [(const_int 2) (const_int 3)])))
1682 (SE:V2SI (vec_select:V2HI (match_dup 2)
1683 (parallel [(const_int 2) (const_int 3)])))))
1686 "vmpy2h<V_US_suffix>%? %0, %R1, %R2"
1687 [(set_attr "length" "4")
1688 (set_attr "type" "multi")
1689 (set_attr "predicable" "yes,no")
1690 (set_attr "cond" "canuse,nocond")])
1692 (define_expand "vec_widen_<V_US>mult_hi_v4hi"
1693 [(set (match_operand:V2SI 0 "even_register_operand" "")
1694 (mult:V2SI (SE:V2SI (vec_select:V2HI
1695 (match_operand:V4HI 1 "even_register_operand" "")
1696 (parallel [(const_int 2) (const_int 3)])))
1697 (SE:V2SI (vec_select:V2HI
1698 (match_operand:V4HI 2 "even_register_operand" "")
1699 (parallel [(const_int 2) (const_int 3)])))))]
1702 emit_insn (gen_arc_vec_<V_US>mult_hi_v4hi (operands[0],
1709 (define_insn "arc_vec_<V_US>mac_hi_v4hi"
1710 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
1712 (reg:V2SI ARCV2_ACC)
1713 (mult:V2SI (SE:V2SI (vec_select:V2HI
1714 (match_operand:V4HI 1 "even_register_operand" "0,r")
1715 (parallel [(const_int 2) (const_int 3)])))
1716 (SE:V2SI (vec_select:V2HI
1717 (match_operand:V4HI 2 "even_register_operand" "r,r")
1718 (parallel [(const_int 2) (const_int 3)]))))))
1719 (set (reg:V2SI ARCV2_ACC)
1721 (reg:V2SI ARCV2_ACC)
1722 (mult:V2SI (SE:V2SI (vec_select:V2HI (match_dup 1)
1723 (parallel [(const_int 2) (const_int 3)])))
1724 (SE:V2SI (vec_select:V2HI (match_dup 2)
1725 (parallel [(const_int 2) (const_int 3)]))))))
1728 "vmac2h<V_US_suffix>%? %0, %R1, %R2"
1729 [(set_attr "length" "4")
1730 (set_attr "type" "multi")
1731 (set_attr "predicable" "yes,no")
1732 (set_attr "cond" "canuse,nocond")])
1735 (define_insn "dmach"
1736 [(set (match_operand:SI 0 "register_operand" "=r,r")
1737 (unspec:SI [(match_operand:V2HI 1 "register_operand" "0,r")
1738 (match_operand:V2HI 2 "register_operand" "r,r")
1741 (clobber (reg:DI ARCV2_ACC))]
1743 "dmach%? %0, %1, %2"
1744 [(set_attr "length" "4")
1745 (set_attr "type" "multi")
1746 (set_attr "predicable" "yes,no")
1747 (set_attr "cond" "canuse,nocond")])
1749 (define_insn "dmachu"
1750 [(set (match_operand:SI 0 "register_operand" "=r,r")
1751 (unspec:SI [(match_operand:V2HI 1 "register_operand" "0,r")
1752 (match_operand:V2HI 2 "register_operand" "r,r")
1755 (clobber (reg:DI ARCV2_ACC))]
1757 "dmachu%? %0, %1, %2"
1758 [(set_attr "length" "4")
1759 (set_attr "type" "multi")
1760 (set_attr "predicable" "yes,no")
1761 (set_attr "cond" "canuse,nocond")])
1763 (define_insn "dmacwh"
1764 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
1765 (unspec:DI [(match_operand:V2SI 1 "even_register_operand" "0,r")
1766 (match_operand:V2HI 2 "register_operand" "r,r")
1769 (clobber (reg:DI ARCV2_ACC))]
1771 "dmacwh%? %0, %1, %2"
1772 [(set_attr "length" "4")
1773 (set_attr "type" "multi")
1774 (set_attr "predicable" "yes,no")
1775 (set_attr "cond" "canuse,nocond")])
1777 (define_insn "dmacwhu"
1778 [(set (match_operand:DI 0 "register_operand" "=r,r")
1779 (unspec:DI [(match_operand:V2SI 1 "even_register_operand" "0,r")
1780 (match_operand:V2HI 2 "register_operand" "r,r")
1782 UNSPEC_ARC_DMACWHU))
1783 (clobber (reg:DI ARCV2_ACC))]
1785 "dmacwhu%? %0, %1, %2"
1786 [(set_attr "length" "4")
1787 (set_attr "type" "multi")
1788 (set_attr "predicable" "yes,no")
1789 (set_attr "cond" "canuse,nocond")])
1791 (define_insn "vmac2h"
1792 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
1793 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r")
1794 (match_operand:V2HI 2 "register_operand" "r,r")
1797 (clobber (reg:DI ARCV2_ACC))]
1799 "vmac2h%? %0, %1, %2"
1800 [(set_attr "length" "4")
1801 (set_attr "type" "multi")
1802 (set_attr "predicable" "yes,no")
1803 (set_attr "cond" "canuse,nocond")])
1805 (define_insn "vmac2hu"
1806 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
1807 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r")
1808 (match_operand:V2HI 2 "register_operand" "r,r")
1810 UNSPEC_ARC_VMAC2HU))
1811 (clobber (reg:DI ARCV2_ACC))]
1813 "vmac2hu%? %0, %1, %2"
1814 [(set_attr "length" "4")
1815 (set_attr "type" "multi")
1816 (set_attr "predicable" "yes,no")
1817 (set_attr "cond" "canuse,nocond")])
1819 (define_insn "vmpy2h"
1820 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
1821 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r")
1822 (match_operand:V2HI 2 "register_operand" "r,r")]
1824 (clobber (reg:DI ARCV2_ACC))]
1826 "vmpy2h%? %0, %1, %2"
1827 [(set_attr "length" "4")
1828 (set_attr "type" "multi")
1829 (set_attr "predicable" "yes,no")
1830 (set_attr "cond" "canuse,nocond")])
1832 (define_insn "vmpy2hu"
1833 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
1834 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r")
1835 (match_operand:V2HI 2 "register_operand" "r,r")]
1836 UNSPEC_ARC_VMPY2HU))
1837 (clobber (reg:DI ARCV2_ACC))]
1839 "vmpy2hu%? %0, %1, %2"
1840 [(set_attr "length" "4")
1841 (set_attr "type" "multi")
1842 (set_attr "predicable" "yes,no")
1843 (set_attr "cond" "canuse,nocond")])
1845 (define_insn "qmach"
1846 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
1847 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r")
1848 (match_operand:V4HI 2 "even_register_operand" "r,r")
1851 (clobber (reg:DI ARCV2_ACC))]
1853 "qmach%? %0, %1, %2"
1854 [(set_attr "length" "4")
1855 (set_attr "type" "multi")
1856 (set_attr "predicable" "yes,no")
1857 (set_attr "cond" "canuse,nocond")])
1859 (define_insn "qmachu"
1860 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
1861 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r")
1862 (match_operand:V4HI 2 "even_register_operand" "r,r")
1865 (clobber (reg:DI ARCV2_ACC))]
1867 "qmachu%? %0, %1, %2"
1868 [(set_attr "length" "4")
1869 (set_attr "type" "multi")
1870 (set_attr "predicable" "yes,no")
1871 (set_attr "cond" "canuse,nocond")])
1873 (define_insn "qmpyh"
1874 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
1875 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r")
1876 (match_operand:V4HI 2 "even_register_operand" "r,r")]
1878 (clobber (reg:DI ARCV2_ACC))]
1880 "qmpyh%? %0, %1, %2"
1881 [(set_attr "length" "4")
1882 (set_attr "type" "multi")
1883 (set_attr "predicable" "yes,no")
1884 (set_attr "cond" "canuse,nocond")])
1886 (define_insn "qmpyhu"
1887 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
1888 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r")
1889 (match_operand:V4HI 2 "even_register_operand" "r,r")]
1891 (clobber (reg:DI ARCV2_ACC))]
1893 "qmpyhu%? %0, %1, %2"
1894 [(set_attr "length" "4")
1895 (set_attr "type" "multi")
1896 (set_attr "predicable" "yes,no")
1897 (set_attr "cond" "canuse,nocond")])