1 /* Copyright (C
) 2015-2017 Free Software Foundation
, Inc.
3 This file is part of GCC.
5 GCC is free software
; you can redistribute it and
/or modify it under
6 the terms of the GNU General Public License as published by the Free
7 Software Foundation
; either version
3, or (at your option
) any later
10 GCC is distributed in the hope that it will be useful
, but WITHOUT ANY
11 WARRANTY
; without even the implied warranty of MERCHANTABILITY or
12 FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 You should have received a copy of the GNU General Public License
16 along with GCC
; see the file COPYING3. If not see
17 <http
://www.gnu.org
/licenses
/>.
*/
19 /* This file contains the definitions and documentation for the
20 builtins defined in the ARC part of the GNU compiler. Before
21 including this file
, define a macro
23 DEF_BUILTIN(NAME
, N_ARGS
, TYPE, ICODE
, MASK
)
25 NAME
: `__builtin_arc_name
' will be the user-level name of the builtin.
26 `ARC_BUILTIN_NAME' will be the internal builtin
's id.
27 N_ARGS: Number of input arguments. If special treatment is needed,
28 set to -1 and handle it by hand, see arc.c:arc_expand_builtin().
29 TYPE: A tree node describing the prototype of the built-in.
30 ICODE: Name of attached insn or expander. If special treatment in arc.c
31 is needed to expand the built-in, use `nothing'.
32 MASK
: CPU selector mask.
*/
34 /* Special builtins.
*/
35 DEF_BUILTIN (NOP
, 0, void_ftype_void
, nothing
, 1)
36 DEF_BUILTIN (RTIE
, 0, void_ftype_void
, rtie
, 1)
37 DEF_BUILTIN (SYNC
, 0, void_ftype_void
, sync
, TARGET_ARC700
)
38 DEF_BUILTIN (BRK
, 0, void_ftype_void
, brk
, 1)
39 DEF_BUILTIN (SWI
, 0, void_ftype_void
, swi
, 1)
40 DEF_BUILTIN (UNIMP_S
, 0, void_ftype_void
, unimp_s
, !TARGET_ARC600_FAMILY
)
41 DEF_BUILTIN (TRAP_S
, 1, void_ftype_usint
, trap_s
, !TARGET_ARC600_FAMILY
)
42 DEF_BUILTIN (ALIGNED
, 2, int_ftype_pcvoid_int
, nothing
, 1)
43 DEF_BUILTIN (CLRI
, 0, int_ftype_void
, clri
, TARGET_V2
)
44 DEF_BUILTIN (SLEEP
, 1, void_ftype_usint
, sleep
, 1)
46 DEF_BUILTIN (FLAG
, 1, void_ftype_usint
, flag
, 1)
47 DEF_BUILTIN (SR
, 2, void_ftype_usint_usint
, sr
, 1)
48 DEF_BUILTIN (KFLAG
, 1, void_ftype_usint
, kflag
, TARGET_V2
)
49 DEF_BUILTIN (CORE_WRITE
, 2, void_ftype_usint_usint
, core_write
, 1)
50 DEF_BUILTIN (SETI
, 1, void_ftype_int
, seti
, TARGET_V2
)
52 /* Regular builtins.
*/
53 DEF_BUILTIN (NORM
, 1, int_ftype_int
, clrsbsi2
, TARGET_NORM
)
54 DEF_BUILTIN (NORMW
, 1, int_ftype_short
, normw
, TARGET_NORM
)
55 DEF_BUILTIN (SWAP
, 1, int_ftype_int
, swap
, TARGET_SWAP
)
56 DEF_BUILTIN (DIVAW
, 2, int_ftype_int_int
, divaw
, TARGET_EA_SET
)
57 DEF_BUILTIN (CORE_READ
, 1, usint_ftype_usint
, core_read
, 1)
58 DEF_BUILTIN (LR
, 1, usint_ftype_usint
, lr
, 1)
59 DEF_BUILTIN (FFS
, 1, int_ftype_int
, ffs
, (TARGET_EM
&& TARGET_NORM
) || TARGET_HS
)
60 DEF_BUILTIN (FLS
, 1, int_ftype_int
, fls
, (TARGET_EM
&& TARGET_NORM
) || TARGET_HS
)
62 /* ARC SIMD extenssion.
*/
63 /* BEGIN SIMD marker.
*/
64 DEF_BUILTIN (SIMD_BEGIN
, 0, void_ftype_void
, nothing
, 0)
66 DEF_BUILTIN ( VADDAW
, 2, v8hi_ftype_v8hi_v8hi
, vaddaw_insn
, TARGET_SIMD_SET
)
67 DEF_BUILTIN ( VADDW
, 2, v8hi_ftype_v8hi_v8hi
, vaddw_insn
, TARGET_SIMD_SET
)
68 DEF_BUILTIN ( VAVB
, 2, v8hi_ftype_v8hi_v8hi
, vavb_insn
, TARGET_SIMD_SET
)
69 DEF_BUILTIN ( VAVRB
, 2, v8hi_ftype_v8hi_v8hi
, vavrb_insn
, TARGET_SIMD_SET
)
70 DEF_BUILTIN ( VDIFAW
, 2, v8hi_ftype_v8hi_v8hi
, vdifaw_insn
, TARGET_SIMD_SET
)
71 DEF_BUILTIN ( VDIFW
, 2, v8hi_ftype_v8hi_v8hi
, vdifw_insn
, TARGET_SIMD_SET
)
72 DEF_BUILTIN ( VMAXAW
, 2, v8hi_ftype_v8hi_v8hi
, vmaxaw_insn
, TARGET_SIMD_SET
)
73 DEF_BUILTIN ( VMAXW
, 2, v8hi_ftype_v8hi_v8hi
, vmaxw_insn
, TARGET_SIMD_SET
)
74 DEF_BUILTIN ( VMINAW
, 2, v8hi_ftype_v8hi_v8hi
, vminaw_insn
, TARGET_SIMD_SET
)
75 DEF_BUILTIN ( VMINW
, 2, v8hi_ftype_v8hi_v8hi
, vminw_insn
, TARGET_SIMD_SET
)
76 DEF_BUILTIN ( VMULAW
, 2, v8hi_ftype_v8hi_v8hi
, vmulaw_insn
, TARGET_SIMD_SET
)
77 DEF_BUILTIN (VMULFAW
, 2, v8hi_ftype_v8hi_v8hi
, vmulfaw_insn
, TARGET_SIMD_SET
)
78 DEF_BUILTIN ( VMULFW
, 2, v8hi_ftype_v8hi_v8hi
, vmulfw_insn
, TARGET_SIMD_SET
)
79 DEF_BUILTIN ( VMULW
, 2, v8hi_ftype_v8hi_v8hi
, vmulw_insn
, TARGET_SIMD_SET
)
80 DEF_BUILTIN ( VSUBAW
, 2, v8hi_ftype_v8hi_v8hi
, vsubaw_insn
, TARGET_SIMD_SET
)
81 DEF_BUILTIN ( VSUBW
, 2, v8hi_ftype_v8hi_v8hi
, vsubw_insn
, TARGET_SIMD_SET
)
82 DEF_BUILTIN ( VSUMMW
, 2, v8hi_ftype_v8hi_v8hi
, vsummw_insn
, TARGET_SIMD_SET
)
83 DEF_BUILTIN ( VAND
, 2, v8hi_ftype_v8hi_v8hi
, vand_insn
, TARGET_SIMD_SET
)
84 DEF_BUILTIN ( VANDAW
, 2, v8hi_ftype_v8hi_v8hi
, vandaw_insn
, TARGET_SIMD_SET
)
85 DEF_BUILTIN ( VBIC
, 2, v8hi_ftype_v8hi_v8hi
, vbic_insn
, TARGET_SIMD_SET
)
86 DEF_BUILTIN ( VBICAW
, 2, v8hi_ftype_v8hi_v8hi
, vbicaw_insn
, TARGET_SIMD_SET
)
87 DEF_BUILTIN ( VOR
, 2, v8hi_ftype_v8hi_v8hi
, vor_insn
, TARGET_SIMD_SET
)
88 DEF_BUILTIN ( VXOR
, 2, v8hi_ftype_v8hi_v8hi
, vxor_insn
, TARGET_SIMD_SET
)
89 DEF_BUILTIN ( VXORAW
, 2, v8hi_ftype_v8hi_v8hi
, vxoraw_insn
, TARGET_SIMD_SET
)
90 DEF_BUILTIN ( VEQW
, 2, v8hi_ftype_v8hi_v8hi
, veqw_insn
, TARGET_SIMD_SET
)
91 DEF_BUILTIN ( VLEW
, 2, v8hi_ftype_v8hi_v8hi
, vlew_insn
, TARGET_SIMD_SET
)
92 DEF_BUILTIN ( VLTW
, 2, v8hi_ftype_v8hi_v8hi
, vltw_insn
, TARGET_SIMD_SET
)
93 DEF_BUILTIN ( VNEW
, 2, v8hi_ftype_v8hi_v8hi
, vnew_insn
, TARGET_SIMD_SET
)
94 DEF_BUILTIN ( VMR1AW
, 2, v8hi_ftype_v8hi_v8hi
, vmr1aw_insn
, TARGET_SIMD_SET
)
95 DEF_BUILTIN ( VMR1W
, 2, v8hi_ftype_v8hi_v8hi
, vmr1w_insn
, TARGET_SIMD_SET
)
96 DEF_BUILTIN ( VMR2AW
, 2, v8hi_ftype_v8hi_v8hi
, vmr2aw_insn
, TARGET_SIMD_SET
)
97 DEF_BUILTIN ( VMR2W
, 2, v8hi_ftype_v8hi_v8hi
, vmr2w_insn
, TARGET_SIMD_SET
)
98 DEF_BUILTIN ( VMR3AW
, 2, v8hi_ftype_v8hi_v8hi
, vmr3aw_insn
, TARGET_SIMD_SET
)
99 DEF_BUILTIN ( VMR3W
, 2, v8hi_ftype_v8hi_v8hi
, vmr3w_insn
, TARGET_SIMD_SET
)
100 DEF_BUILTIN ( VMR4AW
, 2, v8hi_ftype_v8hi_v8hi
, vmr4aw_insn
, TARGET_SIMD_SET
)
101 DEF_BUILTIN ( VMR4W
, 2, v8hi_ftype_v8hi_v8hi
, vmr4w_insn
, TARGET_SIMD_SET
)
102 DEF_BUILTIN ( VMR5AW
, 2, v8hi_ftype_v8hi_v8hi
, vmr5aw_insn
, TARGET_SIMD_SET
)
103 DEF_BUILTIN ( VMR5W
, 2, v8hi_ftype_v8hi_v8hi
, vmr5w_insn
, TARGET_SIMD_SET
)
104 DEF_BUILTIN ( VMR6AW
, 2, v8hi_ftype_v8hi_v8hi
, vmr6aw_insn
, TARGET_SIMD_SET
)
105 DEF_BUILTIN ( VMR6W
, 2, v8hi_ftype_v8hi_v8hi
, vmr6w_insn
, TARGET_SIMD_SET
)
106 DEF_BUILTIN ( VMR7AW
, 2, v8hi_ftype_v8hi_v8hi
, vmr7aw_insn
, TARGET_SIMD_SET
)
107 DEF_BUILTIN ( VMR7W
, 2, v8hi_ftype_v8hi_v8hi
, vmr7w_insn
, TARGET_SIMD_SET
)
108 DEF_BUILTIN ( VMRB
, 2, v8hi_ftype_v8hi_v8hi
, vmrb_insn
, TARGET_SIMD_SET
)
109 DEF_BUILTIN ( VH264F
, 2, v8hi_ftype_v8hi_v8hi
, vh264f_insn
, TARGET_SIMD_SET
)
110 DEF_BUILTIN (VH264FT
, 2, v8hi_ftype_v8hi_v8hi
, vh264ft_insn
, TARGET_SIMD_SET
)
111 DEF_BUILTIN (VH264FW
, 2, v8hi_ftype_v8hi_v8hi
, vh264fw_insn
, TARGET_SIMD_SET
)
112 DEF_BUILTIN ( VVC1F
, 2, v8hi_ftype_v8hi_v8hi
, vvc1f_insn
, TARGET_SIMD_SET
)
113 DEF_BUILTIN ( VVC1FT
, 2, v8hi_ftype_v8hi_v8hi
, vvc1ft_insn
, TARGET_SIMD_SET
)
115 DEF_BUILTIN ( VBADDW
, 2, v8hi_ftype_v8hi_int
, vbaddw_insn
, TARGET_SIMD_SET
)
116 DEF_BUILTIN ( VBMAXW
, 2, v8hi_ftype_v8hi_int
, vbmaxw_insn
, TARGET_SIMD_SET
)
117 DEF_BUILTIN ( VBMINW
, 2, v8hi_ftype_v8hi_int
, vbminw_insn
, TARGET_SIMD_SET
)
118 DEF_BUILTIN (VBMULAW
, 2, v8hi_ftype_v8hi_int
, vbmulaw_insn
, TARGET_SIMD_SET
)
119 DEF_BUILTIN (VBMULFW
, 2, v8hi_ftype_v8hi_int
, vbmulfw_insn
, TARGET_SIMD_SET
)
120 DEF_BUILTIN ( VBMULW
, 2, v8hi_ftype_v8hi_int
, vbmulw_insn
, TARGET_SIMD_SET
)
121 DEF_BUILTIN (VBRSUBW
, 2, v8hi_ftype_v8hi_int
, vbrsubw_insn
, TARGET_SIMD_SET
)
122 DEF_BUILTIN ( VBSUBW
, 2, v8hi_ftype_v8hi_int
, vbsubw_insn
, TARGET_SIMD_SET
)
124 /* Va
, Vb
, Ic instructions.
*/
125 DEF_BUILTIN ( VASRW
, 2, v8hi_ftype_v8hi_int
, vasrw_insn
, TARGET_SIMD_SET
)
126 DEF_BUILTIN ( VSR8
, 2, v8hi_ftype_v8hi_int
, vsr8_insn
, TARGET_SIMD_SET
)
127 DEF_BUILTIN (VSR8AW
, 2, v8hi_ftype_v8hi_int
, vsr8aw_insn
, TARGET_SIMD_SET
)
129 /* Va
, Vb
, u6 instructions.
*/
130 DEF_BUILTIN ( VASRRWi
, 2, v8hi_ftype_v8hi_int
, vasrrwi_insn
, TARGET_SIMD_SET
)
131 DEF_BUILTIN ( VASRSRWi
, 2, v8hi_ftype_v8hi_int
, vasrsrwi_insn
, TARGET_SIMD_SET
)
132 DEF_BUILTIN ( VASRWi
, 2, v8hi_ftype_v8hi_int
, vasrwi_insn
, TARGET_SIMD_SET
)
133 DEF_BUILTIN ( VASRPWBi
, 2, v8hi_ftype_v8hi_int
, vasrpwbi_insn
, TARGET_SIMD_SET
)
134 DEF_BUILTIN (VASRRPWBi
, 2, v8hi_ftype_v8hi_int
, vasrrpwbi_insn
, TARGET_SIMD_SET
)
135 DEF_BUILTIN ( VSR8AWi
, 2, v8hi_ftype_v8hi_int
, vsr8awi_insn
, TARGET_SIMD_SET
)
136 DEF_BUILTIN ( VSR8i
, 2, v8hi_ftype_v8hi_int
, vsr8i_insn
, TARGET_SIMD_SET
)
138 /* Va
, Vb
, u8 (simm
) instructions.
*/
139 DEF_BUILTIN ( VMVAW
, 2, v8hi_ftype_v8hi_int
, vmvaw_insn
, TARGET_SIMD_SET
)
140 DEF_BUILTIN ( VMVW
, 2, v8hi_ftype_v8hi_int
, vmvw_insn
, TARGET_SIMD_SET
)
141 DEF_BUILTIN ( VMVZW
, 2, v8hi_ftype_v8hi_int
, vmvzw_insn
, TARGET_SIMD_SET
)
142 DEF_BUILTIN (VD6TAPF
, 2, v8hi_ftype_v8hi_int
, vd6tapf_insn
, TARGET_SIMD_SET
)
144 /* Va
, rlimm
, u8 (simm
) instructions.
*/
145 DEF_BUILTIN (VMOVAW
, 2, v8hi_ftype_int_int
, vmovaw_insn
, TARGET_SIMD_SET
)
146 DEF_BUILTIN ( VMOVW
, 2, v8hi_ftype_int_int
, vmovw_insn
, TARGET_SIMD_SET
)
147 DEF_BUILTIN (VMOVZW
, 2, v8hi_ftype_int_int
, vmovzw_insn
, TARGET_SIMD_SET
)
149 /* Va
, Vb instructions.
*/
150 DEF_BUILTIN ( VABSAW
, 1, v8hi_ftype_v8hi
, vabsaw_insn
, TARGET_SIMD_SET
)
151 DEF_BUILTIN ( VABSW
, 1, v8hi_ftype_v8hi
, vabsw_insn
, TARGET_SIMD_SET
)
152 DEF_BUILTIN (VADDSUW
, 1, v8hi_ftype_v8hi
, vaddsuw_insn
, TARGET_SIMD_SET
)
153 DEF_BUILTIN ( VSIGNW
, 1, v8hi_ftype_v8hi
, vsignw_insn
, TARGET_SIMD_SET
)
154 DEF_BUILTIN ( VEXCH1
, 1, v8hi_ftype_v8hi
, vexch1_insn
, TARGET_SIMD_SET
)
155 DEF_BUILTIN ( VEXCH2
, 1, v8hi_ftype_v8hi
, vexch2_insn
, TARGET_SIMD_SET
)
156 DEF_BUILTIN ( VEXCH4
, 1, v8hi_ftype_v8hi
, vexch4_insn
, TARGET_SIMD_SET
)
157 DEF_BUILTIN ( VUPBAW
, 1, v8hi_ftype_v8hi
, vupbaw_insn
, TARGET_SIMD_SET
)
158 DEF_BUILTIN ( VUPBW
, 1, v8hi_ftype_v8hi
, vupbw_insn
, TARGET_SIMD_SET
)
159 DEF_BUILTIN (VUPSBAW
, 1, v8hi_ftype_v8hi
, vupsbaw_insn
, TARGET_SIMD_SET
)
160 DEF_BUILTIN ( VUPSBW
, 1, v8hi_ftype_v8hi
, vupsbw_insn
, TARGET_SIMD_SET
)
162 /* SIMD special DIb
, rlimm
, rlimm instructions.
*/
163 DEF_BUILTIN (VDIRUN
, 2, void_ftype_int_int
, vdirun_insn
, TARGET_SIMD_SET
)
164 DEF_BUILTIN (VDORUN
, 2, void_ftype_int_int
, vdorun_insn
, TARGET_SIMD_SET
)
166 /* SIMD special DIb
, limm
, rlimm instructions.
*/
167 DEF_BUILTIN (VDIWR
, 2, void_ftype_int_int
, vdiwr_insn
, TARGET_SIMD_SET
)
168 DEF_BUILTIN (VDOWR
, 2, void_ftype_int_int
, vdowr_insn
, TARGET_SIMD_SET
)
170 /* rlimm instructions.
*/
171 DEF_BUILTIN ( VREC
, 1, void_ftype_int
, vrec_insn
, TARGET_SIMD_SET
)
172 DEF_BUILTIN ( VRUN
, 1, void_ftype_int
, vrun_insn
, TARGET_SIMD_SET
)
173 DEF_BUILTIN (VRECRUN
, 1, void_ftype_int
, vrecrun_insn
, TARGET_SIMD_SET
)
174 DEF_BUILTIN (VENDREC
, 1, void_ftype_int
, vendrec_insn
, TARGET_SIMD_SET
)
176 /* Va
, [Ib
,u8
] instructions.
*/
177 DEF_BUILTIN (VLD32WH
, 3, v8hi_ftype_v8hi_int_int
, vld32wh_insn
, TARGET_SIMD_SET
)
178 DEF_BUILTIN (VLD32WL
, 3, v8hi_ftype_v8hi_int_int
, vld32wl_insn
, TARGET_SIMD_SET
)
179 DEF_BUILTIN ( VLD64
, 3, v8hi_ftype_v8hi_int_int
, vld64_insn
, TARGET_SIMD_SET
)
180 DEF_BUILTIN ( VLD32
, 3, v8hi_ftype_v8hi_int_int
, vld32_insn
, TARGET_SIMD_SET
)
182 DEF_BUILTIN (VLD64W
, 2, v8hi_ftype_int_int
, vld64w_insn
, TARGET_SIMD_SET
)
183 DEF_BUILTIN (VLD128
, 2, v8hi_ftype_int_int
, vld128_insn
, TARGET_SIMD_SET
)
185 DEF_BUILTIN (VST128
, 3, void_ftype_v8hi_int_int
, vst128_insn
, TARGET_SIMD_SET
)
186 DEF_BUILTIN ( VST64
, 3, void_ftype_v8hi_int_int
, vst64_insn
, TARGET_SIMD_SET
)
188 /* Va
, [Ib
, u8
] instructions.
*/
189 DEF_BUILTIN (VST16_N
, 4, void_ftype_v8hi_int_int_int
, vst16_n_insn
, TARGET_SIMD_SET
)
190 DEF_BUILTIN (VST32_N
, 4, void_ftype_v8hi_int_int_int
, vst32_n_insn
, TARGET_SIMD_SET
)
192 DEF_BUILTIN (VINTI
, 1, void_ftype_int
, vinti_insn
, TARGET_SIMD_SET
)
194 /* END SIMD marker.
*/
195 DEF_BUILTIN (SIMD_END
, 0, void_ftype_void
, nothing
, 0)
197 /* ARCv2 SIMD instructions that use
/clobber the accumulator reg.
*/
198 DEF_BUILTIN (QMACH
, 2, long_ftype_v4hi_v4hi
, qmach
, TARGET_PLUS_QMACW
)
199 DEF_BUILTIN (QMACHU
, 2, long_ftype_v4hi_v4hi
, qmachu
, TARGET_PLUS_QMACW
)
200 DEF_BUILTIN (QMPYH
, 2, long_ftype_v4hi_v4hi
, qmpyh
, TARGET_PLUS_QMACW
)
201 DEF_BUILTIN (QMPYHU
, 2, long_ftype_v4hi_v4hi
, qmpyhu
, TARGET_PLUS_QMACW
)
203 DEF_BUILTIN (DMACH
, 2, int_ftype_v2hi_v2hi
, dmach
, TARGET_PLUS_DMPY
)
204 DEF_BUILTIN (DMACHU
, 2, int_ftype_v2hi_v2hi
, dmachu
, TARGET_PLUS_DMPY
)
205 DEF_BUILTIN (DMPYH
, 2, int_ftype_v2hi_v2hi
, dmpyh
, TARGET_PLUS_DMPY
)
206 DEF_BUILTIN (DMPYHU
, 2, int_ftype_v2hi_v2hi
, dmpyhu
, TARGET_PLUS_DMPY
)
208 DEF_BUILTIN (DMACWH
, 2, long_ftype_v2si_v2hi
, dmacwh
, TARGET_PLUS_QMACW
)
209 DEF_BUILTIN (DMACWHU
, 2, long_ftype_v2si_v2hi
, dmacwhu
, TARGET_PLUS_QMACW
)
211 DEF_BUILTIN (VMAC2H
, 2, v2si_ftype_v2hi_v2hi
, vmac2h
, TARGET_PLUS_MACD
)
212 DEF_BUILTIN (VMAC2HU
, 2, v2si_ftype_v2hi_v2hi
, vmac2hu
, TARGET_PLUS_MACD
)
213 DEF_BUILTIN (VMPY2H
, 2, v2si_ftype_v2hi_v2hi
, vmpy2h
, TARGET_PLUS_MACD
)
214 DEF_BUILTIN (VMPY2HU
, 2, v2si_ftype_v2hi_v2hi
, vmpy2hu
, TARGET_PLUS_MACD
)
216 /* Combined add
/sub HS SIMD instructions.
*/
217 DEF_BUILTIN (VADDSUB2H
, 2, v2hi_ftype_v2hi_v2hi
, addsubv2hi3
, TARGET_PLUS_DMPY
)
218 DEF_BUILTIN (VSUBADD2H
, 2, v2hi_ftype_v2hi_v2hi
, subaddv2hi3
, TARGET_PLUS_DMPY
)
219 DEF_BUILTIN (VADDSUB
, 2, v2si_ftype_v2si_v2si
, addsubv2si3
, TARGET_PLUS_QMACW
)
220 DEF_BUILTIN (VSUBADD
, 2, v2si_ftype_v2si_v2si
, subaddv2si3
, TARGET_PLUS_QMACW
)
221 DEF_BUILTIN (VADDSUB4H
, 2, v4hi_ftype_v4hi_v4hi
, addsubv4hi3
, TARGET_PLUS_QMACW
)
222 DEF_BUILTIN (VSUBADD4H
, 2, v4hi_ftype_v4hi_v4hi
, subaddv4hi3
, TARGET_PLUS_QMACW
)