1 ; Options for the Synopsys DesignWare ARC port of the compiler
3 ; Copyright (C) 2005-2017 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
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13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ; License for more details.
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18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
25 Target Report RejectNegative Mask(BIG_ENDIAN)
26 Compile code for big endian mode.
29 Target Report RejectNegative InverseMask(BIG_ENDIAN)
30 Compile code for little endian mode. This is the default.
33 Target Report RejectNegative Mask(NO_COND_EXEC)
34 Disable ARCompact specific pass to generate conditional execution instructions.
38 Generate ARCompact 32-bit code for ARC600 processor.
46 Generate ARCompact 32-bit code for ARC601 processor.
50 Generate ARCompact 32-bit code for ARC700 processor.
57 Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option)
58 -mmpy-option=MPY Compile ARCv2 code with a multiplier design option.
61 Name(arc_mpy) Type(int)
64 Enum(arc_mpy) String(0) Value(0)
67 Enum(arc_mpy) String(none) Value(0) Canonical
70 Enum(arc_mpy) String(1) Value(1)
73 Enum(arc_mpy) String(w) Value(1) Canonical
76 Enum(arc_mpy) String(2) Value(2)
79 Enum(arc_mpy) String(mpy) Value(2)
82 Enum(arc_mpy) String(wlh1) Value(2) Canonical
85 Enum(arc_mpy) String(3) Value(3)
88 Enum(arc_mpy) String(wlh2) Value(3) Canonical
91 Enum(arc_mpy) String(4) Value(4)
94 Enum(arc_mpy) String(wlh3) Value(4) Canonical
97 Enum(arc_mpy) String(5) Value(5)
100 Enum(arc_mpy) String(wlh4) Value(5) Canonical
103 Enum(arc_mpy) String(6) Value(6)
106 Enum(arc_mpy) String(wlh5) Value(6) Canonical
109 Enum(arc_mpy) String(7) Value(7)
112 Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical
115 Enum(arc_mpy) String(8) Value(8)
118 Enum(arc_mpy) String(plus_macd) Value(8) Canonical
121 Enum(arc_mpy) String(9) Value(9)
124 Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical
127 Target Report Mask(DIVREM)
128 Enable DIV-REM instructions for ARCv2.
131 Target Report Mask(CODE_DENSITY)
132 Enable code density instructions for ARCv2.
135 Target Report Mask(MIXED_CODE_SET)
136 Tweak register allocation to help 16-bit instruction generation.
137 ; originally this was:
138 ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
139 ; but we do that without -mmixed-code, too, it's just a different instruction
140 ; count / size tradeoff.
142 ; We use an explict definition for the negative form because that is the
143 ; actually interesting option, and we want that to have its own comment.
145 Target Report RejectNegative Mask(VOLATILE_CACHE_SET)
146 Use ordinarily cached memory accesses for volatile references.
149 Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET)
150 Enable cache bypass for volatile references.
153 Target Report Mask(BARREL_SHIFTER)
154 Generate instructions supported by barrel shifter.
157 Target Report Mask(NORM_SET)
158 Generate norm instruction.
161 Target Report Mask(SWAP_SET)
162 Generate swap instruction.
165 Target Report Mask(MUL64_SET)
166 Generate mul64 and mulu64 instructions.
169 Target Report Mask(NOMPY_SET) Warn(%qs is deprecated)
170 Do not generate mpy instructions for ARC700.
173 Target Report Mask(EA_SET)
174 Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported.
177 Target Report Mask(0)
178 Dummy flag. This is the default unless FPX switches are provided explicitly.
181 Target Report Mask(LONG_CALLS_SET)
182 Generate call insns as register indirect calls.
185 Target Report Mask(NO_BRCC_SET)
186 Do no generate BRcc instructions in arc_reorg.
189 Target Report InverseMask(NO_SDATA_SET)
190 Generate sdata references. This is the default, unless you compile for PIC.
193 Target Report Mask(NO_MILLICODE_THUNK_SET)
194 Do not generate millicode thunks (needed only with -Os).
197 Target Report Mask(SPFP_COMPACT_SET)
198 FPX: Generate Single Precision FPX (compact) instructions.
201 Target Report Mask(SPFP_COMPACT_SET) MaskExists
202 FPX: Generate Single Precision FPX (compact) instructions.
205 Target Report Mask(SPFP_FAST_SET)
206 FPX: Generate Single Precision FPX (fast) instructions.
209 Target Report Mask(ARGONAUT_SET)
210 FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
213 Target Report Mask(DPFP_COMPACT_SET)
214 FPX: Generate Double Precision FPX (compact) instructions.
217 Target Report Mask(DPFP_COMPACT_SET) MaskExists
218 FPX: Generate Double Precision FPX (compact) instructions.
221 Target Report Mask(DPFP_FAST_SET)
222 FPX: Generate Double Precision FPX (fast) instructions.
225 Target Report Mask(DPFP_DISABLE_LRSR)
226 Disable LR and SR instructions from using FPX extension aux registers.
229 Target Report Mask(SIMD_SET)
230 Enable generation of ARC SIMD instructions via target-specific builtins.
233 Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE)
234 -mcpu=CPU Compile code for ARC variant CPU.
237 Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1)
238 size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os.
241 Target Report PchIgnore Var(TARGET_DUMPISIZE)
242 Annotate assembler instructions with estimated addresses.
245 Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1)
246 Cost to assume for a multiply instruction, with 4 being equal to a normal insn.
249 Target RejectNegative Var(arc_tune, TUNE_ARC600)
253 Target RejectNegative Var(arc_tune, TUNE_ARC600)
257 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD)
258 Tune for ARC700 R4.2 Cpu with standard multiplier block.
261 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
262 Tune for ARC700 R4.2 Cpu with XMAC block.
265 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
266 Tune for ARC700 R4.2 Cpu with XMAC block.
269 Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC)
270 Tune for ARC700 R4.2 Cpu with XMAC block.
273 Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT)
274 Enable the use of indexed loads.
277 Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT)
278 Enable the use of pre/post modify with register displacement.
281 Target Report Mask(MULMAC_32BY16_SET)
282 Generate 32x16 multiply and mac instructions.
284 ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
285 ; alas, basic-block.h is not included in options.c .
286 munalign-prob-threshold=
287 Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2)
288 Set probability threshold for unaligning branches.
291 Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
292 Don't use less than 25 bit addressing range for calls.
295 Target Var(TARGET_ANNOTATE_ALIGN)
296 Explain what alignment considerations lead to the decision to make an insn short or long.
299 Target Var(TARGET_ALIGN_CALL)
300 Do alignment optimizations for call instructions.
303 Target Var(TARGET_Rcq)
304 Enable Rcq constraint handling - most short code generation depends on this.
307 Target Var(TARGET_Rcw)
308 Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
311 Target Var(TARGET_EARLY_CBRANCHSI)
312 Enable pre-reload use of cbranchsi pattern.
315 Target Var(TARGET_BBIT_PEEPHOLE)
316 Enable bbit peephole2.
319 Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
320 Use pc-relative switch case tables - this enables case table shortening.
323 Target Var(TARGET_COMPACT_CASESI)
324 Enable compact casesi pattern.
327 Target Var(TARGET_Q_CLASS)
328 Enable 'q' instruction alternatives.
331 Target Warn(%qs is deprecated)
332 Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
335 ; Flags used by the assembler, but for which we define preprocessor
336 ; macro symbols as well.
338 Target Report Warn(%qs is deprecated)
339 Enable variable polynomial CRC extension.
342 Target Report Warn(%qs is deprecated)
343 Enable DSP 3.1 Pack A extensions.
346 Target Report Warn(%qs is deprecated)
347 Enable dual viterbi butterfly extension.
350 Target Report Undocumented Warn(%qs is deprecated)
353 Target Report Undocumented Warn(%qs is deprecated)
356 Target Report RejectNegative Warn(%qs is deprecated)
357 Enable Dual and Single Operand Instructions for Telephony.
361 Enable XY Memory extension (DSP version 3).
363 ; ARC700 4.10 extension instructions
366 Enable Locked Load/Store Conditional extension.
370 Enable swap byte ordering extension instruction.
373 Target Report Warn(%qs is deprecated)
374 Enable 64-bit Time-Stamp Counter extension instruction.
378 Pass -EB option through to linker.
382 Pass -EL option through to linker.
386 Pass -marclinux option through to linker.
390 Pass -marclinux_prof option through to linker.
392 ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra.
393 ;Target InverseMask(NO_LRA)
394 ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464.
395 ; so don't enable by default.
401 Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE)
402 Don't indicate any priority with TARGET_REGISTER_PRIORITY.
404 mlra-priority-compact
405 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT)
406 Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
408 mlra-priority-noncompact
409 Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT)
410 Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY.
412 ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS
418 Target RejectNegative Joined
421 Target Report Mask(ATOMIC)
422 Enable atomic instructions.
425 Target Report Mask(LL64)
426 Enable double load/store instructions for ARC HS.
429 Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build)
430 Specify the name of the target floating point configuration.
433 Name(arc_fpu) Type(int)
436 Enum(arc_fpu) String(fpus) Value(FPU_FPUS)
439 Enum(arc_fpu) String(fpud) Value(FPU_FPUD)
442 Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA)
445 Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV)
448 Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA)
451 Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL)
454 Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV)
457 Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV)
460 Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA)
463 Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA)
466 Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL)
469 Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL)
472 Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT)
473 Specify thread pointer register number.
476 Target RejectNegative Var(arc_tp_regno,-1)
479 Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT)
480 Enable use of NPS400 bit operations.
483 Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT)
484 Enable use of NPS400 xld/xst extension.
487 Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT)
488 Enable unaligned word and halfword accesses to packed data.
491 Target RejectNegative Joined Var(arc_deferred_options) Defer
492 Specifies the registers that the processor saves on an interrupt entry and exit.
495 Target RejectNegative Joined Var(arc_deferred_options) Defer
496 Specifies the number of registers replicated in second register bank on entry to fast interrupt.