1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
52 [; TLS relocation specifiers
57 (UNSPEC_GOTNTPOFF 504)
58 (UNSPEC_INDNTPOFF 505)
62 (UNSPEC_TLSLDM_NTPOFF 511)
67 ;; UNSPEC_VOLATILE usage
76 ;; Processor type. This attribute must exactly match the processor_type
77 ;; enumeration in s390.h.
79 (define_attr "cpu" "g5,g6,z900"
80 (const (symbol_ref "s390_cpu")))
82 ;; Define an insn type attribute. This is used in function unit delay
85 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
86 cs,vs,store,imul,idiv,
87 branch,jsr,fsimpd,fsimps,
88 floadd,floads,fstored, fstores,
89 fmuld,fmuls,fdivd,fdivs,
90 ftoi,itof,fsqrtd,fsqrts,
92 (const_string "integer"))
94 ;; Operand type. Used to default length attribute values
96 (define_attr "op_type"
97 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
100 ;; Insn are devide in two classes:
101 ;; agen: Insn using agen
102 ;; reg: Insn not using agen
104 (define_attr "atype" "agen,reg"
105 (cond [ (eq_attr "op_type" "E") (const_string "reg")
106 (eq_attr "op_type" "RR") (const_string "reg")
107 (eq_attr "op_type" "RX") (const_string "agen")
108 (eq_attr "op_type" "RI") (const_string "reg")
109 (eq_attr "op_type" "RRE") (const_string "reg")
110 (eq_attr "op_type" "RS") (const_string "agen")
111 (eq_attr "op_type" "RSI") (const_string "agen")
112 (eq_attr "op_type" "S") (const_string "agen")
113 (eq_attr "op_type" "SI") (const_string "agen")
114 (eq_attr "op_type" "SS") (const_string "agen")
115 (eq_attr "op_type" "SSE") (const_string "agen")
116 (eq_attr "op_type" "RXE") (const_string "agen")
117 (eq_attr "op_type" "RSE") (const_string "agen")
118 (eq_attr "op_type" "RIL") (const_string "agen")]
119 (const_string "reg")))
121 ;; Generic pipeline function unit.
123 (define_function_unit "integer" 1 0
124 (eq_attr "type" "none") 0 0)
126 (define_function_unit "integer" 1 0
127 (eq_attr "type" "integer") 1 1)
129 (define_function_unit "integer" 1 0
130 (eq_attr "type" "fsimpd") 1 1)
132 (define_function_unit "integer" 1 0
133 (eq_attr "type" "fsimps") 1 1)
135 (define_function_unit "integer" 1 0
136 (eq_attr "type" "load") 1 1)
138 (define_function_unit "integer" 1 0
139 (eq_attr "type" "floadd") 1 1)
141 (define_function_unit "integer" 1 0
142 (eq_attr "type" "floads") 1 1)
144 (define_function_unit "integer" 1 0
145 (eq_attr "type" "la") 1 1)
147 (define_function_unit "integer" 1 0
148 (eq_attr "type" "larl") 1 1)
150 (define_function_unit "integer" 1 0
151 (eq_attr "type" "lr") 1 1)
153 (define_function_unit "integer" 1 0
154 (eq_attr "type" "branch") 1 1)
156 (define_function_unit "integer" 1 0
157 (eq_attr "type" "store") 1 1)
159 (define_function_unit "integer" 1 0
160 (eq_attr "type" "fstored") 1 1)
162 (define_function_unit "integer" 1 0
163 (eq_attr "type" "fstores") 1 1)
165 (define_function_unit "integer" 1 0
166 (eq_attr "type" "lm") 2 2)
168 (define_function_unit "integer" 1 0
169 (eq_attr "type" "stm") 2 2)
171 (define_function_unit "integer" 1 0
172 (eq_attr "type" "cs") 5 5)
174 (define_function_unit "integer" 1 0
175 (eq_attr "type" "vs") 30 30)
177 (define_function_unit "integer" 1 0
178 (eq_attr "type" "jsr") 5 5)
180 (define_function_unit "integer" 1 0
181 (eq_attr "type" "imul") 7 7)
183 (define_function_unit "integer" 1 0
184 (eq_attr "type" "fmuld") 6 6)
186 (define_function_unit "integer" 1 0
187 (eq_attr "type" "fmuls") 6 6)
189 (define_function_unit "integer" 1 0
190 (eq_attr "type" "idiv") 33 33)
192 (define_function_unit "integer" 1 0
193 (eq_attr "type" "fdivd") 33 33)
195 (define_function_unit "integer" 1 0
196 (eq_attr "type" "fdivs") 33 33)
198 (define_function_unit "integer" 1 0
199 (eq_attr "type" "fsqrtd") 30 30)
201 (define_function_unit "integer" 1 0
202 (eq_attr "type" "fsqrts") 30 30)
204 (define_function_unit "integer" 1 0
205 (eq_attr "type" "ftoi") 2 2)
207 (define_function_unit "integer" 1 0
208 (eq_attr "type" "itof") 2 2)
210 (define_function_unit "integer" 1 0
211 (eq_attr "type" "o2") 2 2)
213 (define_function_unit "integer" 1 0
214 (eq_attr "type" "o3") 3 3)
216 (define_function_unit "integer" 1 0
217 (eq_attr "type" "other") 5 5)
219 ;; Pipeline description for z900
225 (define_attr "length" ""
226 (cond [ (eq_attr "op_type" "E") (const_int 2)
227 (eq_attr "op_type" "RR") (const_int 2)
228 (eq_attr "op_type" "RX") (const_int 4)
229 (eq_attr "op_type" "RI") (const_int 4)
230 (eq_attr "op_type" "RRE") (const_int 4)
231 (eq_attr "op_type" "RS") (const_int 4)
232 (eq_attr "op_type" "RSI") (const_int 4)
233 (eq_attr "op_type" "S") (const_int 4)
234 (eq_attr "op_type" "SI") (const_int 4)
235 (eq_attr "op_type" "SS") (const_int 6)
236 (eq_attr "op_type" "SSE") (const_int 6)
237 (eq_attr "op_type" "RXE") (const_int 6)
238 (eq_attr "op_type" "RSE") (const_int 6)
239 (eq_attr "op_type" "RIL") (const_int 6)]
242 ;; Define attributes for `asm' insns.
244 (define_asm_attributes [(set_attr "type" "other")
245 (set_attr "op_type" "NN")])
251 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
252 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
253 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
254 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
255 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
258 ; CCZ1 -> CCA/CCU/CCS/CCT
261 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
262 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
266 ;;- Compare instructions.
269 (define_expand "cmpdi"
271 (compare:CC (match_operand:DI 0 "register_operand" "")
272 (match_operand:DI 1 "general_operand" "")))]
276 s390_compare_op0 = operands[0];
277 s390_compare_op1 = operands[1];
281 (define_expand "cmpsi"
283 (compare:CC (match_operand:SI 0 "register_operand" "")
284 (match_operand:SI 1 "general_operand" "")))]
288 s390_compare_op0 = operands[0];
289 s390_compare_op1 = operands[1];
293 (define_expand "cmpdf"
295 (compare:CC (match_operand:DF 0 "register_operand" "")
296 (match_operand:DF 1 "general_operand" "")))]
300 s390_compare_op0 = operands[0];
301 s390_compare_op1 = operands[1];
305 (define_expand "cmpsf"
307 (compare:CC (match_operand:SF 0 "register_operand" "")
308 (match_operand:SF 1 "general_operand" "")))]
312 s390_compare_op0 = operands[0];
313 s390_compare_op1 = operands[1];
318 ; Test-under-Mask (zero_extract) instructions
320 (define_insn "*tmdi_ext"
322 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
323 (match_operand:DI 1 "const_int_operand" "n")
324 (match_operand:DI 2 "const_int_operand" "n"))
326 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
327 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
328 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
329 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
330 == INTVAL (operands[2]) >> 4"
333 int part = INTVAL (operands[2]) >> 4;
334 int block = (1 << INTVAL (operands[1])) - 1;
335 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
337 operands[2] = GEN_INT (block << shift);
341 case 0: return \"tmhh\\t%0,%x2\";
342 case 1: return \"tmhl\\t%0,%x2\";
343 case 2: return \"tmlh\\t%0,%x2\";
344 case 3: return \"tmll\\t%0,%x2\";
348 [(set_attr "op_type" "RI")])
350 (define_insn "*tmsi_ext"
352 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
353 (match_operand:SI 1 "const_int_operand" "n")
354 (match_operand:SI 2 "const_int_operand" "n"))
356 "s390_match_ccmode(insn, CCTmode)
357 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
358 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
359 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
360 == INTVAL (operands[2]) >> 4"
363 int part = INTVAL (operands[2]) >> 4;
364 int block = (1 << INTVAL (operands[1])) - 1;
365 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
367 operands[2] = GEN_INT (block << shift);
371 case 0: return \"tmh\\t%0,%x2\";
372 case 1: return \"tml\\t%0,%x2\";
376 [(set_attr "op_type" "RI")])
378 (define_insn "*tmqi_ext"
380 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
381 (match_operand:SI 1 "const_int_operand" "n")
382 (match_operand:SI 2 "const_int_operand" "n"))
384 "s390_match_ccmode(insn, CCTmode)
385 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
386 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
389 int block = (1 << INTVAL (operands[1])) - 1;
390 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
392 operands[2] = GEN_INT (block << shift);
393 return \"tm\\t%0,%b2\";
395 [(set_attr "op_type" "SI")])
397 ; Test-under-Mask instructions
399 (define_insn "*tmdi_mem"
401 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
402 (match_operand:DI 1 "immediate_operand" "n"))
403 (match_operand:DI 2 "immediate_operand" "n")))]
405 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
406 && s390_single_qi (operands[1], DImode, 0) >= 0"
409 int part = s390_single_qi (operands[1], DImode, 0);
410 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
412 operands[0] = gen_rtx_MEM (QImode,
413 plus_constant (XEXP (operands[0], 0), part));
414 return \"tm\\t%0,%b1\";
416 [(set_attr "op_type" "SI")])
418 (define_insn "*tmsi_mem"
420 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
421 (match_operand:SI 1 "immediate_operand" "n"))
422 (match_operand:SI 2 "immediate_operand" "n")))]
423 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
424 && s390_single_qi (operands[1], SImode, 0) >= 0"
427 int part = s390_single_qi (operands[1], SImode, 0);
428 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
430 operands[0] = gen_rtx_MEM (QImode,
431 plus_constant (XEXP (operands[0], 0), part));
432 return \"tm\\t%0,%b1\";
434 [(set_attr "op_type" "SI")])
436 (define_insn "*tmhi_mem"
438 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
439 (match_operand:SI 1 "immediate_operand" "n"))
440 (match_operand:SI 2 "immediate_operand" "n")))]
441 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
442 && s390_single_qi (operands[1], HImode, 0) >= 0"
445 int part = s390_single_qi (operands[1], HImode, 0);
446 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
448 operands[0] = gen_rtx_MEM (QImode,
449 plus_constant (XEXP (operands[0], 0), part));
450 return \"tm\\t%0,%b1\";
452 [(set_attr "op_type" "SI")])
454 (define_insn "*tmqi_mem"
456 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
457 (match_operand:SI 1 "immediate_operand" "n"))
458 (match_operand:SI 2 "immediate_operand" "n")))]
459 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
461 [(set_attr "op_type" "SI")])
463 (define_insn "*tmdi_reg"
465 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
466 (match_operand:DI 1 "immediate_operand" "n"))
467 (match_operand:DI 2 "immediate_operand" "n")))]
469 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
470 && s390_single_hi (operands[1], DImode, 0) >= 0"
473 int part = s390_single_hi (operands[1], DImode, 0);
474 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
478 case 0: return \"tmhh\\t%0,%x1\";
479 case 1: return \"tmhl\\t%0,%x1\";
480 case 2: return \"tmlh\\t%0,%x1\";
481 case 3: return \"tmll\\t%0,%x1\";
485 [(set_attr "op_type" "RI")])
487 (define_insn "*tmsi_reg"
489 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
490 (match_operand:SI 1 "immediate_operand" "n"))
491 (match_operand:SI 2 "immediate_operand" "n")))]
492 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
493 && s390_single_hi (operands[1], SImode, 0) >= 0"
496 int part = s390_single_hi (operands[1], SImode, 0);
497 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
501 case 0: return \"tmh\\t%0,%x1\";
502 case 1: return \"tml\\t%0,%x1\";
506 [(set_attr "op_type" "RI")])
508 (define_insn "*tmhi_full"
510 (compare (match_operand:HI 0 "register_operand" "d")
511 (match_operand:HI 1 "immediate_operand" "n")))]
512 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
514 [(set_attr "op_type" "RX")])
516 (define_insn "*tmqi_full"
518 (compare (match_operand:QI 0 "register_operand" "d")
519 (match_operand:QI 1 "immediate_operand" "n")))]
520 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
522 [(set_attr "op_type" "RI")])
525 ; Load-and-Test instructions
527 (define_insn "*tstdi_sign"
529 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
530 (const_int 32)) (const_int 32))
531 (match_operand:DI 1 "const0_operand" "")))
532 (set (match_operand:DI 2 "register_operand" "=d")
533 (sign_extend:DI (match_dup 0)))]
534 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
536 [(set_attr "op_type" "RRE")])
538 (define_insn "*tstdi"
540 (compare (match_operand:DI 0 "register_operand" "d")
541 (match_operand:DI 1 "const0_operand" "")))
542 (set (match_operand:DI 2 "register_operand" "=d")
544 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
546 [(set_attr "op_type" "RRE")])
548 (define_insn "*tstdi_cconly"
550 (compare (match_operand:DI 0 "register_operand" "d")
551 (match_operand:DI 1 "const0_operand" "")))]
552 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
554 [(set_attr "op_type" "RRE")])
556 (define_insn "*tstdi_cconly_31"
558 (compare (match_operand:DI 0 "register_operand" "d")
559 (match_operand:DI 1 "const0_operand" "")))]
560 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
562 [(set_attr "op_type" "RS")
563 (set_attr "atype" "reg")])
566 (define_insn "*tstsi"
568 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
569 (match_operand:SI 1 "const0_operand" "")))
570 (set (match_operand:SI 2 "register_operand" "=d,d")
572 "s390_match_ccmode(insn, CCSmode)"
576 [(set_attr "op_type" "RR,RS")])
578 (define_insn "*tstsi_cconly"
580 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
581 (match_operand:SI 1 "const0_operand" "")))
582 (clobber (match_scratch:SI 2 "=X,d"))]
583 "s390_match_ccmode(insn, CCSmode)"
587 [(set_attr "op_type" "RR,RS")])
589 (define_insn "*tstsi_cconly2"
591 (compare (match_operand:SI 0 "register_operand" "d")
592 (match_operand:SI 1 "const0_operand" "")))]
593 "s390_match_ccmode(insn, CCSmode)"
595 [(set_attr "op_type" "RR")])
597 (define_insn "*tsthiCCT"
599 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
600 (match_operand:HI 1 "const0_operand" "")))
601 (set (match_operand:HI 2 "register_operand" "=d,0")
603 "s390_match_ccmode(insn, CCTmode)"
607 [(set_attr "op_type" "RS,RI")])
609 (define_insn "*tsthiCCT_cconly"
611 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
612 (match_operand:HI 1 "const0_operand" "")))
613 (clobber (match_scratch:HI 2 "=d,X"))]
614 "s390_match_ccmode(insn, CCTmode)"
618 [(set_attr "op_type" "RS,RI")])
620 (define_insn "*tsthi"
622 (compare (match_operand:HI 0 "s_operand" "Q")
623 (match_operand:HI 1 "const0_operand" "")))
624 (set (match_operand:HI 2 "register_operand" "=d")
626 "s390_match_ccmode(insn, CCSmode)"
628 [(set_attr "op_type" "RS")])
630 (define_insn "*tsthi_cconly"
632 (compare (match_operand:HI 0 "s_operand" "Q")
633 (match_operand:HI 1 "const0_operand" "")))
634 (clobber (match_scratch:HI 2 "=d"))]
635 "s390_match_ccmode(insn, CCSmode)"
637 [(set_attr "op_type" "RS")])
639 (define_insn "*tstqiCCT"
641 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
642 (match_operand:QI 1 "const0_operand" "")))
643 (set (match_operand:QI 2 "register_operand" "=d,0")
645 "s390_match_ccmode(insn, CCTmode)"
649 [(set_attr "op_type" "RS,RI")])
651 (define_insn "*tstqiCCT_cconly"
653 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
654 (match_operand:QI 1 "const0_operand" "")))]
655 "s390_match_ccmode(insn, CCTmode)"
659 [(set_attr "op_type" "SI,RI")])
661 (define_insn "*tstqi"
663 (compare (match_operand:QI 0 "s_operand" "Q")
664 (match_operand:QI 1 "const0_operand" "")))
665 (set (match_operand:QI 2 "register_operand" "=d")
667 "s390_match_ccmode(insn, CCSmode)"
669 [(set_attr "op_type" "RS")])
671 (define_insn "*tstqi_cconly"
673 (compare (match_operand:QI 0 "s_operand" "Q")
674 (match_operand:QI 1 "const0_operand" "")))
675 (clobber (match_scratch:QI 2 "=d"))]
676 "s390_match_ccmode(insn, CCSmode)"
678 [(set_attr "op_type" "RS")])
680 ; Compare (signed) instructions
682 (define_insn "*cmpdi_ccs_sign"
684 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
685 (match_operand:DI 0 "register_operand" "d,d")))]
686 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
690 [(set_attr "op_type" "RRE,RXE")])
692 (define_insn "*cmpdi_ccs"
694 (compare (match_operand:DI 0 "register_operand" "d,d,d")
695 (match_operand:DI 1 "general_operand" "d,K,m")))]
696 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
701 [(set_attr "op_type" "RRE,RI,RXE")])
703 (define_insn "*cmpsi_ccs_sign"
705 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
706 (match_operand:SI 0 "register_operand" "d")))]
707 "s390_match_ccmode(insn, CCSRmode)"
709 [(set_attr "op_type" "RX")])
711 (define_insn "*cmpsi_ccs"
713 (compare (match_operand:SI 0 "register_operand" "d,d,d")
714 (match_operand:SI 1 "general_operand" "d,K,m")))]
715 "s390_match_ccmode(insn, CCSmode)"
720 [(set_attr "op_type" "RR,RI,RX")])
723 ; Compare (unsigned) instructions
725 (define_insn "*cmpdi_ccu_zero"
727 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
728 (match_operand:DI 0 "register_operand" "d,d")))]
729 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
733 [(set_attr "op_type" "RRE,RXE")])
735 (define_insn "*cmpdi_ccu"
737 (compare (match_operand:DI 0 "register_operand" "d,d")
738 (match_operand:DI 1 "general_operand" "d,m")))]
739 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
743 [(set_attr "op_type" "RRE,RXE")])
745 (define_insn "*cmpsi_ccu"
747 (compare (match_operand:SI 0 "register_operand" "d,d")
748 (match_operand:SI 1 "general_operand" "d,m")))]
749 "s390_match_ccmode(insn, CCUmode)"
753 [(set_attr "op_type" "RR,RX")])
755 (define_insn "*cmphi_ccu"
757 (compare (match_operand:HI 0 "register_operand" "d")
758 (match_operand:HI 1 "s_imm_operand" "Q")))]
759 "s390_match_ccmode(insn, CCUmode)"
761 [(set_attr "op_type" "RS")])
763 (define_insn "*cmpqi_ccu"
765 (compare (match_operand:QI 0 "register_operand" "d")
766 (match_operand:QI 1 "s_imm_operand" "Q")))]
767 "s390_match_ccmode(insn, CCUmode)"
769 [(set_attr "op_type" "RS")])
773 (compare (match_operand:QI 0 "memory_operand" "Q")
774 (match_operand:QI 1 "immediate_operand" "n")))]
775 "s390_match_ccmode (insn, CCUmode)"
777 [(set_attr "op_type" "SI")])
779 (define_insn "*cmpdi_ccu_mem"
781 (compare (match_operand:DI 0 "s_operand" "Q")
782 (match_operand:DI 1 "s_imm_operand" "Q")))]
783 "s390_match_ccmode(insn, CCUmode)"
784 "clc\\t%O0(8,%R0),%1"
785 [(set_attr "op_type" "SS")])
787 (define_insn "*cmpsi_ccu_mem"
789 (compare (match_operand:SI 0 "s_operand" "Q")
790 (match_operand:SI 1 "s_imm_operand" "Q")))]
791 "s390_match_ccmode(insn, CCUmode)"
792 "clc\\t%O0(4,%R0),%1"
793 [(set_attr "op_type" "SS")])
795 (define_insn "*cmphi_ccu_mem"
797 (compare (match_operand:HI 0 "s_operand" "Q")
798 (match_operand:HI 1 "s_imm_operand" "Q")))]
799 "s390_match_ccmode(insn, CCUmode)"
800 "clc\\t%O0(2,%R0),%1"
801 [(set_attr "op_type" "SS")])
803 (define_insn "*cmpqi_ccu_mem"
805 (compare (match_operand:QI 0 "s_operand" "Q")
806 (match_operand:QI 1 "s_imm_operand" "Q")))]
807 "s390_match_ccmode(insn, CCUmode)"
808 "clc\\t%O0(1,%R0),%1"
809 [(set_attr "op_type" "SS")])
814 (define_insn "*cmpdf_ccs_0"
816 (compare (match_operand:DF 0 "register_operand" "f")
817 (match_operand:DF 1 "const0_operand" "")))]
818 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
820 [(set_attr "op_type" "RRE")
821 (set_attr "type" "fsimpd")])
823 (define_insn "*cmpdf_ccs_0_ibm"
825 (compare (match_operand:DF 0 "register_operand" "f")
826 (match_operand:DF 1 "const0_operand" "")))]
827 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
829 [(set_attr "op_type" "RR")
830 (set_attr "type" "fsimpd")])
832 (define_insn "*cmpdf_ccs"
834 (compare (match_operand:DF 0 "register_operand" "f,f")
835 (match_operand:DF 1 "general_operand" "f,m")))]
836 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
840 [(set_attr "op_type" "RRE,RXE")
841 (set_attr "type" "fsimpd")])
843 (define_insn "*cmpdf_ccs_ibm"
845 (compare (match_operand:DF 0 "register_operand" "f,f")
846 (match_operand:DF 1 "general_operand" "f,m")))]
847 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
851 [(set_attr "op_type" "RR,RX")
852 (set_attr "type" "fsimpd")])
857 (define_insn "*cmpsf_ccs_0"
859 (compare (match_operand:SF 0 "register_operand" "f")
860 (match_operand:SF 1 "const0_operand" "")))]
861 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
863 [(set_attr "op_type" "RRE")
864 (set_attr "type" "fsimps")])
866 (define_insn "*cmpsf_ccs_0_ibm"
868 (compare (match_operand:SF 0 "register_operand" "f")
869 (match_operand:SF 1 "const0_operand" "")))]
870 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
872 [(set_attr "op_type" "RR")
873 (set_attr "type" "fsimps")])
875 (define_insn "*cmpsf_ccs"
877 (compare (match_operand:SF 0 "register_operand" "f,f")
878 (match_operand:SF 1 "general_operand" "f,m")))]
879 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
883 [(set_attr "op_type" "RRE,RXE")
884 (set_attr "type" "fsimps")])
886 (define_insn "*cmpsf_ccs"
888 (compare (match_operand:SF 0 "register_operand" "f,f")
889 (match_operand:SF 1 "general_operand" "f,m")))]
890 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
894 [(set_attr "op_type" "RR,RX")
895 (set_attr "type" "fsimps")])
899 ;;- Move instructions.
903 ; movti instruction pattern(s).
907 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
908 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
915 mvc\\t%O0(16,%R0),%1"
916 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")])
919 [(set (match_operand:TI 0 "nonimmediate_operand" "")
920 (match_operand:TI 1 "general_operand" ""))]
921 "TARGET_64BIT && reload_completed
922 && !s_operand (operands[0], VOIDmode)
923 && !s_operand (operands[1], VOIDmode)
924 && (register_operand (operands[0], VOIDmode)
925 || register_operand (operands[1], VOIDmode))
926 && (!register_operand (operands[0], VOIDmode)
927 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
929 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
931 [(set (match_dup 2) (match_dup 4))
932 (set (match_dup 3) (match_dup 5))]
935 if (!register_operand (operands[0], VOIDmode)
936 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
939 operands[2] = operand_subword (operands[0], 0, 0, TImode);
940 operands[3] = operand_subword (operands[0], 1, 0, TImode);
941 operands[4] = operand_subword (operands[1], 0, 0, TImode);
942 operands[5] = operand_subword (operands[1], 1, 0, TImode);
946 operands[2] = operand_subword (operands[0], 1, 0, TImode);
947 operands[3] = operand_subword (operands[0], 0, 0, TImode);
948 operands[4] = operand_subword (operands[1], 1, 0, TImode);
949 operands[5] = operand_subword (operands[1], 0, 0, TImode);
954 [(set (match_operand:TI 0 "register_operand" "")
955 (match_operand:TI 1 "memory_operand" ""))]
956 "TARGET_64BIT && reload_completed
957 && !s_operand (operands[1], VOIDmode)"
958 [(set (match_dup 0) (match_dup 1))]
961 rtx addr = operand_subword (operands[0], 1, 0, TImode);
962 s390_load_address (addr, XEXP (operands[1], 0));
963 operands[1] = replace_equiv_address (operands[1], addr);
967 ; movdi instruction pattern(s).
970 (define_expand "movdi"
971 [(set (match_operand:DI 0 "general_operand" "")
972 (match_operand:DI 1 "general_operand" ""))]
976 /* Handle symbolic constants. */
977 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
978 emit_symbolic_move (operands);
980 /* During and after reload, we need to force constants
981 to the literal pool ourselves, if necessary. */
982 if ((reload_in_progress || reload_completed)
983 && CONSTANT_P (operands[1])
984 && (!legitimate_reload_constant_p (operands[1])
985 || FP_REG_P (operands[0])))
986 operands[1] = force_const_mem (DImode, operands[1]);
989 (define_insn "*movdi_lhi"
990 [(set (match_operand:DI 0 "register_operand" "=d")
991 (match_operand:DI 1 "immediate_operand" "K"))]
993 && GET_CODE (operands[1]) == CONST_INT
994 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
995 && !FP_REG_P (operands[0])"
997 [(set_attr "op_type" "RI")])
999 (define_insn "*movdi_lli"
1000 [(set (match_operand:DI 0 "register_operand" "=d")
1001 (match_operand:DI 1 "immediate_operand" "n"))]
1002 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
1003 && !FP_REG_P (operands[0])"
1006 int part = s390_single_hi (operands[1], DImode, 0);
1007 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
1011 case 0: return \"llihh\\t%0,%x1\";
1012 case 1: return \"llihl\\t%0,%x1\";
1013 case 2: return \"llilh\\t%0,%x1\";
1014 case 3: return \"llill\\t%0,%x1\";
1018 [(set_attr "op_type" "RI")])
1020 (define_insn "*movdi_larl"
1021 [(set (match_operand:DI 0 "register_operand" "=d")
1022 (match_operand:DI 1 "larl_operand" "X"))]
1024 && !FP_REG_P (operands[0])"
1026 [(set_attr "op_type" "RIL")
1027 (set_attr "type" "larl")])
1029 (define_insn "*movdi_64"
1030 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1031 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1040 mvc\\t%O0(8,%R0),%1"
1041 [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
1042 (set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")])
1044 (define_insn "*movdi_31"
1045 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
1046 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
1056 mvc\\t%O0(8,%R0),%1"
1057 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
1058 (set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")])
1061 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1062 (match_operand:DI 1 "general_operand" ""))]
1063 "!TARGET_64BIT && reload_completed
1064 && !FP_REG_P (operands[0])
1065 && !FP_REG_P (operands[1])
1066 && !s_operand (operands[0], VOIDmode)
1067 && !s_operand (operands[1], VOIDmode)
1068 && (register_operand (operands[0], VOIDmode)
1069 || register_operand (operands[1], VOIDmode))
1070 && (!register_operand (operands[0], VOIDmode)
1071 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1073 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
1075 [(set (match_dup 2) (match_dup 4))
1076 (set (match_dup 3) (match_dup 5))]
1079 if (!register_operand (operands[0], VOIDmode)
1080 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
1083 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1084 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1085 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1086 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1090 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1091 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1092 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1093 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1098 [(set (match_operand:DI 0 "register_operand" "")
1099 (match_operand:DI 1 "memory_operand" ""))]
1100 "!TARGET_64BIT && reload_completed
1101 && !FP_REG_P (operands[0])
1102 && !FP_REG_P (operands[1])
1103 && !s_operand (operands[1], VOIDmode)"
1104 [(set (match_dup 0) (match_dup 1))]
1107 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1108 s390_load_address (addr, XEXP (operands[1], 0));
1109 operands[1] = replace_equiv_address (operands[1], addr);
1113 [(set (match_operand:DI 0 "register_operand" "")
1114 (mem:DI (match_operand 1 "address_operand" "")))]
1116 && !FP_REG_P (operands[0])
1117 && GET_CODE (operands[1]) == SYMBOL_REF
1118 && CONSTANT_POOL_ADDRESS_P (operands[1])
1119 && get_pool_mode (operands[1]) == DImode
1120 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1121 [(set (match_dup 0) (match_dup 2))]
1122 "operands[2] = get_pool_constant (operands[1]);")
1125 ; movsi instruction pattern(s).
1128 (define_expand "movsi"
1129 [(set (match_operand:SI 0 "general_operand" "")
1130 (match_operand:SI 1 "general_operand" ""))]
1134 /* Handle symbolic constants. */
1135 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1136 emit_symbolic_move (operands);
1138 /* expr.c tries to load an effective address using
1139 force_reg. This fails because we don't have a
1140 generic load_address pattern. Convert the move
1141 to a proper arithmetic operation instead, unless
1142 it is guaranteed to be OK. */
1143 if (GET_CODE (operands[1]) == PLUS
1144 && !legitimate_la_operand_p (operands[1]))
1146 operands[1] = force_operand (operands[1], operands[0]);
1147 if (operands[1] == operands[0])
1151 /* During and after reload, we need to force constants
1152 to the literal pool ourselves, if necessary. */
1153 if ((reload_in_progress || reload_completed)
1154 && CONSTANT_P (operands[1])
1155 && (!legitimate_reload_constant_p (operands[1])
1156 || FP_REG_P (operands[0])))
1157 operands[1] = force_const_mem (SImode, operands[1]);
1160 (define_insn "*movsi_lhi"
1161 [(set (match_operand:SI 0 "register_operand" "=d")
1162 (match_operand:SI 1 "immediate_operand" "K"))]
1163 "GET_CODE (operands[1]) == CONST_INT
1164 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1165 && !FP_REG_P (operands[0])"
1167 [(set_attr "op_type" "RI")])
1169 (define_insn "*movsi_lli"
1170 [(set (match_operand:SI 0 "register_operand" "=d")
1171 (match_operand:SI 1 "immediate_operand" "n"))]
1172 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1173 && !FP_REG_P (operands[0])"
1176 int part = s390_single_hi (operands[1], SImode, 0);
1177 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1181 case 0: return \"llilh\\t%0,%x1\";
1182 case 1: return \"llill\\t%0,%x1\";
1186 [(set_attr "op_type" "RI")])
1188 (define_insn "*movsi"
1189 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1190 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1199 mvc\\t%O0(4,%R0),%1"
1200 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1201 (set_attr "type" "lr,load,store,floads,floads,fstores,cs")])
1204 [(set (match_operand:SI 0 "register_operand" "")
1205 (mem:SI (match_operand 1 "address_operand" "")))]
1206 "!FP_REG_P (operands[0])
1207 && GET_CODE (operands[1]) == SYMBOL_REF
1208 && CONSTANT_POOL_ADDRESS_P (operands[1])
1209 && get_pool_mode (operands[1]) == SImode
1210 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1211 [(set (match_dup 0) (match_dup 2))]
1212 "operands[2] = get_pool_constant (operands[1]);")
1215 ; movhi instruction pattern(s).
1218 (define_insn "movhi"
1219 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1220 (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1227 mvc\\t%O0(2,%R0),%1"
1228 [(set_attr "op_type" "RR,RI,RX,RX,SS")])
1231 [(set (match_operand:HI 0 "register_operand" "")
1232 (mem:HI (match_operand 1 "address_operand" "")))]
1233 "GET_CODE (operands[1]) == SYMBOL_REF
1234 && CONSTANT_POOL_ADDRESS_P (operands[1])
1235 && get_pool_mode (operands[1]) == HImode
1236 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1237 [(set (match_dup 0) (match_dup 2))]
1238 "operands[2] = get_pool_constant (operands[1]);")
1241 ; movqi instruction pattern(s).
1244 (define_insn "movqi_64"
1245 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1246 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1254 mvc\\t%O0(1,%R0),%1"
1255 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1256 (set_attr "type" "lr,*,*,store,store,cs")])
1258 (define_insn "movqi"
1259 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1260 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1268 mvc\\t%O0(1,%R0),%1"
1269 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")])
1272 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1273 (mem:QI (match_operand 1 "address_operand" "")))]
1274 "GET_CODE (operands[1]) == SYMBOL_REF
1275 && CONSTANT_POOL_ADDRESS_P (operands[1])
1276 && get_pool_mode (operands[1]) == QImode
1277 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1278 [(set (match_dup 0) (match_dup 2))]
1279 "operands[2] = get_pool_constant (operands[1]);")
1282 ; movstrictqi instruction pattern(s).
1285 (define_insn "*movstrictqi"
1286 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1287 (match_operand:QI 1 "memory_operand" "m"))]
1290 [(set_attr "op_type" "RX")])
1293 ; movstricthi instruction pattern(s).
1296 (define_insn "*movstricthi"
1297 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1298 (match_operand:HI 1 "s_imm_operand" "Q"))
1299 (clobber (reg:CC 33))]
1302 [(set_attr "op_type" "RS")])
1306 ; movstrictsi instruction pattern(s).
1309 (define_insn "movstrictsi"
1310 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1311 (match_operand:SI 1 "general_operand" "d,m"))]
1316 [(set_attr "op_type" "RR,RS")
1317 (set_attr "type" "lr,load")])
1321 ; movdf instruction pattern(s).
1324 (define_expand "movdf"
1325 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1326 (match_operand:DF 1 "general_operand" ""))]
1330 /* During and after reload, we need to force constants
1331 to the literal pool ourselves, if necessary. */
1332 if ((reload_in_progress || reload_completed)
1333 && CONSTANT_P (operands[1]))
1334 operands[1] = force_const_mem (DFmode, operands[1]);
1337 (define_insn "*movdf_64"
1338 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1339 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1348 mvc\\t%O0(8,%R0),%1"
1349 [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
1350 (set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")])
1352 (define_insn "*movdf_31"
1353 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1354 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1364 mvc\\t%O0(8,%R0),%1"
1365 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1366 (set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")])
1369 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1370 (match_operand:DF 1 "general_operand" ""))]
1371 "!TARGET_64BIT && reload_completed
1372 && !FP_REG_P (operands[0])
1373 && !FP_REG_P (operands[1])
1374 && !s_operand (operands[0], VOIDmode)
1375 && !s_operand (operands[1], VOIDmode)
1376 && (register_operand (operands[0], VOIDmode)
1377 || register_operand (operands[1], VOIDmode))
1378 && (!register_operand (operands[0], VOIDmode)
1379 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1381 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1383 [(set (match_dup 2) (match_dup 4))
1384 (set (match_dup 3) (match_dup 5))]
1387 if (!register_operand (operands[0], VOIDmode)
1388 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1391 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1392 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1393 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1394 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1398 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1399 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1400 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1401 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1406 [(set (match_operand:DF 0 "register_operand" "")
1407 (match_operand:DF 1 "memory_operand" ""))]
1408 "!TARGET_64BIT && reload_completed
1409 && !FP_REG_P (operands[0])
1410 && !FP_REG_P (operands[1])
1411 && !s_operand (operands[1], VOIDmode)"
1412 [(set (match_dup 0) (match_dup 1))]
1415 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1416 s390_load_address (addr, XEXP (operands[1], 0));
1417 operands[1] = replace_equiv_address (operands[1], addr);
1421 ; movsf instruction pattern(s).
1424 (define_expand "movsf"
1425 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1426 (match_operand:SF 1 "general_operand" ""))]
1430 /* During and after reload, we need to force constants
1431 to the literal pool ourselves, if necessary. */
1432 if ((reload_in_progress || reload_completed)
1433 && CONSTANT_P (operands[1]))
1434 operands[1] = force_const_mem (SFmode, operands[1]);
1437 (define_insn "*movsf"
1438 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1439 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1448 mvc\\t%O0(4,%R0),%1"
1449 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1450 (set_attr "type" "floads,floads,fstores,lr,load,store,cs")])
1453 ; load_multiple pattern(s).
1456 (define_expand "load_multiple"
1457 [(match_par_dup 3 [(set (match_operand 0 "" "")
1458 (match_operand 1 "" ""))
1459 (use (match_operand 2 "" ""))])]
1468 /* Support only loading a constant number of fixed-point registers from
1469 memory and only bother with this if more than two */
1470 if (GET_CODE (operands[2]) != CONST_INT
1471 || INTVAL (operands[2]) < 2
1472 || INTVAL (operands[2]) > 16
1473 || GET_CODE (operands[1]) != MEM
1474 || GET_CODE (operands[0]) != REG
1475 || REGNO (operands[0]) >= 16)
1478 count = INTVAL (operands[2]);
1479 regno = REGNO (operands[0]);
1481 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1484 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1486 from = XEXP (operands[1], 0);
1489 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1490 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1491 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1493 from = XEXP (XEXP (operands[1], 0), 0);
1494 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1499 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1504 from = force_reg (Pmode, XEXP (operands[1], 0));
1508 for (i = 0; i < count; i++)
1509 XVECEXP (operands[3], 0, i)
1510 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1511 change_address (operands[1], Pmode,
1512 plus_constant (from,
1513 off + i * UNITS_PER_WORD)));
1516 (define_insn "*load_multiple_di"
1517 [(match_parallel 0 "load_multiple_operation"
1518 [(set (match_operand:DI 1 "register_operand" "=r")
1519 (match_operand:DI 2 "s_operand" "Q"))])]
1523 int words = XVECLEN (operands[0], 0);
1525 if (XVECLEN (operands[0], 0) == 1)
1526 return \"lg\\t%1,0(%2)\";
1528 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1529 return \"lmg\\t%1,%0,%2\";
1531 [(set_attr "op_type" "RXE")
1532 (set_attr "type" "lm")])
1534 (define_insn "*load_multiple_si"
1535 [(match_parallel 0 "load_multiple_operation"
1536 [(set (match_operand:SI 1 "register_operand" "=r")
1537 (match_operand:SI 2 "s_operand" "Q"))])]
1541 int words = XVECLEN (operands[0], 0);
1543 if (XVECLEN (operands[0], 0) == 1)
1544 return \"l\\t%1,0(%2)\";
1546 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1547 return \"lm\\t%1,%0,%2\";
1549 [(set_attr "op_type" "RXE")
1550 (set_attr "type" "lm")])
1553 ; store multiple pattern(s).
1556 (define_expand "store_multiple"
1557 [(match_par_dup 3 [(set (match_operand 0 "" "")
1558 (match_operand 1 "" ""))
1559 (use (match_operand 2 "" ""))])]
1568 /* Support only storing a constant number of fixed-point registers to
1569 memory and only bother with this if more than two. */
1570 if (GET_CODE (operands[2]) != CONST_INT
1571 || INTVAL (operands[2]) < 2
1572 || INTVAL (operands[2]) > 16
1573 || GET_CODE (operands[0]) != MEM
1574 || GET_CODE (operands[1]) != REG
1575 || REGNO (operands[1]) >= 16)
1578 count = INTVAL (operands[2]);
1579 regno = REGNO (operands[1]);
1581 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1585 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1587 to = XEXP (operands[0], 0);
1590 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1591 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1592 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1594 to = XEXP (XEXP (operands[0], 0), 0);
1595 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1600 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1605 to = force_reg (Pmode, XEXP (operands[0], 0));
1609 for (i = 0; i < count; i++)
1610 XVECEXP (operands[3], 0, i)
1611 = gen_rtx_SET (VOIDmode,
1612 change_address (operands[0], Pmode,
1614 off + i * UNITS_PER_WORD)),
1615 gen_rtx_REG (Pmode, regno + i));
1618 (define_insn "*store_multiple_di"
1619 [(match_parallel 0 "store_multiple_operation"
1620 [(set (match_operand:DI 1 "s_operand" "=Q")
1621 (match_operand:DI 2 "register_operand" "r"))])]
1625 int words = XVECLEN (operands[0], 0);
1627 if (XVECLEN (operands[0], 0) == 1)
1628 return \"stg\\t%1,0(%2)\";
1630 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1631 return \"stmg\\t%2,%0,%1\";
1633 [(set_attr "op_type" "RXE")
1634 (set_attr "type" "stm")])
1637 (define_insn "*store_multiple_si"
1638 [(match_parallel 0 "store_multiple_operation"
1639 [(set (match_operand:SI 1 "s_operand" "=Q")
1640 (match_operand:SI 2 "register_operand" "r"))])]
1644 int words = XVECLEN (operands[0], 0);
1646 if (XVECLEN (operands[0], 0) == 1)
1647 return \"st\\t%1,0(%2)\";
1649 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1650 return \"stm\\t%2,%0,%1\";
1652 [(set_attr "op_type" "RXE")
1653 (set_attr "type" "stm")])
1656 ;; String instructions.
1660 ; movstrM instruction pattern(s).
1663 (define_expand "movstrdi"
1664 [(set (match_operand:BLK 0 "memory_operand" "")
1665 (match_operand:BLK 1 "memory_operand" ""))
1666 (use (match_operand:DI 2 "general_operand" ""))
1667 (match_operand 3 "" "")]
1669 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1671 (define_expand "movstrsi"
1672 [(set (match_operand:BLK 0 "memory_operand" "")
1673 (match_operand:BLK 1 "memory_operand" ""))
1674 (use (match_operand:SI 2 "general_operand" ""))
1675 (match_operand 3 "" "")]
1677 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1679 ; Move a block that is up to 256 bytes in length.
1680 ; The block length is taken as (operands[2] % 256) + 1.
1682 (define_insn "movstr_short_64"
1683 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1684 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1685 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1686 (clobber (match_scratch:DI 3 "=X,&a"))]
1690 switch (which_alternative)
1693 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1696 output_asm_insn (\"bras\\t%3,.+10\", operands);
1697 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1698 return \"ex\\t%2,0(%3)\";
1704 [(set_attr "op_type" "SS,NN")
1705 (set_attr "type" "cs,cs")
1706 (set_attr "atype" "*,agen")
1707 (set_attr "length" "*,14")])
1709 (define_insn "movstr_short_31"
1710 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1711 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1712 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1713 (clobber (match_scratch:SI 3 "=X,&a"))]
1717 switch (which_alternative)
1720 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1723 output_asm_insn (\"bras\\t%3,.+10\", operands);
1724 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1725 return \"ex\\t%2,0(%3)\";
1731 [(set_attr "op_type" "SS,NN")
1732 (set_attr "type" "cs,cs")
1733 (set_attr "atype" "*,agen")
1734 (set_attr "length" "*,14")])
1736 ; Move a block of arbitrary length.
1738 (define_insn "movstr_long_64"
1739 [(set (match_operand:TI 0 "register_operand" "=d")
1740 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1741 (lshiftrt:TI (match_dup 2) (const_int 64)))
1743 (set (match_operand:TI 1 "register_operand" "=d")
1744 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1745 (lshiftrt:TI (match_dup 3) (const_int 64)))
1747 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1748 (mem:BLK (subreg:DI (match_dup 3) 0)))
1749 (clobber (reg:CC 33))]
1751 "mvcle\\t%0,%1,0\;jo\\t.-4"
1752 [(set_attr "op_type" "NN")
1753 (set_attr "type" "vs")
1754 (set_attr "length" "8")])
1756 (define_insn "movstr_long_31"
1757 [(set (match_operand:DI 0 "register_operand" "=d")
1758 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1759 (lshiftrt:DI (match_dup 2) (const_int 32)))
1761 (set (match_operand:DI 1 "register_operand" "=d")
1762 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1763 (lshiftrt:DI (match_dup 3) (const_int 32)))
1765 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1766 (mem:BLK (subreg:SI (match_dup 3) 0)))
1767 (clobber (reg:CC 33))]
1769 "mvcle\\t%0,%1,0\;jo\\t.-4"
1770 [(set_attr "op_type" "NN")
1771 (set_attr "type" "vs")
1772 (set_attr "length" "8")])
1775 ; clrstrM instruction pattern(s).
1778 (define_expand "clrstrdi"
1779 [(set (match_operand:BLK 0 "memory_operand" "")
1781 (use (match_operand:DI 1 "general_operand" ""))
1782 (match_operand 2 "" "")]
1784 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1786 (define_expand "clrstrsi"
1787 [(set (match_operand:BLK 0 "memory_operand" "")
1789 (use (match_operand:SI 1 "general_operand" ""))
1790 (match_operand 2 "" "")]
1792 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1794 ; Clear a block that is up to 256 bytes in length.
1795 ; The block length is taken as (operands[2] % 256) + 1.
1797 (define_insn "clrstr_short_64"
1798 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1800 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1801 (clobber (match_scratch:DI 2 "=X,&a"))
1802 (clobber (reg:CC 33))]
1806 switch (which_alternative)
1809 return \"xc\\t%O0(%b1+1,%R0),%0\";
1812 output_asm_insn (\"bras\\t%2,.+10\", operands);
1813 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1814 return \"ex\\t%1,0(%2)\";
1820 [(set_attr "op_type" "SS,NN")
1821 (set_attr "type" "cs,cs")
1822 (set_attr "atype" "*,agen")
1823 (set_attr "length" "*,14")])
1825 (define_insn "clrstr_short_31"
1826 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1828 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1829 (clobber (match_scratch:SI 2 "=X,&a"))
1830 (clobber (reg:CC 33))]
1834 switch (which_alternative)
1837 return \"xc\\t%O0(%b1+1,%R0),%0\";
1840 output_asm_insn (\"bras\\t%2,.+10\", operands);
1841 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1842 return \"ex\\t%1,0(%2)\";
1848 [(set_attr "op_type" "SS,NN")
1849 (set_attr "type" "cs,cs")
1850 (set_attr "atype" "*,agen")
1851 (set_attr "length" "*,14")])
1853 ; Clear a block of arbitrary length.
1855 (define_insn "clrstr_long_64"
1856 [(set (match_operand:TI 0 "register_operand" "=d")
1857 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1858 (lshiftrt:TI (match_dup 2) (const_int 64)))
1860 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1862 (use (match_operand:TI 1 "register_operand" "d"))
1863 (clobber (reg:CC 33))]
1865 "mvcle\\t%0,%1,0\;jo\\t.-4"
1866 [(set_attr "op_type" "NN")
1867 (set_attr "type" "vs")
1868 (set_attr "length" "8")])
1870 (define_insn "clrstr_long_31"
1871 [(set (match_operand:DI 0 "register_operand" "=d")
1872 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1873 (lshiftrt:DI (match_dup 2) (const_int 32)))
1875 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1877 (use (match_operand:DI 1 "register_operand" "d"))
1878 (clobber (reg:CC 33))]
1880 "mvcle\\t%0,%1,0\;jo\\t.-4"
1881 [(set_attr "op_type" "NN")
1882 (set_attr "type" "vs")
1883 (set_attr "length" "8")])
1886 ; cmpstrM instruction pattern(s).
1889 (define_expand "cmpstrdi"
1890 [(set (match_operand:DI 0 "register_operand" "")
1891 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1892 (match_operand:BLK 2 "memory_operand" "") ) )
1893 (use (match_operand:DI 3 "general_operand" ""))
1894 (use (match_operand:DI 4 "" ""))]
1896 "s390_expand_cmpstr (operands[0], operands[1],
1897 operands[2], operands[3]); DONE;")
1899 (define_expand "cmpstrsi"
1900 [(set (match_operand:SI 0 "register_operand" "")
1901 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1902 (match_operand:BLK 2 "memory_operand" "") ) )
1903 (use (match_operand:SI 3 "general_operand" ""))
1904 (use (match_operand:SI 4 "" ""))]
1906 "s390_expand_cmpstr (operands[0], operands[1],
1907 operands[2], operands[3]); DONE;")
1909 ; Compare a block that is up to 256 bytes in length.
1910 ; The block length is taken as (operands[2] % 256) + 1.
1912 (define_insn "cmpstr_short_64"
1914 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1915 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1916 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1917 (clobber (match_scratch:DI 3 "=X,&a"))]
1921 switch (which_alternative)
1924 return \"clc\\t%O0(%b2+1,%R0),%1\";
1927 output_asm_insn (\"bras\\t%3,.+10\", operands);
1928 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1929 return \"ex\\t%2,0(%3)\";
1935 [(set_attr "op_type" "SS,NN")
1936 (set_attr "type" "cs,cs")
1937 (set_attr "atype" "*,agen")
1938 (set_attr "length" "*,14")])
1940 (define_insn "cmpstr_short_31"
1942 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1943 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1944 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1945 (clobber (match_scratch:SI 3 "=X,&a"))]
1949 switch (which_alternative)
1952 return \"clc\\t%O0(%b2+1,%R0),%1\";
1955 output_asm_insn (\"bras\\t%3,.+10\", operands);
1956 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1957 return \"ex\\t%2,0(%3)\";
1963 [(set_attr "op_type" "SS,NN")
1964 (set_attr "type" "cs,cs")
1965 (set_attr "atype" "*,agen")
1966 (set_attr "length" "*,14")])
1968 ; Compare a block of arbitrary length.
1970 (define_insn "cmpstr_long_64"
1971 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1972 (clobber (match_operand:TI 1 "register_operand" "=d"))
1974 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1975 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1977 (use (match_dup 3))]
1980 [(set_attr "op_type" "RR")
1981 (set_attr "type" "vs")])
1983 (define_insn "cmpstr_long_31"
1984 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1985 (clobber (match_operand:DI 1 "register_operand" "=d"))
1987 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1988 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1990 (use (match_dup 3))]
1993 [(set_attr "op_type" "RR")
1994 (set_attr "type" "vs")])
1996 ; Convert condition code to integer in range (-1, 0, 1)
1998 (define_insn "cmpint_si"
1999 [(set (match_operand:SI 0 "register_operand" "=d")
2000 (compare:SI (reg:CCS 33) (const_int 0)))]
2004 output_asm_insn (\"lhi\\t%0,1\", operands);
2005 output_asm_insn (\"jh\\t.+12\", operands);
2006 output_asm_insn (\"jl\\t.+6\", operands);
2007 output_asm_insn (\"sr\\t%0,%0\", operands);
2008 return \"lcr\\t%0,%0\";
2010 [(set_attr "op_type" "NN")
2011 (set_attr "length" "16")
2012 (set_attr "type" "other")])
2014 (define_insn "cmpint_di"
2015 [(set (match_operand:DI 0 "register_operand" "=d")
2016 (compare:DI (reg:CCS 33) (const_int 0)))]
2020 output_asm_insn (\"lghi\\t%0,1\", operands);
2021 output_asm_insn (\"jh\\t.+12\", operands);
2022 output_asm_insn (\"jl\\t.+6\", operands);
2023 output_asm_insn (\"sgr\\t%0,%0\", operands);
2024 return \"lcgr\\t%0,%0\";
2026 [(set_attr "op_type" "NN")
2027 (set_attr "length" "22")
2028 (set_attr "type" "other")])
2032 ;;- Conversion instructions.
2035 (define_insn "*sethighqisi"
2036 [(set (match_operand:SI 0 "register_operand" "=d")
2037 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
2038 (clobber (reg:CC 33))]
2041 [(set_attr "op_type" "RS")])
2043 (define_insn "*sethighhisi"
2044 [(set (match_operand:SI 0 "register_operand" "=d")
2045 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
2046 (clobber (reg:CC 33))]
2049 [(set_attr "op_type" "RS")])
2051 (define_insn "*sethighqidi_64"
2052 [(set (match_operand:DI 0 "register_operand" "=d")
2053 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2054 (clobber (reg:CC 33))]
2057 [(set_attr "op_type" "RSE")])
2059 (define_insn "*sethighqidi_31"
2060 [(set (match_operand:DI 0 "register_operand" "=d")
2061 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
2062 (clobber (reg:CC 33))]
2065 [(set_attr "op_type" "RS")])
2067 (define_insn_and_split "*extractqi"
2068 [(set (match_operand:SI 0 "register_operand" "=d")
2069 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2070 (match_operand 2 "const_int_operand" "n")
2072 (clobber (reg:CC 33))]
2074 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2076 "&& reload_completed"
2078 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2079 (clobber (reg:CC 33))])
2080 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2083 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2084 operands[1] = change_address (operands[1], QImode, 0);
2086 [(set_attr "type" "o2")
2087 (set_attr "atype" "agen")])
2089 (define_insn_and_split "*extracthi"
2090 [(set (match_operand:SI 0 "register_operand" "=d")
2091 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2092 (match_operand 2 "const_int_operand" "n")
2094 (clobber (reg:CC 33))]
2096 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2098 "&& reload_completed"
2100 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2101 (clobber (reg:CC 33))])
2102 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2105 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2106 operands[1] = change_address (operands[1], HImode, 0);
2108 [(set_attr "type" "o2")
2109 (set_attr "atype" "agen")])
2112 ; extendsidi2 instruction pattern(s).
2115 (define_expand "extendsidi2"
2116 [(set (match_operand:DI 0 "register_operand" "")
2117 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2123 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2124 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2125 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2126 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2132 (define_insn "*extendsidi2"
2133 [(set (match_operand:DI 0 "register_operand" "=d,d")
2134 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2139 [(set_attr "op_type" "RRE,RXE")])
2142 ; extendhidi2 instruction pattern(s).
2145 (define_expand "extendhidi2"
2146 [(set (match_operand:DI 0 "register_operand" "")
2147 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2153 rtx tmp = gen_reg_rtx (SImode);
2154 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2155 emit_insn (gen_extendsidi2 (operands[0], tmp));
2160 operands[1] = gen_lowpart (DImode, operands[1]);
2161 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2162 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2168 (define_insn "*extendhidi2"
2169 [(set (match_operand:DI 0 "register_operand" "=d")
2170 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2173 [(set_attr "op_type" "RXE")])
2176 ; extendqidi2 instruction pattern(s).
2179 (define_expand "extendqidi2"
2180 [(set (match_operand:DI 0 "register_operand" "")
2181 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2187 rtx tmp = gen_reg_rtx (SImode);
2188 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2189 emit_insn (gen_extendsidi2 (operands[0], tmp));
2194 operands[1] = gen_lowpart (DImode, operands[1]);
2195 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2196 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2203 [(set (match_operand:DI 0 "register_operand" "")
2204 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2205 "TARGET_64BIT && !reload_completed"
2207 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2208 (clobber (reg:CC 33))])
2210 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2211 (clobber (reg:CC 33))])]
2215 ; extendhisi2 instruction pattern(s).
2218 (define_expand "extendhisi2"
2219 [(set (match_operand:SI 0 "register_operand" "")
2220 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2224 operands[1] = gen_lowpart (SImode, operands[1]);
2225 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2226 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2231 (define_insn "*extendhisi2"
2232 [(set (match_operand:SI 0 "register_operand" "=d")
2233 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2236 [(set_attr "op_type" "RX")])
2239 ; extendqisi2 instruction pattern(s).
2242 (define_expand "extendqisi2"
2243 [(set (match_operand:SI 0 "register_operand" "")
2244 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2248 operands[1] = gen_lowpart (SImode, operands[1]);
2249 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2250 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2256 [(set (match_operand:SI 0 "register_operand" "")
2257 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2260 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2261 (clobber (reg:CC 33))])
2263 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2264 (clobber (reg:CC 33))])]
2268 ; extendqihi2 instruction pattern(s).
2273 ; zero_extendsidi2 instruction pattern(s).
2276 (define_expand "zero_extendsidi2"
2277 [(set (match_operand:DI 0 "register_operand" "")
2278 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2284 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2285 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2286 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2292 (define_insn "*zero_extendsidi2"
2293 [(set (match_operand:DI 0 "register_operand" "=d,d")
2294 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2299 [(set_attr "op_type" "RRE,RXE")])
2302 ; zero_extendhidi2 instruction pattern(s).
2305 (define_expand "zero_extendhidi2"
2306 [(set (match_operand:DI 0 "register_operand" "")
2307 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2313 rtx tmp = gen_reg_rtx (SImode);
2314 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2315 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2320 operands[1] = gen_lowpart (DImode, operands[1]);
2321 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2322 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2328 (define_insn "*zero_extendhidi2"
2329 [(set (match_operand:DI 0 "register_operand" "=d")
2330 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2333 [(set_attr "op_type" "RXE")])
2336 ; zero_extendqidi2 instruction pattern(s)
2339 (define_expand "zero_extendqidi2"
2340 [(set (match_operand:DI 0 "register_operand" "")
2341 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2347 rtx tmp = gen_reg_rtx (SImode);
2348 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2349 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2354 operands[1] = gen_lowpart (DImode, operands[1]);
2355 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2356 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2362 (define_insn "*zero_extendqidi2"
2363 [(set (match_operand:DI 0 "register_operand" "=d")
2364 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2367 [(set_attr "op_type" "RXE")])
2370 ; zero_extendhisi2 instruction pattern(s).
2373 (define_expand "zero_extendhisi2"
2374 [(set (match_operand:SI 0 "register_operand" "")
2375 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2379 operands[1] = gen_lowpart (SImode, operands[1]);
2380 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2385 (define_insn "*zero_extendhisi2_64"
2386 [(set (match_operand:SI 0 "register_operand" "=d")
2387 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2390 [(set_attr "op_type" "RXE")])
2392 (define_insn_and_split "*zero_extendhisi2_31"
2393 [(set (match_operand:SI 0 "register_operand" "=&d")
2394 (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
2395 (clobber (reg:CC 33))]
2398 "&& reload_completed"
2399 [(set (match_dup 0) (const_int 0))
2401 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2402 (clobber (reg:CC 33))])]
2403 "operands[2] = gen_lowpart (HImode, operands[0]);"
2404 [(set_attr "type" "o2")
2405 (set_attr "atype" "agen")])
2408 ; zero_extendqisi2 instruction pattern(s).
2411 (define_expand "zero_extendqisi2"
2412 [(set (match_operand:SI 0 "register_operand" "")
2413 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2417 operands[1] = gen_lowpart (SImode, operands[1]);
2418 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2423 (define_insn "*zero_extendqisi2_64"
2424 [(set (match_operand:SI 0 "register_operand" "=d")
2425 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2428 [(set_attr "op_type" "RXE")])
2430 (define_insn_and_split "*zero_extendqisi2_31"
2431 [(set (match_operand:SI 0 "register_operand" "=&d")
2432 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2435 "&& reload_completed"
2436 [(set (match_dup 0) (const_int 0))
2437 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2438 "operands[2] = gen_lowpart (QImode, operands[0]);"
2439 [(set_attr "type" "o2")
2440 (set_attr "atype" "agen")])
2443 ; zero_extendqihi2 instruction pattern(s).
2446 (define_expand "zero_extendqihi2"
2447 [(set (match_operand:HI 0 "register_operand" "")
2448 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2452 operands[1] = gen_lowpart (HImode, operands[1]);
2453 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2458 (define_insn "*zero_extendqihi2_64"
2459 [(set (match_operand:HI 0 "register_operand" "=d")
2460 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2463 [(set_attr "op_type" "RXE")])
2465 (define_insn_and_split "*zero_extendqihi2_31"
2466 [(set (match_operand:HI 0 "register_operand" "=&d")
2467 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2470 "&& reload_completed"
2471 [(set (match_dup 0) (const_int 0))
2472 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2473 "operands[2] = gen_lowpart (QImode, operands[0]);"
2474 [(set_attr "type" "o2")
2475 (set_attr "atype" "agen")])
2479 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2482 (define_expand "fixuns_truncdfdi2"
2483 [(set (match_operand:DI 0 "register_operand" "")
2484 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2485 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2488 rtx label1 = gen_label_rtx ();
2489 rtx label2 = gen_label_rtx ();
2490 rtx temp = gen_reg_rtx (DFmode);
2491 operands[1] = force_reg (DFmode, operands[1]);
2493 emit_insn (gen_cmpdf (operands[1],
2494 CONST_DOUBLE_FROM_REAL_VALUE (
2495 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2496 emit_jump_insn (gen_blt (label1));
2497 emit_insn (gen_subdf3 (temp, operands[1],
2498 CONST_DOUBLE_FROM_REAL_VALUE (
2499 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2500 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2503 emit_label (label1);
2504 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2505 emit_label (label2);
2509 (define_expand "fix_truncdfdi2"
2510 [(set (match_operand:DI 0 "register_operand" "")
2511 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2512 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2515 operands[1] = force_reg (DFmode, operands[1]);
2516 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2520 (define_insn "fix_truncdfdi2_ieee"
2521 [(set (match_operand:DI 0 "register_operand" "=d")
2522 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2523 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2524 (clobber (reg:CC 33))]
2525 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2527 [(set_attr "op_type" "RRE")
2528 (set_attr "type" "ftoi")])
2531 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2534 (define_expand "fixuns_truncdfsi2"
2535 [(set (match_operand:SI 0 "register_operand" "")
2536 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2537 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2540 rtx label1 = gen_label_rtx ();
2541 rtx label2 = gen_label_rtx ();
2542 rtx temp = gen_reg_rtx (DFmode);
2544 operands[1] = force_reg (DFmode,operands[1]);
2545 emit_insn (gen_cmpdf (operands[1],
2546 CONST_DOUBLE_FROM_REAL_VALUE (
2547 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2548 emit_jump_insn (gen_blt (label1));
2549 emit_insn (gen_subdf3 (temp, operands[1],
2550 CONST_DOUBLE_FROM_REAL_VALUE (
2551 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2552 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2555 emit_label (label1);
2556 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2557 emit_label (label2);
2561 (define_expand "fix_truncdfsi2"
2562 [(set (match_operand:SI 0 "register_operand" "")
2563 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2567 if (TARGET_IBM_FLOAT)
2569 /* This is the algorithm from POP chapter A.5.7.2. */
2571 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2572 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2573 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2575 operands[1] = force_reg (DFmode, operands[1]);
2576 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2577 two31r, two32, temp));
2581 operands[1] = force_reg (DFmode, operands[1]);
2582 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2588 (define_insn "fix_truncdfsi2_ieee"
2589 [(set (match_operand:SI 0 "register_operand" "=d")
2590 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2591 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2592 (clobber (reg:CC 33))]
2593 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2595 [(set_attr "op_type" "RRE")
2596 (set_attr "type" "other" )])
2598 (define_insn "fix_truncdfsi2_ibm"
2599 [(set (match_operand:SI 0 "register_operand" "=d")
2600 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2601 (use (match_operand:DI 2 "immediate_operand" "m"))
2602 (use (match_operand:DI 3 "immediate_operand" "m"))
2603 (use (match_operand:BLK 4 "memory_operand" "m"))
2604 (clobber (reg:CC 33))]
2605 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2608 output_asm_insn (\"sd\\t%1,%2\", operands);
2609 output_asm_insn (\"aw\\t%1,%3\", operands);
2610 output_asm_insn (\"std\\t%1,%4\", operands);
2611 output_asm_insn (\"xi\\t%N4,128\", operands);
2612 return \"l\\t%0,%N4\";
2614 [(set_attr "op_type" "NN")
2615 (set_attr "type" "ftoi")
2616 (set_attr "atype" "agen")
2617 (set_attr "length" "20")])
2620 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2623 (define_expand "fixuns_truncsfdi2"
2624 [(set (match_operand:DI 0 "register_operand" "")
2625 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2626 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2629 rtx label1 = gen_label_rtx ();
2630 rtx label2 = gen_label_rtx ();
2631 rtx temp = gen_reg_rtx (SFmode);
2633 operands[1] = force_reg (SFmode, operands[1]);
2634 emit_insn (gen_cmpsf (operands[1],
2635 CONST_DOUBLE_FROM_REAL_VALUE (
2636 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2637 emit_jump_insn (gen_blt (label1));
2639 emit_insn (gen_subsf3 (temp, operands[1],
2640 CONST_DOUBLE_FROM_REAL_VALUE (
2641 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2642 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2645 emit_label (label1);
2646 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2647 emit_label (label2);
2651 (define_expand "fix_truncsfdi2"
2652 [(set (match_operand:DI 0 "register_operand" "")
2653 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2654 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2657 operands[1] = force_reg (SFmode, operands[1]);
2658 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2662 (define_insn "fix_truncsfdi2_ieee"
2663 [(set (match_operand:DI 0 "register_operand" "=d")
2664 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2665 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2666 (clobber (reg:CC 33))]
2667 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2669 [(set_attr "op_type" "RRE")
2670 (set_attr "type" "ftoi")])
2673 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2676 (define_expand "fixuns_truncsfsi2"
2677 [(set (match_operand:SI 0 "register_operand" "")
2678 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2679 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2682 rtx label1 = gen_label_rtx ();
2683 rtx label2 = gen_label_rtx ();
2684 rtx temp = gen_reg_rtx (SFmode);
2686 operands[1] = force_reg (SFmode, operands[1]);
2687 emit_insn (gen_cmpsf (operands[1],
2688 CONST_DOUBLE_FROM_REAL_VALUE (
2689 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2690 emit_jump_insn (gen_blt (label1));
2691 emit_insn (gen_subsf3 (temp, operands[1],
2692 CONST_DOUBLE_FROM_REAL_VALUE (
2693 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2694 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2697 emit_label (label1);
2698 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2699 emit_label (label2);
2703 (define_expand "fix_truncsfsi2"
2704 [(set (match_operand:SI 0 "register_operand" "")
2705 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2709 if (TARGET_IBM_FLOAT)
2711 /* Convert to DFmode and then use the POP algorithm. */
2712 rtx temp = gen_reg_rtx (DFmode);
2713 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2714 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2718 operands[1] = force_reg (SFmode, operands[1]);
2719 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2725 (define_insn "fix_truncsfsi2_ieee"
2726 [(set (match_operand:SI 0 "register_operand" "=d")
2727 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2728 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2729 (clobber (reg:CC 33))]
2730 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2732 [(set_attr "op_type" "RRE")
2733 (set_attr "type" "ftoi")])
2736 ; floatdidf2 instruction pattern(s).
2739 (define_insn "floatdidf2"
2740 [(set (match_operand:DF 0 "register_operand" "=f")
2741 (float:DF (match_operand:DI 1 "register_operand" "d")))
2742 (clobber (reg:CC 33))]
2743 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2745 [(set_attr "op_type" "RRE")
2746 (set_attr "type" "itof" )])
2749 ; floatdisf2 instruction pattern(s).
2752 (define_insn "floatdisf2"
2753 [(set (match_operand:SF 0 "register_operand" "=f")
2754 (float:SF (match_operand:DI 1 "register_operand" "d")))
2755 (clobber (reg:CC 33))]
2756 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2758 [(set_attr "op_type" "RRE")
2759 (set_attr "type" "itof" )])
2762 ; floatsidf2 instruction pattern(s).
2765 (define_expand "floatsidf2"
2767 [(set (match_operand:DF 0 "register_operand" "")
2768 (float:DF (match_operand:SI 1 "register_operand" "")))
2769 (clobber (reg:CC 33))])]
2773 if (TARGET_IBM_FLOAT)
2775 /* This is the algorithm from POP chapter A.5.7.1. */
2777 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2778 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2780 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2785 (define_insn "floatsidf2_ieee"
2786 [(set (match_operand:DF 0 "register_operand" "=f")
2787 (float:DF (match_operand:SI 1 "register_operand" "d")))
2788 (clobber (reg:CC 33))]
2789 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2791 [(set_attr "op_type" "RRE")
2792 (set_attr "type" "itof" )])
2794 (define_insn "floatsidf2_ibm"
2795 [(set (match_operand:DF 0 "register_operand" "=f")
2796 (float:DF (match_operand:SI 1 "register_operand" "d")))
2797 (use (match_operand:DI 2 "immediate_operand" "m"))
2798 (use (match_operand:BLK 3 "memory_operand" "m"))
2799 (clobber (reg:CC 33))]
2800 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2803 output_asm_insn (\"st\\t%1,%N3\", operands);
2804 output_asm_insn (\"xi\\t%N3,128\", operands);
2805 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2806 output_asm_insn (\"ld\\t%0,%3\", operands);
2807 return \"sd\\t%0,%2\";
2809 [(set_attr "op_type" "NN")
2810 (set_attr "type" "other" )
2811 (set_attr "atype" "agen")
2812 (set_attr "length" "20")])
2815 ; floatsisf2 instruction pattern(s).
2818 (define_expand "floatsisf2"
2820 [(set (match_operand:SF 0 "register_operand" "")
2821 (float:SF (match_operand:SI 1 "register_operand" "")))
2822 (clobber (reg:CC 33))])]
2826 if (TARGET_IBM_FLOAT)
2828 /* Use the POP algorithm to convert to DFmode and then truncate. */
2829 rtx temp = gen_reg_rtx (DFmode);
2830 emit_insn (gen_floatsidf2 (temp, operands[1]));
2831 emit_insn (gen_truncdfsf2 (operands[0], temp));
2836 (define_insn "floatsisf2_ieee"
2837 [(set (match_operand:SF 0 "register_operand" "=f")
2838 (float:SF (match_operand:SI 1 "register_operand" "d")))
2839 (clobber (reg:CC 33))]
2840 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2842 [(set_attr "op_type" "RRE")
2843 (set_attr "type" "itof" )])
2846 ; truncdfsf2 instruction pattern(s).
2849 (define_expand "truncdfsf2"
2850 [(set (match_operand:SF 0 "register_operand" "")
2851 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2855 (define_insn "truncdfsf2_ieee"
2856 [(set (match_operand:SF 0 "register_operand" "=f")
2857 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2858 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2860 [(set_attr "op_type" "RRE")])
2862 (define_insn "truncdfsf2_ibm"
2863 [(set (match_operand:SF 0 "register_operand" "=f,f")
2864 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2865 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2869 [(set_attr "op_type" "RR,RX")
2870 (set_attr "type" "floads,floads")])
2873 ; extendsfdf2 instruction pattern(s).
2876 (define_expand "extendsfdf2"
2877 [(set (match_operand:DF 0 "register_operand" "")
2878 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2882 if (TARGET_IBM_FLOAT)
2884 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2889 (define_insn "extendsfdf2_ieee"
2890 [(set (match_operand:DF 0 "register_operand" "=f,f")
2891 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2892 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2896 [(set_attr "op_type" "RRE,RXE")
2897 (set_attr "type" "floads,floads")])
2899 (define_insn "extendsfdf2_ibm"
2900 [(set (match_operand:DF 0 "register_operand" "=f,f")
2901 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2902 (clobber (reg:CC 33))]
2903 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2905 sdr\\t%0,%0\;ler\\t%0,%1
2906 sdr\\t%0,%0\;le\\t%0,%1"
2907 [(set_attr "op_type" "NN,NN")
2908 (set_attr "atype" "reg,agen")
2909 (set_attr "length" "4,6")
2910 (set_attr "type" "o2,o2")])
2914 ;; ARITHMETRIC OPERATIONS
2916 ; arithmetric operations set the ConditionCode,
2917 ; because of unpredictable Bits in Register for Halfword and Byte
2918 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2921 ;;- Add instructions.
2925 ; adddi3 instruction pattern(s).
2928 (define_insn "*adddi3_sign"
2929 [(set (match_operand:DI 0 "register_operand" "=d,d")
2930 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2931 (match_operand:DI 1 "register_operand" "0,0")))
2932 (clobber (reg:CC 33))]
2937 [(set_attr "op_type" "RRE,RXE")])
2939 (define_insn "*adddi3_zero_cc"
2941 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2942 (match_operand:DI 1 "register_operand" "0,0"))
2944 (set (match_operand:DI 0 "register_operand" "=d,d")
2945 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2946 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2950 [(set_attr "op_type" "RRE,RXE")])
2952 (define_insn "*adddi3_zero_cconly"
2954 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2955 (match_operand:DI 1 "register_operand" "0,0"))
2957 (clobber (match_scratch:DI 0 "=d,d"))]
2958 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2962 [(set_attr "op_type" "RRE,RXE")])
2964 (define_insn "*adddi3_zero"
2965 [(set (match_operand:DI 0 "register_operand" "=d,d")
2966 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2967 (match_operand:DI 1 "register_operand" "0,0")))
2968 (clobber (reg:CC 33))]
2973 [(set_attr "op_type" "RRE,RXE")])
2975 (define_insn "*adddi3_imm_cc"
2977 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2978 (match_operand:DI 2 "const_int_operand" "K"))
2980 (set (match_operand:DI 0 "register_operand" "=d")
2981 (plus:DI (match_dup 1) (match_dup 2)))]
2983 && s390_match_ccmode (insn, CCAmode)
2984 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2986 [(set_attr "op_type" "RI")])
2988 (define_insn "*adddi3_cc"
2990 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2991 (match_operand:DI 2 "general_operand" "d,m"))
2993 (set (match_operand:DI 0 "register_operand" "=d,d")
2994 (plus:DI (match_dup 1) (match_dup 2)))]
2995 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2999 [(set_attr "op_type" "RRE,RXE")])
3001 (define_insn "*adddi3_cconly"
3003 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3004 (match_operand:DI 2 "general_operand" "d,m"))
3006 (clobber (match_scratch:DI 0 "=d,d"))]
3007 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3011 [(set_attr "op_type" "RRE,RXE")])
3013 (define_insn "*adddi3_cconly2"
3015 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3016 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3017 (clobber (match_scratch:DI 0 "=d,d"))]
3018 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3022 [(set_attr "op_type" "RRE,RXE")])
3024 (define_insn "*adddi3_64"
3025 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3026 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3027 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3028 (clobber (reg:CC 33))]
3034 [(set_attr "op_type" "RRE,RI,RXE")])
3036 (define_insn_and_split "*adddi3_31"
3037 [(set (match_operand:DI 0 "register_operand" "=&d")
3038 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3039 (match_operand:DI 2 "general_operand" "dm") ) )
3040 (clobber (reg:CC 33))]
3043 "&& reload_completed"
3045 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3046 (clobber (reg:CC 33))])
3049 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3051 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3053 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3055 (label_ref (match_dup 9))))
3057 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3058 (clobber (reg:CC 33))])
3060 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3061 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3062 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3063 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3064 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3065 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3066 operands[9] = gen_label_rtx ();"
3067 [(set_attr "op_type" "NN")
3068 (set_attr "type" "o3")])
3070 (define_expand "adddi3"
3072 [(set (match_operand:DI 0 "register_operand" "")
3073 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3074 (match_operand:DI 2 "general_operand" "")))
3075 (clobber (reg:CC 33))])]
3079 (define_insn "*la_64"
3080 [(set (match_operand:DI 0 "register_operand" "=d")
3081 (match_operand:QI 1 "address_operand" "p"))]
3084 [(set_attr "op_type" "RX")
3085 (set_attr "type" "la")])
3089 [(set (match_operand:DI 0 "register_operand" "")
3090 (match_operand:QI 1 "address_operand" ""))
3091 (clobber (reg:CC 33))])]
3093 && strict_memory_address_p (VOIDmode, operands[1])
3094 && preferred_la_operand_p (operands[1])"
3095 [(set (match_dup 0) (match_dup 1))]
3099 [(set (match_operand:DI 0 "register_operand" "")
3100 (match_operand:DI 1 "register_operand" ""))
3103 (plus:DI (match_dup 0)
3104 (match_operand:DI 2 "nonmemory_operand" "")))
3105 (clobber (reg:CC 33))])]
3107 && !reg_overlap_mentioned_p (operands[0], operands[2])
3108 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2]))
3109 && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))"
3110 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3113 (define_expand "reload_indi"
3114 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3115 (match_operand:DI 1 "s390_plus_operand" "")
3116 (match_operand:DI 2 "register_operand" "=&a")])]
3120 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3126 ; addsi3 instruction pattern(s).
3129 (define_insn "*addsi3_imm_cc"
3131 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3132 (match_operand:SI 2 "const_int_operand" "K"))
3134 (set (match_operand:SI 0 "register_operand" "=d")
3135 (plus:SI (match_dup 1) (match_dup 2)))]
3136 "s390_match_ccmode (insn, CCAmode)
3137 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3139 [(set_attr "op_type" "RI")])
3141 (define_insn "*addsi3_carry1_cc"
3143 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3144 (match_operand:SI 2 "general_operand" "d,m"))
3146 (set (match_operand:SI 0 "register_operand" "=d,d")
3147 (plus:SI (match_dup 1) (match_dup 2)))]
3148 "s390_match_ccmode (insn, CCL1mode)"
3152 [(set_attr "op_type" "RR,RX")])
3154 (define_insn "*addsi3_carry1_cconly"
3156 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3157 (match_operand:SI 2 "general_operand" "d,m"))
3159 (clobber (match_scratch:SI 0 "=d,d"))]
3160 "s390_match_ccmode (insn, CCL1mode)"
3164 [(set_attr "op_type" "RR,RX")])
3166 (define_insn "*addsi3_carry2_cc"
3168 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3169 (match_operand:SI 2 "general_operand" "d,m"))
3171 (set (match_operand:SI 0 "register_operand" "=d,d")
3172 (plus:SI (match_dup 1) (match_dup 2)))]
3173 "s390_match_ccmode (insn, CCL1mode)"
3177 [(set_attr "op_type" "RR,RX")])
3179 (define_insn "*addsi3_carry2_cconly"
3181 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3182 (match_operand:SI 2 "general_operand" "d,m"))
3184 (clobber (match_scratch:SI 0 "=d,d"))]
3185 "s390_match_ccmode (insn, CCL1mode)"
3189 [(set_attr "op_type" "RR,RX")])
3191 (define_insn "*addsi3_cc"
3193 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3194 (match_operand:SI 2 "general_operand" "d,m"))
3196 (set (match_operand:SI 0 "register_operand" "=d,d")
3197 (plus:SI (match_dup 1) (match_dup 2)))]
3198 "s390_match_ccmode (insn, CCLmode)"
3202 [(set_attr "op_type" "RR,RX")])
3204 (define_insn "*addsi3_cconly"
3206 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3207 (match_operand:SI 2 "general_operand" "d,m"))
3209 (clobber (match_scratch:SI 0 "=d,d"))]
3210 "s390_match_ccmode (insn, CCLmode)"
3214 [(set_attr "op_type" "RR,RX")])
3216 (define_insn "*addsi3_cconly2"
3218 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3219 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3220 (clobber (match_scratch:SI 0 "=d,d"))]
3221 "s390_match_ccmode(insn, CCLmode)"
3225 [(set_attr "op_type" "RR,RX")])
3227 (define_insn "*addsi3_sign"
3228 [(set (match_operand:SI 0 "register_operand" "=d")
3229 (plus:SI (match_operand:SI 1 "register_operand" "0")
3230 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3231 (clobber (reg:CC 33))]
3234 [(set_attr "op_type" "RX")])
3236 (define_insn "*addsi3_sub"
3237 [(set (match_operand:SI 0 "register_operand" "=d")
3238 (plus:SI (match_operand:SI 1 "register_operand" "0")
3239 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3240 (clobber (reg:CC 33))]
3243 [(set_attr "op_type" "RX")])
3245 (define_insn "addsi3"
3246 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3247 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3248 (match_operand:SI 2 "general_operand" "d,K,m")))
3249 (clobber (reg:CC 33))]
3255 [(set_attr "op_type" "RR,RI,RX")])
3257 (define_insn "*la_31"
3258 [(set (match_operand:SI 0 "register_operand" "=d")
3259 (match_operand:QI 1 "address_operand" "p"))]
3260 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
3262 [(set_attr "op_type" "RX")
3263 (set_attr "type" "la")])
3267 [(set (match_operand:SI 0 "register_operand" "")
3268 (match_operand:QI 1 "address_operand" ""))
3269 (clobber (reg:CC 33))])]
3271 && strict_memory_address_p (VOIDmode, operands[1])
3272 && preferred_la_operand_p (operands[1])"
3273 [(set (match_dup 0) (match_dup 1))]
3277 [(set (match_operand:SI 0 "register_operand" "")
3278 (match_operand:SI 1 "register_operand" ""))
3281 (plus:SI (match_dup 0)
3282 (match_operand:SI 2 "nonmemory_operand" "")))
3283 (clobber (reg:CC 33))])]
3285 && !reg_overlap_mentioned_p (operands[0], operands[2])
3286 && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2]))
3287 && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))"
3288 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3291 (define_insn "*la_31_and"
3292 [(set (match_operand:SI 0 "register_operand" "=d")
3293 (and:SI (match_operand:QI 1 "address_operand" "p")
3294 (const_int 2147483647)))]
3297 [(set_attr "op_type" "RX")
3298 (set_attr "type" "la")])
3300 (define_insn_and_split "*la_31_and_cc"
3301 [(set (match_operand:SI 0 "register_operand" "=d")
3302 (and:SI (match_operand:QI 1 "address_operand" "p")
3303 (const_int 2147483647)))
3304 (clobber (reg:CC 33))]
3307 "&& reload_completed"
3309 (and:SI (match_dup 1) (const_int 2147483647)))]
3311 [(set_attr "op_type" "RX")
3312 (set_attr "type" "la")])
3314 (define_insn "force_la_31"
3315 [(set (match_operand:SI 0 "register_operand" "=d")
3316 (match_operand:QI 1 "address_operand" "p"))
3317 (use (const_int 0))]
3320 [(set_attr "op_type" "RX")
3321 (set_attr "type" "la")])
3323 (define_expand "reload_insi"
3324 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3325 (match_operand:SI 1 "s390_plus_operand" "")
3326 (match_operand:SI 2 "register_operand" "=&a")])]
3330 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3336 ; adddf3 instruction pattern(s).
3339 (define_expand "adddf3"
3341 [(set (match_operand:DF 0 "register_operand" "=f,f")
3342 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3343 (match_operand:DF 2 "general_operand" "f,m")))
3344 (clobber (reg:CC 33))])]
3348 (define_insn "*adddf3"
3349 [(set (match_operand:DF 0 "register_operand" "=f,f")
3350 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3351 (match_operand:DF 2 "general_operand" "f,m")))
3352 (clobber (reg:CC 33))]
3353 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3357 [(set_attr "op_type" "RRE,RXE")
3358 (set_attr "type" "fsimpd,fsimpd")])
3360 (define_insn "*adddf3_ibm"
3361 [(set (match_operand:DF 0 "register_operand" "=f,f")
3362 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3363 (match_operand:DF 2 "general_operand" "f,m")))
3364 (clobber (reg:CC 33))]
3365 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3369 [(set_attr "op_type" "RR,RX")
3370 (set_attr "type" "fsimpd,fsimpd")])
3373 ; addsf3 instruction pattern(s).
3376 (define_expand "addsf3"
3378 [(set (match_operand:SF 0 "register_operand" "=f,f")
3379 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3380 (match_operand:SF 2 "general_operand" "f,m")))
3381 (clobber (reg:CC 33))])]
3385 (define_insn "*addsf3"
3386 [(set (match_operand:SF 0 "register_operand" "=f,f")
3387 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3388 (match_operand:SF 2 "general_operand" "f,m")))
3389 (clobber (reg:CC 33))]
3390 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3394 [(set_attr "op_type" "RRE,RXE")
3395 (set_attr "type" "fsimps,fsimps")])
3397 (define_insn "*addsf3"
3398 [(set (match_operand:SF 0 "register_operand" "=f,f")
3399 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3400 (match_operand:SF 2 "general_operand" "f,m")))
3401 (clobber (reg:CC 33))]
3402 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3406 [(set_attr "op_type" "RR,RX")
3407 (set_attr "type" "fsimps,fsimps")])
3411 ;;- Subtract instructions.
3415 ; subdi3 instruction pattern(s).
3418 (define_insn "*subdi3_sign"
3419 [(set (match_operand:DI 0 "register_operand" "=d,d")
3420 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3421 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3422 (clobber (reg:CC 33))]
3427 [(set_attr "op_type" "RRE,RXE")])
3429 (define_insn "*subdi3_zero_cc"
3431 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3432 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3434 (set (match_operand:DI 0 "register_operand" "=d,d")
3435 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3436 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3440 [(set_attr "op_type" "RRE,RXE")])
3442 (define_insn "*subdi3_zero_cconly"
3444 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3445 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3447 (clobber (match_scratch:DI 0 "=d,d"))]
3448 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3452 [(set_attr "op_type" "RRE,RXE")])
3454 (define_insn "*subdi3_zero"
3455 [(set (match_operand:DI 0 "register_operand" "=d,d")
3456 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3457 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3458 (clobber (reg:CC 33))]
3463 [(set_attr "op_type" "RRE,RXE")])
3465 (define_insn "*subdi3_cc"
3467 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3468 (match_operand:DI 2 "general_operand" "d,m"))
3470 (set (match_operand:DI 0 "register_operand" "=d,d")
3471 (minus:DI (match_dup 1) (match_dup 2)))]
3472 "s390_match_ccmode (insn, CCLmode)"
3476 [(set_attr "op_type" "RRE,RXE")])
3478 (define_insn "*subdi3_cconly"
3480 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3481 (match_operand:DI 2 "general_operand" "d,m"))
3483 (clobber (match_scratch:DI 0 "=d,d"))]
3484 "s390_match_ccmode (insn, CCLmode)"
3488 [(set_attr "op_type" "RRE,RXE")])
3490 (define_insn "*subdi3_64"
3491 [(set (match_operand:DI 0 "register_operand" "=d,d")
3492 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3493 (match_operand:DI 2 "general_operand" "d,m") ) )
3494 (clobber (reg:CC 33))]
3499 [(set_attr "op_type" "RRE,RRE")])
3501 (define_insn_and_split "*subdi3_31"
3502 [(set (match_operand:DI 0 "register_operand" "=&d")
3503 (minus:DI (match_operand:DI 1 "register_operand" "0")
3504 (match_operand:DI 2 "general_operand" "dm") ) )
3505 (clobber (reg:CC 33))]
3508 "&& reload_completed"
3510 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3511 (clobber (reg:CC 33))])
3514 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3516 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3518 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3520 (label_ref (match_dup 9))))
3522 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3523 (clobber (reg:CC 33))])
3525 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3526 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3527 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3528 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3529 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3530 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3531 operands[9] = gen_label_rtx ();"
3532 [(set_attr "op_type" "NN")
3533 (set_attr "type" "o3")])
3535 (define_expand "subdi3"
3537 [(set (match_operand:DI 0 "register_operand" "")
3538 (minus:DI (match_operand:DI 1 "register_operand" "")
3539 (match_operand:DI 2 "general_operand" "")))
3540 (clobber (reg:CC 33))])]
3545 ; subsi3 instruction pattern(s).
3548 (define_insn "*subsi3_borrow_cc"
3550 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3551 (match_operand:SI 2 "general_operand" "d,m"))
3553 (set (match_operand:SI 0 "register_operand" "=d,d")
3554 (minus:SI (match_dup 1) (match_dup 2)))]
3555 "s390_match_ccmode(insn, CCL2mode)"
3559 [(set_attr "op_type" "RR,RX")])
3561 (define_insn "*subsi3_borrow_cconly"
3563 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3564 (match_operand:SI 2 "general_operand" "d,m"))
3566 (clobber (match_scratch:SI 0 "=d,d"))]
3567 "s390_match_ccmode(insn, CCL2mode)"
3571 [(set_attr "op_type" "RR,RX")])
3573 (define_insn "*subsi3_cc"
3575 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3576 (match_operand:SI 2 "general_operand" "d,m"))
3578 (set (match_operand:SI 0 "register_operand" "=d,d")
3579 (minus:SI (match_dup 1) (match_dup 2)))]
3580 "s390_match_ccmode(insn, CCLmode)"
3584 [(set_attr "op_type" "RR,RX")])
3586 (define_insn "*subsi3_cconly"
3588 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3589 (match_operand:SI 2 "general_operand" "d,m"))
3591 (clobber (match_scratch:SI 0 "=d,d"))]
3592 "s390_match_ccmode(insn, CCLmode)"
3596 [(set_attr "op_type" "RR,RX")])
3598 (define_insn "*subsi3_sign"
3599 [(set (match_operand:SI 0 "register_operand" "=d")
3600 (minus:SI (match_operand:SI 1 "register_operand" "0")
3601 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3602 (clobber (reg:CC 33))]
3605 [(set_attr "op_type" "RX")])
3607 (define_insn "*subsi3_sub"
3608 [(set (match_operand:SI 0 "register_operand" "=d")
3609 (minus:SI (match_operand:SI 1 "register_operand" "0")
3610 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3611 (clobber (reg:CC 33))]
3614 [(set_attr "op_type" "RX")])
3616 (define_insn "subsi3"
3617 [(set (match_operand:SI 0 "register_operand" "=d,d")
3618 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3619 (match_operand:SI 2 "general_operand" "d,m")))
3620 (clobber (reg:CC 33))]
3625 [(set_attr "op_type" "RR,RX")])
3629 ; subdf3 instruction pattern(s).
3632 (define_expand "subdf3"
3634 [(set (match_operand:DF 0 "register_operand" "=f,f")
3635 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3636 (match_operand:DF 2 "general_operand" "f,m")))
3637 (clobber (reg:CC 33))])]
3641 (define_insn "*subdf3"
3642 [(set (match_operand:DF 0 "register_operand" "=f,f")
3643 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3644 (match_operand:DF 2 "general_operand" "f,m")))
3645 (clobber (reg:CC 33))]
3646 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3650 [(set_attr "op_type" "RRE,RXE")
3651 (set_attr "type" "fsimpd,fsimpd")])
3653 (define_insn "*subdf3_ibm"
3654 [(set (match_operand:DF 0 "register_operand" "=f,f")
3655 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3656 (match_operand:DF 2 "general_operand" "f,m")))
3657 (clobber (reg:CC 33))]
3658 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3662 [(set_attr "op_type" "RR,RX")
3663 (set_attr "type" "fsimpd,fsimpd")])
3666 ; subsf3 instruction pattern(s).
3669 (define_expand "subsf3"
3671 [(set (match_operand:SF 0 "register_operand" "=f,f")
3672 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3673 (match_operand:SF 2 "general_operand" "f,m")))
3674 (clobber (reg:CC 33))])]
3678 (define_insn "*subsf3"
3679 [(set (match_operand:SF 0 "register_operand" "=f,f")
3680 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3681 (match_operand:SF 2 "general_operand" "f,m")))
3682 (clobber (reg:CC 33))]
3683 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3687 [(set_attr "op_type" "RRE,RXE")
3688 (set_attr "type" "fsimps,fsimps")])
3690 (define_insn "*subsf3_ibm"
3691 [(set (match_operand:SF 0 "register_operand" "=f,f")
3692 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3693 (match_operand:SF 2 "general_operand" "f,m")))
3694 (clobber (reg:CC 33))]
3695 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3699 [(set_attr "op_type" "RR,RX")
3700 (set_attr "type" "fsimps,fsimps")])
3704 ;;- Multiply instructions.
3708 ; muldi3 instruction pattern(s).
3711 (define_insn "*muldi3_sign"
3712 [(set (match_operand:DI 0 "register_operand" "=d,d")
3713 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3714 (match_operand:DI 1 "register_operand" "0,0")))]
3719 [(set_attr "op_type" "RRE,RXE")
3720 (set_attr "type" "imul")])
3723 (define_insn "muldi3"
3724 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3725 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3726 (match_operand:DI 2 "general_operand" "d,K,m")))]
3732 [(set_attr "op_type" "RRE,RI,RXE")
3733 (set_attr "type" "imul")])
3736 ; mulsi3 instruction pattern(s).
3739 (define_insn "mulsi3"
3740 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3741 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3742 (match_operand:SI 2 "general_operand" "d,K,m")))]
3748 [(set_attr "op_type" "RRE,RI,RX")
3749 (set_attr "type" "imul")])
3752 ; mulsidi3 instruction pattern(s).
3755 (define_expand "mulsidi3"
3756 [(set (match_operand:DI 0 "register_operand" "")
3757 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3758 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3764 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3765 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3768 gen_rtx_EXPR_LIST (REG_EQUAL,
3769 gen_rtx_MULT (DImode,
3770 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3771 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3776 (define_insn "mulsi_6432"
3777 [(set (match_operand:DI 0 "register_operand" "=d,d")
3778 (mult:DI (sign_extend:DI
3779 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3781 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3786 [(set_attr "op_type" "RR,RX")
3787 (set_attr "type" "imul")])
3790 ; muldf3 instruction pattern(s).
3793 (define_expand "muldf3"
3795 [(set (match_operand:DF 0 "register_operand" "=f,f")
3796 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3797 (match_operand:DF 2 "general_operand" "f,m")))
3798 (clobber (reg:CC 33))])]
3802 (define_insn "*muldf3"
3803 [(set (match_operand:DF 0 "register_operand" "=f,f")
3804 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3805 (match_operand:DF 2 "general_operand" "f,m")))
3806 (clobber (reg:CC 33))]
3807 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3811 [(set_attr "op_type" "RRE,RXE")
3812 (set_attr "type" "fmuld")])
3814 (define_insn "*muldf3_ibm"
3815 [(set (match_operand:DF 0 "register_operand" "=f,f")
3816 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3817 (match_operand:DF 2 "general_operand" "f,m")))
3818 (clobber (reg:CC 33))]
3819 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3823 [(set_attr "op_type" "RR,RX")
3824 (set_attr "type" "fmuld")])
3827 ; mulsf3 instruction pattern(s).
3830 (define_expand "mulsf3"
3832 [(set (match_operand:SF 0 "register_operand" "=f,f")
3833 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3834 (match_operand:SF 2 "general_operand" "f,m")))
3835 (clobber (reg:CC 33))])]
3839 (define_insn "*mulsf3"
3840 [(set (match_operand:SF 0 "register_operand" "=f,f")
3841 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3842 (match_operand:SF 2 "general_operand" "f,m")))
3843 (clobber (reg:CC 33))]
3844 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3848 [(set_attr "op_type" "RRE,RXE")
3849 (set_attr "type" "fmuls")])
3851 (define_insn "*mulsf3_ibm"
3852 [(set (match_operand:SF 0 "register_operand" "=f,f")
3853 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3854 (match_operand:SF 2 "general_operand" "f,m")))
3855 (clobber (reg:CC 33))]
3856 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3860 [(set_attr "op_type" "RR,RX")
3861 (set_attr "type" "fmuls")])
3865 ;;- Divide and modulo instructions.
3869 ; divmoddi4 instruction pattern(s).
3872 (define_expand "divmoddi4"
3873 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3874 (div:DI (match_operand:DI 1 "general_operand" "")
3875 (match_operand:DI 2 "general_operand" "")))
3876 (set (match_operand:DI 3 "general_operand" "")
3877 (mod:DI (match_dup 1) (match_dup 2)))])
3878 (clobber (match_dup 4))]
3882 rtx insn, div_equal, mod_equal, equal;
3884 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3885 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3886 equal = gen_rtx_IOR (TImode,
3887 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3888 gen_rtx_ASHIFT (TImode,
3889 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3892 operands[4] = gen_reg_rtx(TImode);
3893 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3894 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3895 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3896 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3898 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3900 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3902 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3904 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3906 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3911 (define_insn "divmodtidi3"
3912 [(set (match_operand:TI 0 "register_operand" "=d,d")
3915 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3916 (match_operand:DI 2 "general_operand" "d,m")))
3919 (mod:DI (truncate:DI (match_dup 1))
3926 [(set_attr "op_type" "RRE,RXE")
3927 (set_attr "type" "idiv")])
3929 (define_insn "divmodtisi3"
3930 [(set (match_operand:TI 0 "register_operand" "=d,d")
3933 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3934 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3937 (mod:DI (truncate:DI (match_dup 1))
3938 (sign_extend:DI (match_dup 2))))
3944 [(set_attr "op_type" "RRE,RXE")
3945 (set_attr "type" "idiv")])
3948 ; udivmoddi4 instruction pattern(s).
3951 (define_expand "udivmoddi4"
3952 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3953 (udiv:DI (match_operand:DI 1 "general_operand" "")
3954 (match_operand:DI 2 "nonimmediate_operand" "")))
3955 (set (match_operand:DI 3 "general_operand" "")
3956 (umod:DI (match_dup 1) (match_dup 2)))])
3957 (clobber (match_dup 4))]
3961 rtx insn, div_equal, mod_equal, equal;
3963 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3964 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3965 equal = gen_rtx_IOR (TImode,
3966 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3967 gen_rtx_ASHIFT (TImode,
3968 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3971 operands[4] = gen_reg_rtx(TImode);
3972 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3973 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3974 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3975 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3977 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3979 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3981 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3983 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3985 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3990 (define_insn "udivmodtidi3"
3991 [(set (match_operand:TI 0 "register_operand" "=d,d")
3992 (ior:TI (zero_extend:TI
3994 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3996 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4000 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
4006 [(set_attr "op_type" "RRE,RXE")
4007 (set_attr "type" "idiv")])
4010 ; divmodsi4 instruction pattern(s).
4013 (define_expand "divmodsi4"
4014 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4015 (div:SI (match_operand:SI 1 "general_operand" "")
4016 (match_operand:SI 2 "nonimmediate_operand" "")))
4017 (set (match_operand:SI 3 "general_operand" "")
4018 (mod:SI (match_dup 1) (match_dup 2)))])
4019 (clobber (match_dup 4))]
4023 rtx insn, div_equal, mod_equal, equal;
4025 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4026 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4027 equal = gen_rtx_IOR (DImode,
4028 gen_rtx_ZERO_EXTEND (DImode, div_equal),
4029 gen_rtx_ASHIFT (DImode,
4030 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4033 operands[4] = gen_reg_rtx(DImode);
4034 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4035 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4037 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4039 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4041 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4043 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4045 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4050 (define_insn "divmoddisi3"
4051 [(set (match_operand:DI 0 "register_operand" "=d,d")
4052 (ior:DI (zero_extend:DI
4054 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4056 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4060 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4066 [(set_attr "op_type" "RR,RX")
4067 (set_attr "type" "idiv")])
4070 ; udivsi3 and umodsi3 instruction pattern(s).
4074 (define_expand "udivsi3"
4075 [(set (match_operand:SI 0 "register_operand" "=d")
4076 (udiv:SI (match_operand:SI 1 "general_operand" "")
4077 (match_operand:SI 2 "general_operand" "")))
4078 (clobber (match_dup 3))]
4082 rtx insn, udiv_equal, umod_equal, equal;
4084 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4085 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4086 equal = gen_rtx_IOR (DImode,
4087 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4088 gen_rtx_ASHIFT (DImode,
4089 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4092 operands[3] = gen_reg_rtx (DImode);
4094 if (CONSTANT_P (operands[2]))
4096 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4098 rtx label1 = gen_label_rtx ();
4100 operands[1] = make_safe_from (operands[1], operands[0]);
4101 emit_move_insn (operands[0], const0_rtx);
4102 emit_insn (gen_cmpsi (operands[1], operands[2]));
4103 emit_jump_insn (gen_bltu (label1));
4104 emit_move_insn (operands[0], const1_rtx);
4105 emit_label (label1);
4109 operands[2] = force_reg (SImode, operands[2]);
4110 operands[2] = make_safe_from (operands[2], operands[0]);
4112 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4113 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4116 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4118 insn = emit_move_insn (operands[0],
4119 gen_lowpart (SImode, operands[3]));
4121 gen_rtx_EXPR_LIST (REG_EQUAL,
4122 udiv_equal, REG_NOTES (insn));
4127 rtx label1 = gen_label_rtx ();
4128 rtx label2 = gen_label_rtx ();
4129 rtx label3 = gen_label_rtx ();
4131 operands[1] = force_reg (SImode, operands[1]);
4132 operands[1] = make_safe_from (operands[1], operands[0]);
4133 operands[2] = force_reg (SImode, operands[2]);
4134 operands[2] = make_safe_from (operands[2], operands[0]);
4136 emit_move_insn (operands[0], const0_rtx);
4137 emit_insn (gen_cmpsi (operands[2], operands[1]));
4138 emit_jump_insn (gen_bgtu (label3));
4139 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4140 emit_jump_insn (gen_blt (label2));
4141 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4142 emit_jump_insn (gen_beq (label1));
4143 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4144 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4147 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4149 insn = emit_move_insn (operands[0],
4150 gen_lowpart (SImode, operands[3]));
4152 gen_rtx_EXPR_LIST (REG_EQUAL,
4153 udiv_equal, REG_NOTES (insn));
4155 emit_label (label1);
4156 emit_move_insn (operands[0], operands[1]);
4158 emit_label (label2);
4159 emit_move_insn (operands[0], const1_rtx);
4160 emit_label (label3);
4162 emit_move_insn (operands[0], operands[0]);
4166 (define_expand "umodsi3"
4167 [(set (match_operand:SI 0 "register_operand" "=d")
4168 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4169 (match_operand:SI 2 "nonimmediate_operand" "")))
4170 (clobber (match_dup 3))]
4174 rtx insn, udiv_equal, umod_equal, equal;
4176 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4177 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4178 equal = gen_rtx_IOR (DImode,
4179 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4180 gen_rtx_ASHIFT (DImode,
4181 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4184 operands[3] = gen_reg_rtx (DImode);
4186 if (CONSTANT_P (operands[2]))
4188 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4190 rtx label1 = gen_label_rtx ();
4192 operands[1] = make_safe_from (operands[1], operands[0]);
4193 emit_move_insn (operands[0], operands[1]);
4194 emit_insn (gen_cmpsi (operands[0], operands[2]));
4195 emit_jump_insn (gen_bltu (label1));
4196 emit_insn (gen_abssi2 (operands[0], operands[2]));
4197 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4198 emit_label (label1);
4202 operands[2] = force_reg (SImode, operands[2]);
4203 operands[2] = make_safe_from (operands[2], operands[0]);
4205 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4206 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4209 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4211 insn = emit_move_insn (operands[0],
4212 gen_highpart (SImode, operands[3]));
4214 gen_rtx_EXPR_LIST (REG_EQUAL,
4215 umod_equal, REG_NOTES (insn));
4220 rtx label1 = gen_label_rtx ();
4221 rtx label2 = gen_label_rtx ();
4222 rtx label3 = gen_label_rtx ();
4224 operands[1] = force_reg (SImode, operands[1]);
4225 operands[1] = make_safe_from (operands[1], operands[0]);
4226 operands[2] = force_reg (SImode, operands[2]);
4227 operands[2] = make_safe_from (operands[2], operands[0]);
4229 emit_move_insn(operands[0], operands[1]);
4230 emit_insn (gen_cmpsi (operands[2], operands[1]));
4231 emit_jump_insn (gen_bgtu (label3));
4232 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4233 emit_jump_insn (gen_blt (label2));
4234 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4235 emit_jump_insn (gen_beq (label1));
4236 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4237 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4240 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4242 insn = emit_move_insn (operands[0],
4243 gen_highpart (SImode, operands[3]));
4245 gen_rtx_EXPR_LIST (REG_EQUAL,
4246 umod_equal, REG_NOTES (insn));
4248 emit_label (label1);
4249 emit_move_insn (operands[0], const0_rtx);
4251 emit_label (label2);
4252 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4253 emit_label (label3);
4259 ; divdf3 instruction pattern(s).
4262 (define_expand "divdf3"
4264 [(set (match_operand:DF 0 "register_operand" "=f,f")
4265 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4266 (match_operand:DF 2 "general_operand" "f,m")))
4267 (clobber (reg:CC 33))])]
4271 (define_insn "*divdf3"
4272 [(set (match_operand:DF 0 "register_operand" "=f,f")
4273 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4274 (match_operand:DF 2 "general_operand" "f,m")))
4275 (clobber (reg:CC 33))]
4276 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4280 [(set_attr "op_type" "RRE,RXE")
4281 (set_attr "type" "fdivd")])
4283 (define_insn "*divdf3_ibm"
4284 [(set (match_operand:DF 0 "register_operand" "=f,f")
4285 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4286 (match_operand:DF 2 "general_operand" "f,m")))
4287 (clobber (reg:CC 33))]
4288 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4292 [(set_attr "op_type" "RR,RX")
4293 (set_attr "type" "fdivd")])
4296 ; divsf3 instruction pattern(s).
4299 (define_expand "divsf3"
4301 [(set (match_operand:SF 0 "register_operand" "=f,f")
4302 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4303 (match_operand:SF 2 "general_operand" "f,m")))
4304 (clobber (reg:CC 33))])]
4308 (define_insn "*divsf3"
4309 [(set (match_operand:SF 0 "register_operand" "=f,f")
4310 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4311 (match_operand:SF 2 "general_operand" "f,m")))
4312 (clobber (reg:CC 33))]
4313 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4317 [(set_attr "op_type" "RRE,RXE")
4318 (set_attr "type" "fdivs")])
4320 (define_insn "*divsf3"
4321 [(set (match_operand:SF 0 "register_operand" "=f,f")
4322 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4323 (match_operand:SF 2 "general_operand" "f,m")))
4324 (clobber (reg:CC 33))]
4325 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4329 [(set_attr "op_type" "RR,RX")
4330 (set_attr "type" "fdivs")])
4334 ;;- And instructions.
4338 ; anddi3 instruction pattern(s).
4341 (define_insn "*anddi3_cc"
4343 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4344 (match_operand:DI 2 "general_operand" "d,m"))
4346 (set (match_operand:DI 0 "register_operand" "=d,d")
4347 (and:DI (match_dup 1) (match_dup 2)))]
4348 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4352 [(set_attr "op_type" "RRE,RXE")])
4354 (define_insn "*anddi3_cconly"
4356 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4357 (match_operand:DI 2 "general_operand" "d,m"))
4359 (clobber (match_scratch:DI 0 "=d,d"))]
4360 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4364 [(set_attr "op_type" "RRE,RXE")])
4366 (define_insn "*anddi3_ni"
4367 [(set (match_operand:DI 0 "register_operand" "=d")
4368 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4369 (match_operand:DI 2 "immediate_operand" "n")))
4370 (clobber (reg:CC 33))]
4371 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4374 int part = s390_single_hi (operands[2], DImode, -1);
4375 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4379 case 0: return \"nihh\\t%0,%x2\";
4380 case 1: return \"nihl\\t%0,%x2\";
4381 case 2: return \"nilh\\t%0,%x2\";
4382 case 3: return \"nill\\t%0,%x2\";
4386 [(set_attr "op_type" "RI")])
4388 (define_insn "anddi3"
4389 [(set (match_operand:DI 0 "register_operand" "=d,d")
4390 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4391 (match_operand:DI 2 "general_operand" "d,m")))
4392 (clobber (reg:CC 33))]
4397 [(set_attr "op_type" "RRE,RXE")])
4399 (define_insn "*anddi3_ss"
4400 [(set (match_operand:DI 0 "s_operand" "=Q")
4401 (and:DI (match_dup 0)
4402 (match_operand:DI 1 "s_imm_operand" "Q")))
4403 (clobber (reg:CC 33))]
4405 "nc\\t%O0(8,%R0),%1"
4406 [(set_attr "op_type" "SS")])
4408 (define_insn "*anddi3_ss_inv"
4409 [(set (match_operand:DI 0 "s_operand" "=Q")
4410 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4412 (clobber (reg:CC 33))]
4414 "nc\\t%O0(8,%R0),%1"
4415 [(set_attr "op_type" "SS")])
4418 ; andsi3 instruction pattern(s).
4421 (define_insn "*andsi3_cc"
4423 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4424 (match_operand:SI 2 "general_operand" "d,m"))
4426 (set (match_operand:SI 0 "register_operand" "=d,d")
4427 (and:SI (match_dup 1) (match_dup 2)))]
4428 "s390_match_ccmode(insn, CCTmode)"
4432 [(set_attr "op_type" "RR,RX")])
4434 (define_insn "*andsi3_cconly"
4436 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4437 (match_operand:SI 2 "general_operand" "d,m"))
4439 (clobber (match_scratch:SI 0 "=d,d"))]
4440 "s390_match_ccmode(insn, CCTmode)"
4444 [(set_attr "op_type" "RR,RX")])
4446 (define_insn "*andsi3_ni"
4447 [(set (match_operand:SI 0 "register_operand" "=d")
4448 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4449 (match_operand:SI 2 "immediate_operand" "n")))
4450 (clobber (reg:CC 33))]
4451 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4454 int part = s390_single_hi (operands[2], SImode, -1);
4455 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4459 case 0: return \"nilh\\t%0,%x2\";
4460 case 1: return \"nill\\t%0,%x2\";
4464 [(set_attr "op_type" "RI")])
4466 (define_insn "andsi3"
4467 [(set (match_operand:SI 0 "register_operand" "=d,d")
4468 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4469 (match_operand:SI 2 "general_operand" "d,m")))
4470 (clobber (reg:CC 33))]
4475 [(set_attr "op_type" "RR,RX")])
4477 (define_insn "*andsi3_ss"
4478 [(set (match_operand:SI 0 "s_operand" "=Q")
4479 (and:SI (match_dup 0)
4480 (match_operand:SI 1 "s_imm_operand" "Q")))
4481 (clobber (reg:CC 33))]
4483 "nc\\t%O0(4,%R0),%1"
4484 [(set_attr "op_type" "SS")])
4486 (define_insn "*andsi3_ss_inv"
4487 [(set (match_operand:SI 0 "s_operand" "=Q")
4488 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4490 (clobber (reg:CC 33))]
4492 "nc\\t%O0(4,%R0),%1"
4493 [(set_attr "op_type" "SS")])
4496 ; andhi3 instruction pattern(s).
4499 (define_insn "*andhi3_ni"
4500 [(set (match_operand:HI 0 "register_operand" "=d,d")
4501 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4502 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4503 (clobber (reg:CC 33))]
4508 [(set_attr "op_type" "RR,RI")])
4510 (define_insn "andhi3"
4511 [(set (match_operand:HI 0 "register_operand" "=d")
4512 (and:HI (match_operand:HI 1 "register_operand" "%0")
4513 (match_operand:HI 2 "nonmemory_operand" "d")))
4514 (clobber (reg:CC 33))]
4517 [(set_attr "op_type" "RR")])
4519 (define_insn "*andhi3_ss"
4520 [(set (match_operand:HI 0 "s_operand" "=Q")
4521 (and:HI (match_dup 0)
4522 (match_operand:HI 1 "s_imm_operand" "Q")))
4523 (clobber (reg:CC 33))]
4525 "nc\\t%O0(2,%R0),%1"
4526 [(set_attr "op_type" "SS")])
4528 (define_insn "*andhi3_ss_inv"
4529 [(set (match_operand:HI 0 "s_operand" "=Q")
4530 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4532 (clobber (reg:CC 33))]
4534 "nc\\t%O0(2,%R0),%1"
4535 [(set_attr "op_type" "SS")])
4538 ; andqi3 instruction pattern(s).
4541 (define_insn "*andqi3_ni"
4542 [(set (match_operand:QI 0 "register_operand" "=d,d")
4543 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4544 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4545 (clobber (reg:CC 33))]
4550 [(set_attr "op_type" "RR,RI")])
4552 (define_insn "andqi3"
4553 [(set (match_operand:QI 0 "register_operand" "=d")
4554 (and:QI (match_operand:QI 1 "register_operand" "%0")
4555 (match_operand:QI 2 "nonmemory_operand" "d")))
4556 (clobber (reg:CC 33))]
4559 [(set_attr "op_type" "RR")])
4561 (define_insn "*andqi3_ss"
4562 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4563 (and:QI (match_dup 0)
4564 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4565 (clobber (reg:CC 33))]
4570 [(set_attr "op_type" "SI,SS")])
4572 (define_insn "*andqi3_ss_inv"
4573 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4574 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4576 (clobber (reg:CC 33))]
4581 [(set_attr "op_type" "SI,SS")])
4585 ;;- Bit set (inclusive or) instructions.
4589 ; iordi3 instruction pattern(s).
4592 (define_insn "*iordi3_cc"
4594 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4595 (match_operand:DI 2 "general_operand" "d,m"))
4597 (set (match_operand:DI 0 "register_operand" "=d,d")
4598 (ior:DI (match_dup 1) (match_dup 2)))]
4599 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4603 [(set_attr "op_type" "RRE,RXE")])
4605 (define_insn "*iordi3_cconly"
4607 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4608 (match_operand:DI 2 "general_operand" "d,m"))
4610 (clobber (match_scratch:DI 0 "=d,d"))]
4611 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4615 [(set_attr "op_type" "RRE,RXE")])
4617 (define_insn "*iordi3_oi"
4618 [(set (match_operand:DI 0 "register_operand" "=d")
4619 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4620 (match_operand:DI 2 "immediate_operand" "n")))
4621 (clobber (reg:CC 33))]
4622 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4625 int part = s390_single_hi (operands[2], DImode, 0);
4626 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4630 case 0: return \"oihh\\t%0,%x2\";
4631 case 1: return \"oihl\\t%0,%x2\";
4632 case 2: return \"oilh\\t%0,%x2\";
4633 case 3: return \"oill\\t%0,%x2\";
4637 [(set_attr "op_type" "RI")])
4639 (define_insn "iordi3"
4640 [(set (match_operand:DI 0 "register_operand" "=d,d")
4641 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4642 (match_operand:DI 2 "general_operand" "d,m")))
4643 (clobber (reg:CC 33))]
4648 [(set_attr "op_type" "RRE,RXE")])
4650 (define_insn "*iordi3_ss"
4651 [(set (match_operand:DI 0 "s_operand" "=Q")
4652 (ior:DI (match_dup 0)
4653 (match_operand:DI 1 "s_imm_operand" "Q")))
4654 (clobber (reg:CC 33))]
4656 "oc\\t%O0(8,%R0),%1"
4657 [(set_attr "op_type" "SS")])
4659 (define_insn "*iordi3_ss_inv"
4660 [(set (match_operand:DI 0 "s_operand" "=Q")
4661 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4663 (clobber (reg:CC 33))]
4665 "oc\\t%O0(8,%R0),%1"
4666 [(set_attr "op_type" "SS")])
4669 ; iorsi3 instruction pattern(s).
4672 (define_insn "*iorsi3_cc"
4674 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4675 (match_operand:SI 2 "general_operand" "d,m"))
4677 (set (match_operand:SI 0 "register_operand" "=d,d")
4678 (ior:SI (match_dup 1) (match_dup 2)))]
4679 "s390_match_ccmode(insn, CCTmode)"
4683 [(set_attr "op_type" "RR,RX")])
4685 (define_insn "*iorsi3_cconly"
4687 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4688 (match_operand:SI 2 "general_operand" "d,m"))
4690 (clobber (match_scratch:SI 0 "=d,d"))]
4691 "s390_match_ccmode(insn, CCTmode)"
4695 [(set_attr "op_type" "RR,RX")])
4697 (define_insn "*iorsi3_oi"
4698 [(set (match_operand:SI 0 "register_operand" "=d")
4699 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4700 (match_operand:SI 2 "immediate_operand" "n")))
4701 (clobber (reg:CC 33))]
4702 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4705 int part = s390_single_hi (operands[2], SImode, 0);
4706 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4710 case 0: return \"oilh\\t%0,%x2\";
4711 case 1: return \"oill\\t%0,%x2\";
4715 [(set_attr "op_type" "RI")])
4717 (define_insn "iorsi3"
4718 [(set (match_operand:SI 0 "register_operand" "=d,d")
4719 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4720 (match_operand:SI 2 "general_operand" "d,m")))
4721 (clobber (reg:CC 33))]
4726 [(set_attr "op_type" "RR,RX")])
4728 (define_insn "*iorsi3_ss"
4729 [(set (match_operand:SI 0 "s_operand" "=Q")
4730 (ior:SI (match_dup 0)
4731 (match_operand:SI 1 "s_imm_operand" "Q")))
4732 (clobber (reg:CC 33))]
4734 "oc\\t%O0(4,%R0),%1"
4735 [(set_attr "op_type" "SS")])
4737 (define_insn "*iorsi3_ss_inv"
4738 [(set (match_operand:SI 0 "s_operand" "=Q")
4739 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4741 (clobber (reg:CC 33))]
4743 "oc\\t%O0(4,%R0),%1"
4744 [(set_attr "op_type" "SS")])
4747 ; iorhi3 instruction pattern(s).
4750 (define_insn "*iorhi3_oi"
4751 [(set (match_operand:HI 0 "register_operand" "=d,d")
4752 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4753 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4754 (clobber (reg:CC 33))]
4759 [(set_attr "op_type" "RR,RI")])
4761 (define_insn "iorhi3"
4762 [(set (match_operand:HI 0 "register_operand" "=d")
4763 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4764 (match_operand:HI 2 "nonmemory_operand" "d")))
4765 (clobber (reg:CC 33))]
4768 [(set_attr "op_type" "RR")])
4770 (define_insn "*iorhi3_ss"
4771 [(set (match_operand:HI 0 "s_operand" "=Q")
4772 (ior:HI (match_dup 0)
4773 (match_operand:HI 1 "s_imm_operand" "Q")))
4774 (clobber (reg:CC 33))]
4776 "oc\\t%O0(2,%R0),%1"
4777 [(set_attr "op_type" "SS")])
4779 (define_insn "*iorhi3_ss_inv"
4780 [(set (match_operand:HI 0 "s_operand" "=Q")
4781 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4783 (clobber (reg:CC 33))]
4785 "oc\\t%O0(2,%R0),%1"
4786 [(set_attr "op_type" "SS")])
4789 ; iorqi3 instruction pattern(s).
4792 (define_insn "*iorqi3_oi"
4793 [(set (match_operand:QI 0 "register_operand" "=d,d")
4794 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4795 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4796 (clobber (reg:CC 33))]
4801 [(set_attr "op_type" "RR,RI")])
4803 (define_insn "iorqi3"
4804 [(set (match_operand:QI 0 "register_operand" "=d")
4805 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4806 (match_operand:QI 2 "nonmemory_operand" "d")))
4807 (clobber (reg:CC 33))]
4810 [(set_attr "op_type" "RR")])
4812 (define_insn "*iorqi3_ss"
4813 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4814 (ior:QI (match_dup 0)
4815 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4816 (clobber (reg:CC 33))]
4821 [(set_attr "op_type" "SI,SS")])
4823 (define_insn "*iorqi3_ss_inv"
4824 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4825 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4827 (clobber (reg:CC 33))]
4832 [(set_attr "op_type" "SI,SS")])
4836 ;;- Xor instructions.
4840 ; xordi3 instruction pattern(s).
4843 (define_insn "*xordi3_cc"
4845 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4846 (match_operand:DI 2 "general_operand" "d,m"))
4848 (set (match_operand:DI 0 "register_operand" "=d,d")
4849 (xor:DI (match_dup 1) (match_dup 2)))]
4850 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4854 [(set_attr "op_type" "RRE,RXE")])
4856 (define_insn "*xordi3_cconly"
4858 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4859 (match_operand:DI 2 "general_operand" "d,m"))
4861 (clobber (match_scratch:DI 0 "=d,d"))]
4862 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4866 [(set_attr "op_type" "RRE,RXE")])
4868 (define_insn "xordi3"
4869 [(set (match_operand:DI 0 "register_operand" "=d,d")
4870 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4871 (match_operand:DI 2 "general_operand" "d,m")))
4872 (clobber (reg:CC 33))]
4877 [(set_attr "op_type" "RRE,RXE")])
4879 (define_insn "*xordi3_ss"
4880 [(set (match_operand:DI 0 "s_operand" "=Q")
4881 (xor:DI (match_dup 0)
4882 (match_operand:DI 1 "s_imm_operand" "Q")))
4883 (clobber (reg:CC 33))]
4885 "xc\\t%O0(8,%R0),%1"
4886 [(set_attr "op_type" "SS")])
4888 (define_insn "*xordi3_ss_inv"
4889 [(set (match_operand:DI 0 "s_operand" "=Q")
4890 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4892 (clobber (reg:CC 33))]
4894 "xc\\t%O0(8,%R0),%1"
4895 [(set_attr "op_type" "SS")])
4898 ; xorsi3 instruction pattern(s).
4901 (define_insn "*xorsi3_cc"
4903 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4904 (match_operand:SI 2 "general_operand" "d,m"))
4906 (set (match_operand:SI 0 "register_operand" "=d,d")
4907 (xor:SI (match_dup 1) (match_dup 2)))]
4908 "s390_match_ccmode(insn, CCTmode)"
4912 [(set_attr "op_type" "RR,RX")])
4914 (define_insn "*xorsi3_cconly"
4916 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4917 (match_operand:SI 2 "general_operand" "d,m"))
4919 (clobber (match_scratch:SI 0 "=d,d"))]
4920 "s390_match_ccmode(insn, CCTmode)"
4924 [(set_attr "op_type" "RR,RX")])
4926 (define_insn "xorsi3"
4927 [(set (match_operand:SI 0 "register_operand" "=d,d")
4928 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4929 (match_operand:SI 2 "general_operand" "d,m")))
4930 (clobber (reg:CC 33))]
4935 [(set_attr "op_type" "RR,RX")])
4937 (define_insn "*xorsi3_ss"
4938 [(set (match_operand:SI 0 "s_operand" "=Q")
4939 (xor:SI (match_dup 0)
4940 (match_operand:SI 1 "s_imm_operand" "Q")))
4941 (clobber (reg:CC 33))]
4943 "xc\\t%O0(4,%R0),%1"
4944 [(set_attr "op_type" "SS")])
4946 (define_insn "*xorsi3_ss_inv"
4947 [(set (match_operand:SI 0 "s_operand" "=Q")
4948 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
4950 (clobber (reg:CC 33))]
4952 "xc\\t%O0(4,%R0),%1"
4953 [(set_attr "op_type" "SS")])
4956 ; xorhi3 instruction pattern(s).
4959 (define_insn "xorhi3"
4960 [(set (match_operand:HI 0 "register_operand" "=d")
4961 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4962 (match_operand:HI 2 "nonmemory_operand" "d")))
4963 (clobber (reg:CC 33))]
4966 [(set_attr "op_type" "RR")
4967 (set_attr "atype" "reg")])
4969 (define_insn "*xorhi3_ss"
4970 [(set (match_operand:HI 0 "s_operand" "=Q")
4971 (xor:HI (match_dup 0)
4972 (match_operand:HI 1 "s_imm_operand" "Q")))
4973 (clobber (reg:CC 33))]
4975 "xc\\t%O0(2,%R0),%1"
4976 [(set_attr "op_type" "SS")])
4978 (define_insn "*xorhi3_ss_inv"
4979 [(set (match_operand:HI 0 "s_operand" "=Q")
4980 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
4982 (clobber (reg:CC 33))]
4984 "xc\\t%O0(2,%R0),%1"
4985 [(set_attr "op_type" "SS")])
4988 ; xorqi3 instruction pattern(s).
4991 (define_insn "xorqi3"
4992 [(set (match_operand:QI 0 "register_operand" "=d")
4993 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4994 (match_operand:QI 2 "nonmemory_operand" "d")))
4995 (clobber (reg:CC 33))]
4998 [(set_attr "op_type" "RR")])
5000 (define_insn "*xorqi3_ss"
5001 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5002 (xor:QI (match_dup 0)
5003 (match_operand:QI 1 "s_imm_operand" "n,Q")))
5004 (clobber (reg:CC 33))]
5009 [(set_attr "op_type" "SI,SS")])
5011 (define_insn "*xorqi3_ss_inv"
5012 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5013 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
5015 (clobber (reg:CC 33))]
5020 [(set_attr "op_type" "SI,SS")])
5024 ;;- Negate instructions.
5028 ; negdi2 instruction pattern(s).
5031 (define_expand "negdi2"
5033 [(set (match_operand:DI 0 "register_operand" "=d")
5034 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5035 (clobber (reg:CC 33))])]
5039 (define_insn "*negdi2_64"
5040 [(set (match_operand:DI 0 "register_operand" "=d")
5041 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5042 (clobber (reg:CC 33))]
5045 [(set_attr "op_type" "RR")])
5047 (define_insn "*negdi2_31"
5048 [(set (match_operand:DI 0 "register_operand" "=d")
5049 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5050 (clobber (reg:CC 33))]
5055 xop[0] = gen_label_rtx ();
5056 output_asm_insn (\"lcr\\t%0,%1\", operands);
5057 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5058 output_asm_insn (\"je\\t%l0\", xop);
5059 output_asm_insn (\"bctr\\t%0,0\", operands);
5060 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5061 CODE_LABEL_NUMBER (xop[0]));
5064 [(set_attr "op_type" "NN")
5065 (set_attr "type" "other")
5066 (set_attr "length" "10")])
5069 ; negsi2 instruction pattern(s).
5072 (define_insn "negsi2"
5073 [(set (match_operand:SI 0 "register_operand" "=d")
5074 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5075 (clobber (reg:CC 33))]
5078 [(set_attr "op_type" "RR")])
5081 ; negdf2 instruction pattern(s).
5084 (define_expand "negdf2"
5086 [(set (match_operand:DF 0 "register_operand" "=f")
5087 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5088 (clobber (reg:CC 33))])]
5092 (define_insn "*negdf2"
5093 [(set (match_operand:DF 0 "register_operand" "=f")
5094 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5095 (clobber (reg:CC 33))]
5096 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5098 [(set_attr "op_type" "RRE")
5099 (set_attr "type" "fsimpd")])
5101 (define_insn "*negdf2_ibm"
5102 [(set (match_operand:DF 0 "register_operand" "=f")
5103 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5104 (clobber (reg:CC 33))]
5105 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5107 [(set_attr "op_type" "RR")
5108 (set_attr "type" "fsimpd")])
5111 ; negsf2 instruction pattern(s).
5114 (define_expand "negsf2"
5116 [(set (match_operand:SF 0 "register_operand" "=f")
5117 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5118 (clobber (reg:CC 33))])]
5122 (define_insn "*negsf2"
5123 [(set (match_operand:SF 0 "register_operand" "=f")
5124 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5125 (clobber (reg:CC 33))]
5126 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5128 [(set_attr "op_type" "RRE")
5129 (set_attr "type" "fsimps")])
5131 (define_insn "*negsf2"
5132 [(set (match_operand:SF 0 "register_operand" "=f")
5133 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5134 (clobber (reg:CC 33))]
5135 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5137 [(set_attr "op_type" "RR")
5138 (set_attr "type" "fsimps")])
5142 ;;- Absolute value instructions.
5146 ; absdi2 instruction pattern(s).
5149 (define_insn "absdi2"
5150 [(set (match_operand:DI 0 "register_operand" "=d")
5151 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5152 (clobber (reg:CC 33))]
5155 [(set_attr "op_type" "RRE")])
5158 ; abssi2 instruction pattern(s).
5161 (define_insn "abssi2"
5162 [(set (match_operand:SI 0 "register_operand" "=d")
5163 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5164 (clobber (reg:CC 33))]
5167 [(set_attr "op_type" "RR")])
5170 ; absdf2 instruction pattern(s).
5173 (define_expand "absdf2"
5175 [(set (match_operand:DF 0 "register_operand" "=f")
5176 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5177 (clobber (reg:CC 33))])]
5181 (define_insn "*absdf2"
5182 [(set (match_operand:DF 0 "register_operand" "=f")
5183 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5184 (clobber (reg:CC 33))]
5185 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5187 [(set_attr "op_type" "RRE")
5188 (set_attr "type" "fsimpd")])
5190 (define_insn "*absdf2_ibm"
5191 [(set (match_operand:DF 0 "register_operand" "=f")
5192 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5193 (clobber (reg:CC 33))]
5194 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5196 [(set_attr "op_type" "RR")
5197 (set_attr "type" "fsimpd")])
5200 ; abssf2 instruction pattern(s).
5203 (define_expand "abssf2"
5205 [(set (match_operand:SF 0 "register_operand" "=f")
5206 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5207 (clobber (reg:CC 33))])]
5211 (define_insn "*abssf2"
5212 [(set (match_operand:SF 0 "register_operand" "=f")
5213 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5214 (clobber (reg:CC 33))]
5215 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5217 [(set_attr "op_type" "RRE")
5218 (set_attr "type" "fsimps")])
5220 (define_insn "*abssf2_ibm"
5221 [(set (match_operand:SF 0 "register_operand" "=f")
5222 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5223 (clobber (reg:CC 33))]
5224 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5226 [(set_attr "op_type" "RR")
5227 (set_attr "type" "fsimps")])
5230 ;;- Square root instructions.
5234 ; sqrtdf2 instruction pattern(s).
5237 (define_insn "sqrtdf2"
5238 [(set (match_operand:DF 0 "register_operand" "=f,f")
5239 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5240 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5244 [(set_attr "op_type" "RRE,RSE")
5245 (set_attr "type" "fsqrtd")])
5248 ; sqrtsf2 instruction pattern(s).
5251 (define_insn "sqrtsf2"
5252 [(set (match_operand:SF 0 "register_operand" "=f,f")
5253 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5254 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5258 [(set_attr "op_type" "RRE,RSE")
5259 (set_attr "type" "fsqrts")])
5262 ;;- One complement instructions.
5266 ; one_cmpldi2 instruction pattern(s).
5269 (define_expand "one_cmpldi2"
5271 [(set (match_operand:DI 0 "register_operand" "")
5272 (xor:DI (match_operand:DI 1 "register_operand" "")
5274 (clobber (reg:CC 33))])]
5279 ; one_cmplsi2 instruction pattern(s).
5282 (define_expand "one_cmplsi2"
5284 [(set (match_operand:SI 0 "register_operand" "")
5285 (xor:SI (match_operand:SI 1 "register_operand" "")
5287 (clobber (reg:CC 33))])]
5292 ; one_cmplhi2 instruction pattern(s).
5295 (define_expand "one_cmplhi2"
5297 [(set (match_operand:HI 0 "register_operand" "")
5298 (xor:HI (match_operand:HI 1 "register_operand" "")
5300 (clobber (reg:CC 33))])]
5305 ; one_cmplqi2 instruction pattern(s).
5308 (define_expand "one_cmplqi2"
5310 [(set (match_operand:QI 0 "register_operand" "")
5311 (xor:QI (match_operand:QI 1 "register_operand" "")
5313 (clobber (reg:CC 33))])]
5319 ;;- Rotate instructions.
5323 ; rotldi3 instruction pattern(s).
5326 (define_insn "rotldi3"
5327 [(set (match_operand:DI 0 "register_operand" "=d,d")
5328 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5329 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5334 [(set_attr "op_type" "RSE")
5335 (set_attr "atype" "reg")])
5338 ; rotlsi3 instruction pattern(s).
5341 (define_insn "rotlsi3"
5342 [(set (match_operand:SI 0 "register_operand" "=d,d")
5343 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5344 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5349 [(set_attr "op_type" "RSE")
5350 (set_attr "atype" "reg")])
5354 ;;- Arithmetic shift instructions.
5358 ; ashldi3 instruction pattern(s).
5361 (define_expand "ashldi3"
5362 [(set (match_operand:DI 0 "register_operand" "")
5363 (ashift:DI (match_operand:DI 1 "register_operand" "")
5364 (match_operand:SI 2 "nonmemory_operand" "")))]
5368 (define_insn "*ashldi3_31"
5369 [(set (match_operand:DI 0 "register_operand" "=d,d")
5370 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5371 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5376 [(set_attr "op_type" "RS")
5377 (set_attr "atype" "reg")])
5379 (define_insn "*ashldi3_64"
5380 [(set (match_operand:DI 0 "register_operand" "=d,d")
5381 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5382 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5387 [(set_attr "op_type" "RSE")
5388 (set_attr "atype" "reg")])
5391 ; ashrdi3 instruction pattern(s).
5394 (define_expand "ashrdi3"
5396 [(set (match_operand:DI 0 "register_operand" "")
5397 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5398 (match_operand:SI 2 "nonmemory_operand" "")))
5399 (clobber (reg:CC 33))])]
5403 (define_insn "*ashrdi3_cc_31"
5405 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5406 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5408 (set (match_operand:DI 0 "register_operand" "=d,d")
5409 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5410 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5414 [(set_attr "op_type" "RS")
5415 (set_attr "atype" "reg")])
5417 (define_insn "*ashrdi3_cconly_31"
5419 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5420 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5422 (clobber (match_scratch:DI 0 "=d,d"))]
5423 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5427 [(set_attr "op_type" "RS")
5428 (set_attr "atype" "reg")])
5430 (define_insn "*ashrdi3_31"
5431 [(set (match_operand:DI 0 "register_operand" "=d,d")
5432 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5433 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5434 (clobber (reg:CC 33))]
5439 [(set_attr "op_type" "RS")
5440 (set_attr "atype" "reg")])
5442 (define_insn "*ashrdi3_cc_64"
5444 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5445 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5447 (set (match_operand:DI 0 "register_operand" "=d,d")
5448 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5449 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5453 [(set_attr "op_type" "RSE")
5454 (set_attr "atype" "reg")])
5456 (define_insn "*ashrdi3_cconly_64"
5458 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5459 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5461 (clobber (match_scratch:DI 0 "=d,d"))]
5462 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5466 [(set_attr "op_type" "RSE")
5467 (set_attr "atype" "reg")])
5469 (define_insn "*ashrdi3_64"
5470 [(set (match_operand:DI 0 "register_operand" "=d,d")
5471 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5472 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5473 (clobber (reg:CC 33))]
5478 [(set_attr "op_type" "RSE")
5479 (set_attr "atype" "reg")])
5483 ; ashlsi3 instruction pattern(s).
5486 (define_insn "ashlsi3"
5487 [(set (match_operand:SI 0 "register_operand" "=d,d")
5488 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5489 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5494 [(set_attr "op_type" "RS")
5495 (set_attr "atype" "reg")])
5498 ; ashrsi3 instruction pattern(s).
5501 (define_insn "*ashrsi3_cc"
5503 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5504 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5506 (set (match_operand:SI 0 "register_operand" "=d,d")
5507 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5508 "s390_match_ccmode(insn, CCSmode)"
5512 [(set_attr "op_type" "RS")
5513 (set_attr "atype" "reg")])
5516 (define_insn "*ashrsi3_cconly"
5518 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5519 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5521 (clobber (match_scratch:SI 0 "=d,d"))]
5522 "s390_match_ccmode(insn, CCSmode)"
5526 [(set_attr "op_type" "RS")
5527 (set_attr "atype" "reg")])
5529 (define_insn "ashrsi3"
5530 [(set (match_operand:SI 0 "register_operand" "=d,d")
5531 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5532 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5533 (clobber (reg:CC 33))]
5538 [(set_attr "op_type" "RS")
5539 (set_attr "atype" "reg")])
5543 ;;- logical shift instructions.
5547 ; lshrdi3 instruction pattern(s).
5550 (define_expand "lshrdi3"
5551 [(set (match_operand:DI 0 "register_operand" "")
5552 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5553 (match_operand:SI 2 "nonmemory_operand" "")))]
5557 (define_insn "*lshrdi3_31"
5558 [(set (match_operand:DI 0 "register_operand" "=d,d")
5559 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5560 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5565 [(set_attr "op_type" "RS,RS")
5566 (set_attr "atype" "reg")])
5568 (define_insn "*lshrdi3_64"
5569 [(set (match_operand:DI 0 "register_operand" "=d,d")
5570 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5571 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5576 [(set_attr "op_type" "RSE,RSE")
5577 (set_attr "atype" "reg")])
5580 ; lshrsi3 instruction pattern(s).
5583 (define_insn "lshrsi3"
5584 [(set (match_operand:SI 0 "register_operand" "=d,d")
5585 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5586 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5591 [(set_attr "op_type" "RS")
5592 (set_attr "atype" "reg")])
5596 ;; Branch instruction patterns.
5599 (define_expand "beq"
5600 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5602 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5603 (label_ref (match_operand 0 "" ""))
5606 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5608 (define_expand "bne"
5609 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5611 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5612 (label_ref (match_operand 0 "" ""))
5615 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5617 (define_expand "bgt"
5618 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5620 (if_then_else (gt (reg:CCS 33) (const_int 0))
5621 (label_ref (match_operand 0 "" ""))
5624 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5626 (define_expand "bgtu"
5627 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5629 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5630 (label_ref (match_operand 0 "" ""))
5633 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5635 (define_expand "blt"
5636 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5638 (if_then_else (lt (reg:CCS 33) (const_int 0))
5639 (label_ref (match_operand 0 "" ""))
5642 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5644 (define_expand "bltu"
5645 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5647 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5648 (label_ref (match_operand 0 "" ""))
5651 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5653 (define_expand "bge"
5654 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5656 (if_then_else (ge (reg:CCS 33) (const_int 0))
5657 (label_ref (match_operand 0 "" ""))
5660 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5662 (define_expand "bgeu"
5663 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5665 (if_then_else (geu (reg:CCU 33) (const_int 0))
5666 (label_ref (match_operand 0 "" ""))
5669 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5671 (define_expand "ble"
5672 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5674 (if_then_else (le (reg:CCS 33) (const_int 0))
5675 (label_ref (match_operand 0 "" ""))
5678 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5680 (define_expand "bleu"
5681 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5683 (if_then_else (leu (reg:CCU 33) (const_int 0))
5684 (label_ref (match_operand 0 "" ""))
5687 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5689 (define_expand "bunordered"
5690 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5692 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5693 (label_ref (match_operand 0 "" ""))
5696 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5698 (define_expand "bordered"
5699 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5701 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5702 (label_ref (match_operand 0 "" ""))
5705 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5707 (define_expand "buneq"
5708 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5710 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5711 (label_ref (match_operand 0 "" ""))
5714 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5716 (define_expand "bungt"
5717 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5719 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5720 (label_ref (match_operand 0 "" ""))
5723 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5725 (define_expand "bunlt"
5726 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5728 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5729 (label_ref (match_operand 0 "" ""))
5732 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5734 (define_expand "bunge"
5735 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5737 (if_then_else (unge (reg:CCS 33) (const_int 0))
5738 (label_ref (match_operand 0 "" ""))
5741 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5743 (define_expand "bunle"
5744 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5746 (if_then_else (unle (reg:CCS 33) (const_int 0))
5747 (label_ref (match_operand 0 "" ""))
5750 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5752 (define_expand "bltgt"
5753 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5755 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5756 (label_ref (match_operand 0 "" ""))
5759 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5763 ;;- Conditional jump instructions.
5766 (define_insn "cjump"
5769 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5770 (label_ref (match_operand 0 "" ""))
5775 if (get_attr_length (insn) == 4)
5776 return \"j%C1\\t%l0\";
5777 else if (TARGET_64BIT)
5778 return \"jg%C1\\t%l0\";
5782 [(set_attr "op_type" "RI")
5783 (set_attr "type" "branch")
5784 (set (attr "length")
5785 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5787 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5789 (eq (symbol_ref "flag_pic") (const_int 0))
5790 (const_int 6)] (const_int 8)))])
5792 (define_insn "*cjump_long"
5795 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5796 (match_operand 0 "address_operand" "p")
5801 if (get_attr_op_type (insn) == OP_TYPE_RR)
5802 return \"b%C1r\\t%0\";
5804 return \"b%C1\\t%a0\";
5806 [(set (attr "op_type")
5807 (if_then_else (match_operand 0 "register_operand" "")
5808 (const_string "RR") (const_string "RX")))
5809 (set_attr "type" "branch")
5810 (set_attr "atype" "agen")])
5814 ;;- Negated conditional jump instructions.
5817 (define_insn "icjump"
5820 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5822 (label_ref (match_operand 0 "" ""))))]
5826 if (get_attr_length (insn) == 4)
5827 return \"j%D1\\t%l0\";
5828 else if (TARGET_64BIT)
5829 return \"jg%D1\\t%l0\";
5833 [(set_attr "op_type" "RI")
5834 (set_attr "type" "branch")
5835 (set (attr "length")
5836 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5838 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5840 (eq (symbol_ref "flag_pic") (const_int 0))
5841 (const_int 6)] (const_int 8)))])
5843 (define_insn "*icjump_long"
5846 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5848 (match_operand 0 "address_operand" "p")))]
5852 if (get_attr_op_type (insn) == OP_TYPE_RR)
5853 return \"b%D1r\\t%0\";
5855 return \"b%D1\\t%a0\";
5857 [(set (attr "op_type")
5858 (if_then_else (match_operand 0 "register_operand" "")
5859 (const_string "RR") (const_string "RX")))
5860 (set_attr "type" "branch")
5861 (set_attr "atype" "agen")])
5864 ;;- Trap instructions.
5868 [(trap_if (const_int 1) (const_int 0))]
5871 [(set_attr "op_type" "RX")
5872 (set_attr "type" "branch")])
5874 (define_expand "conditional_trap"
5875 [(set (match_dup 2) (match_dup 3))
5876 (trap_if (match_operator 0 "comparison_operator"
5877 [(match_dup 2) (const_int 0)])
5878 (match_operand:SI 1 "general_operand" ""))]
5882 enum machine_mode ccmode;
5884 if (operands[1] != const0_rtx) FAIL;
5886 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5887 s390_compare_op0, s390_compare_op1);
5888 operands[2] = gen_rtx_REG (ccmode, 33);
5889 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5892 (define_insn "*trap"
5893 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5897 [(set_attr "op_type" "RI")
5898 (set_attr "type" "branch")])
5901 ;;- Loop instructions.
5903 ;; This is all complicated by the fact that since this is a jump insn
5904 ;; we must handle our own output reloads.
5906 (define_expand "doloop_end"
5907 [(use (match_operand 0 "" "")) ; loop pseudo
5908 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5909 (use (match_operand 2 "" "")) ; max iterations
5910 (use (match_operand 3 "" "")) ; loop level
5911 (use (match_operand 4 "" ""))] ; label
5915 if (GET_MODE (operands[0]) == SImode)
5916 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5917 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5918 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5925 (define_insn "doloop_si"
5928 (ne (match_operand:SI 1 "register_operand" "d,d")
5930 (label_ref (match_operand 0 "" ""))
5932 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5933 (plus:SI (match_dup 1) (const_int -1)))
5934 (clobber (match_scratch:SI 3 "=X,&d"))
5935 (clobber (reg:CC 33))]
5939 if (which_alternative != 0)
5941 else if (get_attr_length (insn) == 4)
5942 return \"brct\\t%1,%l0\";
5946 [(set_attr "op_type" "RI")
5947 (set_attr "type" "branch")
5948 (set (attr "length")
5949 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5951 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5953 (eq (symbol_ref "flag_pic") (const_int 0))
5954 (const_int 6)] (const_int 8)))])
5956 (define_insn "*doloop_si_long"
5959 (ne (match_operand:SI 1 "register_operand" "d,d")
5961 (match_operand 0 "address_operand" "p,p")
5963 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5964 (plus:SI (match_dup 1) (const_int -1)))
5965 (clobber (match_scratch:SI 3 "=X,&d"))
5966 (clobber (reg:CC 33))]
5970 if (get_attr_op_type (insn) == OP_TYPE_RR)
5971 return \"bctr\\t%1,%0\";
5973 return \"bct\\t%1,%a0\";
5975 [(set (attr "op_type")
5976 (if_then_else (match_operand 0 "register_operand" "")
5977 (const_string "RR") (const_string "RX")))
5978 (set_attr "type" "branch")
5979 (set_attr "atype" "agen")])
5983 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
5985 (match_operand 0 "" "")
5987 (set (match_operand:SI 2 "nonimmediate_operand" "")
5988 (plus:SI (match_dup 1) (const_int -1)))
5989 (clobber (match_scratch:SI 3 ""))
5990 (clobber (reg:CC 33))]
5992 && (! REG_P (operands[2])
5993 || ! rtx_equal_p (operands[1], operands[2]))"
5994 [(set (match_dup 3) (match_dup 1))
5995 (parallel [(set (reg:CCAN 33)
5996 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
5998 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
5999 (set (match_dup 2) (match_dup 3))
6000 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6005 (define_insn "doloop_di"
6008 (ne (match_operand:DI 1 "register_operand" "d,d")
6010 (label_ref (match_operand 0 "" ""))
6012 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
6013 (plus:DI (match_dup 1) (const_int -1)))
6014 (clobber (match_scratch:DI 3 "=X,&d"))
6015 (clobber (reg:CC 33))]
6019 if (which_alternative != 0)
6021 else if (get_attr_length (insn) == 4)
6022 return \"brctg\\t%1,%l0\";
6026 [(set_attr "op_type" "RI")
6027 (set_attr "type" "branch")
6028 (set (attr "length")
6029 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6030 (const_int 4) (const_int 12)))])
6032 (define_insn "*doloop_di_long"
6035 (ne (match_operand:DI 1 "register_operand" "d,d")
6037 (match_operand 0 "address_operand" "p,p")
6039 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
6040 (plus:DI (match_dup 1) (const_int -1)))
6041 (clobber (match_scratch:DI 3 "=X,&d"))
6042 (clobber (reg:CC 33))]
6046 if (get_attr_op_type (insn) == OP_TYPE_RRE)
6047 return \"bctgr\\t%1,%0\";
6049 return \"bctg\\t%1,%a0\";
6051 [(set (attr "op_type")
6052 (if_then_else (match_operand 0 "register_operand" "")
6053 (const_string "RRE") (const_string "RXE")))
6054 (set_attr "type" "branch")
6055 (set_attr "atype" "agen")])
6059 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
6061 (match_operand 0 "" "")
6063 (set (match_operand:DI 2 "nonimmediate_operand" "")
6064 (plus:DI (match_dup 1) (const_int -1)))
6065 (clobber (match_scratch:DI 3 ""))
6066 (clobber (reg:CC 33))]
6068 && (! REG_P (operands[2])
6069 || ! rtx_equal_p (operands[1], operands[2]))"
6070 [(set (match_dup 3) (match_dup 1))
6071 (parallel [(set (reg:CCAN 33)
6072 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6074 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6075 (set (match_dup 2) (match_dup 3))
6076 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6082 ;;- Unconditional jump instructions.
6086 ; jump instruction pattern(s).
6090 [(set (pc) (label_ref (match_operand 0 "" "")))]
6094 if (get_attr_length (insn) == 4)
6096 else if (TARGET_64BIT)
6097 return \"jg\\t%l0\";
6101 [(set_attr "op_type" "RI")
6102 (set_attr "type" "branch")
6103 (set (attr "length")
6104 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6106 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6108 (eq (symbol_ref "flag_pic") (const_int 0))
6109 (const_int 6)] (const_int 8)))])
6112 ; indirect-jump instruction pattern(s).
6115 (define_insn "indirect_jump"
6116 [(set (pc) (match_operand 0 "address_operand" "p"))]
6120 if (get_attr_op_type (insn) == OP_TYPE_RR)
6125 [(set (attr "op_type")
6126 (if_then_else (match_operand 0 "register_operand" "")
6127 (const_string "RR") (const_string "RX")))
6128 (set_attr "type" "branch")
6129 (set_attr "atype" "agen")])
6132 ; casesi instruction pattern(s).
6135 (define_insn "casesi_jump"
6136 [(set (pc) (match_operand 0 "address_operand" "p"))
6137 (use (label_ref (match_operand 1 "" "")))]
6141 if (get_attr_op_type (insn) == OP_TYPE_RR)
6146 [(set (attr "op_type")
6147 (if_then_else (match_operand 0 "register_operand" "")
6148 (const_string "RR") (const_string "RX")))
6149 (set_attr "type" "branch")
6150 (set_attr "atype" "agen")])
6152 (define_expand "casesi"
6153 [(match_operand:SI 0 "general_operand" "")
6154 (match_operand:SI 1 "general_operand" "")
6155 (match_operand:SI 2 "general_operand" "")
6156 (label_ref (match_operand 3 "" ""))
6157 (label_ref (match_operand 4 "" ""))]
6161 rtx index = gen_reg_rtx (SImode);
6162 rtx base = gen_reg_rtx (Pmode);
6163 rtx target = gen_reg_rtx (Pmode);
6165 emit_move_insn (index, operands[0]);
6166 emit_insn (gen_subsi3 (index, index, operands[1]));
6167 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6170 if (Pmode != SImode)
6171 index = convert_to_mode (Pmode, index, 1);
6172 if (GET_CODE (index) != REG)
6173 index = copy_to_mode_reg (Pmode, index);
6176 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6178 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6180 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6182 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6183 emit_move_insn (target, index);
6186 target = gen_rtx_PLUS (Pmode, base, target);
6187 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6194 ;;- Jump to subroutine.
6199 ; untyped call instruction pattern(s).
6202 ;; Call subroutine returning any type.
6203 (define_expand "untyped_call"
6204 [(parallel [(call (match_operand 0 "" "")
6206 (match_operand 1 "" "")
6207 (match_operand 2 "" "")])]
6213 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6215 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6217 rtx set = XVECEXP (operands[2], 0, i);
6218 emit_move_insn (SET_DEST (set), SET_SRC (set));
6221 /* The optimizer does not know that the call sets the function value
6222 registers we stored in the result block. We avoid problems by
6223 claiming that all hard registers are used and clobbered at this
6225 emit_insn (gen_blockage ());
6230 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6231 ;; all of memory. This blocks insns from being moved across this point.
6233 (define_insn "blockage"
6234 [(unspec_volatile [(const_int 0)] 0)]
6237 [(set_attr "type" "none")
6238 (set_attr "length" "0")])
6243 ; call instruction pattern(s).
6246 (define_expand "call"
6247 [(call (match_operand 0 "" "")
6248 (match_operand 1 "" ""))
6249 (use (match_operand 2 "" ""))]
6256 /* Direct function calls need special treatment. */
6257 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6259 rtx sym = XEXP (operands[0], 0);
6261 /* When calling a global routine in PIC mode, we must
6262 replace the symbol itself with the PLT stub. */
6263 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6265 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6266 sym = gen_rtx_CONST (Pmode, sym);
6271 /* Unless we can use the bras(l) insn, force the
6272 routine address into a register. */
6273 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6275 rtx target = gen_reg_rtx (Pmode);
6276 emit_move_insn (target, sym);
6280 operands[0] = gen_rtx_MEM (QImode, sym);
6284 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6285 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6287 /* In 31-bit, we must load the GOT register even if the
6288 compiler doesn't know about it, because the PLT glue
6289 code uses it. In 64-bit, this is not necessary. */
6290 if (plt_call && !TARGET_64BIT)
6291 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6296 (define_expand "call_exp"
6297 [(parallel [(call (match_operand 0 "" "")
6298 (match_operand 1 "" ""))
6299 (clobber (match_operand 2 "" ""))])]
6303 (define_insn "brasl"
6304 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6305 (match_operand:SI 1 "const_int_operand" "n"))
6306 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6309 [(set_attr "op_type" "RIL")
6310 (set_attr "type" "jsr")])
6313 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6314 (match_operand:SI 1 "const_int_operand" "n"))
6315 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6318 [(set_attr "op_type" "RI")
6319 (set_attr "type" "jsr")])
6321 (define_insn "basr_64"
6322 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6323 (match_operand:SI 1 "const_int_operand" "n"))
6324 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6327 [(set_attr "op_type" "RR")
6328 (set_attr "type" "jsr")
6329 (set_attr "atype" "agen")])
6331 (define_insn "basr_31"
6332 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6333 (match_operand:SI 1 "const_int_operand" "n"))
6334 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6337 [(set_attr "op_type" "RR")
6338 (set_attr "type" "jsr")
6339 (set_attr "atype" "agen")])
6341 (define_insn "bas_64"
6342 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6343 (match_operand:SI 1 "const_int_operand" "n"))
6344 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6347 [(set_attr "op_type" "RX")
6348 (set_attr "type" "jsr")])
6350 (define_insn "bas_31"
6351 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6352 (match_operand:SI 1 "const_int_operand" "n"))
6353 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6356 [(set_attr "op_type" "RX")
6357 (set_attr "type" "jsr")])
6361 ; call_value instruction pattern(s).
6364 (define_expand "call_value"
6365 [(set (match_operand 0 "" "")
6366 (call (match_operand 1 "" "")
6367 (match_operand 2 "" "")))
6368 (use (match_operand 3 "" ""))]
6375 /* Direct function calls need special treatment. */
6376 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6378 rtx sym = XEXP (operands[1], 0);
6380 /* When calling a global routine in PIC mode, we must
6381 replace the symbol itself with the PLT stub. */
6382 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6384 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6385 sym = gen_rtx_CONST (Pmode, sym);
6390 /* Unless we can use the bras(l) insn, force the
6391 routine address into a register. */
6392 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6394 rtx target = gen_reg_rtx (Pmode);
6395 emit_move_insn (target, sym);
6399 operands[1] = gen_rtx_MEM (QImode, sym);
6403 insn = emit_call_insn (
6404 gen_call_value_exp (operands[0], operands[1], operands[2],
6405 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6407 /* In 31-bit, we must load the GOT register even if the
6408 compiler doesn't know about it, because the PLT glue
6409 code uses it. In 64-bit, this is not necessary. */
6410 if (plt_call && !TARGET_64BIT)
6411 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6416 (define_expand "call_value_exp"
6417 [(parallel [(set (match_operand 0 "" "")
6418 (call (match_operand 1 "" "")
6419 (match_operand 2 "" "")))
6420 (clobber (match_operand 3 "" ""))])]
6424 (define_insn "brasl_r"
6425 [(set (match_operand 0 "register_operand" "=df")
6426 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6427 (match_operand:SI 2 "const_int_operand" "n")))
6428 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6431 [(set_attr "op_type" "RIL")
6432 (set_attr "type" "jsr")])
6434 (define_insn "bras_r"
6435 [(set (match_operand 0 "register_operand" "=df")
6436 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6437 (match_operand:SI 2 "const_int_operand" "n")))
6438 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6441 [(set_attr "op_type" "RI")
6442 (set_attr "type" "jsr")])
6444 (define_insn "basr_r_64"
6445 [(set (match_operand 0 "register_operand" "=df")
6446 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6447 (match_operand:SI 2 "const_int_operand" "n")))
6448 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6451 [(set_attr "op_type" "RR")
6452 (set_attr "type" "jsr")
6453 (set_attr "atype" "agen")])
6455 (define_insn "basr_r_31"
6456 [(set (match_operand 0 "register_operand" "=df")
6457 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6458 (match_operand:SI 2 "const_int_operand" "n")))
6459 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6462 [(set_attr "op_type" "RR")
6463 (set_attr "type" "jsr")
6464 (set_attr "atype" "agen")])
6466 (define_insn "bas_r_64"
6467 [(set (match_operand 0 "register_operand" "=df")
6468 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6469 (match_operand:SI 2 "const_int_operand" "n")))
6470 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6473 [(set_attr "op_type" "RX")
6474 (set_attr "type" "jsr")])
6476 (define_insn "bas_r_31"
6477 [(set (match_operand 0 "register_operand" "=df")
6478 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6479 (match_operand:SI 2 "const_int_operand" "n")))
6480 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6483 [(set_attr "op_type" "RX")
6484 (set_attr "type" "jsr")])
6488 ;;- Thread-local storage support.
6491 (define_insn "get_tp_64"
6492 [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q")
6493 (unspec:DI [(const_int 0)] UNSPEC_TP))]
6496 ear\\t%0,%%a0\;sllg\\t%0,%0,32\;ear\\t%0,%%a1
6497 stam\\t%%a0,%%a1,%0"
6498 [(set_attr "op_type" "NN,RS")
6499 (set_attr "atype" "reg,*")
6500 (set_attr "type" "o3,*")
6501 (set_attr "length" "14,*")])
6503 (define_insn "get_tp_31"
6504 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q")
6505 (unspec:SI [(const_int 0)] UNSPEC_TP))]
6509 stam\\t%%a0,%%a0,%0"
6510 [(set_attr "op_type" "RRE,RS")])
6512 (define_insn "set_tp_64"
6513 [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP)
6514 (clobber (match_scratch:SI 1 "=d,X"))]
6517 sar\\t%%a1,%0\;srlg\\t%1,%0,32\;sar\\t%%a0,%1
6519 [(set_attr "op_type" "NN,RS")
6520 (set_attr "atype" "reg,*")
6521 (set_attr "type" "o3,*")
6522 (set_attr "length" "14,*")])
6524 (define_insn "set_tp_31"
6525 [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)]
6530 [(set_attr "op_type" "RRE,RS")])
6532 (define_insn "*tls_load_64"
6533 [(set (match_operand:DI 0 "register_operand" "=d")
6534 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6535 (match_operand:DI 2 "" "")]
6539 [(set_attr "op_type" "RXE")])
6541 (define_insn "*tls_load_31"
6542 [(set (match_operand:SI 0 "register_operand" "=d")
6543 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
6544 (match_operand:SI 2 "" "")]
6548 [(set_attr "op_type" "RX")])
6550 (define_expand "call_value_tls"
6551 [(set (match_operand 0 "" "")
6552 (call (const_int 0) (const_int 0)))
6553 (use (match_operand 1 "" ""))]
6562 sym = s390_tls_get_offset ();
6563 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6564 sym = gen_rtx_CONST (Pmode, sym);
6566 /* Unless we can use the bras(l) insn, force the
6567 routine address into a register. */
6568 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6570 rtx target = gen_reg_rtx (Pmode);
6571 emit_move_insn (target, sym);
6575 sym = gen_rtx_MEM (QImode, sym);
6578 insn = emit_call_insn (
6579 gen_call_value_tls_exp (operands[0], sym, const0_rtx,
6580 gen_rtx_REG (Pmode, RETURN_REGNUM),
6583 /* The calling convention of __tls_get_offset uses the
6584 GOT register implicitly. */
6585 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6586 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]);
6587 CONST_OR_PURE_CALL_P (insn) = 1;
6592 (define_expand "call_value_tls_exp"
6593 [(parallel [(set (match_operand 0 "" "")
6594 (call (match_operand 1 "" "")
6595 (match_operand 2 "" "")))
6596 (clobber (match_operand 3 "" ""))
6597 (use (match_operand 4 "" ""))])]
6601 (define_insn "brasl_tls"
6602 [(set (match_operand 0 "register_operand" "=df")
6603 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6604 (match_operand:SI 2 "const_int_operand" "n")))
6605 (clobber (match_operand:DI 3 "register_operand" "=r"))
6606 (use (match_operand:DI 4 "" ""))]
6609 [(set_attr "op_type" "RIL")
6610 (set_attr "type" "jsr")])
6612 (define_insn "bras_tls"
6613 [(set (match_operand 0 "register_operand" "=df")
6614 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6615 (match_operand:SI 2 "const_int_operand" "n")))
6616 (clobber (match_operand:SI 3 "register_operand" "=r"))
6617 (use (match_operand:SI 4 "" ""))]
6620 [(set_attr "op_type" "RI")
6621 (set_attr "type" "jsr")])
6623 (define_insn "basr_tls_64"
6624 [(set (match_operand 0 "register_operand" "=df")
6625 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6626 (match_operand:SI 2 "const_int_operand" "n")))
6627 (clobber (match_operand:DI 3 "register_operand" "=r"))
6628 (use (match_operand:DI 4 "" ""))]
6631 [(set_attr "op_type" "RR")
6632 (set_attr "type" "jsr")])
6634 (define_insn "basr_tls_31"
6635 [(set (match_operand 0 "register_operand" "=df")
6636 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6637 (match_operand:SI 2 "const_int_operand" "n")))
6638 (clobber (match_operand:SI 3 "register_operand" "=r"))
6639 (use (match_operand:SI 4 "" ""))]
6642 [(set_attr "op_type" "RR")
6643 (set_attr "type" "jsr")
6644 (set_attr "atype" "agen")])
6646 (define_insn "bas_tls_64"
6647 [(set (match_operand 0 "register_operand" "=df")
6648 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6649 (match_operand:SI 2 "const_int_operand" "n")))
6650 (clobber (match_operand:DI 3 "register_operand" "=r"))
6651 (use (match_operand:DI 4 "" ""))]
6654 [(set_attr "op_type" "RX")
6655 (set_attr "type" "jsr")
6656 (set_attr "atype" "agen")])
6658 (define_insn "bas_tls_31"
6659 [(set (match_operand 0 "register_operand" "=df")
6660 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6661 (match_operand:SI 2 "const_int_operand" "n")))
6662 (clobber (match_operand:SI 3 "register_operand" "=r"))
6663 (use (match_operand:SI 4 "" ""))]
6666 [(set_attr "op_type" "RX")
6667 (set_attr "type" "jsr")
6668 (set_attr "atype" "agen")])
6671 ;;- Miscellaneous instructions.
6675 ; allocate stack instruction pattern(s).
6678 (define_expand "allocate_stack"
6680 (plus (reg 15) (match_operand 1 "general_operand" "")))
6681 (set (match_operand 0 "general_operand" "")
6686 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6687 rtx chain = gen_rtx (MEM, Pmode, stack);
6688 rtx temp = gen_reg_rtx (Pmode);
6690 emit_move_insn (temp, chain);
6693 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6695 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6697 emit_move_insn (chain, temp);
6699 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6705 ; setjmp/longjmp instruction pattern(s).
6708 (define_expand "builtin_setjmp_setup"
6709 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6713 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6714 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6716 emit_move_insn (base, basereg);
6720 (define_expand "builtin_setjmp_receiver"
6721 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6725 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6726 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6727 SYMBOL_REF_FLAG (got) = 1;
6729 emit_move_insn (gotreg, got);
6730 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6734 (define_expand "builtin_longjmp"
6735 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6739 /* The elements of the buffer are, in order: */
6740 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6741 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6742 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6743 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6744 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6745 rtx jmp = gen_rtx_REG (Pmode, 14);
6747 emit_move_insn (jmp, lab);
6748 emit_move_insn (basereg, base);
6749 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6750 emit_move_insn (hard_frame_pointer_rtx, fp);
6752 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6753 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6754 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6755 emit_indirect_jump (jmp);
6760 ;; These patterns say how to save and restore the stack pointer. We need not
6761 ;; save the stack pointer at function level since we are careful to
6762 ;; preserve the backchain. At block level, we have to restore the backchain
6763 ;; when we restore the stack pointer.
6765 ;; For nonlocal gotos, we must save both the stack pointer and its
6766 ;; backchain and restore both. Note that in the nonlocal case, the
6767 ;; save area is a memory location.
6769 (define_expand "save_stack_function"
6770 [(match_operand 0 "general_operand" "")
6771 (match_operand 1 "general_operand" "")]
6775 (define_expand "restore_stack_function"
6776 [(match_operand 0 "general_operand" "")
6777 (match_operand 1 "general_operand" "")]
6781 (define_expand "restore_stack_block"
6782 [(use (match_operand 0 "register_operand" ""))
6783 (set (match_dup 2) (match_dup 3))
6784 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6785 (set (match_dup 3) (match_dup 2))]
6789 operands[2] = gen_reg_rtx (Pmode);
6790 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6793 (define_expand "save_stack_nonlocal"
6794 [(match_operand 0 "memory_operand" "")
6795 (match_operand 1 "register_operand" "")]
6799 rtx temp = gen_reg_rtx (Pmode);
6801 /* Copy the backchain to the first word, sp to the second. */
6802 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6803 emit_move_insn (operand_subword (operands[0], 0, 0,
6804 TARGET_64BIT ? TImode : DImode),
6806 emit_move_insn (operand_subword (operands[0], 1, 0,
6807 TARGET_64BIT ? TImode : DImode),
6812 (define_expand "restore_stack_nonlocal"
6813 [(match_operand 0 "register_operand" "")
6814 (match_operand 1 "memory_operand" "")]
6818 rtx temp = gen_reg_rtx (Pmode);
6820 /* Restore the backchain from the first word, sp from the second. */
6821 emit_move_insn (temp,
6822 operand_subword (operands[1], 0, 0,
6823 TARGET_64BIT ? TImode : DImode));
6824 emit_move_insn (operands[0],
6825 operand_subword (operands[1], 1, 0,
6826 TARGET_64BIT ? TImode : DImode));
6827 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6833 ; nop instruction pattern(s).
6840 [(set_attr "op_type" "RR")])
6844 ; Special literal pool access instruction pattern(s).
6847 (define_insn "consttable_qi"
6848 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6852 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6855 [(set_attr "op_type" "NN")
6856 (set_attr "length" "1")])
6858 (define_insn "consttable_hi"
6859 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6863 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6866 [(set_attr "op_type" "NN")
6867 (set_attr "length" "2")])
6869 (define_insn "consttable_si"
6870 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6874 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6875 return \".long\\t%0\";
6877 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6880 [(set_attr "op_type" "NN")
6881 (set_attr "length" "4")])
6883 (define_insn "consttable_di"
6884 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6888 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6891 [(set_attr "op_type" "NN")
6892 (set_attr "length" "8")])
6894 (define_insn "consttable_sf"
6895 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6901 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6904 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6905 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6908 [(set_attr "op_type" "NN")
6909 (set_attr "length" "4")])
6911 (define_insn "consttable_df"
6912 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6918 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6921 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6922 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6925 [(set_attr "op_type" "NN")
6926 (set_attr "length" "8")])
6928 (define_insn "pool_start_31"
6929 [(unspec_volatile [(const_int 0)] 206)]
6932 [(set_attr "op_type" "NN")
6933 (set_attr "length" "2")])
6935 (define_insn "pool_end_31"
6936 [(unspec_volatile [(const_int 0)] 207)]
6939 [(set_attr "op_type" "NN")
6940 (set_attr "length" "2")])
6942 (define_insn "pool_start_64"
6943 [(unspec_volatile [(const_int 0)] 206)]
6945 ".section\\t.rodata\;.align\\t8"
6946 [(set_attr "op_type" "NN")
6947 (set_attr "length" "0")])
6949 (define_insn "pool_end_64"
6950 [(unspec_volatile [(const_int 0)] 207)]
6953 [(set_attr "op_type" "NN")
6954 (set_attr "length" "0")])
6956 (define_insn "reload_base_31"
6957 [(set (match_operand:SI 0 "register_operand" "=a")
6958 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6960 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6961 [(set_attr "op_type" "NN")
6962 (set_attr "type" "la")
6963 (set_attr "length" "6")])
6965 (define_insn "reload_base_64"
6966 [(set (match_operand:DI 0 "register_operand" "=a")
6967 (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))]
6970 [(set_attr "op_type" "RIL")
6971 (set_attr "type" "larl")])
6973 (define_insn "reload_anchor"
6974 [(set (match_operand:SI 0 "register_operand" "=a")
6975 (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))]
6977 "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
6978 [(set_attr "op_type" "NN")
6979 (set_attr "type" "la")
6980 (set_attr "atype" "agen")
6981 (set_attr "length" "8")])
6984 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)]
6987 [(set_attr "op_type" "NN")
6988 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6991 ;; Insns related to generating the function prologue and epilogue.
6995 (define_expand "prologue"
6996 [(use (const_int 0))]
7000 s390_emit_prologue ();
7004 (define_expand "epilogue"
7005 [(use (const_int 1))]
7009 s390_emit_epilogue ();
7014 (define_insn "*return_si"
7016 (use (match_operand:SI 0 "register_operand" "a"))]
7019 [(set_attr "op_type" "RR")
7020 (set_attr "type" "jsr")
7021 (set_attr "atype" "agen")])
7023 (define_insn "*return_di"
7025 (use (match_operand:DI 0 "register_operand" "a"))]
7028 [(set_attr "op_type" "RR")
7029 (set_attr "type" "jsr")
7030 (set_attr "atype" "agen")])
7032 (define_insn "literal_pool_31"
7033 [(unspec_volatile [(const_int 0)] 300)
7034 (set (match_operand:SI 0 "register_operand" "=a")
7035 (label_ref (match_operand 1 "" "")))
7036 (use (label_ref (match_operand 2 "" "")))]
7040 if (s390_nr_constants) {
7041 output_asm_insn (\"bras\\t%0,%2\", operands);
7042 s390_output_constant_pool (operands[1], operands[2]);
7046 [(set_attr "op_type" "NN")
7047 (set_attr "type" "larl")])
7049 (define_insn "literal_pool_64"
7050 [(unspec_volatile [(const_int 0)] 300)
7051 (set (match_operand:DI 0 "register_operand" "=a")
7052 (label_ref (match_operand 1 "" "")))
7053 (use (label_ref (match_operand 2 "" "")))]
7057 if (s390_nr_constants) {
7058 output_asm_insn (\"larl\\t%0,%1\", operands);
7059 s390_output_constant_pool (operands[1], operands[2]);
7063 [(set_attr "op_type" "NN")
7064 (set_attr "type" "larl")])