1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 typedef struct reg_stat_struct
{
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label
;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 DEF_VEC_O(reg_stat_type
);
256 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
258 static VEC(reg_stat_type
,heap
) *reg_stat
;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set
;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid
;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn
;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid
;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs
;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn
;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block
;
300 static bool optimize_this_for_speed_p
;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known
;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost
;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx
*uid_log_links
;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick
;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start
;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode
;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid
;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
};
351 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
352 union { rtx
*r
; int *i
; } where
;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf
;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences
;
375 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
377 unsigned HOST_WIDE_INT
,
378 unsigned HOST_WIDE_INT
*);
379 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx
*, rtx
);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx
);
386 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
387 static int cant_combine_insn_p (rtx
);
388 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
389 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
390 static int contains_muldiv (rtx
);
391 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx
*find_split_point (rtx
*, rtx
, bool);
395 static rtx
subst (rtx
, rtx
, rtx
, int, int);
396 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
397 static rtx
simplify_if_then_else (rtx
);
398 static rtx
simplify_set (rtx
);
399 static rtx
simplify_logical (rtx
);
400 static rtx
expand_compound_operation (rtx
);
401 static const_rtx
expand_field_assignment (const_rtx
);
402 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
403 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
404 static rtx
extract_left_shift (rtx
, int);
405 static rtx
make_compound_operation (rtx
, enum rtx_code
);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
407 unsigned HOST_WIDE_INT
*);
408 static rtx
canon_reg_for_combine (rtx
, rtx
);
409 static rtx
force_to_mode (rtx
, enum machine_mode
,
410 unsigned HOST_WIDE_INT
, int);
411 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
412 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
413 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
414 static rtx
make_field_assignment (rtx
);
415 static rtx
apply_distributive_law (rtx
);
416 static rtx
distribute_and_simplify_rtx (rtx
, int);
417 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
418 unsigned HOST_WIDE_INT
);
419 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
420 unsigned HOST_WIDE_INT
);
421 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
422 HOST_WIDE_INT
, enum machine_mode
, int *);
423 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
424 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
426 static int recog_for_combine (rtx
*, rtx
, rtx
*);
427 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
428 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
429 static void update_table_tick (rtx
);
430 static void record_value_for_reg (rtx
, rtx
, rtx
);
431 static void check_promoted_subreg (rtx
, rtx
);
432 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
433 static void record_dead_and_set_regs (rtx
);
434 static int get_last_value_validate (rtx
*, rtx
, int, int);
435 static rtx
get_last_value (const_rtx
);
436 static int use_crosses_set_p (const_rtx
, int);
437 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
438 static int reg_dead_at_p (rtx
, rtx
);
439 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
440 static int reg_bitfield_target_p (rtx
, rtx
);
441 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
442 static void distribute_links (rtx
);
443 static void mark_used_regs_combine (rtx
);
444 static void record_promoted_value (rtx
, rtx
);
445 static int unmentioned_reg_p_1 (rtx
*, void *);
446 static bool unmentioned_reg_p (rtx
, rtx
);
447 static int record_truncated_value (rtx
*, void *);
448 static void record_truncated_values (rtx
*, void *);
449 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
450 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern
, rtx insn
)
486 ret
= split_insns (pattern
, insn
);
487 nregs
= max_reg_num ();
488 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
489 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest
, rtx
*loc
)
503 enum rtx_code code
= GET_CODE (x
);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x
)) != CC0
526 && GET_CODE (SET_DEST (x
)) != PC
527 && !REG_P (SET_DEST (x
))
528 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x
)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
531 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
533 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
536 return find_single_use_1 (dest
, &SET_SRC (x
));
540 return find_single_use_1 (dest
, &XEXP (x
, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt
= GET_RTX_FORMAT (code
);
550 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
554 if (dest
== XEXP (x
, i
)
555 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
556 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
559 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
562 result
= this_result
;
563 else if (this_result
)
564 /* Duplicate usage. */
567 else if (fmt
[i
] == 'E')
571 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
573 if (XVECEXP (x
, i
, j
) == dest
575 && REG_P (XVECEXP (x
, i
, j
))
576 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
579 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
582 result
= this_result
;
583 else if (this_result
)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
618 next
= NEXT_INSN (insn
);
620 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
623 result
= find_single_use_1 (dest
, &PATTERN (next
));
633 bb
= BLOCK_FOR_INSN (insn
);
634 for (next
= NEXT_INSN (insn
);
635 next
&& BLOCK_FOR_INSN (next
) == bb
;
636 next
= NEXT_INSN (next
))
637 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
639 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
640 if (XEXP (link
, 0) == insn
)
645 result
= find_single_use_1 (dest
, &PATTERN (next
));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx
*into
, rtx newval
)
667 if (oldval
== newval
)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
676 && CONST_INT_P (newval
))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval
)
681 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval
) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval
))));
691 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval
, 0))));
696 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
698 buf
= XNEW (struct undo
);
700 buf
->kind
= UNDO_RTX
;
702 buf
->old_contents
.r
= oldval
;
705 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into
, int newval
)
720 if (oldval
== newval
)
724 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
726 buf
= XNEW (struct undo
);
728 buf
->kind
= UNDO_INT
;
730 buf
->old_contents
.i
= oldval
;
733 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
747 enum machine_mode oldval
= GET_MODE (*into
);
749 if (oldval
== newval
)
753 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
755 buf
= XNEW (struct undo
);
757 buf
->kind
= UNDO_MODE
;
759 buf
->old_contents
.m
= oldval
;
760 adjust_reg_mode (*into
, newval
);
762 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
778 rtx newi2pat
, rtx newotherpat
)
780 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
781 int new_i2_cost
, new_i3_cost
;
782 int old_cost
, new_cost
;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost
= INSN_COST (i2
);
786 i3_cost
= INSN_COST (i3
);
790 i1_cost
= INSN_COST (i1
);
793 i0_cost
= INSN_COST (i0
);
794 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
795 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
799 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
800 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
806 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
807 i1_cost
= i0_cost
= 0;
810 /* Calculate the replacement insn_rtx_costs. */
811 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
814 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
815 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
816 ? new_i2_cost
+ new_i3_cost
: 0;
820 new_cost
= new_i3_cost
;
824 if (undobuf
.other_insn
)
826 int old_other_cost
, new_other_cost
;
828 old_other_cost
= INSN_COST (undobuf
.other_insn
);
829 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
830 if (old_other_cost
> 0 && new_other_cost
> 0)
832 old_cost
+= old_other_cost
;
833 new_cost
+= new_other_cost
;
839 /* Disallow this recombination if both new_cost and old_cost are
840 greater than zero, and new_cost is greater than old cost. */
842 && new_cost
> old_cost
)
849 "rejecting combination of insns %d, %d, %d and %d\n",
850 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
852 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
853 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
858 "rejecting combination of insns %d, %d and %d\n",
859 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
860 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
861 i1_cost
, i2_cost
, i3_cost
, old_cost
);
866 "rejecting combination of insns %d and %d\n",
867 INSN_UID (i2
), INSN_UID (i3
));
868 fprintf (dump_file
, "original costs %d + %d = %d\n",
869 i2_cost
, i3_cost
, old_cost
);
874 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
875 new_i2_cost
, new_i3_cost
, new_cost
);
878 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
884 /* Update the uid_insn_cost array with the replacement costs. */
885 INSN_COST (i2
) = new_i2_cost
;
886 INSN_COST (i3
) = new_i3_cost
;
894 /* Delete any insns that copy a register to itself. */
897 delete_noop_moves (void)
904 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
906 next
= NEXT_INSN (insn
);
907 if (INSN_P (insn
) && noop_move_p (insn
))
910 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
912 delete_insn_and_edges (insn
);
919 /* Fill in log links field for all insns. */
922 create_log_links (void)
926 df_ref
*def_vec
, *use_vec
;
928 next_use
= XCNEWVEC (rtx
, max_reg_num ());
930 /* Pass through each block from the end, recording the uses of each
931 register and establishing log links when def is encountered.
932 Note that we do not clear next_use array in order to save time,
933 so we have to test whether the use is in the same basic block as def.
935 There are a few cases below when we do not consider the definition or
936 usage -- these are taken from original flow.c did. Don't ask me why it is
937 done this way; I don't know and if it works, I don't want to know. */
941 FOR_BB_INSNS_REVERSE (bb
, insn
)
943 if (!NONDEBUG_INSN_P (insn
))
946 /* Log links are created only once. */
947 gcc_assert (!LOG_LINKS (insn
));
949 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
951 df_ref def
= *def_vec
;
952 int regno
= DF_REF_REGNO (def
);
955 if (!next_use
[regno
])
958 /* Do not consider if it is pre/post modification in MEM. */
959 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
962 /* Do not make the log link for frame pointer. */
963 if ((regno
== FRAME_POINTER_REGNUM
964 && (! reload_completed
|| frame_pointer_needed
))
965 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
966 || (regno
== HARD_FRAME_POINTER_REGNUM
967 && (! reload_completed
|| frame_pointer_needed
))
969 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
970 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
975 use_insn
= next_use
[regno
];
976 if (BLOCK_FOR_INSN (use_insn
) == bb
)
980 We don't build a LOG_LINK for hard registers contained
981 in ASM_OPERANDs. If these registers get replaced,
982 we might wind up changing the semantics of the insn,
983 even if reload can make what appear to be valid
984 assignments later. */
985 if (regno
>= FIRST_PSEUDO_REGISTER
986 || asm_noperands (PATTERN (use_insn
)) < 0)
988 /* Don't add duplicate links between instructions. */
990 for (links
= LOG_LINKS (use_insn
); links
;
991 links
= XEXP (links
, 1))
992 if (insn
== XEXP (links
, 0))
996 LOG_LINKS (use_insn
) =
997 alloc_INSN_LIST (insn
, LOG_LINKS (use_insn
));
1000 next_use
[regno
] = NULL_RTX
;
1003 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1005 df_ref use
= *use_vec
;
1006 int regno
= DF_REF_REGNO (use
);
1008 /* Do not consider the usage of the stack pointer
1009 by function call. */
1010 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1013 next_use
[regno
] = insn
;
1021 /* Clear LOG_LINKS fields of insns. */
1024 clear_log_links (void)
1028 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1030 free_INSN_LIST_list (&LOG_LINKS (insn
));
1033 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1034 true if we found a LOG_LINK that proves that A feeds B. This only works
1035 if there are no instructions between A and B which could have a link
1036 depending on A, since in that case we would not record a link for B. */
1039 insn_a_feeds_b (rtx a
, rtx b
)
1042 for (links
= LOG_LINKS (b
); links
; links
= XEXP (links
, 1))
1043 if (XEXP (links
, 0) == a
)
1048 /* Main entry point for combiner. F is the first insn of the function.
1049 NREGS is the first unused pseudo-reg number.
1051 Return nonzero if the combiner has turned an indirect jump
1052 instruction into a direct jump. */
1054 combine_instructions (rtx f
, unsigned int nregs
)
1060 rtx links
, nextlinks
;
1062 basic_block last_bb
;
1064 int new_direct_jump_p
= 0;
1066 for (first
= f
; first
&& !INSN_P (first
); )
1067 first
= NEXT_INSN (first
);
1071 combine_attempts
= 0;
1074 combine_successes
= 0;
1076 rtl_hooks
= combine_rtl_hooks
;
1078 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1080 init_recog_no_volatile ();
1082 /* Allocate array for insn info. */
1083 max_uid_known
= get_max_uid ();
1084 uid_log_links
= XCNEWVEC (rtx
, max_uid_known
+ 1);
1085 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1087 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1089 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1090 problems when, for example, we have j <<= 1 in a loop. */
1092 nonzero_sign_valid
= 0;
1093 label_tick
= label_tick_ebb_start
= 1;
1095 /* Scan all SETs and see if we can deduce anything about what
1096 bits are known to be zero for some registers and how many copies
1097 of the sign bit are known to exist for those registers.
1099 Also set any known values so that we can use it while searching
1100 for what bits are known to be set. */
1102 setup_incoming_promotions (first
);
1103 /* Allow the entry block and the first block to fall into the same EBB.
1104 Conceptually the incoming promotions are assigned to the entry block. */
1105 last_bb
= ENTRY_BLOCK_PTR
;
1107 create_log_links ();
1108 FOR_EACH_BB (this_basic_block
)
1110 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1115 if (!single_pred_p (this_basic_block
)
1116 || single_pred (this_basic_block
) != last_bb
)
1117 label_tick_ebb_start
= label_tick
;
1118 last_bb
= this_basic_block
;
1120 FOR_BB_INSNS (this_basic_block
, insn
)
1121 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1123 subst_low_luid
= DF_INSN_LUID (insn
);
1126 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1128 record_dead_and_set_regs (insn
);
1131 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1132 if (REG_NOTE_KIND (links
) == REG_INC
)
1133 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1137 /* Record the current insn_rtx_cost of this instruction. */
1138 if (NONJUMP_INSN_P (insn
))
1139 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1140 optimize_this_for_speed_p
);
1142 fprintf(dump_file
, "insn_cost %d: %d\n",
1143 INSN_UID (insn
), INSN_COST (insn
));
1147 nonzero_sign_valid
= 1;
1149 /* Now scan all the insns in forward order. */
1150 label_tick
= label_tick_ebb_start
= 1;
1152 setup_incoming_promotions (first
);
1153 last_bb
= ENTRY_BLOCK_PTR
;
1155 FOR_EACH_BB (this_basic_block
)
1157 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1162 if (!single_pred_p (this_basic_block
)
1163 || single_pred (this_basic_block
) != last_bb
)
1164 label_tick_ebb_start
= label_tick
;
1165 last_bb
= this_basic_block
;
1167 rtl_profile_for_bb (this_basic_block
);
1168 for (insn
= BB_HEAD (this_basic_block
);
1169 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1170 insn
= next
? next
: NEXT_INSN (insn
))
1173 if (NONDEBUG_INSN_P (insn
))
1175 /* See if we know about function return values before this
1176 insn based upon SUBREG flags. */
1177 check_promoted_subreg (insn
, PATTERN (insn
));
1179 /* See if we can find hardregs and subreg of pseudos in
1180 narrower modes. This could help turning TRUNCATEs
1182 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1184 /* Try this insn with each insn it links back to. */
1186 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1187 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
,
1188 NULL_RTX
, &new_direct_jump_p
)) != 0)
1191 /* Try each sequence of three linked insns ending with this one. */
1193 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1195 rtx link
= XEXP (links
, 0);
1197 /* If the linked insn has been replaced by a note, then there
1198 is no point in pursuing this chain any further. */
1202 for (nextlinks
= LOG_LINKS (link
);
1204 nextlinks
= XEXP (nextlinks
, 1))
1205 if ((next
= try_combine (insn
, link
, XEXP (nextlinks
, 0),
1207 &new_direct_jump_p
)) != 0)
1212 /* Try to combine a jump insn that uses CC0
1213 with a preceding insn that sets CC0, and maybe with its
1214 logical predecessor as well.
1215 This is how we make decrement-and-branch insns.
1216 We need this special code because data flow connections
1217 via CC0 do not get entered in LOG_LINKS. */
1220 && (prev
= prev_nonnote_insn (insn
)) != 0
1221 && NONJUMP_INSN_P (prev
)
1222 && sets_cc0_p (PATTERN (prev
)))
1224 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1225 &new_direct_jump_p
)) != 0)
1228 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1229 nextlinks
= XEXP (nextlinks
, 1))
1230 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1232 &new_direct_jump_p
)) != 0)
1236 /* Do the same for an insn that explicitly references CC0. */
1237 if (NONJUMP_INSN_P (insn
)
1238 && (prev
= prev_nonnote_insn (insn
)) != 0
1239 && NONJUMP_INSN_P (prev
)
1240 && sets_cc0_p (PATTERN (prev
))
1241 && GET_CODE (PATTERN (insn
)) == SET
1242 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1244 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1245 &new_direct_jump_p
)) != 0)
1248 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1249 nextlinks
= XEXP (nextlinks
, 1))
1250 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1252 &new_direct_jump_p
)) != 0)
1256 /* Finally, see if any of the insns that this insn links to
1257 explicitly references CC0. If so, try this insn, that insn,
1258 and its predecessor if it sets CC0. */
1259 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1260 if (NONJUMP_INSN_P (XEXP (links
, 0))
1261 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
1262 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
1263 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
1264 && NONJUMP_INSN_P (prev
)
1265 && sets_cc0_p (PATTERN (prev
))
1266 && (next
= try_combine (insn
, XEXP (links
, 0),
1268 &new_direct_jump_p
)) != 0)
1272 /* Try combining an insn with two different insns whose results it
1274 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1275 for (nextlinks
= XEXP (links
, 1); nextlinks
;
1276 nextlinks
= XEXP (nextlinks
, 1))
1277 if ((next
= try_combine (insn
, XEXP (links
, 0),
1278 XEXP (nextlinks
, 0), NULL_RTX
,
1279 &new_direct_jump_p
)) != 0)
1282 /* Try four-instruction combinations. */
1283 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1286 rtx link
= XEXP (links
, 0);
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 for (next1
= LOG_LINKS (link
); next1
; next1
= XEXP (next1
, 1))
1295 rtx link1
= XEXP (next1
, 0);
1298 /* I0 -> I1 -> I2 -> I3. */
1299 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1300 nextlinks
= XEXP (nextlinks
, 1))
1301 if ((next
= try_combine (insn
, link
, link1
,
1302 XEXP (nextlinks
, 0),
1303 &new_direct_jump_p
)) != 0)
1305 /* I0, I1 -> I2, I2 -> I3. */
1306 for (nextlinks
= XEXP (next1
, 1); nextlinks
;
1307 nextlinks
= XEXP (nextlinks
, 1))
1308 if ((next
= try_combine (insn
, link
, link1
,
1309 XEXP (nextlinks
, 0),
1310 &new_direct_jump_p
)) != 0)
1314 for (next1
= XEXP (links
, 1); next1
; next1
= XEXP (next1
, 1))
1316 rtx link1
= XEXP (next1
, 0);
1319 /* I0 -> I2; I1, I2 -> I3. */
1320 for (nextlinks
= LOG_LINKS (link
); nextlinks
;
1321 nextlinks
= XEXP (nextlinks
, 1))
1322 if ((next
= try_combine (insn
, link
, link1
,
1323 XEXP (nextlinks
, 0),
1324 &new_direct_jump_p
)) != 0)
1326 /* I0 -> I1; I1, I2 -> I3. */
1327 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1328 nextlinks
= XEXP (nextlinks
, 1))
1329 if ((next
= try_combine (insn
, link
, link1
,
1330 XEXP (nextlinks
, 0),
1331 &new_direct_jump_p
)) != 0)
1336 /* Try this insn with each REG_EQUAL note it links back to. */
1337 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1340 rtx temp
= XEXP (links
, 0);
1341 if ((set
= single_set (temp
)) != 0
1342 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1343 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1344 /* Avoid using a register that may already been marked
1345 dead by an earlier instruction. */
1346 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1347 && (GET_MODE (note
) == VOIDmode
1348 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1349 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1351 /* Temporarily replace the set's source with the
1352 contents of the REG_EQUAL note. The insn will
1353 be deleted or recognized by try_combine. */
1354 rtx orig
= SET_SRC (set
);
1355 SET_SRC (set
) = note
;
1357 i2mod_old_rhs
= copy_rtx (orig
);
1358 i2mod_new_rhs
= copy_rtx (note
);
1359 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1360 &new_direct_jump_p
);
1364 SET_SRC (set
) = orig
;
1369 record_dead_and_set_regs (insn
);
1377 default_rtl_profile ();
1380 new_direct_jump_p
|= purge_all_dead_edges ();
1381 delete_noop_moves ();
1384 free (uid_log_links
);
1385 free (uid_insn_cost
);
1386 VEC_free (reg_stat_type
, heap
, reg_stat
);
1389 struct undo
*undo
, *next
;
1390 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1398 total_attempts
+= combine_attempts
;
1399 total_merges
+= combine_merges
;
1400 total_extras
+= combine_extras
;
1401 total_successes
+= combine_successes
;
1403 nonzero_sign_valid
= 0;
1404 rtl_hooks
= general_rtl_hooks
;
1406 /* Make recognizer allow volatile MEMs again. */
1409 return new_direct_jump_p
;
1412 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1415 init_reg_last (void)
1420 FOR_EACH_VEC_ELT (reg_stat_type
, reg_stat
, i
, p
)
1421 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1424 /* Set up any promoted values for incoming argument registers. */
1427 setup_incoming_promotions (rtx first
)
1430 bool strictly_local
= false;
1432 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1433 arg
= DECL_CHAIN (arg
))
1435 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1437 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1439 /* Only continue if the incoming argument is in a register. */
1443 /* Determine, if possible, whether all call sites of the current
1444 function lie within the current compilation unit. (This does
1445 take into account the exporting of a function via taking its
1446 address, and so forth.) */
1447 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1449 /* The mode and signedness of the argument before any promotions happen
1450 (equal to the mode of the pseudo holding it at that stage). */
1451 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1452 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1454 /* The mode and signedness of the argument after any source language and
1455 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1456 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1457 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1459 /* The mode and signedness of the argument as it is actually passed,
1460 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1461 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1462 TREE_TYPE (cfun
->decl
), 0);
1464 /* The mode of the register in which the argument is being passed. */
1465 mode4
= GET_MODE (reg
);
1467 /* Eliminate sign extensions in the callee when:
1468 (a) A mode promotion has occurred; */
1471 /* (b) The mode of the register is the same as the mode of
1472 the argument as it is passed; */
1475 /* (c) There's no language level extension; */
1478 /* (c.1) All callers are from the current compilation unit. If that's
1479 the case we don't have to rely on an ABI, we only have to know
1480 what we're generating right now, and we know that we will do the
1481 mode1 to mode2 promotion with the given sign. */
1482 else if (!strictly_local
)
1484 /* (c.2) The combination of the two promotions is useful. This is
1485 true when the signs match, or if the first promotion is unsigned.
1486 In the later case, (sign_extend (zero_extend x)) is the same as
1487 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1493 /* Record that the value was promoted from mode1 to mode3,
1494 so that any sign extension at the head of the current
1495 function may be eliminated. */
1496 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1497 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1498 record_value_for_reg (reg
, first
, x
);
1502 /* Called via note_stores. If X is a pseudo that is narrower than
1503 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1505 If we are setting only a portion of X and we can't figure out what
1506 portion, assume all bits will be used since we don't know what will
1509 Similarly, set how many bits of X are known to be copies of the sign bit
1510 at all locations in the function. This is the smallest number implied
1514 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1516 rtx insn
= (rtx
) data
;
1520 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1521 /* If this register is undefined at the start of the file, we can't
1522 say what its contents were. */
1523 && ! REGNO_REG_SET_P
1524 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1525 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1527 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1529 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1531 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1532 rsp
->sign_bit_copies
= 1;
1536 /* If this register is being initialized using itself, and the
1537 register is uninitialized in this basic block, and there are
1538 no LOG_LINKS which set the register, then part of the
1539 register is uninitialized. In that case we can't assume
1540 anything about the number of nonzero bits.
1542 ??? We could do better if we checked this in
1543 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1544 could avoid making assumptions about the insn which initially
1545 sets the register, while still using the information in other
1546 insns. We would have to be careful to check every insn
1547 involved in the combination. */
1550 && reg_referenced_p (x
, PATTERN (insn
))
1551 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1556 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1558 if (dead_or_set_p (XEXP (link
, 0), x
))
1563 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1564 rsp
->sign_bit_copies
= 1;
1569 /* If this is a complex assignment, see if we can convert it into a
1570 simple assignment. */
1571 set
= expand_field_assignment (set
);
1573 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1574 set what we know about X. */
1576 if (SET_DEST (set
) == x
1577 || (GET_CODE (SET_DEST (set
)) == SUBREG
1578 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1579 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1580 && SUBREG_REG (SET_DEST (set
)) == x
))
1582 rtx src
= SET_SRC (set
);
1584 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1585 /* If X is narrower than a word and SRC is a non-negative
1586 constant that would appear negative in the mode of X,
1587 sign-extend it for use in reg_stat[].nonzero_bits because some
1588 machines (maybe most) will actually do the sign-extension
1589 and this is the conservative approach.
1591 ??? For 2.5, try to tighten up the MD files in this regard
1592 instead of this kludge. */
1594 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1595 && CONST_INT_P (src
)
1597 && 0 != (INTVAL (src
)
1598 & ((HOST_WIDE_INT
) 1
1599 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1600 src
= GEN_INT (INTVAL (src
)
1601 | ((HOST_WIDE_INT
) (-1)
1602 << GET_MODE_BITSIZE (GET_MODE (x
))));
1605 /* Don't call nonzero_bits if it cannot change anything. */
1606 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1607 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1608 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1609 if (rsp
->sign_bit_copies
== 0
1610 || rsp
->sign_bit_copies
> num
)
1611 rsp
->sign_bit_copies
= num
;
1615 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1616 rsp
->sign_bit_copies
= 1;
1621 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1622 optionally insns that were previously combined into I3 or that will be
1623 combined into the merger of INSN and I3. The order is PRED, PRED2,
1624 INSN, SUCC, SUCC2, I3.
1626 Return 0 if the combination is not allowed for any reason.
1628 If the combination is allowed, *PDEST will be set to the single
1629 destination of INSN and *PSRC to the single source, and this function
1633 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1634 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1635 rtx
*pdest
, rtx
*psrc
)
1644 bool all_adjacent
= true;
1650 if (next_active_insn (succ2
) != i3
)
1651 all_adjacent
= false;
1652 if (next_active_insn (succ
) != succ2
)
1653 all_adjacent
= false;
1655 else if (next_active_insn (succ
) != i3
)
1656 all_adjacent
= false;
1657 if (next_active_insn (insn
) != succ
)
1658 all_adjacent
= false;
1660 else if (next_active_insn (insn
) != i3
)
1661 all_adjacent
= false;
1663 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1664 or a PARALLEL consisting of such a SET and CLOBBERs.
1666 If INSN has CLOBBER parallel parts, ignore them for our processing.
1667 By definition, these happen during the execution of the insn. When it
1668 is merged with another insn, all bets are off. If they are, in fact,
1669 needed and aren't also supplied in I3, they may be added by
1670 recog_for_combine. Otherwise, it won't match.
1672 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1675 Get the source and destination of INSN. If more than one, can't
1678 if (GET_CODE (PATTERN (insn
)) == SET
)
1679 set
= PATTERN (insn
);
1680 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1681 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1683 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1685 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1687 switch (GET_CODE (elt
))
1689 /* This is important to combine floating point insns
1690 for the SH4 port. */
1692 /* Combining an isolated USE doesn't make sense.
1693 We depend here on combinable_i3pat to reject them. */
1694 /* The code below this loop only verifies that the inputs of
1695 the SET in INSN do not change. We call reg_set_between_p
1696 to verify that the REG in the USE does not change between
1698 If the USE in INSN was for a pseudo register, the matching
1699 insn pattern will likely match any register; combining this
1700 with any other USE would only be safe if we knew that the
1701 used registers have identical values, or if there was
1702 something to tell them apart, e.g. different modes. For
1703 now, we forgo such complicated tests and simply disallow
1704 combining of USES of pseudo registers with any other USE. */
1705 if (REG_P (XEXP (elt
, 0))
1706 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1708 rtx i3pat
= PATTERN (i3
);
1709 int i
= XVECLEN (i3pat
, 0) - 1;
1710 unsigned int regno
= REGNO (XEXP (elt
, 0));
1714 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1716 if (GET_CODE (i3elt
) == USE
1717 && REG_P (XEXP (i3elt
, 0))
1718 && (REGNO (XEXP (i3elt
, 0)) == regno
1719 ? reg_set_between_p (XEXP (elt
, 0),
1720 PREV_INSN (insn
), i3
)
1721 : regno
>= FIRST_PSEUDO_REGISTER
))
1728 /* We can ignore CLOBBERs. */
1733 /* Ignore SETs whose result isn't used but not those that
1734 have side-effects. */
1735 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1736 && insn_nothrow_p (insn
)
1737 && !side_effects_p (elt
))
1740 /* If we have already found a SET, this is a second one and
1741 so we cannot combine with this insn. */
1749 /* Anything else means we can't combine. */
1755 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1756 so don't do anything with it. */
1757 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1766 set
= expand_field_assignment (set
);
1767 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1769 /* Don't eliminate a store in the stack pointer. */
1770 if (dest
== stack_pointer_rtx
1771 /* Don't combine with an insn that sets a register to itself if it has
1772 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1773 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1774 /* Can't merge an ASM_OPERANDS. */
1775 || GET_CODE (src
) == ASM_OPERANDS
1776 /* Can't merge a function call. */
1777 || GET_CODE (src
) == CALL
1778 /* Don't eliminate a function call argument. */
1780 && (find_reg_fusage (i3
, USE
, dest
)
1782 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1783 && global_regs
[REGNO (dest
)])))
1784 /* Don't substitute into an incremented register. */
1785 || FIND_REG_INC_NOTE (i3
, dest
)
1786 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1787 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1788 /* Don't substitute into a non-local goto, this confuses CFG. */
1789 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1790 /* Make sure that DEST is not used after SUCC but before I3. */
1793 && (reg_used_between_p (dest
, succ2
, i3
)
1794 || reg_used_between_p (dest
, succ
, succ2
)))
1795 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1796 /* Make sure that the value that is to be substituted for the register
1797 does not use any registers whose values alter in between. However,
1798 If the insns are adjacent, a use can't cross a set even though we
1799 think it might (this can happen for a sequence of insns each setting
1800 the same destination; last_set of that register might point to
1801 a NOTE). If INSN has a REG_EQUIV note, the register is always
1802 equivalent to the memory so the substitution is valid even if there
1803 are intervening stores. Also, don't move a volatile asm or
1804 UNSPEC_VOLATILE across any other insns. */
1807 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1808 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1809 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1810 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1811 /* Don't combine across a CALL_INSN, because that would possibly
1812 change whether the life span of some REGs crosses calls or not,
1813 and it is a pain to update that information.
1814 Exception: if source is a constant, moving it later can't hurt.
1815 Accept that as a special case. */
1816 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1819 /* DEST must either be a REG or CC0. */
1822 /* If register alignment is being enforced for multi-word items in all
1823 cases except for parameters, it is possible to have a register copy
1824 insn referencing a hard register that is not allowed to contain the
1825 mode being copied and which would not be valid as an operand of most
1826 insns. Eliminate this problem by not combining with such an insn.
1828 Also, on some machines we don't want to extend the life of a hard
1832 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1833 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1834 /* Don't extend the life of a hard register unless it is
1835 user variable (if we have few registers) or it can't
1836 fit into the desired register (meaning something special
1838 Also avoid substituting a return register into I3, because
1839 reload can't handle a conflict with constraints of other
1841 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1842 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1845 else if (GET_CODE (dest
) != CC0
)
1849 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1850 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1851 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1853 /* Don't substitute for a register intended as a clobberable
1855 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1856 if (rtx_equal_p (reg
, dest
))
1859 /* If the clobber represents an earlyclobber operand, we must not
1860 substitute an expression containing the clobbered register.
1861 As we do not analyze the constraint strings here, we have to
1862 make the conservative assumption. However, if the register is
1863 a fixed hard reg, the clobber cannot represent any operand;
1864 we leave it up to the machine description to either accept or
1865 reject use-and-clobber patterns. */
1867 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1868 || !fixed_regs
[REGNO (reg
)])
1869 if (reg_overlap_mentioned_p (reg
, src
))
1873 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1874 or not), reject, unless nothing volatile comes between it and I3 */
1876 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1878 /* Make sure neither succ nor succ2 contains a volatile reference. */
1879 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1881 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1883 /* We'll check insns between INSN and I3 below. */
1886 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1887 to be an explicit register variable, and was chosen for a reason. */
1889 if (GET_CODE (src
) == ASM_OPERANDS
1890 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1893 /* If there are any volatile insns between INSN and I3, reject, because
1894 they might affect machine state. */
1896 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1897 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& volatile_insn_p (PATTERN (p
)))
1900 /* If INSN contains an autoincrement or autodecrement, make sure that
1901 register is not used between there and I3, and not already used in
1902 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1903 Also insist that I3 not be a jump; if it were one
1904 and the incremented register were spilled, we would lose. */
1907 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1908 if (REG_NOTE_KIND (link
) == REG_INC
1910 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1911 || (pred
!= NULL_RTX
1912 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1913 || (pred2
!= NULL_RTX
1914 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1915 || (succ
!= NULL_RTX
1916 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1917 || (succ2
!= NULL_RTX
1918 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1919 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1924 /* Don't combine an insn that follows a CC0-setting insn.
1925 An insn that uses CC0 must not be separated from the one that sets it.
1926 We do, however, allow I2 to follow a CC0-setting insn if that insn
1927 is passed as I1; in that case it will be deleted also.
1928 We also allow combining in this case if all the insns are adjacent
1929 because that would leave the two CC0 insns adjacent as well.
1930 It would be more logical to test whether CC0 occurs inside I1 or I2,
1931 but that would be much slower, and this ought to be equivalent. */
1933 p
= prev_nonnote_insn (insn
);
1934 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1939 /* If we get here, we have passed all the tests and the combination is
1948 /* LOC is the location within I3 that contains its pattern or the component
1949 of a PARALLEL of the pattern. We validate that it is valid for combining.
1951 One problem is if I3 modifies its output, as opposed to replacing it
1952 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1953 doing so would produce an insn that is not equivalent to the original insns.
1957 (set (reg:DI 101) (reg:DI 100))
1958 (set (subreg:SI (reg:DI 101) 0) <foo>)
1960 This is NOT equivalent to:
1962 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1963 (set (reg:DI 101) (reg:DI 100))])
1965 Not only does this modify 100 (in which case it might still be valid
1966 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1968 We can also run into a problem if I2 sets a register that I1
1969 uses and I1 gets directly substituted into I3 (not via I2). In that
1970 case, we would be getting the wrong value of I2DEST into I3, so we
1971 must reject the combination. This case occurs when I2 and I1 both
1972 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1973 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1974 of a SET must prevent combination from occurring. The same situation
1975 can occur for I0, in which case I0_NOT_IN_SRC is set.
1977 Before doing the above check, we first try to expand a field assignment
1978 into a set of logical operations.
1980 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1981 we place a register that is both set and used within I3. If more than one
1982 such register is detected, we fail.
1984 Return 1 if the combination is valid, zero otherwise. */
1987 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
1988 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
1992 if (GET_CODE (x
) == SET
)
1995 rtx dest
= SET_DEST (set
);
1996 rtx src
= SET_SRC (set
);
1997 rtx inner_dest
= dest
;
2000 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2001 || GET_CODE (inner_dest
) == SUBREG
2002 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2003 inner_dest
= XEXP (inner_dest
, 0);
2005 /* Check for the case where I3 modifies its output, as discussed
2006 above. We don't want to prevent pseudos from being combined
2007 into the address of a MEM, so only prevent the combination if
2008 i1 or i2 set the same MEM. */
2009 if ((inner_dest
!= dest
&&
2010 (!MEM_P (inner_dest
)
2011 || rtx_equal_p (i2dest
, inner_dest
)
2012 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2013 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2014 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2015 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2016 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2018 /* This is the same test done in can_combine_p except we can't test
2019 all_adjacent; we don't have to, since this instruction will stay
2020 in place, thus we are not considering increasing the lifetime of
2023 Also, if this insn sets a function argument, combining it with
2024 something that might need a spill could clobber a previous
2025 function argument; the all_adjacent test in can_combine_p also
2026 checks this; here, we do a more specific test for this case. */
2028 || (REG_P (inner_dest
)
2029 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2030 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2031 GET_MODE (inner_dest
))))
2032 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2033 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2036 /* If DEST is used in I3, it is being killed in this insn, so
2037 record that for later. We have to consider paradoxical
2038 subregs here, since they kill the whole register, but we
2039 ignore partial subregs, STRICT_LOW_PART, etc.
2040 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2041 STACK_POINTER_REGNUM, since these are always considered to be
2042 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2044 if (GET_CODE (subdest
) == SUBREG
2045 && (GET_MODE_SIZE (GET_MODE (subdest
))
2046 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2047 subdest
= SUBREG_REG (subdest
);
2050 && reg_referenced_p (subdest
, PATTERN (i3
))
2051 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2052 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2053 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2055 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2056 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2057 || ! fixed_regs
[REGNO (subdest
)])
2059 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2061 if (*pi3dest_killed
)
2064 *pi3dest_killed
= subdest
;
2068 else if (GET_CODE (x
) == PARALLEL
)
2072 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2073 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2074 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2081 /* Return 1 if X is an arithmetic expression that contains a multiplication
2082 and division. We don't count multiplications by powers of two here. */
2085 contains_muldiv (rtx x
)
2087 switch (GET_CODE (x
))
2089 case MOD
: case DIV
: case UMOD
: case UDIV
:
2093 return ! (CONST_INT_P (XEXP (x
, 1))
2094 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
2097 return contains_muldiv (XEXP (x
, 0))
2098 || contains_muldiv (XEXP (x
, 1));
2101 return contains_muldiv (XEXP (x
, 0));
2107 /* Determine whether INSN can be used in a combination. Return nonzero if
2108 not. This is used in try_combine to detect early some cases where we
2109 can't perform combinations. */
2112 cant_combine_insn_p (rtx insn
)
2117 /* If this isn't really an insn, we can't do anything.
2118 This can occur when flow deletes an insn that it has merged into an
2119 auto-increment address. */
2120 if (! INSN_P (insn
))
2123 /* Never combine loads and stores involving hard regs that are likely
2124 to be spilled. The register allocator can usually handle such
2125 reg-reg moves by tying. If we allow the combiner to make
2126 substitutions of likely-spilled regs, reload might die.
2127 As an exception, we allow combinations involving fixed regs; these are
2128 not available to the register allocator so there's no risk involved. */
2130 set
= single_set (insn
);
2133 src
= SET_SRC (set
);
2134 dest
= SET_DEST (set
);
2135 if (GET_CODE (src
) == SUBREG
)
2136 src
= SUBREG_REG (src
);
2137 if (GET_CODE (dest
) == SUBREG
)
2138 dest
= SUBREG_REG (dest
);
2139 if (REG_P (src
) && REG_P (dest
)
2140 && ((HARD_REGISTER_P (src
)
2141 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2142 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2143 || (HARD_REGISTER_P (dest
)
2144 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2145 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2151 struct likely_spilled_retval_info
2153 unsigned regno
, nregs
;
2157 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2158 hard registers that are known to be written to / clobbered in full. */
2160 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2162 struct likely_spilled_retval_info
*const info
=
2163 (struct likely_spilled_retval_info
*) data
;
2164 unsigned regno
, nregs
;
2167 if (!REG_P (XEXP (set
, 0)))
2170 if (regno
>= info
->regno
+ info
->nregs
)
2172 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2173 if (regno
+ nregs
<= info
->regno
)
2175 new_mask
= (2U << (nregs
- 1)) - 1;
2176 if (regno
< info
->regno
)
2177 new_mask
>>= info
->regno
- regno
;
2179 new_mask
<<= regno
- info
->regno
;
2180 info
->mask
&= ~new_mask
;
2183 /* Return nonzero iff part of the return value is live during INSN, and
2184 it is likely spilled. This can happen when more than one insn is needed
2185 to copy the return value, e.g. when we consider to combine into the
2186 second copy insn for a complex value. */
2189 likely_spilled_retval_p (rtx insn
)
2191 rtx use
= BB_END (this_basic_block
);
2193 unsigned regno
, nregs
;
2194 /* We assume here that no machine mode needs more than
2195 32 hard registers when the value overlaps with a register
2196 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2198 struct likely_spilled_retval_info info
;
2200 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2202 reg
= XEXP (PATTERN (use
), 0);
2203 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2205 regno
= REGNO (reg
);
2206 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2209 mask
= (2U << (nregs
- 1)) - 1;
2211 /* Disregard parts of the return value that are set later. */
2215 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2217 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2220 /* Check if any of the (probably) live return value registers is
2225 if ((mask
& 1 << nregs
)
2226 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2232 /* Adjust INSN after we made a change to its destination.
2234 Changing the destination can invalidate notes that say something about
2235 the results of the insn and a LOG_LINK pointing to the insn. */
2238 adjust_for_new_dest (rtx insn
)
2240 /* For notes, be conservative and simply remove them. */
2241 remove_reg_equal_equiv_notes (insn
);
2243 /* The new insn will have a destination that was previously the destination
2244 of an insn just above it. Call distribute_links to make a LOG_LINK from
2245 the next use of that destination. */
2246 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
2248 df_insn_rescan (insn
);
2251 /* Return TRUE if combine can reuse reg X in mode MODE.
2252 ADDED_SETS is nonzero if the original set is still required. */
2254 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2262 /* Allow hard registers if the new mode is legal, and occupies no more
2263 registers than the old mode. */
2264 if (regno
< FIRST_PSEUDO_REGISTER
)
2265 return (HARD_REGNO_MODE_OK (regno
, mode
)
2266 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2267 >= hard_regno_nregs
[regno
][mode
]));
2269 /* Or a pseudo that is only used once. */
2270 return (REG_N_SETS (regno
) == 1 && !added_sets
2271 && !REG_USERVAR_P (x
));
2275 /* Check whether X, the destination of a set, refers to part of
2276 the register specified by REG. */
2279 reg_subword_p (rtx x
, rtx reg
)
2281 /* Check that reg is an integer mode register. */
2282 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2285 if (GET_CODE (x
) == STRICT_LOW_PART
2286 || GET_CODE (x
) == ZERO_EXTRACT
)
2289 return GET_CODE (x
) == SUBREG
2290 && SUBREG_REG (x
) == reg
2291 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2295 /* Replace auto-increment addressing modes with explicit operations to
2296 access the same addresses without modifying the corresponding
2297 registers. If AFTER holds, SRC is meant to be reused after the
2298 side effect, otherwise it is to be reused before that. */
2301 cleanup_auto_inc_dec (rtx src
, bool after
, enum machine_mode mem_mode
)
2304 const RTX_CODE code
= GET_CODE (x
);
2320 /* SCRATCH must be shared because they represent distinct values. */
2323 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2328 if (shared_const_p (x
))
2333 mem_mode
= GET_MODE (x
);
2340 gcc_assert (mem_mode
!= VOIDmode
&& mem_mode
!= BLKmode
);
2341 if (after
== (code
== PRE_INC
|| code
== PRE_DEC
))
2342 x
= cleanup_auto_inc_dec (XEXP (x
, 0), after
, mem_mode
);
2344 x
= gen_rtx_PLUS (GET_MODE (x
),
2345 cleanup_auto_inc_dec (XEXP (x
, 0), after
, mem_mode
),
2346 GEN_INT ((code
== PRE_INC
|| code
== POST_INC
)
2347 ? GET_MODE_SIZE (mem_mode
)
2348 : -GET_MODE_SIZE (mem_mode
)));
2353 if (after
== (code
== PRE_MODIFY
))
2357 return cleanup_auto_inc_dec (x
, after
, mem_mode
);
2363 /* Copy the various flags, fields, and other information. We assume
2364 that all fields need copying, and then clear the fields that should
2365 not be copied. That is the sensible default behavior, and forces
2366 us to explicitly document why we are *not* copying a flag. */
2367 x
= shallow_copy_rtx (x
);
2369 /* We do not copy the USED flag, which is used as a mark bit during
2370 walks over the RTL. */
2371 RTX_FLAG (x
, used
) = 0;
2373 /* We do not copy FRAME_RELATED for INSNs. */
2375 RTX_FLAG (x
, frame_related
) = 0;
2377 fmt
= GET_RTX_FORMAT (code
);
2378 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2380 XEXP (x
, i
) = cleanup_auto_inc_dec (XEXP (x
, i
), after
, mem_mode
);
2381 else if (fmt
[i
] == 'E' || fmt
[i
] == 'V')
2384 XVEC (x
, i
) = rtvec_alloc (XVECLEN (x
, i
));
2385 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2387 = cleanup_auto_inc_dec (XVECEXP (src
, i
, j
), after
, mem_mode
);
2394 /* Auxiliary data structure for propagate_for_debug_stmt. */
2396 struct rtx_subst_pair
2403 /* DATA points to an rtx_subst_pair. Return the value that should be
2407 propagate_for_debug_subst (rtx from
, const_rtx old_rtx
, void *data
)
2409 struct rtx_subst_pair
*pair
= (struct rtx_subst_pair
*)data
;
2411 if (!rtx_equal_p (from
, old_rtx
))
2413 if (!pair
->adjusted
)
2415 pair
->adjusted
= true;
2417 pair
->to
= cleanup_auto_inc_dec (pair
->to
, pair
->after
, VOIDmode
);
2419 pair
->to
= copy_rtx (pair
->to
);
2421 pair
->to
= make_compound_operation (pair
->to
, SET
);
2424 return copy_rtx (pair
->to
);
2427 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2428 and LAST. If MOVE holds, debug insns must also be moved past
2432 propagate_for_debug (rtx insn
, rtx last
, rtx dest
, rtx src
, bool move
)
2434 rtx next
, move_pos
= move
? last
: NULL_RTX
, loc
;
2436 struct rtx_subst_pair p
;
2441 next
= NEXT_INSN (insn
);
2442 while (next
!= last
)
2445 next
= NEXT_INSN (insn
);
2446 if (DEBUG_INSN_P (insn
))
2448 loc
= simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn
),
2449 dest
, propagate_for_debug_subst
, &p
);
2450 if (loc
== INSN_VAR_LOCATION_LOC (insn
))
2452 INSN_VAR_LOCATION_LOC (insn
) = loc
;
2456 PREV_INSN (insn
) = NEXT_INSN (insn
) = NULL_RTX
;
2457 move_pos
= emit_debug_insn_after (insn
, move_pos
);
2460 df_insn_rescan (insn
);
2465 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2466 Note that the INSN should be deleted *after* removing dead edges, so
2467 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2468 but not for a (set (pc) (label_ref FOO)). */
2471 update_cfg_for_uncondjump (rtx insn
)
2473 basic_block bb
= BLOCK_FOR_INSN (insn
);
2474 bool at_end
= (BB_END (bb
) == insn
);
2477 purge_dead_edges (bb
);
2480 if (at_end
&& EDGE_COUNT (bb
->succs
) == 1)
2481 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2484 /* Try to combine the insns I0, I1 and I2 into I3.
2485 Here I0, I1 and I2 appear earlier than I3.
2486 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2489 If we are combining more than two insns and the resulting insn is not
2490 recognized, try splitting it into two insns. If that happens, I2 and I3
2491 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2492 Otherwise, I0, I1 and I2 are pseudo-deleted.
2494 Return 0 if the combination does not work. Then nothing is changed.
2495 If we did the combination, return the insn at which combine should
2498 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2499 new direct jump instruction. */
2502 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
)
2504 /* New patterns for I3 and I2, respectively. */
2505 rtx newpat
, newi2pat
= 0;
2506 rtvec newpat_vec_with_clobbers
= 0;
2507 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2508 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2510 int added_sets_0
, added_sets_1
, added_sets_2
;
2511 /* Total number of SETs to put into I3. */
2513 /* Nonzero if I2's or I1's body now appears in I3. */
2514 int i2_is_used
= 0, i1_is_used
= 0;
2515 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2516 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2517 /* Contains I3 if the destination of I3 is used in its source, which means
2518 that the old life of I3 is being killed. If that usage is placed into
2519 I2 and not in I3, a REG_DEAD note must be made. */
2520 rtx i3dest_killed
= 0;
2521 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2522 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2523 /* Set if I2DEST was reused as a scratch register. */
2524 bool i2scratch
= false;
2525 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2526 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2528 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2529 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2530 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2531 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2532 /* Notes that must be added to REG_NOTES in I3 and I2. */
2533 rtx new_i3_notes
, new_i2_notes
;
2534 /* Notes that we substituted I3 into I2 instead of the normal case. */
2535 int i3_subst_into_i2
= 0;
2536 /* Notes that I1, I2 or I3 is a MULT operation. */
2539 int changed_i3_dest
= 0;
2545 rtx new_other_notes
;
2548 /* Only try four-insn combinations when there's high likelihood of
2549 success. Look for simple insns, such as loads of constants or
2550 binary operations involving a constant. */
2557 if (!flag_expensive_optimizations
)
2560 for (i
= 0; i
< 4; i
++)
2562 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2563 rtx set
= single_set (insn
);
2567 src
= SET_SRC (set
);
2568 if (CONSTANT_P (src
))
2573 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2575 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2576 || GET_CODE (src
) == LSHIFTRT
)
2579 if (ngood
< 2 && nshift
< 2)
2583 /* Exit early if one of the insns involved can't be used for
2585 if (cant_combine_insn_p (i3
)
2586 || cant_combine_insn_p (i2
)
2587 || (i1
&& cant_combine_insn_p (i1
))
2588 || (i0
&& cant_combine_insn_p (i0
))
2589 || likely_spilled_retval_p (i3
))
2593 undobuf
.other_insn
= 0;
2595 /* Reset the hard register usage information. */
2596 CLEAR_HARD_REG_SET (newpat_used_regs
);
2598 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2601 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2602 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2604 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2605 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2607 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2608 INSN_UID (i2
), INSN_UID (i3
));
2611 /* If multiple insns feed into one of I2 or I3, they can be in any
2612 order. To simplify the code below, reorder them in sequence. */
2613 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2614 temp
= i2
, i2
= i0
, i0
= temp
;
2615 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2616 temp
= i1
, i1
= i0
, i0
= temp
;
2617 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2618 temp
= i1
, i1
= i2
, i2
= temp
;
2620 added_links_insn
= 0;
2622 /* First check for one important special-case that the code below will
2623 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2624 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2625 we may be able to replace that destination with the destination of I3.
2626 This occurs in the common code where we compute both a quotient and
2627 remainder into a structure, in which case we want to do the computation
2628 directly into the structure to avoid register-register copies.
2630 Note that this case handles both multiple sets in I2 and also
2631 cases where I2 has a number of CLOBBER or PARALLELs.
2633 We make very conservative checks below and only try to handle the
2634 most common cases of this. For example, we only handle the case
2635 where I2 and I3 are adjacent to avoid making difficult register
2638 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2639 && REG_P (SET_SRC (PATTERN (i3
)))
2640 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2641 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2642 && GET_CODE (PATTERN (i2
)) == PARALLEL
2643 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2644 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2645 below would need to check what is inside (and reg_overlap_mentioned_p
2646 doesn't support those codes anyway). Don't allow those destinations;
2647 the resulting insn isn't likely to be recognized anyway. */
2648 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2649 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2650 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2651 SET_DEST (PATTERN (i3
)))
2652 && next_active_insn (i2
) == i3
)
2654 rtx p2
= PATTERN (i2
);
2656 /* Make sure that the destination of I3,
2657 which we are going to substitute into one output of I2,
2658 is not used within another output of I2. We must avoid making this:
2659 (parallel [(set (mem (reg 69)) ...)
2660 (set (reg 69) ...)])
2661 which is not well-defined as to order of actions.
2662 (Besides, reload can't handle output reloads for this.)
2664 The problem can also happen if the dest of I3 is a memory ref,
2665 if another dest in I2 is an indirect memory ref. */
2666 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2667 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2668 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2669 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2670 SET_DEST (XVECEXP (p2
, 0, i
))))
2673 if (i
== XVECLEN (p2
, 0))
2674 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2675 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2676 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2677 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2682 subst_low_luid
= DF_INSN_LUID (i2
);
2684 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2685 i2src
= SET_DEST (PATTERN (i3
));
2686 i2dest
= SET_SRC (PATTERN (i3
));
2687 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2689 /* Replace the dest in I2 with our dest and make the resulting
2690 insn the new pattern for I3. Then skip to where we
2691 validate the pattern. Everything was set up above. */
2692 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
2693 SET_DEST (PATTERN (i3
)));
2696 i3_subst_into_i2
= 1;
2697 goto validate_replacement
;
2701 /* If I2 is setting a pseudo to a constant and I3 is setting some
2702 sub-part of it to another constant, merge them by making a new
2705 && (temp
= single_set (i2
)) != 0
2706 && (CONST_INT_P (SET_SRC (temp
))
2707 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2708 && GET_CODE (PATTERN (i3
)) == SET
2709 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2710 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2711 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2713 rtx dest
= SET_DEST (PATTERN (i3
));
2717 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2719 if (CONST_INT_P (XEXP (dest
, 1))
2720 && CONST_INT_P (XEXP (dest
, 2)))
2722 width
= INTVAL (XEXP (dest
, 1));
2723 offset
= INTVAL (XEXP (dest
, 2));
2724 dest
= XEXP (dest
, 0);
2725 if (BITS_BIG_ENDIAN
)
2726 offset
= GET_MODE_BITSIZE (GET_MODE (dest
)) - width
- offset
;
2731 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2732 dest
= XEXP (dest
, 0);
2733 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
2739 /* If this is the low part, we're done. */
2740 if (subreg_lowpart_p (dest
))
2742 /* Handle the case where inner is twice the size of outer. */
2743 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2744 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
2745 offset
+= GET_MODE_BITSIZE (GET_MODE (dest
));
2746 /* Otherwise give up for now. */
2752 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2753 <= HOST_BITS_PER_DOUBLE_INT
))
2756 rtx inner
= SET_SRC (PATTERN (i3
));
2757 rtx outer
= SET_SRC (temp
);
2759 o
= rtx_to_double_int (outer
);
2760 i
= rtx_to_double_int (inner
);
2762 m
= double_int_mask (width
);
2763 i
= double_int_and (i
, m
);
2764 m
= double_int_lshift (m
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2765 i
= double_int_lshift (i
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2766 o
= double_int_ior (double_int_and_not (o
, m
), i
);
2770 subst_low_luid
= DF_INSN_LUID (i2
);
2771 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2772 i2dest
= SET_DEST (temp
);
2773 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2775 /* Replace the source in I2 with the new constant and make the
2776 resulting insn the new pattern for I3. Then skip to where we
2777 validate the pattern. Everything was set up above. */
2778 SUBST (SET_SRC (temp
),
2779 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2781 newpat
= PATTERN (i2
);
2783 /* The dest of I3 has been replaced with the dest of I2. */
2784 changed_i3_dest
= 1;
2785 goto validate_replacement
;
2790 /* If we have no I1 and I2 looks like:
2791 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2793 make up a dummy I1 that is
2796 (set (reg:CC X) (compare:CC Y (const_int 0)))
2798 (We can ignore any trailing CLOBBERs.)
2800 This undoes a previous combination and allows us to match a branch-and-
2803 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2804 && XVECLEN (PATTERN (i2
), 0) >= 2
2805 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2806 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2808 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2809 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2810 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2811 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2812 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2813 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2815 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2816 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2821 /* We make I1 with the same INSN_UID as I2. This gives it
2822 the same DF_INSN_LUID for value tracking. Our fake I1 will
2823 never appear in the insn stream so giving it the same INSN_UID
2824 as I2 will not cause a problem. */
2826 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2827 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2828 INSN_LOCATOR (i2
), -1, NULL_RTX
);
2830 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2831 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2832 SET_DEST (PATTERN (i1
)));
2837 /* Verify that I2 and I1 are valid for combining. */
2838 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2839 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2841 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2848 /* Record whether I2DEST is used in I2SRC and similarly for the other
2849 cases. Knowing this will help in register status updating below. */
2850 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2851 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2852 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2853 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2854 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2855 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2856 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2857 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2858 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2860 /* For the earlier insns, determine which of the subsequent ones they
2862 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2863 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2864 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2865 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2866 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2868 /* Ensure that I3's pattern can be the destination of combines. */
2869 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2870 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2871 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2872 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2879 /* See if any of the insns is a MULT operation. Unless one is, we will
2880 reject a combination that is, since it must be slower. Be conservative
2882 if (GET_CODE (i2src
) == MULT
2883 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2884 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2885 || (GET_CODE (PATTERN (i3
)) == SET
2886 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2889 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2890 We used to do this EXCEPT in one case: I3 has a post-inc in an
2891 output operand. However, that exception can give rise to insns like
2893 which is a famous insn on the PDP-11 where the value of r3 used as the
2894 source was model-dependent. Avoid this sort of thing. */
2897 if (!(GET_CODE (PATTERN (i3
)) == SET
2898 && REG_P (SET_SRC (PATTERN (i3
)))
2899 && MEM_P (SET_DEST (PATTERN (i3
)))
2900 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2901 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2902 /* It's not the exception. */
2905 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2906 if (REG_NOTE_KIND (link
) == REG_INC
2907 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2909 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2916 /* See if the SETs in I1 or I2 need to be kept around in the merged
2917 instruction: whenever the value set there is still needed past I3.
2918 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2920 For the SET in I1, we have two cases: If I1 and I2 independently
2921 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2922 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2923 in I1 needs to be kept around unless I1DEST dies or is set in either
2924 I2 or I3. The same consideration applies to I0. */
2926 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2929 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2930 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2935 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2936 || (i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
2937 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)));
2941 /* If the set in I2 needs to be kept around, we must make a copy of
2942 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2943 PATTERN (I2), we are only substituting for the original I1DEST, not into
2944 an already-substituted copy. This also prevents making self-referential
2945 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2950 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2951 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2953 i2pat
= copy_rtx (PATTERN (i2
));
2958 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2959 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2961 i1pat
= copy_rtx (PATTERN (i1
));
2966 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2967 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2969 i0pat
= copy_rtx (PATTERN (i0
));
2974 /* Substitute in the latest insn for the regs set by the earlier ones. */
2976 maxreg
= max_reg_num ();
2981 /* Many machines that don't use CC0 have insns that can both perform an
2982 arithmetic operation and set the condition code. These operations will
2983 be represented as a PARALLEL with the first element of the vector
2984 being a COMPARE of an arithmetic operation with the constant zero.
2985 The second element of the vector will set some pseudo to the result
2986 of the same arithmetic operation. If we simplify the COMPARE, we won't
2987 match such a pattern and so will generate an extra insn. Here we test
2988 for this case, where both the comparison and the operation result are
2989 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2990 I2SRC. Later we will make the PARALLEL that contains I2. */
2992 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2993 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2994 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2995 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2997 #ifdef SELECT_CC_MODE
2999 enum machine_mode compare_mode
;
3002 newpat
= PATTERN (i3
);
3003 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
3007 #ifdef SELECT_CC_MODE
3008 /* See if a COMPARE with the operand we substituted in should be done
3009 with the mode that is currently being used. If not, do the same
3010 processing we do in `subst' for a SET; namely, if the destination
3011 is used only once, try to replace it with a register of the proper
3012 mode and also replace the COMPARE. */
3013 if (undobuf
.other_insn
== 0
3014 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
3015 &undobuf
.other_insn
))
3016 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
3018 != GET_MODE (SET_DEST (newpat
))))
3020 if (can_change_dest_mode (SET_DEST (newpat
), added_sets_2
,
3023 unsigned int regno
= REGNO (SET_DEST (newpat
));
3026 if (regno
< FIRST_PSEUDO_REGISTER
)
3027 new_dest
= gen_rtx_REG (compare_mode
, regno
);
3030 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3031 new_dest
= regno_reg_rtx
[regno
];
3034 SUBST (SET_DEST (newpat
), new_dest
);
3035 SUBST (XEXP (*cc_use
, 0), new_dest
);
3036 SUBST (SET_SRC (newpat
),
3037 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
3040 undobuf
.other_insn
= 0;
3047 /* It is possible that the source of I2 or I1 may be performing
3048 an unneeded operation, such as a ZERO_EXTEND of something
3049 that is known to have the high part zero. Handle that case
3050 by letting subst look at the innermost one of them.
3052 Another way to do this would be to have a function that tries
3053 to simplify a single insn instead of merging two or more
3054 insns. We don't do this because of the potential of infinite
3055 loops and because of the potential extra memory required.
3056 However, doing it the way we are is a bit of a kludge and
3057 doesn't catch all cases.
3059 But only do this if -fexpensive-optimizations since it slows
3060 things down and doesn't usually win.
3062 This is not done in the COMPARE case above because the
3063 unmodified I2PAT is used in the PARALLEL and so a pattern
3064 with a modified I2SRC would not match. */
3066 if (flag_expensive_optimizations
)
3068 /* Pass pc_rtx so no substitutions are done, just
3072 subst_low_luid
= DF_INSN_LUID (i1
);
3073 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
3077 subst_low_luid
= DF_INSN_LUID (i2
);
3078 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
3082 n_occurrences
= 0; /* `subst' counts here */
3084 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a
3085 unique copy of I2SRC each time we substitute it to avoid
3086 self-referential rtl. */
3088 subst_low_luid
= DF_INSN_LUID (i2
);
3089 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
3090 ((i1_feeds_i2_n
&& i1dest_in_i1src
)
3091 || (i0_feeds_i2_n
&& i0dest_in_i0src
)));
3094 /* Record whether i2's body now appears within i3's body. */
3095 i2_is_used
= n_occurrences
;
3098 /* If we already got a failure, don't try to do more. Otherwise,
3099 try to substitute in I1 if we have it. */
3101 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3103 /* Check that an autoincrement side-effect on I1 has not been lost.
3104 This happens if I1DEST is mentioned in I2 and dies there, and
3105 has disappeared from the new pattern. */
3106 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3108 && dead_or_set_p (i2
, i1dest
)
3109 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3110 /* Before we can do this substitution, we must redo the test done
3111 above (see detailed comments there) that ensures that I1DEST
3112 isn't mentioned in any SETs in NEWPAT that are field assignments. */
3113 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3121 subst_low_luid
= DF_INSN_LUID (i1
);
3122 newpat
= subst (newpat
, i1dest
, i1src
, 0,
3123 i0_feeds_i1_n
&& i0dest_in_i0src
);
3125 i1_is_used
= n_occurrences
;
3127 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3129 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3130 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3131 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3132 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3133 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3141 subst_low_luid
= DF_INSN_LUID (i0
);
3142 newpat
= subst (newpat
, i0dest
, i0src
, 0,
3143 i0_feeds_i1_n
&& i0dest_in_i0src
);
3147 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3148 to count all the ways that I2SRC and I1SRC can be used. */
3149 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3150 && i2_is_used
+ added_sets_2
> 1)
3151 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3152 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3154 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3155 && (n_occurrences
+ added_sets_0
3156 + (added_sets_1
&& i0_feeds_i1_n
)
3157 + (added_sets_2
&& i0_feeds_i2_n
)
3159 /* Fail if we tried to make a new register. */
3160 || max_reg_num () != maxreg
3161 /* Fail if we couldn't do something and have a CLOBBER. */
3162 || GET_CODE (newpat
) == CLOBBER
3163 /* Fail if this new pattern is a MULT and we didn't have one before
3164 at the outer level. */
3165 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3172 /* If the actions of the earlier insns must be kept
3173 in addition to substituting them into the latest one,
3174 we must make a new PARALLEL for the latest insn
3175 to hold additional the SETs. */
3177 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3179 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3182 if (GET_CODE (newpat
) == PARALLEL
)
3184 rtvec old
= XVEC (newpat
, 0);
3185 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3186 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3187 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3188 sizeof (old
->elem
[0]) * old
->num_elem
);
3193 total_sets
= 1 + extra_sets
;
3194 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3195 XVECEXP (newpat
, 0, 0) = old
;
3199 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3205 t
= subst (t
, i0dest
, i0src
, 0, 0);
3207 XVECEXP (newpat
, 0, --total_sets
) = t
;
3213 t
= subst (t
, i0dest
, i0src
, 0, 0);
3215 t
= subst (t
, i1dest
, i1src
, 0, 0);
3217 XVECEXP (newpat
, 0, --total_sets
) = t
;
3221 validate_replacement
:
3223 /* Note which hard regs this insn has as inputs. */
3224 mark_used_regs_combine (newpat
);
3226 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3227 consider splitting this pattern, we might need these clobbers. */
3228 if (i1
&& GET_CODE (newpat
) == PARALLEL
3229 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3231 int len
= XVECLEN (newpat
, 0);
3233 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3234 for (i
= 0; i
< len
; i
++)
3235 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3238 /* Is the result of combination a valid instruction? */
3239 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3241 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242 the second SET's destination is a register that is unused and isn't
3243 marked as an instruction that might trap in an EH region. In that case,
3244 we just need the first SET. This can occur when simplifying a divmod
3245 insn. We *must* test for this case here because the code below that
3246 splits two independent SETs doesn't handle this case correctly when it
3247 updates the register status.
3249 It's pointless doing this if we originally had two sets, one from
3250 i3, and one from i2. Combining then splitting the parallel results
3251 in the original i2 again plus an invalid insn (which we delete).
3252 The net effect is only to move instructions around, which makes
3253 debug info less accurate.
3255 Also check the case where the first SET's destination is unused.
3256 That would not cause incorrect code, but does cause an unneeded
3259 if (insn_code_number
< 0
3260 && !(added_sets_2
&& i1
== 0)
3261 && GET_CODE (newpat
) == PARALLEL
3262 && XVECLEN (newpat
, 0) == 2
3263 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3264 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3265 && asm_noperands (newpat
) < 0)
3267 rtx set0
= XVECEXP (newpat
, 0, 0);
3268 rtx set1
= XVECEXP (newpat
, 0, 1);
3270 if (((REG_P (SET_DEST (set1
))
3271 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3272 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3273 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3274 && insn_nothrow_p (i3
)
3275 && !side_effects_p (SET_SRC (set1
)))
3278 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3281 else if (((REG_P (SET_DEST (set0
))
3282 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3283 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3284 && find_reg_note (i3
, REG_UNUSED
,
3285 SUBREG_REG (SET_DEST (set0
)))))
3286 && insn_nothrow_p (i3
)
3287 && !side_effects_p (SET_SRC (set0
)))
3290 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3292 if (insn_code_number
>= 0)
3293 changed_i3_dest
= 1;
3297 /* If we were combining three insns and the result is a simple SET
3298 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299 insns. There are two ways to do this. It can be split using a
3300 machine-specific method (like when you have an addition of a large
3301 constant) or by combine in the function find_split_point. */
3303 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3304 && asm_noperands (newpat
) < 0)
3306 rtx parallel
, m_split
, *split
;
3308 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3309 use I2DEST as a scratch register will help. In the latter case,
3310 convert I2DEST to the mode of the source of NEWPAT if we can. */
3312 m_split
= combine_split_insns (newpat
, i3
);
3314 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315 inputs of NEWPAT. */
3317 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318 possible to try that as a scratch reg. This would require adding
3319 more code to make it work though. */
3321 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3323 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3325 /* First try to split using the original register as a
3326 scratch register. */
3327 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3328 gen_rtvec (2, newpat
,
3329 gen_rtx_CLOBBER (VOIDmode
,
3331 m_split
= combine_split_insns (parallel
, i3
);
3333 /* If that didn't work, try changing the mode of I2DEST if
3336 && new_mode
!= GET_MODE (i2dest
)
3337 && new_mode
!= VOIDmode
3338 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3340 enum machine_mode old_mode
= GET_MODE (i2dest
);
3343 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3344 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3347 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3348 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3351 parallel
= (gen_rtx_PARALLEL
3353 gen_rtvec (2, newpat
,
3354 gen_rtx_CLOBBER (VOIDmode
,
3356 m_split
= combine_split_insns (parallel
, i3
);
3359 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3363 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3364 buf
= undobuf
.undos
;
3365 undobuf
.undos
= buf
->next
;
3366 buf
->next
= undobuf
.frees
;
3367 undobuf
.frees
= buf
;
3371 i2scratch
= m_split
!= 0;
3374 /* If recog_for_combine has discarded clobbers, try to use them
3375 again for the split. */
3376 if (m_split
== 0 && newpat_vec_with_clobbers
)
3378 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3379 m_split
= combine_split_insns (parallel
, i3
);
3382 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3384 m_split
= PATTERN (m_split
);
3385 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3386 if (insn_code_number
>= 0)
3389 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3390 && (next_real_insn (i2
) == i3
3391 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3394 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3395 newi2pat
= PATTERN (m_split
);
3397 i3set
= single_set (NEXT_INSN (m_split
));
3398 i2set
= single_set (m_split
);
3400 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3402 /* If I2 or I3 has multiple SETs, we won't know how to track
3403 register status, so don't use these insns. If I2's destination
3404 is used between I2 and I3, we also can't use these insns. */
3406 if (i2_code_number
>= 0 && i2set
&& i3set
3407 && (next_real_insn (i2
) == i3
3408 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3409 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3411 if (insn_code_number
>= 0)
3414 /* It is possible that both insns now set the destination of I3.
3415 If so, we must show an extra use of it. */
3417 if (insn_code_number
>= 0)
3419 rtx new_i3_dest
= SET_DEST (i3set
);
3420 rtx new_i2_dest
= SET_DEST (i2set
);
3422 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3423 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3424 || GET_CODE (new_i3_dest
) == SUBREG
)
3425 new_i3_dest
= XEXP (new_i3_dest
, 0);
3427 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3428 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3429 || GET_CODE (new_i2_dest
) == SUBREG
)
3430 new_i2_dest
= XEXP (new_i2_dest
, 0);
3432 if (REG_P (new_i3_dest
)
3433 && REG_P (new_i2_dest
)
3434 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3435 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3439 /* If we can split it and use I2DEST, go ahead and see if that
3440 helps things be recognized. Verify that none of the registers
3441 are set between I2 and I3. */
3442 if (insn_code_number
< 0
3443 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3447 /* We need I2DEST in the proper mode. If it is a hard register
3448 or the only use of a pseudo, we can change its mode.
3449 Make sure we don't change a hard register to have a mode that
3450 isn't valid for it, or change the number of registers. */
3451 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3452 || GET_MODE (*split
) == VOIDmode
3453 || can_change_dest_mode (i2dest
, added_sets_2
,
3455 && (next_real_insn (i2
) == i3
3456 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3457 /* We can't overwrite I2DEST if its value is still used by
3459 && ! reg_referenced_p (i2dest
, newpat
))
3461 rtx newdest
= i2dest
;
3462 enum rtx_code split_code
= GET_CODE (*split
);
3463 enum machine_mode split_mode
= GET_MODE (*split
);
3464 bool subst_done
= false;
3465 newi2pat
= NULL_RTX
;
3469 /* *SPLIT may be part of I2SRC, so make sure we have the
3470 original expression around for later debug processing.
3471 We should not need I2SRC any more in other cases. */
3472 if (MAY_HAVE_DEBUG_INSNS
)
3473 i2src
= copy_rtx (i2src
);
3477 /* Get NEWDEST as a register in the proper mode. We have already
3478 validated that we can do this. */
3479 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3481 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3482 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3485 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3486 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3490 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491 an ASHIFT. This can occur if it was inside a PLUS and hence
3492 appeared to be a memory address. This is a kludge. */
3493 if (split_code
== MULT
3494 && CONST_INT_P (XEXP (*split
, 1))
3495 && INTVAL (XEXP (*split
, 1)) > 0
3496 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
3498 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3499 XEXP (*split
, 0), GEN_INT (i
)));
3500 /* Update split_code because we may not have a multiply
3502 split_code
= GET_CODE (*split
);
3505 #ifdef INSN_SCHEDULING
3506 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507 be written as a ZERO_EXTEND. */
3508 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3510 #ifdef LOAD_EXTEND_OP
3511 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512 what it really is. */
3513 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3515 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3516 SUBREG_REG (*split
)));
3519 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3520 SUBREG_REG (*split
)));
3524 /* Attempt to split binary operators using arithmetic identities. */
3525 if (BINARY_P (SET_SRC (newpat
))
3526 && split_mode
== GET_MODE (SET_SRC (newpat
))
3527 && ! side_effects_p (SET_SRC (newpat
)))
3529 rtx setsrc
= SET_SRC (newpat
);
3530 enum machine_mode mode
= GET_MODE (setsrc
);
3531 enum rtx_code code
= GET_CODE (setsrc
);
3532 rtx src_op0
= XEXP (setsrc
, 0);
3533 rtx src_op1
= XEXP (setsrc
, 1);
3535 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3536 if (rtx_equal_p (src_op0
, src_op1
))
3538 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3539 SUBST (XEXP (setsrc
, 0), newdest
);
3540 SUBST (XEXP (setsrc
, 1), newdest
);
3543 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3544 else if ((code
== PLUS
|| code
== MULT
)
3545 && GET_CODE (src_op0
) == code
3546 && GET_CODE (XEXP (src_op0
, 0)) == code
3547 && (INTEGRAL_MODE_P (mode
)
3548 || (FLOAT_MODE_P (mode
)
3549 && flag_unsafe_math_optimizations
)))
3551 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3552 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3553 rtx r
= XEXP (src_op0
, 1);
3556 /* Split both "((X op Y) op X) op Y" and
3557 "((X op Y) op Y) op X" as "T op T" where T is
3559 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3560 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3562 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3564 SUBST (XEXP (setsrc
, 0), newdest
);
3565 SUBST (XEXP (setsrc
, 1), newdest
);
3568 /* Split "((X op X) op Y) op Y)" as "T op T" where
3570 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3572 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3573 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3574 SUBST (XEXP (setsrc
, 0), newdest
);
3575 SUBST (XEXP (setsrc
, 1), newdest
);
3583 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3584 SUBST (*split
, newdest
);
3587 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3589 /* recog_for_combine might have added CLOBBERs to newi2pat.
3590 Make sure NEWPAT does not depend on the clobbered regs. */
3591 if (GET_CODE (newi2pat
) == PARALLEL
)
3592 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3593 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3595 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3596 if (reg_overlap_mentioned_p (reg
, newpat
))
3603 /* If the split point was a MULT and we didn't have one before,
3604 don't use one now. */
3605 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3606 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3610 /* Check for a case where we loaded from memory in a narrow mode and
3611 then sign extended it, but we need both registers. In that case,
3612 we have a PARALLEL with both loads from the same memory location.
3613 We can split this into a load from memory followed by a register-register
3614 copy. This saves at least one insn, more if register allocation can
3617 We cannot do this if the destination of the first assignment is a
3618 condition code register or cc0. We eliminate this case by making sure
3619 the SET_DEST and SET_SRC have the same mode.
3621 We cannot do this if the destination of the second assignment is
3622 a register that we have already assumed is zero-extended. Similarly
3623 for a SUBREG of such a register. */
3625 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3626 && GET_CODE (newpat
) == PARALLEL
3627 && XVECLEN (newpat
, 0) == 2
3628 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3629 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3630 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3631 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3632 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3633 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3634 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3635 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3637 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3638 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3639 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3641 && VEC_index (reg_stat_type
, reg_stat
,
3642 REGNO (temp
))->nonzero_bits
!= 0
3643 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3644 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3645 && (VEC_index (reg_stat_type
, reg_stat
,
3646 REGNO (temp
))->nonzero_bits
3647 != GET_MODE_MASK (word_mode
))))
3648 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3649 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3651 && VEC_index (reg_stat_type
, reg_stat
,
3652 REGNO (temp
))->nonzero_bits
!= 0
3653 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3654 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3655 && (VEC_index (reg_stat_type
, reg_stat
,
3656 REGNO (temp
))->nonzero_bits
3657 != GET_MODE_MASK (word_mode
)))))
3658 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3659 SET_SRC (XVECEXP (newpat
, 0, 1)))
3660 && ! find_reg_note (i3
, REG_UNUSED
,
3661 SET_DEST (XVECEXP (newpat
, 0, 0))))
3665 newi2pat
= XVECEXP (newpat
, 0, 0);
3666 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3667 newpat
= XVECEXP (newpat
, 0, 1);
3668 SUBST (SET_SRC (newpat
),
3669 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3670 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3672 if (i2_code_number
>= 0)
3673 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3675 if (insn_code_number
>= 0)
3679 /* Similarly, check for a case where we have a PARALLEL of two independent
3680 SETs but we started with three insns. In this case, we can do the sets
3681 as two separate insns. This case occurs when some SET allows two
3682 other insns to combine, but the destination of that SET is still live. */
3684 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3685 && GET_CODE (newpat
) == PARALLEL
3686 && XVECLEN (newpat
, 0) == 2
3687 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3688 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3689 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3690 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3691 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3692 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3693 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3694 XVECEXP (newpat
, 0, 0))
3695 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3696 XVECEXP (newpat
, 0, 1))
3697 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3698 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3700 /* Normally, it doesn't matter which of the two is done first,
3701 but the one that references cc0 can't be the second, and
3702 one which uses any regs/memory set in between i2 and i3 can't
3704 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3707 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3711 newi2pat
= XVECEXP (newpat
, 0, 1);
3712 newpat
= XVECEXP (newpat
, 0, 0);
3714 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3717 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3721 newi2pat
= XVECEXP (newpat
, 0, 0);
3722 newpat
= XVECEXP (newpat
, 0, 1);
3730 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3732 if (i2_code_number
>= 0)
3734 /* recog_for_combine might have added CLOBBERs to newi2pat.
3735 Make sure NEWPAT does not depend on the clobbered regs. */
3736 if (GET_CODE (newi2pat
) == PARALLEL
)
3738 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3739 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3741 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3742 if (reg_overlap_mentioned_p (reg
, newpat
))
3750 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3754 /* If it still isn't recognized, fail and change things back the way they
3756 if ((insn_code_number
< 0
3757 /* Is the result a reasonable ASM_OPERANDS? */
3758 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3764 /* If we had to change another insn, make sure it is valid also. */
3765 if (undobuf
.other_insn
)
3767 CLEAR_HARD_REG_SET (newpat_used_regs
);
3769 other_pat
= PATTERN (undobuf
.other_insn
);
3770 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3773 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3781 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3782 they are adjacent to each other or not. */
3784 rtx p
= prev_nonnote_insn (i3
);
3785 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3786 && sets_cc0_p (newi2pat
))
3794 /* Only allow this combination if insn_rtx_costs reports that the
3795 replacement instructions are cheaper than the originals. */
3796 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3802 if (MAY_HAVE_DEBUG_INSNS
)
3806 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3807 if (undo
->kind
== UNDO_MODE
)
3809 rtx reg
= *undo
->where
.r
;
3810 enum machine_mode new_mode
= GET_MODE (reg
);
3811 enum machine_mode old_mode
= undo
->old_contents
.m
;
3813 /* Temporarily revert mode back. */
3814 adjust_reg_mode (reg
, old_mode
);
3816 if (reg
== i2dest
&& i2scratch
)
3818 /* If we used i2dest as a scratch register with a
3819 different mode, substitute it for the original
3820 i2src while its original mode is temporarily
3821 restored, and then clear i2scratch so that we don't
3822 do it again later. */
3823 propagate_for_debug (i2
, i3
, reg
, i2src
, false);
3825 /* Put back the new mode. */
3826 adjust_reg_mode (reg
, new_mode
);
3830 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3841 last
= undobuf
.other_insn
;
3845 /* We're dealing with a reg that changed mode but not
3846 meaning, so we want to turn it into a subreg for
3847 the new mode. However, because of REG sharing and
3848 because its mode had already changed, we have to do
3849 it in two steps. First, replace any debug uses of
3850 reg, with its original mode temporarily restored,
3851 with this copy we have created; then, replace the
3852 copy with the SUBREG of the original shared reg,
3853 once again changed to the new mode. */
3854 propagate_for_debug (first
, last
, reg
, tempreg
, false);
3855 adjust_reg_mode (reg
, new_mode
);
3856 propagate_for_debug (first
, last
, tempreg
,
3857 lowpart_subreg (old_mode
, reg
, new_mode
),
3863 /* If we will be able to accept this, we have made a
3864 change to the destination of I3. This requires us to
3865 do a few adjustments. */
3867 if (changed_i3_dest
)
3869 PATTERN (i3
) = newpat
;
3870 adjust_for_new_dest (i3
);
3873 /* We now know that we can do this combination. Merge the insns and
3874 update the status of registers and LOG_LINKS. */
3876 if (undobuf
.other_insn
)
3880 PATTERN (undobuf
.other_insn
) = other_pat
;
3882 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3883 are still valid. Then add any non-duplicate notes added by
3884 recog_for_combine. */
3885 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3887 next
= XEXP (note
, 1);
3889 if (REG_NOTE_KIND (note
) == REG_UNUSED
3890 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3891 remove_note (undobuf
.other_insn
, note
);
3894 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3895 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3905 /* I3 now uses what used to be its destination and which is now
3906 I2's destination. This requires us to do a few adjustments. */
3907 PATTERN (i3
) = newpat
;
3908 adjust_for_new_dest (i3
);
3910 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3913 However, some later insn might be using I2's dest and have
3914 a LOG_LINK pointing at I3. We must remove this link.
3915 The simplest way to remove the link is to point it at I1,
3916 which we know will be a NOTE. */
3918 /* newi2pat is usually a SET here; however, recog_for_combine might
3919 have added some clobbers. */
3920 if (GET_CODE (newi2pat
) == PARALLEL
)
3921 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3923 ni2dest
= SET_DEST (newi2pat
);
3925 for (insn
= NEXT_INSN (i3
);
3926 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3927 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3928 insn
= NEXT_INSN (insn
))
3930 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3932 for (link
= LOG_LINKS (insn
); link
;
3933 link
= XEXP (link
, 1))
3934 if (XEXP (link
, 0) == i3
)
3935 XEXP (link
, 0) = i1
;
3943 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3944 rtx i3links
, i2links
, i1links
= 0, i0links
= 0;
3948 /* Compute which registers we expect to eliminate. newi2pat may be setting
3949 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3950 same as i3dest, in which case newi2pat may be setting i1dest. */
3951 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3952 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3955 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3956 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3959 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3960 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3964 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3966 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3967 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3969 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3971 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
3973 /* Ensure that we do not have something that should not be shared but
3974 occurs multiple times in the new insns. Check this by first
3975 resetting all the `used' flags and then copying anything is shared. */
3977 reset_used_flags (i3notes
);
3978 reset_used_flags (i2notes
);
3979 reset_used_flags (i1notes
);
3980 reset_used_flags (i0notes
);
3981 reset_used_flags (newpat
);
3982 reset_used_flags (newi2pat
);
3983 if (undobuf
.other_insn
)
3984 reset_used_flags (PATTERN (undobuf
.other_insn
));
3986 i3notes
= copy_rtx_if_shared (i3notes
);
3987 i2notes
= copy_rtx_if_shared (i2notes
);
3988 i1notes
= copy_rtx_if_shared (i1notes
);
3989 i0notes
= copy_rtx_if_shared (i0notes
);
3990 newpat
= copy_rtx_if_shared (newpat
);
3991 newi2pat
= copy_rtx_if_shared (newi2pat
);
3992 if (undobuf
.other_insn
)
3993 reset_used_flags (PATTERN (undobuf
.other_insn
));
3995 INSN_CODE (i3
) = insn_code_number
;
3996 PATTERN (i3
) = newpat
;
3998 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4000 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4002 reset_used_flags (call_usage
);
4003 call_usage
= copy_rtx (call_usage
);
4007 /* I2SRC must still be meaningful at this point. Some splitting
4008 operations can invalidate I2SRC, but those operations do not
4011 replace_rtx (call_usage
, i2dest
, i2src
);
4015 replace_rtx (call_usage
, i1dest
, i1src
);
4017 replace_rtx (call_usage
, i0dest
, i0src
);
4019 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4022 if (undobuf
.other_insn
)
4023 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4025 /* We had one special case above where I2 had more than one set and
4026 we replaced a destination of one of those sets with the destination
4027 of I3. In that case, we have to update LOG_LINKS of insns later
4028 in this basic block. Note that this (expensive) case is rare.
4030 Also, in this case, we must pretend that all REG_NOTEs for I2
4031 actually came from I3, so that REG_UNUSED notes from I2 will be
4032 properly handled. */
4034 if (i3_subst_into_i2
)
4036 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4037 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4038 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4039 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4040 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4041 && ! find_reg_note (i2
, REG_UNUSED
,
4042 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4043 for (temp
= NEXT_INSN (i2
);
4044 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4045 || BB_HEAD (this_basic_block
) != temp
);
4046 temp
= NEXT_INSN (temp
))
4047 if (temp
!= i3
&& INSN_P (temp
))
4048 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
4049 if (XEXP (link
, 0) == i2
)
4050 XEXP (link
, 0) = i3
;
4055 while (XEXP (link
, 1))
4056 link
= XEXP (link
, 1);
4057 XEXP (link
, 1) = i2notes
;
4071 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4072 propagate_for_debug (i2
, i3
, i2dest
, i2src
, false);
4073 INSN_CODE (i2
) = i2_code_number
;
4074 PATTERN (i2
) = newi2pat
;
4078 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4079 propagate_for_debug (i2
, i3
, i2dest
, i2src
, i3_subst_into_i2
);
4080 SET_INSN_DELETED (i2
);
4087 if (MAY_HAVE_DEBUG_INSNS
)
4088 propagate_for_debug (i1
, i3
, i1dest
, i1src
, false);
4089 SET_INSN_DELETED (i1
);
4096 if (MAY_HAVE_DEBUG_INSNS
)
4097 propagate_for_debug (i0
, i3
, i0dest
, i0src
, false);
4098 SET_INSN_DELETED (i0
);
4101 /* Get death notes for everything that is now used in either I3 or
4102 I2 and used to die in a previous insn. If we built two new
4103 patterns, move from I1 to I2 then I2 to I3 so that we get the
4104 proper movement on registers that I2 modifies. */
4107 from_luid
= DF_INSN_LUID (i0
);
4109 from_luid
= DF_INSN_LUID (i1
);
4111 from_luid
= DF_INSN_LUID (i2
);
4113 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4114 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4116 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4118 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4119 elim_i2
, elim_i1
, elim_i0
);
4121 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4122 elim_i2
, elim_i1
, elim_i0
);
4124 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4125 elim_i2
, elim_i1
, elim_i0
);
4127 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4128 elim_i2
, elim_i1
, elim_i0
);
4130 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4131 elim_i2
, elim_i1
, elim_i0
);
4133 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4134 know these are REG_UNUSED and want them to go to the desired insn,
4135 so we always pass it as i3. */
4137 if (newi2pat
&& new_i2_notes
)
4138 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4142 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4145 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4146 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4147 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4148 in that case, it might delete I2. Similarly for I2 and I1.
4149 Show an additional death due to the REG_DEAD note we make here. If
4150 we discard it in distribute_notes, we will decrement it again. */
4154 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4155 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4157 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
, elim_i0
);
4159 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4161 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4162 elim_i2
, elim_i1
, elim_i0
);
4165 if (i2dest_in_i2src
)
4167 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4168 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4169 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4170 NULL_RTX
, NULL_RTX
);
4172 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4173 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4176 if (i1dest_in_i1src
)
4178 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4179 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4180 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4181 NULL_RTX
, NULL_RTX
);
4183 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4184 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4187 if (i0dest_in_i0src
)
4189 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4190 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4191 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4192 NULL_RTX
, NULL_RTX
);
4194 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4195 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4198 distribute_links (i3links
);
4199 distribute_links (i2links
);
4200 distribute_links (i1links
);
4201 distribute_links (i0links
);
4206 rtx i2_insn
= 0, i2_val
= 0, set
;
4208 /* The insn that used to set this register doesn't exist, and
4209 this life of the register may not exist either. See if one of
4210 I3's links points to an insn that sets I2DEST. If it does,
4211 that is now the last known value for I2DEST. If we don't update
4212 this and I2 set the register to a value that depended on its old
4213 contents, we will get confused. If this insn is used, thing
4214 will be set correctly in combine_instructions. */
4216 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4217 if ((set
= single_set (XEXP (link
, 0))) != 0
4218 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4219 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
4221 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4223 /* If the reg formerly set in I2 died only once and that was in I3,
4224 zero its use count so it won't make `reload' do any work. */
4226 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4227 && ! i2dest_in_i2src
)
4229 regno
= REGNO (i2dest
);
4230 INC_REG_N_SETS (regno
, -1);
4234 if (i1
&& REG_P (i1dest
))
4237 rtx i1_insn
= 0, i1_val
= 0, set
;
4239 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4240 if ((set
= single_set (XEXP (link
, 0))) != 0
4241 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4242 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
4244 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4246 regno
= REGNO (i1dest
);
4247 if (! added_sets_1
&& ! i1dest_in_i1src
)
4248 INC_REG_N_SETS (regno
, -1);
4251 if (i0
&& REG_P (i0dest
))
4254 rtx i0_insn
= 0, i0_val
= 0, set
;
4256 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4257 if ((set
= single_set (XEXP (link
, 0))) != 0
4258 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4259 i0_insn
= XEXP (link
, 0), i0_val
= SET_SRC (set
);
4261 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4263 regno
= REGNO (i0dest
);
4264 if (! added_sets_0
&& ! i0dest_in_i0src
)
4265 INC_REG_N_SETS (regno
, -1);
4268 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4269 been made to this insn. The order of
4270 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4271 can affect nonzero_bits of newpat */
4273 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4274 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4277 if (undobuf
.other_insn
!= NULL_RTX
)
4281 fprintf (dump_file
, "modifying other_insn ");
4282 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4284 df_insn_rescan (undobuf
.other_insn
);
4287 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4291 fprintf (dump_file
, "modifying insn i1 ");
4292 dump_insn_slim (dump_file
, i0
);
4294 df_insn_rescan (i0
);
4297 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4301 fprintf (dump_file
, "modifying insn i1 ");
4302 dump_insn_slim (dump_file
, i1
);
4304 df_insn_rescan (i1
);
4307 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4311 fprintf (dump_file
, "modifying insn i2 ");
4312 dump_insn_slim (dump_file
, i2
);
4314 df_insn_rescan (i2
);
4317 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4321 fprintf (dump_file
, "modifying insn i3 ");
4322 dump_insn_slim (dump_file
, i3
);
4324 df_insn_rescan (i3
);
4327 /* Set new_direct_jump_p if a new return or simple jump instruction
4328 has been created. Adjust the CFG accordingly. */
4330 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4332 *new_direct_jump_p
= 1;
4333 mark_jump_label (PATTERN (i3
), i3
, 0);
4334 update_cfg_for_uncondjump (i3
);
4337 if (undobuf
.other_insn
!= NULL_RTX
4338 && (returnjump_p (undobuf
.other_insn
)
4339 || any_uncondjump_p (undobuf
.other_insn
)))
4341 *new_direct_jump_p
= 1;
4342 update_cfg_for_uncondjump (undobuf
.other_insn
);
4345 /* A noop might also need cleaning up of CFG, if it comes from the
4346 simplification of a jump. */
4347 if (GET_CODE (newpat
) == SET
4348 && SET_SRC (newpat
) == pc_rtx
4349 && SET_DEST (newpat
) == pc_rtx
)
4351 *new_direct_jump_p
= 1;
4352 update_cfg_for_uncondjump (i3
);
4355 combine_successes
++;
4358 if (added_links_insn
4359 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4360 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4361 return added_links_insn
;
4363 return newi2pat
? i2
: i3
;
4366 /* Undo all the modifications recorded in undobuf. */
4371 struct undo
*undo
, *next
;
4373 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4379 *undo
->where
.r
= undo
->old_contents
.r
;
4382 *undo
->where
.i
= undo
->old_contents
.i
;
4385 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4391 undo
->next
= undobuf
.frees
;
4392 undobuf
.frees
= undo
;
4398 /* We've committed to accepting the changes we made. Move all
4399 of the undos to the free list. */
4404 struct undo
*undo
, *next
;
4406 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4409 undo
->next
= undobuf
.frees
;
4410 undobuf
.frees
= undo
;
4415 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4416 where we have an arithmetic expression and return that point. LOC will
4419 try_combine will call this function to see if an insn can be split into
4423 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4426 enum rtx_code code
= GET_CODE (x
);
4428 unsigned HOST_WIDE_INT len
= 0;
4429 HOST_WIDE_INT pos
= 0;
4431 rtx inner
= NULL_RTX
;
4433 /* First special-case some codes. */
4437 #ifdef INSN_SCHEDULING
4438 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4440 if (MEM_P (SUBREG_REG (x
)))
4443 return find_split_point (&SUBREG_REG (x
), insn
, false);
4447 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4448 using LO_SUM and HIGH. */
4449 if (GET_CODE (XEXP (x
, 0)) == CONST
4450 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4452 enum machine_mode address_mode
4453 = targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (x
));
4456 gen_rtx_LO_SUM (address_mode
,
4457 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4459 return &XEXP (XEXP (x
, 0), 0);
4463 /* If we have a PLUS whose second operand is a constant and the
4464 address is not valid, perhaps will can split it up using
4465 the machine-specific way to split large constants. We use
4466 the first pseudo-reg (one of the virtual regs) as a placeholder;
4467 it will not remain in the result. */
4468 if (GET_CODE (XEXP (x
, 0)) == PLUS
4469 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4470 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4471 MEM_ADDR_SPACE (x
)))
4473 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4474 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4478 /* This should have produced two insns, each of which sets our
4479 placeholder. If the source of the second is a valid address,
4480 we can make put both sources together and make a split point
4484 && NEXT_INSN (seq
) != NULL_RTX
4485 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4486 && NONJUMP_INSN_P (seq
)
4487 && GET_CODE (PATTERN (seq
)) == SET
4488 && SET_DEST (PATTERN (seq
)) == reg
4489 && ! reg_mentioned_p (reg
,
4490 SET_SRC (PATTERN (seq
)))
4491 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4492 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4493 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4494 && memory_address_addr_space_p
4495 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4496 MEM_ADDR_SPACE (x
)))
4498 rtx src1
= SET_SRC (PATTERN (seq
));
4499 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4501 /* Replace the placeholder in SRC2 with SRC1. If we can
4502 find where in SRC2 it was placed, that can become our
4503 split point and we can replace this address with SRC2.
4504 Just try two obvious places. */
4506 src2
= replace_rtx (src2
, reg
, src1
);
4508 if (XEXP (src2
, 0) == src1
)
4509 split
= &XEXP (src2
, 0);
4510 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4511 && XEXP (XEXP (src2
, 0), 0) == src1
)
4512 split
= &XEXP (XEXP (src2
, 0), 0);
4516 SUBST (XEXP (x
, 0), src2
);
4521 /* If that didn't work, perhaps the first operand is complex and
4522 needs to be computed separately, so make a split point there.
4523 This will occur on machines that just support REG + CONST
4524 and have a constant moved through some previous computation. */
4526 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4527 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4528 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4529 return &XEXP (XEXP (x
, 0), 0);
4532 /* If we have a PLUS whose first operand is complex, try computing it
4533 separately by making a split there. */
4534 if (GET_CODE (XEXP (x
, 0)) == PLUS
4535 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4537 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4538 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4539 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4540 return &XEXP (XEXP (x
, 0), 0);
4545 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4546 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4547 we need to put the operand into a register. So split at that
4550 if (SET_DEST (x
) == cc0_rtx
4551 && GET_CODE (SET_SRC (x
)) != COMPARE
4552 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4553 && !OBJECT_P (SET_SRC (x
))
4554 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4555 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4556 return &SET_SRC (x
);
4559 /* See if we can split SET_SRC as it stands. */
4560 split
= find_split_point (&SET_SRC (x
), insn
, true);
4561 if (split
&& split
!= &SET_SRC (x
))
4564 /* See if we can split SET_DEST as it stands. */
4565 split
= find_split_point (&SET_DEST (x
), insn
, false);
4566 if (split
&& split
!= &SET_DEST (x
))
4569 /* See if this is a bitfield assignment with everything constant. If
4570 so, this is an IOR of an AND, so split it into that. */
4571 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4572 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
4573 <= HOST_BITS_PER_WIDE_INT
)
4574 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4575 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4576 && CONST_INT_P (SET_SRC (x
))
4577 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4578 + INTVAL (XEXP (SET_DEST (x
), 2)))
4579 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
4580 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4582 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4583 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4584 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4585 rtx dest
= XEXP (SET_DEST (x
), 0);
4586 enum machine_mode mode
= GET_MODE (dest
);
4587 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
4590 if (BITS_BIG_ENDIAN
)
4591 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
4593 or_mask
= gen_int_mode (src
<< pos
, mode
);
4596 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4599 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4601 simplify_gen_binary (IOR
, mode
,
4602 simplify_gen_binary (AND
, mode
,
4607 SUBST (SET_DEST (x
), dest
);
4609 split
= find_split_point (&SET_SRC (x
), insn
, true);
4610 if (split
&& split
!= &SET_SRC (x
))
4614 /* Otherwise, see if this is an operation that we can split into two.
4615 If so, try to split that. */
4616 code
= GET_CODE (SET_SRC (x
));
4621 /* If we are AND'ing with a large constant that is only a single
4622 bit and the result is only being used in a context where we
4623 need to know if it is zero or nonzero, replace it with a bit
4624 extraction. This will avoid the large constant, which might
4625 have taken more than one insn to make. If the constant were
4626 not a valid argument to the AND but took only one insn to make,
4627 this is no worse, but if it took more than one insn, it will
4630 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4631 && REG_P (XEXP (SET_SRC (x
), 0))
4632 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4633 && REG_P (SET_DEST (x
))
4634 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4635 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4636 && XEXP (*split
, 0) == SET_DEST (x
)
4637 && XEXP (*split
, 1) == const0_rtx
)
4639 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4640 XEXP (SET_SRC (x
), 0),
4641 pos
, NULL_RTX
, 1, 1, 0, 0);
4642 if (extraction
!= 0)
4644 SUBST (SET_SRC (x
), extraction
);
4645 return find_split_point (loc
, insn
, false);
4651 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4652 is known to be on, this can be converted into a NEG of a shift. */
4653 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4654 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4655 && 1 <= (pos
= exact_log2
4656 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4657 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4659 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4663 gen_rtx_LSHIFTRT (mode
,
4664 XEXP (SET_SRC (x
), 0),
4667 split
= find_split_point (&SET_SRC (x
), insn
, true);
4668 if (split
&& split
!= &SET_SRC (x
))
4674 inner
= XEXP (SET_SRC (x
), 0);
4676 /* We can't optimize if either mode is a partial integer
4677 mode as we don't know how many bits are significant
4679 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4680 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4684 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
4690 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4691 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4693 inner
= XEXP (SET_SRC (x
), 0);
4694 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4695 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4697 if (BITS_BIG_ENDIAN
)
4698 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
4699 unsignedp
= (code
== ZERO_EXTRACT
);
4707 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
4709 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4711 /* For unsigned, we have a choice of a shift followed by an
4712 AND or two shifts. Use two shifts for field sizes where the
4713 constant might be too large. We assume here that we can
4714 always at least get 8-bit constants in an AND insn, which is
4715 true for every current RISC. */
4717 if (unsignedp
&& len
<= 8)
4722 (mode
, gen_lowpart (mode
, inner
),
4724 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
4726 split
= find_split_point (&SET_SRC (x
), insn
, true);
4727 if (split
&& split
!= &SET_SRC (x
))
4734 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4735 gen_rtx_ASHIFT (mode
,
4736 gen_lowpart (mode
, inner
),
4737 GEN_INT (GET_MODE_BITSIZE (mode
)
4739 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
4741 split
= find_split_point (&SET_SRC (x
), insn
, true);
4742 if (split
&& split
!= &SET_SRC (x
))
4747 /* See if this is a simple operation with a constant as the second
4748 operand. It might be that this constant is out of range and hence
4749 could be used as a split point. */
4750 if (BINARY_P (SET_SRC (x
))
4751 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4752 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4753 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4754 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4755 return &XEXP (SET_SRC (x
), 1);
4757 /* Finally, see if this is a simple operation with its first operand
4758 not in a register. The operation might require this operand in a
4759 register, so return it as a split point. We can always do this
4760 because if the first operand were another operation, we would have
4761 already found it as a split point. */
4762 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4763 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4764 return &XEXP (SET_SRC (x
), 0);
4770 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4771 it is better to write this as (not (ior A B)) so we can split it.
4772 Similarly for IOR. */
4773 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4776 gen_rtx_NOT (GET_MODE (x
),
4777 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4779 XEXP (XEXP (x
, 0), 0),
4780 XEXP (XEXP (x
, 1), 0))));
4781 return find_split_point (loc
, insn
, set_src
);
4784 /* Many RISC machines have a large set of logical insns. If the
4785 second operand is a NOT, put it first so we will try to split the
4786 other operand first. */
4787 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4789 rtx tem
= XEXP (x
, 0);
4790 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4791 SUBST (XEXP (x
, 1), tem
);
4797 /* Canonicalization can produce (minus A (mult B C)), where C is a
4798 constant. It may be better to try splitting (plus (mult B -C) A)
4799 instead if this isn't a multiply by a power of two. */
4800 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4801 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4802 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4804 enum machine_mode mode
= GET_MODE (x
);
4805 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4806 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4807 SUBST (*loc
, gen_rtx_PLUS (mode
, gen_rtx_MULT (mode
,
4808 XEXP (XEXP (x
, 1), 0),
4809 GEN_INT (other_int
)),
4811 return find_split_point (loc
, insn
, set_src
);
4814 /* Split at a multiply-accumulate instruction. However if this is
4815 the SET_SRC, we likely do not have such an instruction and it's
4816 worthless to try this split. */
4817 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4824 /* Otherwise, select our actions depending on our rtx class. */
4825 switch (GET_RTX_CLASS (code
))
4827 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4829 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4832 /* ... fall through ... */
4834 case RTX_COMM_ARITH
:
4836 case RTX_COMM_COMPARE
:
4837 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4840 /* ... fall through ... */
4842 /* Some machines have (and (shift ...) ...) insns. If X is not
4843 an AND, but XEXP (X, 0) is, use it as our split point. */
4844 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4845 return &XEXP (x
, 0);
4847 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4853 /* Otherwise, we don't have a split point. */
4858 /* Throughout X, replace FROM with TO, and return the result.
4859 The result is TO if X is FROM;
4860 otherwise the result is X, but its contents may have been modified.
4861 If they were modified, a record was made in undobuf so that
4862 undo_all will (among other things) return X to its original state.
4864 If the number of changes necessary is too much to record to undo,
4865 the excess changes are not made, so the result is invalid.
4866 The changes already made can still be undone.
4867 undobuf.num_undo is incremented for such changes, so by testing that
4868 the caller can tell whether the result is valid.
4870 `n_occurrences' is incremented each time FROM is replaced.
4872 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4874 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4875 by copying if `n_occurrences' is nonzero. */
4878 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
4880 enum rtx_code code
= GET_CODE (x
);
4881 enum machine_mode op0_mode
= VOIDmode
;
4886 /* Two expressions are equal if they are identical copies of a shared
4887 RTX or if they are both registers with the same register number
4890 #define COMBINE_RTX_EQUAL_P(X,Y) \
4892 || (REG_P (X) && REG_P (Y) \
4893 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4895 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4898 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4901 /* If X and FROM are the same register but different modes, they
4902 will not have been seen as equal above. However, the log links code
4903 will make a LOG_LINKS entry for that case. If we do nothing, we
4904 will try to rerecognize our original insn and, when it succeeds,
4905 we will delete the feeding insn, which is incorrect.
4907 So force this insn not to match in this (rare) case. */
4908 if (! in_dest
&& code
== REG
&& REG_P (from
)
4909 && reg_overlap_mentioned_p (x
, from
))
4910 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4912 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4913 of which may contain things that can be combined. */
4914 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4917 /* It is possible to have a subexpression appear twice in the insn.
4918 Suppose that FROM is a register that appears within TO.
4919 Then, after that subexpression has been scanned once by `subst',
4920 the second time it is scanned, TO may be found. If we were
4921 to scan TO here, we would find FROM within it and create a
4922 self-referent rtl structure which is completely wrong. */
4923 if (COMBINE_RTX_EQUAL_P (x
, to
))
4926 /* Parallel asm_operands need special attention because all of the
4927 inputs are shared across the arms. Furthermore, unsharing the
4928 rtl results in recognition failures. Failure to handle this case
4929 specially can result in circular rtl.
4931 Solve this by doing a normal pass across the first entry of the
4932 parallel, and only processing the SET_DESTs of the subsequent
4935 if (code
== PARALLEL
4936 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4937 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4939 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
4941 /* If this substitution failed, this whole thing fails. */
4942 if (GET_CODE (new_rtx
) == CLOBBER
4943 && XEXP (new_rtx
, 0) == const0_rtx
)
4946 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4948 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4950 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4953 && GET_CODE (dest
) != CC0
4954 && GET_CODE (dest
) != PC
)
4956 new_rtx
= subst (dest
, from
, to
, 0, unique_copy
);
4958 /* If this substitution failed, this whole thing fails. */
4959 if (GET_CODE (new_rtx
) == CLOBBER
4960 && XEXP (new_rtx
, 0) == const0_rtx
)
4963 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4969 len
= GET_RTX_LENGTH (code
);
4970 fmt
= GET_RTX_FORMAT (code
);
4972 /* We don't need to process a SET_DEST that is a register, CC0,
4973 or PC, so set up to skip this common case. All other cases
4974 where we want to suppress replacing something inside a
4975 SET_SRC are handled via the IN_DEST operand. */
4977 && (REG_P (SET_DEST (x
))
4978 || GET_CODE (SET_DEST (x
)) == CC0
4979 || GET_CODE (SET_DEST (x
)) == PC
))
4982 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4985 op0_mode
= GET_MODE (XEXP (x
, 0));
4987 for (i
= 0; i
< len
; i
++)
4992 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4994 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
4996 new_rtx
= (unique_copy
&& n_occurrences
4997 ? copy_rtx (to
) : to
);
5002 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0,
5005 /* If this substitution failed, this whole thing
5007 if (GET_CODE (new_rtx
) == CLOBBER
5008 && XEXP (new_rtx
, 0) == const0_rtx
)
5012 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5015 else if (fmt
[i
] == 'e')
5017 /* If this is a register being set, ignore it. */
5018 new_rtx
= XEXP (x
, i
);
5021 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5023 || code
== STRICT_LOW_PART
))
5026 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5028 /* In general, don't install a subreg involving two
5029 modes not tieable. It can worsen register
5030 allocation, and can even make invalid reload
5031 insns, since the reg inside may need to be copied
5032 from in the outside mode, and that may be invalid
5033 if it is an fp reg copied in integer mode.
5035 We allow two exceptions to this: It is valid if
5036 it is inside another SUBREG and the mode of that
5037 SUBREG and the mode of the inside of TO is
5038 tieable and it is valid if X is a SET that copies
5041 if (GET_CODE (to
) == SUBREG
5042 && ! MODES_TIEABLE_P (GET_MODE (to
),
5043 GET_MODE (SUBREG_REG (to
)))
5044 && ! (code
== SUBREG
5045 && MODES_TIEABLE_P (GET_MODE (x
),
5046 GET_MODE (SUBREG_REG (to
))))
5048 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5051 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5053 #ifdef CANNOT_CHANGE_MODE_CLASS
5056 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5057 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5060 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5063 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5067 /* If we are in a SET_DEST, suppress most cases unless we
5068 have gone inside a MEM, in which case we want to
5069 simplify the address. We assume here that things that
5070 are actually part of the destination have their inner
5071 parts in the first expression. This is true for SUBREG,
5072 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5073 things aside from REG and MEM that should appear in a
5075 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5077 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5078 || code
== ZERO_EXTRACT
))
5080 && i
== 0), unique_copy
);
5082 /* If we found that we will have to reject this combination,
5083 indicate that by returning the CLOBBER ourselves, rather than
5084 an expression containing it. This will speed things up as
5085 well as prevent accidents where two CLOBBERs are considered
5086 to be equal, thus producing an incorrect simplification. */
5088 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5091 if (GET_CODE (x
) == SUBREG
5092 && (CONST_INT_P (new_rtx
)
5093 || GET_CODE (new_rtx
) == CONST_DOUBLE
))
5095 enum machine_mode mode
= GET_MODE (x
);
5097 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5098 GET_MODE (SUBREG_REG (x
)),
5101 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5103 else if (CONST_INT_P (new_rtx
)
5104 && GET_CODE (x
) == ZERO_EXTEND
)
5106 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5107 new_rtx
, GET_MODE (XEXP (x
, 0)));
5111 SUBST (XEXP (x
, i
), new_rtx
);
5116 /* Check if we are loading something from the constant pool via float
5117 extension; in this case we would undo compress_float_constant
5118 optimization and degenerate constant load to an immediate value. */
5119 if (GET_CODE (x
) == FLOAT_EXTEND
5120 && MEM_P (XEXP (x
, 0))
5121 && MEM_READONLY_P (XEXP (x
, 0)))
5123 rtx tmp
= avoid_constant_pool_reference (x
);
5128 /* Try to simplify X. If the simplification changed the code, it is likely
5129 that further simplification will help, so loop, but limit the number
5130 of repetitions that will be performed. */
5132 for (i
= 0; i
< 4; i
++)
5134 /* If X is sufficiently simple, don't bother trying to do anything
5136 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5137 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
5139 if (GET_CODE (x
) == code
)
5142 code
= GET_CODE (x
);
5144 /* We no longer know the original mode of operand 0 since we
5145 have changed the form of X) */
5146 op0_mode
= VOIDmode
;
5152 /* Simplify X, a piece of RTL. We just operate on the expression at the
5153 outer level; call `subst' to simplify recursively. Return the new
5156 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5157 if we are inside a SET_DEST. */
5160 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
5162 enum rtx_code code
= GET_CODE (x
);
5163 enum machine_mode mode
= GET_MODE (x
);
5167 /* If this is a commutative operation, put a constant last and a complex
5168 expression first. We don't need to do this for comparisons here. */
5169 if (COMMUTATIVE_ARITH_P (x
)
5170 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5173 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5174 SUBST (XEXP (x
, 1), temp
);
5177 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5178 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5179 things. Check for cases where both arms are testing the same
5182 Don't do anything if all operands are very simple. */
5185 && ((!OBJECT_P (XEXP (x
, 0))
5186 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5187 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5188 || (!OBJECT_P (XEXP (x
, 1))
5189 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5190 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5192 && (!OBJECT_P (XEXP (x
, 0))
5193 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5194 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5196 rtx cond
, true_rtx
, false_rtx
;
5198 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5200 /* If everything is a comparison, what we have is highly unlikely
5201 to be simpler, so don't use it. */
5202 && ! (COMPARISON_P (x
)
5203 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5205 rtx cop1
= const0_rtx
;
5206 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5208 if (cond_code
== NE
&& COMPARISON_P (cond
))
5211 /* Simplify the alternative arms; this may collapse the true and
5212 false arms to store-flag values. Be careful to use copy_rtx
5213 here since true_rtx or false_rtx might share RTL with x as a
5214 result of the if_then_else_cond call above. */
5215 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5216 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5218 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5219 is unlikely to be simpler. */
5220 if (general_operand (true_rtx
, VOIDmode
)
5221 && general_operand (false_rtx
, VOIDmode
))
5223 enum rtx_code reversed
;
5225 /* Restarting if we generate a store-flag expression will cause
5226 us to loop. Just drop through in this case. */
5228 /* If the result values are STORE_FLAG_VALUE and zero, we can
5229 just make the comparison operation. */
5230 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5231 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5233 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5234 && ((reversed
= reversed_comparison_code_parts
5235 (cond_code
, cond
, cop1
, NULL
))
5237 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5240 /* Likewise, we can make the negate of a comparison operation
5241 if the result values are - STORE_FLAG_VALUE and zero. */
5242 else if (CONST_INT_P (true_rtx
)
5243 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5244 && false_rtx
== const0_rtx
)
5245 x
= simplify_gen_unary (NEG
, mode
,
5246 simplify_gen_relational (cond_code
,
5250 else if (CONST_INT_P (false_rtx
)
5251 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5252 && true_rtx
== const0_rtx
5253 && ((reversed
= reversed_comparison_code_parts
5254 (cond_code
, cond
, cop1
, NULL
))
5256 x
= simplify_gen_unary (NEG
, mode
,
5257 simplify_gen_relational (reversed
,
5262 return gen_rtx_IF_THEN_ELSE (mode
,
5263 simplify_gen_relational (cond_code
,
5268 true_rtx
, false_rtx
);
5270 code
= GET_CODE (x
);
5271 op0_mode
= VOIDmode
;
5276 /* Try to fold this expression in case we have constants that weren't
5279 switch (GET_RTX_CLASS (code
))
5282 if (op0_mode
== VOIDmode
)
5283 op0_mode
= GET_MODE (XEXP (x
, 0));
5284 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5287 case RTX_COMM_COMPARE
:
5289 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5290 if (cmp_mode
== VOIDmode
)
5292 cmp_mode
= GET_MODE (XEXP (x
, 1));
5293 if (cmp_mode
== VOIDmode
)
5294 cmp_mode
= op0_mode
;
5296 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5297 XEXP (x
, 0), XEXP (x
, 1));
5300 case RTX_COMM_ARITH
:
5302 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5304 case RTX_BITFIELD_OPS
:
5306 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5307 XEXP (x
, 1), XEXP (x
, 2));
5316 code
= GET_CODE (temp
);
5317 op0_mode
= VOIDmode
;
5318 mode
= GET_MODE (temp
);
5321 /* First see if we can apply the inverse distributive law. */
5322 if (code
== PLUS
|| code
== MINUS
5323 || code
== AND
|| code
== IOR
|| code
== XOR
)
5325 x
= apply_distributive_law (x
);
5326 code
= GET_CODE (x
);
5327 op0_mode
= VOIDmode
;
5330 /* If CODE is an associative operation not otherwise handled, see if we
5331 can associate some operands. This can win if they are constants or
5332 if they are logically related (i.e. (a & b) & a). */
5333 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5334 || code
== AND
|| code
== IOR
|| code
== XOR
5335 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5336 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5337 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5339 if (GET_CODE (XEXP (x
, 0)) == code
)
5341 rtx other
= XEXP (XEXP (x
, 0), 0);
5342 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5343 rtx inner_op1
= XEXP (x
, 1);
5346 /* Make sure we pass the constant operand if any as the second
5347 one if this is a commutative operation. */
5348 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5350 rtx tem
= inner_op0
;
5351 inner_op0
= inner_op1
;
5354 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5355 : code
== DIV
? MULT
5357 mode
, inner_op0
, inner_op1
);
5359 /* For commutative operations, try the other pair if that one
5361 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5363 other
= XEXP (XEXP (x
, 0), 1);
5364 inner
= simplify_binary_operation (code
, mode
,
5365 XEXP (XEXP (x
, 0), 0),
5370 return simplify_gen_binary (code
, mode
, other
, inner
);
5374 /* A little bit of algebraic simplification here. */
5378 /* Ensure that our address has any ASHIFTs converted to MULT in case
5379 address-recognizing predicates are called later. */
5380 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5381 SUBST (XEXP (x
, 0), temp
);
5385 if (op0_mode
== VOIDmode
)
5386 op0_mode
= GET_MODE (SUBREG_REG (x
));
5388 /* See if this can be moved to simplify_subreg. */
5389 if (CONSTANT_P (SUBREG_REG (x
))
5390 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5391 /* Don't call gen_lowpart if the inner mode
5392 is VOIDmode and we cannot simplify it, as SUBREG without
5393 inner mode is invalid. */
5394 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5395 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5396 return gen_lowpart (mode
, SUBREG_REG (x
));
5398 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5402 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5408 /* Don't change the mode of the MEM if that would change the meaning
5410 if (MEM_P (SUBREG_REG (x
))
5411 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5412 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
5413 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5415 /* Note that we cannot do any narrowing for non-constants since
5416 we might have been counting on using the fact that some bits were
5417 zero. We now do this in the SET. */
5422 temp
= expand_compound_operation (XEXP (x
, 0));
5424 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5425 replaced by (lshiftrt X C). This will convert
5426 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5428 if (GET_CODE (temp
) == ASHIFTRT
5429 && CONST_INT_P (XEXP (temp
, 1))
5430 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5431 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5432 INTVAL (XEXP (temp
, 1)));
5434 /* If X has only a single bit that might be nonzero, say, bit I, convert
5435 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5436 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5437 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5438 or a SUBREG of one since we'd be making the expression more
5439 complex if it was just a register. */
5442 && ! (GET_CODE (temp
) == SUBREG
5443 && REG_P (SUBREG_REG (temp
)))
5444 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5446 rtx temp1
= simplify_shift_const
5447 (NULL_RTX
, ASHIFTRT
, mode
,
5448 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5449 GET_MODE_BITSIZE (mode
) - 1 - i
),
5450 GET_MODE_BITSIZE (mode
) - 1 - i
);
5452 /* If all we did was surround TEMP with the two shifts, we
5453 haven't improved anything, so don't use it. Otherwise,
5454 we are better off with TEMP1. */
5455 if (GET_CODE (temp1
) != ASHIFTRT
5456 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5457 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5463 /* We can't handle truncation to a partial integer mode here
5464 because we don't know the real bitsize of the partial
5466 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5469 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5471 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5472 GET_MODE_MASK (mode
), 0));
5474 /* We can truncate a constant value and return it. */
5475 if (CONST_INT_P (XEXP (x
, 0)))
5476 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5478 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5479 whose value is a comparison can be replaced with a subreg if
5480 STORE_FLAG_VALUE permits. */
5481 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5482 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5483 && (temp
= get_last_value (XEXP (x
, 0)))
5484 && COMPARISON_P (temp
))
5485 return gen_lowpart (mode
, XEXP (x
, 0));
5489 /* (const (const X)) can become (const X). Do it this way rather than
5490 returning the inner CONST since CONST can be shared with a
5492 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5493 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5498 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5499 can add in an offset. find_split_point will split this address up
5500 again if it doesn't match. */
5501 if (GET_CODE (XEXP (x
, 0)) == HIGH
5502 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5508 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5509 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5510 bit-field and can be replaced by either a sign_extend or a
5511 sign_extract. The `and' may be a zero_extend and the two
5512 <c>, -<c> constants may be reversed. */
5513 if (GET_CODE (XEXP (x
, 0)) == XOR
5514 && CONST_INT_P (XEXP (x
, 1))
5515 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5516 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5517 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5518 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
5519 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5520 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5521 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5522 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5523 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5524 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5525 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5526 == (unsigned int) i
+ 1))))
5527 return simplify_shift_const
5528 (NULL_RTX
, ASHIFTRT
, mode
,
5529 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5530 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5531 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
5532 GET_MODE_BITSIZE (mode
) - (i
+ 1));
5534 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5535 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5536 the bitsize of the mode - 1. This allows simplification of
5537 "a = (b & 8) == 0;" */
5538 if (XEXP (x
, 1) == constm1_rtx
5539 && !REG_P (XEXP (x
, 0))
5540 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5541 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5542 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5543 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5544 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5545 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5546 GET_MODE_BITSIZE (mode
) - 1),
5547 GET_MODE_BITSIZE (mode
) - 1);
5549 /* If we are adding two things that have no bits in common, convert
5550 the addition into an IOR. This will often be further simplified,
5551 for example in cases like ((a & 1) + (a & 2)), which can
5554 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5555 && (nonzero_bits (XEXP (x
, 0), mode
)
5556 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5558 /* Try to simplify the expression further. */
5559 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5560 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
5562 /* If we could, great. If not, do not go ahead with the IOR
5563 replacement, since PLUS appears in many special purpose
5564 address arithmetic instructions. */
5565 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
5571 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5572 (and <foo> (const_int pow2-1)) */
5573 if (GET_CODE (XEXP (x
, 1)) == AND
5574 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5575 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5576 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5577 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5578 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5582 /* If we have (mult (plus A B) C), apply the distributive law and then
5583 the inverse distributive law to see if things simplify. This
5584 occurs mostly in addresses, often when unrolling loops. */
5586 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5588 rtx result
= distribute_and_simplify_rtx (x
, 0);
5593 /* Try simplify a*(b/c) as (a*b)/c. */
5594 if (FLOAT_MODE_P (mode
) && flag_associative_math
5595 && GET_CODE (XEXP (x
, 0)) == DIV
)
5597 rtx tem
= simplify_binary_operation (MULT
, mode
,
5598 XEXP (XEXP (x
, 0), 0),
5601 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5606 /* If this is a divide by a power of two, treat it as a shift if
5607 its first operand is a shift. */
5608 if (CONST_INT_P (XEXP (x
, 1))
5609 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
5610 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5611 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5612 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5613 || GET_CODE (XEXP (x
, 0)) == ROTATE
5614 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5615 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5619 case GT
: case GTU
: case GE
: case GEU
:
5620 case LT
: case LTU
: case LE
: case LEU
:
5621 case UNEQ
: case LTGT
:
5622 case UNGT
: case UNGE
:
5623 case UNLT
: case UNLE
:
5624 case UNORDERED
: case ORDERED
:
5625 /* If the first operand is a condition code, we can't do anything
5627 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5628 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5629 && ! CC0_P (XEXP (x
, 0))))
5631 rtx op0
= XEXP (x
, 0);
5632 rtx op1
= XEXP (x
, 1);
5633 enum rtx_code new_code
;
5635 if (GET_CODE (op0
) == COMPARE
)
5636 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5638 /* Simplify our comparison, if possible. */
5639 new_code
= simplify_comparison (code
, &op0
, &op1
);
5641 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5642 if only the low-order bit is possibly nonzero in X (such as when
5643 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5644 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5645 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5648 Remove any ZERO_EXTRACT we made when thinking this was a
5649 comparison. It may now be simpler to use, e.g., an AND. If a
5650 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5651 the call to make_compound_operation in the SET case. */
5653 if (STORE_FLAG_VALUE
== 1
5654 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5655 && op1
== const0_rtx
5656 && mode
== GET_MODE (op0
)
5657 && nonzero_bits (op0
, mode
) == 1)
5658 return gen_lowpart (mode
,
5659 expand_compound_operation (op0
));
5661 else if (STORE_FLAG_VALUE
== 1
5662 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5663 && op1
== const0_rtx
5664 && mode
== GET_MODE (op0
)
5665 && (num_sign_bit_copies (op0
, mode
)
5666 == GET_MODE_BITSIZE (mode
)))
5668 op0
= expand_compound_operation (op0
);
5669 return simplify_gen_unary (NEG
, mode
,
5670 gen_lowpart (mode
, op0
),
5674 else if (STORE_FLAG_VALUE
== 1
5675 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5676 && op1
== const0_rtx
5677 && mode
== GET_MODE (op0
)
5678 && nonzero_bits (op0
, mode
) == 1)
5680 op0
= expand_compound_operation (op0
);
5681 return simplify_gen_binary (XOR
, mode
,
5682 gen_lowpart (mode
, op0
),
5686 else if (STORE_FLAG_VALUE
== 1
5687 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5688 && op1
== const0_rtx
5689 && mode
== GET_MODE (op0
)
5690 && (num_sign_bit_copies (op0
, mode
)
5691 == GET_MODE_BITSIZE (mode
)))
5693 op0
= expand_compound_operation (op0
);
5694 return plus_constant (gen_lowpart (mode
, op0
), 1);
5697 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5699 if (STORE_FLAG_VALUE
== -1
5700 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5701 && op1
== const0_rtx
5702 && (num_sign_bit_copies (op0
, mode
)
5703 == GET_MODE_BITSIZE (mode
)))
5704 return gen_lowpart (mode
,
5705 expand_compound_operation (op0
));
5707 else if (STORE_FLAG_VALUE
== -1
5708 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5709 && op1
== const0_rtx
5710 && mode
== GET_MODE (op0
)
5711 && nonzero_bits (op0
, mode
) == 1)
5713 op0
= expand_compound_operation (op0
);
5714 return simplify_gen_unary (NEG
, mode
,
5715 gen_lowpart (mode
, op0
),
5719 else if (STORE_FLAG_VALUE
== -1
5720 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5721 && op1
== const0_rtx
5722 && mode
== GET_MODE (op0
)
5723 && (num_sign_bit_copies (op0
, mode
)
5724 == GET_MODE_BITSIZE (mode
)))
5726 op0
= expand_compound_operation (op0
);
5727 return simplify_gen_unary (NOT
, mode
,
5728 gen_lowpart (mode
, op0
),
5732 /* If X is 0/1, (eq X 0) is X-1. */
5733 else if (STORE_FLAG_VALUE
== -1
5734 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5735 && op1
== const0_rtx
5736 && mode
== GET_MODE (op0
)
5737 && nonzero_bits (op0
, mode
) == 1)
5739 op0
= expand_compound_operation (op0
);
5740 return plus_constant (gen_lowpart (mode
, op0
), -1);
5743 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5744 one bit that might be nonzero, we can convert (ne x 0) to
5745 (ashift x c) where C puts the bit in the sign bit. Remove any
5746 AND with STORE_FLAG_VALUE when we are done, since we are only
5747 going to test the sign bit. */
5748 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5749 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5750 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5751 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5752 && op1
== const0_rtx
5753 && mode
== GET_MODE (op0
)
5754 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5756 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5757 expand_compound_operation (op0
),
5758 GET_MODE_BITSIZE (mode
) - 1 - i
);
5759 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5765 /* If the code changed, return a whole new comparison. */
5766 if (new_code
!= code
)
5767 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5769 /* Otherwise, keep this operation, but maybe change its operands.
5770 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5771 SUBST (XEXP (x
, 0), op0
);
5772 SUBST (XEXP (x
, 1), op1
);
5777 return simplify_if_then_else (x
);
5783 /* If we are processing SET_DEST, we are done. */
5787 return expand_compound_operation (x
);
5790 return simplify_set (x
);
5794 return simplify_logical (x
);
5801 /* If this is a shift by a constant amount, simplify it. */
5802 if (CONST_INT_P (XEXP (x
, 1)))
5803 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5804 INTVAL (XEXP (x
, 1)));
5806 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5808 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5810 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5822 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5825 simplify_if_then_else (rtx x
)
5827 enum machine_mode mode
= GET_MODE (x
);
5828 rtx cond
= XEXP (x
, 0);
5829 rtx true_rtx
= XEXP (x
, 1);
5830 rtx false_rtx
= XEXP (x
, 2);
5831 enum rtx_code true_code
= GET_CODE (cond
);
5832 int comparison_p
= COMPARISON_P (cond
);
5835 enum rtx_code false_code
;
5838 /* Simplify storing of the truth value. */
5839 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5840 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5841 XEXP (cond
, 0), XEXP (cond
, 1));
5843 /* Also when the truth value has to be reversed. */
5845 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5846 && (reversed
= reversed_comparison (cond
, mode
)))
5849 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5850 in it is being compared against certain values. Get the true and false
5851 comparisons and see if that says anything about the value of each arm. */
5854 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5856 && REG_P (XEXP (cond
, 0)))
5859 rtx from
= XEXP (cond
, 0);
5860 rtx true_val
= XEXP (cond
, 1);
5861 rtx false_val
= true_val
;
5864 /* If FALSE_CODE is EQ, swap the codes and arms. */
5866 if (false_code
== EQ
)
5868 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5869 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5872 /* If we are comparing against zero and the expression being tested has
5873 only a single bit that might be nonzero, that is its value when it is
5874 not equal to zero. Similarly if it is known to be -1 or 0. */
5876 if (true_code
== EQ
&& true_val
== const0_rtx
5877 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5880 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
5882 else if (true_code
== EQ
&& true_val
== const0_rtx
5883 && (num_sign_bit_copies (from
, GET_MODE (from
))
5884 == GET_MODE_BITSIZE (GET_MODE (from
))))
5887 false_val
= constm1_rtx
;
5890 /* Now simplify an arm if we know the value of the register in the
5891 branch and it is used in the arm. Be careful due to the potential
5892 of locally-shared RTL. */
5894 if (reg_mentioned_p (from
, true_rtx
))
5895 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5897 pc_rtx
, pc_rtx
, 0, 0);
5898 if (reg_mentioned_p (from
, false_rtx
))
5899 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5901 pc_rtx
, pc_rtx
, 0, 0);
5903 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5904 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5906 true_rtx
= XEXP (x
, 1);
5907 false_rtx
= XEXP (x
, 2);
5908 true_code
= GET_CODE (cond
);
5911 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5912 reversed, do so to avoid needing two sets of patterns for
5913 subtract-and-branch insns. Similarly if we have a constant in the true
5914 arm, the false arm is the same as the first operand of the comparison, or
5915 the false arm is more complicated than the true arm. */
5918 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5919 && (true_rtx
== pc_rtx
5920 || (CONSTANT_P (true_rtx
)
5921 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5922 || true_rtx
== const0_rtx
5923 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5924 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5925 && !OBJECT_P (false_rtx
))
5926 || reg_mentioned_p (true_rtx
, false_rtx
)
5927 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5929 true_code
= reversed_comparison_code (cond
, NULL
);
5930 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5931 SUBST (XEXP (x
, 1), false_rtx
);
5932 SUBST (XEXP (x
, 2), true_rtx
);
5934 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5937 /* It is possible that the conditional has been simplified out. */
5938 true_code
= GET_CODE (cond
);
5939 comparison_p
= COMPARISON_P (cond
);
5942 /* If the two arms are identical, we don't need the comparison. */
5944 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5947 /* Convert a == b ? b : a to "a". */
5948 if (true_code
== EQ
&& ! side_effects_p (cond
)
5949 && !HONOR_NANS (mode
)
5950 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5951 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5953 else if (true_code
== NE
&& ! side_effects_p (cond
)
5954 && !HONOR_NANS (mode
)
5955 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5956 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5959 /* Look for cases where we have (abs x) or (neg (abs X)). */
5961 if (GET_MODE_CLASS (mode
) == MODE_INT
5963 && XEXP (cond
, 1) == const0_rtx
5964 && GET_CODE (false_rtx
) == NEG
5965 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
5966 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
5967 && ! side_effects_p (true_rtx
))
5972 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
5976 simplify_gen_unary (NEG
, mode
,
5977 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
5983 /* Look for MIN or MAX. */
5985 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
5987 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5988 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
5989 && ! side_effects_p (cond
))
5994 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
5997 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6000 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6003 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6008 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6009 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6010 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6011 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6012 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6013 neither 1 or -1, but it isn't worth checking for. */
6015 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6017 && GET_MODE_CLASS (mode
) == MODE_INT
6018 && ! side_effects_p (x
))
6020 rtx t
= make_compound_operation (true_rtx
, SET
);
6021 rtx f
= make_compound_operation (false_rtx
, SET
);
6022 rtx cond_op0
= XEXP (cond
, 0);
6023 rtx cond_op1
= XEXP (cond
, 1);
6024 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6025 enum machine_mode m
= mode
;
6026 rtx z
= 0, c1
= NULL_RTX
;
6028 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6029 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6030 || GET_CODE (t
) == ASHIFT
6031 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6032 && rtx_equal_p (XEXP (t
, 0), f
))
6033 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6035 /* If an identity-zero op is commutative, check whether there
6036 would be a match if we swapped the operands. */
6037 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6038 || GET_CODE (t
) == XOR
)
6039 && rtx_equal_p (XEXP (t
, 1), f
))
6040 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6041 else if (GET_CODE (t
) == SIGN_EXTEND
6042 && (GET_CODE (XEXP (t
, 0)) == PLUS
6043 || GET_CODE (XEXP (t
, 0)) == MINUS
6044 || GET_CODE (XEXP (t
, 0)) == IOR
6045 || GET_CODE (XEXP (t
, 0)) == XOR
6046 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6047 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6048 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6049 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6050 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6051 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6052 && (num_sign_bit_copies (f
, GET_MODE (f
))
6054 (GET_MODE_BITSIZE (mode
)
6055 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6057 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6058 extend_op
= SIGN_EXTEND
;
6059 m
= GET_MODE (XEXP (t
, 0));
6061 else if (GET_CODE (t
) == SIGN_EXTEND
6062 && (GET_CODE (XEXP (t
, 0)) == PLUS
6063 || GET_CODE (XEXP (t
, 0)) == IOR
6064 || GET_CODE (XEXP (t
, 0)) == XOR
)
6065 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6066 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6067 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6068 && (num_sign_bit_copies (f
, GET_MODE (f
))
6070 (GET_MODE_BITSIZE (mode
)
6071 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6073 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6074 extend_op
= SIGN_EXTEND
;
6075 m
= GET_MODE (XEXP (t
, 0));
6077 else if (GET_CODE (t
) == ZERO_EXTEND
6078 && (GET_CODE (XEXP (t
, 0)) == PLUS
6079 || GET_CODE (XEXP (t
, 0)) == MINUS
6080 || GET_CODE (XEXP (t
, 0)) == IOR
6081 || GET_CODE (XEXP (t
, 0)) == XOR
6082 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6083 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6084 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6085 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6086 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6087 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6088 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6089 && ((nonzero_bits (f
, GET_MODE (f
))
6090 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6093 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6094 extend_op
= ZERO_EXTEND
;
6095 m
= GET_MODE (XEXP (t
, 0));
6097 else if (GET_CODE (t
) == ZERO_EXTEND
6098 && (GET_CODE (XEXP (t
, 0)) == PLUS
6099 || GET_CODE (XEXP (t
, 0)) == IOR
6100 || GET_CODE (XEXP (t
, 0)) == XOR
)
6101 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6102 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6103 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6104 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6105 && ((nonzero_bits (f
, GET_MODE (f
))
6106 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6109 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6110 extend_op
= ZERO_EXTEND
;
6111 m
= GET_MODE (XEXP (t
, 0));
6116 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6117 cond_op0
, cond_op1
),
6118 pc_rtx
, pc_rtx
, 0, 0);
6119 temp
= simplify_gen_binary (MULT
, m
, temp
,
6120 simplify_gen_binary (MULT
, m
, c1
,
6122 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
6123 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6125 if (extend_op
!= UNKNOWN
)
6126 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6132 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6133 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6134 negation of a single bit, we can convert this operation to a shift. We
6135 can actually do this more generally, but it doesn't seem worth it. */
6137 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6138 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6139 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6140 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
6141 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6142 == GET_MODE_BITSIZE (mode
))
6143 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
6145 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6146 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6148 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6149 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6150 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6151 && GET_MODE (XEXP (cond
, 0)) == mode
6152 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6153 == nonzero_bits (XEXP (cond
, 0), mode
)
6154 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6155 return XEXP (cond
, 0);
6160 /* Simplify X, a SET expression. Return the new expression. */
6163 simplify_set (rtx x
)
6165 rtx src
= SET_SRC (x
);
6166 rtx dest
= SET_DEST (x
);
6167 enum machine_mode mode
6168 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6172 /* (set (pc) (return)) gets written as (return). */
6173 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
6176 /* Now that we know for sure which bits of SRC we are using, see if we can
6177 simplify the expression for the object knowing that we only need the
6180 if (GET_MODE_CLASS (mode
) == MODE_INT
6181 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
6183 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, 0);
6184 SUBST (SET_SRC (x
), src
);
6187 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6188 the comparison result and try to simplify it unless we already have used
6189 undobuf.other_insn. */
6190 if ((GET_MODE_CLASS (mode
) == MODE_CC
6191 || GET_CODE (src
) == COMPARE
6193 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6194 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6195 && COMPARISON_P (*cc_use
)
6196 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6198 enum rtx_code old_code
= GET_CODE (*cc_use
);
6199 enum rtx_code new_code
;
6201 int other_changed
= 0;
6202 enum machine_mode compare_mode
= GET_MODE (dest
);
6204 if (GET_CODE (src
) == COMPARE
)
6205 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6207 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6209 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6212 new_code
= old_code
;
6213 else if (!CONSTANT_P (tmp
))
6215 new_code
= GET_CODE (tmp
);
6216 op0
= XEXP (tmp
, 0);
6217 op1
= XEXP (tmp
, 1);
6221 rtx pat
= PATTERN (other_insn
);
6222 undobuf
.other_insn
= other_insn
;
6223 SUBST (*cc_use
, tmp
);
6225 /* Attempt to simplify CC user. */
6226 if (GET_CODE (pat
) == SET
)
6228 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6229 if (new_rtx
!= NULL_RTX
)
6230 SUBST (SET_SRC (pat
), new_rtx
);
6233 /* Convert X into a no-op move. */
6234 SUBST (SET_DEST (x
), pc_rtx
);
6235 SUBST (SET_SRC (x
), pc_rtx
);
6239 /* Simplify our comparison, if possible. */
6240 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6242 #ifdef SELECT_CC_MODE
6243 /* If this machine has CC modes other than CCmode, check to see if we
6244 need to use a different CC mode here. */
6245 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6246 compare_mode
= GET_MODE (op0
);
6248 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6251 /* If the mode changed, we have to change SET_DEST, the mode in the
6252 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6253 a hard register, just build new versions with the proper mode. If it
6254 is a pseudo, we lose unless it is only time we set the pseudo, in
6255 which case we can safely change its mode. */
6256 if (compare_mode
!= GET_MODE (dest
))
6258 if (can_change_dest_mode (dest
, 0, compare_mode
))
6260 unsigned int regno
= REGNO (dest
);
6263 if (regno
< FIRST_PSEUDO_REGISTER
)
6264 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6267 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6268 new_dest
= regno_reg_rtx
[regno
];
6271 SUBST (SET_DEST (x
), new_dest
);
6272 SUBST (XEXP (*cc_use
, 0), new_dest
);
6279 #endif /* SELECT_CC_MODE */
6281 /* If the code changed, we have to build a new comparison in
6282 undobuf.other_insn. */
6283 if (new_code
!= old_code
)
6285 int other_changed_previously
= other_changed
;
6286 unsigned HOST_WIDE_INT mask
;
6287 rtx old_cc_use
= *cc_use
;
6289 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6293 /* If the only change we made was to change an EQ into an NE or
6294 vice versa, OP0 has only one bit that might be nonzero, and OP1
6295 is zero, check if changing the user of the condition code will
6296 produce a valid insn. If it won't, we can keep the original code
6297 in that insn by surrounding our operation with an XOR. */
6299 if (((old_code
== NE
&& new_code
== EQ
)
6300 || (old_code
== EQ
&& new_code
== NE
))
6301 && ! other_changed_previously
&& op1
== const0_rtx
6302 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
6303 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6305 rtx pat
= PATTERN (other_insn
), note
= 0;
6307 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6308 && ! check_asm_operands (pat
)))
6310 *cc_use
= old_cc_use
;
6313 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6314 op0
, GEN_INT (mask
));
6320 undobuf
.other_insn
= other_insn
;
6322 /* Otherwise, if we didn't previously have a COMPARE in the
6323 correct mode, we need one. */
6324 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6326 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6329 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6331 SUBST (SET_SRC (x
), op0
);
6334 /* Otherwise, update the COMPARE if needed. */
6335 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6337 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6343 /* Get SET_SRC in a form where we have placed back any
6344 compound expressions. Then do the checks below. */
6345 src
= make_compound_operation (src
, SET
);
6346 SUBST (SET_SRC (x
), src
);
6349 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6350 and X being a REG or (subreg (reg)), we may be able to convert this to
6351 (set (subreg:m2 x) (op)).
6353 We can always do this if M1 is narrower than M2 because that means that
6354 we only care about the low bits of the result.
6356 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6357 perform a narrower operation than requested since the high-order bits will
6358 be undefined. On machine where it is defined, this transformation is safe
6359 as long as M1 and M2 have the same number of words. */
6361 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6362 && !OBJECT_P (SUBREG_REG (src
))
6363 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6365 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6366 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6367 #ifndef WORD_REGISTER_OPERATIONS
6368 && (GET_MODE_SIZE (GET_MODE (src
))
6369 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6371 #ifdef CANNOT_CHANGE_MODE_CLASS
6372 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6373 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6374 GET_MODE (SUBREG_REG (src
)),
6378 || (GET_CODE (dest
) == SUBREG
6379 && REG_P (SUBREG_REG (dest
)))))
6381 SUBST (SET_DEST (x
),
6382 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6384 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6386 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6390 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6393 && GET_CODE (src
) == SUBREG
6394 && subreg_lowpart_p (src
)
6395 && (GET_MODE_BITSIZE (GET_MODE (src
))
6396 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
6398 rtx inner
= SUBREG_REG (src
);
6399 enum machine_mode inner_mode
= GET_MODE (inner
);
6401 /* Here we make sure that we don't have a sign bit on. */
6402 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
6403 && (nonzero_bits (inner
, inner_mode
)
6404 < ((unsigned HOST_WIDE_INT
) 1
6405 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
6407 SUBST (SET_SRC (x
), inner
);
6413 #ifdef LOAD_EXTEND_OP
6414 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6415 would require a paradoxical subreg. Replace the subreg with a
6416 zero_extend to avoid the reload that would otherwise be required. */
6418 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6419 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6420 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6421 && SUBREG_BYTE (src
) == 0
6422 && (GET_MODE_SIZE (GET_MODE (src
))
6423 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6424 && MEM_P (SUBREG_REG (src
)))
6427 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6428 GET_MODE (src
), SUBREG_REG (src
)));
6434 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6435 are comparing an item known to be 0 or -1 against 0, use a logical
6436 operation instead. Check for one of the arms being an IOR of the other
6437 arm with some value. We compute three terms to be IOR'ed together. In
6438 practice, at most two will be nonzero. Then we do the IOR's. */
6440 if (GET_CODE (dest
) != PC
6441 && GET_CODE (src
) == IF_THEN_ELSE
6442 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6443 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6444 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6445 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6446 #ifdef HAVE_conditional_move
6447 && ! can_conditionally_move_p (GET_MODE (src
))
6449 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6450 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6451 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6452 && ! side_effects_p (src
))
6454 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6455 ? XEXP (src
, 1) : XEXP (src
, 2));
6456 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6457 ? XEXP (src
, 2) : XEXP (src
, 1));
6458 rtx term1
= const0_rtx
, term2
, term3
;
6460 if (GET_CODE (true_rtx
) == IOR
6461 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6462 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6463 else if (GET_CODE (true_rtx
) == IOR
6464 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6465 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6466 else if (GET_CODE (false_rtx
) == IOR
6467 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6468 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6469 else if (GET_CODE (false_rtx
) == IOR
6470 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6471 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6473 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6474 XEXP (XEXP (src
, 0), 0), true_rtx
);
6475 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6476 simplify_gen_unary (NOT
, GET_MODE (src
),
6477 XEXP (XEXP (src
, 0), 0),
6482 simplify_gen_binary (IOR
, GET_MODE (src
),
6483 simplify_gen_binary (IOR
, GET_MODE (src
),
6490 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6491 whole thing fail. */
6492 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6494 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6497 /* Convert this into a field assignment operation, if possible. */
6498 return make_field_assignment (x
);
6501 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6505 simplify_logical (rtx x
)
6507 enum machine_mode mode
= GET_MODE (x
);
6508 rtx op0
= XEXP (x
, 0);
6509 rtx op1
= XEXP (x
, 1);
6511 switch (GET_CODE (x
))
6514 /* We can call simplify_and_const_int only if we don't lose
6515 any (sign) bits when converting INTVAL (op1) to
6516 "unsigned HOST_WIDE_INT". */
6517 if (CONST_INT_P (op1
)
6518 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6519 || INTVAL (op1
) > 0))
6521 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6522 if (GET_CODE (x
) != AND
)
6529 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6530 apply the distributive law and then the inverse distributive
6531 law to see if things simplify. */
6532 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6534 rtx result
= distribute_and_simplify_rtx (x
, 0);
6538 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6540 rtx result
= distribute_and_simplify_rtx (x
, 1);
6547 /* If we have (ior (and A B) C), apply the distributive law and then
6548 the inverse distributive law to see if things simplify. */
6550 if (GET_CODE (op0
) == AND
)
6552 rtx result
= distribute_and_simplify_rtx (x
, 0);
6557 if (GET_CODE (op1
) == AND
)
6559 rtx result
= distribute_and_simplify_rtx (x
, 1);
6572 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6573 operations" because they can be replaced with two more basic operations.
6574 ZERO_EXTEND is also considered "compound" because it can be replaced with
6575 an AND operation, which is simpler, though only one operation.
6577 The function expand_compound_operation is called with an rtx expression
6578 and will convert it to the appropriate shifts and AND operations,
6579 simplifying at each stage.
6581 The function make_compound_operation is called to convert an expression
6582 consisting of shifts and ANDs into the equivalent compound expression.
6583 It is the inverse of this function, loosely speaking. */
6586 expand_compound_operation (rtx x
)
6588 unsigned HOST_WIDE_INT pos
= 0, len
;
6590 unsigned int modewidth
;
6593 switch (GET_CODE (x
))
6598 /* We can't necessarily use a const_int for a multiword mode;
6599 it depends on implicitly extending the value.
6600 Since we don't know the right way to extend it,
6601 we can't tell whether the implicit way is right.
6603 Even for a mode that is no wider than a const_int,
6604 we can't win, because we need to sign extend one of its bits through
6605 the rest of it, and we don't know which bit. */
6606 if (CONST_INT_P (XEXP (x
, 0)))
6609 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6610 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6611 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6612 reloaded. If not for that, MEM's would very rarely be safe.
6614 Reject MODEs bigger than a word, because we might not be able
6615 to reference a two-register group starting with an arbitrary register
6616 (and currently gen_lowpart might crash for a SUBREG). */
6618 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6621 /* Reject MODEs that aren't scalar integers because turning vector
6622 or complex modes into shifts causes problems. */
6624 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6627 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
6628 /* If the inner object has VOIDmode (the only way this can happen
6629 is if it is an ASM_OPERANDS), we can't do anything since we don't
6630 know how much masking to do. */
6639 /* ... fall through ... */
6642 /* If the operand is a CLOBBER, just return it. */
6643 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6646 if (!CONST_INT_P (XEXP (x
, 1))
6647 || !CONST_INT_P (XEXP (x
, 2))
6648 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6651 /* Reject MODEs that aren't scalar integers because turning vector
6652 or complex modes into shifts causes problems. */
6654 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6657 len
= INTVAL (XEXP (x
, 1));
6658 pos
= INTVAL (XEXP (x
, 2));
6660 /* This should stay within the object being extracted, fail otherwise. */
6661 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
6664 if (BITS_BIG_ENDIAN
)
6665 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6672 /* Convert sign extension to zero extension, if we know that the high
6673 bit is not set, as this is easier to optimize. It will be converted
6674 back to cheaper alternative in make_extraction. */
6675 if (GET_CODE (x
) == SIGN_EXTEND
6676 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6677 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6678 & ~(((unsigned HOST_WIDE_INT
)
6679 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6683 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6684 rtx temp2
= expand_compound_operation (temp
);
6686 /* Make sure this is a profitable operation. */
6687 if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6688 > rtx_cost (temp2
, SET
, optimize_this_for_speed_p
))
6690 else if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6691 > rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
6697 /* We can optimize some special cases of ZERO_EXTEND. */
6698 if (GET_CODE (x
) == ZERO_EXTEND
)
6700 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6701 know that the last value didn't have any inappropriate bits
6703 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6704 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6705 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6706 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6707 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6708 return XEXP (XEXP (x
, 0), 0);
6710 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6711 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6712 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6713 && subreg_lowpart_p (XEXP (x
, 0))
6714 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6715 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6716 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6717 return SUBREG_REG (XEXP (x
, 0));
6719 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6720 is a comparison and STORE_FLAG_VALUE permits. This is like
6721 the first case, but it works even when GET_MODE (x) is larger
6722 than HOST_WIDE_INT. */
6723 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6724 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6725 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6726 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6727 <= HOST_BITS_PER_WIDE_INT
)
6728 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6729 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6730 return XEXP (XEXP (x
, 0), 0);
6732 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6733 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6734 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6735 && subreg_lowpart_p (XEXP (x
, 0))
6736 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6737 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6738 <= HOST_BITS_PER_WIDE_INT
)
6739 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6740 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6741 return SUBREG_REG (XEXP (x
, 0));
6745 /* If we reach here, we want to return a pair of shifts. The inner
6746 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6747 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6748 logical depending on the value of UNSIGNEDP.
6750 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6751 converted into an AND of a shift.
6753 We must check for the case where the left shift would have a negative
6754 count. This can happen in a case like (x >> 31) & 255 on machines
6755 that can't shift by a constant. On those machines, we would first
6756 combine the shift with the AND to produce a variable-position
6757 extraction. Then the constant of 31 would be substituted in to produce
6758 a such a position. */
6760 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6761 if (modewidth
+ len
>= pos
)
6763 enum machine_mode mode
= GET_MODE (x
);
6764 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6765 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6767 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6768 tem
, modewidth
- pos
- len
);
6769 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6770 mode
, tem
, modewidth
- len
);
6772 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6773 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6774 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6777 ((HOST_WIDE_INT
) 1 << len
) - 1);
6779 /* Any other cases we can't handle. */
6782 /* If we couldn't do this for some reason, return the original
6784 if (GET_CODE (tem
) == CLOBBER
)
6790 /* X is a SET which contains an assignment of one object into
6791 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6792 or certain SUBREGS). If possible, convert it into a series of
6795 We half-heartedly support variable positions, but do not at all
6796 support variable lengths. */
6799 expand_field_assignment (const_rtx x
)
6802 rtx pos
; /* Always counts from low bit. */
6804 rtx mask
, cleared
, masked
;
6805 enum machine_mode compute_mode
;
6807 /* Loop until we find something we can't simplify. */
6810 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6811 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6813 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6814 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6815 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6817 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6818 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6820 inner
= XEXP (SET_DEST (x
), 0);
6821 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6822 pos
= XEXP (SET_DEST (x
), 2);
6824 /* A constant position should stay within the width of INNER. */
6825 if (CONST_INT_P (pos
)
6826 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6829 if (BITS_BIG_ENDIAN
)
6831 if (CONST_INT_P (pos
))
6832 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6834 else if (GET_CODE (pos
) == MINUS
6835 && CONST_INT_P (XEXP (pos
, 1))
6836 && (INTVAL (XEXP (pos
, 1))
6837 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6838 /* If position is ADJUST - X, new position is X. */
6839 pos
= XEXP (pos
, 0);
6841 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6842 GEN_INT (GET_MODE_BITSIZE (
6849 /* A SUBREG between two modes that occupy the same numbers of words
6850 can be done by moving the SUBREG to the source. */
6851 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6852 /* We need SUBREGs to compute nonzero_bits properly. */
6853 && nonzero_sign_valid
6854 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6855 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6856 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6857 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6859 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6861 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6868 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6869 inner
= SUBREG_REG (inner
);
6871 compute_mode
= GET_MODE (inner
);
6873 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6874 if (! SCALAR_INT_MODE_P (compute_mode
))
6876 enum machine_mode imode
;
6878 /* Don't do anything for vector or complex integral types. */
6879 if (! FLOAT_MODE_P (compute_mode
))
6882 /* Try to find an integral mode to pun with. */
6883 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6884 if (imode
== BLKmode
)
6887 compute_mode
= imode
;
6888 inner
= gen_lowpart (imode
, inner
);
6891 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6892 if (len
>= HOST_BITS_PER_WIDE_INT
)
6895 /* Now compute the equivalent expression. Make a copy of INNER
6896 for the SET_DEST in case it is a MEM into which we will substitute;
6897 we don't want shared RTL in that case. */
6898 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6899 cleared
= simplify_gen_binary (AND
, compute_mode
,
6900 simplify_gen_unary (NOT
, compute_mode
,
6901 simplify_gen_binary (ASHIFT
,
6906 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6907 simplify_gen_binary (
6909 gen_lowpart (compute_mode
, SET_SRC (x
)),
6913 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6914 simplify_gen_binary (IOR
, compute_mode
,
6921 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6922 it is an RTX that represents a variable starting position; otherwise,
6923 POS is the (constant) starting bit position (counted from the LSB).
6925 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6928 IN_DEST is nonzero if this is a reference in the destination of a
6929 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6930 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6933 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6934 ZERO_EXTRACT should be built even for bits starting at bit 0.
6936 MODE is the desired mode of the result (if IN_DEST == 0).
6938 The result is an RTX for the extraction or NULL_RTX if the target
6942 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6943 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6944 int in_dest
, int in_compare
)
6946 /* This mode describes the size of the storage area
6947 to fetch the overall value from. Within that, we
6948 ignore the POS lowest bits, etc. */
6949 enum machine_mode is_mode
= GET_MODE (inner
);
6950 enum machine_mode inner_mode
;
6951 enum machine_mode wanted_inner_mode
;
6952 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6953 enum machine_mode pos_mode
= word_mode
;
6954 enum machine_mode extraction_mode
= word_mode
;
6955 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6957 rtx orig_pos_rtx
= pos_rtx
;
6958 HOST_WIDE_INT orig_pos
;
6960 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6962 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6963 consider just the QI as the memory to extract from.
6964 The subreg adds or removes high bits; its mode is
6965 irrelevant to the meaning of this extraction,
6966 since POS and LEN count from the lsb. */
6967 if (MEM_P (SUBREG_REG (inner
)))
6968 is_mode
= GET_MODE (SUBREG_REG (inner
));
6969 inner
= SUBREG_REG (inner
);
6971 else if (GET_CODE (inner
) == ASHIFT
6972 && CONST_INT_P (XEXP (inner
, 1))
6973 && pos_rtx
== 0 && pos
== 0
6974 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6976 /* We're extracting the least significant bits of an rtx
6977 (ashift X (const_int C)), where LEN > C. Extract the
6978 least significant (LEN - C) bits of X, giving an rtx
6979 whose mode is MODE, then shift it left C times. */
6980 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
6981 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6982 unsignedp
, in_dest
, in_compare
);
6984 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
6987 inner_mode
= GET_MODE (inner
);
6989 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
6990 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6992 /* See if this can be done without an extraction. We never can if the
6993 width of the field is not the same as that of some integer mode. For
6994 registers, we can only avoid the extraction if the position is at the
6995 low-order bit and this is either not in the destination or we have the
6996 appropriate STRICT_LOW_PART operation available.
6998 For MEM, we can avoid an extract if the field starts on an appropriate
6999 boundary and we can change the mode of the memory reference. */
7001 if (tmode
!= BLKmode
7002 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7004 && (inner_mode
== tmode
7006 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
7007 GET_MODE_BITSIZE (inner_mode
))
7008 || reg_truncated_to_mode (tmode
, inner
))
7011 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7012 || (MEM_P (inner
) && pos_rtx
== 0
7014 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7015 : BITS_PER_UNIT
)) == 0
7016 /* We can't do this if we are widening INNER_MODE (it
7017 may not be aligned, for one thing). */
7018 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
7019 && (inner_mode
== tmode
7020 || (! mode_dependent_address_p (XEXP (inner
, 0))
7021 && ! MEM_VOLATILE_P (inner
))))))
7023 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7024 field. If the original and current mode are the same, we need not
7025 adjust the offset. Otherwise, we do if bytes big endian.
7027 If INNER is not a MEM, get a piece consisting of just the field
7028 of interest (in this case POS % BITS_PER_WORD must be 0). */
7032 HOST_WIDE_INT offset
;
7034 /* POS counts from lsb, but make OFFSET count in memory order. */
7035 if (BYTES_BIG_ENDIAN
)
7036 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7038 offset
= pos
/ BITS_PER_UNIT
;
7040 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7042 else if (REG_P (inner
))
7044 if (tmode
!= inner_mode
)
7046 /* We can't call gen_lowpart in a DEST since we
7047 always want a SUBREG (see below) and it would sometimes
7048 return a new hard register. */
7051 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7053 if (WORDS_BIG_ENDIAN
7054 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7055 final_word
= ((GET_MODE_SIZE (inner_mode
)
7056 - GET_MODE_SIZE (tmode
))
7057 / UNITS_PER_WORD
) - final_word
;
7059 final_word
*= UNITS_PER_WORD
;
7060 if (BYTES_BIG_ENDIAN
&&
7061 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7062 final_word
+= (GET_MODE_SIZE (inner_mode
)
7063 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7065 /* Avoid creating invalid subregs, for example when
7066 simplifying (x>>32)&255. */
7067 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7070 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7073 new_rtx
= gen_lowpart (tmode
, inner
);
7079 new_rtx
= force_to_mode (inner
, tmode
,
7080 len
>= HOST_BITS_PER_WIDE_INT
7081 ? ~(unsigned HOST_WIDE_INT
) 0
7082 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7085 /* If this extraction is going into the destination of a SET,
7086 make a STRICT_LOW_PART unless we made a MEM. */
7089 return (MEM_P (new_rtx
) ? new_rtx
7090 : (GET_CODE (new_rtx
) != SUBREG
7091 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7092 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7097 if (CONST_INT_P (new_rtx
)
7098 || GET_CODE (new_rtx
) == CONST_DOUBLE
)
7099 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7100 mode
, new_rtx
, tmode
);
7102 /* If we know that no extraneous bits are set, and that the high
7103 bit is not set, convert the extraction to the cheaper of
7104 sign and zero extension, that are equivalent in these cases. */
7105 if (flag_expensive_optimizations
7106 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
7107 && ((nonzero_bits (new_rtx
, tmode
)
7108 & ~(((unsigned HOST_WIDE_INT
)
7109 GET_MODE_MASK (tmode
))
7113 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7114 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7116 /* Prefer ZERO_EXTENSION, since it gives more information to
7118 if (rtx_cost (temp
, SET
, optimize_this_for_speed_p
)
7119 <= rtx_cost (temp1
, SET
, optimize_this_for_speed_p
))
7124 /* Otherwise, sign- or zero-extend unless we already are in the
7127 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7131 /* Unless this is a COMPARE or we have a funny memory reference,
7132 don't do anything with zero-extending field extracts starting at
7133 the low-order bit since they are simple AND operations. */
7134 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7135 && ! in_compare
&& unsignedp
)
7138 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7139 if the position is not a constant and the length is not 1. In all
7140 other cases, we would only be going outside our object in cases when
7141 an original shift would have been undefined. */
7143 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
7144 || (pos_rtx
!= 0 && len
!= 1)))
7147 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7148 and the mode for the result. */
7149 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
7151 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
7152 pos_mode
= mode_for_extraction (EP_insv
, 2);
7153 extraction_mode
= mode_for_extraction (EP_insv
, 3);
7156 if (! in_dest
&& unsignedp
7157 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
7159 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
7160 pos_mode
= mode_for_extraction (EP_extzv
, 3);
7161 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
7164 if (! in_dest
&& ! unsignedp
7165 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
7167 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
7168 pos_mode
= mode_for_extraction (EP_extv
, 3);
7169 extraction_mode
= mode_for_extraction (EP_extv
, 0);
7172 /* Never narrow an object, since that might not be safe. */
7174 if (mode
!= VOIDmode
7175 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7176 extraction_mode
= mode
;
7178 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
7179 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7180 pos_mode
= GET_MODE (pos_rtx
);
7182 /* If this is not from memory, the desired mode is the preferred mode
7183 for an extraction pattern's first input operand, or word_mode if there
7186 wanted_inner_mode
= wanted_inner_reg_mode
;
7189 /* Be careful not to go beyond the extracted object and maintain the
7190 natural alignment of the memory. */
7191 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7192 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7193 > GET_MODE_BITSIZE (wanted_inner_mode
))
7195 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7196 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7199 /* If we have to change the mode of memory and cannot, the desired mode
7200 is EXTRACTION_MODE. */
7201 if (inner_mode
!= wanted_inner_mode
7202 && (mode_dependent_address_p (XEXP (inner
, 0))
7203 || MEM_VOLATILE_P (inner
)
7205 wanted_inner_mode
= extraction_mode
;
7210 if (BITS_BIG_ENDIAN
)
7212 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7213 BITS_BIG_ENDIAN style. If position is constant, compute new
7214 position. Otherwise, build subtraction.
7215 Note that POS is relative to the mode of the original argument.
7216 If it's a MEM we need to recompute POS relative to that.
7217 However, if we're extracting from (or inserting into) a register,
7218 we want to recompute POS relative to wanted_inner_mode. */
7219 int width
= (MEM_P (inner
)
7220 ? GET_MODE_BITSIZE (is_mode
)
7221 : GET_MODE_BITSIZE (wanted_inner_mode
));
7224 pos
= width
- len
- pos
;
7227 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
7228 /* POS may be less than 0 now, but we check for that below.
7229 Note that it can only be less than 0 if !MEM_P (inner). */
7232 /* If INNER has a wider mode, and this is a constant extraction, try to
7233 make it smaller and adjust the byte to point to the byte containing
7235 if (wanted_inner_mode
!= VOIDmode
7236 && inner_mode
!= wanted_inner_mode
7238 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7240 && ! mode_dependent_address_p (XEXP (inner
, 0))
7241 && ! MEM_VOLATILE_P (inner
))
7245 /* The computations below will be correct if the machine is big
7246 endian in both bits and bytes or little endian in bits and bytes.
7247 If it is mixed, we must adjust. */
7249 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7250 adjust OFFSET to compensate. */
7251 if (BYTES_BIG_ENDIAN
7252 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7253 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7255 /* We can now move to the desired byte. */
7256 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7257 * GET_MODE_SIZE (wanted_inner_mode
);
7258 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7260 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7261 && is_mode
!= wanted_inner_mode
)
7262 offset
= (GET_MODE_SIZE (is_mode
)
7263 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7265 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7268 /* If INNER is not memory, get it into the proper mode. If we are changing
7269 its mode, POS must be a constant and smaller than the size of the new
7271 else if (!MEM_P (inner
))
7273 /* On the LHS, don't create paradoxical subregs implicitely truncating
7274 the register unless TRULY_NOOP_TRUNCATION. */
7276 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner
)),
7277 GET_MODE_BITSIZE (wanted_inner_mode
)))
7280 if (GET_MODE (inner
) != wanted_inner_mode
7282 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7288 inner
= force_to_mode (inner
, wanted_inner_mode
,
7290 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7291 ? ~(unsigned HOST_WIDE_INT
) 0
7292 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7297 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7298 have to zero extend. Otherwise, we can just use a SUBREG. */
7300 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7302 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7304 /* If we know that no extraneous bits are set, and that the high
7305 bit is not set, convert extraction to cheaper one - either
7306 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7308 if (flag_expensive_optimizations
7309 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
7310 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7311 & ~(((unsigned HOST_WIDE_INT
)
7312 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7316 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7318 /* Prefer ZERO_EXTENSION, since it gives more information to
7320 if (rtx_cost (temp1
, SET
, optimize_this_for_speed_p
)
7321 < rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
7326 else if (pos_rtx
!= 0
7327 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7328 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
7330 /* Make POS_RTX unless we already have it and it is correct. If we don't
7331 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7333 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7334 pos_rtx
= orig_pos_rtx
;
7336 else if (pos_rtx
== 0)
7337 pos_rtx
= GEN_INT (pos
);
7339 /* Make the required operation. See if we can use existing rtx. */
7340 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7341 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7343 new_rtx
= gen_lowpart (mode
, new_rtx
);
7348 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7349 with any other operations in X. Return X without that shift if so. */
7352 extract_left_shift (rtx x
, int count
)
7354 enum rtx_code code
= GET_CODE (x
);
7355 enum machine_mode mode
= GET_MODE (x
);
7361 /* This is the shift itself. If it is wide enough, we will return
7362 either the value being shifted if the shift count is equal to
7363 COUNT or a shift for the difference. */
7364 if (CONST_INT_P (XEXP (x
, 1))
7365 && INTVAL (XEXP (x
, 1)) >= count
)
7366 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7367 INTVAL (XEXP (x
, 1)) - count
);
7371 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7372 return simplify_gen_unary (code
, mode
, tem
, mode
);
7376 case PLUS
: case IOR
: case XOR
: case AND
:
7377 /* If we can safely shift this constant and we find the inner shift,
7378 make a new operation. */
7379 if (CONST_INT_P (XEXP (x
, 1))
7380 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7381 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7382 return simplify_gen_binary (code
, mode
, tem
,
7383 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7394 /* Look at the expression rooted at X. Look for expressions
7395 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7396 Form these expressions.
7398 Return the new rtx, usually just X.
7400 Also, for machines like the VAX that don't have logical shift insns,
7401 try to convert logical to arithmetic shift operations in cases where
7402 they are equivalent. This undoes the canonicalizations to logical
7403 shifts done elsewhere.
7405 We try, as much as possible, to re-use rtl expressions to save memory.
7407 IN_CODE says what kind of expression we are processing. Normally, it is
7408 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7409 being kludges), it is MEM. When processing the arguments of a comparison
7410 or a COMPARE against zero, it is COMPARE. */
7413 make_compound_operation (rtx x
, enum rtx_code in_code
)
7415 enum rtx_code code
= GET_CODE (x
);
7416 enum machine_mode mode
= GET_MODE (x
);
7417 int mode_width
= GET_MODE_BITSIZE (mode
);
7419 enum rtx_code next_code
;
7425 /* Select the code to be used in recursive calls. Once we are inside an
7426 address, we stay there. If we have a comparison, set to COMPARE,
7427 but once inside, go back to our default of SET. */
7429 next_code
= (code
== MEM
? MEM
7430 : ((code
== PLUS
|| code
== MINUS
)
7431 && SCALAR_INT_MODE_P (mode
)) ? MEM
7432 : ((code
== COMPARE
|| COMPARISON_P (x
))
7433 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7434 : in_code
== COMPARE
? SET
: in_code
);
7436 /* Process depending on the code of this operation. If NEW is set
7437 nonzero, it will be returned. */
7442 /* Convert shifts by constants into multiplications if inside
7444 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7445 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7446 && INTVAL (XEXP (x
, 1)) >= 0)
7448 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7449 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7451 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7452 if (GET_CODE (new_rtx
) == NEG
)
7454 new_rtx
= XEXP (new_rtx
, 0);
7457 multval
= trunc_int_for_mode (multval
, mode
);
7458 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, GEN_INT (multval
));
7465 lhs
= make_compound_operation (lhs
, next_code
);
7466 rhs
= make_compound_operation (rhs
, next_code
);
7467 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7468 && SCALAR_INT_MODE_P (mode
))
7470 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7472 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7474 else if (GET_CODE (lhs
) == MULT
7475 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7477 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7478 simplify_gen_unary (NEG
, mode
,
7481 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7485 SUBST (XEXP (x
, 0), lhs
);
7486 SUBST (XEXP (x
, 1), rhs
);
7489 x
= gen_lowpart (mode
, new_rtx
);
7495 lhs
= make_compound_operation (lhs
, next_code
);
7496 rhs
= make_compound_operation (rhs
, next_code
);
7497 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7498 && SCALAR_INT_MODE_P (mode
))
7500 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7502 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7504 else if (GET_CODE (rhs
) == MULT
7505 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7507 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7508 simplify_gen_unary (NEG
, mode
,
7511 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7515 SUBST (XEXP (x
, 0), lhs
);
7516 SUBST (XEXP (x
, 1), rhs
);
7519 return gen_lowpart (mode
, new_rtx
);
7522 /* If the second operand is not a constant, we can't do anything
7524 if (!CONST_INT_P (XEXP (x
, 1)))
7527 /* If the constant is a power of two minus one and the first operand
7528 is a logical right shift, make an extraction. */
7529 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7530 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7532 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7533 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7534 0, in_code
== COMPARE
);
7537 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7538 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7539 && subreg_lowpart_p (XEXP (x
, 0))
7540 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7541 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7543 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7545 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7546 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7547 0, in_code
== COMPARE
);
7549 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7550 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7551 || GET_CODE (XEXP (x
, 0)) == IOR
)
7552 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7553 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7554 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7556 /* Apply the distributive law, and then try to make extractions. */
7557 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7558 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7560 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7562 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7565 /* If we are have (and (rotate X C) M) and C is larger than the number
7566 of bits in M, this is an extraction. */
7568 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7569 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7570 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
7571 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7573 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7574 new_rtx
= make_extraction (mode
, new_rtx
,
7575 (GET_MODE_BITSIZE (mode
)
7576 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7577 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7580 /* On machines without logical shifts, if the operand of the AND is
7581 a logical shift and our mask turns off all the propagated sign
7582 bits, we can replace the logical shift with an arithmetic shift. */
7583 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7584 && !have_insn_for (LSHIFTRT
, mode
)
7585 && have_insn_for (ASHIFTRT
, mode
)
7586 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7587 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7588 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7589 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7591 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7593 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7594 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7596 gen_rtx_ASHIFTRT (mode
,
7597 make_compound_operation
7598 (XEXP (XEXP (x
, 0), 0), next_code
),
7599 XEXP (XEXP (x
, 0), 1)));
7602 /* If the constant is one less than a power of two, this might be
7603 representable by an extraction even if no shift is present.
7604 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7605 we are in a COMPARE. */
7606 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7607 new_rtx
= make_extraction (mode
,
7608 make_compound_operation (XEXP (x
, 0),
7610 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7612 /* If we are in a comparison and this is an AND with a power of two,
7613 convert this into the appropriate bit extract. */
7614 else if (in_code
== COMPARE
7615 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
7616 new_rtx
= make_extraction (mode
,
7617 make_compound_operation (XEXP (x
, 0),
7619 i
, NULL_RTX
, 1, 1, 0, 1);
7624 /* If the sign bit is known to be zero, replace this with an
7625 arithmetic shift. */
7626 if (have_insn_for (ASHIFTRT
, mode
)
7627 && ! have_insn_for (LSHIFTRT
, mode
)
7628 && mode_width
<= HOST_BITS_PER_WIDE_INT
7629 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7631 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7632 make_compound_operation (XEXP (x
, 0),
7638 /* ... fall through ... */
7644 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7645 this is a SIGN_EXTRACT. */
7646 if (CONST_INT_P (rhs
)
7647 && GET_CODE (lhs
) == ASHIFT
7648 && CONST_INT_P (XEXP (lhs
, 1))
7649 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7650 && INTVAL (rhs
) < mode_width
)
7652 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7653 new_rtx
= make_extraction (mode
, new_rtx
,
7654 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7655 NULL_RTX
, mode_width
- INTVAL (rhs
),
7656 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7660 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7661 If so, try to merge the shifts into a SIGN_EXTEND. We could
7662 also do this for some cases of SIGN_EXTRACT, but it doesn't
7663 seem worth the effort; the case checked for occurs on Alpha. */
7666 && ! (GET_CODE (lhs
) == SUBREG
7667 && (OBJECT_P (SUBREG_REG (lhs
))))
7668 && CONST_INT_P (rhs
)
7669 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7670 && INTVAL (rhs
) < mode_width
7671 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7672 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7673 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7674 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7679 /* Call ourselves recursively on the inner expression. If we are
7680 narrowing the object and it has a different RTL code from
7681 what it originally did, do this SUBREG as a force_to_mode. */
7683 rtx inner
= SUBREG_REG (x
), simplified
;
7685 tem
= make_compound_operation (inner
, in_code
);
7688 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7692 if (GET_CODE (tem
) != GET_CODE (inner
)
7693 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7694 && subreg_lowpart_p (x
))
7696 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0, 0);
7698 /* If we have something other than a SUBREG, we might have
7699 done an expansion, so rerun ourselves. */
7700 if (GET_CODE (newer
) != SUBREG
)
7701 newer
= make_compound_operation (newer
, in_code
);
7703 /* force_to_mode can expand compounds. If it just re-expanded the
7704 compound, use gen_lowpart to convert to the desired mode. */
7705 if (rtx_equal_p (newer
, x
)
7706 /* Likewise if it re-expanded the compound only partially.
7707 This happens for SUBREG of ZERO_EXTRACT if they extract
7708 the same number of bits. */
7709 || (GET_CODE (newer
) == SUBREG
7710 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7711 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7712 && GET_CODE (inner
) == AND
7713 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7714 return gen_lowpart (GET_MODE (x
), tem
);
7730 x
= gen_lowpart (mode
, new_rtx
);
7731 code
= GET_CODE (x
);
7734 /* Now recursively process each operand of this operation. */
7735 fmt
= GET_RTX_FORMAT (code
);
7736 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7739 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7740 SUBST (XEXP (x
, i
), new_rtx
);
7742 else if (fmt
[i
] == 'E')
7743 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7745 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7746 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7750 /* If this is a commutative operation, the changes to the operands
7751 may have made it noncanonical. */
7752 if (COMMUTATIVE_ARITH_P (x
)
7753 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7756 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7757 SUBST (XEXP (x
, 1), tem
);
7763 /* Given M see if it is a value that would select a field of bits
7764 within an item, but not the entire word. Return -1 if not.
7765 Otherwise, return the starting position of the field, where 0 is the
7768 *PLEN is set to the length of the field. */
7771 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7773 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7774 int pos
= m
? ctz_hwi (m
) : -1;
7778 /* Now shift off the low-order zero bits and see if we have a
7779 power of two minus 1. */
7780 len
= exact_log2 ((m
>> pos
) + 1);
7789 /* If X refers to a register that equals REG in value, replace these
7790 references with REG. */
7792 canon_reg_for_combine (rtx x
, rtx reg
)
7799 enum rtx_code code
= GET_CODE (x
);
7800 switch (GET_RTX_CLASS (code
))
7803 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7804 if (op0
!= XEXP (x
, 0))
7805 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7810 case RTX_COMM_ARITH
:
7811 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7812 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7813 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7814 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7818 case RTX_COMM_COMPARE
:
7819 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7820 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7821 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7822 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7823 GET_MODE (op0
), op0
, op1
);
7827 case RTX_BITFIELD_OPS
:
7828 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7829 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7830 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7831 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7832 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7833 GET_MODE (op0
), op0
, op1
, op2
);
7838 if (rtx_equal_p (get_last_value (reg
), x
)
7839 || rtx_equal_p (reg
, get_last_value (x
)))
7848 fmt
= GET_RTX_FORMAT (code
);
7850 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7853 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7854 if (op
!= XEXP (x
, i
))
7864 else if (fmt
[i
] == 'E')
7867 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7869 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7870 if (op
!= XVECEXP (x
, i
, j
))
7877 XVECEXP (x
, i
, j
) = op
;
7888 /* Return X converted to MODE. If the value is already truncated to
7889 MODE we can just return a subreg even though in the general case we
7890 would need an explicit truncation. */
7893 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7895 if (!CONST_INT_P (x
)
7896 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7897 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
7898 GET_MODE_BITSIZE (GET_MODE (x
)))
7899 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7901 /* Bit-cast X into an integer mode. */
7902 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7903 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7904 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7908 return gen_lowpart (mode
, x
);
7911 /* See if X can be simplified knowing that we will only refer to it in
7912 MODE and will only refer to those bits that are nonzero in MASK.
7913 If other bits are being computed or if masking operations are done
7914 that select a superset of the bits in MASK, they can sometimes be
7917 Return a possibly simplified expression, but always convert X to
7918 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7920 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7921 are all off in X. This is used when X will be complemented, by either
7922 NOT, NEG, or XOR. */
7925 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7928 enum rtx_code code
= GET_CODE (x
);
7929 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7930 enum machine_mode op_mode
;
7931 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7934 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7935 code below will do the wrong thing since the mode of such an
7936 expression is VOIDmode.
7938 Also do nothing if X is a CLOBBER; this can happen if X was
7939 the return value from a call to gen_lowpart. */
7940 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7943 /* We want to perform the operation is its present mode unless we know
7944 that the operation is valid in MODE, in which case we do the operation
7946 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7947 && have_insn_for (code
, mode
))
7948 ? mode
: GET_MODE (x
));
7950 /* It is not valid to do a right-shift in a narrower mode
7951 than the one it came in with. */
7952 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7953 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
7954 op_mode
= GET_MODE (x
);
7956 /* Truncate MASK to fit OP_MODE. */
7958 mask
&= GET_MODE_MASK (op_mode
);
7960 /* When we have an arithmetic operation, or a shift whose count we
7961 do not know, we need to assume that all bits up to the highest-order
7962 bit in MASK will be needed. This is how we form such a mask. */
7963 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
7964 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
7966 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
7969 /* Determine what bits of X are guaranteed to be (non)zero. */
7970 nonzero
= nonzero_bits (x
, mode
);
7972 /* If none of the bits in X are needed, return a zero. */
7973 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
7976 /* If X is a CONST_INT, return a new one. Do this here since the
7977 test below will fail. */
7978 if (CONST_INT_P (x
))
7980 if (SCALAR_INT_MODE_P (mode
))
7981 return gen_int_mode (INTVAL (x
) & mask
, mode
);
7984 x
= GEN_INT (INTVAL (x
) & mask
);
7985 return gen_lowpart_common (mode
, x
);
7989 /* If X is narrower than MODE and we want all the bits in X's mode, just
7990 get X in the proper mode. */
7991 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
7992 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
7993 return gen_lowpart (mode
, x
);
7995 /* We can ignore the effect of a SUBREG if it narrows the mode or
7996 if the constant masks to zero all the bits the mode doesn't have. */
7997 if (GET_CODE (x
) == SUBREG
7998 && subreg_lowpart_p (x
)
7999 && ((GET_MODE_SIZE (GET_MODE (x
))
8000 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8002 & GET_MODE_MASK (GET_MODE (x
))
8003 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8004 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8006 /* The arithmetic simplifications here only work for scalar integer modes. */
8007 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8008 return gen_lowpart_or_truncate (mode
, x
);
8013 /* If X is a (clobber (const_int)), return it since we know we are
8014 generating something that won't match. */
8021 x
= expand_compound_operation (x
);
8022 if (GET_CODE (x
) != code
)
8023 return force_to_mode (x
, mode
, mask
, next_select
);
8027 /* Similarly for a truncate. */
8028 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8031 /* If this is an AND with a constant, convert it into an AND
8032 whose constant is the AND of that constant with MASK. If it
8033 remains an AND of MASK, delete it since it is redundant. */
8035 if (CONST_INT_P (XEXP (x
, 1)))
8037 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8038 mask
& INTVAL (XEXP (x
, 1)));
8040 /* If X is still an AND, see if it is an AND with a mask that
8041 is just some low-order bits. If so, and it is MASK, we don't
8044 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8045 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8049 /* If it remains an AND, try making another AND with the bits
8050 in the mode mask that aren't in MASK turned on. If the
8051 constant in the AND is wide enough, this might make a
8052 cheaper constant. */
8054 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8055 && GET_MODE_MASK (GET_MODE (x
)) != mask
8056 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
8058 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
8059 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
8060 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
8063 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8064 number, sign extend it. */
8065 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8066 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8067 cval
|= (HOST_WIDE_INT
) -1 << width
;
8069 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8070 XEXP (x
, 0), GEN_INT (cval
));
8071 if (rtx_cost (y
, SET
, optimize_this_for_speed_p
)
8072 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
8082 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8083 low-order bits (as in an alignment operation) and FOO is already
8084 aligned to that boundary, mask C1 to that boundary as well.
8085 This may eliminate that PLUS and, later, the AND. */
8088 unsigned int width
= GET_MODE_BITSIZE (mode
);
8089 unsigned HOST_WIDE_INT smask
= mask
;
8091 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8092 number, sign extend it. */
8094 if (width
< HOST_BITS_PER_WIDE_INT
8095 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8096 smask
|= (HOST_WIDE_INT
) -1 << width
;
8098 if (CONST_INT_P (XEXP (x
, 1))
8099 && exact_log2 (- smask
) >= 0
8100 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8101 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8102 return force_to_mode (plus_constant (XEXP (x
, 0),
8103 (INTVAL (XEXP (x
, 1)) & smask
)),
8104 mode
, smask
, next_select
);
8107 /* ... fall through ... */
8110 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8111 most significant bit in MASK since carries from those bits will
8112 affect the bits we are interested in. */
8117 /* If X is (minus C Y) where C's least set bit is larger than any bit
8118 in the mask, then we may replace with (neg Y). */
8119 if (CONST_INT_P (XEXP (x
, 0))
8120 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8121 & -INTVAL (XEXP (x
, 0))))
8124 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8126 return force_to_mode (x
, mode
, mask
, next_select
);
8129 /* Similarly, if C contains every bit in the fuller_mask, then we may
8130 replace with (not Y). */
8131 if (CONST_INT_P (XEXP (x
, 0))
8132 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
8133 == INTVAL (XEXP (x
, 0))))
8135 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8136 XEXP (x
, 1), GET_MODE (x
));
8137 return force_to_mode (x
, mode
, mask
, next_select
);
8145 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8146 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8147 operation which may be a bitfield extraction. Ensure that the
8148 constant we form is not wider than the mode of X. */
8150 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8151 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8152 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8153 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8154 && CONST_INT_P (XEXP (x
, 1))
8155 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8156 + floor_log2 (INTVAL (XEXP (x
, 1))))
8157 < GET_MODE_BITSIZE (GET_MODE (x
)))
8158 && (INTVAL (XEXP (x
, 1))
8159 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8161 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8162 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8163 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8164 XEXP (XEXP (x
, 0), 0), temp
);
8165 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8166 XEXP (XEXP (x
, 0), 1));
8167 return force_to_mode (x
, mode
, mask
, next_select
);
8171 /* For most binary operations, just propagate into the operation and
8172 change the mode if we have an operation of that mode. */
8174 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8175 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8177 /* If we ended up truncating both operands, truncate the result of the
8178 operation instead. */
8179 if (GET_CODE (op0
) == TRUNCATE
8180 && GET_CODE (op1
) == TRUNCATE
)
8182 op0
= XEXP (op0
, 0);
8183 op1
= XEXP (op1
, 0);
8186 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8187 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8189 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8190 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8194 /* For left shifts, do the same, but just for the first operand.
8195 However, we cannot do anything with shifts where we cannot
8196 guarantee that the counts are smaller than the size of the mode
8197 because such a count will have a different meaning in a
8200 if (! (CONST_INT_P (XEXP (x
, 1))
8201 && INTVAL (XEXP (x
, 1)) >= 0
8202 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
8203 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8204 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8205 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
8208 /* If the shift count is a constant and we can do arithmetic in
8209 the mode of the shift, refine which bits we need. Otherwise, use the
8210 conservative form of the mask. */
8211 if (CONST_INT_P (XEXP (x
, 1))
8212 && INTVAL (XEXP (x
, 1)) >= 0
8213 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
8214 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8215 mask
>>= INTVAL (XEXP (x
, 1));
8219 op0
= gen_lowpart_or_truncate (op_mode
,
8220 force_to_mode (XEXP (x
, 0), op_mode
,
8221 mask
, next_select
));
8223 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8224 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8228 /* Here we can only do something if the shift count is a constant,
8229 this shift constant is valid for the host, and we can do arithmetic
8232 if (CONST_INT_P (XEXP (x
, 1))
8233 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8234 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8236 rtx inner
= XEXP (x
, 0);
8237 unsigned HOST_WIDE_INT inner_mask
;
8239 /* Select the mask of the bits we need for the shift operand. */
8240 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8242 /* We can only change the mode of the shift if we can do arithmetic
8243 in the mode of the shift and INNER_MASK is no wider than the
8244 width of X's mode. */
8245 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8246 op_mode
= GET_MODE (x
);
8248 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8250 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8251 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8254 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8255 shift and AND produces only copies of the sign bit (C2 is one less
8256 than a power of two), we can do this with just a shift. */
8258 if (GET_CODE (x
) == LSHIFTRT
8259 && CONST_INT_P (XEXP (x
, 1))
8260 /* The shift puts one of the sign bit copies in the least significant
8262 && ((INTVAL (XEXP (x
, 1))
8263 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8264 >= GET_MODE_BITSIZE (GET_MODE (x
)))
8265 && exact_log2 (mask
+ 1) >= 0
8266 /* Number of bits left after the shift must be more than the mask
8268 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8269 <= GET_MODE_BITSIZE (GET_MODE (x
)))
8270 /* Must be more sign bit copies than the mask needs. */
8271 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8272 >= exact_log2 (mask
+ 1)))
8273 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8274 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
8275 - exact_log2 (mask
+ 1)));
8280 /* If we are just looking for the sign bit, we don't need this shift at
8281 all, even if it has a variable count. */
8282 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8283 && (mask
== ((unsigned HOST_WIDE_INT
) 1
8284 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8285 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8287 /* If this is a shift by a constant, get a mask that contains those bits
8288 that are not copies of the sign bit. We then have two cases: If
8289 MASK only includes those bits, this can be a logical shift, which may
8290 allow simplifications. If MASK is a single-bit field not within
8291 those bits, we are requesting a copy of the sign bit and hence can
8292 shift the sign bit to the appropriate location. */
8294 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8295 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8299 /* If the considered data is wider than HOST_WIDE_INT, we can't
8300 represent a mask for all its bits in a single scalar.
8301 But we only care about the lower bits, so calculate these. */
8303 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8305 nonzero
= ~(HOST_WIDE_INT
) 0;
8307 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8308 is the number of bits a full-width mask would have set.
8309 We need only shift if these are fewer than nonzero can
8310 hold. If not, we must keep all bits set in nonzero. */
8312 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8313 < HOST_BITS_PER_WIDE_INT
)
8314 nonzero
>>= INTVAL (XEXP (x
, 1))
8315 + HOST_BITS_PER_WIDE_INT
8316 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
8320 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8321 nonzero
>>= INTVAL (XEXP (x
, 1));
8324 if ((mask
& ~nonzero
) == 0)
8326 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8327 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8328 if (GET_CODE (x
) != ASHIFTRT
)
8329 return force_to_mode (x
, mode
, mask
, next_select
);
8332 else if ((i
= exact_log2 (mask
)) >= 0)
8334 x
= simplify_shift_const
8335 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8336 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
8338 if (GET_CODE (x
) != ASHIFTRT
)
8339 return force_to_mode (x
, mode
, mask
, next_select
);
8343 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8344 even if the shift count isn't a constant. */
8346 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8347 XEXP (x
, 0), XEXP (x
, 1));
8351 /* If this is a zero- or sign-extension operation that just affects bits
8352 we don't care about, remove it. Be sure the call above returned
8353 something that is still a shift. */
8355 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8356 && CONST_INT_P (XEXP (x
, 1))
8357 && INTVAL (XEXP (x
, 1)) >= 0
8358 && (INTVAL (XEXP (x
, 1))
8359 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8360 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8361 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8362 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8369 /* If the shift count is constant and we can do computations
8370 in the mode of X, compute where the bits we care about are.
8371 Otherwise, we can't do anything. Don't change the mode of
8372 the shift or propagate MODE into the shift, though. */
8373 if (CONST_INT_P (XEXP (x
, 1))
8374 && INTVAL (XEXP (x
, 1)) >= 0)
8376 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8377 GET_MODE (x
), GEN_INT (mask
),
8379 if (temp
&& CONST_INT_P (temp
))
8381 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8382 INTVAL (temp
), next_select
));
8387 /* If we just want the low-order bit, the NEG isn't needed since it
8388 won't change the low-order bit. */
8390 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8392 /* We need any bits less significant than the most significant bit in
8393 MASK since carries from those bits will affect the bits we are
8399 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8400 same as the XOR case above. Ensure that the constant we form is not
8401 wider than the mode of X. */
8403 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8404 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8405 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8406 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8407 < GET_MODE_BITSIZE (GET_MODE (x
)))
8408 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8410 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8412 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8413 XEXP (XEXP (x
, 0), 0), temp
);
8414 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8415 temp
, XEXP (XEXP (x
, 0), 1));
8417 return force_to_mode (x
, mode
, mask
, next_select
);
8420 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8421 use the full mask inside the NOT. */
8425 op0
= gen_lowpart_or_truncate (op_mode
,
8426 force_to_mode (XEXP (x
, 0), mode
, mask
,
8428 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8429 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8433 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8434 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8435 which is equal to STORE_FLAG_VALUE. */
8436 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
8437 && GET_MODE (XEXP (x
, 0)) == mode
8438 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8439 && (nonzero_bits (XEXP (x
, 0), mode
)
8440 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8441 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8446 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8447 written in a narrower mode. We play it safe and do not do so. */
8450 gen_lowpart_or_truncate (GET_MODE (x
),
8451 force_to_mode (XEXP (x
, 1), mode
,
8452 mask
, next_select
)));
8454 gen_lowpart_or_truncate (GET_MODE (x
),
8455 force_to_mode (XEXP (x
, 2), mode
,
8456 mask
, next_select
)));
8463 /* Ensure we return a value of the proper mode. */
8464 return gen_lowpart_or_truncate (mode
, x
);
8467 /* Return nonzero if X is an expression that has one of two values depending on
8468 whether some other value is zero or nonzero. In that case, we return the
8469 value that is being tested, *PTRUE is set to the value if the rtx being
8470 returned has a nonzero value, and *PFALSE is set to the other alternative.
8472 If we return zero, we set *PTRUE and *PFALSE to X. */
8475 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8477 enum machine_mode mode
= GET_MODE (x
);
8478 enum rtx_code code
= GET_CODE (x
);
8479 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8480 unsigned HOST_WIDE_INT nz
;
8482 /* If we are comparing a value against zero, we are done. */
8483 if ((code
== NE
|| code
== EQ
)
8484 && XEXP (x
, 1) == const0_rtx
)
8486 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8487 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8491 /* If this is a unary operation whose operand has one of two values, apply
8492 our opcode to compute those values. */
8493 else if (UNARY_P (x
)
8494 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8496 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8497 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8498 GET_MODE (XEXP (x
, 0)));
8502 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8503 make can't possibly match and would suppress other optimizations. */
8504 else if (code
== COMPARE
)
8507 /* If this is a binary operation, see if either side has only one of two
8508 values. If either one does or if both do and they are conditional on
8509 the same value, compute the new true and false values. */
8510 else if (BINARY_P (x
))
8512 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8513 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8515 if ((cond0
!= 0 || cond1
!= 0)
8516 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8518 /* If if_then_else_cond returned zero, then true/false are the
8519 same rtl. We must copy one of them to prevent invalid rtl
8522 true0
= copy_rtx (true0
);
8523 else if (cond1
== 0)
8524 true1
= copy_rtx (true1
);
8526 if (COMPARISON_P (x
))
8528 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8530 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8535 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8536 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8539 return cond0
? cond0
: cond1
;
8542 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8543 operands is zero when the other is nonzero, and vice-versa,
8544 and STORE_FLAG_VALUE is 1 or -1. */
8546 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8547 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8549 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8551 rtx op0
= XEXP (XEXP (x
, 0), 1);
8552 rtx op1
= XEXP (XEXP (x
, 1), 1);
8554 cond0
= XEXP (XEXP (x
, 0), 0);
8555 cond1
= XEXP (XEXP (x
, 1), 0);
8557 if (COMPARISON_P (cond0
)
8558 && COMPARISON_P (cond1
)
8559 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8560 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8561 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8562 || ((swap_condition (GET_CODE (cond0
))
8563 == reversed_comparison_code (cond1
, NULL
))
8564 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8565 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8566 && ! side_effects_p (x
))
8568 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8569 *pfalse
= simplify_gen_binary (MULT
, mode
,
8571 ? simplify_gen_unary (NEG
, mode
,
8579 /* Similarly for MULT, AND and UMIN, except that for these the result
8581 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8582 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8583 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8585 cond0
= XEXP (XEXP (x
, 0), 0);
8586 cond1
= XEXP (XEXP (x
, 1), 0);
8588 if (COMPARISON_P (cond0
)
8589 && COMPARISON_P (cond1
)
8590 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8591 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8592 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8593 || ((swap_condition (GET_CODE (cond0
))
8594 == reversed_comparison_code (cond1
, NULL
))
8595 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8596 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8597 && ! side_effects_p (x
))
8599 *ptrue
= *pfalse
= const0_rtx
;
8605 else if (code
== IF_THEN_ELSE
)
8607 /* If we have IF_THEN_ELSE already, extract the condition and
8608 canonicalize it if it is NE or EQ. */
8609 cond0
= XEXP (x
, 0);
8610 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8611 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8612 return XEXP (cond0
, 0);
8613 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8615 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8616 return XEXP (cond0
, 0);
8622 /* If X is a SUBREG, we can narrow both the true and false values
8623 if the inner expression, if there is a condition. */
8624 else if (code
== SUBREG
8625 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8628 true0
= simplify_gen_subreg (mode
, true0
,
8629 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8630 false0
= simplify_gen_subreg (mode
, false0
,
8631 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8632 if (true0
&& false0
)
8640 /* If X is a constant, this isn't special and will cause confusions
8641 if we treat it as such. Likewise if it is equivalent to a constant. */
8642 else if (CONSTANT_P (x
)
8643 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8646 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8647 will be least confusing to the rest of the compiler. */
8648 else if (mode
== BImode
)
8650 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8654 /* If X is known to be either 0 or -1, those are the true and
8655 false values when testing X. */
8656 else if (x
== constm1_rtx
|| x
== const0_rtx
8657 || (mode
!= VOIDmode
8658 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
8660 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8664 /* Likewise for 0 or a single bit. */
8665 else if (SCALAR_INT_MODE_P (mode
)
8666 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8667 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8669 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8673 /* Otherwise fail; show no condition with true and false values the same. */
8674 *ptrue
= *pfalse
= x
;
8678 /* Return the value of expression X given the fact that condition COND
8679 is known to be true when applied to REG as its first operand and VAL
8680 as its second. X is known to not be shared and so can be modified in
8683 We only handle the simplest cases, and specifically those cases that
8684 arise with IF_THEN_ELSE expressions. */
8687 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8689 enum rtx_code code
= GET_CODE (x
);
8694 if (side_effects_p (x
))
8697 /* If either operand of the condition is a floating point value,
8698 then we have to avoid collapsing an EQ comparison. */
8700 && rtx_equal_p (x
, reg
)
8701 && ! FLOAT_MODE_P (GET_MODE (x
))
8702 && ! FLOAT_MODE_P (GET_MODE (val
)))
8705 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8708 /* If X is (abs REG) and we know something about REG's relationship
8709 with zero, we may be able to simplify this. */
8711 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8714 case GE
: case GT
: case EQ
:
8717 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8719 GET_MODE (XEXP (x
, 0)));
8724 /* The only other cases we handle are MIN, MAX, and comparisons if the
8725 operands are the same as REG and VAL. */
8727 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8729 if (rtx_equal_p (XEXP (x
, 0), val
))
8730 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8732 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8734 if (COMPARISON_P (x
))
8736 if (comparison_dominates_p (cond
, code
))
8737 return const_true_rtx
;
8739 code
= reversed_comparison_code (x
, NULL
);
8741 && comparison_dominates_p (cond
, code
))
8746 else if (code
== SMAX
|| code
== SMIN
8747 || code
== UMIN
|| code
== UMAX
)
8749 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8751 /* Do not reverse the condition when it is NE or EQ.
8752 This is because we cannot conclude anything about
8753 the value of 'SMAX (x, y)' when x is not equal to y,
8754 but we can when x equals y. */
8755 if ((code
== SMAX
|| code
== UMAX
)
8756 && ! (cond
== EQ
|| cond
== NE
))
8757 cond
= reverse_condition (cond
);
8762 return unsignedp
? x
: XEXP (x
, 1);
8764 return unsignedp
? x
: XEXP (x
, 0);
8766 return unsignedp
? XEXP (x
, 1) : x
;
8768 return unsignedp
? XEXP (x
, 0) : x
;
8775 else if (code
== SUBREG
)
8777 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8778 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8780 if (SUBREG_REG (x
) != r
)
8782 /* We must simplify subreg here, before we lose track of the
8783 original inner_mode. */
8784 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8785 inner_mode
, SUBREG_BYTE (x
));
8789 SUBST (SUBREG_REG (x
), r
);
8794 /* We don't have to handle SIGN_EXTEND here, because even in the
8795 case of replacing something with a modeless CONST_INT, a
8796 CONST_INT is already (supposed to be) a valid sign extension for
8797 its narrower mode, which implies it's already properly
8798 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8799 story is different. */
8800 else if (code
== ZERO_EXTEND
)
8802 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8803 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8805 if (XEXP (x
, 0) != r
)
8807 /* We must simplify the zero_extend here, before we lose
8808 track of the original inner_mode. */
8809 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8814 SUBST (XEXP (x
, 0), r
);
8820 fmt
= GET_RTX_FORMAT (code
);
8821 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8824 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8825 else if (fmt
[i
] == 'E')
8826 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8827 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8834 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8835 assignment as a field assignment. */
8838 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8840 if (x
== y
|| rtx_equal_p (x
, y
))
8843 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8846 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8847 Note that all SUBREGs of MEM are paradoxical; otherwise they
8848 would have been rewritten. */
8849 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8850 && MEM_P (SUBREG_REG (y
))
8851 && rtx_equal_p (SUBREG_REG (y
),
8852 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8855 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8856 && MEM_P (SUBREG_REG (x
))
8857 && rtx_equal_p (SUBREG_REG (x
),
8858 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8861 /* We used to see if get_last_value of X and Y were the same but that's
8862 not correct. In one direction, we'll cause the assignment to have
8863 the wrong destination and in the case, we'll import a register into this
8864 insn that might have already have been dead. So fail if none of the
8865 above cases are true. */
8869 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8870 Return that assignment if so.
8872 We only handle the most common cases. */
8875 make_field_assignment (rtx x
)
8877 rtx dest
= SET_DEST (x
);
8878 rtx src
= SET_SRC (x
);
8883 unsigned HOST_WIDE_INT len
;
8885 enum machine_mode mode
;
8887 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8888 a clear of a one-bit field. We will have changed it to
8889 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8892 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8893 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8894 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8895 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8897 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8900 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8904 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8905 && subreg_lowpart_p (XEXP (src
, 0))
8906 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8907 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8908 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8909 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8910 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8911 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8913 assign
= make_extraction (VOIDmode
, dest
, 0,
8914 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8917 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8921 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8923 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8924 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8925 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8927 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8930 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8934 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8935 SRC is an AND with all bits of that field set, then we can discard
8937 if (GET_CODE (dest
) == ZERO_EXTRACT
8938 && CONST_INT_P (XEXP (dest
, 1))
8939 && GET_CODE (src
) == AND
8940 && CONST_INT_P (XEXP (src
, 1)))
8942 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8943 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8944 unsigned HOST_WIDE_INT ze_mask
;
8946 if (width
>= HOST_BITS_PER_WIDE_INT
)
8949 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8951 /* Complete overlap. We can remove the source AND. */
8952 if ((and_mask
& ze_mask
) == ze_mask
)
8953 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
8955 /* Partial overlap. We can reduce the source AND. */
8956 if ((and_mask
& ze_mask
) != and_mask
)
8958 mode
= GET_MODE (src
);
8959 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
8960 gen_int_mode (and_mask
& ze_mask
, mode
));
8961 return gen_rtx_SET (VOIDmode
, dest
, src
);
8965 /* The other case we handle is assignments into a constant-position
8966 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8967 a mask that has all one bits except for a group of zero bits and
8968 OTHER is known to have zeros where C1 has ones, this is such an
8969 assignment. Compute the position and length from C1. Shift OTHER
8970 to the appropriate position, force it to the required mode, and
8971 make the extraction. Check for the AND in both operands. */
8973 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
8976 rhs
= expand_compound_operation (XEXP (src
, 0));
8977 lhs
= expand_compound_operation (XEXP (src
, 1));
8979 if (GET_CODE (rhs
) == AND
8980 && CONST_INT_P (XEXP (rhs
, 1))
8981 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
8982 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
8983 else if (GET_CODE (lhs
) == AND
8984 && CONST_INT_P (XEXP (lhs
, 1))
8985 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
8986 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
8990 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
8991 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
8992 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
8993 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
8996 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9000 /* The mode to use for the source is the mode of the assignment, or of
9001 what is inside a possible STRICT_LOW_PART. */
9002 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9003 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9005 /* Shift OTHER right POS places and make it the source, restricting it
9006 to the proper length and mode. */
9008 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9012 src
= force_to_mode (src
, mode
,
9013 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
9014 ? ~(unsigned HOST_WIDE_INT
) 0
9015 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9018 /* If SRC is masked by an AND that does not make a difference in
9019 the value being stored, strip it. */
9020 if (GET_CODE (assign
) == ZERO_EXTRACT
9021 && CONST_INT_P (XEXP (assign
, 1))
9022 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9023 && GET_CODE (src
) == AND
9024 && CONST_INT_P (XEXP (src
, 1))
9025 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
9026 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
9027 src
= XEXP (src
, 0);
9029 return gen_rtx_SET (VOIDmode
, assign
, src
);
9032 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9036 apply_distributive_law (rtx x
)
9038 enum rtx_code code
= GET_CODE (x
);
9039 enum rtx_code inner_code
;
9040 rtx lhs
, rhs
, other
;
9043 /* Distributivity is not true for floating point as it can change the
9044 value. So we don't do it unless -funsafe-math-optimizations. */
9045 if (FLOAT_MODE_P (GET_MODE (x
))
9046 && ! flag_unsafe_math_optimizations
)
9049 /* The outer operation can only be one of the following: */
9050 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9051 && code
!= PLUS
&& code
!= MINUS
)
9057 /* If either operand is a primitive we can't do anything, so get out
9059 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9062 lhs
= expand_compound_operation (lhs
);
9063 rhs
= expand_compound_operation (rhs
);
9064 inner_code
= GET_CODE (lhs
);
9065 if (inner_code
!= GET_CODE (rhs
))
9068 /* See if the inner and outer operations distribute. */
9075 /* These all distribute except over PLUS. */
9076 if (code
== PLUS
|| code
== MINUS
)
9081 if (code
!= PLUS
&& code
!= MINUS
)
9086 /* This is also a multiply, so it distributes over everything. */
9090 /* Non-paradoxical SUBREGs distributes over all operations,
9091 provided the inner modes and byte offsets are the same, this
9092 is an extraction of a low-order part, we don't convert an fp
9093 operation to int or vice versa, this is not a vector mode,
9094 and we would not be converting a single-word operation into a
9095 multi-word operation. The latter test is not required, but
9096 it prevents generating unneeded multi-word operations. Some
9097 of the previous tests are redundant given the latter test,
9098 but are retained because they are required for correctness.
9100 We produce the result slightly differently in this case. */
9102 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
9103 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
9104 || ! subreg_lowpart_p (lhs
)
9105 || (GET_MODE_CLASS (GET_MODE (lhs
))
9106 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
9107 || (GET_MODE_SIZE (GET_MODE (lhs
))
9108 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
9109 || VECTOR_MODE_P (GET_MODE (lhs
))
9110 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
9111 /* Result might need to be truncated. Don't change mode if
9112 explicit truncation is needed. */
9113 || !TRULY_NOOP_TRUNCATION
9114 (GET_MODE_BITSIZE (GET_MODE (x
)),
9115 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
9118 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
9119 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
9120 return gen_lowpart (GET_MODE (x
), tem
);
9126 /* Set LHS and RHS to the inner operands (A and B in the example
9127 above) and set OTHER to the common operand (C in the example).
9128 There is only one way to do this unless the inner operation is
9130 if (COMMUTATIVE_ARITH_P (lhs
)
9131 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9132 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9133 else if (COMMUTATIVE_ARITH_P (lhs
)
9134 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9135 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9136 else if (COMMUTATIVE_ARITH_P (lhs
)
9137 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9138 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9139 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9140 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9144 /* Form the new inner operation, seeing if it simplifies first. */
9145 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9147 /* There is one exception to the general way of distributing:
9148 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9149 if (code
== XOR
&& inner_code
== IOR
)
9152 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9155 /* We may be able to continuing distributing the result, so call
9156 ourselves recursively on the inner operation before forming the
9157 outer operation, which we return. */
9158 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9159 apply_distributive_law (tem
), other
);
9162 /* See if X is of the form (* (+ A B) C), and if so convert to
9163 (+ (* A C) (* B C)) and try to simplify.
9165 Most of the time, this results in no change. However, if some of
9166 the operands are the same or inverses of each other, simplifications
9169 For example, (and (ior A B) (not B)) can occur as the result of
9170 expanding a bit field assignment. When we apply the distributive
9171 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9172 which then simplifies to (and (A (not B))).
9174 Note that no checks happen on the validity of applying the inverse
9175 distributive law. This is pointless since we can do it in the
9176 few places where this routine is called.
9178 N is the index of the term that is decomposed (the arithmetic operation,
9179 i.e. (+ A B) in the first example above). !N is the index of the term that
9180 is distributed, i.e. of C in the first example above. */
9182 distribute_and_simplify_rtx (rtx x
, int n
)
9184 enum machine_mode mode
;
9185 enum rtx_code outer_code
, inner_code
;
9186 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9188 /* Distributivity is not true for floating point as it can change the
9189 value. So we don't do it unless -funsafe-math-optimizations. */
9190 if (FLOAT_MODE_P (GET_MODE (x
))
9191 && ! flag_unsafe_math_optimizations
)
9194 decomposed
= XEXP (x
, n
);
9195 if (!ARITHMETIC_P (decomposed
))
9198 mode
= GET_MODE (x
);
9199 outer_code
= GET_CODE (x
);
9200 distributed
= XEXP (x
, !n
);
9202 inner_code
= GET_CODE (decomposed
);
9203 inner_op0
= XEXP (decomposed
, 0);
9204 inner_op1
= XEXP (decomposed
, 1);
9206 /* Special case (and (xor B C) (not A)), which is equivalent to
9207 (xor (ior A B) (ior A C)) */
9208 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9210 distributed
= XEXP (distributed
, 0);
9216 /* Distribute the second term. */
9217 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9218 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9222 /* Distribute the first term. */
9223 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9224 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9227 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9229 if (GET_CODE (tmp
) != outer_code
9230 && rtx_cost (tmp
, SET
, optimize_this_for_speed_p
)
9231 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
9237 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9238 in MODE. Return an equivalent form, if different from (and VAROP
9239 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9242 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9243 unsigned HOST_WIDE_INT constop
)
9245 unsigned HOST_WIDE_INT nonzero
;
9246 unsigned HOST_WIDE_INT orig_constop
;
9251 orig_constop
= constop
;
9252 if (GET_CODE (varop
) == CLOBBER
)
9255 /* Simplify VAROP knowing that we will be only looking at some of the
9258 Note by passing in CONSTOP, we guarantee that the bits not set in
9259 CONSTOP are not significant and will never be examined. We must
9260 ensure that is the case by explicitly masking out those bits
9261 before returning. */
9262 varop
= force_to_mode (varop
, mode
, constop
, 0);
9264 /* If VAROP is a CLOBBER, we will fail so return it. */
9265 if (GET_CODE (varop
) == CLOBBER
)
9268 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9269 to VAROP and return the new constant. */
9270 if (CONST_INT_P (varop
))
9271 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9273 /* See what bits may be nonzero in VAROP. Unlike the general case of
9274 a call to nonzero_bits, here we don't care about bits outside
9277 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9279 /* Turn off all bits in the constant that are known to already be zero.
9280 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9281 which is tested below. */
9285 /* If we don't have any bits left, return zero. */
9289 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9290 a power of two, we can replace this with an ASHIFT. */
9291 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9292 && (i
= exact_log2 (constop
)) >= 0)
9293 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9295 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9296 or XOR, then try to apply the distributive law. This may eliminate
9297 operations if either branch can be simplified because of the AND.
9298 It may also make some cases more complex, but those cases probably
9299 won't match a pattern either with or without this. */
9301 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9305 apply_distributive_law
9306 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9307 simplify_and_const_int (NULL_RTX
,
9311 simplify_and_const_int (NULL_RTX
,
9316 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9317 the AND and see if one of the operands simplifies to zero. If so, we
9318 may eliminate it. */
9320 if (GET_CODE (varop
) == PLUS
9321 && exact_log2 (constop
+ 1) >= 0)
9325 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9326 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9327 if (o0
== const0_rtx
)
9329 if (o1
== const0_rtx
)
9333 /* Make a SUBREG if necessary. If we can't make it, fail. */
9334 varop
= gen_lowpart (mode
, varop
);
9335 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9338 /* If we are only masking insignificant bits, return VAROP. */
9339 if (constop
== nonzero
)
9342 if (varop
== orig_varop
&& constop
== orig_constop
)
9345 /* Otherwise, return an AND. */
9346 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9350 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9353 Return an equivalent form, if different from X. Otherwise, return X. If
9354 X is zero, we are to always construct the equivalent form. */
9357 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9358 unsigned HOST_WIDE_INT constop
)
9360 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9365 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9366 gen_int_mode (constop
, mode
));
9367 if (GET_MODE (x
) != mode
)
9368 x
= gen_lowpart (mode
, x
);
9372 /* Given a REG, X, compute which bits in X can be nonzero.
9373 We don't care about bits outside of those defined in MODE.
9375 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9376 a shift, AND, or zero_extract, we can do better. */
9379 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9380 const_rtx known_x ATTRIBUTE_UNUSED
,
9381 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9382 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9383 unsigned HOST_WIDE_INT
*nonzero
)
9388 /* If X is a register whose nonzero bits value is current, use it.
9389 Otherwise, if X is a register whose value we can find, use that
9390 value. Otherwise, use the previously-computed global nonzero bits
9391 for this register. */
9393 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9394 if (rsp
->last_set_value
!= 0
9395 && (rsp
->last_set_mode
== mode
9396 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9397 && GET_MODE_CLASS (mode
) == MODE_INT
))
9398 && ((rsp
->last_set_label
>= label_tick_ebb_start
9399 && rsp
->last_set_label
< label_tick
)
9400 || (rsp
->last_set_label
== label_tick
9401 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9402 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9403 && REG_N_SETS (REGNO (x
)) == 1
9405 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9407 *nonzero
&= rsp
->last_set_nonzero_bits
;
9411 tem
= get_last_value (x
);
9415 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9416 /* If X is narrower than MODE and TEM is a non-negative
9417 constant that would appear negative in the mode of X,
9418 sign-extend it for use in reg_nonzero_bits because some
9419 machines (maybe most) will actually do the sign-extension
9420 and this is the conservative approach.
9422 ??? For 2.5, try to tighten up the MD files in this regard
9423 instead of this kludge. */
9425 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
9426 && CONST_INT_P (tem
)
9428 && 0 != (INTVAL (tem
)
9429 & ((HOST_WIDE_INT
) 1
9430 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
9431 tem
= GEN_INT (INTVAL (tem
)
9432 | ((HOST_WIDE_INT
) (-1)
9433 << GET_MODE_BITSIZE (GET_MODE (x
))));
9437 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9439 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9441 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
9442 /* We don't know anything about the upper bits. */
9443 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9450 /* Return the number of bits at the high-order end of X that are known to
9451 be equal to the sign bit. X will be used in mode MODE; if MODE is
9452 VOIDmode, X will be used in its own mode. The returned value will always
9453 be between 1 and the number of bits in MODE. */
9456 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9457 const_rtx known_x ATTRIBUTE_UNUSED
,
9458 enum machine_mode known_mode
9460 unsigned int known_ret ATTRIBUTE_UNUSED
,
9461 unsigned int *result
)
9466 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9467 if (rsp
->last_set_value
!= 0
9468 && rsp
->last_set_mode
== mode
9469 && ((rsp
->last_set_label
>= label_tick_ebb_start
9470 && rsp
->last_set_label
< label_tick
)
9471 || (rsp
->last_set_label
== label_tick
9472 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9473 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9474 && REG_N_SETS (REGNO (x
)) == 1
9476 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9478 *result
= rsp
->last_set_sign_bit_copies
;
9482 tem
= get_last_value (x
);
9486 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9487 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
9488 *result
= rsp
->sign_bit_copies
;
9493 /* Return the number of "extended" bits there are in X, when interpreted
9494 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9495 unsigned quantities, this is the number of high-order zero bits.
9496 For signed quantities, this is the number of copies of the sign bit
9497 minus 1. In both case, this function returns the number of "spare"
9498 bits. For example, if two quantities for which this function returns
9499 at least 1 are added, the addition is known not to overflow.
9501 This function will always return 0 unless called during combine, which
9502 implies that it must be called from a define_split. */
9505 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9507 if (nonzero_sign_valid
== 0)
9511 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9512 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
9513 - floor_log2 (nonzero_bits (x
, mode
)))
9515 : num_sign_bit_copies (x
, mode
) - 1);
9518 /* This function is called from `simplify_shift_const' to merge two
9519 outer operations. Specifically, we have already found that we need
9520 to perform operation *POP0 with constant *PCONST0 at the outermost
9521 position. We would now like to also perform OP1 with constant CONST1
9522 (with *POP0 being done last).
9524 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9525 the resulting operation. *PCOMP_P is set to 1 if we would need to
9526 complement the innermost operand, otherwise it is unchanged.
9528 MODE is the mode in which the operation will be done. No bits outside
9529 the width of this mode matter. It is assumed that the width of this mode
9530 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9532 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9533 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9534 result is simply *PCONST0.
9536 If the resulting operation cannot be expressed as one operation, we
9537 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9540 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9542 enum rtx_code op0
= *pop0
;
9543 HOST_WIDE_INT const0
= *pconst0
;
9545 const0
&= GET_MODE_MASK (mode
);
9546 const1
&= GET_MODE_MASK (mode
);
9548 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9552 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9555 if (op1
== UNKNOWN
|| op0
== SET
)
9558 else if (op0
== UNKNOWN
)
9559 op0
= op1
, const0
= const1
;
9561 else if (op0
== op1
)
9585 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9586 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9589 /* If the two constants aren't the same, we can't do anything. The
9590 remaining six cases can all be done. */
9591 else if (const0
!= const1
)
9599 /* (a & b) | b == b */
9601 else /* op1 == XOR */
9602 /* (a ^ b) | b == a | b */
9608 /* (a & b) ^ b == (~a) & b */
9609 op0
= AND
, *pcomp_p
= 1;
9610 else /* op1 == IOR */
9611 /* (a | b) ^ b == a & ~b */
9612 op0
= AND
, const0
= ~const0
;
9617 /* (a | b) & b == b */
9619 else /* op1 == XOR */
9620 /* (a ^ b) & b) == (~a) & b */
9627 /* Check for NO-OP cases. */
9628 const0
&= GET_MODE_MASK (mode
);
9630 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9632 else if (const0
== 0 && op0
== AND
)
9634 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9640 /* ??? Slightly redundant with the above mask, but not entirely.
9641 Moving this above means we'd have to sign-extend the mode mask
9642 for the final test. */
9643 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9644 *pconst0
= trunc_int_for_mode (const0
, mode
);
9649 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9650 the shift in. The original shift operation CODE is performed on OP in
9651 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9652 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9653 result of the shift is subject to operation OUTER_CODE with operand
9656 static enum machine_mode
9657 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9658 enum machine_mode orig_mode
, enum machine_mode mode
,
9659 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9661 if (orig_mode
== mode
)
9663 gcc_assert (GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (orig_mode
));
9665 /* In general we can't perform in wider mode for right shift and rotate. */
9669 /* We can still widen if the bits brought in from the left are identical
9670 to the sign bit of ORIG_MODE. */
9671 if (num_sign_bit_copies (op
, mode
)
9672 > (unsigned) (GET_MODE_BITSIZE (mode
)
9673 - GET_MODE_BITSIZE (orig_mode
)))
9678 /* Similarly here but with zero bits. */
9679 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9680 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9683 /* We can also widen if the bits brought in will be masked off. This
9684 operation is performed in ORIG_MODE. */
9685 if (outer_code
== AND
)
9687 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9690 && GET_MODE_BITSIZE (orig_mode
) - care_bits
>= count
)
9706 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9707 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9708 simplify it. Otherwise, return a simplified value.
9710 The shift is normally computed in the widest mode we find in VAROP, as
9711 long as it isn't a different number of words than RESULT_MODE. Exceptions
9712 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9715 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9716 rtx varop
, int orig_count
)
9718 enum rtx_code orig_code
= code
;
9719 rtx orig_varop
= varop
;
9721 enum machine_mode mode
= result_mode
;
9722 enum machine_mode shift_mode
, tmode
;
9723 unsigned int mode_words
9724 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9725 /* We form (outer_op (code varop count) (outer_const)). */
9726 enum rtx_code outer_op
= UNKNOWN
;
9727 HOST_WIDE_INT outer_const
= 0;
9728 int complement_p
= 0;
9731 /* Make sure and truncate the "natural" shift on the way in. We don't
9732 want to do this inside the loop as it makes it more difficult to
9734 if (SHIFT_COUNT_TRUNCATED
)
9735 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9737 /* If we were given an invalid count, don't do anything except exactly
9738 what was requested. */
9740 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9745 /* Unless one of the branches of the `if' in this loop does a `continue',
9746 we will `break' the loop after the `if'. */
9750 /* If we have an operand of (clobber (const_int 0)), fail. */
9751 if (GET_CODE (varop
) == CLOBBER
)
9754 /* Convert ROTATERT to ROTATE. */
9755 if (code
== ROTATERT
)
9757 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9759 if (VECTOR_MODE_P (result_mode
))
9760 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9762 count
= bitsize
- count
;
9765 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9766 mode
, outer_op
, outer_const
);
9768 /* Handle cases where the count is greater than the size of the mode
9769 minus 1. For ASHIFT, use the size minus one as the count (this can
9770 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9771 take the count modulo the size. For other shifts, the result is
9774 Since these shifts are being produced by the compiler by combining
9775 multiple operations, each of which are defined, we know what the
9776 result is supposed to be. */
9778 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
9780 if (code
== ASHIFTRT
)
9781 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9782 else if (code
== ROTATE
|| code
== ROTATERT
)
9783 count
%= GET_MODE_BITSIZE (shift_mode
);
9786 /* We can't simply return zero because there may be an
9794 /* If we discovered we had to complement VAROP, leave. Making a NOT
9795 here would cause an infinite loop. */
9799 /* An arithmetic right shift of a quantity known to be -1 or 0
9801 if (code
== ASHIFTRT
9802 && (num_sign_bit_copies (varop
, shift_mode
)
9803 == GET_MODE_BITSIZE (shift_mode
)))
9809 /* If we are doing an arithmetic right shift and discarding all but
9810 the sign bit copies, this is equivalent to doing a shift by the
9811 bitsize minus one. Convert it into that shift because it will often
9812 allow other simplifications. */
9814 if (code
== ASHIFTRT
9815 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9816 >= GET_MODE_BITSIZE (shift_mode
)))
9817 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9819 /* We simplify the tests below and elsewhere by converting
9820 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9821 `make_compound_operation' will convert it to an ASHIFTRT for
9822 those machines (such as VAX) that don't have an LSHIFTRT. */
9823 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9825 && ((nonzero_bits (varop
, shift_mode
)
9826 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9830 if (((code
== LSHIFTRT
9831 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9832 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9834 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9835 && !((nonzero_bits (varop
, shift_mode
) << count
)
9836 & GET_MODE_MASK (shift_mode
))))
9837 && !side_effects_p (varop
))
9840 switch (GET_CODE (varop
))
9846 new_rtx
= expand_compound_operation (varop
);
9847 if (new_rtx
!= varop
)
9855 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9856 minus the width of a smaller mode, we can do this with a
9857 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9858 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9859 && ! mode_dependent_address_p (XEXP (varop
, 0))
9860 && ! MEM_VOLATILE_P (varop
)
9861 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9862 MODE_INT
, 1)) != BLKmode
)
9864 new_rtx
= adjust_address_nv (varop
, tmode
,
9865 BYTES_BIG_ENDIAN
? 0
9866 : count
/ BITS_PER_UNIT
);
9868 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9869 : ZERO_EXTEND
, mode
, new_rtx
);
9876 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9877 the same number of words as what we've seen so far. Then store
9878 the widest mode in MODE. */
9879 if (subreg_lowpart_p (varop
)
9880 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9881 > GET_MODE_SIZE (GET_MODE (varop
)))
9882 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9883 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9885 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9886 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9888 varop
= SUBREG_REG (varop
);
9889 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9890 mode
= GET_MODE (varop
);
9896 /* Some machines use MULT instead of ASHIFT because MULT
9897 is cheaper. But it is still better on those machines to
9898 merge two shifts into one. */
9899 if (CONST_INT_P (XEXP (varop
, 1))
9900 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9903 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9905 GEN_INT (exact_log2 (
9906 INTVAL (XEXP (varop
, 1)))));
9912 /* Similar, for when divides are cheaper. */
9913 if (CONST_INT_P (XEXP (varop
, 1))
9914 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9917 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9919 GEN_INT (exact_log2 (
9920 INTVAL (XEXP (varop
, 1)))));
9926 /* If we are extracting just the sign bit of an arithmetic
9927 right shift, that shift is not needed. However, the sign
9928 bit of a wider mode may be different from what would be
9929 interpreted as the sign bit in a narrower mode, so, if
9930 the result is narrower, don't discard the shift. */
9931 if (code
== LSHIFTRT
9932 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9933 && (GET_MODE_BITSIZE (result_mode
)
9934 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9936 varop
= XEXP (varop
, 0);
9940 /* ... fall through ... */
9945 /* Here we have two nested shifts. The result is usually the
9946 AND of a new shift with a mask. We compute the result below. */
9947 if (CONST_INT_P (XEXP (varop
, 1))
9948 && INTVAL (XEXP (varop
, 1)) >= 0
9949 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9950 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9951 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9952 && !VECTOR_MODE_P (result_mode
))
9954 enum rtx_code first_code
= GET_CODE (varop
);
9955 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9956 unsigned HOST_WIDE_INT mask
;
9959 /* We have one common special case. We can't do any merging if
9960 the inner code is an ASHIFTRT of a smaller mode. However, if
9961 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9962 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9963 we can convert it to
9964 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9965 This simplifies certain SIGN_EXTEND operations. */
9966 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9967 && count
== (GET_MODE_BITSIZE (result_mode
)
9968 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9970 /* C3 has the low-order C1 bits zero. */
9972 mask
= (GET_MODE_MASK (mode
)
9973 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9975 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9976 XEXP (varop
, 0), mask
);
9977 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9979 count
= first_count
;
9984 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9985 than C1 high-order bits equal to the sign bit, we can convert
9986 this to either an ASHIFT or an ASHIFTRT depending on the
9989 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9991 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9992 && GET_MODE (varop
) == shift_mode
9993 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9996 varop
= XEXP (varop
, 0);
9997 count
-= first_count
;
10007 /* There are some cases we can't do. If CODE is ASHIFTRT,
10008 we can only do this if FIRST_CODE is also ASHIFTRT.
10010 We can't do the case when CODE is ROTATE and FIRST_CODE is
10013 If the mode of this shift is not the mode of the outer shift,
10014 we can't do this if either shift is a right shift or ROTATE.
10016 Finally, we can't do any of these if the mode is too wide
10017 unless the codes are the same.
10019 Handle the case where the shift codes are the same
10022 if (code
== first_code
)
10024 if (GET_MODE (varop
) != result_mode
10025 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10026 || code
== ROTATE
))
10029 count
+= first_count
;
10030 varop
= XEXP (varop
, 0);
10034 if (code
== ASHIFTRT
10035 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10036 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
10037 || (GET_MODE (varop
) != result_mode
10038 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10039 || first_code
== ROTATE
10040 || code
== ROTATE
)))
10043 /* To compute the mask to apply after the shift, shift the
10044 nonzero bits of the inner shift the same way the
10045 outer shift will. */
10047 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10050 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10053 /* Give up if we can't compute an outer operation to use. */
10055 || !CONST_INT_P (mask_rtx
)
10056 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10058 result_mode
, &complement_p
))
10061 /* If the shifts are in the same direction, we add the
10062 counts. Otherwise, we subtract them. */
10063 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10064 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10065 count
+= first_count
;
10067 count
-= first_count
;
10069 /* If COUNT is positive, the new shift is usually CODE,
10070 except for the two exceptions below, in which case it is
10071 FIRST_CODE. If the count is negative, FIRST_CODE should
10074 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10075 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10077 else if (count
< 0)
10078 code
= first_code
, count
= -count
;
10080 varop
= XEXP (varop
, 0);
10084 /* If we have (A << B << C) for any shift, we can convert this to
10085 (A << C << B). This wins if A is a constant. Only try this if
10086 B is not a constant. */
10088 else if (GET_CODE (varop
) == code
10089 && CONST_INT_P (XEXP (varop
, 0))
10090 && !CONST_INT_P (XEXP (varop
, 1)))
10092 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10095 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10102 if (VECTOR_MODE_P (mode
))
10105 /* Make this fit the case below. */
10106 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
10107 GEN_INT (GET_MODE_MASK (mode
)));
10113 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10114 with C the size of VAROP - 1 and the shift is logical if
10115 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10116 we have an (le X 0) operation. If we have an arithmetic shift
10117 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10118 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10120 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10121 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10122 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10123 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10124 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10125 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10128 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10131 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10132 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10137 /* If we have (shift (logical)), move the logical to the outside
10138 to allow it to possibly combine with another logical and the
10139 shift to combine with another shift. This also canonicalizes to
10140 what a ZERO_EXTRACT looks like. Also, some machines have
10141 (and (shift)) insns. */
10143 if (CONST_INT_P (XEXP (varop
, 1))
10144 /* We can't do this if we have (ashiftrt (xor)) and the
10145 constant has its sign bit set in shift_mode. */
10146 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10147 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10149 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10151 GEN_INT (count
))) != 0
10152 && CONST_INT_P (new_rtx
)
10153 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10154 INTVAL (new_rtx
), result_mode
, &complement_p
))
10156 varop
= XEXP (varop
, 0);
10160 /* If we can't do that, try to simplify the shift in each arm of the
10161 logical expression, make a new logical expression, and apply
10162 the inverse distributive law. This also can't be done
10163 for some (ashiftrt (xor)). */
10164 if (CONST_INT_P (XEXP (varop
, 1))
10165 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10166 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10169 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10170 XEXP (varop
, 0), count
);
10171 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10172 XEXP (varop
, 1), count
);
10174 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10176 varop
= apply_distributive_law (varop
);
10184 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10185 says that the sign bit can be tested, FOO has mode MODE, C is
10186 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10187 that may be nonzero. */
10188 if (code
== LSHIFTRT
10189 && XEXP (varop
, 1) == const0_rtx
10190 && GET_MODE (XEXP (varop
, 0)) == result_mode
10191 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10192 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10193 && STORE_FLAG_VALUE
== -1
10194 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10195 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10196 (HOST_WIDE_INT
) 1, result_mode
,
10199 varop
= XEXP (varop
, 0);
10206 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10207 than the number of bits in the mode is equivalent to A. */
10208 if (code
== LSHIFTRT
10209 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10210 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10212 varop
= XEXP (varop
, 0);
10217 /* NEG commutes with ASHIFT since it is multiplication. Move the
10218 NEG outside to allow shifts to combine. */
10220 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
10221 (HOST_WIDE_INT
) 0, result_mode
,
10224 varop
= XEXP (varop
, 0);
10230 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10231 is one less than the number of bits in the mode is
10232 equivalent to (xor A 1). */
10233 if (code
== LSHIFTRT
10234 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10235 && XEXP (varop
, 1) == constm1_rtx
10236 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10237 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10238 (HOST_WIDE_INT
) 1, result_mode
,
10242 varop
= XEXP (varop
, 0);
10246 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10247 that might be nonzero in BAR are those being shifted out and those
10248 bits are known zero in FOO, we can replace the PLUS with FOO.
10249 Similarly in the other operand order. This code occurs when
10250 we are computing the size of a variable-size array. */
10252 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10253 && count
< HOST_BITS_PER_WIDE_INT
10254 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10255 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10256 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10258 varop
= XEXP (varop
, 0);
10261 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10262 && count
< HOST_BITS_PER_WIDE_INT
10263 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10264 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10266 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10267 & nonzero_bits (XEXP (varop
, 1),
10270 varop
= XEXP (varop
, 1);
10274 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10276 && CONST_INT_P (XEXP (varop
, 1))
10277 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10279 GEN_INT (count
))) != 0
10280 && CONST_INT_P (new_rtx
)
10281 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10282 INTVAL (new_rtx
), result_mode
, &complement_p
))
10284 varop
= XEXP (varop
, 0);
10288 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10289 signbit', and attempt to change the PLUS to an XOR and move it to
10290 the outer operation as is done above in the AND/IOR/XOR case
10291 leg for shift(logical). See details in logical handling above
10292 for reasoning in doing so. */
10293 if (code
== LSHIFTRT
10294 && CONST_INT_P (XEXP (varop
, 1))
10295 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10296 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10298 GEN_INT (count
))) != 0
10299 && CONST_INT_P (new_rtx
)
10300 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10301 INTVAL (new_rtx
), result_mode
, &complement_p
))
10303 varop
= XEXP (varop
, 0);
10310 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10311 with C the size of VAROP - 1 and the shift is logical if
10312 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10313 we have a (gt X 0) operation. If the shift is arithmetic with
10314 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10315 we have a (neg (gt X 0)) operation. */
10317 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10318 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10319 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10320 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10321 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10322 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10323 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10326 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10329 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10330 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10337 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10338 if the truncate does not affect the value. */
10339 if (code
== LSHIFTRT
10340 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10341 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10342 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10343 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
10344 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
10346 rtx varop_inner
= XEXP (varop
, 0);
10349 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10350 XEXP (varop_inner
, 0),
10352 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10353 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10366 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10367 outer_op
, outer_const
);
10369 /* We have now finished analyzing the shift. The result should be
10370 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10371 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10372 to the result of the shift. OUTER_CONST is the relevant constant,
10373 but we must turn off all bits turned off in the shift. */
10375 if (outer_op
== UNKNOWN
10376 && orig_code
== code
&& orig_count
== count
10377 && varop
== orig_varop
10378 && shift_mode
== GET_MODE (varop
))
10381 /* Make a SUBREG if necessary. If we can't make it, fail. */
10382 varop
= gen_lowpart (shift_mode
, varop
);
10383 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10386 /* If we have an outer operation and we just made a shift, it is
10387 possible that we could have simplified the shift were it not
10388 for the outer operation. So try to do the simplification
10391 if (outer_op
!= UNKNOWN
)
10392 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10397 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10399 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10400 turn off all the bits that the shift would have turned off. */
10401 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10402 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10403 GET_MODE_MASK (result_mode
) >> orig_count
);
10405 /* Do the remainder of the processing in RESULT_MODE. */
10406 x
= gen_lowpart_or_truncate (result_mode
, x
);
10408 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10411 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10413 if (outer_op
!= UNKNOWN
)
10415 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10416 && GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10417 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10419 if (outer_op
== AND
)
10420 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10421 else if (outer_op
== SET
)
10423 /* This means that we have determined that the result is
10424 equivalent to a constant. This should be rare. */
10425 if (!side_effects_p (x
))
10426 x
= GEN_INT (outer_const
);
10428 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10429 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10431 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10432 GEN_INT (outer_const
));
10438 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10439 The result of the shift is RESULT_MODE. If we cannot simplify it,
10440 return X or, if it is NULL, synthesize the expression with
10441 simplify_gen_binary. Otherwise, return a simplified value.
10443 The shift is normally computed in the widest mode we find in VAROP, as
10444 long as it isn't a different number of words than RESULT_MODE. Exceptions
10445 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10448 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10449 rtx varop
, int count
)
10451 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10456 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10457 if (GET_MODE (x
) != result_mode
)
10458 x
= gen_lowpart (result_mode
, x
);
10463 /* Like recog, but we receive the address of a pointer to a new pattern.
10464 We try to match the rtx that the pointer points to.
10465 If that fails, we may try to modify or replace the pattern,
10466 storing the replacement into the same pointer object.
10468 Modifications include deletion or addition of CLOBBERs.
10470 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10471 the CLOBBERs are placed.
10473 The value is the final insn code from the pattern ultimately matched,
10477 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10479 rtx pat
= *pnewpat
;
10480 int insn_code_number
;
10481 int num_clobbers_to_add
= 0;
10484 rtx old_notes
, old_pat
;
10486 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10487 we use to indicate that something didn't match. If we find such a
10488 thing, force rejection. */
10489 if (GET_CODE (pat
) == PARALLEL
)
10490 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10491 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10492 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10495 old_pat
= PATTERN (insn
);
10496 old_notes
= REG_NOTES (insn
);
10497 PATTERN (insn
) = pat
;
10498 REG_NOTES (insn
) = 0;
10500 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10501 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10503 if (insn_code_number
< 0)
10504 fputs ("Failed to match this instruction:\n", dump_file
);
10506 fputs ("Successfully matched this instruction:\n", dump_file
);
10507 print_rtl_single (dump_file
, pat
);
10510 /* If it isn't, there is the possibility that we previously had an insn
10511 that clobbered some register as a side effect, but the combined
10512 insn doesn't need to do that. So try once more without the clobbers
10513 unless this represents an ASM insn. */
10515 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10516 && GET_CODE (pat
) == PARALLEL
)
10520 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10521 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10524 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10528 SUBST_INT (XVECLEN (pat
, 0), pos
);
10531 pat
= XVECEXP (pat
, 0, 0);
10533 PATTERN (insn
) = pat
;
10534 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10535 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10537 if (insn_code_number
< 0)
10538 fputs ("Failed to match this instruction:\n", dump_file
);
10540 fputs ("Successfully matched this instruction:\n", dump_file
);
10541 print_rtl_single (dump_file
, pat
);
10544 PATTERN (insn
) = old_pat
;
10545 REG_NOTES (insn
) = old_notes
;
10547 /* Recognize all noop sets, these will be killed by followup pass. */
10548 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10549 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10551 /* If we had any clobbers to add, make a new pattern than contains
10552 them. Then check to make sure that all of them are dead. */
10553 if (num_clobbers_to_add
)
10555 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10556 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10557 ? (XVECLEN (pat
, 0)
10558 + num_clobbers_to_add
)
10559 : num_clobbers_to_add
+ 1));
10561 if (GET_CODE (pat
) == PARALLEL
)
10562 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10563 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10565 XVECEXP (newpat
, 0, 0) = pat
;
10567 add_clobbers (newpat
, insn_code_number
);
10569 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10570 i
< XVECLEN (newpat
, 0); i
++)
10572 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10573 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10575 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10577 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10578 notes
= alloc_reg_note (REG_UNUSED
,
10579 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10588 return insn_code_number
;
10591 /* Like gen_lowpart_general but for use by combine. In combine it
10592 is not possible to create any new pseudoregs. However, it is
10593 safe to create invalid memory addresses, because combine will
10594 try to recognize them and all they will do is make the combine
10597 If for some reason this cannot do its job, an rtx
10598 (clobber (const_int 0)) is returned.
10599 An insn containing that will not be recognized. */
10602 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10604 enum machine_mode imode
= GET_MODE (x
);
10605 unsigned int osize
= GET_MODE_SIZE (omode
);
10606 unsigned int isize
= GET_MODE_SIZE (imode
);
10609 if (omode
== imode
)
10612 /* Return identity if this is a CONST or symbolic reference. */
10614 && (GET_CODE (x
) == CONST
10615 || GET_CODE (x
) == SYMBOL_REF
10616 || GET_CODE (x
) == LABEL_REF
))
10619 /* We can only support MODE being wider than a word if X is a
10620 constant integer or has a mode the same size. */
10621 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10622 && ! ((imode
== VOIDmode
10623 && (CONST_INT_P (x
)
10624 || GET_CODE (x
) == CONST_DOUBLE
))
10625 || isize
== osize
))
10628 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10629 won't know what to do. So we will strip off the SUBREG here and
10630 process normally. */
10631 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10633 x
= SUBREG_REG (x
);
10635 /* For use in case we fall down into the address adjustments
10636 further below, we need to adjust the known mode and size of
10637 x; imode and isize, since we just adjusted x. */
10638 imode
= GET_MODE (x
);
10640 if (imode
== omode
)
10643 isize
= GET_MODE_SIZE (imode
);
10646 result
= gen_lowpart_common (omode
, x
);
10655 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10657 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10660 /* If we want to refer to something bigger than the original memref,
10661 generate a paradoxical subreg instead. That will force a reload
10662 of the original memref X. */
10664 return gen_rtx_SUBREG (omode
, x
, 0);
10666 if (WORDS_BIG_ENDIAN
)
10667 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10669 /* Adjust the address so that the address-after-the-data is
10671 if (BYTES_BIG_ENDIAN
)
10672 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10674 return adjust_address_nv (x
, omode
, offset
);
10677 /* If X is a comparison operator, rewrite it in a new mode. This
10678 probably won't match, but may allow further simplifications. */
10679 else if (COMPARISON_P (x
))
10680 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10682 /* If we couldn't simplify X any other way, just enclose it in a
10683 SUBREG. Normally, this SUBREG won't match, but some patterns may
10684 include an explicit SUBREG or we may simplify it further in combine. */
10690 offset
= subreg_lowpart_offset (omode
, imode
);
10691 if (imode
== VOIDmode
)
10693 imode
= int_mode_for_mode (omode
);
10694 x
= gen_lowpart_common (imode
, x
);
10698 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10704 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10707 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10708 comparison code that will be tested.
10710 The result is a possibly different comparison code to use. *POP0 and
10711 *POP1 may be updated.
10713 It is possible that we might detect that a comparison is either always
10714 true or always false. However, we do not perform general constant
10715 folding in combine, so this knowledge isn't useful. Such tautologies
10716 should have been detected earlier. Hence we ignore all such cases. */
10718 static enum rtx_code
10719 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10725 enum machine_mode mode
, tmode
;
10727 /* Try a few ways of applying the same transformation to both operands. */
10730 #ifndef WORD_REGISTER_OPERATIONS
10731 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10732 so check specially. */
10733 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10734 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10735 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10736 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10737 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10738 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10739 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10740 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10741 && CONST_INT_P (XEXP (op0
, 1))
10742 && XEXP (op0
, 1) == XEXP (op1
, 1)
10743 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10744 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10745 && (INTVAL (XEXP (op0
, 1))
10746 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10747 - (GET_MODE_BITSIZE
10748 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10750 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10751 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10755 /* If both operands are the same constant shift, see if we can ignore the
10756 shift. We can if the shift is a rotate or if the bits shifted out of
10757 this shift are known to be zero for both inputs and if the type of
10758 comparison is compatible with the shift. */
10759 if (GET_CODE (op0
) == GET_CODE (op1
)
10760 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10761 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10762 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10763 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10764 || (GET_CODE (op0
) == ASHIFTRT
10765 && (code
!= GTU
&& code
!= LTU
10766 && code
!= GEU
&& code
!= LEU
)))
10767 && CONST_INT_P (XEXP (op0
, 1))
10768 && INTVAL (XEXP (op0
, 1)) >= 0
10769 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10770 && XEXP (op0
, 1) == XEXP (op1
, 1))
10772 enum machine_mode mode
= GET_MODE (op0
);
10773 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10774 int shift_count
= INTVAL (XEXP (op0
, 1));
10776 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10777 mask
&= (mask
>> shift_count
) << shift_count
;
10778 else if (GET_CODE (op0
) == ASHIFT
)
10779 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10781 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10782 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10783 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10788 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10789 SUBREGs are of the same mode, and, in both cases, the AND would
10790 be redundant if the comparison was done in the narrower mode,
10791 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10792 and the operand's possibly nonzero bits are 0xffffff01; in that case
10793 if we only care about QImode, we don't need the AND). This case
10794 occurs if the output mode of an scc insn is not SImode and
10795 STORE_FLAG_VALUE == 1 (e.g., the 386).
10797 Similarly, check for a case where the AND's are ZERO_EXTEND
10798 operations from some narrower mode even though a SUBREG is not
10801 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10802 && CONST_INT_P (XEXP (op0
, 1))
10803 && CONST_INT_P (XEXP (op1
, 1)))
10805 rtx inner_op0
= XEXP (op0
, 0);
10806 rtx inner_op1
= XEXP (op1
, 0);
10807 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10808 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10811 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10812 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10813 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10814 && (GET_MODE (SUBREG_REG (inner_op0
))
10815 == GET_MODE (SUBREG_REG (inner_op1
)))
10816 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10817 <= HOST_BITS_PER_WIDE_INT
)
10818 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10819 GET_MODE (SUBREG_REG (inner_op0
)))))
10820 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10821 GET_MODE (SUBREG_REG (inner_op1
))))))
10823 op0
= SUBREG_REG (inner_op0
);
10824 op1
= SUBREG_REG (inner_op1
);
10826 /* The resulting comparison is always unsigned since we masked
10827 off the original sign bit. */
10828 code
= unsigned_condition (code
);
10834 for (tmode
= GET_CLASS_NARROWEST_MODE
10835 (GET_MODE_CLASS (GET_MODE (op0
)));
10836 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10837 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10839 op0
= gen_lowpart (tmode
, inner_op0
);
10840 op1
= gen_lowpart (tmode
, inner_op1
);
10841 code
= unsigned_condition (code
);
10850 /* If both operands are NOT, we can strip off the outer operation
10851 and adjust the comparison code for swapped operands; similarly for
10852 NEG, except that this must be an equality comparison. */
10853 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10854 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10855 && (code
== EQ
|| code
== NE
)))
10856 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10862 /* If the first operand is a constant, swap the operands and adjust the
10863 comparison code appropriately, but don't do this if the second operand
10864 is already a constant integer. */
10865 if (swap_commutative_operands_p (op0
, op1
))
10867 tem
= op0
, op0
= op1
, op1
= tem
;
10868 code
= swap_condition (code
);
10871 /* We now enter a loop during which we will try to simplify the comparison.
10872 For the most part, we only are concerned with comparisons with zero,
10873 but some things may really be comparisons with zero but not start
10874 out looking that way. */
10876 while (CONST_INT_P (op1
))
10878 enum machine_mode mode
= GET_MODE (op0
);
10879 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10880 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10881 int equality_comparison_p
;
10882 int sign_bit_comparison_p
;
10883 int unsigned_comparison_p
;
10884 HOST_WIDE_INT const_op
;
10886 /* We only want to handle integral modes. This catches VOIDmode,
10887 CCmode, and the floating-point modes. An exception is that we
10888 can handle VOIDmode if OP0 is a COMPARE or a comparison
10891 if (GET_MODE_CLASS (mode
) != MODE_INT
10892 && ! (mode
== VOIDmode
10893 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10896 /* Get the constant we are comparing against and turn off all bits
10897 not on in our mode. */
10898 const_op
= INTVAL (op1
);
10899 if (mode
!= VOIDmode
)
10900 const_op
= trunc_int_for_mode (const_op
, mode
);
10901 op1
= GEN_INT (const_op
);
10903 /* If we are comparing against a constant power of two and the value
10904 being compared can only have that single bit nonzero (e.g., it was
10905 `and'ed with that bit), we can replace this with a comparison
10908 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10909 || code
== LT
|| code
== LTU
)
10910 && mode_width
<= HOST_BITS_PER_WIDE_INT
10911 && exact_log2 (const_op
) >= 0
10912 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10914 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10915 op1
= const0_rtx
, const_op
= 0;
10918 /* Similarly, if we are comparing a value known to be either -1 or
10919 0 with -1, change it to the opposite comparison against zero. */
10922 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10923 || code
== GEU
|| code
== LTU
)
10924 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10926 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10927 op1
= const0_rtx
, const_op
= 0;
10930 /* Do some canonicalizations based on the comparison code. We prefer
10931 comparisons against zero and then prefer equality comparisons.
10932 If we can reduce the size of a constant, we will do that too. */
10937 /* < C is equivalent to <= (C - 1) */
10941 op1
= GEN_INT (const_op
);
10943 /* ... fall through to LE case below. */
10949 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10953 op1
= GEN_INT (const_op
);
10957 /* If we are doing a <= 0 comparison on a value known to have
10958 a zero sign bit, we can replace this with == 0. */
10959 else if (const_op
== 0
10960 && mode_width
<= HOST_BITS_PER_WIDE_INT
10961 && (nonzero_bits (op0
, mode
)
10962 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10967 /* >= C is equivalent to > (C - 1). */
10971 op1
= GEN_INT (const_op
);
10973 /* ... fall through to GT below. */
10979 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10983 op1
= GEN_INT (const_op
);
10987 /* If we are doing a > 0 comparison on a value known to have
10988 a zero sign bit, we can replace this with != 0. */
10989 else if (const_op
== 0
10990 && mode_width
<= HOST_BITS_PER_WIDE_INT
10991 && (nonzero_bits (op0
, mode
)
10992 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10997 /* < C is equivalent to <= (C - 1). */
11001 op1
= GEN_INT (const_op
);
11003 /* ... fall through ... */
11006 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11007 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
11008 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11010 const_op
= 0, op1
= const0_rtx
;
11018 /* unsigned <= 0 is equivalent to == 0 */
11022 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11023 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
11024 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
11026 const_op
= 0, op1
= const0_rtx
;
11032 /* >= C is equivalent to > (C - 1). */
11036 op1
= GEN_INT (const_op
);
11038 /* ... fall through ... */
11041 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11042 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
11043 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11045 const_op
= 0, op1
= const0_rtx
;
11053 /* unsigned > 0 is equivalent to != 0 */
11057 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11058 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
11059 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
11061 const_op
= 0, op1
= const0_rtx
;
11070 /* Compute some predicates to simplify code below. */
11072 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11073 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11074 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11077 /* If this is a sign bit comparison and we can do arithmetic in
11078 MODE, say that we will only be needing the sign bit of OP0. */
11079 if (sign_bit_comparison_p
11080 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11081 op0
= force_to_mode (op0
, mode
,
11083 << (GET_MODE_BITSIZE (mode
) - 1)),
11086 /* Now try cases based on the opcode of OP0. If none of the cases
11087 does a "continue", we exit this loop immediately after the
11090 switch (GET_CODE (op0
))
11093 /* If we are extracting a single bit from a variable position in
11094 a constant that has only a single bit set and are comparing it
11095 with zero, we can convert this into an equality comparison
11096 between the position and the location of the single bit. */
11097 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11098 have already reduced the shift count modulo the word size. */
11099 if (!SHIFT_COUNT_TRUNCATED
11100 && CONST_INT_P (XEXP (op0
, 0))
11101 && XEXP (op0
, 1) == const1_rtx
11102 && equality_comparison_p
&& const_op
== 0
11103 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
11105 if (BITS_BIG_ENDIAN
)
11107 enum machine_mode new_mode
11108 = mode_for_extraction (EP_extzv
, 1);
11109 if (new_mode
== MAX_MACHINE_MODE
)
11110 i
= BITS_PER_WORD
- 1 - i
;
11114 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
11118 op0
= XEXP (op0
, 2);
11122 /* Result is nonzero iff shift count is equal to I. */
11123 code
= reverse_condition (code
);
11127 /* ... fall through ... */
11130 tem
= expand_compound_operation (op0
);
11139 /* If testing for equality, we can take the NOT of the constant. */
11140 if (equality_comparison_p
11141 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11143 op0
= XEXP (op0
, 0);
11148 /* If just looking at the sign bit, reverse the sense of the
11150 if (sign_bit_comparison_p
)
11152 op0
= XEXP (op0
, 0);
11153 code
= (code
== GE
? LT
: GE
);
11159 /* If testing for equality, we can take the NEG of the constant. */
11160 if (equality_comparison_p
11161 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11163 op0
= XEXP (op0
, 0);
11168 /* The remaining cases only apply to comparisons with zero. */
11172 /* When X is ABS or is known positive,
11173 (neg X) is < 0 if and only if X != 0. */
11175 if (sign_bit_comparison_p
11176 && (GET_CODE (XEXP (op0
, 0)) == ABS
11177 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11178 && (nonzero_bits (XEXP (op0
, 0), mode
)
11179 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
11181 op0
= XEXP (op0
, 0);
11182 code
= (code
== LT
? NE
: EQ
);
11186 /* If we have NEG of something whose two high-order bits are the
11187 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11188 if (num_sign_bit_copies (op0
, mode
) >= 2)
11190 op0
= XEXP (op0
, 0);
11191 code
= swap_condition (code
);
11197 /* If we are testing equality and our count is a constant, we
11198 can perform the inverse operation on our RHS. */
11199 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11200 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11201 op1
, XEXP (op0
, 1))) != 0)
11203 op0
= XEXP (op0
, 0);
11208 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11209 a particular bit. Convert it to an AND of a constant of that
11210 bit. This will be converted into a ZERO_EXTRACT. */
11211 if (const_op
== 0 && sign_bit_comparison_p
11212 && CONST_INT_P (XEXP (op0
, 1))
11213 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11215 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11218 - INTVAL (XEXP (op0
, 1)))));
11219 code
= (code
== LT
? NE
: EQ
);
11223 /* Fall through. */
11226 /* ABS is ignorable inside an equality comparison with zero. */
11227 if (const_op
== 0 && equality_comparison_p
)
11229 op0
= XEXP (op0
, 0);
11235 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11236 (compare FOO CONST) if CONST fits in FOO's mode and we
11237 are either testing inequality or have an unsigned
11238 comparison with ZERO_EXTEND or a signed comparison with
11239 SIGN_EXTEND. But don't do it if we don't have a compare
11240 insn of the given mode, since we'd have to revert it
11241 later on, and then we wouldn't know whether to sign- or
11243 mode
= GET_MODE (XEXP (op0
, 0));
11244 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11245 && ! unsigned_comparison_p
11246 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11247 && ((unsigned HOST_WIDE_INT
) const_op
11248 < (((unsigned HOST_WIDE_INT
) 1
11249 << (GET_MODE_BITSIZE (mode
) - 1))))
11250 && have_insn_for (COMPARE
, mode
))
11252 op0
= XEXP (op0
, 0);
11258 /* Check for the case where we are comparing A - C1 with C2, that is
11260 (subreg:MODE (plus (A) (-C1))) op (C2)
11262 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11263 comparison in the wider mode. One of the following two conditions
11264 must be true in order for this to be valid:
11266 1. The mode extension results in the same bit pattern being added
11267 on both sides and the comparison is equality or unsigned. As
11268 C2 has been truncated to fit in MODE, the pattern can only be
11271 2. The mode extension results in the sign bit being copied on
11274 The difficulty here is that we have predicates for A but not for
11275 (A - C1) so we need to check that C1 is within proper bounds so
11276 as to perturbate A as little as possible. */
11278 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11279 && subreg_lowpart_p (op0
)
11280 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
11281 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11282 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11284 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11285 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11286 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11289 && (unsigned HOST_WIDE_INT
) c1
11290 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11291 && (equality_comparison_p
|| unsigned_comparison_p
)
11292 /* (A - C1) zero-extends if it is positive and sign-extends
11293 if it is negative, C2 both zero- and sign-extends. */
11294 && ((0 == (nonzero_bits (a
, inner_mode
)
11295 & ~GET_MODE_MASK (mode
))
11297 /* (A - C1) sign-extends if it is positive and 1-extends
11298 if it is negative, C2 both sign- and 1-extends. */
11299 || (num_sign_bit_copies (a
, inner_mode
)
11300 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11303 || ((unsigned HOST_WIDE_INT
) c1
11304 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11305 /* (A - C1) always sign-extends, like C2. */
11306 && num_sign_bit_copies (a
, inner_mode
)
11307 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11308 - (mode_width
- 1))))
11310 op0
= SUBREG_REG (op0
);
11315 /* If the inner mode is narrower and we are extracting the low part,
11316 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11317 if (subreg_lowpart_p (op0
)
11318 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11319 /* Fall through */ ;
11323 /* ... fall through ... */
11326 mode
= GET_MODE (XEXP (op0
, 0));
11327 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11328 && (unsigned_comparison_p
|| equality_comparison_p
)
11329 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11330 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
11331 && have_insn_for (COMPARE
, mode
))
11333 op0
= XEXP (op0
, 0);
11339 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11340 this for equality comparisons due to pathological cases involving
11342 if (equality_comparison_p
11343 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11344 op1
, XEXP (op0
, 1))))
11346 op0
= XEXP (op0
, 0);
11351 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11352 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11353 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11355 op0
= XEXP (XEXP (op0
, 0), 0);
11356 code
= (code
== LT
? EQ
: NE
);
11362 /* We used to optimize signed comparisons against zero, but that
11363 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11364 arrive here as equality comparisons, or (GEU, LTU) are
11365 optimized away. No need to special-case them. */
11367 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11368 (eq B (minus A C)), whichever simplifies. We can only do
11369 this for equality comparisons due to pathological cases involving
11371 if (equality_comparison_p
11372 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11373 XEXP (op0
, 1), op1
)))
11375 op0
= XEXP (op0
, 0);
11380 if (equality_comparison_p
11381 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11382 XEXP (op0
, 0), op1
)))
11384 op0
= XEXP (op0
, 1);
11389 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11390 of bits in X minus 1, is one iff X > 0. */
11391 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11392 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11393 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
11395 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11397 op0
= XEXP (op0
, 1);
11398 code
= (code
== GE
? LE
: GT
);
11404 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11405 if C is zero or B is a constant. */
11406 if (equality_comparison_p
11407 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11408 XEXP (op0
, 1), op1
)))
11410 op0
= XEXP (op0
, 0);
11417 case UNEQ
: case LTGT
:
11418 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11419 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11420 case UNORDERED
: case ORDERED
:
11421 /* We can't do anything if OP0 is a condition code value, rather
11422 than an actual data value. */
11424 || CC0_P (XEXP (op0
, 0))
11425 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11428 /* Get the two operands being compared. */
11429 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11430 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11432 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11434 /* Check for the cases where we simply want the result of the
11435 earlier test or the opposite of that result. */
11436 if (code
== NE
|| code
== EQ
11437 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
11438 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11439 && (STORE_FLAG_VALUE
11440 & (((HOST_WIDE_INT
) 1
11441 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
11442 && (code
== LT
|| code
== GE
)))
11444 enum rtx_code new_code
;
11445 if (code
== LT
|| code
== NE
)
11446 new_code
= GET_CODE (op0
);
11448 new_code
= reversed_comparison_code (op0
, NULL
);
11450 if (new_code
!= UNKNOWN
)
11461 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11463 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11464 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11465 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11467 op0
= XEXP (op0
, 1);
11468 code
= (code
== GE
? GT
: LE
);
11474 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11475 will be converted to a ZERO_EXTRACT later. */
11476 if (const_op
== 0 && equality_comparison_p
11477 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11478 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11480 op0
= simplify_and_const_int
11481 (NULL_RTX
, mode
, gen_rtx_LSHIFTRT (mode
,
11483 XEXP (XEXP (op0
, 0), 1)),
11484 (HOST_WIDE_INT
) 1);
11488 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11489 zero and X is a comparison and C1 and C2 describe only bits set
11490 in STORE_FLAG_VALUE, we can compare with X. */
11491 if (const_op
== 0 && equality_comparison_p
11492 && mode_width
<= HOST_BITS_PER_WIDE_INT
11493 && CONST_INT_P (XEXP (op0
, 1))
11494 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11495 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11496 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11497 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11499 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11500 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11501 if ((~STORE_FLAG_VALUE
& mask
) == 0
11502 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11503 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11504 && COMPARISON_P (tem
))))
11506 op0
= XEXP (XEXP (op0
, 0), 0);
11511 /* If we are doing an equality comparison of an AND of a bit equal
11512 to the sign bit, replace this with a LT or GE comparison of
11513 the underlying value. */
11514 if (equality_comparison_p
11516 && CONST_INT_P (XEXP (op0
, 1))
11517 && mode_width
<= HOST_BITS_PER_WIDE_INT
11518 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11519 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11521 op0
= XEXP (op0
, 0);
11522 code
= (code
== EQ
? GE
: LT
);
11526 /* If this AND operation is really a ZERO_EXTEND from a narrower
11527 mode, the constant fits within that mode, and this is either an
11528 equality or unsigned comparison, try to do this comparison in
11533 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11534 -> (ne:DI (reg:SI 4) (const_int 0))
11536 unless TRULY_NOOP_TRUNCATION allows it or the register is
11537 known to hold a value of the required mode the
11538 transformation is invalid. */
11539 if ((equality_comparison_p
|| unsigned_comparison_p
)
11540 && CONST_INT_P (XEXP (op0
, 1))
11541 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
11542 & GET_MODE_MASK (mode
))
11544 && const_op
>> i
== 0
11545 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11546 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
11547 GET_MODE_BITSIZE (GET_MODE (op0
)))
11548 || (REG_P (XEXP (op0
, 0))
11549 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11551 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11555 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11556 fits in both M1 and M2 and the SUBREG is either paradoxical
11557 or represents the low part, permute the SUBREG and the AND
11559 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11561 unsigned HOST_WIDE_INT c1
;
11562 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11563 /* Require an integral mode, to avoid creating something like
11565 if (SCALAR_INT_MODE_P (tmode
)
11566 /* It is unsafe to commute the AND into the SUBREG if the
11567 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11568 not defined. As originally written the upper bits
11569 have a defined value due to the AND operation.
11570 However, if we commute the AND inside the SUBREG then
11571 they no longer have defined values and the meaning of
11572 the code has been changed. */
11574 #ifdef WORD_REGISTER_OPERATIONS
11575 || (mode_width
> GET_MODE_BITSIZE (tmode
)
11576 && mode_width
<= BITS_PER_WORD
)
11578 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
11579 && subreg_lowpart_p (XEXP (op0
, 0))))
11580 && CONST_INT_P (XEXP (op0
, 1))
11581 && mode_width
<= HOST_BITS_PER_WIDE_INT
11582 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
11583 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11584 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11586 && c1
!= GET_MODE_MASK (tmode
))
11588 op0
= simplify_gen_binary (AND
, tmode
,
11589 SUBREG_REG (XEXP (op0
, 0)),
11590 gen_int_mode (c1
, tmode
));
11591 op0
= gen_lowpart (mode
, op0
);
11596 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11597 if (const_op
== 0 && equality_comparison_p
11598 && XEXP (op0
, 1) == const1_rtx
11599 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11601 op0
= simplify_and_const_int
11602 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
11603 code
= (code
== NE
? EQ
: NE
);
11607 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11608 (eq (and (lshiftrt X) 1) 0).
11609 Also handle the case where (not X) is expressed using xor. */
11610 if (const_op
== 0 && equality_comparison_p
11611 && XEXP (op0
, 1) == const1_rtx
11612 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11614 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11615 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11617 if (GET_CODE (shift_op
) == NOT
11618 || (GET_CODE (shift_op
) == XOR
11619 && CONST_INT_P (XEXP (shift_op
, 1))
11620 && CONST_INT_P (shift_count
)
11621 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11622 && (INTVAL (XEXP (shift_op
, 1))
11623 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11625 op0
= simplify_and_const_int
11627 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11628 (HOST_WIDE_INT
) 1);
11629 code
= (code
== NE
? EQ
: NE
);
11636 /* If we have (compare (ashift FOO N) (const_int C)) and
11637 the high order N bits of FOO (N+1 if an inequality comparison)
11638 are known to be zero, we can do this by comparing FOO with C
11639 shifted right N bits so long as the low-order N bits of C are
11641 if (CONST_INT_P (XEXP (op0
, 1))
11642 && INTVAL (XEXP (op0
, 1)) >= 0
11643 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11644 < HOST_BITS_PER_WIDE_INT
)
11646 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11647 && mode_width
<= HOST_BITS_PER_WIDE_INT
11648 && (nonzero_bits (XEXP (op0
, 0), mode
)
11649 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11650 + ! equality_comparison_p
))) == 0)
11652 /* We must perform a logical shift, not an arithmetic one,
11653 as we want the top N bits of C to be zero. */
11654 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11656 temp
>>= INTVAL (XEXP (op0
, 1));
11657 op1
= gen_int_mode (temp
, mode
);
11658 op0
= XEXP (op0
, 0);
11662 /* If we are doing a sign bit comparison, it means we are testing
11663 a particular bit. Convert it to the appropriate AND. */
11664 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11665 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11667 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11670 - INTVAL (XEXP (op0
, 1)))));
11671 code
= (code
== LT
? NE
: EQ
);
11675 /* If this an equality comparison with zero and we are shifting
11676 the low bit to the sign bit, we can convert this to an AND of the
11678 if (const_op
== 0 && equality_comparison_p
11679 && CONST_INT_P (XEXP (op0
, 1))
11680 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11683 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11684 (HOST_WIDE_INT
) 1);
11690 /* If this is an equality comparison with zero, we can do this
11691 as a logical shift, which might be much simpler. */
11692 if (equality_comparison_p
&& const_op
== 0
11693 && CONST_INT_P (XEXP (op0
, 1)))
11695 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11697 INTVAL (XEXP (op0
, 1)));
11701 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11702 do the comparison in a narrower mode. */
11703 if (! unsigned_comparison_p
11704 && CONST_INT_P (XEXP (op0
, 1))
11705 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11706 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11707 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11708 MODE_INT
, 1)) != BLKmode
11709 && (((unsigned HOST_WIDE_INT
) const_op
11710 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11711 <= GET_MODE_MASK (tmode
)))
11713 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11717 /* Likewise if OP0 is a PLUS of a sign extension with a
11718 constant, which is usually represented with the PLUS
11719 between the shifts. */
11720 if (! unsigned_comparison_p
11721 && CONST_INT_P (XEXP (op0
, 1))
11722 && GET_CODE (XEXP (op0
, 0)) == PLUS
11723 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11724 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11725 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11726 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11727 MODE_INT
, 1)) != BLKmode
11728 && (((unsigned HOST_WIDE_INT
) const_op
11729 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11730 <= GET_MODE_MASK (tmode
)))
11732 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11733 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11734 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11735 add_const
, XEXP (op0
, 1));
11737 op0
= simplify_gen_binary (PLUS
, tmode
,
11738 gen_lowpart (tmode
, inner
),
11743 /* ... fall through ... */
11745 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11746 the low order N bits of FOO are known to be zero, we can do this
11747 by comparing FOO with C shifted left N bits so long as no
11748 overflow occurs. Even if the low order N bits of FOO aren't known
11749 to be zero, if the comparison is >= or < we can use the same
11750 optimization and for > or <= by setting all the low
11751 order N bits in the comparison constant. */
11752 if (CONST_INT_P (XEXP (op0
, 1))
11753 && INTVAL (XEXP (op0
, 1)) > 0
11754 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11755 && mode_width
<= HOST_BITS_PER_WIDE_INT
11756 && (((unsigned HOST_WIDE_INT
) const_op
11757 + (GET_CODE (op0
) != LSHIFTRT
11758 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11761 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11763 unsigned HOST_WIDE_INT low_bits
11764 = (nonzero_bits (XEXP (op0
, 0), mode
)
11765 & (((unsigned HOST_WIDE_INT
) 1
11766 << INTVAL (XEXP (op0
, 1))) - 1));
11767 if (low_bits
== 0 || !equality_comparison_p
)
11769 /* If the shift was logical, then we must make the condition
11771 if (GET_CODE (op0
) == LSHIFTRT
)
11772 code
= unsigned_condition (code
);
11774 const_op
<<= INTVAL (XEXP (op0
, 1));
11776 && (code
== GT
|| code
== GTU
11777 || code
== LE
|| code
== LEU
))
11779 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11780 op1
= GEN_INT (const_op
);
11781 op0
= XEXP (op0
, 0);
11786 /* If we are using this shift to extract just the sign bit, we
11787 can replace this with an LT or GE comparison. */
11789 && (equality_comparison_p
|| sign_bit_comparison_p
)
11790 && CONST_INT_P (XEXP (op0
, 1))
11791 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11794 op0
= XEXP (op0
, 0);
11795 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11807 /* Now make any compound operations involved in this comparison. Then,
11808 check for an outmost SUBREG on OP0 that is not doing anything or is
11809 paradoxical. The latter transformation must only be performed when
11810 it is known that the "extra" bits will be the same in op0 and op1 or
11811 that they don't matter. There are three cases to consider:
11813 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11814 care bits and we can assume they have any convenient value. So
11815 making the transformation is safe.
11817 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11818 In this case the upper bits of op0 are undefined. We should not make
11819 the simplification in that case as we do not know the contents of
11822 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11823 UNKNOWN. In that case we know those bits are zeros or ones. We must
11824 also be sure that they are the same as the upper bits of op1.
11826 We can never remove a SUBREG for a non-equality comparison because
11827 the sign bit is in a different place in the underlying object. */
11829 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11830 op1
= make_compound_operation (op1
, SET
);
11832 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11833 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11834 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11835 && (code
== NE
|| code
== EQ
))
11837 if (GET_MODE_SIZE (GET_MODE (op0
))
11838 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11840 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11842 if (REG_P (SUBREG_REG (op0
)))
11844 op0
= SUBREG_REG (op0
);
11845 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11848 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11849 <= HOST_BITS_PER_WIDE_INT
)
11850 && (nonzero_bits (SUBREG_REG (op0
),
11851 GET_MODE (SUBREG_REG (op0
)))
11852 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11854 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11856 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11857 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11858 op0
= SUBREG_REG (op0
), op1
= tem
;
11862 /* We now do the opposite procedure: Some machines don't have compare
11863 insns in all modes. If OP0's mode is an integer mode smaller than a
11864 word and we can't do a compare in that mode, see if there is a larger
11865 mode for which we can do the compare. There are a number of cases in
11866 which we can use the wider mode. */
11868 mode
= GET_MODE (op0
);
11869 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11870 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11871 && ! have_insn_for (COMPARE
, mode
))
11872 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11874 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11875 tmode
= GET_MODE_WIDER_MODE (tmode
))
11876 if (have_insn_for (COMPARE
, tmode
))
11880 /* If this is a test for negative, we can make an explicit
11881 test of the sign bit. Test this first so we can use
11882 a paradoxical subreg to extend OP0. */
11884 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11885 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11887 op0
= simplify_gen_binary (AND
, tmode
,
11888 gen_lowpart (tmode
, op0
),
11889 GEN_INT ((HOST_WIDE_INT
) 1
11890 << (GET_MODE_BITSIZE (mode
)
11892 code
= (code
== LT
) ? NE
: EQ
;
11896 /* If the only nonzero bits in OP0 and OP1 are those in the
11897 narrower mode and this is an equality or unsigned comparison,
11898 we can use the wider mode. Similarly for sign-extended
11899 values, in which case it is true for all comparisons. */
11900 zero_extended
= ((code
== EQ
|| code
== NE
11901 || code
== GEU
|| code
== GTU
11902 || code
== LEU
|| code
== LTU
)
11903 && (nonzero_bits (op0
, tmode
)
11904 & ~GET_MODE_MASK (mode
)) == 0
11905 && ((CONST_INT_P (op1
)
11906 || (nonzero_bits (op1
, tmode
)
11907 & ~GET_MODE_MASK (mode
)) == 0)));
11910 || ((num_sign_bit_copies (op0
, tmode
)
11911 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11912 - GET_MODE_BITSIZE (mode
)))
11913 && (num_sign_bit_copies (op1
, tmode
)
11914 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11915 - GET_MODE_BITSIZE (mode
)))))
11917 /* If OP0 is an AND and we don't have an AND in MODE either,
11918 make a new AND in the proper mode. */
11919 if (GET_CODE (op0
) == AND
11920 && !have_insn_for (AND
, mode
))
11921 op0
= simplify_gen_binary (AND
, tmode
,
11922 gen_lowpart (tmode
,
11924 gen_lowpart (tmode
,
11930 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
11931 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
11935 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
11936 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
11943 #ifdef CANONICALIZE_COMPARISON
11944 /* If this machine only supports a subset of valid comparisons, see if we
11945 can convert an unsupported one into a supported one. */
11946 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11955 /* Utility function for record_value_for_reg. Count number of
11960 enum rtx_code code
= GET_CODE (x
);
11964 if (GET_RTX_CLASS (code
) == '2'
11965 || GET_RTX_CLASS (code
) == 'c')
11967 rtx x0
= XEXP (x
, 0);
11968 rtx x1
= XEXP (x
, 1);
11971 return 1 + 2 * count_rtxs (x0
);
11973 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11974 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11975 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11976 return 2 + 2 * count_rtxs (x0
)
11977 + count_rtxs (x
== XEXP (x1
, 0)
11978 ? XEXP (x1
, 1) : XEXP (x1
, 0));
11980 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11981 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11982 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11983 return 2 + 2 * count_rtxs (x1
)
11984 + count_rtxs (x
== XEXP (x0
, 0)
11985 ? XEXP (x0
, 1) : XEXP (x0
, 0));
11988 fmt
= GET_RTX_FORMAT (code
);
11989 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11991 ret
+= count_rtxs (XEXP (x
, i
));
11992 else if (fmt
[i
] == 'E')
11993 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11994 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
11999 /* Utility function for following routine. Called when X is part of a value
12000 being stored into last_set_value. Sets last_set_table_tick
12001 for each register mentioned. Similar to mention_regs in cse.c */
12004 update_table_tick (rtx x
)
12006 enum rtx_code code
= GET_CODE (x
);
12007 const char *fmt
= GET_RTX_FORMAT (code
);
12012 unsigned int regno
= REGNO (x
);
12013 unsigned int endregno
= END_REGNO (x
);
12016 for (r
= regno
; r
< endregno
; r
++)
12018 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
12019 rsp
->last_set_table_tick
= label_tick
;
12025 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12028 /* Check for identical subexpressions. If x contains
12029 identical subexpression we only have to traverse one of
12031 if (i
== 0 && ARITHMETIC_P (x
))
12033 /* Note that at this point x1 has already been
12035 rtx x0
= XEXP (x
, 0);
12036 rtx x1
= XEXP (x
, 1);
12038 /* If x0 and x1 are identical then there is no need to
12043 /* If x0 is identical to a subexpression of x1 then while
12044 processing x1, x0 has already been processed. Thus we
12045 are done with x. */
12046 if (ARITHMETIC_P (x1
)
12047 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12050 /* If x1 is identical to a subexpression of x0 then we
12051 still have to process the rest of x0. */
12052 if (ARITHMETIC_P (x0
)
12053 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12055 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12060 update_table_tick (XEXP (x
, i
));
12062 else if (fmt
[i
] == 'E')
12063 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12064 update_table_tick (XVECEXP (x
, i
, j
));
12067 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12068 are saying that the register is clobbered and we no longer know its
12069 value. If INSN is zero, don't update reg_stat[].last_set; this is
12070 only permitted with VALUE also zero and is used to invalidate the
12074 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12076 unsigned int regno
= REGNO (reg
);
12077 unsigned int endregno
= END_REGNO (reg
);
12079 reg_stat_type
*rsp
;
12081 /* If VALUE contains REG and we have a previous value for REG, substitute
12082 the previous value. */
12083 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12087 /* Set things up so get_last_value is allowed to see anything set up to
12089 subst_low_luid
= DF_INSN_LUID (insn
);
12090 tem
= get_last_value (reg
);
12092 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12093 it isn't going to be useful and will take a lot of time to process,
12094 so just use the CLOBBER. */
12098 if (ARITHMETIC_P (tem
)
12099 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12100 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12101 tem
= XEXP (tem
, 0);
12102 else if (count_occurrences (value
, reg
, 1) >= 2)
12104 /* If there are two or more occurrences of REG in VALUE,
12105 prevent the value from growing too much. */
12106 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12107 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12110 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12114 /* For each register modified, show we don't know its value, that
12115 we don't know about its bitwise content, that its value has been
12116 updated, and that we don't know the location of the death of the
12118 for (i
= regno
; i
< endregno
; i
++)
12120 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12123 rsp
->last_set
= insn
;
12125 rsp
->last_set_value
= 0;
12126 rsp
->last_set_mode
= VOIDmode
;
12127 rsp
->last_set_nonzero_bits
= 0;
12128 rsp
->last_set_sign_bit_copies
= 0;
12129 rsp
->last_death
= 0;
12130 rsp
->truncated_to_mode
= VOIDmode
;
12133 /* Mark registers that are being referenced in this value. */
12135 update_table_tick (value
);
12137 /* Now update the status of each register being set.
12138 If someone is using this register in this block, set this register
12139 to invalid since we will get confused between the two lives in this
12140 basic block. This makes using this register always invalid. In cse, we
12141 scan the table to invalidate all entries using this register, but this
12142 is too much work for us. */
12144 for (i
= regno
; i
< endregno
; i
++)
12146 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12147 rsp
->last_set_label
= label_tick
;
12149 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12150 rsp
->last_set_invalid
= 1;
12152 rsp
->last_set_invalid
= 0;
12155 /* The value being assigned might refer to X (like in "x++;"). In that
12156 case, we must replace it with (clobber (const_int 0)) to prevent
12158 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12159 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12161 value
= copy_rtx (value
);
12162 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12166 /* For the main register being modified, update the value, the mode, the
12167 nonzero bits, and the number of sign bit copies. */
12169 rsp
->last_set_value
= value
;
12173 enum machine_mode mode
= GET_MODE (reg
);
12174 subst_low_luid
= DF_INSN_LUID (insn
);
12175 rsp
->last_set_mode
= mode
;
12176 if (GET_MODE_CLASS (mode
) == MODE_INT
12177 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
12178 mode
= nonzero_bits_mode
;
12179 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12180 rsp
->last_set_sign_bit_copies
12181 = num_sign_bit_copies (value
, GET_MODE (reg
));
12185 /* Called via note_stores from record_dead_and_set_regs to handle one
12186 SET or CLOBBER in an insn. DATA is the instruction in which the
12187 set is occurring. */
12190 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12192 rtx record_dead_insn
= (rtx
) data
;
12194 if (GET_CODE (dest
) == SUBREG
)
12195 dest
= SUBREG_REG (dest
);
12197 if (!record_dead_insn
)
12200 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12206 /* If we are setting the whole register, we know its value. Otherwise
12207 show that we don't know the value. We can handle SUBREG in
12209 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12210 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12211 else if (GET_CODE (setter
) == SET
12212 && GET_CODE (SET_DEST (setter
)) == SUBREG
12213 && SUBREG_REG (SET_DEST (setter
)) == dest
12214 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
12215 && subreg_lowpart_p (SET_DEST (setter
)))
12216 record_value_for_reg (dest
, record_dead_insn
,
12217 gen_lowpart (GET_MODE (dest
),
12218 SET_SRC (setter
)));
12220 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12222 else if (MEM_P (dest
)
12223 /* Ignore pushes, they clobber nothing. */
12224 && ! push_operand (dest
, GET_MODE (dest
)))
12225 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12228 /* Update the records of when each REG was most recently set or killed
12229 for the things done by INSN. This is the last thing done in processing
12230 INSN in the combiner loop.
12232 We update reg_stat[], in particular fields last_set, last_set_value,
12233 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12234 last_death, and also the similar information mem_last_set (which insn
12235 most recently modified memory) and last_call_luid (which insn was the
12236 most recent subroutine call). */
12239 record_dead_and_set_regs (rtx insn
)
12244 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12246 if (REG_NOTE_KIND (link
) == REG_DEAD
12247 && REG_P (XEXP (link
, 0)))
12249 unsigned int regno
= REGNO (XEXP (link
, 0));
12250 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12252 for (i
= regno
; i
< endregno
; i
++)
12254 reg_stat_type
*rsp
;
12256 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12257 rsp
->last_death
= insn
;
12260 else if (REG_NOTE_KIND (link
) == REG_INC
)
12261 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12266 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12267 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
12269 reg_stat_type
*rsp
;
12271 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12272 rsp
->last_set_invalid
= 1;
12273 rsp
->last_set
= insn
;
12274 rsp
->last_set_value
= 0;
12275 rsp
->last_set_mode
= VOIDmode
;
12276 rsp
->last_set_nonzero_bits
= 0;
12277 rsp
->last_set_sign_bit_copies
= 0;
12278 rsp
->last_death
= 0;
12279 rsp
->truncated_to_mode
= VOIDmode
;
12282 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12284 /* We can't combine into a call pattern. Remember, though, that
12285 the return value register is set at this LUID. We could
12286 still replace a register with the return value from the
12287 wrong subroutine call! */
12288 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12291 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12294 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12295 register present in the SUBREG, so for each such SUBREG go back and
12296 adjust nonzero and sign bit information of the registers that are
12297 known to have some zero/sign bits set.
12299 This is needed because when combine blows the SUBREGs away, the
12300 information on zero/sign bits is lost and further combines can be
12301 missed because of that. */
12304 record_promoted_value (rtx insn
, rtx subreg
)
12307 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12308 enum machine_mode mode
= GET_MODE (subreg
);
12310 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
12313 for (links
= LOG_LINKS (insn
); links
;)
12315 reg_stat_type
*rsp
;
12317 insn
= XEXP (links
, 0);
12318 set
= single_set (insn
);
12320 if (! set
|| !REG_P (SET_DEST (set
))
12321 || REGNO (SET_DEST (set
)) != regno
12322 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12324 links
= XEXP (links
, 1);
12328 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12329 if (rsp
->last_set
== insn
)
12331 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12332 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12335 if (REG_P (SET_SRC (set
)))
12337 regno
= REGNO (SET_SRC (set
));
12338 links
= LOG_LINKS (insn
);
12345 /* Check if X, a register, is known to contain a value already
12346 truncated to MODE. In this case we can use a subreg to refer to
12347 the truncated value even though in the generic case we would need
12348 an explicit truncation. */
12351 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12353 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12354 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12357 || rsp
->truncation_label
< label_tick_ebb_start
)
12359 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12361 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
12362 GET_MODE_BITSIZE (truncated
)))
12367 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12368 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12369 might be able to turn a truncate into a subreg using this information.
12370 Return -1 if traversing *P is complete or 0 otherwise. */
12373 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12376 enum machine_mode truncated_mode
;
12377 reg_stat_type
*rsp
;
12379 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12381 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12382 truncated_mode
= GET_MODE (x
);
12384 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12387 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
12388 GET_MODE_BITSIZE (original_mode
)))
12391 x
= SUBREG_REG (x
);
12393 /* ??? For hard-regs we now record everything. We might be able to
12394 optimize this using last_set_mode. */
12395 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12396 truncated_mode
= GET_MODE (x
);
12400 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12401 if (rsp
->truncated_to_mode
== 0
12402 || rsp
->truncation_label
< label_tick_ebb_start
12403 || (GET_MODE_SIZE (truncated_mode
)
12404 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12406 rsp
->truncated_to_mode
= truncated_mode
;
12407 rsp
->truncation_label
= label_tick
;
12413 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12414 the modes they are used in. This can help truning TRUNCATEs into
12418 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12420 for_each_rtx (x
, record_truncated_value
, NULL
);
12423 /* Scan X for promoted SUBREGs. For each one found,
12424 note what it implies to the registers used in it. */
12427 check_promoted_subreg (rtx insn
, rtx x
)
12429 if (GET_CODE (x
) == SUBREG
12430 && SUBREG_PROMOTED_VAR_P (x
)
12431 && REG_P (SUBREG_REG (x
)))
12432 record_promoted_value (insn
, x
);
12435 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12438 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12442 check_promoted_subreg (insn
, XEXP (x
, i
));
12446 if (XVEC (x
, i
) != 0)
12447 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12448 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12454 /* Verify that all the registers and memory references mentioned in *LOC are
12455 still valid. *LOC was part of a value set in INSN when label_tick was
12456 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12457 the invalid references with (clobber (const_int 0)) and return 1. This
12458 replacement is useful because we often can get useful information about
12459 the form of a value (e.g., if it was produced by a shift that always
12460 produces -1 or 0) even though we don't know exactly what registers it
12461 was produced from. */
12464 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12467 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12468 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12473 unsigned int regno
= REGNO (x
);
12474 unsigned int endregno
= END_REGNO (x
);
12477 for (j
= regno
; j
< endregno
; j
++)
12479 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
12480 if (rsp
->last_set_invalid
12481 /* If this is a pseudo-register that was only set once and not
12482 live at the beginning of the function, it is always valid. */
12483 || (! (regno
>= FIRST_PSEUDO_REGISTER
12484 && REG_N_SETS (regno
) == 1
12485 && (!REGNO_REG_SET_P
12486 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12487 && rsp
->last_set_label
> tick
))
12490 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12497 /* If this is a memory reference, make sure that there were no stores after
12498 it that might have clobbered the value. We don't have alias info, so we
12499 assume any store invalidates it. Moreover, we only have local UIDs, so
12500 we also assume that there were stores in the intervening basic blocks. */
12501 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12502 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12505 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12509 for (i
= 0; i
< len
; i
++)
12513 /* Check for identical subexpressions. If x contains
12514 identical subexpression we only have to traverse one of
12516 if (i
== 1 && ARITHMETIC_P (x
))
12518 /* Note that at this point x0 has already been checked
12519 and found valid. */
12520 rtx x0
= XEXP (x
, 0);
12521 rtx x1
= XEXP (x
, 1);
12523 /* If x0 and x1 are identical then x is also valid. */
12527 /* If x1 is identical to a subexpression of x0 then
12528 while checking x0, x1 has already been checked. Thus
12529 it is valid and so as x. */
12530 if (ARITHMETIC_P (x0
)
12531 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12534 /* If x0 is identical to a subexpression of x1 then x is
12535 valid iff the rest of x1 is valid. */
12536 if (ARITHMETIC_P (x1
)
12537 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12539 get_last_value_validate (&XEXP (x1
,
12540 x0
== XEXP (x1
, 0) ? 1 : 0),
12541 insn
, tick
, replace
);
12544 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12548 else if (fmt
[i
] == 'E')
12549 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12550 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12551 insn
, tick
, replace
) == 0)
12555 /* If we haven't found a reason for it to be invalid, it is valid. */
12559 /* Get the last value assigned to X, if known. Some registers
12560 in the value may be replaced with (clobber (const_int 0)) if their value
12561 is known longer known reliably. */
12564 get_last_value (const_rtx x
)
12566 unsigned int regno
;
12568 reg_stat_type
*rsp
;
12570 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12571 then convert it to the desired mode. If this is a paradoxical SUBREG,
12572 we cannot predict what values the "extra" bits might have. */
12573 if (GET_CODE (x
) == SUBREG
12574 && subreg_lowpart_p (x
)
12575 && (GET_MODE_SIZE (GET_MODE (x
))
12576 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
12577 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12578 return gen_lowpart (GET_MODE (x
), value
);
12584 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12585 value
= rsp
->last_set_value
;
12587 /* If we don't have a value, or if it isn't for this basic block and
12588 it's either a hard register, set more than once, or it's a live
12589 at the beginning of the function, return 0.
12591 Because if it's not live at the beginning of the function then the reg
12592 is always set before being used (is never used without being set).
12593 And, if it's set only once, and it's always set before use, then all
12594 uses must have the same last value, even if it's not from this basic
12598 || (rsp
->last_set_label
< label_tick_ebb_start
12599 && (regno
< FIRST_PSEUDO_REGISTER
12600 || REG_N_SETS (regno
) != 1
12602 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12605 /* If the value was set in a later insn than the ones we are processing,
12606 we can't use it even if the register was only set once. */
12607 if (rsp
->last_set_label
== label_tick
12608 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12611 /* If the value has all its registers valid, return it. */
12612 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12615 /* Otherwise, make a copy and replace any invalid register with
12616 (clobber (const_int 0)). If that fails for some reason, return 0. */
12618 value
= copy_rtx (value
);
12619 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12625 /* Return nonzero if expression X refers to a REG or to memory
12626 that is set in an instruction more recent than FROM_LUID. */
12629 use_crosses_set_p (const_rtx x
, int from_luid
)
12633 enum rtx_code code
= GET_CODE (x
);
12637 unsigned int regno
= REGNO (x
);
12638 unsigned endreg
= END_REGNO (x
);
12640 #ifdef PUSH_ROUNDING
12641 /* Don't allow uses of the stack pointer to be moved,
12642 because we don't know whether the move crosses a push insn. */
12643 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12646 for (; regno
< endreg
; regno
++)
12648 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12650 && rsp
->last_set_label
== label_tick
12651 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12657 if (code
== MEM
&& mem_last_set
> from_luid
)
12660 fmt
= GET_RTX_FORMAT (code
);
12662 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12667 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12668 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12671 else if (fmt
[i
] == 'e'
12672 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12678 /* Define three variables used for communication between the following
12681 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12682 static int reg_dead_flag
;
12684 /* Function called via note_stores from reg_dead_at_p.
12686 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12687 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12690 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12692 unsigned int regno
, endregno
;
12697 regno
= REGNO (dest
);
12698 endregno
= END_REGNO (dest
);
12699 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12700 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12703 /* Return nonzero if REG is known to be dead at INSN.
12705 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12706 referencing REG, it is dead. If we hit a SET referencing REG, it is
12707 live. Otherwise, see if it is live or dead at the start of the basic
12708 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12709 must be assumed to be always live. */
12712 reg_dead_at_p (rtx reg
, rtx insn
)
12717 /* Set variables for reg_dead_at_p_1. */
12718 reg_dead_regno
= REGNO (reg
);
12719 reg_dead_endregno
= END_REGNO (reg
);
12723 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12724 we allow the machine description to decide whether use-and-clobber
12725 patterns are OK. */
12726 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12728 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12729 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12733 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12734 beginning of basic block. */
12735 block
= BLOCK_FOR_INSN (insn
);
12740 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12742 return reg_dead_flag
== 1 ? 1 : 0;
12744 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12748 if (insn
== BB_HEAD (block
))
12751 insn
= PREV_INSN (insn
);
12754 /* Look at live-in sets for the basic block that we were in. */
12755 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12756 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12762 /* Note hard registers in X that are used. */
12765 mark_used_regs_combine (rtx x
)
12767 RTX_CODE code
= GET_CODE (x
);
12768 unsigned int regno
;
12781 case ADDR_DIFF_VEC
:
12784 /* CC0 must die in the insn after it is set, so we don't need to take
12785 special note of it here. */
12791 /* If we are clobbering a MEM, mark any hard registers inside the
12792 address as used. */
12793 if (MEM_P (XEXP (x
, 0)))
12794 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12799 /* A hard reg in a wide mode may really be multiple registers.
12800 If so, mark all of them just like the first. */
12801 if (regno
< FIRST_PSEUDO_REGISTER
)
12803 /* None of this applies to the stack, frame or arg pointers. */
12804 if (regno
== STACK_POINTER_REGNUM
12805 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12806 || regno
== HARD_FRAME_POINTER_REGNUM
12808 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12809 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12811 || regno
== FRAME_POINTER_REGNUM
)
12814 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12820 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12822 rtx testreg
= SET_DEST (x
);
12824 while (GET_CODE (testreg
) == SUBREG
12825 || GET_CODE (testreg
) == ZERO_EXTRACT
12826 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12827 testreg
= XEXP (testreg
, 0);
12829 if (MEM_P (testreg
))
12830 mark_used_regs_combine (XEXP (testreg
, 0));
12832 mark_used_regs_combine (SET_SRC (x
));
12840 /* Recursively scan the operands of this expression. */
12843 const char *fmt
= GET_RTX_FORMAT (code
);
12845 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12848 mark_used_regs_combine (XEXP (x
, i
));
12849 else if (fmt
[i
] == 'E')
12853 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12854 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12860 /* Remove register number REGNO from the dead registers list of INSN.
12862 Return the note used to record the death, if there was one. */
12865 remove_death (unsigned int regno
, rtx insn
)
12867 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12870 remove_note (insn
, note
);
12875 /* For each register (hardware or pseudo) used within expression X, if its
12876 death is in an instruction with luid between FROM_LUID (inclusive) and
12877 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12878 list headed by PNOTES.
12880 That said, don't move registers killed by maybe_kill_insn.
12882 This is done when X is being merged by combination into TO_INSN. These
12883 notes will then be distributed as needed. */
12886 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12891 enum rtx_code code
= GET_CODE (x
);
12895 unsigned int regno
= REGNO (x
);
12896 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
12898 /* Don't move the register if it gets killed in between from and to. */
12899 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12900 && ! reg_referenced_p (x
, maybe_kill_insn
))
12904 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12905 && DF_INSN_LUID (where_dead
) >= from_luid
12906 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12908 rtx note
= remove_death (regno
, where_dead
);
12910 /* It is possible for the call above to return 0. This can occur
12911 when last_death points to I2 or I1 that we combined with.
12912 In that case make a new note.
12914 We must also check for the case where X is a hard register
12915 and NOTE is a death note for a range of hard registers
12916 including X. In that case, we must put REG_DEAD notes for
12917 the remaining registers in place of NOTE. */
12919 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12920 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12921 > GET_MODE_SIZE (GET_MODE (x
))))
12923 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12924 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12925 unsigned int ourend
= END_HARD_REGNO (x
);
12928 for (i
= deadregno
; i
< deadend
; i
++)
12929 if (i
< regno
|| i
>= ourend
)
12930 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12933 /* If we didn't find any note, or if we found a REG_DEAD note that
12934 covers only part of the given reg, and we have a multi-reg hard
12935 register, then to be safe we must check for REG_DEAD notes
12936 for each register other than the first. They could have
12937 their own REG_DEAD notes lying around. */
12938 else if ((note
== 0
12940 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12941 < GET_MODE_SIZE (GET_MODE (x
)))))
12942 && regno
< FIRST_PSEUDO_REGISTER
12943 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12945 unsigned int ourend
= END_HARD_REGNO (x
);
12946 unsigned int i
, offset
;
12950 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12954 for (i
= regno
+ offset
; i
< ourend
; i
++)
12955 move_deaths (regno_reg_rtx
[i
],
12956 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
12959 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12961 XEXP (note
, 1) = *pnotes
;
12965 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
12971 else if (GET_CODE (x
) == SET
)
12973 rtx dest
= SET_DEST (x
);
12975 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12977 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12978 that accesses one word of a multi-word item, some
12979 piece of everything register in the expression is used by
12980 this insn, so remove any old death. */
12981 /* ??? So why do we test for equality of the sizes? */
12983 if (GET_CODE (dest
) == ZERO_EXTRACT
12984 || GET_CODE (dest
) == STRICT_LOW_PART
12985 || (GET_CODE (dest
) == SUBREG
12986 && (((GET_MODE_SIZE (GET_MODE (dest
))
12987 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12988 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12989 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12991 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12995 /* If this is some other SUBREG, we know it replaces the entire
12996 value, so use that as the destination. */
12997 if (GET_CODE (dest
) == SUBREG
)
12998 dest
= SUBREG_REG (dest
);
13000 /* If this is a MEM, adjust deaths of anything used in the address.
13001 For a REG (the only other possibility), the entire value is
13002 being replaced so the old value is not used in this insn. */
13005 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13010 else if (GET_CODE (x
) == CLOBBER
)
13013 len
= GET_RTX_LENGTH (code
);
13014 fmt
= GET_RTX_FORMAT (code
);
13016 for (i
= 0; i
< len
; i
++)
13021 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13022 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13025 else if (fmt
[i
] == 'e')
13026 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13030 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13031 pattern of an insn. X must be a REG. */
13034 reg_bitfield_target_p (rtx x
, rtx body
)
13038 if (GET_CODE (body
) == SET
)
13040 rtx dest
= SET_DEST (body
);
13042 unsigned int regno
, tregno
, endregno
, endtregno
;
13044 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13045 target
= XEXP (dest
, 0);
13046 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13047 target
= SUBREG_REG (XEXP (dest
, 0));
13051 if (GET_CODE (target
) == SUBREG
)
13052 target
= SUBREG_REG (target
);
13054 if (!REG_P (target
))
13057 tregno
= REGNO (target
), regno
= REGNO (x
);
13058 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13059 return target
== x
;
13061 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13062 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13064 return endregno
> tregno
&& regno
< endtregno
;
13067 else if (GET_CODE (body
) == PARALLEL
)
13068 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13069 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13075 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13076 as appropriate. I3 and I2 are the insns resulting from the combination
13077 insns including FROM (I2 may be zero).
13079 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13080 not need REG_DEAD notes because they are being substituted for. This
13081 saves searching in the most common cases.
13083 Each note in the list is either ignored or placed on some insns, depending
13084 on the type of note. */
13087 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13088 rtx elim_i1
, rtx elim_i0
)
13090 rtx note
, next_note
;
13093 for (note
= notes
; note
; note
= next_note
)
13095 rtx place
= 0, place2
= 0;
13097 next_note
= XEXP (note
, 1);
13098 switch (REG_NOTE_KIND (note
))
13102 /* Doesn't matter much where we put this, as long as it's somewhere.
13103 It is preferable to keep these notes on branches, which is most
13104 likely to be i3. */
13108 case REG_VALUE_PROFILE
:
13109 /* Just get rid of this note, as it is unused later anyway. */
13112 case REG_NON_LOCAL_GOTO
:
13117 gcc_assert (i2
&& JUMP_P (i2
));
13122 case REG_EH_REGION
:
13123 /* These notes must remain with the call or trapping instruction. */
13126 else if (i2
&& CALL_P (i2
))
13130 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13131 if (may_trap_p (i3
))
13133 else if (i2
&& may_trap_p (i2
))
13135 /* ??? Otherwise assume we've combined things such that we
13136 can now prove that the instructions can't trap. Drop the
13137 note in this case. */
13143 /* These notes must remain with the call. It should not be
13144 possible for both I2 and I3 to be a call. */
13149 gcc_assert (i2
&& CALL_P (i2
));
13155 /* Any clobbers for i3 may still exist, and so we must process
13156 REG_UNUSED notes from that insn.
13158 Any clobbers from i2 or i1 can only exist if they were added by
13159 recog_for_combine. In that case, recog_for_combine created the
13160 necessary REG_UNUSED notes. Trying to keep any original
13161 REG_UNUSED notes from these insns can cause incorrect output
13162 if it is for the same register as the original i3 dest.
13163 In that case, we will notice that the register is set in i3,
13164 and then add a REG_UNUSED note for the destination of i3, which
13165 is wrong. However, it is possible to have REG_UNUSED notes from
13166 i2 or i1 for register which were both used and clobbered, so
13167 we keep notes from i2 or i1 if they will turn into REG_DEAD
13170 /* If this register is set or clobbered in I3, put the note there
13171 unless there is one already. */
13172 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13174 if (from_insn
!= i3
)
13177 if (! (REG_P (XEXP (note
, 0))
13178 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13179 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13182 /* Otherwise, if this register is used by I3, then this register
13183 now dies here, so we must put a REG_DEAD note here unless there
13185 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13186 && ! (REG_P (XEXP (note
, 0))
13187 ? find_regno_note (i3
, REG_DEAD
,
13188 REGNO (XEXP (note
, 0)))
13189 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13191 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13199 /* These notes say something about results of an insn. We can
13200 only support them if they used to be on I3 in which case they
13201 remain on I3. Otherwise they are ignored.
13203 If the note refers to an expression that is not a constant, we
13204 must also ignore the note since we cannot tell whether the
13205 equivalence is still true. It might be possible to do
13206 slightly better than this (we only have a problem if I2DEST
13207 or I1DEST is present in the expression), but it doesn't
13208 seem worth the trouble. */
13210 if (from_insn
== i3
13211 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13216 /* These notes say something about how a register is used. They must
13217 be present on any use of the register in I2 or I3. */
13218 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13221 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13230 case REG_LABEL_TARGET
:
13231 case REG_LABEL_OPERAND
:
13232 /* This can show up in several ways -- either directly in the
13233 pattern, or hidden off in the constant pool with (or without?)
13234 a REG_EQUAL note. */
13235 /* ??? Ignore the without-reg_equal-note problem for now. */
13236 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13237 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13238 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13239 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13243 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13244 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13245 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13246 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13254 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13255 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13257 if (place
&& JUMP_P (place
)
13258 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13259 && (JUMP_LABEL (place
) == NULL
13260 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13262 rtx label
= JUMP_LABEL (place
);
13265 JUMP_LABEL (place
) = XEXP (note
, 0);
13266 else if (LABEL_P (label
))
13267 LABEL_NUSES (label
)--;
13270 if (place2
&& JUMP_P (place2
)
13271 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13272 && (JUMP_LABEL (place2
) == NULL
13273 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13275 rtx label
= JUMP_LABEL (place2
);
13278 JUMP_LABEL (place2
) = XEXP (note
, 0);
13279 else if (LABEL_P (label
))
13280 LABEL_NUSES (label
)--;
13286 /* This note says something about the value of a register prior
13287 to the execution of an insn. It is too much trouble to see
13288 if the note is still correct in all situations. It is better
13289 to simply delete it. */
13293 /* If we replaced the right hand side of FROM_INSN with a
13294 REG_EQUAL note, the original use of the dying register
13295 will not have been combined into I3 and I2. In such cases,
13296 FROM_INSN is guaranteed to be the first of the combined
13297 instructions, so we simply need to search back before
13298 FROM_INSN for the previous use or set of this register,
13299 then alter the notes there appropriately.
13301 If the register is used as an input in I3, it dies there.
13302 Similarly for I2, if it is nonzero and adjacent to I3.
13304 If the register is not used as an input in either I3 or I2
13305 and it is not one of the registers we were supposed to eliminate,
13306 there are two possibilities. We might have a non-adjacent I2
13307 or we might have somehow eliminated an additional register
13308 from a computation. For example, we might have had A & B where
13309 we discover that B will always be zero. In this case we will
13310 eliminate the reference to A.
13312 In both cases, we must search to see if we can find a previous
13313 use of A and put the death note there. */
13316 && from_insn
== i2mod
13317 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13322 && CALL_P (from_insn
)
13323 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13325 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13327 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13328 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13330 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13332 && reg_overlap_mentioned_p (XEXP (note
, 0),
13334 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13335 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13342 basic_block bb
= this_basic_block
;
13344 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13346 if (!NONDEBUG_INSN_P (tem
))
13348 if (tem
== BB_HEAD (bb
))
13353 /* If the register is being set at TEM, see if that is all
13354 TEM is doing. If so, delete TEM. Otherwise, make this
13355 into a REG_UNUSED note instead. Don't delete sets to
13356 global register vars. */
13357 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13358 || !global_regs
[REGNO (XEXP (note
, 0))])
13359 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13361 rtx set
= single_set (tem
);
13362 rtx inner_dest
= 0;
13364 rtx cc0_setter
= NULL_RTX
;
13368 for (inner_dest
= SET_DEST (set
);
13369 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13370 || GET_CODE (inner_dest
) == SUBREG
13371 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13372 inner_dest
= XEXP (inner_dest
, 0))
13375 /* Verify that it was the set, and not a clobber that
13376 modified the register.
13378 CC0 targets must be careful to maintain setter/user
13379 pairs. If we cannot delete the setter due to side
13380 effects, mark the user with an UNUSED note instead
13383 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13384 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13386 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13387 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13388 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13392 /* Move the notes and links of TEM elsewhere.
13393 This might delete other dead insns recursively.
13394 First set the pattern to something that won't use
13396 rtx old_notes
= REG_NOTES (tem
);
13398 PATTERN (tem
) = pc_rtx
;
13399 REG_NOTES (tem
) = NULL
;
13401 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13402 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13403 distribute_links (LOG_LINKS (tem
));
13405 SET_INSN_DELETED (tem
);
13410 /* Delete the setter too. */
13413 PATTERN (cc0_setter
) = pc_rtx
;
13414 old_notes
= REG_NOTES (cc0_setter
);
13415 REG_NOTES (cc0_setter
) = NULL
;
13417 distribute_notes (old_notes
, cc0_setter
,
13418 cc0_setter
, NULL_RTX
,
13419 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13420 distribute_links (LOG_LINKS (cc0_setter
));
13422 SET_INSN_DELETED (cc0_setter
);
13423 if (cc0_setter
== i2
)
13430 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13432 /* If there isn't already a REG_UNUSED note, put one
13433 here. Do not place a REG_DEAD note, even if
13434 the register is also used here; that would not
13435 match the algorithm used in lifetime analysis
13436 and can cause the consistency check in the
13437 scheduler to fail. */
13438 if (! find_regno_note (tem
, REG_UNUSED
,
13439 REGNO (XEXP (note
, 0))))
13444 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13446 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13450 /* If we are doing a 3->2 combination, and we have a
13451 register which formerly died in i3 and was not used
13452 by i2, which now no longer dies in i3 and is used in
13453 i2 but does not die in i2, and place is between i2
13454 and i3, then we may need to move a link from place to
13456 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13458 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13459 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13461 rtx links
= LOG_LINKS (place
);
13462 LOG_LINKS (place
) = 0;
13463 distribute_links (links
);
13468 if (tem
== BB_HEAD (bb
))
13474 /* If the register is set or already dead at PLACE, we needn't do
13475 anything with this note if it is still a REG_DEAD note.
13476 We check here if it is set at all, not if is it totally replaced,
13477 which is what `dead_or_set_p' checks, so also check for it being
13480 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13482 unsigned int regno
= REGNO (XEXP (note
, 0));
13483 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
13485 if (dead_or_set_p (place
, XEXP (note
, 0))
13486 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13488 /* Unless the register previously died in PLACE, clear
13489 last_death. [I no longer understand why this is
13491 if (rsp
->last_death
!= place
)
13492 rsp
->last_death
= 0;
13496 rsp
->last_death
= place
;
13498 /* If this is a death note for a hard reg that is occupying
13499 multiple registers, ensure that we are still using all
13500 parts of the object. If we find a piece of the object
13501 that is unused, we must arrange for an appropriate REG_DEAD
13502 note to be added for it. However, we can't just emit a USE
13503 and tag the note to it, since the register might actually
13504 be dead; so we recourse, and the recursive call then finds
13505 the previous insn that used this register. */
13507 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13508 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13510 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13514 for (i
= regno
; i
< endregno
; i
++)
13515 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13516 && ! find_regno_fusage (place
, USE
, i
))
13517 || dead_or_set_regno_p (place
, i
))
13522 /* Put only REG_DEAD notes for pieces that are
13523 not already dead or set. */
13525 for (i
= regno
; i
< endregno
;
13526 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13528 rtx piece
= regno_reg_rtx
[i
];
13529 basic_block bb
= this_basic_block
;
13531 if (! dead_or_set_p (place
, piece
)
13532 && ! reg_bitfield_target_p (piece
,
13535 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13538 distribute_notes (new_note
, place
, place
,
13539 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13542 else if (! refers_to_regno_p (i
, i
+ 1,
13543 PATTERN (place
), 0)
13544 && ! find_regno_fusage (place
, USE
, i
))
13545 for (tem
= PREV_INSN (place
); ;
13546 tem
= PREV_INSN (tem
))
13548 if (!NONDEBUG_INSN_P (tem
))
13550 if (tem
== BB_HEAD (bb
))
13554 if (dead_or_set_p (tem
, piece
)
13555 || reg_bitfield_target_p (piece
,
13558 add_reg_note (tem
, REG_UNUSED
, piece
);
13572 /* Any other notes should not be present at this point in the
13574 gcc_unreachable ();
13579 XEXP (note
, 1) = REG_NOTES (place
);
13580 REG_NOTES (place
) = note
;
13584 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13588 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13589 I3, I2, and I1 to new locations. This is also called to add a link
13590 pointing at I3 when I3's destination is changed. */
13593 distribute_links (rtx links
)
13595 rtx link
, next_link
;
13597 for (link
= links
; link
; link
= next_link
)
13603 next_link
= XEXP (link
, 1);
13605 /* If the insn that this link points to is a NOTE or isn't a single
13606 set, ignore it. In the latter case, it isn't clear what we
13607 can do other than ignore the link, since we can't tell which
13608 register it was for. Such links wouldn't be used by combine
13611 It is not possible for the destination of the target of the link to
13612 have been changed by combine. The only potential of this is if we
13613 replace I3, I2, and I1 by I3 and I2. But in that case the
13614 destination of I2 also remains unchanged. */
13616 if (NOTE_P (XEXP (link
, 0))
13617 || (set
= single_set (XEXP (link
, 0))) == 0)
13620 reg
= SET_DEST (set
);
13621 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13622 || GET_CODE (reg
) == STRICT_LOW_PART
)
13623 reg
= XEXP (reg
, 0);
13625 /* A LOG_LINK is defined as being placed on the first insn that uses
13626 a register and points to the insn that sets the register. Start
13627 searching at the next insn after the target of the link and stop
13628 when we reach a set of the register or the end of the basic block.
13630 Note that this correctly handles the link that used to point from
13631 I3 to I2. Also note that not much searching is typically done here
13632 since most links don't point very far away. */
13634 for (insn
= NEXT_INSN (XEXP (link
, 0));
13635 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13636 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13637 insn
= NEXT_INSN (insn
))
13638 if (DEBUG_INSN_P (insn
))
13640 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13642 if (reg_referenced_p (reg
, PATTERN (insn
)))
13646 else if (CALL_P (insn
)
13647 && find_reg_fusage (insn
, USE
, reg
))
13652 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13655 /* If we found a place to put the link, place it there unless there
13656 is already a link to the same insn as LINK at that point. */
13662 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13663 if (XEXP (link2
, 0) == XEXP (link
, 0))
13668 XEXP (link
, 1) = LOG_LINKS (place
);
13669 LOG_LINKS (place
) = link
;
13671 /* Set added_links_insn to the earliest insn we added a
13673 if (added_links_insn
== 0
13674 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13675 added_links_insn
= place
;
13681 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13682 Check whether the expression pointer to by LOC is a register or
13683 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13684 Otherwise return zero. */
13687 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13692 && (REG_P (x
) || MEM_P (x
))
13693 && ! reg_mentioned_p (x
, (rtx
) expr
))
13698 /* Check for any register or memory mentioned in EQUIV that is not
13699 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13700 of EXPR where some registers may have been replaced by constants. */
13703 unmentioned_reg_p (rtx equiv
, rtx expr
)
13705 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13709 dump_combine_stats (FILE *file
)
13713 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13714 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13718 dump_combine_total_stats (FILE *file
)
13722 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13723 total_attempts
, total_merges
, total_extras
, total_successes
);
13727 gate_handle_combine (void)
13729 return (optimize
> 0);
13732 /* Try combining insns through substitution. */
13733 static unsigned int
13734 rest_of_handle_combine (void)
13736 int rebuild_jump_labels_after_combine
;
13738 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13739 df_note_add_problem ();
13742 regstat_init_n_sets_and_refs ();
13744 rebuild_jump_labels_after_combine
13745 = combine_instructions (get_insns (), max_reg_num ());
13747 /* Combining insns may have turned an indirect jump into a
13748 direct jump. Rebuild the JUMP_LABEL fields of jumping
13750 if (rebuild_jump_labels_after_combine
)
13752 timevar_push (TV_JUMP
);
13753 rebuild_jump_labels (get_insns ());
13755 timevar_pop (TV_JUMP
);
13758 regstat_free_n_sets_and_refs ();
13762 struct rtl_opt_pass pass_combine
=
13766 "combine", /* name */
13767 gate_handle_combine
, /* gate */
13768 rest_of_handle_combine
, /* execute */
13771 0, /* static_pass_number */
13772 TV_COMBINE
, /* tv_id */
13773 PROP_cfglayout
, /* properties_required */
13774 0, /* properties_provided */
13775 0, /* properties_destroyed */
13776 0, /* todo_flags_start */
13778 TODO_df_finish
| TODO_verify_rtl_sharing
|
13779 TODO_ggc_collect
, /* todo_flags_finish */