1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; I -- An 8-bit constant (0..255).
31 ;; J -- A 12-bit constant (0..4095).
32 ;; K -- A 16-bit constant (-32768..32767).
33 ;; L -- Value appropriate as displacement.
34 ;; (0..4095) for short displacement
35 ;; (-524288..524287) for long displacement
36 ;; M -- Constant integer with a value of 0x7fffffff.
37 ;; N -- Multiple letter constraint followed by 4 parameter letters.
38 ;; 0..9,x: number of the part counting from most to least significant
39 ;; H,Q: mode of the part
40 ;; D,S,H: mode of the containing operand
41 ;; 0,F: value of the other parts (F - all bits set)
43 ;; The constraint matches if the specified part of a constant
44 ;; has a value different from its other parts. If the letter x
45 ;; is specified instead of a part number, the constraint matches
46 ;; if there is any single part with non-default value.
47 ;; Q -- Memory reference without index register and with short displacement.
48 ;; R -- Memory reference with index register and short displacement.
49 ;; S -- Memory reference without index register but with long displacement.
50 ;; T -- Memory reference with index register and long displacement.
51 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
52 ;; Offsettable memory reference of type specified by second letter.
53 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
54 ;; Memory reference of the type specified by second letter that
55 ;; does *not* refer to a literal pool entry.
56 ;; U -- Pointer with short displacement.
57 ;; W -- Pointer with long displacement.
58 ;; Y -- Shift count operand.
60 ;; Special formats used for outputting 390 instructions.
62 ;; %C: print opcode suffix for branch condition.
63 ;; %D: print opcode suffix for inverse branch condition.
64 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
65 ;; %O: print only the displacement of a memory reference.
66 ;; %R: print only the base register of a memory reference.
67 ;; %S: print S-type memory reference (base+displacement).
68 ;; %N: print the second word of a DImode operand.
69 ;; %M: print the second word of a TImode operand.
71 ;; %b: print integer X as if it's an unsigned byte.
72 ;; %x: print integer X as if it's an unsigned word.
73 ;; %h: print integer X as if it's a signed word.
74 ;; %i: print the first nonzero HImode part of X
75 ;; %j: print the first HImode part unequal to 0xffff of X
78 ;; We have a special constraint for pattern matching.
80 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
93 ; GOT/PLT and lt-relative accesses
94 (UNSPEC_LTREL_OFFSET 100)
95 (UNSPEC_LTREL_BASE 101)
103 (UNSPEC_RELOAD_BASE 210)
104 (UNSPEC_MAIN_BASE 211)
109 ; TLS relocation specifiers
114 (UNSPEC_GOTNTPOFF 504)
115 (UNSPEC_INDNTPOFF 505)
118 (UNSPEC_TLSLDM_NTPOFF 511)
119 (UNSPEC_TLS_LOAD 512)
126 ;; UNSPEC_VOLATILE usage
134 (UNSPECV_TPF_PROLOGUE 20)
135 (UNSPECV_TPF_EPILOGUE 21)
139 (UNSPECV_POOL_SECTION 201)
140 (UNSPECV_POOL_ALIGN 202)
141 (UNSPECV_POOL_ENTRY 203)
142 (UNSPECV_MAIN_POOL 300)
149 ;; Instruction operand type as used in the Principles of Operation.
150 ;; Used to determine defaults for length and other attribute values.
152 (define_attr "op_type"
153 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
156 ;; Instruction type attribute used for scheduling.
158 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
160 imulhi,imulsi,imuldi,
161 branch,jsr,fsimpd,fsimps,
162 floadd,floads,fstored, fstores,
163 fmuld,fmuls,fdivd,fdivs,
164 ftoi,itof,fsqrtd,fsqrts,
166 (cond [(eq_attr "op_type" "NN") (const_string "other")
167 (eq_attr "op_type" "SS") (const_string "cs")]
168 (const_string "integer")))
170 ;; Another attribute used for scheduling purposes:
171 ;; agen: Instruction uses the address generation unit
172 ;; reg: Instruction does not use the agen unit
174 (define_attr "atype" "agen,reg"
175 (cond [(eq_attr "op_type" "E") (const_string "reg")
176 (eq_attr "op_type" "RR") (const_string "reg")
177 (eq_attr "op_type" "RX") (const_string "agen")
178 (eq_attr "op_type" "RI") (const_string "reg")
179 (eq_attr "op_type" "RRE") (const_string "reg")
180 (eq_attr "op_type" "RS") (const_string "agen")
181 (eq_attr "op_type" "RSI") (const_string "agen")
182 (eq_attr "op_type" "S") (const_string "agen")
183 (eq_attr "op_type" "SI") (const_string "agen")
184 (eq_attr "op_type" "SS") (const_string "agen")
185 (eq_attr "op_type" "SSE") (const_string "agen")
186 (eq_attr "op_type" "RXE") (const_string "agen")
187 (eq_attr "op_type" "RSE") (const_string "agen")
188 (eq_attr "op_type" "RIL") (const_string "agen")
189 (eq_attr "op_type" "RXY") (const_string "agen")
190 (eq_attr "op_type" "RSY") (const_string "agen")
191 (eq_attr "op_type" "SIY") (const_string "agen")]
192 (const_string "agen")))
196 (define_attr "length" ""
197 (cond [(eq_attr "op_type" "E") (const_int 2)
198 (eq_attr "op_type" "RR") (const_int 2)
199 (eq_attr "op_type" "RX") (const_int 4)
200 (eq_attr "op_type" "RI") (const_int 4)
201 (eq_attr "op_type" "RRE") (const_int 4)
202 (eq_attr "op_type" "RS") (const_int 4)
203 (eq_attr "op_type" "RSI") (const_int 4)
204 (eq_attr "op_type" "S") (const_int 4)
205 (eq_attr "op_type" "SI") (const_int 4)
206 (eq_attr "op_type" "SS") (const_int 6)
207 (eq_attr "op_type" "SSE") (const_int 6)
208 (eq_attr "op_type" "RXE") (const_int 6)
209 (eq_attr "op_type" "RSE") (const_int 6)
210 (eq_attr "op_type" "RIL") (const_int 6)
211 (eq_attr "op_type" "RXY") (const_int 6)
212 (eq_attr "op_type" "RSY") (const_int 6)
213 (eq_attr "op_type" "SIY") (const_int 6)]
217 ;; Processor type. This attribute must exactly match the processor_type
218 ;; enumeration in s390.h. The current machine description does not
219 ;; distinguish between g5 and g6, but there are differences between the two
220 ;; CPUs could in theory be modeled.
222 (define_attr "cpu" "g5,g6,z900,z990"
223 (const (symbol_ref "s390_tune")))
225 ;; Pipeline description for z900. For lack of anything better,
226 ;; this description is also used for the g5 and g6.
229 ;; Pipeline description for z990.
233 (include "predicates.md")
236 ;;- Compare instructions.
239 (define_expand "cmpdi"
241 (compare:CC (match_operand:DI 0 "register_operand" "")
242 (match_operand:DI 1 "general_operand" "")))]
245 s390_compare_op0 = operands[0];
246 s390_compare_op1 = operands[1];
250 (define_expand "cmpsi"
252 (compare:CC (match_operand:SI 0 "register_operand" "")
253 (match_operand:SI 1 "general_operand" "")))]
256 s390_compare_op0 = operands[0];
257 s390_compare_op1 = operands[1];
261 (define_expand "cmpdf"
263 (compare:CC (match_operand:DF 0 "register_operand" "")
264 (match_operand:DF 1 "general_operand" "")))]
267 s390_compare_op0 = operands[0];
268 s390_compare_op1 = operands[1];
272 (define_expand "cmpsf"
274 (compare:CC (match_operand:SF 0 "register_operand" "")
275 (match_operand:SF 1 "general_operand" "")))]
278 s390_compare_op0 = operands[0];
279 s390_compare_op1 = operands[1];
284 ; Test-under-Mask instructions
286 (define_insn "*tmqi_mem"
288 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
289 (match_operand:QI 1 "immediate_operand" "n,n"))
290 (match_operand:QI 2 "immediate_operand" "n,n")))]
291 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
295 [(set_attr "op_type" "SI,SIY")])
297 (define_insn "*tmdi_reg"
299 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
300 (match_operand:DI 1 "immediate_operand"
301 "N0HD0,N1HD0,N2HD0,N3HD0"))
302 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
304 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
305 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
311 [(set_attr "op_type" "RI")])
313 (define_insn "*tmsi_reg"
315 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
316 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
317 (match_operand:SI 2 "immediate_operand" "n,n")))]
318 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
319 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
323 [(set_attr "op_type" "RI")])
325 (define_insn "*tmhi_full"
327 (compare (match_operand:HI 0 "register_operand" "d")
328 (match_operand:HI 1 "immediate_operand" "n")))]
329 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
331 [(set_attr "op_type" "RI")])
333 (define_insn "*tmqi_full"
335 (compare (match_operand:QI 0 "register_operand" "d")
336 (match_operand:QI 1 "immediate_operand" "n")))]
337 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
339 [(set_attr "op_type" "RI")])
342 ; Load-and-Test instructions
344 (define_insn "*tstdi_sign"
346 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
347 (const_int 32)) (const_int 32))
348 (match_operand:DI 1 "const0_operand" "")))
349 (set (match_operand:DI 2 "register_operand" "=d")
350 (sign_extend:DI (match_dup 0)))]
351 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
353 [(set_attr "op_type" "RRE")])
355 (define_insn "*tstdi"
357 (compare (match_operand:DI 0 "register_operand" "d")
358 (match_operand:DI 1 "const0_operand" "")))
359 (set (match_operand:DI 2 "register_operand" "=d")
361 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
363 [(set_attr "op_type" "RRE")])
365 (define_insn "*tstdi_cconly"
367 (compare (match_operand:DI 0 "register_operand" "d")
368 (match_operand:DI 1 "const0_operand" "")))]
369 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
371 [(set_attr "op_type" "RRE")])
373 (define_insn "*tstdi_cconly_31"
375 (compare (match_operand:DI 0 "register_operand" "d")
376 (match_operand:DI 1 "const0_operand" "")))]
377 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
379 [(set_attr "op_type" "RS")
380 (set_attr "atype" "reg")])
383 (define_insn "*tstsi"
385 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
386 (match_operand:SI 1 "const0_operand" "")))
387 (set (match_operand:SI 2 "register_operand" "=d,d,d")
389 "s390_match_ccmode(insn, CCSmode)"
394 [(set_attr "op_type" "RR,RS,RSY")])
396 (define_insn "*tstsi_cconly"
398 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
399 (match_operand:SI 1 "const0_operand" "")))
400 (clobber (match_scratch:SI 2 "=X,d,d"))]
401 "s390_match_ccmode(insn, CCSmode)"
406 [(set_attr "op_type" "RR,RS,RSY")])
408 (define_insn "*tstsi_cconly2"
410 (compare (match_operand:SI 0 "register_operand" "d")
411 (match_operand:SI 1 "const0_operand" "")))]
412 "s390_match_ccmode(insn, CCSmode)"
414 [(set_attr "op_type" "RR")])
416 (define_insn "*tsthiCCT"
418 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d")
419 (match_operand:HI 1 "const0_operand" "")))
420 (set (match_operand:HI 2 "register_operand" "=d,d,0")
422 "s390_match_ccmode(insn, CCTmode)"
427 [(set_attr "op_type" "RS,RSY,RI")])
429 (define_insn "*tsthiCCT_cconly"
431 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
432 (match_operand:HI 1 "const0_operand" "")))
433 (clobber (match_scratch:HI 2 "=d,d,X"))]
434 "s390_match_ccmode(insn, CCTmode)"
439 [(set_attr "op_type" "RS,RSY,RI")])
441 (define_insn "*tsthi"
443 (compare (match_operand:HI 0 "s_operand" "Q,S")
444 (match_operand:HI 1 "const0_operand" "")))
445 (set (match_operand:HI 2 "register_operand" "=d,d")
447 "s390_match_ccmode(insn, CCSmode)"
451 [(set_attr "op_type" "RS,RSY")])
453 (define_insn "*tsthi_cconly"
455 (compare (match_operand:HI 0 "s_operand" "Q,S")
456 (match_operand:HI 1 "const0_operand" "")))
457 (clobber (match_scratch:HI 2 "=d,d"))]
458 "s390_match_ccmode(insn, CCSmode)"
462 [(set_attr "op_type" "RS,RSY")])
464 (define_insn "*tstqiCCT"
466 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
467 (match_operand:QI 1 "const0_operand" "")))
468 (set (match_operand:QI 2 "register_operand" "=d,d,0")
470 "s390_match_ccmode(insn, CCTmode)"
475 [(set_attr "op_type" "RS,RSY,RI")])
477 (define_insn "*tstqiCCT_cconly"
479 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
480 (match_operand:QI 1 "const0_operand" "")))]
481 "s390_match_ccmode(insn, CCTmode)"
486 [(set_attr "op_type" "SI,SIY,RI")])
488 (define_insn "*tstqi"
490 (compare (match_operand:QI 0 "s_operand" "Q,S")
491 (match_operand:QI 1 "const0_operand" "")))
492 (set (match_operand:QI 2 "register_operand" "=d,d")
494 "s390_match_ccmode(insn, CCSmode)"
498 [(set_attr "op_type" "RS,RSY")])
500 (define_insn "*tstqi_cconly"
502 (compare (match_operand:QI 0 "s_operand" "Q,S")
503 (match_operand:QI 1 "const0_operand" "")))
504 (clobber (match_scratch:QI 2 "=d,d"))]
505 "s390_match_ccmode(insn, CCSmode)"
509 [(set_attr "op_type" "RS,RSY")])
512 ; Compare (equality) instructions
514 (define_insn "*cmpdi_cct"
516 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
517 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
518 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
524 [(set_attr "op_type" "RRE,RI,RXY,SS")])
526 (define_insn "*cmpsi_cct"
528 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
529 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
530 "s390_match_ccmode (insn, CCTmode)"
537 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
540 ; Compare (signed) instructions
542 (define_insn "*cmpdi_ccs_sign"
544 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
545 (match_operand:DI 0 "register_operand" "d,d")))]
546 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
550 [(set_attr "op_type" "RRE,RXY")])
552 (define_insn "*cmpdi_ccs"
554 (compare (match_operand:DI 0 "register_operand" "d,d,d")
555 (match_operand:DI 1 "general_operand" "d,K,m")))]
556 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
561 [(set_attr "op_type" "RRE,RI,RXY")])
563 (define_insn "*cmpsi_ccs_sign"
565 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
566 (match_operand:SI 0 "register_operand" "d,d")))]
567 "s390_match_ccmode(insn, CCSRmode)"
571 [(set_attr "op_type" "RX,RXY")])
573 (define_insn "*cmpsi_ccs"
575 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
576 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
577 "s390_match_ccmode(insn, CCSmode)"
583 [(set_attr "op_type" "RR,RI,RX,RXY")])
586 ; Compare (unsigned) instructions
588 (define_insn "*cmpdi_ccu_zero"
590 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
591 (match_operand:DI 0 "register_operand" "d,d")))]
592 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
596 [(set_attr "op_type" "RRE,RXY")])
598 (define_insn "*cmpdi_ccu"
600 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
601 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
602 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
608 [(set_attr "op_type" "RRE,RXY,SS,SS")])
610 (define_insn "*cmpsi_ccu"
612 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
613 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
614 "s390_match_ccmode (insn, CCUmode)"
621 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
623 (define_insn "*cmphi_ccu"
625 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
626 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
627 "s390_match_ccmode (insn, CCUmode)
628 && !register_operand (operands[1], HImode)"
634 [(set_attr "op_type" "RS,RSY,SS,SS")])
636 (define_insn "*cmpqi_ccu"
638 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
639 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
640 "s390_match_ccmode (insn, CCUmode)
641 && !register_operand (operands[1], QImode)"
649 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
652 ; Block compare (CLC) instruction patterns.
656 (compare (match_operand:BLK 0 "memory_operand" "Q")
657 (match_operand:BLK 1 "memory_operand" "Q")))
658 (use (match_operand 2 "const_int_operand" "n"))]
659 "s390_match_ccmode (insn, CCUmode)
660 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
661 "clc\t%O0(%2,%R0),%S1"
662 [(set_attr "op_type" "SS")])
666 (compare (match_operand 0 "memory_operand" "")
667 (match_operand 1 "memory_operand" "")))]
669 && s390_match_ccmode (insn, CCUmode)
670 && GET_MODE (operands[0]) == GET_MODE (operands[1])
671 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
673 [(set (match_dup 0) (match_dup 1))
674 (use (match_dup 2))])]
676 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
677 operands[0] = adjust_address (operands[0], BLKmode, 0);
678 operands[1] = adjust_address (operands[1], BLKmode, 0);
680 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
681 operands[0], operands[1]);
682 operands[0] = SET_DEST (PATTERN (curr_insn));
688 (define_insn "*cmpdf_ccs_0"
690 (compare (match_operand:DF 0 "register_operand" "f")
691 (match_operand:DF 1 "const0_operand" "")))]
692 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
694 [(set_attr "op_type" "RRE")
695 (set_attr "type" "fsimpd")])
697 (define_insn "*cmpdf_ccs_0_ibm"
699 (compare (match_operand:DF 0 "register_operand" "f")
700 (match_operand:DF 1 "const0_operand" "")))]
701 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
703 [(set_attr "op_type" "RR")
704 (set_attr "type" "fsimpd")])
706 (define_insn "*cmpdf_ccs"
708 (compare (match_operand:DF 0 "register_operand" "f,f")
709 (match_operand:DF 1 "general_operand" "f,R")))]
710 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
714 [(set_attr "op_type" "RRE,RXE")
715 (set_attr "type" "fsimpd")])
717 (define_insn "*cmpdf_ccs_ibm"
719 (compare (match_operand:DF 0 "register_operand" "f,f")
720 (match_operand:DF 1 "general_operand" "f,R")))]
721 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
725 [(set_attr "op_type" "RR,RX")
726 (set_attr "type" "fsimpd")])
731 (define_insn "*cmpsf_ccs_0"
733 (compare (match_operand:SF 0 "register_operand" "f")
734 (match_operand:SF 1 "const0_operand" "")))]
735 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
737 [(set_attr "op_type" "RRE")
738 (set_attr "type" "fsimps")])
740 (define_insn "*cmpsf_ccs_0_ibm"
742 (compare (match_operand:SF 0 "register_operand" "f")
743 (match_operand:SF 1 "const0_operand" "")))]
744 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
746 [(set_attr "op_type" "RR")
747 (set_attr "type" "fsimps")])
749 (define_insn "*cmpsf_ccs"
751 (compare (match_operand:SF 0 "register_operand" "f,f")
752 (match_operand:SF 1 "general_operand" "f,R")))]
753 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
757 [(set_attr "op_type" "RRE,RXE")
758 (set_attr "type" "fsimps")])
760 (define_insn "*cmpsf_ccs"
762 (compare (match_operand:SF 0 "register_operand" "f,f")
763 (match_operand:SF 1 "general_operand" "f,R")))]
764 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
768 [(set_attr "op_type" "RR,RX")
769 (set_attr "type" "fsimps")])
773 ;;- Move instructions.
777 ; movti instruction pattern(s).
781 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
782 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
790 [(set_attr "op_type" "RSY,RSY,*,*,SS")
791 (set_attr "type" "lm,stm,*,*,*")])
794 [(set (match_operand:TI 0 "nonimmediate_operand" "")
795 (match_operand:TI 1 "general_operand" ""))]
796 "TARGET_64BIT && reload_completed
797 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
798 [(set (match_dup 2) (match_dup 4))
799 (set (match_dup 3) (match_dup 5))]
801 operands[2] = operand_subword (operands[0], 0, 0, TImode);
802 operands[3] = operand_subword (operands[0], 1, 0, TImode);
803 operands[4] = operand_subword (operands[1], 0, 0, TImode);
804 operands[5] = operand_subword (operands[1], 1, 0, TImode);
808 [(set (match_operand:TI 0 "nonimmediate_operand" "")
809 (match_operand:TI 1 "general_operand" ""))]
810 "TARGET_64BIT && reload_completed
811 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
812 [(set (match_dup 2) (match_dup 4))
813 (set (match_dup 3) (match_dup 5))]
815 operands[2] = operand_subword (operands[0], 1, 0, TImode);
816 operands[3] = operand_subword (operands[0], 0, 0, TImode);
817 operands[4] = operand_subword (operands[1], 1, 0, TImode);
818 operands[5] = operand_subword (operands[1], 0, 0, TImode);
822 [(set (match_operand:TI 0 "register_operand" "")
823 (match_operand:TI 1 "memory_operand" ""))]
824 "TARGET_64BIT && reload_completed
825 && !s_operand (operands[1], VOIDmode)"
826 [(set (match_dup 0) (match_dup 1))]
828 rtx addr = operand_subword (operands[0], 1, 0, TImode);
829 s390_load_address (addr, XEXP (operands[1], 0));
830 operands[1] = replace_equiv_address (operands[1], addr);
833 (define_expand "reload_outti"
834 [(parallel [(match_operand:TI 0 "" "")
835 (match_operand:TI 1 "register_operand" "d")
836 (match_operand:DI 2 "register_operand" "=&a")])]
839 gcc_assert (MEM_P (operands[0]));
840 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
841 operands[0] = replace_equiv_address (operands[0], operands[2]);
842 emit_move_insn (operands[0], operands[1]);
847 ; movdi instruction pattern(s).
850 (define_expand "movdi"
851 [(set (match_operand:DI 0 "general_operand" "")
852 (match_operand:DI 1 "general_operand" ""))]
855 /* Handle symbolic constants. */
856 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
857 emit_symbolic_move (operands);
860 (define_insn "*movdi_larl"
861 [(set (match_operand:DI 0 "register_operand" "=d")
862 (match_operand:DI 1 "larl_operand" "X"))]
864 && !FP_REG_P (operands[0])"
866 [(set_attr "op_type" "RIL")
867 (set_attr "type" "larl")])
869 (define_insn "*movdi_64"
870 [(set (match_operand:DI 0 "nonimmediate_operand"
871 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
872 (match_operand:DI 1 "general_operand"
873 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
895 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
896 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
897 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
898 floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")])
901 [(set (match_operand:DI 0 "register_operand" "")
902 (match_operand:DI 1 "register_operand" ""))]
903 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
904 [(set (match_dup 2) (match_dup 3))
905 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
906 (set (strict_low_part (match_dup 2)) (match_dup 4))]
907 "operands[2] = gen_lowpart (SImode, operands[0]);
908 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
911 [(set (match_operand:DI 0 "register_operand" "")
912 (match_operand:DI 1 "register_operand" ""))]
913 "TARGET_64BIT && ACCESS_REG_P (operands[0])
914 && dead_or_set_p (insn, operands[1])"
915 [(set (match_dup 3) (match_dup 2))
916 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
917 (set (match_dup 4) (match_dup 2))]
918 "operands[2] = gen_lowpart (SImode, operands[1]);
919 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
922 [(set (match_operand:DI 0 "register_operand" "")
923 (match_operand:DI 1 "register_operand" ""))]
924 "TARGET_64BIT && ACCESS_REG_P (operands[0])
925 && !dead_or_set_p (insn, operands[1])"
926 [(set (match_dup 3) (match_dup 2))
927 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
928 (set (match_dup 4) (match_dup 2))
929 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
930 "operands[2] = gen_lowpart (SImode, operands[1]);
931 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
933 (define_insn "*movdi_31"
934 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
935 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
948 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
949 (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")])
952 [(set (match_operand:DI 0 "nonimmediate_operand" "")
953 (match_operand:DI 1 "general_operand" ""))]
954 "!TARGET_64BIT && reload_completed
955 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
956 [(set (match_dup 2) (match_dup 4))
957 (set (match_dup 3) (match_dup 5))]
959 operands[2] = operand_subword (operands[0], 0, 0, DImode);
960 operands[3] = operand_subword (operands[0], 1, 0, DImode);
961 operands[4] = operand_subword (operands[1], 0, 0, DImode);
962 operands[5] = operand_subword (operands[1], 1, 0, DImode);
966 [(set (match_operand:DI 0 "nonimmediate_operand" "")
967 (match_operand:DI 1 "general_operand" ""))]
968 "!TARGET_64BIT && reload_completed
969 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
970 [(set (match_dup 2) (match_dup 4))
971 (set (match_dup 3) (match_dup 5))]
973 operands[2] = operand_subword (operands[0], 1, 0, DImode);
974 operands[3] = operand_subword (operands[0], 0, 0, DImode);
975 operands[4] = operand_subword (operands[1], 1, 0, DImode);
976 operands[5] = operand_subword (operands[1], 0, 0, DImode);
980 [(set (match_operand:DI 0 "register_operand" "")
981 (match_operand:DI 1 "memory_operand" ""))]
982 "!TARGET_64BIT && reload_completed
983 && !FP_REG_P (operands[0])
984 && !s_operand (operands[1], VOIDmode)"
985 [(set (match_dup 0) (match_dup 1))]
987 rtx addr = operand_subword (operands[0], 1, 0, DImode);
988 s390_load_address (addr, XEXP (operands[1], 0));
989 operands[1] = replace_equiv_address (operands[1], addr);
992 (define_expand "reload_outdi"
993 [(parallel [(match_operand:DI 0 "" "")
994 (match_operand:DI 1 "register_operand" "d")
995 (match_operand:SI 2 "register_operand" "=&a")])]
998 gcc_assert (MEM_P (operands[0]));
999 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1000 operands[0] = replace_equiv_address (operands[0], operands[2]);
1001 emit_move_insn (operands[0], operands[1]);
1006 [(set (match_operand:DI 0 "register_operand" "")
1007 (mem:DI (match_operand 1 "address_operand" "")))]
1009 && !FP_REG_P (operands[0])
1010 && GET_CODE (operands[1]) == SYMBOL_REF
1011 && CONSTANT_POOL_ADDRESS_P (operands[1])
1012 && get_pool_mode (operands[1]) == DImode
1013 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1014 [(set (match_dup 0) (match_dup 2))]
1015 "operands[2] = get_pool_constant (operands[1]);")
1017 (define_insn "*la_64"
1018 [(set (match_operand:DI 0 "register_operand" "=d,d")
1019 (match_operand:QI 1 "address_operand" "U,W"))]
1024 [(set_attr "op_type" "RX,RXY")
1025 (set_attr "type" "la")])
1029 [(set (match_operand:DI 0 "register_operand" "")
1030 (match_operand:QI 1 "address_operand" ""))
1031 (clobber (reg:CC 33))])]
1033 && preferred_la_operand_p (operands[1], const0_rtx)"
1034 [(set (match_dup 0) (match_dup 1))]
1038 [(set (match_operand:DI 0 "register_operand" "")
1039 (match_operand:DI 1 "register_operand" ""))
1042 (plus:DI (match_dup 0)
1043 (match_operand:DI 2 "nonmemory_operand" "")))
1044 (clobber (reg:CC 33))])]
1046 && !reg_overlap_mentioned_p (operands[0], operands[2])
1047 && preferred_la_operand_p (operands[1], operands[2])"
1048 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1051 (define_expand "reload_indi"
1052 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1053 (match_operand:DI 1 "s390_plus_operand" "")
1054 (match_operand:DI 2 "register_operand" "=&a")])]
1057 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1062 ; movsi instruction pattern(s).
1065 (define_expand "movsi"
1066 [(set (match_operand:SI 0 "general_operand" "")
1067 (match_operand:SI 1 "general_operand" ""))]
1070 /* Handle symbolic constants. */
1071 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1072 emit_symbolic_move (operands);
1075 (define_insn "*movsi_larl"
1076 [(set (match_operand:SI 0 "register_operand" "=d")
1077 (match_operand:SI 1 "larl_operand" "X"))]
1078 "!TARGET_64BIT && TARGET_CPU_ZARCH
1079 && !FP_REG_P (operands[0])"
1081 [(set_attr "op_type" "RIL")
1082 (set_attr "type" "larl")])
1084 (define_insn "*movsi_zarch"
1085 [(set (match_operand:SI 0 "nonimmediate_operand"
1086 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1087 (match_operand:SI 1 "general_operand"
1088 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1110 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1111 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1112 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1113 floads,floads,floads,fstores,fstores,*,*,*,*,*")])
1115 (define_insn "*movsi_esa"
1116 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1117 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1132 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1133 (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")])
1136 [(set (match_operand:SI 0 "register_operand" "")
1137 (mem:SI (match_operand 1 "address_operand" "")))]
1138 "!FP_REG_P (operands[0])
1139 && GET_CODE (operands[1]) == SYMBOL_REF
1140 && CONSTANT_POOL_ADDRESS_P (operands[1])
1141 && get_pool_mode (operands[1]) == SImode
1142 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1143 [(set (match_dup 0) (match_dup 2))]
1144 "operands[2] = get_pool_constant (operands[1]);")
1146 (define_insn "*la_31"
1147 [(set (match_operand:SI 0 "register_operand" "=d,d")
1148 (match_operand:QI 1 "address_operand" "U,W"))]
1149 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1153 [(set_attr "op_type" "RX,RXY")
1154 (set_attr "type" "la")])
1158 [(set (match_operand:SI 0 "register_operand" "")
1159 (match_operand:QI 1 "address_operand" ""))
1160 (clobber (reg:CC 33))])]
1162 && preferred_la_operand_p (operands[1], const0_rtx)"
1163 [(set (match_dup 0) (match_dup 1))]
1167 [(set (match_operand:SI 0 "register_operand" "")
1168 (match_operand:SI 1 "register_operand" ""))
1171 (plus:SI (match_dup 0)
1172 (match_operand:SI 2 "nonmemory_operand" "")))
1173 (clobber (reg:CC 33))])]
1175 && !reg_overlap_mentioned_p (operands[0], operands[2])
1176 && preferred_la_operand_p (operands[1], operands[2])"
1177 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1180 (define_insn "*la_31_and"
1181 [(set (match_operand:SI 0 "register_operand" "=d,d")
1182 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1183 (const_int 2147483647)))]
1188 [(set_attr "op_type" "RX,RXY")
1189 (set_attr "type" "la")])
1191 (define_insn_and_split "*la_31_and_cc"
1192 [(set (match_operand:SI 0 "register_operand" "=d")
1193 (and:SI (match_operand:QI 1 "address_operand" "p")
1194 (const_int 2147483647)))
1195 (clobber (reg:CC 33))]
1198 "&& reload_completed"
1200 (and:SI (match_dup 1) (const_int 2147483647)))]
1202 [(set_attr "op_type" "RX")
1203 (set_attr "type" "la")])
1205 (define_insn "force_la_31"
1206 [(set (match_operand:SI 0 "register_operand" "=d,d")
1207 (match_operand:QI 1 "address_operand" "U,W"))
1208 (use (const_int 0))]
1213 [(set_attr "op_type" "RX")
1214 (set_attr "type" "la")])
1216 (define_expand "reload_insi"
1217 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1218 (match_operand:SI 1 "s390_plus_operand" "")
1219 (match_operand:SI 2 "register_operand" "=&a")])]
1222 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1227 ; movhi instruction pattern(s).
1230 (define_expand "movhi"
1231 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1232 (match_operand:HI 1 "general_operand" ""))]
1235 /* Make it explicit that loading a register from memory
1236 always sign-extends (at least) to SImode. */
1237 if (optimize && !no_new_pseudos
1238 && register_operand (operands[0], VOIDmode)
1239 && GET_CODE (operands[1]) == MEM)
1241 rtx tmp = gen_reg_rtx (SImode);
1242 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1243 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1244 operands[1] = gen_lowpart (HImode, tmp);
1248 (define_insn "*movhi"
1249 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1250 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1260 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1261 (set_attr "type" "lr,*,*,*,store,store,*")])
1264 [(set (match_operand:HI 0 "register_operand" "")
1265 (mem:HI (match_operand 1 "address_operand" "")))]
1266 "GET_CODE (operands[1]) == SYMBOL_REF
1267 && CONSTANT_POOL_ADDRESS_P (operands[1])
1268 && get_pool_mode (operands[1]) == HImode
1269 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1270 [(set (match_dup 0) (match_dup 2))]
1271 "operands[2] = get_pool_constant (operands[1]);")
1274 ; movqi instruction pattern(s).
1277 (define_expand "movqi"
1278 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1279 (match_operand:QI 1 "general_operand" ""))]
1282 /* On z/Architecture, zero-extending from memory to register
1283 is just as fast as a QImode load. */
1284 if (TARGET_ZARCH && optimize && !no_new_pseudos
1285 && register_operand (operands[0], VOIDmode)
1286 && GET_CODE (operands[1]) == MEM)
1288 rtx tmp = gen_reg_rtx (word_mode);
1289 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1290 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1291 operands[1] = gen_lowpart (QImode, tmp);
1295 (define_insn "*movqi"
1296 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1297 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1309 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1310 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1313 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1314 (mem:QI (match_operand 1 "address_operand" "")))]
1315 "GET_CODE (operands[1]) == SYMBOL_REF
1316 && CONSTANT_POOL_ADDRESS_P (operands[1])
1317 && get_pool_mode (operands[1]) == QImode
1318 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1319 [(set (match_dup 0) (match_dup 2))]
1320 "operands[2] = get_pool_constant (operands[1]);")
1323 ; movstrictqi instruction pattern(s).
1326 (define_insn "*movstrictqi"
1327 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1328 (match_operand:QI 1 "memory_operand" "R,T"))]
1333 [(set_attr "op_type" "RX,RXY")])
1336 ; movstricthi instruction pattern(s).
1339 (define_insn "*movstricthi"
1340 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1341 (match_operand:HI 1 "memory_operand" "Q,S"))
1342 (clobber (reg:CC 33))]
1347 [(set_attr "op_type" "RS,RSY")])
1350 ; movstrictsi instruction pattern(s).
1353 (define_insn "movstrictsi"
1354 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1355 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1362 [(set_attr "op_type" "RR,RX,RXY,RRE")
1363 (set_attr "type" "lr,load,load,*")])
1366 ; movdf instruction pattern(s).
1369 (define_expand "movdf"
1370 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1371 (match_operand:DF 1 "general_operand" ""))]
1375 (define_insn "*movdf_64"
1376 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
1377 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
1389 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1390 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")])
1392 (define_insn "*movdf_31"
1393 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
1394 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
1407 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1408 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")])
1411 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1412 (match_operand:DF 1 "general_operand" ""))]
1413 "!TARGET_64BIT && reload_completed
1414 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1415 [(set (match_dup 2) (match_dup 4))
1416 (set (match_dup 3) (match_dup 5))]
1418 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1419 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1420 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1421 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1425 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1426 (match_operand:DF 1 "general_operand" ""))]
1427 "!TARGET_64BIT && reload_completed
1428 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1429 [(set (match_dup 2) (match_dup 4))
1430 (set (match_dup 3) (match_dup 5))]
1432 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1433 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1434 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1435 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1439 [(set (match_operand:DF 0 "register_operand" "")
1440 (match_operand:DF 1 "memory_operand" ""))]
1441 "!TARGET_64BIT && reload_completed
1442 && !FP_REG_P (operands[0])
1443 && !s_operand (operands[1], VOIDmode)"
1444 [(set (match_dup 0) (match_dup 1))]
1446 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1447 s390_load_address (addr, XEXP (operands[1], 0));
1448 operands[1] = replace_equiv_address (operands[1], addr);
1451 (define_expand "reload_outdf"
1452 [(parallel [(match_operand:DF 0 "" "")
1453 (match_operand:DF 1 "register_operand" "d")
1454 (match_operand:SI 2 "register_operand" "=&a")])]
1457 gcc_assert (MEM_P (operands[0]));
1458 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1459 operands[0] = replace_equiv_address (operands[0], operands[2]);
1460 emit_move_insn (operands[0], operands[1]);
1465 ; movsf instruction pattern(s).
1468 (define_insn "movsf"
1469 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
1470 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
1484 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1485 (set_attr "type" "floads,floads,floads,fstores,fstores,
1486 lr,load,load,store,store,*")])
1489 ; movcc instruction pattern
1492 (define_insn "movcc"
1493 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1494 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1504 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1505 (set_attr "type" "lr,*,*,store,store,load,load")])
1508 ; Block move (MVC) patterns.
1512 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1513 (match_operand:BLK 1 "memory_operand" "Q"))
1514 (use (match_operand 2 "const_int_operand" "n"))]
1515 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1516 "mvc\t%O0(%2,%R0),%S1"
1517 [(set_attr "op_type" "SS")])
1520 [(set (match_operand 0 "memory_operand" "")
1521 (match_operand 1 "memory_operand" ""))]
1523 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1524 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1526 [(set (match_dup 0) (match_dup 1))
1527 (use (match_dup 2))])]
1529 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1530 operands[0] = adjust_address (operands[0], BLKmode, 0);
1531 operands[1] = adjust_address (operands[1], BLKmode, 0);
1536 [(set (match_operand:BLK 0 "memory_operand" "")
1537 (match_operand:BLK 1 "memory_operand" ""))
1538 (use (match_operand 2 "const_int_operand" ""))])
1540 [(set (match_operand:BLK 3 "memory_operand" "")
1541 (match_operand:BLK 4 "memory_operand" ""))
1542 (use (match_operand 5 "const_int_operand" ""))])]
1543 "s390_offset_p (operands[0], operands[3], operands[2])
1544 && s390_offset_p (operands[1], operands[4], operands[2])
1545 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1547 [(set (match_dup 6) (match_dup 7))
1548 (use (match_dup 8))])]
1549 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1550 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1551 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1555 ; load_multiple pattern(s).
1557 ; ??? Due to reload problems with replacing registers inside match_parallel
1558 ; we currently support load_multiple/store_multiple only after reload.
1561 (define_expand "load_multiple"
1562 [(match_par_dup 3 [(set (match_operand 0 "" "")
1563 (match_operand 1 "" ""))
1564 (use (match_operand 2 "" ""))])]
1567 enum machine_mode mode;
1573 /* Support only loading a constant number of fixed-point registers from
1574 memory and only bother with this if more than two */
1575 if (GET_CODE (operands[2]) != CONST_INT
1576 || INTVAL (operands[2]) < 2
1577 || INTVAL (operands[2]) > 16
1578 || GET_CODE (operands[1]) != MEM
1579 || GET_CODE (operands[0]) != REG
1580 || REGNO (operands[0]) >= 16)
1583 count = INTVAL (operands[2]);
1584 regno = REGNO (operands[0]);
1585 mode = GET_MODE (operands[0]);
1586 if (mode != SImode && mode != word_mode)
1589 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1592 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1594 from = XEXP (operands[1], 0);
1597 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1598 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1599 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1601 from = XEXP (XEXP (operands[1], 0), 0);
1602 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1609 from = force_reg (Pmode, XEXP (operands[1], 0));
1613 for (i = 0; i < count; i++)
1614 XVECEXP (operands[3], 0, i)
1615 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1616 change_address (operands[1], mode,
1617 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1620 (define_insn "*load_multiple_di"
1621 [(match_parallel 0 "load_multiple_operation"
1622 [(set (match_operand:DI 1 "register_operand" "=r")
1623 (match_operand:DI 2 "s_operand" "QS"))])]
1624 "reload_completed && word_mode == DImode"
1626 int words = XVECLEN (operands[0], 0);
1627 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1628 return "lmg\t%1,%0,%S2";
1630 [(set_attr "op_type" "RSY")
1631 (set_attr "type" "lm")])
1633 (define_insn "*load_multiple_si"
1634 [(match_parallel 0 "load_multiple_operation"
1635 [(set (match_operand:SI 1 "register_operand" "=r,r")
1636 (match_operand:SI 2 "s_operand" "Q,S"))])]
1639 int words = XVECLEN (operands[0], 0);
1640 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1641 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1643 [(set_attr "op_type" "RS,RSY")
1644 (set_attr "type" "lm")])
1647 ; store multiple pattern(s).
1650 (define_expand "store_multiple"
1651 [(match_par_dup 3 [(set (match_operand 0 "" "")
1652 (match_operand 1 "" ""))
1653 (use (match_operand 2 "" ""))])]
1656 enum machine_mode mode;
1662 /* Support only storing a constant number of fixed-point registers to
1663 memory and only bother with this if more than two. */
1664 if (GET_CODE (operands[2]) != CONST_INT
1665 || INTVAL (operands[2]) < 2
1666 || INTVAL (operands[2]) > 16
1667 || GET_CODE (operands[0]) != MEM
1668 || GET_CODE (operands[1]) != REG
1669 || REGNO (operands[1]) >= 16)
1672 count = INTVAL (operands[2]);
1673 regno = REGNO (operands[1]);
1674 mode = GET_MODE (operands[1]);
1675 if (mode != SImode && mode != word_mode)
1678 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1682 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1684 to = XEXP (operands[0], 0);
1687 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1688 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1689 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1691 to = XEXP (XEXP (operands[0], 0), 0);
1692 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1699 to = force_reg (Pmode, XEXP (operands[0], 0));
1703 for (i = 0; i < count; i++)
1704 XVECEXP (operands[3], 0, i)
1705 = gen_rtx_SET (VOIDmode,
1706 change_address (operands[0], mode,
1707 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1708 gen_rtx_REG (mode, regno + i));
1711 (define_insn "*store_multiple_di"
1712 [(match_parallel 0 "store_multiple_operation"
1713 [(set (match_operand:DI 1 "s_operand" "=QS")
1714 (match_operand:DI 2 "register_operand" "r"))])]
1715 "reload_completed && word_mode == DImode"
1717 int words = XVECLEN (operands[0], 0);
1718 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1719 return "stmg\t%2,%0,%S1";
1721 [(set_attr "op_type" "RSY")
1722 (set_attr "type" "stm")])
1725 (define_insn "*store_multiple_si"
1726 [(match_parallel 0 "store_multiple_operation"
1727 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1728 (match_operand:SI 2 "register_operand" "r,r"))])]
1731 int words = XVECLEN (operands[0], 0);
1732 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1733 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1735 [(set_attr "op_type" "RS,RSY")
1736 (set_attr "type" "stm")])
1739 ;; String instructions.
1742 (define_insn "*execute"
1743 [(match_parallel 0 ""
1744 [(unspec [(match_operand 1 "register_operand" "a")
1745 (match_operand:BLK 2 "memory_operand" "R")
1746 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1747 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1748 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1750 [(set_attr "op_type" "RX")
1751 (set_attr "type" "cs")])
1755 ; strlenM instruction pattern(s).
1758 (define_expand "strlendi"
1759 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1762 (unspec:DI [(const_int 0)
1763 (match_operand:BLK 1 "memory_operand" "")
1765 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1766 (clobber (scratch:DI))
1767 (clobber (reg:CC 33))])
1769 [(set (match_operand:DI 0 "register_operand" "")
1770 (minus:DI (match_dup 4) (match_dup 5)))
1771 (clobber (reg:CC 33))])]
1774 operands[4] = gen_reg_rtx (DImode);
1775 operands[5] = gen_reg_rtx (DImode);
1776 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1777 operands[1] = replace_equiv_address (operands[1], operands[5]);
1780 (define_insn "*strlendi"
1781 [(set (match_operand:DI 0 "register_operand" "=a")
1782 (unspec:DI [(match_operand:DI 2 "general_operand" "0")
1783 (mem:BLK (match_operand:DI 3 "register_operand" "1"))
1785 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1786 (clobber (match_scratch:DI 1 "=a"))
1787 (clobber (reg:CC 33))]
1789 "srst\t%0,%1\;jo\t.-4"
1790 [(set_attr "length" "8")
1791 (set_attr "type" "vs")])
1793 (define_expand "strlensi"
1794 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1797 (unspec:SI [(const_int 0)
1798 (match_operand:BLK 1 "memory_operand" "")
1800 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1801 (clobber (scratch:SI))
1802 (clobber (reg:CC 33))])
1804 [(set (match_operand:SI 0 "register_operand" "")
1805 (minus:SI (match_dup 4) (match_dup 5)))
1806 (clobber (reg:CC 33))])]
1809 operands[4] = gen_reg_rtx (SImode);
1810 operands[5] = gen_reg_rtx (SImode);
1811 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1812 operands[1] = replace_equiv_address (operands[1], operands[5]);
1815 (define_insn "*strlensi"
1816 [(set (match_operand:SI 0 "register_operand" "=a")
1817 (unspec:SI [(match_operand:SI 2 "general_operand" "0")
1818 (mem:BLK (match_operand:SI 3 "register_operand" "1"))
1820 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1821 (clobber (match_scratch:SI 1 "=a"))
1822 (clobber (reg:CC 33))]
1824 "srst\t%0,%1\;jo\t.-4"
1825 [(set_attr "length" "8")
1826 (set_attr "type" "vs")])
1829 ; movmemM instruction pattern(s).
1832 (define_expand "movmemdi"
1833 [(set (match_operand:BLK 0 "memory_operand" "")
1834 (match_operand:BLK 1 "memory_operand" ""))
1835 (use (match_operand:DI 2 "general_operand" ""))
1836 (match_operand 3 "" "")]
1838 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1840 (define_expand "movmemsi"
1841 [(set (match_operand:BLK 0 "memory_operand" "")
1842 (match_operand:BLK 1 "memory_operand" ""))
1843 (use (match_operand:SI 2 "general_operand" ""))
1844 (match_operand 3 "" "")]
1846 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1848 ; Move a block that is up to 256 bytes in length.
1849 ; The block length is taken as (operands[2] % 256) + 1.
1851 (define_expand "movmem_short"
1853 [(set (match_operand:BLK 0 "memory_operand" "")
1854 (match_operand:BLK 1 "memory_operand" ""))
1855 (use (match_operand 2 "nonmemory_operand" ""))
1856 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1857 (clobber (match_dup 3))])]
1859 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1861 (define_insn "*movmem_short"
1862 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1863 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1864 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1865 (use (match_operand 3 "immediate_operand" "X,R,X"))
1866 (clobber (match_scratch 4 "=X,X,&a"))]
1867 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1868 && GET_MODE (operands[4]) == Pmode"
1870 [(set_attr "type" "cs")])
1873 [(set (match_operand:BLK 0 "memory_operand" "")
1874 (match_operand:BLK 1 "memory_operand" ""))
1875 (use (match_operand 2 "const_int_operand" ""))
1876 (use (match_operand 3 "immediate_operand" ""))
1877 (clobber (scratch))]
1880 [(set (match_dup 0) (match_dup 1))
1881 (use (match_dup 2))])]
1882 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1885 [(set (match_operand:BLK 0 "memory_operand" "")
1886 (match_operand:BLK 1 "memory_operand" ""))
1887 (use (match_operand 2 "register_operand" ""))
1888 (use (match_operand 3 "memory_operand" ""))
1889 (clobber (scratch))]
1892 [(unspec [(match_dup 2) (match_dup 3)
1893 (const_int 0)] UNSPEC_EXECUTE)
1894 (set (match_dup 0) (match_dup 1))
1895 (use (const_int 1))])]
1899 [(set (match_operand:BLK 0 "memory_operand" "")
1900 (match_operand:BLK 1 "memory_operand" ""))
1901 (use (match_operand 2 "register_operand" ""))
1902 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1903 (clobber (match_operand 3 "register_operand" ""))]
1904 "reload_completed && TARGET_CPU_ZARCH"
1905 [(set (match_dup 3) (label_ref (match_dup 4)))
1907 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1908 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1909 (set (match_dup 0) (match_dup 1))
1910 (use (const_int 1))])]
1911 "operands[4] = gen_label_rtx ();")
1913 ; Move a block of arbitrary length.
1915 (define_expand "movmem_long"
1917 [(clobber (match_dup 2))
1918 (clobber (match_dup 3))
1919 (set (match_operand:BLK 0 "memory_operand" "")
1920 (match_operand:BLK 1 "memory_operand" ""))
1921 (use (match_operand 2 "general_operand" ""))
1923 (clobber (reg:CC 33))])]
1926 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1927 rtx reg0 = gen_reg_rtx (dword_mode);
1928 rtx reg1 = gen_reg_rtx (dword_mode);
1929 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1930 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1931 rtx len0 = gen_lowpart (Pmode, reg0);
1932 rtx len1 = gen_lowpart (Pmode, reg1);
1934 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1935 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1936 emit_move_insn (len0, operands[2]);
1938 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1939 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1940 emit_move_insn (len1, operands[2]);
1942 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1943 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1948 (define_insn "*movmem_long_64"
1949 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1950 (clobber (match_operand:TI 1 "register_operand" "=d"))
1951 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1952 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1955 (clobber (reg:CC 33))]
1957 "mvcle\t%0,%1,0\;jo\t.-4"
1958 [(set_attr "length" "8")
1959 (set_attr "type" "vs")])
1961 (define_insn "*movmem_long_31"
1962 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1963 (clobber (match_operand:DI 1 "register_operand" "=d"))
1964 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1965 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1968 (clobber (reg:CC 33))]
1970 "mvcle\t%0,%1,0\;jo\t.-4"
1971 [(set_attr "length" "8")
1972 (set_attr "type" "vs")])
1975 ; clrmemM instruction pattern(s).
1978 (define_expand "clrmemdi"
1979 [(set (match_operand:BLK 0 "memory_operand" "")
1981 (use (match_operand:DI 1 "general_operand" ""))
1982 (match_operand 2 "" "")]
1984 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1986 (define_expand "clrmemsi"
1987 [(set (match_operand:BLK 0 "memory_operand" "")
1989 (use (match_operand:SI 1 "general_operand" ""))
1990 (match_operand 2 "" "")]
1992 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1994 ; Clear a block that is up to 256 bytes in length.
1995 ; The block length is taken as (operands[1] % 256) + 1.
1997 (define_expand "clrmem_short"
1999 [(set (match_operand:BLK 0 "memory_operand" "")
2001 (use (match_operand 1 "nonmemory_operand" ""))
2002 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2003 (clobber (match_dup 2))
2004 (clobber (reg:CC 33))])]
2006 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2008 (define_insn "*clrmem_short"
2009 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2011 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2012 (use (match_operand 2 "immediate_operand" "X,R,X"))
2013 (clobber (match_scratch 3 "=X,X,&a"))
2014 (clobber (reg:CC 33))]
2015 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2016 && GET_MODE (operands[3]) == Pmode"
2018 [(set_attr "type" "cs")])
2021 [(set (match_operand:BLK 0 "memory_operand" "")
2023 (use (match_operand 1 "const_int_operand" ""))
2024 (use (match_operand 2 "immediate_operand" ""))
2026 (clobber (reg:CC 33))]
2029 [(set (match_dup 0) (const_int 0))
2031 (clobber (reg:CC 33))])]
2032 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2035 [(set (match_operand:BLK 0 "memory_operand" "")
2037 (use (match_operand 1 "register_operand" ""))
2038 (use (match_operand 2 "memory_operand" ""))
2040 (clobber (reg:CC 33))]
2043 [(unspec [(match_dup 1) (match_dup 2)
2044 (const_int 0)] UNSPEC_EXECUTE)
2045 (set (match_dup 0) (const_int 0))
2047 (clobber (reg:CC 33))])]
2051 [(set (match_operand:BLK 0 "memory_operand" "")
2053 (use (match_operand 1 "register_operand" ""))
2054 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2055 (clobber (match_operand 2 "register_operand" ""))
2056 (clobber (reg:CC 33))]
2057 "reload_completed && TARGET_CPU_ZARCH"
2058 [(set (match_dup 2) (label_ref (match_dup 3)))
2060 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2061 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2062 (set (match_dup 0) (const_int 0))
2064 (clobber (reg:CC 33))])]
2065 "operands[3] = gen_label_rtx ();")
2067 ; Clear a block of arbitrary length.
2069 (define_expand "clrmem_long"
2071 [(clobber (match_dup 1))
2072 (set (match_operand:BLK 0 "memory_operand" "")
2074 (use (match_operand 1 "general_operand" ""))
2076 (clobber (reg:CC 33))])]
2079 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2080 rtx reg0 = gen_reg_rtx (dword_mode);
2081 rtx reg1 = gen_reg_rtx (dword_mode);
2082 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2083 rtx len0 = gen_lowpart (Pmode, reg0);
2085 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2086 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2087 emit_move_insn (len0, operands[1]);
2089 emit_move_insn (reg1, const0_rtx);
2091 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2096 (define_insn "*clrmem_long_64"
2097 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2098 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2101 (use (match_operand:TI 1 "register_operand" "d"))
2102 (clobber (reg:CC 33))]
2104 "mvcle\t%0,%1,0\;jo\t.-4"
2105 [(set_attr "length" "8")
2106 (set_attr "type" "vs")])
2108 (define_insn "*clrmem_long_31"
2109 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2110 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2113 (use (match_operand:DI 1 "register_operand" "d"))
2114 (clobber (reg:CC 33))]
2116 "mvcle\t%0,%1,0\;jo\t.-4"
2117 [(set_attr "length" "8")
2118 (set_attr "type" "vs")])
2121 ; cmpmemM instruction pattern(s).
2124 (define_expand "cmpmemsi"
2125 [(set (match_operand:SI 0 "register_operand" "")
2126 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2127 (match_operand:BLK 2 "memory_operand" "") ) )
2128 (use (match_operand:SI 3 "general_operand" ""))
2129 (use (match_operand:SI 4 "" ""))]
2131 "s390_expand_cmpmem (operands[0], operands[1],
2132 operands[2], operands[3]); DONE;")
2134 ; Compare a block that is up to 256 bytes in length.
2135 ; The block length is taken as (operands[2] % 256) + 1.
2137 (define_expand "cmpmem_short"
2140 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2141 (match_operand:BLK 1 "memory_operand" "")))
2142 (use (match_operand 2 "nonmemory_operand" ""))
2143 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2144 (clobber (match_dup 3))])]
2146 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2148 (define_insn "*cmpmem_short"
2150 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2151 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2152 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2153 (use (match_operand 3 "immediate_operand" "X,R,X"))
2154 (clobber (match_scratch 4 "=X,X,&a"))]
2155 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2156 && GET_MODE (operands[4]) == Pmode"
2158 [(set_attr "type" "cs")])
2162 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2163 (match_operand:BLK 1 "memory_operand" "")))
2164 (use (match_operand 2 "const_int_operand" ""))
2165 (use (match_operand 3 "immediate_operand" ""))
2166 (clobber (scratch))]
2169 [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2170 (use (match_dup 2))])]
2171 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2175 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2176 (match_operand:BLK 1 "memory_operand" "")))
2177 (use (match_operand 2 "register_operand" ""))
2178 (use (match_operand 3 "memory_operand" ""))
2179 (clobber (scratch))]
2182 [(unspec [(match_dup 2) (match_dup 3)
2183 (const_int 0)] UNSPEC_EXECUTE)
2184 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2185 (use (const_int 1))])]
2190 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2191 (match_operand:BLK 1 "memory_operand" "")))
2192 (use (match_operand 2 "register_operand" ""))
2193 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2194 (clobber (match_operand 3 "register_operand" ""))]
2195 "reload_completed && TARGET_CPU_ZARCH"
2196 [(set (match_dup 3) (label_ref (match_dup 4)))
2198 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2199 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2200 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2201 (use (const_int 1))])]
2202 "operands[4] = gen_label_rtx ();")
2204 ; Compare a block of arbitrary length.
2206 (define_expand "cmpmem_long"
2208 [(clobber (match_dup 2))
2209 (clobber (match_dup 3))
2211 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2212 (match_operand:BLK 1 "memory_operand" "")))
2213 (use (match_operand 2 "general_operand" ""))
2214 (use (match_dup 3))])]
2217 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2218 rtx reg0 = gen_reg_rtx (dword_mode);
2219 rtx reg1 = gen_reg_rtx (dword_mode);
2220 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2221 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2222 rtx len0 = gen_lowpart (Pmode, reg0);
2223 rtx len1 = gen_lowpart (Pmode, reg1);
2225 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2226 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2227 emit_move_insn (len0, operands[2]);
2229 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2230 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2231 emit_move_insn (len1, operands[2]);
2233 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2234 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2239 (define_insn "*cmpmem_long_64"
2240 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2241 (clobber (match_operand:TI 1 "register_operand" "=d"))
2243 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2244 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2246 (use (match_dup 3))]
2248 "clcle\t%0,%1,0\;jo\t.-4"
2249 [(set_attr "length" "8")
2250 (set_attr "type" "vs")])
2252 (define_insn "*cmpmem_long_31"
2253 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2254 (clobber (match_operand:DI 1 "register_operand" "=d"))
2256 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2257 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2259 (use (match_dup 3))]
2261 "clcle\t%0,%1,0\;jo\t.-4"
2262 [(set_attr "length" "8")
2263 (set_attr "type" "vs")])
2265 ; Convert CCUmode condition code to integer.
2266 ; Result is zero if EQ, positive if LTU, negative if GTU.
2268 (define_insn_and_split "cmpint"
2269 [(set (match_operand:SI 0 "register_operand" "=d")
2270 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2272 (clobber (reg:CC 33))]
2276 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2278 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2279 (clobber (reg:CC 33))])])
2281 (define_insn_and_split "*cmpint_cc"
2283 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2286 (set (match_operand:SI 0 "register_operand" "=d")
2287 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2288 "s390_match_ccmode (insn, CCSmode)"
2290 "&& reload_completed"
2291 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2293 [(set (match_dup 2) (match_dup 3))
2294 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2296 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2297 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2298 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2301 (define_insn_and_split "*cmpint_sign"
2302 [(set (match_operand:DI 0 "register_operand" "=d")
2303 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2305 (clobber (reg:CC 33))]
2308 "&& reload_completed"
2309 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2311 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2312 (clobber (reg:CC 33))])])
2314 (define_insn_and_split "*cmpint_sign_cc"
2316 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2317 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2319 (const_int 32)) (const_int 32))
2321 (set (match_operand:DI 0 "register_operand" "=d")
2322 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2323 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2325 "&& reload_completed"
2326 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2328 [(set (match_dup 2) (match_dup 3))
2329 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2331 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2332 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2333 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2338 ;;- Conversion instructions.
2341 (define_insn "*sethighqisi"
2342 [(set (match_operand:SI 0 "register_operand" "=d,d")
2343 (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2344 (clobber (reg:CC 33))]
2349 [(set_attr "op_type" "RS,RSY")])
2351 (define_insn "*sethighhisi"
2352 [(set (match_operand:SI 0 "register_operand" "=d,d")
2353 (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2354 (clobber (reg:CC 33))]
2359 [(set_attr "op_type" "RS,RSY")])
2361 (define_insn "*sethighqidi_64"
2362 [(set (match_operand:DI 0 "register_operand" "=d")
2363 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2364 (clobber (reg:CC 33))]
2367 [(set_attr "op_type" "RSY")])
2369 (define_insn "*sethighqidi_31"
2370 [(set (match_operand:DI 0 "register_operand" "=d,d")
2371 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2372 (clobber (reg:CC 33))]
2377 [(set_attr "op_type" "RS,RSY")])
2379 (define_insn_and_split "*extractqi"
2380 [(set (match_operand:SI 0 "register_operand" "=d")
2381 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2382 (match_operand 2 "const_int_operand" "n")
2384 (clobber (reg:CC 33))]
2386 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2388 "&& reload_completed"
2390 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2391 (clobber (reg:CC 33))])
2392 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2394 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2395 operands[1] = change_address (operands[1], QImode, 0);
2398 (define_insn_and_split "*extracthi"
2399 [(set (match_operand:SI 0 "register_operand" "=d")
2400 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2401 (match_operand 2 "const_int_operand" "n")
2403 (clobber (reg:CC 33))]
2405 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2407 "&& reload_completed"
2409 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2410 (clobber (reg:CC 33))])
2411 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2413 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2414 operands[1] = change_address (operands[1], HImode, 0);
2418 ; extendsidi2 instruction pattern(s).
2421 (define_expand "extendsidi2"
2422 [(set (match_operand:DI 0 "register_operand" "")
2423 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2429 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2430 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2431 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2432 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2438 (define_insn "*extendsidi2"
2439 [(set (match_operand:DI 0 "register_operand" "=d,d")
2440 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2445 [(set_attr "op_type" "RRE,RXY")])
2448 ; extendhidi2 instruction pattern(s).
2451 (define_expand "extendhidi2"
2452 [(set (match_operand:DI 0 "register_operand" "")
2453 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2459 rtx tmp = gen_reg_rtx (SImode);
2460 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2461 emit_insn (gen_extendsidi2 (operands[0], tmp));
2466 operands[1] = gen_lowpart (DImode, operands[1]);
2467 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2468 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2474 (define_insn "*extendhidi2"
2475 [(set (match_operand:DI 0 "register_operand" "=d")
2476 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2479 [(set_attr "op_type" "RXY")])
2482 ; extendqidi2 instruction pattern(s).
2485 (define_expand "extendqidi2"
2486 [(set (match_operand:DI 0 "register_operand" "")
2487 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2493 rtx tmp = gen_reg_rtx (SImode);
2494 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2495 emit_insn (gen_extendsidi2 (operands[0], tmp));
2500 operands[1] = gen_lowpart (DImode, operands[1]);
2501 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2502 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2508 (define_insn "*extendqidi2"
2509 [(set (match_operand:DI 0 "register_operand" "=d")
2510 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2511 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2513 [(set_attr "op_type" "RXY")])
2515 (define_insn_and_split "*extendqidi2_short_displ"
2516 [(set (match_operand:DI 0 "register_operand" "=d")
2517 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2518 (clobber (reg:CC 33))]
2519 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2521 "&& reload_completed"
2523 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2524 (clobber (reg:CC 33))])
2526 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2527 (clobber (reg:CC 33))])]
2531 ; extendhisi2 instruction pattern(s).
2534 (define_expand "extendhisi2"
2535 [(set (match_operand:SI 0 "register_operand" "")
2536 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2540 operands[1] = gen_lowpart (SImode, operands[1]);
2541 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2542 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2547 (define_insn "*extendhisi2"
2548 [(set (match_operand:SI 0 "register_operand" "=d,d")
2549 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2554 [(set_attr "op_type" "RX,RXY")])
2557 ; extendqisi2 instruction pattern(s).
2560 (define_expand "extendqisi2"
2561 [(set (match_operand:SI 0 "register_operand" "")
2562 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2566 operands[1] = gen_lowpart (SImode, operands[1]);
2567 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2568 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2573 (define_insn "*extendqisi2"
2574 [(set (match_operand:SI 0 "register_operand" "=d")
2575 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2576 "TARGET_LONG_DISPLACEMENT"
2578 [(set_attr "op_type" "RXY")])
2580 (define_insn_and_split "*extendqisi2_short_displ"
2581 [(set (match_operand:SI 0 "register_operand" "=d")
2582 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2583 (clobber (reg:CC 33))]
2584 "!TARGET_LONG_DISPLACEMENT"
2586 "&& reload_completed"
2588 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2589 (clobber (reg:CC 33))])
2591 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2592 (clobber (reg:CC 33))])]
2596 ; extendqihi2 instruction pattern(s).
2601 ; zero_extendsidi2 instruction pattern(s).
2604 (define_expand "zero_extendsidi2"
2605 [(set (match_operand:DI 0 "register_operand" "")
2606 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2612 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2613 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2614 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2620 (define_insn "*zero_extendsidi2"
2621 [(set (match_operand:DI 0 "register_operand" "=d,d")
2622 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2627 [(set_attr "op_type" "RRE,RXY")])
2630 ; zero_extendhidi2 instruction pattern(s).
2633 (define_expand "zero_extendhidi2"
2634 [(set (match_operand:DI 0 "register_operand" "")
2635 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2641 rtx tmp = gen_reg_rtx (SImode);
2642 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2643 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2648 operands[1] = gen_lowpart (DImode, operands[1]);
2649 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2650 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2656 (define_insn "*zero_extendhidi2"
2657 [(set (match_operand:DI 0 "register_operand" "=d")
2658 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2661 [(set_attr "op_type" "RXY")])
2664 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2667 (define_insn "*llgt_sidi"
2668 [(set (match_operand:DI 0 "register_operand" "=d")
2669 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2670 (const_int 2147483647)))]
2673 [(set_attr "op_type" "RXE")])
2675 (define_insn_and_split "*llgt_sidi_split"
2676 [(set (match_operand:DI 0 "register_operand" "=d")
2677 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2678 (const_int 2147483647)))
2679 (clobber (reg:CC 33))]
2682 "&& reload_completed"
2684 (and:DI (subreg:DI (match_dup 1) 0)
2685 (const_int 2147483647)))]
2688 (define_insn "*llgt_sisi"
2689 [(set (match_operand:SI 0 "register_operand" "=d,d")
2690 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2691 (const_int 2147483647)))]
2696 [(set_attr "op_type" "RRE,RXE")])
2699 [(set (match_operand:SI 0 "register_operand" "")
2700 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2701 (const_int 2147483647)))
2702 (clobber (reg:CC 33))]
2703 "TARGET_64BIT && reload_completed"
2705 (and:SI (match_dup 1)
2706 (const_int 2147483647)))]
2709 (define_insn "*llgt_didi"
2710 [(set (match_operand:DI 0 "register_operand" "=d,d")
2711 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2712 (const_int 2147483647)))]
2717 [(set_attr "op_type" "RRE,RXE")])
2720 [(set (match_operand:DI 0 "register_operand" "")
2721 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
2722 (const_int 2147483647)))
2723 (clobber (reg:CC 33))]
2724 "TARGET_64BIT && reload_completed"
2726 (and:DI (match_dup 1)
2727 (const_int 2147483647)))]
2731 ; zero_extendqidi2 instruction pattern(s)
2734 (define_expand "zero_extendqidi2"
2735 [(set (match_operand:DI 0 "register_operand" "")
2736 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2742 rtx tmp = gen_reg_rtx (SImode);
2743 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2744 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2749 operands[1] = gen_lowpart (DImode, operands[1]);
2750 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2751 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2757 (define_insn "*zero_extendqidi2"
2758 [(set (match_operand:DI 0 "register_operand" "=d")
2759 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2762 [(set_attr "op_type" "RXY")])
2765 ; zero_extendhisi2 instruction pattern(s).
2768 (define_expand "zero_extendhisi2"
2769 [(set (match_operand:SI 0 "register_operand" "")
2770 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2774 operands[1] = gen_lowpart (SImode, operands[1]);
2775 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2780 (define_insn "*zero_extendhisi2_64"
2781 [(set (match_operand:SI 0 "register_operand" "=d")
2782 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2785 [(set_attr "op_type" "RXY")])
2787 (define_insn_and_split "*zero_extendhisi2_31"
2788 [(set (match_operand:SI 0 "register_operand" "=&d")
2789 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2790 (clobber (reg:CC 33))]
2793 "&& reload_completed"
2794 [(set (match_dup 0) (const_int 0))
2796 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2797 (clobber (reg:CC 33))])]
2798 "operands[2] = gen_lowpart (HImode, operands[0]);")
2801 ; zero_extendqisi2 instruction pattern(s).
2804 (define_expand "zero_extendqisi2"
2805 [(set (match_operand:SI 0 "register_operand" "")
2806 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2810 operands[1] = gen_lowpart (SImode, operands[1]);
2811 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2816 (define_insn "*zero_extendqisi2_64"
2817 [(set (match_operand:SI 0 "register_operand" "=d")
2818 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2821 [(set_attr "op_type" "RXY")])
2823 (define_insn_and_split "*zero_extendqisi2_31"
2824 [(set (match_operand:SI 0 "register_operand" "=&d")
2825 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2828 "&& reload_completed"
2829 [(set (match_dup 0) (const_int 0))
2830 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2831 "operands[2] = gen_lowpart (QImode, operands[0]);")
2834 ; zero_extendqihi2 instruction pattern(s).
2837 (define_expand "zero_extendqihi2"
2838 [(set (match_operand:HI 0 "register_operand" "")
2839 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2843 operands[1] = gen_lowpart (HImode, operands[1]);
2844 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2849 (define_insn "*zero_extendqihi2_64"
2850 [(set (match_operand:HI 0 "register_operand" "=d")
2851 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2854 [(set_attr "op_type" "RXY")])
2856 (define_insn_and_split "*zero_extendqihi2_31"
2857 [(set (match_operand:HI 0 "register_operand" "=&d")
2858 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2861 "&& reload_completed"
2862 [(set (match_dup 0) (const_int 0))
2863 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2864 "operands[2] = gen_lowpart (QImode, operands[0]);")
2868 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2871 (define_expand "fixuns_truncdfdi2"
2872 [(set (match_operand:DI 0 "register_operand" "")
2873 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2874 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2876 rtx label1 = gen_label_rtx ();
2877 rtx label2 = gen_label_rtx ();
2878 rtx temp = gen_reg_rtx (DFmode);
2879 operands[1] = force_reg (DFmode, operands[1]);
2881 emit_insn (gen_cmpdf (operands[1],
2882 CONST_DOUBLE_FROM_REAL_VALUE (
2883 REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
2884 emit_jump_insn (gen_blt (label1));
2885 emit_insn (gen_subdf3 (temp, operands[1],
2886 CONST_DOUBLE_FROM_REAL_VALUE (
2887 REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
2888 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2891 emit_label (label1);
2892 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2893 emit_label (label2);
2897 (define_expand "fix_truncdfdi2"
2898 [(set (match_operand:DI 0 "register_operand" "")
2899 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2900 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2902 operands[1] = force_reg (DFmode, operands[1]);
2903 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2907 (define_insn "fix_truncdfdi2_ieee"
2908 [(set (match_operand:DI 0 "register_operand" "=d")
2909 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2910 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2911 (clobber (reg:CC 33))]
2912 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2914 [(set_attr "op_type" "RRE")
2915 (set_attr "type" "ftoi")])
2918 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2921 (define_expand "fixuns_truncdfsi2"
2922 [(set (match_operand:SI 0 "register_operand" "")
2923 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2924 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2926 rtx label1 = gen_label_rtx ();
2927 rtx label2 = gen_label_rtx ();
2928 rtx temp = gen_reg_rtx (DFmode);
2930 operands[1] = force_reg (DFmode,operands[1]);
2931 emit_insn (gen_cmpdf (operands[1],
2932 CONST_DOUBLE_FROM_REAL_VALUE (
2933 REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
2934 emit_jump_insn (gen_blt (label1));
2935 emit_insn (gen_subdf3 (temp, operands[1],
2936 CONST_DOUBLE_FROM_REAL_VALUE (
2937 REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
2938 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2941 emit_label (label1);
2942 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2943 emit_label (label2);
2947 (define_expand "fix_truncdfsi2"
2948 [(set (match_operand:SI 0 "register_operand" "")
2949 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2952 if (TARGET_IBM_FLOAT)
2954 /* This is the algorithm from POP chapter A.5.7.2. */
2956 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2957 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2958 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2960 operands[1] = force_reg (DFmode, operands[1]);
2961 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2962 two31r, two32, temp));
2966 operands[1] = force_reg (DFmode, operands[1]);
2967 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2973 (define_insn "fix_truncdfsi2_ieee"
2974 [(set (match_operand:SI 0 "register_operand" "=d")
2975 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2976 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2977 (clobber (reg:CC 33))]
2978 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2980 [(set_attr "op_type" "RRE")
2981 (set_attr "type" "ftoi")])
2983 (define_insn "fix_truncdfsi2_ibm"
2984 [(set (match_operand:SI 0 "register_operand" "=d")
2985 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2986 (use (match_operand:DI 2 "immediate_operand" "m"))
2987 (use (match_operand:DI 3 "immediate_operand" "m"))
2988 (use (match_operand:BLK 4 "memory_operand" "m"))
2989 (clobber (reg:CC 33))]
2990 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2992 output_asm_insn ("sd\t%1,%2", operands);
2993 output_asm_insn ("aw\t%1,%3", operands);
2994 output_asm_insn ("std\t%1,%4", operands);
2995 output_asm_insn ("xi\t%N4,128", operands);
2998 [(set_attr "length" "20")])
3001 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
3004 (define_expand "fixuns_truncsfdi2"
3005 [(set (match_operand:DI 0 "register_operand" "")
3006 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
3007 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3009 rtx label1 = gen_label_rtx ();
3010 rtx label2 = gen_label_rtx ();
3011 rtx temp = gen_reg_rtx (SFmode);
3013 operands[1] = force_reg (SFmode, operands[1]);
3014 emit_insn (gen_cmpsf (operands[1],
3015 CONST_DOUBLE_FROM_REAL_VALUE (
3016 REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
3017 emit_jump_insn (gen_blt (label1));
3019 emit_insn (gen_subsf3 (temp, operands[1],
3020 CONST_DOUBLE_FROM_REAL_VALUE (
3021 REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
3022 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
3025 emit_label (label1);
3026 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
3027 emit_label (label2);
3031 (define_expand "fix_truncsfdi2"
3032 [(set (match_operand:DI 0 "register_operand" "")
3033 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
3034 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3036 operands[1] = force_reg (SFmode, operands[1]);
3037 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
3041 (define_insn "fix_truncsfdi2_ieee"
3042 [(set (match_operand:DI 0 "register_operand" "=d")
3043 (fix:DI (match_operand:SF 1 "register_operand" "f")))
3044 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3045 (clobber (reg:CC 33))]
3046 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3048 [(set_attr "op_type" "RRE")
3049 (set_attr "type" "ftoi")])
3052 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
3055 (define_expand "fixuns_truncsfsi2"
3056 [(set (match_operand:SI 0 "register_operand" "")
3057 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
3058 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3060 rtx label1 = gen_label_rtx ();
3061 rtx label2 = gen_label_rtx ();
3062 rtx temp = gen_reg_rtx (SFmode);
3064 operands[1] = force_reg (SFmode, operands[1]);
3065 emit_insn (gen_cmpsf (operands[1],
3066 CONST_DOUBLE_FROM_REAL_VALUE (
3067 REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
3068 emit_jump_insn (gen_blt (label1));
3069 emit_insn (gen_subsf3 (temp, operands[1],
3070 CONST_DOUBLE_FROM_REAL_VALUE (
3071 REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
3072 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
3075 emit_label (label1);
3076 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3077 emit_label (label2);
3081 (define_expand "fix_truncsfsi2"
3082 [(set (match_operand:SI 0 "register_operand" "")
3083 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3086 if (TARGET_IBM_FLOAT)
3088 /* Convert to DFmode and then use the POP algorithm. */
3089 rtx temp = gen_reg_rtx (DFmode);
3090 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3091 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3095 operands[1] = force_reg (SFmode, operands[1]);
3096 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3102 (define_insn "fix_truncsfsi2_ieee"
3103 [(set (match_operand:SI 0 "register_operand" "=d")
3104 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3105 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3106 (clobber (reg:CC 33))]
3107 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3109 [(set_attr "op_type" "RRE")
3110 (set_attr "type" "ftoi")])
3113 ; floatdidf2 instruction pattern(s).
3116 (define_insn "floatdidf2"
3117 [(set (match_operand:DF 0 "register_operand" "=f")
3118 (float:DF (match_operand:DI 1 "register_operand" "d")))]
3119 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3121 [(set_attr "op_type" "RRE")
3122 (set_attr "type" "itof" )])
3125 ; floatdisf2 instruction pattern(s).
3128 (define_insn "floatdisf2"
3129 [(set (match_operand:SF 0 "register_operand" "=f")
3130 (float:SF (match_operand:DI 1 "register_operand" "d")))]
3131 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3133 [(set_attr "op_type" "RRE")
3134 (set_attr "type" "itof" )])
3137 ; floatsidf2 instruction pattern(s).
3140 (define_expand "floatsidf2"
3141 [(set (match_operand:DF 0 "register_operand" "")
3142 (float:DF (match_operand:SI 1 "register_operand" "")))]
3145 if (TARGET_IBM_FLOAT)
3147 /* This is the algorithm from POP chapter A.5.7.1. */
3149 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3150 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3152 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3157 (define_insn "floatsidf2_ieee"
3158 [(set (match_operand:DF 0 "register_operand" "=f")
3159 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3160 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3162 [(set_attr "op_type" "RRE")
3163 (set_attr "type" "itof" )])
3165 (define_insn "floatsidf2_ibm"
3166 [(set (match_operand:DF 0 "register_operand" "=f")
3167 (float:DF (match_operand:SI 1 "register_operand" "d")))
3168 (use (match_operand:DI 2 "immediate_operand" "m"))
3169 (use (match_operand:BLK 3 "memory_operand" "m"))
3170 (clobber (reg:CC 33))]
3171 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3173 output_asm_insn ("st\t%1,%N3", operands);
3174 output_asm_insn ("xi\t%N3,128", operands);
3175 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3176 output_asm_insn ("ld\t%0,%3", operands);
3179 [(set_attr "length" "20")])
3182 ; floatsisf2 instruction pattern(s).
3185 (define_expand "floatsisf2"
3186 [(set (match_operand:SF 0 "register_operand" "")
3187 (float:SF (match_operand:SI 1 "register_operand" "")))]
3190 if (TARGET_IBM_FLOAT)
3192 /* Use the POP algorithm to convert to DFmode and then truncate. */
3193 rtx temp = gen_reg_rtx (DFmode);
3194 emit_insn (gen_floatsidf2 (temp, operands[1]));
3195 emit_insn (gen_truncdfsf2 (operands[0], temp));
3200 (define_insn "floatsisf2_ieee"
3201 [(set (match_operand:SF 0 "register_operand" "=f")
3202 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3203 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3205 [(set_attr "op_type" "RRE")
3206 (set_attr "type" "itof" )])
3209 ; truncdfsf2 instruction pattern(s).
3212 (define_expand "truncdfsf2"
3213 [(set (match_operand:SF 0 "register_operand" "")
3214 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3218 (define_insn "truncdfsf2_ieee"
3219 [(set (match_operand:SF 0 "register_operand" "=f")
3220 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3221 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3223 [(set_attr "op_type" "RRE")])
3225 (define_insn "truncdfsf2_ibm"
3226 [(set (match_operand:SF 0 "register_operand" "=f,f")
3227 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3228 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3232 [(set_attr "op_type" "RR,RX")
3233 (set_attr "type" "floads,floads")])
3236 ; extendsfdf2 instruction pattern(s).
3239 (define_expand "extendsfdf2"
3240 [(set (match_operand:DF 0 "register_operand" "")
3241 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3244 if (TARGET_IBM_FLOAT)
3246 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3251 (define_insn "extendsfdf2_ieee"
3252 [(set (match_operand:DF 0 "register_operand" "=f,f")
3253 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3254 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3258 [(set_attr "op_type" "RRE,RXE")
3259 (set_attr "type" "floads,floads")])
3261 (define_insn "extendsfdf2_ibm"
3262 [(set (match_operand:DF 0 "register_operand" "=f,f")
3263 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3264 (clobber (reg:CC 33))]
3265 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3267 sdr\t%0,%0\;ler\t%0,%1
3268 sdr\t%0,%0\;le\t%0,%1"
3269 [(set_attr "length" "4,6")
3270 (set_attr "type" "floads,floads")])
3274 ;; ARITHMETIC OPERATIONS
3276 ; arithmetic operations set the ConditionCode,
3277 ; because of unpredictable Bits in Register for Halfword and Byte
3278 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3281 ;;- Add instructions.
3285 ; addti3 instruction pattern(s).
3288 (define_insn_and_split "addti3"
3289 [(set (match_operand:TI 0 "register_operand" "=&d")
3290 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3291 (match_operand:TI 2 "general_operand" "do") ) )
3292 (clobber (reg:CC 33))]
3295 "&& reload_completed"
3298 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3300 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3302 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3303 (ltu:DI (reg:CCL1 33) (const_int 0))))
3304 (clobber (reg:CC 33))])]
3305 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3306 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3307 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3308 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3309 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3310 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3313 ; adddi3 instruction pattern(s).
3316 (define_insn "*adddi3_sign"
3317 [(set (match_operand:DI 0 "register_operand" "=d,d")
3318 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3319 (match_operand:DI 1 "register_operand" "0,0")))
3320 (clobber (reg:CC 33))]
3325 [(set_attr "op_type" "RRE,RXY")])
3327 (define_insn "*adddi3_zero_cc"
3329 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3330 (match_operand:DI 1 "register_operand" "0,0"))
3332 (set (match_operand:DI 0 "register_operand" "=d,d")
3333 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3334 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3338 [(set_attr "op_type" "RRE,RXY")])
3340 (define_insn "*adddi3_zero_cconly"
3342 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3343 (match_operand:DI 1 "register_operand" "0,0"))
3345 (clobber (match_scratch:DI 0 "=d,d"))]
3346 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3350 [(set_attr "op_type" "RRE,RXY")])
3352 (define_insn "*adddi3_zero"
3353 [(set (match_operand:DI 0 "register_operand" "=d,d")
3354 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3355 (match_operand:DI 1 "register_operand" "0,0")))
3356 (clobber (reg:CC 33))]
3361 [(set_attr "op_type" "RRE,RXY")])
3363 (define_insn "*adddi3_imm_cc"
3365 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3366 (match_operand:DI 2 "const_int_operand" "K"))
3368 (set (match_operand:DI 0 "register_operand" "=d")
3369 (plus:DI (match_dup 1) (match_dup 2)))]
3371 && s390_match_ccmode (insn, CCAmode)
3372 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3374 [(set_attr "op_type" "RI")])
3376 (define_insn "*adddi3_carry1_cc"
3378 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3379 (match_operand:DI 2 "general_operand" "d,m"))
3381 (set (match_operand:DI 0 "register_operand" "=d,d")
3382 (plus:DI (match_dup 1) (match_dup 2)))]
3383 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3387 [(set_attr "op_type" "RRE,RXY")])
3389 (define_insn "*adddi3_carry1_cconly"
3391 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3392 (match_operand:DI 2 "general_operand" "d,m"))
3394 (clobber (match_scratch:DI 0 "=d,d"))]
3395 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3399 [(set_attr "op_type" "RRE,RXY")])
3401 (define_insn "*adddi3_carry2_cc"
3403 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3404 (match_operand:DI 2 "general_operand" "d,m"))
3406 (set (match_operand:DI 0 "register_operand" "=d,d")
3407 (plus:DI (match_dup 1) (match_dup 2)))]
3408 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3412 [(set_attr "op_type" "RRE,RXY")])
3414 (define_insn "*adddi3_carry2_cconly"
3416 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3417 (match_operand:DI 2 "general_operand" "d,m"))
3419 (clobber (match_scratch:DI 0 "=d,d"))]
3420 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3424 [(set_attr "op_type" "RRE,RXY")])
3426 (define_insn "*adddi3_cc"
3428 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3429 (match_operand:DI 2 "general_operand" "d,m"))
3431 (set (match_operand:DI 0 "register_operand" "=d,d")
3432 (plus:DI (match_dup 1) (match_dup 2)))]
3433 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3437 [(set_attr "op_type" "RRE,RXY")])
3439 (define_insn "*adddi3_cconly"
3441 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3442 (match_operand:DI 2 "general_operand" "d,m"))
3444 (clobber (match_scratch:DI 0 "=d,d"))]
3445 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3449 [(set_attr "op_type" "RRE,RXY")])
3451 (define_insn "*adddi3_cconly2"
3453 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3454 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3455 (clobber (match_scratch:DI 0 "=d,d"))]
3456 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3460 [(set_attr "op_type" "RRE,RXY")])
3462 (define_insn "*adddi3_64"
3463 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3464 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3465 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3466 (clobber (reg:CC 33))]
3472 [(set_attr "op_type" "RRE,RI,RXY")])
3474 (define_insn_and_split "*adddi3_31z"
3475 [(set (match_operand:DI 0 "register_operand" "=&d")
3476 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3477 (match_operand:DI 2 "general_operand" "do") ) )
3478 (clobber (reg:CC 33))]
3479 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3481 "&& reload_completed"
3484 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3486 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3488 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3489 (ltu:SI (reg:CCL1 33) (const_int 0))))
3490 (clobber (reg:CC 33))])]
3491 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3492 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3493 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3494 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3495 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3496 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3498 (define_insn_and_split "*adddi3_31"
3499 [(set (match_operand:DI 0 "register_operand" "=&d")
3500 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3501 (match_operand:DI 2 "general_operand" "do") ) )
3502 (clobber (reg:CC 33))]
3505 "&& reload_completed"
3507 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3508 (clobber (reg:CC 33))])
3511 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3513 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3515 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3517 (label_ref (match_dup 9))))
3519 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3520 (clobber (reg:CC 33))])
3522 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3523 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3524 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3525 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3526 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3527 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3528 operands[9] = gen_label_rtx ();")
3530 (define_expand "adddi3"
3532 [(set (match_operand:DI 0 "register_operand" "")
3533 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3534 (match_operand:DI 2 "general_operand" "")))
3535 (clobber (reg:CC 33))])]
3540 ; addsi3 instruction pattern(s).
3543 (define_insn "*addsi3_imm_cc"
3545 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3546 (match_operand:SI 2 "const_int_operand" "K"))
3548 (set (match_operand:SI 0 "register_operand" "=d")
3549 (plus:SI (match_dup 1) (match_dup 2)))]
3550 "s390_match_ccmode (insn, CCAmode)
3551 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3553 [(set_attr "op_type" "RI")])
3555 (define_insn "*addsi3_carry1_cc"
3557 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3558 (match_operand:SI 2 "general_operand" "d,R,T"))
3560 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3561 (plus:SI (match_dup 1) (match_dup 2)))]
3562 "s390_match_ccmode (insn, CCL1mode)"
3567 [(set_attr "op_type" "RR,RX,RXY")])
3569 (define_insn "*addsi3_carry1_cconly"
3571 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3572 (match_operand:SI 2 "general_operand" "d,R,T"))
3574 (clobber (match_scratch:SI 0 "=d,d,d"))]
3575 "s390_match_ccmode (insn, CCL1mode)"
3580 [(set_attr "op_type" "RR,RX,RXY")])
3582 (define_insn "*addsi3_carry2_cc"
3584 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3585 (match_operand:SI 2 "general_operand" "d,R,T"))
3587 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3588 (plus:SI (match_dup 1) (match_dup 2)))]
3589 "s390_match_ccmode (insn, CCL1mode)"
3594 [(set_attr "op_type" "RR,RX,RXY")])
3596 (define_insn "*addsi3_carry2_cconly"
3598 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3599 (match_operand:SI 2 "general_operand" "d,R,T"))
3601 (clobber (match_scratch:SI 0 "=d,d,d"))]
3602 "s390_match_ccmode (insn, CCL1mode)"
3607 [(set_attr "op_type" "RR,RX,RXY")])
3609 (define_insn "*addsi3_cc"
3611 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3612 (match_operand:SI 2 "general_operand" "d,R,T"))
3614 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3615 (plus:SI (match_dup 1) (match_dup 2)))]
3616 "s390_match_ccmode (insn, CCLmode)"
3621 [(set_attr "op_type" "RR,RX,RXY")])
3623 (define_insn "*addsi3_cconly"
3625 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3626 (match_operand:SI 2 "general_operand" "d,R,T"))
3628 (clobber (match_scratch:SI 0 "=d,d,d"))]
3629 "s390_match_ccmode (insn, CCLmode)"
3634 [(set_attr "op_type" "RR,RX,RXY")])
3636 (define_insn "*addsi3_cconly2"
3638 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3639 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3640 (clobber (match_scratch:SI 0 "=d,d,d"))]
3641 "s390_match_ccmode (insn, CCLmode)"
3646 [(set_attr "op_type" "RR,RX,RXY")])
3648 (define_insn "*addsi3_sign"
3649 [(set (match_operand:SI 0 "register_operand" "=d,d")
3650 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3651 (match_operand:SI 1 "register_operand" "0,0")))
3652 (clobber (reg:CC 33))]
3657 [(set_attr "op_type" "RX,RXY")])
3659 (define_insn "addsi3"
3660 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3661 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3662 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3663 (clobber (reg:CC 33))]
3670 [(set_attr "op_type" "RR,RI,RX,RXY")])
3673 ; adddf3 instruction pattern(s).
3676 (define_expand "adddf3"
3678 [(set (match_operand:DF 0 "register_operand" "=f,f")
3679 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3680 (match_operand:DF 2 "general_operand" "f,R")))
3681 (clobber (reg:CC 33))])]
3685 (define_insn "*adddf3"
3686 [(set (match_operand:DF 0 "register_operand" "=f,f")
3687 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3688 (match_operand:DF 2 "general_operand" "f,R")))
3689 (clobber (reg:CC 33))]
3690 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3694 [(set_attr "op_type" "RRE,RXE")
3695 (set_attr "type" "fsimpd,fsimpd")])
3697 (define_insn "*adddf3_cc"
3699 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3700 (match_operand:DF 2 "general_operand" "f,R"))
3701 (match_operand:DF 3 "const0_operand" "")))
3702 (set (match_operand:DF 0 "register_operand" "=f,f")
3703 (plus:DF (match_dup 1) (match_dup 2)))]
3704 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3708 [(set_attr "op_type" "RRE,RXE")
3709 (set_attr "type" "fsimpd,fsimpd")])
3711 (define_insn "*adddf3_cconly"
3713 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3714 (match_operand:DF 2 "general_operand" "f,R"))
3715 (match_operand:DF 3 "const0_operand" "")))
3716 (clobber (match_scratch:DF 0 "=f,f"))]
3717 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3721 [(set_attr "op_type" "RRE,RXE")
3722 (set_attr "type" "fsimpd,fsimpd")])
3724 (define_insn "*adddf3_ibm"
3725 [(set (match_operand:DF 0 "register_operand" "=f,f")
3726 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3727 (match_operand:DF 2 "general_operand" "f,R")))
3728 (clobber (reg:CC 33))]
3729 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3733 [(set_attr "op_type" "RR,RX")
3734 (set_attr "type" "fsimpd,fsimpd")])
3737 ; addsf3 instruction pattern(s).
3740 (define_expand "addsf3"
3742 [(set (match_operand:SF 0 "register_operand" "=f,f")
3743 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3744 (match_operand:SF 2 "general_operand" "f,R")))
3745 (clobber (reg:CC 33))])]
3749 (define_insn "*addsf3"
3750 [(set (match_operand:SF 0 "register_operand" "=f,f")
3751 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3752 (match_operand:SF 2 "general_operand" "f,R")))
3753 (clobber (reg:CC 33))]
3754 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3758 [(set_attr "op_type" "RRE,RXE")
3759 (set_attr "type" "fsimps,fsimps")])
3761 (define_insn "*addsf3_cc"
3763 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3764 (match_operand:SF 2 "general_operand" "f,R"))
3765 (match_operand:SF 3 "const0_operand" "")))
3766 (set (match_operand:SF 0 "register_operand" "=f,f")
3767 (plus:SF (match_dup 1) (match_dup 2)))]
3768 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3772 [(set_attr "op_type" "RRE,RXE")
3773 (set_attr "type" "fsimps,fsimps")])
3775 (define_insn "*addsf3_cconly"
3777 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3778 (match_operand:SF 2 "general_operand" "f,R"))
3779 (match_operand:SF 3 "const0_operand" "")))
3780 (clobber (match_scratch:SF 0 "=f,f"))]
3781 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3785 [(set_attr "op_type" "RRE,RXE")
3786 (set_attr "type" "fsimps,fsimps")])
3788 (define_insn "*addsf3"
3789 [(set (match_operand:SF 0 "register_operand" "=f,f")
3790 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3791 (match_operand:SF 2 "general_operand" "f,R")))
3792 (clobber (reg:CC 33))]
3793 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3797 [(set_attr "op_type" "RR,RX")
3798 (set_attr "type" "fsimps,fsimps")])
3802 ;;- Subtract instructions.
3806 ; subti3 instruction pattern(s).
3809 (define_insn_and_split "subti3"
3810 [(set (match_operand:TI 0 "register_operand" "=&d")
3811 (minus:TI (match_operand:TI 1 "register_operand" "0")
3812 (match_operand:TI 2 "general_operand" "do") ) )
3813 (clobber (reg:CC 33))]
3816 "&& reload_completed"
3819 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3821 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3823 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3824 (gtu:DI (reg:CCL2 33) (const_int 0))))
3825 (clobber (reg:CC 33))])]
3826 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3827 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3828 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3829 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3830 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3831 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3834 ; subdi3 instruction pattern(s).
3837 (define_insn "*subdi3_sign"
3838 [(set (match_operand:DI 0 "register_operand" "=d,d")
3839 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3840 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3841 (clobber (reg:CC 33))]
3846 [(set_attr "op_type" "RRE,RXY")])
3848 (define_insn "*subdi3_zero_cc"
3850 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3851 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3853 (set (match_operand:DI 0 "register_operand" "=d,d")
3854 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3855 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3859 [(set_attr "op_type" "RRE,RXY")])
3861 (define_insn "*subdi3_zero_cconly"
3863 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3864 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3866 (clobber (match_scratch:DI 0 "=d,d"))]
3867 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3871 [(set_attr "op_type" "RRE,RXY")])
3873 (define_insn "*subdi3_zero"
3874 [(set (match_operand:DI 0 "register_operand" "=d,d")
3875 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3876 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3877 (clobber (reg:CC 33))]
3882 [(set_attr "op_type" "RRE,RXY")])
3884 (define_insn "*subdi3_borrow_cc"
3886 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3887 (match_operand:DI 2 "general_operand" "d,m"))
3889 (set (match_operand:DI 0 "register_operand" "=d,d")
3890 (minus:DI (match_dup 1) (match_dup 2)))]
3891 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3895 [(set_attr "op_type" "RRE,RXY")])
3897 (define_insn "*subdi3_borrow_cconly"
3899 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3900 (match_operand:DI 2 "general_operand" "d,m"))
3902 (clobber (match_scratch:DI 0 "=d,d"))]
3903 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3907 [(set_attr "op_type" "RRE,RXY")])
3909 (define_insn "*subdi3_cc"
3911 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3912 (match_operand:DI 2 "general_operand" "d,m"))
3914 (set (match_operand:DI 0 "register_operand" "=d,d")
3915 (minus:DI (match_dup 1) (match_dup 2)))]
3916 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3920 [(set_attr "op_type" "RRE,RXY")])
3922 (define_insn "*subdi3_cc2"
3924 (compare (match_operand:DI 1 "register_operand" "0,0")
3925 (match_operand:DI 2 "general_operand" "d,m")))
3926 (set (match_operand:DI 0 "register_operand" "=d,d")
3927 (minus:DI (match_dup 1) (match_dup 2)))]
3928 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3932 [(set_attr "op_type" "RRE,RXY")])
3934 (define_insn "*subdi3_cconly"
3936 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3937 (match_operand:DI 2 "general_operand" "d,m"))
3939 (clobber (match_scratch:DI 0 "=d,d"))]
3940 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3944 [(set_attr "op_type" "RRE,RXY")])
3946 (define_insn "*subdi3_cconly2"
3948 (compare (match_operand:DI 1 "register_operand" "0,0")
3949 (match_operand:DI 2 "general_operand" "d,m")))
3950 (clobber (match_scratch:DI 0 "=d,d"))]
3951 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3955 [(set_attr "op_type" "RRE,RXY")])
3957 (define_insn "*subdi3_64"
3958 [(set (match_operand:DI 0 "register_operand" "=d,d")
3959 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3960 (match_operand:DI 2 "general_operand" "d,m") ) )
3961 (clobber (reg:CC 33))]
3966 [(set_attr "op_type" "RRE,RRE")])
3968 (define_insn_and_split "*subdi3_31z"
3969 [(set (match_operand:DI 0 "register_operand" "=&d")
3970 (minus:DI (match_operand:DI 1 "register_operand" "0")
3971 (match_operand:DI 2 "general_operand" "do") ) )
3972 (clobber (reg:CC 33))]
3973 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3975 "&& reload_completed"
3978 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3980 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3982 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3983 (gtu:SI (reg:CCL2 33) (const_int 0))))
3984 (clobber (reg:CC 33))])]
3985 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3986 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3987 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3988 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3989 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3990 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3992 (define_insn_and_split "*subdi3_31"
3993 [(set (match_operand:DI 0 "register_operand" "=&d")
3994 (minus:DI (match_operand:DI 1 "register_operand" "0")
3995 (match_operand:DI 2 "general_operand" "do") ) )
3996 (clobber (reg:CC 33))]
3999 "&& reload_completed"
4001 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4002 (clobber (reg:CC 33))])
4005 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4007 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4009 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
4011 (label_ref (match_dup 9))))
4013 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4014 (clobber (reg:CC 33))])
4016 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4017 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4018 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4019 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4020 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4021 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4022 operands[9] = gen_label_rtx ();")
4024 (define_expand "subdi3"
4026 [(set (match_operand:DI 0 "register_operand" "")
4027 (minus:DI (match_operand:DI 1 "register_operand" "")
4028 (match_operand:DI 2 "general_operand" "")))
4029 (clobber (reg:CC 33))])]
4034 ; subsi3 instruction pattern(s).
4037 (define_insn "*subsi3_borrow_cc"
4039 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4040 (match_operand:SI 2 "general_operand" "d,R,T"))
4042 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4043 (minus:SI (match_dup 1) (match_dup 2)))]
4044 "s390_match_ccmode (insn, CCL2mode)"
4049 [(set_attr "op_type" "RR,RX,RXY")])
4051 (define_insn "*subsi3_borrow_cconly"
4053 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4054 (match_operand:SI 2 "general_operand" "d,R,T"))
4056 (clobber (match_scratch:SI 0 "=d,d,d"))]
4057 "s390_match_ccmode (insn, CCL2mode)"
4062 [(set_attr "op_type" "RR,RX,RXY")])
4064 (define_insn "*subsi3_cc"
4066 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4067 (match_operand:SI 2 "general_operand" "d,R,T"))
4069 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4070 (minus:SI (match_dup 1) (match_dup 2)))]
4071 "s390_match_ccmode (insn, CCLmode)"
4076 [(set_attr "op_type" "RR,RX,RXY")])
4078 (define_insn "*subsi3_cc2"
4080 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4081 (match_operand:SI 2 "general_operand" "d,R,T")))
4082 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4083 (minus:SI (match_dup 1) (match_dup 2)))]
4084 "s390_match_ccmode (insn, CCL3mode)"
4089 [(set_attr "op_type" "RR,RX,RXY")])
4091 (define_insn "*subsi3_cconly"
4093 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4094 (match_operand:SI 2 "general_operand" "d,R,T"))
4096 (clobber (match_scratch:SI 0 "=d,d,d"))]
4097 "s390_match_ccmode (insn, CCLmode)"
4102 [(set_attr "op_type" "RR,RX,RXY")])
4104 (define_insn "*subsi3_cconly2"
4106 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4107 (match_operand:SI 2 "general_operand" "d,R,T")))
4108 (clobber (match_scratch:SI 0 "=d,d,d"))]
4109 "s390_match_ccmode (insn, CCL3mode)"
4114 [(set_attr "op_type" "RR,RX,RXY")])
4116 (define_insn "*subsi3_sign"
4117 [(set (match_operand:SI 0 "register_operand" "=d,d")
4118 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4119 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4120 (clobber (reg:CC 33))]
4125 [(set_attr "op_type" "RX,RXY")])
4127 (define_insn "subsi3"
4128 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4129 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4130 (match_operand:SI 2 "general_operand" "d,R,T")))
4131 (clobber (reg:CC 33))]
4137 [(set_attr "op_type" "RR,RX,RXY")])
4141 ; subdf3 instruction pattern(s).
4144 (define_expand "subdf3"
4146 [(set (match_operand:DF 0 "register_operand" "=f,f")
4147 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4148 (match_operand:DF 2 "general_operand" "f,R")))
4149 (clobber (reg:CC 33))])]
4153 (define_insn "*subdf3"
4154 [(set (match_operand:DF 0 "register_operand" "=f,f")
4155 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4156 (match_operand:DF 2 "general_operand" "f,R")))
4157 (clobber (reg:CC 33))]
4158 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4162 [(set_attr "op_type" "RRE,RXE")
4163 (set_attr "type" "fsimpd,fsimpd")])
4165 (define_insn "*subdf3_cc"
4167 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4168 (match_operand:DF 2 "general_operand" "f,R"))
4169 (match_operand:DF 3 "const0_operand" "")))
4170 (set (match_operand:DF 0 "register_operand" "=f,f")
4171 (minus:DF (match_dup 1) (match_dup 2)))]
4172 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4176 [(set_attr "op_type" "RRE,RXE")
4177 (set_attr "type" "fsimpd,fsimpd")])
4179 (define_insn "*subdf3_cconly"
4181 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4182 (match_operand:DF 2 "general_operand" "f,R"))
4183 (match_operand:DF 3 "const0_operand" "")))
4184 (clobber (match_scratch:DF 0 "=f,f"))]
4185 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4189 [(set_attr "op_type" "RRE,RXE")
4190 (set_attr "type" "fsimpd,fsimpd")])
4192 (define_insn "*subdf3_ibm"
4193 [(set (match_operand:DF 0 "register_operand" "=f,f")
4194 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4195 (match_operand:DF 2 "general_operand" "f,R")))
4196 (clobber (reg:CC 33))]
4197 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4201 [(set_attr "op_type" "RR,RX")
4202 (set_attr "type" "fsimpd,fsimpd")])
4205 ; subsf3 instruction pattern(s).
4208 (define_expand "subsf3"
4210 [(set (match_operand:SF 0 "register_operand" "=f,f")
4211 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4212 (match_operand:SF 2 "general_operand" "f,R")))
4213 (clobber (reg:CC 33))])]
4217 (define_insn "*subsf3"
4218 [(set (match_operand:SF 0 "register_operand" "=f,f")
4219 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4220 (match_operand:SF 2 "general_operand" "f,R")))
4221 (clobber (reg:CC 33))]
4222 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4226 [(set_attr "op_type" "RRE,RXE")
4227 (set_attr "type" "fsimps,fsimps")])
4229 (define_insn "*subsf3_cc"
4231 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4232 (match_operand:SF 2 "general_operand" "f,R"))
4233 (match_operand:SF 3 "const0_operand" "")))
4234 (set (match_operand:SF 0 "register_operand" "=f,f")
4235 (minus:SF (match_dup 1) (match_dup 2)))]
4236 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4240 [(set_attr "op_type" "RRE,RXE")
4241 (set_attr "type" "fsimps,fsimps")])
4243 (define_insn "*subsf3_cconly"
4245 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4246 (match_operand:SF 2 "general_operand" "f,R"))
4247 (match_operand:SF 3 "const0_operand" "")))
4248 (clobber (match_scratch:SF 0 "=f,f"))]
4249 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4253 [(set_attr "op_type" "RRE,RXE")
4254 (set_attr "type" "fsimps,fsimps")])
4256 (define_insn "*subsf3_ibm"
4257 [(set (match_operand:SF 0 "register_operand" "=f,f")
4258 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4259 (match_operand:SF 2 "general_operand" "f,R")))
4260 (clobber (reg:CC 33))]
4261 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4265 [(set_attr "op_type" "RR,RX")
4266 (set_attr "type" "fsimps,fsimps")])
4270 ;;- Conditional add/subtract instructions.
4274 ; adddicc instruction pattern(s).
4277 (define_insn "*adddi3_alc_cc"
4280 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4281 (match_operand:DI 2 "general_operand" "d,m"))
4282 (match_operand:DI 3 "s390_alc_comparison" ""))
4284 (set (match_operand:DI 0 "register_operand" "=d,d")
4285 (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4286 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4290 [(set_attr "op_type" "RRE,RXY")])
4292 (define_insn "*adddi3_alc"
4293 [(set (match_operand:DI 0 "register_operand" "=d,d")
4294 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4295 (match_operand:DI 2 "general_operand" "d,m"))
4296 (match_operand:DI 3 "s390_alc_comparison" "")))
4297 (clobber (reg:CC 33))]
4302 [(set_attr "op_type" "RRE,RXY")])
4304 (define_insn "*subdi3_slb_cc"
4307 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4308 (match_operand:DI 2 "general_operand" "d,m"))
4309 (match_operand:DI 3 "s390_slb_comparison" ""))
4311 (set (match_operand:DI 0 "register_operand" "=d,d")
4312 (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4313 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4317 [(set_attr "op_type" "RRE,RXY")])
4319 (define_insn "*subdi3_slb"
4320 [(set (match_operand:DI 0 "register_operand" "=d,d")
4321 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4322 (match_operand:DI 2 "general_operand" "d,m"))
4323 (match_operand:DI 3 "s390_slb_comparison" "")))
4324 (clobber (reg:CC 33))]
4329 [(set_attr "op_type" "RRE,RXY")])
4331 (define_expand "adddicc"
4332 [(match_operand:DI 0 "register_operand" "")
4333 (match_operand 1 "comparison_operator" "")
4334 (match_operand:DI 2 "register_operand" "")
4335 (match_operand:DI 3 "const_int_operand" "")]
4337 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4338 s390_compare_op0, s390_compare_op1,
4339 operands[0], operands[2],
4340 operands[3])) FAIL; DONE;")
4343 ; addsicc instruction pattern(s).
4346 (define_insn "*addsi3_alc_cc"
4349 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4350 (match_operand:SI 2 "general_operand" "d,m"))
4351 (match_operand:SI 3 "s390_alc_comparison" ""))
4353 (set (match_operand:SI 0 "register_operand" "=d,d")
4354 (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4355 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4359 [(set_attr "op_type" "RRE,RXY")])
4361 (define_insn "*addsi3_alc"
4362 [(set (match_operand:SI 0 "register_operand" "=d,d")
4363 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4364 (match_operand:SI 2 "general_operand" "d,m"))
4365 (match_operand:SI 3 "s390_alc_comparison" "")))
4366 (clobber (reg:CC 33))]
4371 [(set_attr "op_type" "RRE,RXY")])
4373 (define_insn "*subsi3_slb_cc"
4376 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4377 (match_operand:SI 2 "general_operand" "d,m"))
4378 (match_operand:SI 3 "s390_slb_comparison" ""))
4380 (set (match_operand:SI 0 "register_operand" "=d,d")
4381 (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4382 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4386 [(set_attr "op_type" "RRE,RXY")])
4388 (define_insn "*subsi3_slb"
4389 [(set (match_operand:SI 0 "register_operand" "=d,d")
4390 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4391 (match_operand:SI 2 "general_operand" "d,m"))
4392 (match_operand:SI 3 "s390_slb_comparison" "")))
4393 (clobber (reg:CC 33))]
4398 [(set_attr "op_type" "RRE,RXY")])
4400 (define_expand "addsicc"
4401 [(match_operand:SI 0 "register_operand" "")
4402 (match_operand 1 "comparison_operator" "")
4403 (match_operand:SI 2 "register_operand" "")
4404 (match_operand:SI 3 "const_int_operand" "")]
4406 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4407 s390_compare_op0, s390_compare_op1,
4408 operands[0], operands[2],
4409 operands[3])) FAIL; DONE;")
4412 ; scond instruction pattern(s).
4415 (define_insn_and_split "*sconddi"
4416 [(set (match_operand:DI 0 "register_operand" "=&d")
4417 (match_operand:DI 1 "s390_alc_comparison" ""))
4418 (clobber (reg:CC 33))]
4421 "&& reload_completed"
4422 [(set (match_dup 0) (const_int 0))
4424 [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
4426 (clobber (reg:CC 33))])]
4429 (define_insn_and_split "*scondsi"
4430 [(set (match_operand:SI 0 "register_operand" "=&d")
4431 (match_operand:SI 1 "s390_alc_comparison" ""))
4432 (clobber (reg:CC 33))]
4435 "&& reload_completed"
4436 [(set (match_dup 0) (const_int 0))
4438 [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
4440 (clobber (reg:CC 33))])]
4443 (define_insn_and_split "*sconddi_neg"
4444 [(set (match_operand:DI 0 "register_operand" "=&d")
4445 (match_operand:DI 1 "s390_slb_comparison" ""))
4446 (clobber (reg:CC 33))]
4449 "&& reload_completed"
4450 [(set (match_dup 0) (const_int 0))
4452 [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0))
4454 (clobber (reg:CC 33))])
4456 [(set (match_dup 0) (neg:DI (match_dup 0)))
4457 (clobber (reg:CC 33))])]
4460 (define_insn_and_split "*scondsi_neg"
4461 [(set (match_operand:SI 0 "register_operand" "=&d")
4462 (match_operand:SI 1 "s390_slb_comparison" ""))
4463 (clobber (reg:CC 33))]
4466 "&& reload_completed"
4467 [(set (match_dup 0) (const_int 0))
4469 [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
4471 (clobber (reg:CC 33))])
4473 [(set (match_dup 0) (neg:SI (match_dup 0)))
4474 (clobber (reg:CC 33))])]
4477 (define_expand "sltu"
4478 [(match_operand:SI 0 "register_operand" "")]
4480 "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
4481 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4483 (define_expand "sgtu"
4484 [(match_operand:SI 0 "register_operand" "")]
4486 "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
4487 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4489 (define_expand "sleu"
4490 [(match_operand:SI 0 "register_operand" "")]
4492 "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
4493 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4495 (define_expand "sgeu"
4496 [(match_operand:SI 0 "register_operand" "")]
4498 "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
4499 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4503 ;;- Multiply instructions.
4507 ; muldi3 instruction pattern(s).
4510 (define_insn "*muldi3_sign"
4511 [(set (match_operand:DI 0 "register_operand" "=d,d")
4512 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4513 (match_operand:DI 1 "register_operand" "0,0")))]
4518 [(set_attr "op_type" "RRE,RXY")
4519 (set_attr "type" "imuldi")])
4521 (define_insn "muldi3"
4522 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4523 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4524 (match_operand:DI 2 "general_operand" "d,K,m")))]
4530 [(set_attr "op_type" "RRE,RI,RXY")
4531 (set_attr "type" "imuldi")])
4534 ; mulsi3 instruction pattern(s).
4537 (define_insn "*mulsi3_sign"
4538 [(set (match_operand:SI 0 "register_operand" "=d")
4539 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4540 (match_operand:SI 1 "register_operand" "0")))]
4543 [(set_attr "op_type" "RX")
4544 (set_attr "type" "imulhi")])
4546 (define_insn "mulsi3"
4547 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4548 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4549 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4556 [(set_attr "op_type" "RRE,RI,RX,RXY")
4557 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4560 ; mulsidi3 instruction pattern(s).
4563 (define_insn "mulsidi3"
4564 [(set (match_operand:DI 0 "register_operand" "=d,d")
4565 (mult:DI (sign_extend:DI
4566 (match_operand:SI 1 "register_operand" "%0,0"))
4568 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4573 [(set_attr "op_type" "RR,RX")
4574 (set_attr "type" "imulsi")])
4577 ; umulsidi3 instruction pattern(s).
4580 (define_insn "umulsidi3"
4581 [(set (match_operand:DI 0 "register_operand" "=d,d")
4582 (mult:DI (zero_extend:DI
4583 (match_operand:SI 1 "register_operand" "%0,0"))
4585 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4586 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4590 [(set_attr "op_type" "RRE,RXY")
4591 (set_attr "type" "imulsi")])
4594 ; muldf3 instruction pattern(s).
4597 (define_expand "muldf3"
4598 [(set (match_operand:DF 0 "register_operand" "=f,f")
4599 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4600 (match_operand:DF 2 "general_operand" "f,R")))]
4604 (define_insn "*muldf3"
4605 [(set (match_operand:DF 0 "register_operand" "=f,f")
4606 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4607 (match_operand:DF 2 "general_operand" "f,R")))]
4608 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4612 [(set_attr "op_type" "RRE,RXE")
4613 (set_attr "type" "fmuld")])
4615 (define_insn "*muldf3_ibm"
4616 [(set (match_operand:DF 0 "register_operand" "=f,f")
4617 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4618 (match_operand:DF 2 "general_operand" "f,R")))]
4619 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4623 [(set_attr "op_type" "RR,RX")
4624 (set_attr "type" "fmuld")])
4626 (define_insn "*fmadddf"
4627 [(set (match_operand:DF 0 "register_operand" "=f,f")
4628 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
4629 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4630 (match_operand:DF 3 "register_operand" "0,0")))]
4631 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4635 [(set_attr "op_type" "RRE,RXE")
4636 (set_attr "type" "fmuld")])
4638 (define_insn "*fmsubdf"
4639 [(set (match_operand:DF 0 "register_operand" "=f,f")
4640 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
4641 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4642 (match_operand:DF 3 "register_operand" "0,0")))]
4643 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4647 [(set_attr "op_type" "RRE,RXE")
4648 (set_attr "type" "fmuld")])
4651 ; mulsf3 instruction pattern(s).
4654 (define_expand "mulsf3"
4655 [(set (match_operand:SF 0 "register_operand" "=f,f")
4656 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4657 (match_operand:SF 2 "general_operand" "f,R")))]
4661 (define_insn "*mulsf3"
4662 [(set (match_operand:SF 0 "register_operand" "=f,f")
4663 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4664 (match_operand:SF 2 "general_operand" "f,R")))]
4665 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4669 [(set_attr "op_type" "RRE,RXE")
4670 (set_attr "type" "fmuls")])
4672 (define_insn "*mulsf3_ibm"
4673 [(set (match_operand:SF 0 "register_operand" "=f,f")
4674 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4675 (match_operand:SF 2 "general_operand" "f,R")))]
4676 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4680 [(set_attr "op_type" "RR,RX")
4681 (set_attr "type" "fmuls")])
4683 (define_insn "*fmaddsf"
4684 [(set (match_operand:SF 0 "register_operand" "=f,f")
4685 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
4686 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4687 (match_operand:SF 3 "register_operand" "0,0")))]
4688 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4692 [(set_attr "op_type" "RRE,RXE")
4693 (set_attr "type" "fmuls")])
4695 (define_insn "*fmsubsf"
4696 [(set (match_operand:SF 0 "register_operand" "=f,f")
4697 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
4698 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4699 (match_operand:SF 3 "register_operand" "0,0")))]
4700 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4704 [(set_attr "op_type" "RRE,RXE")
4705 (set_attr "type" "fmuls")])
4708 ;;- Divide and modulo instructions.
4712 ; divmoddi4 instruction pattern(s).
4715 (define_expand "divmoddi4"
4716 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4717 (div:DI (match_operand:DI 1 "register_operand" "")
4718 (match_operand:DI 2 "general_operand" "")))
4719 (set (match_operand:DI 3 "general_operand" "")
4720 (mod:DI (match_dup 1) (match_dup 2)))])
4721 (clobber (match_dup 4))]
4724 rtx insn, div_equal, mod_equal;
4726 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4727 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4729 operands[4] = gen_reg_rtx(TImode);
4730 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4732 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4734 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4736 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4738 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4743 (define_insn "divmodtidi3"
4744 [(set (match_operand:TI 0 "register_operand" "=d,d")
4748 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4749 (match_operand:DI 2 "general_operand" "d,m")))
4751 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4756 [(set_attr "op_type" "RRE,RXY")
4757 (set_attr "type" "idiv")])
4759 (define_insn "divmodtisi3"
4760 [(set (match_operand:TI 0 "register_operand" "=d,d")
4764 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4766 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4769 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4774 [(set_attr "op_type" "RRE,RXY")
4775 (set_attr "type" "idiv")])
4778 ; udivmoddi4 instruction pattern(s).
4781 (define_expand "udivmoddi4"
4782 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4783 (udiv:DI (match_operand:DI 1 "general_operand" "")
4784 (match_operand:DI 2 "nonimmediate_operand" "")))
4785 (set (match_operand:DI 3 "general_operand" "")
4786 (umod:DI (match_dup 1) (match_dup 2)))])
4787 (clobber (match_dup 4))]
4790 rtx insn, div_equal, mod_equal, equal;
4792 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4793 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4794 equal = gen_rtx_IOR (TImode,
4795 gen_rtx_ASHIFT (TImode,
4796 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4798 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4800 operands[4] = gen_reg_rtx(TImode);
4801 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4802 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4803 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4804 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4806 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4808 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4810 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4812 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4814 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4819 (define_insn "udivmodtidi3"
4820 [(set (match_operand:TI 0 "register_operand" "=d,d")
4825 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4827 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4831 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4836 [(set_attr "op_type" "RRE,RXY")
4837 (set_attr "type" "idiv")])
4840 ; divmodsi4 instruction pattern(s).
4843 (define_expand "divmodsi4"
4844 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4845 (div:SI (match_operand:SI 1 "general_operand" "")
4846 (match_operand:SI 2 "nonimmediate_operand" "")))
4847 (set (match_operand:SI 3 "general_operand" "")
4848 (mod:SI (match_dup 1) (match_dup 2)))])
4849 (clobber (match_dup 4))]
4852 rtx insn, div_equal, mod_equal, equal;
4854 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4855 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4856 equal = gen_rtx_IOR (DImode,
4857 gen_rtx_ASHIFT (DImode,
4858 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4860 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4862 operands[4] = gen_reg_rtx(DImode);
4863 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4864 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4866 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4868 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4870 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4872 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4874 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4879 (define_insn "divmoddisi3"
4880 [(set (match_operand:DI 0 "register_operand" "=d,d")
4885 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4887 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4891 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4896 [(set_attr "op_type" "RR,RX")
4897 (set_attr "type" "idiv")])
4900 ; udivsi3 and umodsi3 instruction pattern(s).
4903 (define_expand "udivmodsi4"
4904 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4905 (udiv:SI (match_operand:SI 1 "general_operand" "")
4906 (match_operand:SI 2 "nonimmediate_operand" "")))
4907 (set (match_operand:SI 3 "general_operand" "")
4908 (umod:SI (match_dup 1) (match_dup 2)))])
4909 (clobber (match_dup 4))]
4910 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4912 rtx insn, div_equal, mod_equal, equal;
4914 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4915 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4916 equal = gen_rtx_IOR (DImode,
4917 gen_rtx_ASHIFT (DImode,
4918 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4920 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4922 operands[4] = gen_reg_rtx(DImode);
4923 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4924 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4925 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4926 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4928 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4930 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4932 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4934 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4936 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4941 (define_insn "udivmoddisi3"
4942 [(set (match_operand:DI 0 "register_operand" "=d,d")
4947 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4949 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4953 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4954 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4958 [(set_attr "op_type" "RRE,RXY")
4959 (set_attr "type" "idiv")])
4961 (define_expand "udivsi3"
4962 [(set (match_operand:SI 0 "register_operand" "=d")
4963 (udiv:SI (match_operand:SI 1 "general_operand" "")
4964 (match_operand:SI 2 "general_operand" "")))
4965 (clobber (match_dup 3))]
4966 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4968 rtx insn, udiv_equal, umod_equal, equal;
4970 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4971 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4972 equal = gen_rtx_IOR (DImode,
4973 gen_rtx_ASHIFT (DImode,
4974 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4976 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4978 operands[3] = gen_reg_rtx (DImode);
4980 if (CONSTANT_P (operands[2]))
4982 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4984 rtx label1 = gen_label_rtx ();
4986 operands[1] = make_safe_from (operands[1], operands[0]);
4987 emit_move_insn (operands[0], const0_rtx);
4988 emit_insn (gen_cmpsi (operands[1], operands[2]));
4989 emit_jump_insn (gen_bltu (label1));
4990 emit_move_insn (operands[0], const1_rtx);
4991 emit_label (label1);
4995 operands[2] = force_reg (SImode, operands[2]);
4996 operands[2] = make_safe_from (operands[2], operands[0]);
4998 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4999 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5002 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5004 insn = emit_move_insn (operands[0],
5005 gen_lowpart (SImode, operands[3]));
5007 gen_rtx_EXPR_LIST (REG_EQUAL,
5008 udiv_equal, REG_NOTES (insn));
5013 rtx label1 = gen_label_rtx ();
5014 rtx label2 = gen_label_rtx ();
5015 rtx label3 = gen_label_rtx ();
5017 operands[1] = force_reg (SImode, operands[1]);
5018 operands[1] = make_safe_from (operands[1], operands[0]);
5019 operands[2] = force_reg (SImode, operands[2]);
5020 operands[2] = make_safe_from (operands[2], operands[0]);
5022 emit_move_insn (operands[0], const0_rtx);
5023 emit_insn (gen_cmpsi (operands[2], operands[1]));
5024 emit_jump_insn (gen_bgtu (label3));
5025 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5026 emit_jump_insn (gen_blt (label2));
5027 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5028 emit_jump_insn (gen_beq (label1));
5029 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5030 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5033 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5035 insn = emit_move_insn (operands[0],
5036 gen_lowpart (SImode, operands[3]));
5038 gen_rtx_EXPR_LIST (REG_EQUAL,
5039 udiv_equal, REG_NOTES (insn));
5041 emit_label (label1);
5042 emit_move_insn (operands[0], operands[1]);
5044 emit_label (label2);
5045 emit_move_insn (operands[0], const1_rtx);
5046 emit_label (label3);
5048 emit_move_insn (operands[0], operands[0]);
5052 (define_expand "umodsi3"
5053 [(set (match_operand:SI 0 "register_operand" "=d")
5054 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5055 (match_operand:SI 2 "nonimmediate_operand" "")))
5056 (clobber (match_dup 3))]
5057 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5059 rtx insn, udiv_equal, umod_equal, equal;
5061 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5062 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5063 equal = gen_rtx_IOR (DImode,
5064 gen_rtx_ASHIFT (DImode,
5065 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5067 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5069 operands[3] = gen_reg_rtx (DImode);
5071 if (CONSTANT_P (operands[2]))
5073 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5075 rtx label1 = gen_label_rtx ();
5077 operands[1] = make_safe_from (operands[1], operands[0]);
5078 emit_move_insn (operands[0], operands[1]);
5079 emit_insn (gen_cmpsi (operands[0], operands[2]));
5080 emit_jump_insn (gen_bltu (label1));
5081 emit_insn (gen_abssi2 (operands[0], operands[2]));
5082 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5083 emit_label (label1);
5087 operands[2] = force_reg (SImode, operands[2]);
5088 operands[2] = make_safe_from (operands[2], operands[0]);
5090 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5091 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5094 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5096 insn = emit_move_insn (operands[0],
5097 gen_highpart (SImode, operands[3]));
5099 gen_rtx_EXPR_LIST (REG_EQUAL,
5100 umod_equal, REG_NOTES (insn));
5105 rtx label1 = gen_label_rtx ();
5106 rtx label2 = gen_label_rtx ();
5107 rtx label3 = gen_label_rtx ();
5109 operands[1] = force_reg (SImode, operands[1]);
5110 operands[1] = make_safe_from (operands[1], operands[0]);
5111 operands[2] = force_reg (SImode, operands[2]);
5112 operands[2] = make_safe_from (operands[2], operands[0]);
5114 emit_move_insn(operands[0], operands[1]);
5115 emit_insn (gen_cmpsi (operands[2], operands[1]));
5116 emit_jump_insn (gen_bgtu (label3));
5117 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5118 emit_jump_insn (gen_blt (label2));
5119 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5120 emit_jump_insn (gen_beq (label1));
5121 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5122 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5125 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5127 insn = emit_move_insn (operands[0],
5128 gen_highpart (SImode, operands[3]));
5130 gen_rtx_EXPR_LIST (REG_EQUAL,
5131 umod_equal, REG_NOTES (insn));
5133 emit_label (label1);
5134 emit_move_insn (operands[0], const0_rtx);
5136 emit_label (label2);
5137 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5138 emit_label (label3);
5144 ; divdf3 instruction pattern(s).
5147 (define_expand "divdf3"
5148 [(set (match_operand:DF 0 "register_operand" "=f,f")
5149 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5150 (match_operand:DF 2 "general_operand" "f,R")))]
5154 (define_insn "*divdf3"
5155 [(set (match_operand:DF 0 "register_operand" "=f,f")
5156 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5157 (match_operand:DF 2 "general_operand" "f,R")))]
5158 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5162 [(set_attr "op_type" "RRE,RXE")
5163 (set_attr "type" "fdivd")])
5165 (define_insn "*divdf3_ibm"
5166 [(set (match_operand:DF 0 "register_operand" "=f,f")
5167 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5168 (match_operand:DF 2 "general_operand" "f,R")))]
5169 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5173 [(set_attr "op_type" "RR,RX")
5174 (set_attr "type" "fdivd")])
5177 ; divsf3 instruction pattern(s).
5180 (define_expand "divsf3"
5181 [(set (match_operand:SF 0 "register_operand" "=f,f")
5182 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5183 (match_operand:SF 2 "general_operand" "f,R")))]
5187 (define_insn "*divsf3"
5188 [(set (match_operand:SF 0 "register_operand" "=f,f")
5189 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5190 (match_operand:SF 2 "general_operand" "f,R")))]
5191 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5195 [(set_attr "op_type" "RRE,RXE")
5196 (set_attr "type" "fdivs")])
5198 (define_insn "*divsf3"
5199 [(set (match_operand:SF 0 "register_operand" "=f,f")
5200 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5201 (match_operand:SF 2 "general_operand" "f,R")))]
5202 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5206 [(set_attr "op_type" "RR,RX")
5207 (set_attr "type" "fdivs")])
5211 ;;- And instructions.
5215 ; anddi3 instruction pattern(s).
5218 (define_insn "*anddi3_cc"
5220 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5221 (match_operand:DI 2 "general_operand" "d,m"))
5223 (set (match_operand:DI 0 "register_operand" "=d,d")
5224 (and:DI (match_dup 1) (match_dup 2)))]
5225 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5229 [(set_attr "op_type" "RRE,RXY")])
5231 (define_insn "*anddi3_cconly"
5233 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5234 (match_operand:DI 2 "general_operand" "d,m"))
5236 (clobber (match_scratch:DI 0 "=d,d"))]
5237 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5238 /* Do not steal TM patterns. */
5239 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5243 [(set_attr "op_type" "RRE,RXY")])
5245 (define_insn "*anddi3"
5246 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5247 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5248 "%d,o,0,0,0,0,0,0,0,0")
5249 (match_operand:DI 2 "general_operand"
5250 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5251 (clobber (reg:CC 33))]
5252 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5264 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5267 [(set (match_operand:DI 0 "s_operand" "")
5268 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5269 (clobber (reg:CC 33))]
5272 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5273 (clobber (reg:CC 33))])]
5274 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5276 (define_expand "anddi3"
5277 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5278 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
5279 (match_operand:DI 2 "general_operand" "")))
5280 (clobber (reg:CC 33))]
5282 "s390_expand_logical_operator (AND, DImode, operands); DONE;")
5285 ; andsi3 instruction pattern(s).
5288 (define_insn "*andsi3_cc"
5290 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5291 (match_operand:SI 2 "general_operand" "d,R,T"))
5293 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5294 (and:SI (match_dup 1) (match_dup 2)))]
5295 "s390_match_ccmode(insn, CCTmode)"
5300 [(set_attr "op_type" "RR,RX,RXY")])
5302 (define_insn "*andsi3_cconly"
5304 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5305 (match_operand:SI 2 "general_operand" "d,R,T"))
5307 (clobber (match_scratch:SI 0 "=d,d,d"))]
5308 "s390_match_ccmode(insn, CCTmode)
5309 /* Do not steal TM patterns. */
5310 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5315 [(set_attr "op_type" "RR,RX,RXY")])
5317 (define_insn "*andsi3_zarch"
5318 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
5319 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5320 "%d,o,0,0,0,0,0,0,0")
5321 (match_operand:SI 2 "general_operand"
5322 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
5323 (clobber (reg:CC 33))]
5324 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5335 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
5337 (define_insn "*andsi3_esa"
5338 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5339 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5340 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5341 (clobber (reg:CC 33))]
5342 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5348 [(set_attr "op_type" "RR,RX,SI,SS")])
5351 [(set (match_operand:SI 0 "s_operand" "")
5352 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5353 (clobber (reg:CC 33))]
5356 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5357 (clobber (reg:CC 33))])]
5358 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5360 (define_expand "andsi3"
5361 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5362 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
5363 (match_operand:SI 2 "general_operand" "")))
5364 (clobber (reg:CC 33))]
5366 "s390_expand_logical_operator (AND, SImode, operands); DONE;")
5369 ; andhi3 instruction pattern(s).
5372 (define_insn "*andhi3_zarch"
5373 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5374 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5375 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5376 (clobber (reg:CC 33))]
5377 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5383 [(set_attr "op_type" "RR,RI,SI,SS")])
5385 (define_insn "*andhi3_esa"
5386 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5387 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5388 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5389 (clobber (reg:CC 33))]
5390 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5395 [(set_attr "op_type" "RR,SI,SS")])
5398 [(set (match_operand:HI 0 "s_operand" "")
5399 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5400 (clobber (reg:CC 33))]
5403 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5404 (clobber (reg:CC 33))])]
5405 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5407 (define_expand "andhi3"
5408 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5409 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
5410 (match_operand:HI 2 "general_operand" "")))
5411 (clobber (reg:CC 33))]
5413 "s390_expand_logical_operator (AND, HImode, operands); DONE;")
5416 ; andqi3 instruction pattern(s).
5419 (define_insn "*andqi3_zarch"
5420 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5421 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5422 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5423 (clobber (reg:CC 33))]
5424 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5431 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5433 (define_insn "*andqi3_esa"
5434 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5435 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5436 (match_operand:QI 2 "general_operand" "d,n,Q")))
5437 (clobber (reg:CC 33))]
5438 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5443 [(set_attr "op_type" "RR,SI,SS")])
5445 (define_expand "andqi3"
5446 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5447 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
5448 (match_operand:QI 2 "general_operand" "")))
5449 (clobber (reg:CC 33))]
5451 "s390_expand_logical_operator (AND, QImode, operands); DONE;")
5454 ; Block and (NC) patterns.
5458 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5459 (and:BLK (match_dup 0)
5460 (match_operand:BLK 1 "memory_operand" "Q")))
5461 (use (match_operand 2 "const_int_operand" "n"))
5462 (clobber (reg:CC 33))]
5463 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5464 "nc\t%O0(%2,%R0),%S1"
5465 [(set_attr "op_type" "SS")])
5468 [(set (match_operand 0 "memory_operand" "")
5470 (match_operand 1 "memory_operand" "")))
5471 (clobber (reg:CC 33))]
5473 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5474 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5476 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5478 (clobber (reg:CC 33))])]
5480 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5481 operands[0] = adjust_address (operands[0], BLKmode, 0);
5482 operands[1] = adjust_address (operands[1], BLKmode, 0);
5487 [(set (match_operand:BLK 0 "memory_operand" "")
5488 (and:BLK (match_dup 0)
5489 (match_operand:BLK 1 "memory_operand" "")))
5490 (use (match_operand 2 "const_int_operand" ""))
5491 (clobber (reg:CC 33))])
5493 [(set (match_operand:BLK 3 "memory_operand" "")
5494 (and:BLK (match_dup 3)
5495 (match_operand:BLK 4 "memory_operand" "")))
5496 (use (match_operand 5 "const_int_operand" ""))
5497 (clobber (reg:CC 33))])]
5498 "s390_offset_p (operands[0], operands[3], operands[2])
5499 && s390_offset_p (operands[1], operands[4], operands[2])
5500 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5502 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5504 (clobber (reg:CC 33))])]
5505 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5506 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5507 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5511 ;;- Bit set (inclusive or) instructions.
5515 ; iordi3 instruction pattern(s).
5518 (define_insn "*iordi3_cc"
5520 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5521 (match_operand:DI 2 "general_operand" "d,m"))
5523 (set (match_operand:DI 0 "register_operand" "=d,d")
5524 (ior:DI (match_dup 1) (match_dup 2)))]
5525 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5529 [(set_attr "op_type" "RRE,RXY")])
5531 (define_insn "*iordi3_cconly"
5533 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5534 (match_operand:DI 2 "general_operand" "d,m"))
5536 (clobber (match_scratch:DI 0 "=d,d"))]
5537 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5541 [(set_attr "op_type" "RRE,RXY")])
5543 (define_insn "*iordi3"
5544 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5545 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5546 (match_operand:DI 2 "general_operand"
5547 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5548 (clobber (reg:CC 33))]
5549 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5559 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5562 [(set (match_operand:DI 0 "s_operand" "")
5563 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5564 (clobber (reg:CC 33))]
5567 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5568 (clobber (reg:CC 33))])]
5569 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5571 (define_expand "iordi3"
5572 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5573 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
5574 (match_operand:DI 2 "general_operand" "")))
5575 (clobber (reg:CC 33))]
5577 "s390_expand_logical_operator (IOR, DImode, operands); DONE;")
5580 ; iorsi3 instruction pattern(s).
5583 (define_insn "*iorsi3_cc"
5585 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5586 (match_operand:SI 2 "general_operand" "d,R,T"))
5588 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5589 (ior:SI (match_dup 1) (match_dup 2)))]
5590 "s390_match_ccmode(insn, CCTmode)"
5595 [(set_attr "op_type" "RR,RX,RXY")])
5597 (define_insn "*iorsi3_cconly"
5599 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5600 (match_operand:SI 2 "general_operand" "d,R,T"))
5602 (clobber (match_scratch:SI 0 "=d,d,d"))]
5603 "s390_match_ccmode(insn, CCTmode)"
5608 [(set_attr "op_type" "RR,RX,RXY")])
5610 (define_insn "*iorsi3_zarch"
5611 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
5612 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
5613 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
5614 (clobber (reg:CC 33))]
5615 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5624 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
5626 (define_insn "*iorsi3_esa"
5627 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5628 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5629 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5630 (clobber (reg:CC 33))]
5631 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5637 [(set_attr "op_type" "RR,RX,SI,SS")])
5640 [(set (match_operand:SI 0 "s_operand" "")
5641 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5642 (clobber (reg:CC 33))]
5645 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5646 (clobber (reg:CC 33))])]
5647 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5649 (define_expand "iorsi3"
5650 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5651 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
5652 (match_operand:SI 2 "general_operand" "")))
5653 (clobber (reg:CC 33))]
5655 "s390_expand_logical_operator (IOR, SImode, operands); DONE;")
5658 ; iorhi3 instruction pattern(s).
5661 (define_insn "*iorhi3_zarch"
5662 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5663 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5664 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5665 (clobber (reg:CC 33))]
5666 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5672 [(set_attr "op_type" "RR,RI,SI,SS")])
5674 (define_insn "*iorhi3_esa"
5675 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5676 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5677 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5678 (clobber (reg:CC 33))]
5679 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5684 [(set_attr "op_type" "RR,SI,SS")])
5687 [(set (match_operand:HI 0 "s_operand" "")
5688 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5689 (clobber (reg:CC 33))]
5692 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5693 (clobber (reg:CC 33))])]
5694 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5696 (define_expand "iorhi3"
5697 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5698 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
5699 (match_operand:HI 2 "general_operand" "")))
5700 (clobber (reg:CC 33))]
5702 "s390_expand_logical_operator (IOR, HImode, operands); DONE;")
5705 ; iorqi3 instruction pattern(s).
5708 (define_insn "*iorqi3_zarch"
5709 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5710 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5711 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5712 (clobber (reg:CC 33))]
5713 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5720 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5722 (define_insn "*iorqi3_esa"
5723 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5724 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5725 (match_operand:QI 2 "general_operand" "d,n,Q")))
5726 (clobber (reg:CC 33))]
5727 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5732 [(set_attr "op_type" "RR,SI,SS")])
5734 (define_expand "iorqi3"
5735 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5736 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
5737 (match_operand:QI 2 "general_operand" "")))
5738 (clobber (reg:CC 33))]
5740 "s390_expand_logical_operator (IOR, QImode, operands); DONE;")
5743 ; Block inclusive or (OC) patterns.
5747 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5748 (ior:BLK (match_dup 0)
5749 (match_operand:BLK 1 "memory_operand" "Q")))
5750 (use (match_operand 2 "const_int_operand" "n"))
5751 (clobber (reg:CC 33))]
5752 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5753 "oc\t%O0(%2,%R0),%S1"
5754 [(set_attr "op_type" "SS")])
5757 [(set (match_operand 0 "memory_operand" "")
5759 (match_operand 1 "memory_operand" "")))
5760 (clobber (reg:CC 33))]
5762 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5763 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5765 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5767 (clobber (reg:CC 33))])]
5769 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5770 operands[0] = adjust_address (operands[0], BLKmode, 0);
5771 operands[1] = adjust_address (operands[1], BLKmode, 0);
5776 [(set (match_operand:BLK 0 "memory_operand" "")
5777 (ior:BLK (match_dup 0)
5778 (match_operand:BLK 1 "memory_operand" "")))
5779 (use (match_operand 2 "const_int_operand" ""))
5780 (clobber (reg:CC 33))])
5782 [(set (match_operand:BLK 3 "memory_operand" "")
5783 (ior:BLK (match_dup 3)
5784 (match_operand:BLK 4 "memory_operand" "")))
5785 (use (match_operand 5 "const_int_operand" ""))
5786 (clobber (reg:CC 33))])]
5787 "s390_offset_p (operands[0], operands[3], operands[2])
5788 && s390_offset_p (operands[1], operands[4], operands[2])
5789 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5791 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5793 (clobber (reg:CC 33))])]
5794 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5795 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5796 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5800 ;;- Xor instructions.
5804 ; xordi3 instruction pattern(s).
5807 (define_insn "*xordi3_cc"
5809 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5810 (match_operand:DI 2 "general_operand" "d,m"))
5812 (set (match_operand:DI 0 "register_operand" "=d,d")
5813 (xor:DI (match_dup 1) (match_dup 2)))]
5814 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5818 [(set_attr "op_type" "RRE,RXY")])
5820 (define_insn "*xordi3_cconly"
5822 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5823 (match_operand:DI 2 "general_operand" "d,m"))
5825 (clobber (match_scratch:DI 0 "=d,d"))]
5826 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5830 [(set_attr "op_type" "RRE,RXY")])
5832 (define_insn "*xordi3"
5833 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5834 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5835 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5836 (clobber (reg:CC 33))]
5837 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5843 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5846 [(set (match_operand:DI 0 "s_operand" "")
5847 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5848 (clobber (reg:CC 33))]
5851 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5852 (clobber (reg:CC 33))])]
5853 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5855 (define_expand "xordi3"
5856 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5857 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
5858 (match_operand:DI 2 "general_operand" "")))
5859 (clobber (reg:CC 33))]
5861 "s390_expand_logical_operator (XOR, DImode, operands); DONE;")
5864 ; xorsi3 instruction pattern(s).
5867 (define_insn "*xorsi3_cc"
5869 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5870 (match_operand:SI 2 "general_operand" "d,R,T"))
5872 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5873 (xor:SI (match_dup 1) (match_dup 2)))]
5874 "s390_match_ccmode(insn, CCTmode)"
5879 [(set_attr "op_type" "RR,RX,RXY")])
5881 (define_insn "*xorsi3_cconly"
5883 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5884 (match_operand:SI 2 "general_operand" "d,R,T"))
5886 (clobber (match_scratch:SI 0 "=d,d,d"))]
5887 "s390_match_ccmode(insn, CCTmode)"
5892 [(set_attr "op_type" "RR,RX,RXY")])
5894 (define_insn "*xorsi3"
5895 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5896 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5897 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5898 (clobber (reg:CC 33))]
5899 "s390_logical_operator_ok_p (operands)"
5906 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5909 [(set (match_operand:SI 0 "s_operand" "")
5910 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5911 (clobber (reg:CC 33))]
5914 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5915 (clobber (reg:CC 33))])]
5916 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5918 (define_expand "xorsi3"
5919 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5920 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
5921 (match_operand:SI 2 "general_operand" "")))
5922 (clobber (reg:CC 33))]
5924 "s390_expand_logical_operator (XOR, SImode, operands); DONE;")
5927 ; xorhi3 instruction pattern(s).
5930 (define_insn "*xorhi3"
5931 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5932 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5933 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5934 (clobber (reg:CC 33))]
5935 "s390_logical_operator_ok_p (operands)"
5940 [(set_attr "op_type" "RR,SI,SS")])
5943 [(set (match_operand:HI 0 "s_operand" "")
5944 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5945 (clobber (reg:CC 33))]
5948 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5949 (clobber (reg:CC 33))])]
5950 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5952 (define_expand "xorhi3"
5953 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5954 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
5955 (match_operand:HI 2 "general_operand" "")))
5956 (clobber (reg:CC 33))]
5958 "s390_expand_logical_operator (XOR, HImode, operands); DONE;")
5961 ; xorqi3 instruction pattern(s).
5964 (define_insn "*xorqi3"
5965 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5966 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5967 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5968 (clobber (reg:CC 33))]
5969 "s390_logical_operator_ok_p (operands)"
5975 [(set_attr "op_type" "RR,SI,SIY,SS")])
5977 (define_expand "xorqi3"
5978 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5979 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
5980 (match_operand:QI 2 "general_operand" "")))
5981 (clobber (reg:CC 33))]
5983 "s390_expand_logical_operator (XOR, QImode, operands); DONE;")
5986 ; Block exclusive or (XC) patterns.
5990 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5991 (xor:BLK (match_dup 0)
5992 (match_operand:BLK 1 "memory_operand" "Q")))
5993 (use (match_operand 2 "const_int_operand" "n"))
5994 (clobber (reg:CC 33))]
5995 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5996 "xc\t%O0(%2,%R0),%S1"
5997 [(set_attr "op_type" "SS")])
6000 [(set (match_operand 0 "memory_operand" "")
6002 (match_operand 1 "memory_operand" "")))
6003 (clobber (reg:CC 33))]
6005 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6006 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6008 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6010 (clobber (reg:CC 33))])]
6012 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6013 operands[0] = adjust_address (operands[0], BLKmode, 0);
6014 operands[1] = adjust_address (operands[1], BLKmode, 0);
6019 [(set (match_operand:BLK 0 "memory_operand" "")
6020 (xor:BLK (match_dup 0)
6021 (match_operand:BLK 1 "memory_operand" "")))
6022 (use (match_operand 2 "const_int_operand" ""))
6023 (clobber (reg:CC 33))])
6025 [(set (match_operand:BLK 3 "memory_operand" "")
6026 (xor:BLK (match_dup 3)
6027 (match_operand:BLK 4 "memory_operand" "")))
6028 (use (match_operand 5 "const_int_operand" ""))
6029 (clobber (reg:CC 33))])]
6030 "s390_offset_p (operands[0], operands[3], operands[2])
6031 && s390_offset_p (operands[1], operands[4], operands[2])
6032 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6034 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6036 (clobber (reg:CC 33))])]
6037 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6038 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6039 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6042 ; Block xor (XC) patterns with src == dest.
6045 (define_insn "*xc_zero"
6046 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6048 (use (match_operand 1 "const_int_operand" "n"))
6049 (clobber (reg:CC 33))]
6050 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6051 "xc\t%O0(%1,%R0),%S0"
6052 [(set_attr "op_type" "SS")])
6056 [(set (match_operand:BLK 0 "memory_operand" "")
6058 (use (match_operand 1 "const_int_operand" ""))
6059 (clobber (reg:CC 33))])
6061 [(set (match_operand:BLK 2 "memory_operand" "")
6063 (use (match_operand 3 "const_int_operand" ""))
6064 (clobber (reg:CC 33))])]
6065 "s390_offset_p (operands[0], operands[2], operands[1])
6066 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6068 [(set (match_dup 4) (const_int 0))
6070 (clobber (reg:CC 33))])]
6071 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6072 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6076 ;;- Negate instructions.
6080 ; negdi2 instruction pattern(s).
6083 (define_expand "negdi2"
6085 [(set (match_operand:DI 0 "register_operand" "=d")
6086 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6087 (clobber (reg:CC 33))])]
6091 (define_insn "*negdi2_sign_cc"
6093 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6094 (match_operand:SI 1 "register_operand" "d") 0)
6095 (const_int 32)) (const_int 32)))
6097 (set (match_operand:DI 0 "register_operand" "=d")
6098 (neg:DI (sign_extend:DI (match_dup 1))))]
6099 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6101 [(set_attr "op_type" "RRE")])
6103 (define_insn "*negdi2_sign"
6104 [(set (match_operand:DI 0 "register_operand" "=d")
6105 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6106 (clobber (reg:CC 33))]
6109 [(set_attr "op_type" "RRE")])
6111 (define_insn "*negdi2_cc"
6113 (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
6115 (set (match_operand:DI 0 "register_operand" "=d")
6116 (neg:DI (match_dup 1)))]
6117 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6119 [(set_attr "op_type" "RRE")])
6121 (define_insn "*negdi2_cconly"
6123 (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
6125 (clobber (match_scratch:DI 0 "=d"))]
6126 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6128 [(set_attr "op_type" "RRE")])
6130 (define_insn "*negdi2_64"
6131 [(set (match_operand:DI 0 "register_operand" "=d")
6132 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6133 (clobber (reg:CC 33))]
6136 [(set_attr "op_type" "RRE")])
6138 (define_insn_and_split "*negdi2_31"
6139 [(set (match_operand:DI 0 "register_operand" "=d")
6140 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6141 (clobber (reg:CC 33))]
6144 "&& reload_completed"
6146 [(set (match_dup 2) (neg:SI (match_dup 3)))
6147 (clobber (reg:CC 33))])
6150 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6151 (set (match_dup 4) (neg:SI (match_dup 5)))])
6153 (if_then_else (ne (reg:CCAP 33) (const_int 0))
6155 (label_ref (match_dup 6))))
6157 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6158 (clobber (reg:CC 33))])
6160 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6161 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6162 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6163 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6164 operands[6] = gen_label_rtx ();")
6167 ; negsi2 instruction pattern(s).
6170 (define_insn "*negsi2_cc"
6172 (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
6174 (set (match_operand:SI 0 "register_operand" "=d")
6175 (neg:SI (match_dup 1)))]
6176 "s390_match_ccmode (insn, CCAmode)"
6178 [(set_attr "op_type" "RR")])
6180 (define_insn "*negsi2_cconly"
6182 (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
6184 (clobber (match_scratch:SI 0 "=d"))]
6185 "s390_match_ccmode (insn, CCAmode)"
6187 [(set_attr "op_type" "RR")])
6189 (define_insn "negsi2"
6190 [(set (match_operand:SI 0 "register_operand" "=d")
6191 (neg:SI (match_operand:SI 1 "register_operand" "d")))
6192 (clobber (reg:CC 33))]
6195 [(set_attr "op_type" "RR")])
6198 ; negdf2 instruction pattern(s).
6201 (define_expand "negdf2"
6203 [(set (match_operand:DF 0 "register_operand" "=f")
6204 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6205 (clobber (reg:CC 33))])]
6209 (define_insn "*negdf2_cc"
6211 (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
6212 (match_operand:DF 2 "const0_operand" "")))
6213 (set (match_operand:DF 0 "register_operand" "=f")
6214 (neg:DF (match_dup 1)))]
6215 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6217 [(set_attr "op_type" "RRE")
6218 (set_attr "type" "fsimpd")])
6220 (define_insn "*negdf2_cconly"
6222 (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
6223 (match_operand:DF 2 "const0_operand" "")))
6224 (clobber (match_scratch:DF 0 "=f"))]
6225 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6227 [(set_attr "op_type" "RRE")
6228 (set_attr "type" "fsimpd")])
6230 (define_insn "*negdf2"
6231 [(set (match_operand:DF 0 "register_operand" "=f")
6232 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6233 (clobber (reg:CC 33))]
6234 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6236 [(set_attr "op_type" "RRE")
6237 (set_attr "type" "fsimpd")])
6239 (define_insn "*negdf2_ibm"
6240 [(set (match_operand:DF 0 "register_operand" "=f")
6241 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6242 (clobber (reg:CC 33))]
6243 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6245 [(set_attr "op_type" "RR")
6246 (set_attr "type" "fsimpd")])
6249 ; negsf2 instruction pattern(s).
6252 (define_expand "negsf2"
6254 [(set (match_operand:SF 0 "register_operand" "=f")
6255 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6256 (clobber (reg:CC 33))])]
6260 (define_insn "*negsf2_cc"
6262 (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
6263 (match_operand:SF 2 "const0_operand" "")))
6264 (set (match_operand:SF 0 "register_operand" "=f")
6265 (neg:SF (match_dup 1)))]
6266 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6268 [(set_attr "op_type" "RRE")
6269 (set_attr "type" "fsimps")])
6271 (define_insn "*negsf2_cconly"
6273 (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
6274 (match_operand:SF 2 "const0_operand" "")))
6275 (clobber (match_scratch:SF 0 "=f"))]
6276 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6278 [(set_attr "op_type" "RRE")
6279 (set_attr "type" "fsimps")])
6281 (define_insn "*negsf2"
6282 [(set (match_operand:SF 0 "register_operand" "=f")
6283 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6284 (clobber (reg:CC 33))]
6285 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6287 [(set_attr "op_type" "RRE")
6288 (set_attr "type" "fsimps")])
6290 (define_insn "*negsf2"
6291 [(set (match_operand:SF 0 "register_operand" "=f")
6292 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6293 (clobber (reg:CC 33))]
6294 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6296 [(set_attr "op_type" "RR")
6297 (set_attr "type" "fsimps")])
6301 ;;- Absolute value instructions.
6305 ; absdi2 instruction pattern(s).
6308 (define_insn "*absdi2_sign_cc"
6310 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6311 (match_operand:SI 1 "register_operand" "d") 0)
6312 (const_int 32)) (const_int 32)))
6314 (set (match_operand:DI 0 "register_operand" "=d")
6315 (abs:DI (sign_extend:DI (match_dup 1))))]
6316 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6318 [(set_attr "op_type" "RRE")])
6320 (define_insn "*absdi2_sign"
6321 [(set (match_operand:DI 0 "register_operand" "=d")
6322 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6323 (clobber (reg:CC 33))]
6326 [(set_attr "op_type" "RRE")])
6328 (define_insn "*absdi2_cc"
6330 (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
6332 (set (match_operand:DI 0 "register_operand" "=d")
6333 (abs:DI (match_dup 1)))]
6334 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6336 [(set_attr "op_type" "RRE")])
6338 (define_insn "*absdi2_cconly"
6340 (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
6342 (clobber (match_scratch:DI 0 "=d"))]
6343 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6345 [(set_attr "op_type" "RRE")])
6347 (define_insn "absdi2"
6348 [(set (match_operand:DI 0 "register_operand" "=d")
6349 (abs:DI (match_operand:DI 1 "register_operand" "d")))
6350 (clobber (reg:CC 33))]
6353 [(set_attr "op_type" "RRE")])
6356 ; abssi2 instruction pattern(s).
6359 (define_insn "*abssi2_cc"
6361 (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
6363 (set (match_operand:SI 0 "register_operand" "=d")
6364 (abs:SI (match_dup 1)))]
6365 "s390_match_ccmode (insn, CCAmode)"
6367 [(set_attr "op_type" "RR")])
6369 (define_insn "*abssi2_cconly"
6371 (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
6373 (clobber (match_scratch:SI 0 "=d"))]
6374 "s390_match_ccmode (insn, CCAmode)"
6376 [(set_attr "op_type" "RR")])
6378 (define_insn "abssi2"
6379 [(set (match_operand:SI 0 "register_operand" "=d")
6380 (abs:SI (match_operand:SI 1 "register_operand" "d")))
6381 (clobber (reg:CC 33))]
6384 [(set_attr "op_type" "RR")])
6387 ; absdf2 instruction pattern(s).
6390 (define_expand "absdf2"
6392 [(set (match_operand:DF 0 "register_operand" "=f")
6393 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6394 (clobber (reg:CC 33))])]
6398 (define_insn "*absdf2_cc"
6400 (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
6401 (match_operand:DF 2 "const0_operand" "")))
6402 (set (match_operand:DF 0 "register_operand" "=f")
6403 (abs:DF (match_dup 1)))]
6404 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6406 [(set_attr "op_type" "RRE")
6407 (set_attr "type" "fsimpd")])
6409 (define_insn "*absdf2_cconly"
6411 (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
6412 (match_operand:DF 2 "const0_operand" "")))
6413 (clobber (match_scratch:DF 0 "=f"))]
6414 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6416 [(set_attr "op_type" "RRE")
6417 (set_attr "type" "fsimpd")])
6419 (define_insn "*absdf2"
6420 [(set (match_operand:DF 0 "register_operand" "=f")
6421 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6422 (clobber (reg:CC 33))]
6423 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6425 [(set_attr "op_type" "RRE")
6426 (set_attr "type" "fsimpd")])
6428 (define_insn "*absdf2_ibm"
6429 [(set (match_operand:DF 0 "register_operand" "=f")
6430 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6431 (clobber (reg:CC 33))]
6432 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6434 [(set_attr "op_type" "RR")
6435 (set_attr "type" "fsimpd")])
6438 ; abssf2 instruction pattern(s).
6441 (define_expand "abssf2"
6443 [(set (match_operand:SF 0 "register_operand" "=f")
6444 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6445 (clobber (reg:CC 33))])]
6449 (define_insn "*abssf2_cc"
6451 (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
6452 (match_operand:SF 2 "const0_operand" "")))
6453 (set (match_operand:SF 0 "register_operand" "=f")
6454 (abs:SF (match_dup 1)))]
6455 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6457 [(set_attr "op_type" "RRE")
6458 (set_attr "type" "fsimps")])
6460 (define_insn "*abssf2_cconly"
6462 (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
6463 (match_operand:SF 2 "const0_operand" "")))
6464 (clobber (match_scratch:SF 0 "=f"))]
6465 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6467 [(set_attr "op_type" "RRE")
6468 (set_attr "type" "fsimps")])
6470 (define_insn "*abssf2"
6471 [(set (match_operand:SF 0 "register_operand" "=f")
6472 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6473 (clobber (reg:CC 33))]
6474 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6476 [(set_attr "op_type" "RRE")
6477 (set_attr "type" "fsimps")])
6479 (define_insn "*abssf2_ibm"
6480 [(set (match_operand:SF 0 "register_operand" "=f")
6481 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6482 (clobber (reg:CC 33))]
6483 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6485 [(set_attr "op_type" "RR")
6486 (set_attr "type" "fsimps")])
6489 ;;- Negated absolute value instructions
6496 (define_insn "*negabsdi2_sign_cc"
6498 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6499 (match_operand:SI 1 "register_operand" "d") 0)
6500 (const_int 32)) (const_int 32))))
6502 (set (match_operand:DI 0 "register_operand" "=d")
6503 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6504 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6506 [(set_attr "op_type" "RRE")])
6508 (define_insn "*negabsdi2_sign"
6509 [(set (match_operand:DI 0 "register_operand" "=d")
6510 (neg:DI (abs:DI (sign_extend:DI
6511 (match_operand:SI 1 "register_operand" "d")))))
6512 (clobber (reg:CC 33))]
6515 [(set_attr "op_type" "RRE")])
6517 (define_insn "*negabsdi2_cc"
6519 (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
6521 (set (match_operand:DI 0 "register_operand" "=d")
6522 (neg:DI (abs:DI (match_dup 1))))]
6523 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6525 [(set_attr "op_type" "RRE")])
6527 (define_insn "*negabsdi2_cconly"
6529 (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
6531 (clobber (match_scratch:DI 0 "=d"))]
6532 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6534 [(set_attr "op_type" "RRE")])
6536 (define_insn "*negabsdi2"
6537 [(set (match_operand:DI 0 "register_operand" "=d")
6538 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
6539 (clobber (reg:CC 33))]
6542 [(set_attr "op_type" "RRE")])
6544 (define_insn "*negabssi2_cc"
6546 (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
6548 (set (match_operand:SI 0 "register_operand" "=d")
6549 (neg:SI (abs:SI (match_dup 1))))]
6550 "s390_match_ccmode (insn, CCAmode)"
6552 [(set_attr "op_type" "RR")])
6554 (define_insn "*negabssi2_cconly"
6556 (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
6558 (clobber (match_scratch:SI 0 "=d"))]
6559 "s390_match_ccmode (insn, CCAmode)"
6561 [(set_attr "op_type" "RR")])
6563 (define_insn "*negabssi2"
6564 [(set (match_operand:SI 0 "register_operand" "=d")
6565 (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
6566 (clobber (reg:CC 33))]
6569 [(set_attr "op_type" "RR")])
6575 (define_insn "*negabsdf2_cc"
6577 (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
6578 (match_operand:DF 2 "const0_operand" "")))
6579 (set (match_operand:DF 0 "register_operand" "=f")
6580 (neg:DF (abs:DF (match_dup 1))))]
6581 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6583 [(set_attr "op_type" "RRE")
6584 (set_attr "type" "fsimpd")])
6586 (define_insn "*negabsdf2_cconly"
6588 (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
6589 (match_operand:DF 2 "const0_operand" "")))
6590 (clobber (match_scratch:DF 0 "=f"))]
6591 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6593 [(set_attr "op_type" "RRE")
6594 (set_attr "type" "fsimpd")])
6596 (define_insn "*negabsdf2"
6597 [(set (match_operand:DF 0 "register_operand" "=f")
6598 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6599 (clobber (reg:CC 33))]
6600 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6602 [(set_attr "op_type" "RRE")
6603 (set_attr "type" "fsimpd")])
6605 (define_insn "*negabssf2_cc"
6607 (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
6608 (match_operand:SF 2 "const0_operand" "")))
6609 (set (match_operand:SF 0 "register_operand" "=f")
6610 (neg:SF (abs:SF (match_dup 1))))]
6611 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6613 [(set_attr "op_type" "RRE")
6614 (set_attr "type" "fsimps")])
6616 (define_insn "*negabssf2_cconly"
6618 (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
6619 (match_operand:SF 2 "const0_operand" "")))
6620 (clobber (match_scratch:SF 0 "=f"))]
6621 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6623 [(set_attr "op_type" "RRE")
6624 (set_attr "type" "fsimps")])
6626 (define_insn "*negabssf2"
6627 [(set (match_operand:SF 0 "register_operand" "=f")
6628 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6629 (clobber (reg:CC 33))]
6630 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6632 [(set_attr "op_type" "RRE")
6633 (set_attr "type" "fsimps")])
6636 ;;- Square root instructions.
6640 ; sqrtdf2 instruction pattern(s).
6643 (define_insn "sqrtdf2"
6644 [(set (match_operand:DF 0 "register_operand" "=f,f")
6645 (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
6646 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6650 [(set_attr "op_type" "RRE,RXE")
6651 (set_attr "type" "fsqrtd")])
6654 ; sqrtsf2 instruction pattern(s).
6657 (define_insn "sqrtsf2"
6658 [(set (match_operand:SF 0 "register_operand" "=f,f")
6659 (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
6660 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6664 [(set_attr "op_type" "RRE,RXE")
6665 (set_attr "type" "fsqrts")])
6668 ;;- One complement instructions.
6672 ; one_cmpldi2 instruction pattern(s).
6675 (define_expand "one_cmpldi2"
6677 [(set (match_operand:DI 0 "register_operand" "")
6678 (xor:DI (match_operand:DI 1 "register_operand" "")
6680 (clobber (reg:CC 33))])]
6685 ; one_cmplsi2 instruction pattern(s).
6688 (define_expand "one_cmplsi2"
6690 [(set (match_operand:SI 0 "register_operand" "")
6691 (xor:SI (match_operand:SI 1 "register_operand" "")
6693 (clobber (reg:CC 33))])]
6698 ; one_cmplhi2 instruction pattern(s).
6701 (define_expand "one_cmplhi2"
6703 [(set (match_operand:HI 0 "register_operand" "")
6704 (xor:HI (match_operand:HI 1 "register_operand" "")
6706 (clobber (reg:CC 33))])]
6711 ; one_cmplqi2 instruction pattern(s).
6714 (define_expand "one_cmplqi2"
6716 [(set (match_operand:QI 0 "register_operand" "")
6717 (xor:QI (match_operand:QI 1 "register_operand" "")
6719 (clobber (reg:CC 33))])]
6725 ;;- Rotate instructions.
6729 ; rotldi3 instruction pattern(s).
6732 (define_insn "rotldi3"
6733 [(set (match_operand:DI 0 "register_operand" "=d")
6734 (rotate:DI (match_operand:DI 1 "register_operand" "d")
6735 (match_operand:SI 2 "shift_count_operand" "Y")))]
6738 [(set_attr "op_type" "RSE")
6739 (set_attr "atype" "reg")])
6742 ; rotlsi3 instruction pattern(s).
6745 (define_insn "rotlsi3"
6746 [(set (match_operand:SI 0 "register_operand" "=d")
6747 (rotate:SI (match_operand:SI 1 "register_operand" "d")
6748 (match_operand:SI 2 "shift_count_operand" "Y")))]
6751 [(set_attr "op_type" "RSE")
6752 (set_attr "atype" "reg")])
6756 ;;- Arithmetic shift instructions.
6760 ; ashldi3 instruction pattern(s).
6763 (define_expand "ashldi3"
6764 [(set (match_operand:DI 0 "register_operand" "")
6765 (ashift:DI (match_operand:DI 1 "register_operand" "")
6766 (match_operand:SI 2 "shift_count_operand" "")))]
6770 (define_insn "*ashldi3_31"
6771 [(set (match_operand:DI 0 "register_operand" "=d")
6772 (ashift:DI (match_operand:DI 1 "register_operand" "0")
6773 (match_operand:SI 2 "shift_count_operand" "Y")))]
6776 [(set_attr "op_type" "RS")
6777 (set_attr "atype" "reg")])
6779 (define_insn "*ashldi3_64"
6780 [(set (match_operand:DI 0 "register_operand" "=d")
6781 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6782 (match_operand:SI 2 "shift_count_operand" "Y")))]
6785 [(set_attr "op_type" "RSE")
6786 (set_attr "atype" "reg")])
6789 ; ashrdi3 instruction pattern(s).
6792 (define_expand "ashrdi3"
6794 [(set (match_operand:DI 0 "register_operand" "")
6795 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6796 (match_operand:SI 2 "shift_count_operand" "")))
6797 (clobber (reg:CC 33))])]
6801 (define_insn "*ashrdi3_cc_31"
6803 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6804 (match_operand:SI 2 "shift_count_operand" "Y"))
6806 (set (match_operand:DI 0 "register_operand" "=d")
6807 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6808 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6810 [(set_attr "op_type" "RS")
6811 (set_attr "atype" "reg")])
6813 (define_insn "*ashrdi3_cconly_31"
6815 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6816 (match_operand:SI 2 "shift_count_operand" "Y"))
6818 (clobber (match_scratch:DI 0 "=d"))]
6819 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6821 [(set_attr "op_type" "RS")
6822 (set_attr "atype" "reg")])
6824 (define_insn "*ashrdi3_31"
6825 [(set (match_operand:DI 0 "register_operand" "=d")
6826 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6827 (match_operand:SI 2 "shift_count_operand" "Y")))
6828 (clobber (reg:CC 33))]
6831 [(set_attr "op_type" "RS")
6832 (set_attr "atype" "reg")])
6834 (define_insn "*ashrdi3_cc_64"
6836 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6837 (match_operand:SI 2 "shift_count_operand" "Y"))
6839 (set (match_operand:DI 0 "register_operand" "=d")
6840 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6841 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6843 [(set_attr "op_type" "RSE")
6844 (set_attr "atype" "reg")])
6846 (define_insn "*ashrdi3_cconly_64"
6848 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6849 (match_operand:SI 2 "shift_count_operand" "Y"))
6851 (clobber (match_scratch:DI 0 "=d"))]
6852 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6854 [(set_attr "op_type" "RSE")
6855 (set_attr "atype" "reg")])
6857 (define_insn "*ashrdi3_64"
6858 [(set (match_operand:DI 0 "register_operand" "=d")
6859 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6860 (match_operand:SI 2 "shift_count_operand" "Y")))
6861 (clobber (reg:CC 33))]
6864 [(set_attr "op_type" "RSE")
6865 (set_attr "atype" "reg")])
6869 ; ashlsi3 instruction pattern(s).
6872 (define_insn "ashlsi3"
6873 [(set (match_operand:SI 0 "register_operand" "=d")
6874 (ashift:SI (match_operand:SI 1 "register_operand" "0")
6875 (match_operand:SI 2 "shift_count_operand" "Y")))]
6878 [(set_attr "op_type" "RS")
6879 (set_attr "atype" "reg")])
6882 ; ashrsi3 instruction pattern(s).
6885 (define_insn "*ashrsi3_cc"
6887 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6888 (match_operand:SI 2 "shift_count_operand" "Y"))
6890 (set (match_operand:SI 0 "register_operand" "=d")
6891 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6892 "s390_match_ccmode(insn, CCSmode)"
6894 [(set_attr "op_type" "RS")
6895 (set_attr "atype" "reg")])
6898 (define_insn "*ashrsi3_cconly"
6900 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6901 (match_operand:SI 2 "shift_count_operand" "Y"))
6903 (clobber (match_scratch:SI 0 "=d"))]
6904 "s390_match_ccmode(insn, CCSmode)"
6906 [(set_attr "op_type" "RS")
6907 (set_attr "atype" "reg")])
6909 (define_insn "ashrsi3"
6910 [(set (match_operand:SI 0 "register_operand" "=d")
6911 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6912 (match_operand:SI 2 "shift_count_operand" "Y")))
6913 (clobber (reg:CC 33))]
6916 [(set_attr "op_type" "RS")
6917 (set_attr "atype" "reg")])
6921 ;;- logical shift instructions.
6925 ; lshrdi3 instruction pattern(s).
6928 (define_expand "lshrdi3"
6929 [(set (match_operand:DI 0 "register_operand" "")
6930 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6931 (match_operand:SI 2 "shift_count_operand" "")))]
6935 (define_insn "*lshrdi3_31"
6936 [(set (match_operand:DI 0 "register_operand" "=d")
6937 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
6938 (match_operand:SI 2 "shift_count_operand" "Y")))]
6941 [(set_attr "op_type" "RS")
6942 (set_attr "atype" "reg")])
6944 (define_insn "*lshrdi3_64"
6945 [(set (match_operand:DI 0 "register_operand" "=d")
6946 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
6947 (match_operand:SI 2 "shift_count_operand" "Y")))]
6950 [(set_attr "op_type" "RSE")
6951 (set_attr "atype" "reg")])
6954 ; lshrsi3 instruction pattern(s).
6957 (define_insn "lshrsi3"
6958 [(set (match_operand:SI 0 "register_operand" "=d")
6959 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
6960 (match_operand:SI 2 "shift_count_operand" "Y")))]
6963 [(set_attr "op_type" "RS")
6964 (set_attr "atype" "reg")])
6968 ;; Branch instruction patterns.
6971 (define_expand "beq"
6972 [(match_operand 0 "" "")]
6974 "s390_emit_jump (operands[0],
6975 s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;")
6977 (define_expand "bne"
6978 [(match_operand 0 "" "")]
6980 "s390_emit_jump (operands[0],
6981 s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;")
6983 (define_expand "bgt"
6984 [(match_operand 0 "" "")]
6986 "s390_emit_jump (operands[0],
6987 s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;")
6989 (define_expand "bgtu"
6990 [(match_operand 0 "" "")]
6992 "s390_emit_jump (operands[0],
6993 s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;")
6995 (define_expand "blt"
6996 [(match_operand 0 "" "")]
6998 "s390_emit_jump (operands[0],
6999 s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;")
7001 (define_expand "bltu"
7002 [(match_operand 0 "" "")]
7004 "s390_emit_jump (operands[0],
7005 s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;")
7007 (define_expand "bge"
7008 [(match_operand 0 "" "")]
7010 "s390_emit_jump (operands[0],
7011 s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;")
7013 (define_expand "bgeu"
7014 [(match_operand 0 "" "")]
7016 "s390_emit_jump (operands[0],
7017 s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;")
7019 (define_expand "ble"
7020 [(match_operand 0 "" "")]
7022 "s390_emit_jump (operands[0],
7023 s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;")
7025 (define_expand "bleu"
7026 [(match_operand 0 "" "")]
7028 "s390_emit_jump (operands[0],
7029 s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;")
7031 (define_expand "bunordered"
7032 [(match_operand 0 "" "")]
7034 "s390_emit_jump (operands[0],
7035 s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
7037 (define_expand "bordered"
7038 [(match_operand 0 "" "")]
7040 "s390_emit_jump (operands[0],
7041 s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
7043 (define_expand "buneq"
7044 [(match_operand 0 "" "")]
7046 "s390_emit_jump (operands[0],
7047 s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;")
7049 (define_expand "bunlt"
7050 [(match_operand 0 "" "")]
7052 "s390_emit_jump (operands[0],
7053 s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;")
7055 (define_expand "bungt"
7056 [(match_operand 0 "" "")]
7058 "s390_emit_jump (operands[0],
7059 s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;")
7061 (define_expand "bunle"
7062 [(match_operand 0 "" "")]
7064 "s390_emit_jump (operands[0],
7065 s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;")
7067 (define_expand "bunge"
7068 [(match_operand 0 "" "")]
7070 "s390_emit_jump (operands[0],
7071 s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;")
7073 (define_expand "bltgt"
7074 [(match_operand 0 "" "")]
7076 "s390_emit_jump (operands[0],
7077 s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;")
7081 ;;- Conditional jump instructions.
7084 (define_insn "*cjump_64"
7087 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7088 (label_ref (match_operand 0 "" ""))
7092 if (get_attr_length (insn) == 4)
7095 return "jg%C1\t%l0";
7097 [(set_attr "op_type" "RI")
7098 (set_attr "type" "branch")
7099 (set (attr "length")
7100 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7101 (const_int 4) (const_int 6)))])
7103 (define_insn "*cjump_31"
7106 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7107 (label_ref (match_operand 0 "" ""))
7111 if (get_attr_length (insn) == 4)
7116 [(set_attr "op_type" "RI")
7117 (set_attr "type" "branch")
7118 (set (attr "length")
7119 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7120 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7121 (const_int 4) (const_int 6))
7122 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7123 (const_int 4) (const_int 8))))])
7125 (define_insn "*cjump_long"
7128 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7129 (match_operand 0 "address_operand" "U")
7133 if (get_attr_op_type (insn) == OP_TYPE_RR)
7138 [(set (attr "op_type")
7139 (if_then_else (match_operand 0 "register_operand" "")
7140 (const_string "RR") (const_string "RX")))
7141 (set_attr "type" "branch")
7142 (set_attr "atype" "agen")])
7146 ;;- Negated conditional jump instructions.
7149 (define_insn "*icjump_64"
7152 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7154 (label_ref (match_operand 0 "" ""))))]
7157 if (get_attr_length (insn) == 4)
7160 return "jg%D1\t%l0";
7162 [(set_attr "op_type" "RI")
7163 (set_attr "type" "branch")
7164 (set (attr "length")
7165 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7166 (const_int 4) (const_int 6)))])
7168 (define_insn "*icjump_31"
7171 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7173 (label_ref (match_operand 0 "" ""))))]
7176 if (get_attr_length (insn) == 4)
7181 [(set_attr "op_type" "RI")
7182 (set_attr "type" "branch")
7183 (set (attr "length")
7184 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7185 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7186 (const_int 4) (const_int 6))
7187 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7188 (const_int 4) (const_int 8))))])
7190 (define_insn "*icjump_long"
7193 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7195 (match_operand 0 "address_operand" "U")))]
7198 if (get_attr_op_type (insn) == OP_TYPE_RR)
7203 [(set (attr "op_type")
7204 (if_then_else (match_operand 0 "register_operand" "")
7205 (const_string "RR") (const_string "RX")))
7206 (set_attr "type" "branch")
7207 (set_attr "atype" "agen")])
7210 ;;- Trap instructions.
7214 [(trap_if (const_int 1) (const_int 0))]
7217 [(set_attr "op_type" "RI")
7218 (set_attr "type" "branch")])
7220 (define_expand "conditional_trap"
7221 [(trap_if (match_operand 0 "comparison_operator" "")
7222 (match_operand 1 "general_operand" ""))]
7225 if (operands[1] != const0_rtx) FAIL;
7226 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
7227 s390_compare_op0, s390_compare_op1);
7230 (define_insn "*trap"
7231 [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)])
7235 [(set_attr "op_type" "RI")
7236 (set_attr "type" "branch")])
7239 ;;- Loop instructions.
7241 ;; This is all complicated by the fact that since this is a jump insn
7242 ;; we must handle our own output reloads.
7244 (define_expand "doloop_end"
7245 [(use (match_operand 0 "" "")) ; loop pseudo
7246 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7247 (use (match_operand 2 "" "")) ; max iterations
7248 (use (match_operand 3 "" "")) ; loop level
7249 (use (match_operand 4 "" ""))] ; label
7252 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7253 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7254 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7255 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7256 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7257 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7264 (define_insn_and_split "doloop_si64"
7267 (ne (match_operand:SI 1 "register_operand" "d,d")
7269 (label_ref (match_operand 0 "" ""))
7271 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7272 (plus:SI (match_dup 1) (const_int -1)))
7273 (clobber (match_scratch:SI 3 "=X,&1"))
7274 (clobber (reg:CC 33))]
7277 if (which_alternative != 0)
7279 else if (get_attr_length (insn) == 4)
7280 return "brct\t%1,%l0";
7282 return "ahi\t%1,-1\;jgne\t%l0";
7284 "&& reload_completed
7285 && (! REG_P (operands[2])
7286 || ! rtx_equal_p (operands[1], operands[2]))"
7287 [(parallel [(set (reg:CCAN 33)
7288 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7290 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7291 (set (match_dup 2) (match_dup 3))
7292 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7293 (label_ref (match_dup 0))
7296 [(set_attr "op_type" "RI")
7297 (set_attr "type" "branch")
7298 (set (attr "length")
7299 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7300 (const_int 4) (const_int 10)))])
7302 (define_insn_and_split "doloop_si31"
7305 (ne (match_operand:SI 1 "register_operand" "d,d")
7307 (label_ref (match_operand 0 "" ""))
7309 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7310 (plus:SI (match_dup 1) (const_int -1)))
7311 (clobber (match_scratch:SI 3 "=X,&1"))
7312 (clobber (reg:CC 33))]
7315 if (which_alternative != 0)
7317 else if (get_attr_length (insn) == 4)
7318 return "brct\t%1,%l0";
7322 "&& reload_completed
7323 && (! REG_P (operands[2])
7324 || ! rtx_equal_p (operands[1], operands[2]))"
7325 [(parallel [(set (reg:CCAN 33)
7326 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7328 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7329 (set (match_dup 2) (match_dup 3))
7330 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7331 (label_ref (match_dup 0))
7334 [(set_attr "op_type" "RI")
7335 (set_attr "type" "branch")
7336 (set (attr "length")
7337 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7338 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7339 (const_int 4) (const_int 6))
7340 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7341 (const_int 4) (const_int 8))))])
7343 (define_insn "*doloop_si_long"
7346 (ne (match_operand:SI 1 "register_operand" "d,d")
7348 (match_operand 0 "address_operand" "U,U")
7350 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
7351 (plus:SI (match_dup 1) (const_int -1)))
7352 (clobber (match_scratch:SI 3 "=X,&1"))
7353 (clobber (reg:CC 33))]
7356 if (get_attr_op_type (insn) == OP_TYPE_RR)
7357 return "bctr\t%1,%0";
7359 return "bct\t%1,%a0";
7361 [(set (attr "op_type")
7362 (if_then_else (match_operand 0 "register_operand" "")
7363 (const_string "RR") (const_string "RX")))
7364 (set_attr "type" "branch")
7365 (set_attr "atype" "agen")])
7367 (define_insn_and_split "doloop_di"
7370 (ne (match_operand:DI 1 "register_operand" "d,d")
7372 (label_ref (match_operand 0 "" ""))
7374 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
7375 (plus:DI (match_dup 1) (const_int -1)))
7376 (clobber (match_scratch:DI 3 "=X,&1"))
7377 (clobber (reg:CC 33))]
7380 if (which_alternative != 0)
7382 else if (get_attr_length (insn) == 4)
7383 return "brctg\t%1,%l0";
7385 return "aghi\t%1,-1\;jgne\t%l0";
7387 "&& reload_completed
7388 && (! REG_P (operands[2])
7389 || ! rtx_equal_p (operands[1], operands[2]))"
7390 [(parallel [(set (reg:CCAN 33)
7391 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7393 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7394 (set (match_dup 2) (match_dup 3))
7395 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7396 (label_ref (match_dup 0))
7399 [(set_attr "op_type" "RI")
7400 (set_attr "type" "branch")
7401 (set (attr "length")
7402 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7403 (const_int 4) (const_int 10)))])
7406 ;;- Unconditional jump instructions.
7410 ; jump instruction pattern(s).
7413 (define_expand "jump"
7414 [(match_operand 0 "" "")]
7416 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7418 (define_insn "*jump64"
7419 [(set (pc) (label_ref (match_operand 0 "" "")))]
7422 if (get_attr_length (insn) == 4)
7427 [(set_attr "op_type" "RI")
7428 (set_attr "type" "branch")
7429 (set (attr "length")
7430 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7431 (const_int 4) (const_int 6)))])
7433 (define_insn "*jump31"
7434 [(set (pc) (label_ref (match_operand 0 "" "")))]
7437 if (get_attr_length (insn) == 4)
7442 [(set_attr "op_type" "RI")
7443 (set_attr "type" "branch")
7444 (set (attr "length")
7445 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7446 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7447 (const_int 4) (const_int 6))
7448 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7449 (const_int 4) (const_int 8))))])
7452 ; indirect-jump instruction pattern(s).
7455 (define_insn "indirect_jump"
7456 [(set (pc) (match_operand 0 "address_operand" "U"))]
7459 if (get_attr_op_type (insn) == OP_TYPE_RR)
7464 [(set (attr "op_type")
7465 (if_then_else (match_operand 0 "register_operand" "")
7466 (const_string "RR") (const_string "RX")))
7467 (set_attr "type" "branch")
7468 (set_attr "atype" "agen")])
7471 ; casesi instruction pattern(s).
7474 (define_insn "casesi_jump"
7475 [(set (pc) (match_operand 0 "address_operand" "U"))
7476 (use (label_ref (match_operand 1 "" "")))]
7479 if (get_attr_op_type (insn) == OP_TYPE_RR)
7484 [(set (attr "op_type")
7485 (if_then_else (match_operand 0 "register_operand" "")
7486 (const_string "RR") (const_string "RX")))
7487 (set_attr "type" "branch")
7488 (set_attr "atype" "agen")])
7490 (define_expand "casesi"
7491 [(match_operand:SI 0 "general_operand" "")
7492 (match_operand:SI 1 "general_operand" "")
7493 (match_operand:SI 2 "general_operand" "")
7494 (label_ref (match_operand 3 "" ""))
7495 (label_ref (match_operand 4 "" ""))]
7498 rtx index = gen_reg_rtx (SImode);
7499 rtx base = gen_reg_rtx (Pmode);
7500 rtx target = gen_reg_rtx (Pmode);
7502 emit_move_insn (index, operands[0]);
7503 emit_insn (gen_subsi3 (index, index, operands[1]));
7504 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7507 if (Pmode != SImode)
7508 index = convert_to_mode (Pmode, index, 1);
7509 if (GET_CODE (index) != REG)
7510 index = copy_to_mode_reg (Pmode, index);
7513 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7515 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7517 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7519 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7520 emit_move_insn (target, index);
7523 target = gen_rtx_PLUS (Pmode, base, target);
7524 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7531 ;;- Jump to subroutine.
7536 ; untyped call instruction pattern(s).
7539 ;; Call subroutine returning any type.
7540 (define_expand "untyped_call"
7541 [(parallel [(call (match_operand 0 "" "")
7543 (match_operand 1 "" "")
7544 (match_operand 2 "" "")])]
7549 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7551 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7553 rtx set = XVECEXP (operands[2], 0, i);
7554 emit_move_insn (SET_DEST (set), SET_SRC (set));
7557 /* The optimizer does not know that the call sets the function value
7558 registers we stored in the result block. We avoid problems by
7559 claiming that all hard registers are used and clobbered at this
7561 emit_insn (gen_blockage ());
7566 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7567 ;; all of memory. This blocks insns from being moved across this point.
7569 (define_insn "blockage"
7570 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7573 [(set_attr "type" "none")
7574 (set_attr "length" "0")])
7580 (define_expand "sibcall"
7581 [(call (match_operand 0 "" "")
7582 (match_operand 1 "" ""))]
7585 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7589 (define_insn "*sibcall_br"
7590 [(call (mem:QI (reg 1))
7591 (match_operand 0 "const_int_operand" "n"))]
7592 "SIBLING_CALL_P (insn)
7593 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7595 [(set_attr "op_type" "RR")
7596 (set_attr "type" "branch")
7597 (set_attr "atype" "agen")])
7599 (define_insn "*sibcall_brc"
7600 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7601 (match_operand 1 "const_int_operand" "n"))]
7602 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7604 [(set_attr "op_type" "RI")
7605 (set_attr "type" "branch")])
7607 (define_insn "*sibcall_brcl"
7608 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7609 (match_operand 1 "const_int_operand" "n"))]
7610 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7612 [(set_attr "op_type" "RIL")
7613 (set_attr "type" "branch")])
7616 ; sibcall_value patterns
7619 (define_expand "sibcall_value"
7620 [(set (match_operand 0 "" "")
7621 (call (match_operand 1 "" "")
7622 (match_operand 2 "" "")))]
7625 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7629 (define_insn "*sibcall_value_br"
7630 [(set (match_operand 0 "" "")
7631 (call (mem:QI (reg 1))
7632 (match_operand 1 "const_int_operand" "n")))]
7633 "SIBLING_CALL_P (insn)
7634 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7636 [(set_attr "op_type" "RR")
7637 (set_attr "type" "branch")
7638 (set_attr "atype" "agen")])
7640 (define_insn "*sibcall_value_brc"
7641 [(set (match_operand 0 "" "")
7642 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7643 (match_operand 2 "const_int_operand" "n")))]
7644 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7646 [(set_attr "op_type" "RI")
7647 (set_attr "type" "branch")])
7649 (define_insn "*sibcall_value_brcl"
7650 [(set (match_operand 0 "" "")
7651 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7652 (match_operand 2 "const_int_operand" "n")))]
7653 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7655 [(set_attr "op_type" "RIL")
7656 (set_attr "type" "branch")])
7660 ; call instruction pattern(s).
7663 (define_expand "call"
7664 [(call (match_operand 0 "" "")
7665 (match_operand 1 "" ""))
7666 (use (match_operand 2 "" ""))]
7669 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7670 gen_rtx_REG (Pmode, RETURN_REGNUM));
7674 (define_insn "*bras"
7675 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7676 (match_operand 1 "const_int_operand" "n"))
7677 (clobber (match_operand 2 "register_operand" "=r"))]
7678 "!SIBLING_CALL_P (insn)
7679 && TARGET_SMALL_EXEC
7680 && GET_MODE (operands[2]) == Pmode"
7682 [(set_attr "op_type" "RI")
7683 (set_attr "type" "jsr")])
7685 (define_insn "*brasl"
7686 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7687 (match_operand 1 "const_int_operand" "n"))
7688 (clobber (match_operand 2 "register_operand" "=r"))]
7689 "!SIBLING_CALL_P (insn)
7691 && GET_MODE (operands[2]) == Pmode"
7693 [(set_attr "op_type" "RIL")
7694 (set_attr "type" "jsr")])
7696 (define_insn "*basr"
7697 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7698 (match_operand 1 "const_int_operand" "n"))
7699 (clobber (match_operand 2 "register_operand" "=r"))]
7700 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7702 if (get_attr_op_type (insn) == OP_TYPE_RR)
7703 return "basr\t%2,%0";
7705 return "bas\t%2,%a0";
7707 [(set (attr "op_type")
7708 (if_then_else (match_operand 0 "register_operand" "")
7709 (const_string "RR") (const_string "RX")))
7710 (set_attr "type" "jsr")
7711 (set_attr "atype" "agen")])
7714 ; call_value instruction pattern(s).
7717 (define_expand "call_value"
7718 [(set (match_operand 0 "" "")
7719 (call (match_operand 1 "" "")
7720 (match_operand 2 "" "")))
7721 (use (match_operand 3 "" ""))]
7724 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7725 gen_rtx_REG (Pmode, RETURN_REGNUM));
7729 (define_insn "*bras_r"
7730 [(set (match_operand 0 "" "")
7731 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7732 (match_operand:SI 2 "const_int_operand" "n")))
7733 (clobber (match_operand 3 "register_operand" "=r"))]
7734 "!SIBLING_CALL_P (insn)
7735 && TARGET_SMALL_EXEC
7736 && GET_MODE (operands[3]) == Pmode"
7738 [(set_attr "op_type" "RI")
7739 (set_attr "type" "jsr")])
7741 (define_insn "*brasl_r"
7742 [(set (match_operand 0 "" "")
7743 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7744 (match_operand 2 "const_int_operand" "n")))
7745 (clobber (match_operand 3 "register_operand" "=r"))]
7746 "!SIBLING_CALL_P (insn)
7748 && GET_MODE (operands[3]) == Pmode"
7750 [(set_attr "op_type" "RIL")
7751 (set_attr "type" "jsr")])
7753 (define_insn "*basr_r"
7754 [(set (match_operand 0 "" "")
7755 (call (mem:QI (match_operand 1 "address_operand" "U"))
7756 (match_operand 2 "const_int_operand" "n")))
7757 (clobber (match_operand 3 "register_operand" "=r"))]
7758 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7760 if (get_attr_op_type (insn) == OP_TYPE_RR)
7761 return "basr\t%3,%1";
7763 return "bas\t%3,%a1";
7765 [(set (attr "op_type")
7766 (if_then_else (match_operand 1 "register_operand" "")
7767 (const_string "RR") (const_string "RX")))
7768 (set_attr "type" "jsr")
7769 (set_attr "atype" "agen")])
7772 ;;- Thread-local storage support.
7775 (define_expand "get_tp_64"
7776 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))]
7780 (define_expand "get_tp_31"
7781 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))]
7785 (define_expand "set_tp_64"
7786 [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" ""))
7787 (set (reg:DI 36) (unspec_volatile:DI [(reg:DI 36)] UNSPECV_SET_TP))]
7791 (define_expand "set_tp_31"
7792 [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" ""))
7793 (set (reg:SI 36) (unspec_volatile:SI [(reg:SI 36)] UNSPECV_SET_TP))]
7797 (define_insn "*set_tp"
7798 [(set (reg 36) (unspec_volatile [(reg 36)] UNSPECV_SET_TP))]
7801 [(set_attr "type" "none")
7802 (set_attr "length" "0")])
7804 (define_insn "*tls_load_64"
7805 [(set (match_operand:DI 0 "register_operand" "=d")
7806 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7807 (match_operand:DI 2 "" "")]
7811 [(set_attr "op_type" "RXE")])
7813 (define_insn "*tls_load_31"
7814 [(set (match_operand:SI 0 "register_operand" "=d,d")
7815 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7816 (match_operand:SI 2 "" "")]
7822 [(set_attr "op_type" "RX,RXY")])
7824 (define_insn "*bras_tls"
7825 [(set (match_operand 0 "" "")
7826 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7827 (match_operand 2 "const_int_operand" "n")))
7828 (clobber (match_operand 3 "register_operand" "=r"))
7829 (use (match_operand 4 "" ""))]
7830 "!SIBLING_CALL_P (insn)
7831 && TARGET_SMALL_EXEC
7832 && GET_MODE (operands[3]) == Pmode"
7834 [(set_attr "op_type" "RI")
7835 (set_attr "type" "jsr")])
7837 (define_insn "*brasl_tls"
7838 [(set (match_operand 0 "" "")
7839 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7840 (match_operand 2 "const_int_operand" "n")))
7841 (clobber (match_operand 3 "register_operand" "=r"))
7842 (use (match_operand 4 "" ""))]
7843 "!SIBLING_CALL_P (insn)
7845 && GET_MODE (operands[3]) == Pmode"
7847 [(set_attr "op_type" "RIL")
7848 (set_attr "type" "jsr")])
7850 (define_insn "*basr_tls"
7851 [(set (match_operand 0 "" "")
7852 (call (mem:QI (match_operand 1 "address_operand" "U"))
7853 (match_operand 2 "const_int_operand" "n")))
7854 (clobber (match_operand 3 "register_operand" "=r"))
7855 (use (match_operand 4 "" ""))]
7856 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7858 if (get_attr_op_type (insn) == OP_TYPE_RR)
7859 return "basr\t%3,%1%J4";
7861 return "bas\t%3,%a1%J4";
7863 [(set (attr "op_type")
7864 (if_then_else (match_operand 1 "register_operand" "")
7865 (const_string "RR") (const_string "RX")))
7866 (set_attr "type" "jsr")
7867 (set_attr "atype" "agen")])
7870 ;;- Miscellaneous instructions.
7874 ; allocate stack instruction pattern(s).
7877 (define_expand "allocate_stack"
7878 [(match_operand 0 "general_operand" "")
7879 (match_operand 1 "general_operand" "")]
7882 rtx temp = gen_reg_rtx (Pmode);
7884 emit_move_insn (temp, s390_back_chain_rtx ());
7885 anti_adjust_stack (operands[1]);
7886 emit_move_insn (s390_back_chain_rtx (), temp);
7888 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7894 ; setjmp instruction pattern.
7897 (define_expand "builtin_setjmp_receiver"
7898 [(match_operand 0 "" "")]
7901 emit_insn (s390_load_got ());
7902 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7906 ;; These patterns say how to save and restore the stack pointer. We need not
7907 ;; save the stack pointer at function level since we are careful to
7908 ;; preserve the backchain. At block level, we have to restore the backchain
7909 ;; when we restore the stack pointer.
7911 ;; For nonlocal gotos, we must save both the stack pointer and its
7912 ;; backchain and restore both. Note that in the nonlocal case, the
7913 ;; save area is a memory location.
7915 (define_expand "save_stack_function"
7916 [(match_operand 0 "general_operand" "")
7917 (match_operand 1 "general_operand" "")]
7921 (define_expand "restore_stack_function"
7922 [(match_operand 0 "general_operand" "")
7923 (match_operand 1 "general_operand" "")]
7927 (define_expand "restore_stack_block"
7928 [(match_operand 0 "register_operand" "")
7929 (match_operand 1 "register_operand" "")]
7932 rtx temp = gen_reg_rtx (Pmode);
7934 emit_move_insn (temp, s390_back_chain_rtx ());
7935 emit_move_insn (operands[0], operands[1]);
7936 emit_move_insn (s390_back_chain_rtx (), temp);
7941 (define_expand "save_stack_nonlocal"
7942 [(match_operand 0 "memory_operand" "")
7943 (match_operand 1 "register_operand" "")]
7946 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7947 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7949 /* Copy the backchain to the first word, sp to the second and the
7950 literal pool base to the third. */
7952 if (TARGET_BACKCHAIN)
7954 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7955 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7958 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7959 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7964 (define_expand "restore_stack_nonlocal"
7965 [(match_operand 0 "register_operand" "")
7966 (match_operand 1 "memory_operand" "")]
7969 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7970 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7971 rtx temp = NULL_RTX;
7973 /* Restore the backchain from the first word, sp from the second and the
7974 literal pool base from the third. */
7976 if (TARGET_BACKCHAIN)
7977 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7979 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7980 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7983 emit_move_insn (s390_back_chain_rtx (), temp);
7985 emit_insn (gen_rtx_USE (VOIDmode, base));
7991 ; nop instruction pattern(s).
7998 [(set_attr "op_type" "RR")])
8002 ; Special literal pool access instruction pattern(s).
8005 (define_insn "*pool_entry"
8006 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8007 UNSPECV_POOL_ENTRY)]
8010 enum machine_mode mode = GET_MODE (PATTERN (insn));
8011 unsigned int align = GET_MODE_BITSIZE (mode);
8012 s390_output_pool_entry (operands[0], mode, align);
8015 [(set (attr "length")
8016 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8018 (define_insn "pool_align"
8019 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8020 UNSPECV_POOL_ALIGN)]
8023 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8025 (define_insn "pool_section_start"
8026 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8029 [(set_attr "length" "0")])
8031 (define_insn "pool_section_end"
8032 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8035 [(set_attr "length" "0")])
8037 (define_insn "main_base_31_small"
8038 [(set (match_operand 0 "register_operand" "=a")
8039 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8040 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8042 [(set_attr "op_type" "RR")
8043 (set_attr "type" "la")])
8045 (define_insn "main_base_31_large"
8046 [(set (match_operand 0 "register_operand" "=a")
8047 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8048 (set (pc) (label_ref (match_operand 2 "" "")))]
8049 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8051 [(set_attr "op_type" "RI")])
8053 (define_insn "main_base_64"
8054 [(set (match_operand 0 "register_operand" "=a")
8055 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8056 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8058 [(set_attr "op_type" "RIL")
8059 (set_attr "type" "larl")])
8061 (define_insn "main_pool"
8062 [(set (match_operand 0 "register_operand" "=a")
8063 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8064 "GET_MODE (operands[0]) == Pmode"
8067 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8068 (const_string "larl") (const_string "la")))])
8070 (define_insn "reload_base_31"
8071 [(set (match_operand 0 "register_operand" "=a")
8072 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8073 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8074 "basr\t%0,0\;la\t%0,%1-.(%0)"
8075 [(set_attr "length" "6")
8076 (set_attr "type" "la")])
8078 (define_insn "reload_base_64"
8079 [(set (match_operand 0 "register_operand" "=a")
8080 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8081 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8083 [(set_attr "op_type" "RIL")
8084 (set_attr "type" "larl")])
8087 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8090 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8093 ;; Insns related to generating the function prologue and epilogue.
8097 (define_expand "prologue"
8098 [(use (const_int 0))]
8100 "s390_emit_prologue (); DONE;")
8102 (define_insn "prologue_tpf"
8103 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
8104 (clobber (reg:DI 1))]
8105 "TARGET_TPF_PROFILING"
8107 [(set_attr "type" "jsr")
8108 (set_attr "op_type" "RX")])
8110 (define_expand "epilogue"
8111 [(use (const_int 1))]
8113 "s390_emit_epilogue (false); DONE;")
8115 (define_insn "epilogue_tpf"
8116 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
8117 (clobber (reg:DI 1))]
8118 "TARGET_TPF_PROFILING"
8120 [(set_attr "type" "jsr")
8121 (set_attr "op_type" "RX")])
8124 (define_expand "sibcall_epilogue"
8125 [(use (const_int 0))]
8127 "s390_emit_epilogue (true); DONE;")
8129 (define_insn "*return"
8131 (use (match_operand 0 "register_operand" "a"))]
8132 "GET_MODE (operands[0]) == Pmode"
8134 [(set_attr "op_type" "RR")
8135 (set_attr "type" "jsr")
8136 (set_attr "atype" "agen")])
8139 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8140 ;; pointer. This is used for compatibility.
8142 (define_expand "ptr_extend"
8143 [(set (match_operand:DI 0 "register_operand" "=r")
8144 (match_operand:SI 1 "register_operand" "r"))]
8147 emit_insn (gen_anddi3 (operands[0],
8148 gen_lowpart (DImode, operands[1]),
8149 GEN_INT (0x7fffffff)));
8153 ;; Instruction definition to expand eh_return macro to support
8154 ;; swapping in special linkage return addresses.
8156 (define_expand "eh_return"
8157 [(use (match_operand 0 "register_operand" ""))]
8160 s390_emit_tpf_eh_return (operands[0]);