1 ;; iq2000.md Machine Description for Vitesse IQ2000 processors
2 ;; Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
70 ;; UNSPEC values used in iq2000.md
73 ;; 1 movsi_us, get_fnaddr
75 ;; 20 builtin_setjmp_setup
77 ;; UNSPEC_VOLATILE values
81 ;; 4 exception_receiver
93 ;; ....................
97 ;; ....................
99 ;; Classification of each insn.
100 ;; branch conditional branch
101 ;; jump unconditional jump
102 ;; call unconditional call
103 ;; load load instruction(s)
104 ;; store store instruction(s)
105 ;; move data movement within same register set
106 ;; xfer transfer to/from coprocessor
107 ;; arith integer arithmetic instruction
108 ;; darith double precision integer arithmetic instructions
109 ;; imul integer multiply
110 ;; idiv integer divide
111 ;; icmp integer compare
112 ;; fadd floating point add/subtract
113 ;; fmul floating point multiply
114 ;; fmadd floating point multiply-add
115 ;; fdiv floating point divide
116 ;; fabs floating point absolute value
117 ;; fneg floating point negation
118 ;; fcmp floating point compare
119 ;; fcvt floating point convert
120 ;; fsqrt floating point square root
121 ;; multi multiword sequence (or user asm statements)
125 "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
126 (const_string "unknown"))
128 ;; Main data type used by the insn
129 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
131 ;; Length (in # of bytes). A conditional branch is allowed only to a
132 ;; location within a signed 18-bit offset of the delay slot. If that
133 ;; provides too small a range, we use the `j' instruction. This
134 ;; instruction takes a 28-bit value, but that value is not an offset.
135 ;; Instead, it's bitwise-ored with the high-order four bits of the
136 ;; instruction in the delay slot, which means it cannot be used to
137 ;; cross a 256MB boundary. We could fall back back on the jr,
138 ;; instruction which allows full access to the entire address space,
139 ;; but we do not do so at present.
141 (define_attr "length" ""
142 (cond [(eq_attr "type" "branch")
143 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
151 (const (symbol_ref "iq2000_cpu_attr")))
153 ;; Does the instruction have a mandatory delay slot? has_dslot
154 ;; Can the instruction be in a delay slot? ok_in_dslot
155 ;; Can the instruction not be in a delay slot? not_in_dslot
156 (define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot"
157 (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp")
158 (const_string "has_dslot")
159 (const_string "ok_in_dslot")))
161 ;; Attribute defining whether or not we can use the branch-likely instructions
163 (define_attr "branch_likely" "no,yes"
165 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
167 (const_string "no"))))
170 ;; Describe a user's asm statement.
171 (define_asm_attributes
172 [(set_attr "type" "multi")])
176 ;; .........................
178 ;; Delay slots, can't describe load/fcmp/xfer delay slots here
180 ;; .........................
182 (define_delay (eq_attr "type" "jump")
183 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
187 (define_delay (eq_attr "type" "branch")
188 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
190 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))])
192 (define_delay (eq_attr "type" "call")
193 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
197 (include "predicates.md")
200 ;; .........................
204 ;; .........................
206 (define_automaton "iq2000")
207 (define_cpu_unit "core,memory" "iq2000")
209 (define_insn_reservation "nonmemory" 1
210 (eq_attr "type" "!load,move,store,xfer")
213 (define_insn_reservation "iq2000_load_move" 3
214 (and (eq_attr "type" "load,move")
215 (eq_attr "cpu" "iq2000"))
218 (define_insn_reservation "other_load_move" 1
219 (and (eq_attr "type" "load,move")
220 (eq_attr "cpu" "!iq2000"))
223 (define_insn_reservation "store" 1
224 (eq_attr "type" "store")
227 (define_insn_reservation "xfer" 2
228 (eq_attr "type" "xfer")
232 ;; ....................
236 ;; ....................
240 [(trap_if (const_int 1) (const_int 0))]
248 ;; ....................
252 ;; ....................
255 (define_expand "addsi3"
256 [(set (match_operand:SI 0 "register_operand" "=d")
257 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
258 (match_operand:SI 2 "arith_operand" "dI")))]
262 (define_insn "addsi3_internal"
263 [(set (match_operand:SI 0 "register_operand" "=d,=d")
264 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
265 (match_operand:SI 2 "arith_operand" "d,I")))]
270 [(set_attr "type" "arith")
271 (set_attr "mode" "SI")])
274 ;; ....................
278 ;; ....................
281 (define_expand "subsi3"
282 [(set (match_operand:SI 0 "register_operand" "=d")
283 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
284 (match_operand:SI 2 "arith_operand" "dI")))]
288 (define_insn "subsi3_internal"
289 [(set (match_operand:SI 0 "register_operand" "=d,=d")
290 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
291 (match_operand:SI 2 "arith_operand" "d,I")))]
296 [(set_attr "type" "arith")
297 (set_attr "mode" "SI")])
300 ;; ....................
302 ;; NEGATION and ONE'S COMPLEMENT
304 ;; ....................
306 (define_insn "negsi2"
307 [(set (match_operand:SI 0 "register_operand" "=d")
308 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
312 operands[2] = const0_rtx;
313 return \"subu\\t%0,%z2,%1\";
315 [(set_attr "type" "arith")
316 (set_attr "mode" "SI")])
318 (define_insn "one_cmplsi2"
319 [(set (match_operand:SI 0 "register_operand" "=d")
320 (not:SI (match_operand:SI 1 "register_operand" "d")))]
324 operands[2] = const0_rtx;
325 return \"nor\\t%0,%z2,%1\";
327 [(set_attr "type" "arith")
328 (set_attr "mode" "SI")])
331 ;; ....................
335 ;; ....................
338 (define_expand "andsi3"
339 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
340 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
341 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
346 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
347 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
348 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
352 if (which_alternative == 0)
353 return \"and\\t%0,%1,%2\";
354 else if (which_alternative == 1)
355 return \"andi\\t%0,%1,%x2\";
356 else if (which_alternative == 2)
358 if ((INTVAL (operands[2]) & 0xffff) == 0xffff)
360 operands[2] = GEN_INT (INTVAL (operands[2]) >> 16);
361 return \"andoui\\t%0,%1,%x2\";
365 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
366 return \"andoi\\t%0,%1,%x2\";
370 [(set_attr "type" "arith")
371 (set_attr "mode" "SI")])
373 (define_expand "iorsi3"
374 [(set (match_operand:SI 0 "register_operand" "=d,d")
375 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
376 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
381 [(set (match_operand:SI 0 "register_operand" "=d,d")
382 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
383 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
388 [(set_attr "type" "arith")
389 (set_attr "mode" "SI")])
391 (define_expand "xorsi3"
392 [(set (match_operand:SI 0 "register_operand" "=d,d")
393 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
394 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
399 [(set (match_operand:SI 0 "register_operand" "=d,d")
400 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
401 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
406 [(set_attr "type" "arith")
407 (set_attr "mode" "SI")])
409 (define_insn "*norsi3"
410 [(set (match_operand:SI 0 "register_operand" "=d")
411 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
412 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
415 [(set_attr "type" "arith")
416 (set_attr "mode" "SI")])
419 ;; ....................
423 ;; ....................
426 ;; Those for integer source operand are ordered widest source type first.
428 (define_expand "zero_extendhisi2"
429 [(set (match_operand:SI 0 "register_operand" "")
430 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
435 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
436 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
440 if (which_alternative == 0)
441 return \"andi\\t%0,%1,0xffff\";
443 return iq2000_move_1word (operands, insn, TRUE);
445 [(set_attr "type" "arith,load,load")
446 (set_attr "mode" "SI")
447 (set_attr "length" "4,4,8")])
449 (define_expand "zero_extendqihi2"
450 [(set (match_operand:HI 0 "register_operand" "")
451 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
456 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
457 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
461 if (which_alternative == 0)
462 return \"andi\\t%0,%1,0x00ff\";
464 return iq2000_move_1word (operands, insn, TRUE);
466 [(set_attr "type" "arith,load,load")
467 (set_attr "mode" "HI")
468 (set_attr "length" "4,4,8")])
470 (define_expand "zero_extendqisi2"
471 [(set (match_operand:SI 0 "register_operand" "")
472 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
477 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
478 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
482 if (which_alternative == 0)
483 return \"andi\\t%0,%1,0x00ff\";
485 return iq2000_move_1word (operands, insn, TRUE);
487 [(set_attr "type" "arith,load,load")
488 (set_attr "mode" "SI")
489 (set_attr "length" "4,4,8")])
492 ;; ....................
496 ;; ....................
499 ;; Those for integer source operand are ordered widest source type first.
501 ;; These patterns originally accepted general_operands, however, slightly
502 ;; better code is generated by only accepting register_operands, and then
503 ;; letting combine generate the lh and lb insns.
505 (define_expand "extendhisi2"
506 [(set (match_operand:SI 0 "register_operand" "")
507 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
511 if (optimize && GET_CODE (operands[1]) == MEM)
512 operands[1] = force_not_mem (operands[1]);
514 if (GET_CODE (operands[1]) != MEM)
516 rtx op1 = gen_lowpart (SImode, operands[1]);
517 rtx temp = gen_reg_rtx (SImode);
518 rtx shift = GEN_INT (16);
520 emit_insn (gen_ashlsi3 (temp, op1, shift));
521 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
526 (define_insn "extendhisi2_internal"
527 [(set (match_operand:SI 0 "register_operand" "=d,d")
528 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
530 "* return iq2000_move_1word (operands, insn, FALSE);"
531 [(set_attr "type" "load")
532 (set_attr "mode" "SI")
533 (set_attr "length" "4,8")])
535 (define_expand "extendqihi2"
536 [(set (match_operand:HI 0 "register_operand" "")
537 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
541 if (optimize && GET_CODE (operands[1]) == MEM)
542 operands[1] = force_not_mem (operands[1]);
544 if (GET_CODE (operands[1]) != MEM)
546 rtx op0 = gen_lowpart (SImode, operands[0]);
547 rtx op1 = gen_lowpart (SImode, operands[1]);
548 rtx temp = gen_reg_rtx (SImode);
549 rtx shift = GEN_INT (24);
551 emit_insn (gen_ashlsi3 (temp, op1, shift));
552 emit_insn (gen_ashrsi3 (op0, temp, shift));
557 (define_insn "extendqihi2_internal"
558 [(set (match_operand:HI 0 "register_operand" "=d,d")
559 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
561 "* return iq2000_move_1word (operands, insn, FALSE);"
562 [(set_attr "type" "load")
563 (set_attr "mode" "SI")
564 (set_attr "length" "4,8")])
567 (define_expand "extendqisi2"
568 [(set (match_operand:SI 0 "register_operand" "")
569 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
573 if (optimize && GET_CODE (operands[1]) == MEM)
574 operands[1] = force_not_mem (operands[1]);
576 if (GET_CODE (operands[1]) != MEM)
578 rtx op1 = gen_lowpart (SImode, operands[1]);
579 rtx temp = gen_reg_rtx (SImode);
580 rtx shift = GEN_INT (24);
582 emit_insn (gen_ashlsi3 (temp, op1, shift));
583 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
588 (define_insn "extendqisi2_insn"
589 [(set (match_operand:SI 0 "register_operand" "=d,d")
590 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
592 "* return iq2000_move_1word (operands, insn, FALSE);"
593 [(set_attr "type" "load")
594 (set_attr "mode" "SI")
595 (set_attr "length" "4,8")])
598 ;; ........................
600 ;; BIT FIELD EXTRACTION
602 ;; ........................
605 [(set (match_operand:SI 0 "register_operand" "=r")
606 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
607 (match_operand:SI 2 "const_int_operand" "O")
608 (match_operand:SI 3 "const_int_operand" "O")))]
613 value[2] = INTVAL (operands[2]);
614 value[3] = INTVAL (operands[3]);
615 operands[2] = GEN_INT ((value[3]));
616 operands[3] = GEN_INT ((32 - value[2]));
617 return \"ram\\t%0,%1,%2,%3,0x0\";
619 [(set_attr "type" "arith")])
622 ;; ....................
626 ;; ....................
628 /* Take care of constants that don't fit in single instruction */
630 [(set (match_operand:SI 0 "register_operand" "")
631 (match_operand:SI 1 "general_operand" ""))]
632 "(reload_in_progress || reload_completed)
633 && large_int (operands[1], SImode)"
636 (high:SI (match_dup 1)))
638 (lo_sum:SI (match_dup 0)
642 ;; ??? iq2000_move_1word has support for HIGH, so this pattern may be
646 [(set (match_operand:SI 0 "register_operand" "=r")
647 (high:SI (match_operand:SI 1 "immediate_operand" "")))]
649 "lui\\t%0,%%hi(%1) # high"
650 [(set_attr "type" "move")])
653 [(set (match_operand:SI 0 "register_operand" "=r")
654 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
655 (match_operand:SI 2 "immediate_operand" "")))]
657 "addiu\\t%0,%1,%%lo(%2) # low"
658 [(set_attr "type" "arith")
659 (set_attr "mode" "SI")])
661 ;; 32-bit Integer moves
664 [(set (match_operand:SI 0 "register_operand" "")
665 (match_operand:SI 1 "large_int" ""))]
666 "reload_in_progress | reload_completed"
670 (ior:SI (match_dup 0)
674 operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
677 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
680 ;; Unlike most other insns, the move insns can't be split with
681 ;; different predicates, because register spilling and other parts of
682 ;; the compiler, have memoized the insn number already.
684 (define_expand "movsi"
685 [(set (match_operand:SI 0 "nonimmediate_operand" "")
686 (match_operand:SI 1 "general_operand" ""))]
690 if (iq2000_check_split (operands[1], SImode))
692 enum machine_mode mode = GET_MODE (operands[0]);
693 rtx tem = ((reload_in_progress | reload_completed)
694 ? operands[0] : gen_reg_rtx (mode));
696 emit_insn (gen_rtx_SET (VOIDmode, tem,
697 gen_rtx_HIGH (mode, operands[1])));
699 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
702 if ((reload_in_progress | reload_completed) == 0
703 && !register_operand (operands[0], SImode)
704 && !register_operand (operands[1], SImode)
705 && (GET_CODE (operands[1]) != CONST_INT
706 || INTVAL (operands[1]) != 0))
708 rtx temp = force_reg (SImode, operands[1]);
709 emit_move_insn (operands[0], temp);
713 /* Take care of constants that don't fit in single instruction */
714 if ((reload_in_progress || reload_completed)
715 && CONSTANT_P (operands[1])
716 && GET_CODE (operands[1]) != HIGH
717 && GET_CODE (operands[1]) != LO_SUM
718 && ! SMALL_INT_UNSIGNED (operands[1]))
720 rtx tem = ((reload_in_progress | reload_completed)
721 ? operands[0] : gen_reg_rtx (SImode));
723 emit_insn (gen_rtx_SET (VOIDmode, tem,
724 gen_rtx_HIGH (SImode, operands[1])));
725 operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]);
729 ;; The difference between these two is whether or not ints are allowed
730 ;; in FP registers (off by default, use -mdebugh to enable).
732 (define_insn "movsi_internal2"
733 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
734 (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))]
735 "(register_operand (operands[0], SImode)
736 || register_operand (operands[1], SImode)
737 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
738 "* return iq2000_move_1word (operands, insn, FALSE);"
739 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,move,move,move")
740 (set_attr "mode" "SI")
741 (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,4,4")])
743 ;; 16-bit Integer moves
745 ;; Unlike most other insns, the move insns can't be split with
746 ;; different predicates, because register spilling and other parts of
747 ;; the compiler, have memoized the insn number already.
748 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
750 (define_expand "movhi"
751 [(set (match_operand:HI 0 "nonimmediate_operand" "")
752 (match_operand:HI 1 "general_operand" ""))]
756 if ((reload_in_progress | reload_completed) == 0
757 && !register_operand (operands[0], HImode)
758 && !register_operand (operands[1], HImode)
759 && ((GET_CODE (operands[1]) != CONST_INT
760 || INTVAL (operands[1]) != 0)))
762 rtx temp = force_reg (HImode, operands[1]);
763 emit_move_insn (operands[0], temp);
768 ;; The difference between these two is whether or not ints are allowed
769 ;; in FP registers (off by default, use -mdebugh to enable).
771 (define_insn "movhi_internal2"
772 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
773 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
774 "(register_operand (operands[0], HImode)
775 || register_operand (operands[1], HImode)
776 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
777 "* return iq2000_move_1word (operands, insn, TRUE);"
778 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,move")
779 (set_attr "mode" "HI")
780 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
782 ;; 8-bit Integer moves
784 ;; Unlike most other insns, the move insns can't be split with
785 ;; different predicates, because register spilling and other parts of
786 ;; the compiler, have memoized the insn number already.
787 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
789 (define_expand "movqi"
790 [(set (match_operand:QI 0 "nonimmediate_operand" "")
791 (match_operand:QI 1 "general_operand" ""))]
795 if ((reload_in_progress | reload_completed) == 0
796 && !register_operand (operands[0], QImode)
797 && !register_operand (operands[1], QImode)
798 && (GET_CODE (operands[1]) != CONST_INT
799 || INTVAL (operands[1]) != 0))
801 rtx temp = force_reg (QImode, operands[1]);
802 emit_move_insn (operands[0], temp);
807 ;; The difference between these two is whether or not ints are allowed
808 ;; in FP registers (off by default, use -mdebugh to enable).
810 (define_insn "movqi_internal2"
811 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
812 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
813 "(register_operand (operands[0], QImode)
814 || register_operand (operands[1], QImode)
815 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
816 "* return iq2000_move_1word (operands, insn, TRUE);"
817 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,move")
818 (set_attr "mode" "QI")
819 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
821 ;; 32-bit floating point moves
823 (define_expand "movsf"
824 [(set (match_operand:SF 0 "general_operand" "")
825 (match_operand:SF 1 "general_operand" ""))]
829 if (!reload_in_progress
831 && GET_CODE (operands[0]) == MEM
832 && (GET_CODE (operands[1]) == MEM
833 || GET_CODE (operands[1]) == CONST_DOUBLE))
834 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
836 /* Take care of reg <- SF constant */
837 if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) )
839 emit_insn (gen_movsf_high (operands[0], operands[1]));
840 emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1]));
845 (define_insn "movsf_lo_sum"
846 [(set (match_operand:SF 0 "register_operand" "=r")
847 (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
848 (match_operand:SF 2 "const_double_operand" "")))]
855 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
856 REAL_VALUE_TO_TARGET_SINGLE (r, i);
857 operands[2] = GEN_INT (i);
858 return \"addiu\\t%0,%1,%%lo(%2) # low\";
860 [(set_attr "length" "4")
861 (set_attr "type" "arith")])
863 (define_insn "movsf_high"
864 [(set (match_operand:SF 0 "register_operand" "=r")
865 (high:SF (match_operand:SF 1 "const_double_operand" "")))]
872 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
873 REAL_VALUE_TO_TARGET_SINGLE (r, i);
874 operands[1] = GEN_INT (i);
875 return \"lui\\t%0,%%hi(%1) # high\";
877 [(set_attr "length" "4")
878 (set_attr "type" "arith")])
880 (define_insn "*movsf_internal"
881 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
882 (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))]
883 "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)"
886 iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn);
887 if (which_alternative == 0)
888 return \"or\\t%0,%1,%1\";
889 else if (which_alternative == 1)
890 return \"lw\\t%0,%1\";
891 else if (which_alternative == 2)
892 return \"sw\\t%1,%0\";
894 [(set_attr "length" "4,4,4")
895 (set_attr "type" "arith,load,store")]
899 ;; ....................
903 ;; ....................
905 (define_expand "ashlsi3"
906 [(set (match_operand:SI 0 "register_operand" "=d")
907 (ashift:SI (match_operand:SI 1 "register_operand" "d")
908 (match_operand:SI 2 "arith_operand" "dI")))]
912 (define_insn "ashlsi3_internal1"
913 [(set (match_operand:SI 0 "register_operand" "=d")
914 (ashift:SI (match_operand:SI 1 "register_operand" "d")
915 (match_operand:SI 2 "arith_operand" "dI")))]
919 if (GET_CODE (operands[2]) == CONST_INT)
921 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
922 return \"sll\\t%0,%1,%2\";
925 return \"sllv\\t%0,%1,%2\";
927 [(set_attr "type" "arith")
928 (set_attr "mode" "SI")])
930 (define_expand "ashrsi3"
931 [(set (match_operand:SI 0 "register_operand" "=d")
932 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
933 (match_operand:SI 2 "arith_operand" "dI")))]
937 (define_insn "ashrsi3_internal1"
938 [(set (match_operand:SI 0 "register_operand" "=d")
939 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
940 (match_operand:SI 2 "arith_operand" "dI")))]
944 if (GET_CODE (operands[2]) == CONST_INT)
946 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
947 return \"sra\\t%0,%1,%2\";
950 return \"srav\\t%0,%1,%2\";
952 [(set_attr "type" "arith")
953 (set_attr "mode" "SI")])
955 (define_expand "lshrsi3"
956 [(set (match_operand:SI 0 "register_operand" "=d")
957 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
958 (match_operand:SI 2 "arith_operand" "dI")))]
962 (define_insn "lshrsi3_internal1"
963 [(set (match_operand:SI 0 "register_operand" "=d")
964 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
965 (match_operand:SI 2 "arith_operand" "dI")))]
969 if (GET_CODE (operands[2]) == CONST_INT)
971 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
972 return \"srl\\t%0,%1,%2\";
975 return \"srlv\\t%0,%1,%2\";
977 [(set_attr "type" "arith")
978 (set_attr "mode" "SI")])
981 (define_insn "rotrsi3"
982 [(set (match_operand:SI 0 "register_operand" "=r")
983 (rotatert:SI (match_operand:SI 1 "register_operand" "r")
984 (match_operand:SI 2 "uns_arith_operand" "O")))]
986 "ram %0,%1,%2,0x0,0x0"
987 [(set_attr "type" "arith")])
991 ;; ....................
995 ;; ....................
997 ;; Flow here is rather complex:
999 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
1000 ;; arguments into the branch_cmp array, and the type into
1001 ;; branch_type. No RTL is generated.
1003 ;; 2) The appropriate branch define_expand is called, which then
1004 ;; creates the appropriate RTL for the comparison and branch.
1005 ;; Different CC modes are used, based on what type of branch is
1006 ;; done, so that we can constrain things appropriately. There
1007 ;; are assumptions in the rest of GCC that break if we fold the
1008 ;; operands into the branches for integer operations, and use cc0
1009 ;; for floating point, so we use the fp status register instead.
1010 ;; If needed, an appropriate temporary is created to hold the
1011 ;; of the integer compare.
1013 (define_expand "cmpsi"
1015 (compare:CC (match_operand:SI 0 "register_operand" "")
1016 (match_operand:SI 1 "arith_operand" "")))]
1020 if (operands[0]) /* avoid unused code message */
1022 branch_cmp[0] = operands[0];
1023 branch_cmp[1] = operands[1];
1024 branch_type = CMP_SI;
1029 (define_expand "tstsi"
1031 (match_operand:SI 0 "register_operand" ""))]
1035 if (operands[0]) /* avoid unused code message */
1037 branch_cmp[0] = operands[0];
1038 branch_cmp[1] = const0_rtx;
1039 branch_type = CMP_SI;
1045 ;; ....................
1047 ;; CONDITIONAL BRANCHES
1049 ;; ....................
1051 ;; Conditional branches on comparisons with zero.
1053 (define_insn "branch_zero"
1056 (match_operator:SI 0 "cmp_op"
1057 [(match_operand:SI 2 "register_operand" "d")
1059 (label_ref (match_operand 1 "" ""))
1064 return iq2000_output_conditional_branch (insn,
1066 /*two_operands_p=*/0,
1069 get_attr_length (insn));
1071 [(set_attr "type" "branch")
1072 (set_attr "mode" "none")])
1074 (define_insn "branch_zero_inverted"
1077 (match_operator:SI 0 "cmp_op"
1078 [(match_operand:SI 2 "register_operand" "d")
1081 (label_ref (match_operand 1 "" ""))))]
1085 return iq2000_output_conditional_branch (insn,
1087 /*two_operands_p=*/0,
1090 get_attr_length (insn));
1092 [(set_attr "type" "branch")
1093 (set_attr "mode" "none")])
1095 ;; Conditional branch on equality comparison.
1097 (define_insn "branch_equality"
1100 (match_operator:SI 0 "equality_op"
1101 [(match_operand:SI 2 "register_operand" "d")
1102 (match_operand:SI 3 "register_operand" "d")])
1103 (label_ref (match_operand 1 "" ""))
1108 return iq2000_output_conditional_branch (insn,
1110 /*two_operands_p=*/1,
1113 get_attr_length (insn));
1115 [(set_attr "type" "branch")
1116 (set_attr "mode" "none")])
1118 (define_insn "branch_equality_inverted"
1121 (match_operator:SI 0 "equality_op"
1122 [(match_operand:SI 2 "register_operand" "d")
1123 (match_operand:SI 3 "register_operand" "d")])
1125 (label_ref (match_operand 1 "" ""))))]
1129 return iq2000_output_conditional_branch (insn,
1131 /*two_operands_p=*/1,
1134 get_attr_length (insn));
1136 [(set_attr "type" "branch")
1137 (set_attr "mode" "none")])
1139 (define_expand "beq"
1141 (if_then_else (eq:CC (cc0)
1143 (label_ref (match_operand 0 "" ""))
1148 if (operands[0]) /* avoid unused code warning */
1150 gen_conditional_branch (operands, EQ);
1155 (define_expand "bne"
1157 (if_then_else (ne:CC (cc0)
1159 (label_ref (match_operand 0 "" ""))
1164 if (operands[0]) /* avoid unused code warning */
1166 gen_conditional_branch (operands, NE);
1171 (define_expand "bgt"
1173 (if_then_else (gt:CC (cc0)
1175 (label_ref (match_operand 0 "" ""))
1180 if (operands[0]) /* avoid unused code warning */
1182 gen_conditional_branch (operands, GT);
1187 (define_expand "bge"
1189 (if_then_else (ge:CC (cc0)
1191 (label_ref (match_operand 0 "" ""))
1196 if (operands[0]) /* avoid unused code warning */
1198 gen_conditional_branch (operands, GE);
1203 (define_expand "blt"
1205 (if_then_else (lt:CC (cc0)
1207 (label_ref (match_operand 0 "" ""))
1212 if (operands[0]) /* avoid unused code warning */
1214 gen_conditional_branch (operands, LT);
1219 (define_expand "ble"
1221 (if_then_else (le:CC (cc0)
1223 (label_ref (match_operand 0 "" ""))
1228 if (operands[0]) /* avoid unused code warning */
1230 gen_conditional_branch (operands, LE);
1235 (define_expand "bgtu"
1237 (if_then_else (gtu:CC (cc0)
1239 (label_ref (match_operand 0 "" ""))
1244 if (operands[0]) /* avoid unused code warning */
1246 gen_conditional_branch (operands, GTU);
1251 (define_expand "bgeu"
1253 (if_then_else (geu:CC (cc0)
1255 (label_ref (match_operand 0 "" ""))
1260 if (operands[0]) /* avoid unused code warning */
1262 gen_conditional_branch (operands, GEU);
1268 (define_expand "bltu"
1270 (if_then_else (ltu:CC (cc0)
1272 (label_ref (match_operand 0 "" ""))
1277 if (operands[0]) /* avoid unused code warning */
1279 gen_conditional_branch (operands, LTU);
1284 (define_expand "bleu"
1286 (if_then_else (leu:CC (cc0)
1288 (label_ref (match_operand 0 "" ""))
1293 if (operands[0]) /* avoid unused code warning */
1295 gen_conditional_branch (operands, LEU);
1300 ;; Recognize bbi and bbin instructions. These use two unusual template
1301 ;; patterns, %Ax and %Px. %Ax outputs an 'i' if operand `x' is a LABEL_REF
1302 ;; otherwise it outputs an 'in'. %Px does nothing if `x' is PC
1303 ;; and outputs the operand if `x' is a LABEL_REF.
1308 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1310 (match_operand:SI 1 "arith_operand" "I"))
1312 (match_operand 2 "pc_or_label_operand" "")
1313 (match_operand 3 "pc_or_label_operand" "")))]
1315 "bb%A2\\t%0(31-%1),%P2%P3"
1316 [(set_attr "length" "4")
1317 (set_attr "type" "branch")])
1322 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1324 (match_operand:SI 1 "arith_operand" "I"))
1326 (match_operand 2 "pc_or_label_operand" "")
1327 (match_operand 3 "pc_or_label_operand" "")))]
1329 "bb%A3\\t%0(31-%1),%P2%P3"
1330 [(set_attr "length" "4")
1331 (set_attr "type" "branch")])
1336 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1338 (match_operand:SI 1 "arith_operand" "I"))
1340 (match_operand 2 "pc_or_label_operand" "")
1341 (match_operand 3 "pc_or_label_operand" "")))]
1343 "bb%A2\\t%0(31-%1),%P2%P3"
1344 [(set_attr "length" "4")
1345 (set_attr "type" "branch")])
1350 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1352 (match_operand:SI 1 "arith_operand" "I"))
1354 (match_operand 2 "pc_or_label_operand" "")
1355 (match_operand 3 "pc_or_label_operand" "")))]
1357 "bb%A3\\t%0(31-%1),%P2%P3"
1358 [(set_attr "length" "4")
1359 (set_attr "type" "branch")])
1364 (eq (and:SI (match_operand:SI 0 "register_operand" "r")
1365 (match_operand:SI 1 "power_of_2_operand" "I"))
1367 (match_operand 2 "pc_or_label_operand" "")
1368 (match_operand 3 "pc_or_label_operand" "")))]
1370 "bb%A3\\t%0(%p1),%P2%P3"
1371 [(set_attr "length" "4")
1372 (set_attr "type" "branch")])
1377 (ne (and:SI (match_operand:SI 0 "register_operand" "r")
1378 (match_operand:SI 1 "power_of_2_operand" "I"))
1380 (match_operand 2 "pc_or_label_operand" "")
1381 (match_operand 3 "pc_or_label_operand" "")))]
1383 "bb%A2\\t%0(%p1),%P2%P3"
1384 [(set_attr "length" "4")
1385 (set_attr "type" "branch")])
1388 ;; ....................
1390 ;; SETTING A REGISTER FROM A COMPARISON
1392 ;; ....................
1394 (define_expand "seq"
1395 [(set (match_operand:SI 0 "register_operand" "=d")
1396 (eq:SI (match_dup 1)
1401 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1404 /* Set up operands from compare. */
1405 operands[1] = branch_cmp[0];
1406 operands[2] = branch_cmp[1];
1408 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
1413 (define_insn "seq_si_zero"
1414 [(set (match_operand:SI 0 "register_operand" "=d")
1415 (eq:SI (match_operand:SI 1 "register_operand" "d")
1419 [(set_attr "type" "arith")
1420 (set_attr "mode" "SI")])
1422 (define_expand "sne"
1423 [(set (match_operand:SI 0 "register_operand" "=d")
1424 (ne:SI (match_dup 1)
1429 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1432 /* Set up operands from compare. */
1433 operands[1] = branch_cmp[0];
1434 operands[2] = branch_cmp[1];
1436 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
1440 (define_insn "sne_si_zero"
1441 [(set (match_operand:SI 0 "register_operand" "=d")
1442 (ne:SI (match_operand:SI 1 "register_operand" "d")
1446 [(set_attr "type" "arith")
1447 (set_attr "mode" "SI")])
1449 (define_expand "sgt"
1450 [(set (match_operand:SI 0 "register_operand" "=d")
1451 (gt:SI (match_dup 1)
1456 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1459 /* Set up operands from compare. */
1460 operands[1] = branch_cmp[0];
1461 operands[2] = branch_cmp[1];
1463 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
1467 (define_insn "sgt_si"
1468 [(set (match_operand:SI 0 "register_operand" "=d,=d")
1469 (gt:SI (match_operand:SI 1 "register_operand" "d,d")
1470 (match_operand:SI 2 "reg_or_0_operand" "d,J")))]
1475 [(set_attr "type" "arith,arith")
1476 (set_attr "mode" "SI,SI")])
1478 (define_expand "sge"
1479 [(set (match_operand:SI 0 "register_operand" "=d")
1480 (ge:SI (match_dup 1)
1485 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1488 /* Set up operands from compare. */
1489 operands[1] = branch_cmp[0];
1490 operands[2] = branch_cmp[1];
1492 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
1496 (define_expand "slt"
1497 [(set (match_operand:SI 0 "register_operand" "=d")
1498 (lt:SI (match_dup 1)
1503 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1506 /* Set up operands from compare. */
1507 operands[1] = branch_cmp[0];
1508 operands[2] = branch_cmp[1];
1510 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
1514 (define_insn "slt_si"
1515 [(set (match_operand:SI 0 "register_operand" "=d,=d")
1516 (lt:SI (match_operand:SI 1 "register_operand" "d,d")
1517 (match_operand:SI 2 "arith_operand" "d,I")))]
1522 [(set_attr "type" "arith,arith")
1523 (set_attr "mode" "SI,SI")])
1525 (define_expand "sle"
1526 [(set (match_operand:SI 0 "register_operand" "=d")
1527 (le:SI (match_dup 1)
1532 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1535 /* Set up operands from compare. */
1536 operands[1] = branch_cmp[0];
1537 operands[2] = branch_cmp[1];
1539 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
1543 (define_insn "sle_si_const"
1544 [(set (match_operand:SI 0 "register_operand" "=d")
1545 (le:SI (match_operand:SI 1 "register_operand" "d")
1546 (match_operand:SI 2 "small_int" "I")))]
1547 "INTVAL (operands[2]) < 32767"
1550 operands[2] = GEN_INT (INTVAL (operands[2])+1);
1551 return \"slti\\t%0,%1,%2\";
1553 [(set_attr "type" "arith")
1554 (set_attr "mode" "SI")])
1556 (define_expand "sgtu"
1557 [(set (match_operand:SI 0 "register_operand" "=d")
1558 (gtu:SI (match_dup 1)
1563 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1566 /* Set up operands from compare. */
1567 operands[1] = branch_cmp[0];
1568 operands[2] = branch_cmp[1];
1570 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
1574 (define_insn "sgtu_si"
1575 [(set (match_operand:SI 0 "register_operand" "=d")
1576 (gtu:SI (match_operand:SI 1 "register_operand" "d")
1577 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
1580 [(set_attr "type" "arith")
1581 (set_attr "mode" "SI")])
1584 [(set (match_operand:SI 0 "register_operand" "=t")
1585 (gtu:SI (match_operand:SI 1 "register_operand" "d")
1586 (match_operand:SI 2 "register_operand" "d")))]
1589 [(set_attr "type" "arith")
1590 (set_attr "mode" "SI")])
1592 (define_expand "sgeu"
1593 [(set (match_operand:SI 0 "register_operand" "=d")
1594 (geu:SI (match_dup 1)
1599 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1602 /* Set up operands from compare. */
1603 operands[1] = branch_cmp[0];
1604 operands[2] = branch_cmp[1];
1606 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
1610 (define_expand "sltu"
1611 [(set (match_operand:SI 0 "register_operand" "=d")
1612 (ltu:SI (match_dup 1)
1617 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1620 /* Set up operands from compare. */
1621 operands[1] = branch_cmp[0];
1622 operands[2] = branch_cmp[1];
1624 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
1628 (define_insn "sltu_si"
1629 [(set (match_operand:SI 0 "register_operand" "=d,=d")
1630 (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
1631 (match_operand:SI 2 "arith_operand" "d,I")))]
1636 [(set_attr "type" "arith,arith")
1637 (set_attr "mode" "SI,SI")])
1639 (define_expand "sleu"
1640 [(set (match_operand:SI 0 "register_operand" "=d")
1641 (leu:SI (match_dup 1)
1646 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1649 /* Set up operands from compare. */
1650 operands[1] = branch_cmp[0];
1651 operands[2] = branch_cmp[1];
1653 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
1657 (define_insn "sleu_si_const"
1658 [(set (match_operand:SI 0 "register_operand" "=d")
1659 (leu:SI (match_operand:SI 1 "register_operand" "d")
1660 (match_operand:SI 2 "small_int" "I")))]
1661 "INTVAL (operands[2]) < 32767"
1664 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
1665 return \"sltiu\\t%0,%1,%2\";
1667 [(set_attr "type" "arith")
1668 (set_attr "mode" "SI")])
1672 ;; ....................
1674 ;; UNCONDITIONAL BRANCHES
1676 ;; ....................
1678 ;; Unconditional branches.
1682 (label_ref (match_operand 0 "" "")))]
1686 if (GET_CODE (operands[0]) == REG)
1689 /* return \"b\\t%l0\";*/
1691 [(set_attr "type" "jump")
1692 (set_attr "mode" "none")])
1694 (define_expand "indirect_jump"
1695 [(set (pc) (match_operand 0 "register_operand" "d"))]
1701 if (operands[0]) /* eliminate unused code warnings */
1704 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1705 operands[0] = copy_to_mode_reg (Pmode, dest);
1707 if (!(Pmode == DImode))
1708 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
1710 emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
1716 (define_insn "indirect_jump_internal1"
1717 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1718 "!(Pmode == DImode)"
1720 [(set_attr "type" "jump")
1721 (set_attr "mode" "none")])
1723 (define_expand "tablejump"
1725 (match_operand 0 "register_operand" "d"))
1726 (use (label_ref (match_operand 1 "" "")))]
1730 if (operands[0]) /* eliminate unused code warnings */
1732 if (GET_MODE (operands[0]) != Pmode)
1735 if (!(Pmode == DImode))
1736 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1738 emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
1744 (define_insn "tablejump_internal1"
1746 (match_operand:SI 0 "register_operand" "d"))
1747 (use (label_ref (match_operand 1 "" "")))]
1748 "!(Pmode == DImode)"
1750 [(set_attr "type" "jump")
1751 (set_attr "mode" "none")])
1753 (define_expand "tablejump_internal3"
1754 [(parallel [(set (pc)
1755 (plus:SI (match_operand:SI 0 "register_operand" "d")
1756 (label_ref:SI (match_operand 1 "" ""))))
1757 (use (label_ref:SI (match_dup 1)))])]
1761 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
1762 ;;; it is not valid. ??? With the USE, the condition tests may not be required
1765 ;;; ??? The length depends on the ABI. It is two for o32, and one for n32.
1766 ;;; We just use the conservative number here.
1770 (plus:SI (match_operand:SI 0 "register_operand" "d")
1771 (label_ref:SI (match_operand 1 "" ""))))
1772 (use (label_ref:SI (match_dup 1)))]
1773 "!(Pmode == DImode) && next_active_insn (insn) != 0
1774 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
1775 && PREV_INSN (next_active_insn (insn)) == operands[1]"
1780 [(set_attr "type" "jump")
1781 (set_attr "mode" "none")
1782 (set_attr "length" "8")])
1785 ;; ....................
1787 ;; Function prologue/epilogue
1789 ;; ....................
1792 (define_expand "prologue"
1797 if (iq2000_isa >= 0) /* avoid unused code warnings */
1799 iq2000_expand_prologue ();
1804 ;; Block any insns from being moved before this point, since the
1805 ;; profiling call to mcount can use various registers that aren't
1806 ;; saved or used to pass arguments.
1808 (define_insn "blockage"
1809 [(unspec_volatile [(const_int 0)] 0)]
1812 [(set_attr "type" "unknown")
1813 (set_attr "mode" "none")
1814 (set_attr "length" "0")])
1816 (define_expand "epilogue"
1821 if (iq2000_isa >= 0) /* avoid unused code warnings */
1823 iq2000_expand_epilogue ();
1828 ;; Trivial return. Make it look like a normal return insn as that
1829 ;; allows jump optimizations to work better .
1830 (define_insn "return"
1832 "iq2000_can_use_return_insn ()"
1834 [(set_attr "type" "jump")
1835 (set_attr "mode" "none")])
1839 (define_insn "return_internal"
1840 [(use (match_operand 0 "pmode_register_operand" ""))
1847 [(set_attr "type" "jump")
1848 (set_attr "mode" "none")])
1850 (define_insn "eh_return_internal"
1857 [(set_attr "type" "jump")
1858 (set_attr "mode" "none")])
1860 (define_expand "eh_return"
1861 [(use (match_operand:SI 0 "register_operand" "r"))]
1865 iq2000_expand_eh_return (operands[0]);
1871 ;; ....................
1875 ;; ....................
1877 ;; calls.c now passes a third argument, make saber happy
1879 (define_expand "call"
1880 [(parallel [(call (match_operand 0 "memory_operand" "m")
1881 (match_operand 1 "" "i"))
1882 (clobber (reg:SI 31))
1883 (use (match_operand 2 "" "")) ;; next_arg_reg
1884 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
1890 if (operands[0]) /* eliminate unused code warnings */
1892 addr = XEXP (operands[0], 0);
1893 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1894 || ! call_insn_operand (addr, VOIDmode))
1895 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1897 /* In order to pass small structures by value in registers
1898 compatibly with the IQ2000 compiler, we need to shift the value
1899 into the high part of the register. Function_arg has encoded
1900 a PARALLEL rtx, holding a vector of adjustments to be made
1901 as the next_arg_reg variable, so we split up the insns,
1902 and emit them separately. */
1904 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
1906 rtvec adjust = XVEC (operands[2], 0);
1907 int num = GET_NUM_ELEM (adjust);
1910 for (i = 0; i < num; i++)
1911 emit_insn (RTVEC_ELT (adjust, i));
1914 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
1915 gen_rtx_REG (SImode,
1916 GP_REG_FIRST + 31)));
1921 (define_expand "call_internal0"
1922 [(parallel [(call (match_operand 0 "" "")
1923 (match_operand 1 "" ""))
1924 (clobber (match_operand:SI 2 "" ""))])]
1928 (define_insn "call_internal1"
1929 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
1930 (match_operand 1 "" "i"))
1931 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1935 register rtx target = operands[0];
1937 if (GET_CODE (target) == CONST_INT)
1938 return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
1939 else if (CONSTANT_ADDRESS_P (target))
1940 return \"jal\\t%0\";
1942 return \"jalr\\t%2,%0\";
1944 [(set_attr "type" "call")
1945 (set_attr "mode" "none")])
1947 ;; calls.c now passes a fourth argument, make saber happy
1949 (define_expand "call_value"
1950 [(parallel [(set (match_operand 0 "register_operand" "=df")
1951 (call (match_operand 1 "memory_operand" "m")
1952 (match_operand 2 "" "i")))
1953 (clobber (reg:SI 31))
1954 (use (match_operand 3 "" ""))])] ;; next_arg_reg
1960 if (operands[0]) /* eliminate unused code warning */
1962 addr = XEXP (operands[1], 0);
1963 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1964 || ! call_insn_operand (addr, VOIDmode))
1965 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1967 /* In order to pass small structures by value in registers
1968 compatibly with the IQ2000 compiler, we need to shift the value
1969 into the high part of the register. Function_arg has encoded
1970 a PARALLEL rtx, holding a vector of adjustments to be made
1971 as the next_arg_reg variable, so we split up the insns,
1972 and emit them separately. */
1974 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
1976 rtvec adjust = XVEC (operands[3], 0);
1977 int num = GET_NUM_ELEM (adjust);
1980 for (i = 0; i < num; i++)
1981 emit_insn (RTVEC_ELT (adjust, i));
1984 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
1986 emit_call_insn (gen_call_value_multiple_internal0
1987 (XEXP (XVECEXP (operands[0], 0, 0), 0),
1988 operands[1], operands[2],
1989 XEXP (XVECEXP (operands[0], 0, 1), 0),
1990 gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
1994 /* We have a call returning a DImode structure in an FP reg.
1995 Strip off the now unnecessary PARALLEL. */
1996 if (GET_CODE (operands[0]) == PARALLEL)
1997 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
1999 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
2000 gen_rtx_REG (SImode,
2001 GP_REG_FIRST + 31)));
2007 (define_expand "call_value_internal0"
2008 [(parallel [(set (match_operand 0 "" "")
2009 (call (match_operand 1 "" "")
2010 (match_operand 2 "" "")))
2011 (clobber (match_operand:SI 3 "" ""))])]
2015 (define_insn "call_value_internal1"
2016 [(set (match_operand 0 "register_operand" "=df")
2017 (call (mem (match_operand 1 "call_insn_operand" "ri"))
2018 (match_operand 2 "" "i")))
2019 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2023 register rtx target = operands[1];
2025 if (GET_CODE (target) == CONST_INT)
2026 return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
2027 else if (CONSTANT_ADDRESS_P (target))
2028 return \"jal\\t%1\";
2030 return \"jalr\\t%3,%1\";
2032 [(set_attr "type" "call")
2033 (set_attr "mode" "none")])
2035 (define_expand "call_value_multiple_internal0"
2036 [(parallel [(set (match_operand 0 "" "")
2037 (call (match_operand 1 "" "")
2038 (match_operand 2 "" "")))
2039 (set (match_operand 3 "" "")
2042 (clobber (match_operand:SI 4 "" ""))])]
2046 ;; ??? May eventually need all 6 versions of the call patterns with multiple
2049 (define_insn "call_value_multiple_internal1"
2050 [(set (match_operand 0 "register_operand" "=df")
2051 (call (mem (match_operand 1 "call_insn_operand" "ri"))
2052 (match_operand 2 "" "i")))
2053 (set (match_operand 3 "register_operand" "=df")
2054 (call (mem (match_dup 1))
2056 (clobber (match_operand:SI 4 "register_operand" "=d"))]
2060 register rtx target = operands[1];
2062 if (GET_CODE (target) == CONST_INT)
2063 return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
2064 else if (CONSTANT_ADDRESS_P (target))
2065 return \"jal\\t%1\";
2067 return \"jalr\\t%4,%1\";
2069 [(set_attr "type" "call")
2070 (set_attr "mode" "none")])
2072 ;; Call subroutine returning any type.
2074 (define_expand "untyped_call"
2075 [(parallel [(call (match_operand 0 "" "")
2077 (match_operand 1 "" "")
2078 (match_operand 2 "" "")])]
2082 if (operands[0]) /* silence statement not reached warnings */
2086 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
2088 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2090 rtx set = XVECEXP (operands[2], 0, i);
2091 emit_move_insn (SET_DEST (set), SET_SRC (set));
2094 emit_insn (gen_blockage ());
2100 ;; ....................
2104 ;; ....................
2111 [(set_attr "type" "nop")
2112 (set_attr "mode" "none")])
2115 ;; For the rare case where we need to load an address into a register
2116 ;; that cannot be recognized by the normal movsi/addsi instructions.
2117 ;; I have no idea how many insns this can actually generate. It should
2118 ;; be rare, so over-estimating as 10 instructions should not have any
2119 ;; real performance impact.
2120 (define_insn "leasi"
2121 [(set (match_operand:SI 0 "register_operand" "=d")
2122 (match_operand:SI 1 "address_operand" "p"))]
2128 xoperands[0] = operands[0];
2129 xoperands[1] = XEXP (operands[1], 0);
2130 xoperands[2] = XEXP (operands[1], 1);
2131 output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands);
2134 [(set_attr "type" "arith")
2135 (set_attr "mode" "SI")
2136 (set_attr "length" "40")])
2138 (define_insn "ado16"
2139 [(set (match_operand:SI 0 "register_operand" "=r")
2140 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2141 (match_operand:SI 2 "register_operand" "r")]
2144 "ado16\\t%0, %1, %2"
2148 [(set (match_operand:SI 0 "register_operand" "=r")
2149 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2150 (match_operand:SI 2 "const_int_operand" "I")
2151 (match_operand:SI 3 "const_int_operand" "I")
2152 (match_operand:SI 4 "const_int_operand" "I")]
2155 "ram\\t%0, %1, %2, %3, %4"
2158 (define_insn "chkhdr"
2159 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r")
2160 (match_operand:SI 1 "register_operand" "r")]
2163 "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);"
2164 [(set_attr "dslot" "not_in_dslot")]
2168 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2169 (match_operand:SI 1 "register_operand" "r")]
2172 "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);"
2173 [(set_attr "dslot" "not_in_dslot")]
2177 [(set (match_operand:SI 0 "register_operand" "=r")
2178 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2181 "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2182 [(set_attr "dslot" "ok_in_dslot")]
2186 [(set (match_operand:SI 0 "register_operand" "=r")
2187 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2190 "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2191 [(set_attr "dslot" "ok_in_dslot")]
2195 [(set (match_operand:SI 0 "register_operand" "=r")
2196 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2199 "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2200 [(set_attr "dslot" "not_in_dslot")]
2204 [(set (match_operand:SI 0 "register_operand" "=r")
2205 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2208 "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2209 [(set_attr "dslot" "not_in_dslot")]
2213 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2214 (match_operand:SI 1 "const_int_operand" "I")]
2217 "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2218 [(set_attr "dslot" "ok_in_dslot")]
2222 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2223 (match_operand:SI 1 "const_int_operand" "I")]
2226 "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2227 [(set_attr "dslot" "ok_in_dslot")]
2231 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2232 (match_operand:SI 1 "const_int_operand" "I")]
2235 "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2236 [(set_attr "dslot" "ok_in_dslot")]
2240 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2241 (match_operand:SI 1 "const_int_operand" "I")]
2244 "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2245 [(set_attr "dslot" "ok_in_dslot")]
2249 [(set (match_operand:SI 0 "register_operand" "=r")
2250 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2253 "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2254 [(set_attr "dslot" "ok_in_dslot")]
2258 [(set (match_operand:SI 0 "register_operand" "=r")
2259 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2262 "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2263 [(set_attr "dslot" "ok_in_dslot")]
2267 [(set (match_operand:SI 0 "register_operand" "=r")
2268 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2271 "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2272 [(set_attr "dslot" "not_in_dslot")]
2276 [(set (match_operand:SI 0 "register_operand" "=r")
2277 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2280 "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2281 [(set_attr "dslot" "not_in_dslot")]
2285 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2286 (match_operand:SI 1 "const_int_operand" "I")]
2289 "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2290 [(set_attr "dslot" "ok_in_dslot")]
2294 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2295 (match_operand:SI 1 "const_int_operand" "I")]
2298 "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2299 [(set_attr "dslot" "ok_in_dslot")]
2303 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2304 (match_operand:SI 1 "const_int_operand" "I")]
2307 "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2308 [(set_attr "dslot" "ok_in_dslot")]
2312 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2313 (match_operand:SI 1 "const_int_operand" "I")]
2316 "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2317 [(set_attr "dslot" "ok_in_dslot")]
2321 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2322 (match_operand:SI 1 "register_operand" "r")]
2325 "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);"
2326 [(set_attr "dslot" "not_in_dslot")]
2330 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2331 (match_operand:SI 1 "register_operand" "r")]
2334 "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);"
2335 [(set_attr "dslot" "not_in_dslot")]
2339 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2340 (match_operand:SI 1 "register_operand" "r")]
2343 "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);"
2344 [(set_attr "dslot" "not_in_dslot")]
2348 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2351 "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);"
2352 [(set_attr "dslot" "not_in_dslot")]
2356 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2357 (match_operand:SI 1 "register_operand" "r")]
2360 "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);"
2361 [(set_attr "dslot" "not_in_dslot")]
2365 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2366 (match_operand:SI 1 "register_operand" "r")]
2369 "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);"
2370 [(set_attr "dslot" "not_in_dslot")]
2374 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2375 (match_operand:SI 1 "register_operand" "r")]
2378 "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);"
2379 [(set_attr "dslot" "not_in_dslot")]
2382 (define_insn "luc32"
2383 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2384 (match_operand:SI 1 "register_operand" "r")]
2387 "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);"
2388 [(set_attr "dslot" "not_in_dslot")]
2391 (define_insn "luc32l"
2392 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2393 (match_operand:SI 1 "register_operand" "r")]
2396 "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2397 [(set_attr "dslot" "not_in_dslot")]
2400 (define_insn "luc64"
2401 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2402 (match_operand:SI 1 "register_operand" "r")]
2405 "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);"
2406 [(set_attr "dslot" "not_in_dslot")]
2409 (define_insn "luc64l"
2410 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2411 (match_operand:SI 1 "register_operand" "r")]
2414 "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2415 [(set_attr "dslot" "not_in_dslot")]
2419 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2420 (match_operand:SI 1 "register_operand" "r")]
2423 "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);"
2424 [(set_attr "dslot" "ok_in_dslot")]
2427 (define_insn "lulck"
2428 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2431 "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);"
2432 [(set_attr "dslot" "not_in_dslot")]
2435 (define_insn "lum32"
2436 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2437 (match_operand:SI 1 "register_operand" "r")]
2440 "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);"
2441 [(set_attr "dslot" "not_in_dslot")]
2444 (define_insn "lum32l"
2445 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2446 (match_operand:SI 1 "register_operand" "r")]
2449 "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2450 [(set_attr "dslot" "not_in_dslot")]
2453 (define_insn "lum64"
2454 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2455 (match_operand:SI 1 "register_operand" "r")]
2458 "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);"
2459 [(set_attr "dslot" "not_in_dslot")]
2462 (define_insn "lum64l"
2463 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2464 (match_operand:SI 1 "register_operand" "r")]
2467 "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2468 [(set_attr "dslot" "not_in_dslot")]
2472 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2473 (match_operand:SI 1 "register_operand" "r")]
2476 "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);"
2477 [(set_attr "dslot" "not_in_dslot")]
2481 [(set (match_operand:SI 0 "register_operand" "=r")
2482 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
2483 (match_operand:SI 2 "register_operand" "r")
2484 (match_operand:SI 3 "const_int_operand" "I")]
2487 "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);"
2488 [(set_attr "dslot" "ok_in_dslot")]
2491 (define_insn "srrdl"
2492 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2495 "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);"
2496 [(set_attr "dslot" "not_in_dslot")]
2499 (define_insn "srulck"
2500 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2503 "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);"
2504 [(set_attr "dslot" "not_in_dslot")]
2507 (define_insn "srwru"
2508 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2509 (match_operand:SI 1 "register_operand" "r")]
2512 "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);"
2513 [(set_attr "dslot" "not_in_dslot")]
2516 (define_insn "trapqfl"
2517 [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)]
2519 "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);"
2520 [(set_attr "dslot" "not_in_dslot")]
2523 (define_insn "trapqne"
2524 [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)]
2526 "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);"
2527 [(set_attr "dslot" "not_in_dslot")]
2530 (define_insn "traprel"
2531 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2534 "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);"
2535 [(set_attr "dslot" "not_in_dslot")]
2539 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2540 (match_operand:SI 1 "register_operand" "r")]
2543 "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);"
2544 [(set_attr "dslot" "not_in_dslot")]
2547 (define_insn "syscall"
2548 [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)]
2551 [(set_attr "dslot" "not_in_dslot")]