[RTL-ifcvt] PR rtl-optimization/68506: Fix emitting order of insns in IF-THEN-JOIN...
[official-gcc.git] / gcc / recog.c
blob028190a61a4aa27618fef9b3dfea91173464609f
1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "backend.h"
25 #include "target.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "cfghooks.h"
29 #include "df.h"
30 #include "tm_p.h"
31 #include "insn-config.h"
32 #include "regs.h"
33 #include "emit-rtl.h"
34 #include "recog.h"
35 #include "insn-attr.h"
36 #include "addresses.h"
37 #include "cfgrtl.h"
38 #include "cfgbuild.h"
39 #include "cfgcleanup.h"
40 #include "reload.h"
41 #include "tree-pass.h"
43 #ifndef STACK_POP_CODE
44 #if STACK_GROWS_DOWNWARD
45 #define STACK_POP_CODE POST_INC
46 #else
47 #define STACK_POP_CODE POST_DEC
48 #endif
49 #endif
51 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx_insn *, bool);
52 static void validate_replace_src_1 (rtx *, void *);
53 static rtx_insn *split_insn (rtx_insn *);
55 struct target_recog default_target_recog;
56 #if SWITCHABLE_TARGET
57 struct target_recog *this_target_recog = &default_target_recog;
58 #endif
60 /* Nonzero means allow operands to be volatile.
61 This should be 0 if you are generating rtl, such as if you are calling
62 the functions in optabs.c and expmed.c (most of the time).
63 This should be 1 if all valid insns need to be recognized,
64 such as in reginfo.c and final.c and reload.c.
66 init_recog and init_recog_no_volatile are responsible for setting this. */
68 int volatile_ok;
70 struct recog_data_d recog_data;
72 /* Contains a vector of operand_alternative structures, such that
73 operand OP of alternative A is at index A * n_operands + OP.
74 Set up by preprocess_constraints. */
75 const operand_alternative *recog_op_alt;
77 /* Used to provide recog_op_alt for asms. */
78 static operand_alternative asm_op_alt[MAX_RECOG_OPERANDS
79 * MAX_RECOG_ALTERNATIVES];
81 /* On return from `constrain_operands', indicate which alternative
82 was satisfied. */
84 int which_alternative;
86 /* Nonzero after end of reload pass.
87 Set to 1 or 0 by toplev.c.
88 Controls the significance of (SUBREG (MEM)). */
90 int reload_completed;
92 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
93 int epilogue_completed;
95 /* Initialize data used by the function `recog'.
96 This must be called once in the compilation of a function
97 before any insn recognition may be done in the function. */
99 void
100 init_recog_no_volatile (void)
102 volatile_ok = 0;
105 void
106 init_recog (void)
108 volatile_ok = 1;
112 /* Return true if labels in asm operands BODY are LABEL_REFs. */
114 static bool
115 asm_labels_ok (rtx body)
117 rtx asmop;
118 int i;
120 asmop = extract_asm_operands (body);
121 if (asmop == NULL_RTX)
122 return true;
124 for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++)
125 if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF)
126 return false;
128 return true;
131 /* Check that X is an insn-body for an `asm' with operands
132 and that the operands mentioned in it are legitimate. */
135 check_asm_operands (rtx x)
137 int noperands;
138 rtx *operands;
139 const char **constraints;
140 int i;
142 if (!asm_labels_ok (x))
143 return 0;
145 /* Post-reload, be more strict with things. */
146 if (reload_completed)
148 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
149 rtx_insn *insn = make_insn_raw (x);
150 extract_insn (insn);
151 constrain_operands (1, get_enabled_alternatives (insn));
152 return which_alternative >= 0;
155 noperands = asm_noperands (x);
156 if (noperands < 0)
157 return 0;
158 if (noperands == 0)
159 return 1;
161 operands = XALLOCAVEC (rtx, noperands);
162 constraints = XALLOCAVEC (const char *, noperands);
164 decode_asm_operands (x, operands, NULL, constraints, NULL, NULL);
166 for (i = 0; i < noperands; i++)
168 const char *c = constraints[i];
169 if (c[0] == '%')
170 c++;
171 if (! asm_operand_ok (operands[i], c, constraints))
172 return 0;
175 return 1;
178 /* Static data for the next two routines. */
180 struct change_t
182 rtx object;
183 int old_code;
184 rtx *loc;
185 rtx old;
186 bool unshare;
189 static change_t *changes;
190 static int changes_allocated;
192 static int num_changes = 0;
194 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
195 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
196 the change is simply made.
198 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
199 will be called with the address and mode as parameters. If OBJECT is
200 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
201 the change in place.
203 IN_GROUP is nonzero if this is part of a group of changes that must be
204 performed as a group. In that case, the changes will be stored. The
205 function `apply_change_group' will validate and apply the changes.
207 If IN_GROUP is zero, this is a single change. Try to recognize the insn
208 or validate the memory reference with the change applied. If the result
209 is not valid for the machine, suppress the change and return zero.
210 Otherwise, perform the change and return 1. */
212 static bool
213 validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, bool unshare)
215 rtx old = *loc;
217 if (old == new_rtx || rtx_equal_p (old, new_rtx))
218 return 1;
220 gcc_assert (in_group != 0 || num_changes == 0);
222 *loc = new_rtx;
224 /* Save the information describing this change. */
225 if (num_changes >= changes_allocated)
227 if (changes_allocated == 0)
228 /* This value allows for repeated substitutions inside complex
229 indexed addresses, or changes in up to 5 insns. */
230 changes_allocated = MAX_RECOG_OPERANDS * 5;
231 else
232 changes_allocated *= 2;
234 changes = XRESIZEVEC (change_t, changes, changes_allocated);
237 changes[num_changes].object = object;
238 changes[num_changes].loc = loc;
239 changes[num_changes].old = old;
240 changes[num_changes].unshare = unshare;
242 if (object && !MEM_P (object))
244 /* Set INSN_CODE to force rerecognition of insn. Save old code in
245 case invalid. */
246 changes[num_changes].old_code = INSN_CODE (object);
247 INSN_CODE (object) = -1;
250 num_changes++;
252 /* If we are making a group of changes, return 1. Otherwise, validate the
253 change group we made. */
255 if (in_group)
256 return 1;
257 else
258 return apply_change_group ();
261 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
262 UNSHARE to false. */
264 bool
265 validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
267 return validate_change_1 (object, loc, new_rtx, in_group, false);
270 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
271 UNSHARE to true. */
273 bool
274 validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
276 return validate_change_1 (object, loc, new_rtx, in_group, true);
280 /* Keep X canonicalized if some changes have made it non-canonical; only
281 modifies the operands of X, not (for example) its code. Simplifications
282 are not the job of this routine.
284 Return true if anything was changed. */
285 bool
286 canonicalize_change_group (rtx_insn *insn, rtx x)
288 if (COMMUTATIVE_P (x)
289 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
291 /* Oops, the caller has made X no longer canonical.
292 Let's redo the changes in the correct order. */
293 rtx tem = XEXP (x, 0);
294 validate_unshare_change (insn, &XEXP (x, 0), XEXP (x, 1), 1);
295 validate_unshare_change (insn, &XEXP (x, 1), tem, 1);
296 return true;
298 else
299 return false;
303 /* This subroutine of apply_change_group verifies whether the changes to INSN
304 were valid; i.e. whether INSN can still be recognized.
306 If IN_GROUP is true clobbers which have to be added in order to
307 match the instructions will be added to the current change group.
308 Otherwise the changes will take effect immediately. */
311 insn_invalid_p (rtx_insn *insn, bool in_group)
313 rtx pat = PATTERN (insn);
314 int num_clobbers = 0;
315 /* If we are before reload and the pattern is a SET, see if we can add
316 clobbers. */
317 int icode = recog (pat, insn,
318 (GET_CODE (pat) == SET
319 && ! reload_completed
320 && ! reload_in_progress)
321 ? &num_clobbers : 0);
322 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
325 /* If this is an asm and the operand aren't legal, then fail. Likewise if
326 this is not an asm and the insn wasn't recognized. */
327 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
328 || (!is_asm && icode < 0))
329 return 1;
331 /* If we have to add CLOBBERs, fail if we have to add ones that reference
332 hard registers since our callers can't know if they are live or not.
333 Otherwise, add them. */
334 if (num_clobbers > 0)
336 rtx newpat;
338 if (added_clobbers_hard_reg_p (icode))
339 return 1;
341 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
342 XVECEXP (newpat, 0, 0) = pat;
343 add_clobbers (newpat, icode);
344 if (in_group)
345 validate_change (insn, &PATTERN (insn), newpat, 1);
346 else
347 PATTERN (insn) = pat = newpat;
350 /* After reload, verify that all constraints are satisfied. */
351 if (reload_completed)
353 extract_insn (insn);
355 if (! constrain_operands (1, get_preferred_alternatives (insn)))
356 return 1;
359 INSN_CODE (insn) = icode;
360 return 0;
363 /* Return number of changes made and not validated yet. */
365 num_changes_pending (void)
367 return num_changes;
370 /* Tentatively apply the changes numbered NUM and up.
371 Return 1 if all changes are valid, zero otherwise. */
374 verify_changes (int num)
376 int i;
377 rtx last_validated = NULL_RTX;
379 /* The changes have been applied and all INSN_CODEs have been reset to force
380 rerecognition.
382 The changes are valid if we aren't given an object, or if we are
383 given a MEM and it still is a valid address, or if this is in insn
384 and it is recognized. In the latter case, if reload has completed,
385 we also require that the operands meet the constraints for
386 the insn. */
388 for (i = num; i < num_changes; i++)
390 rtx object = changes[i].object;
392 /* If there is no object to test or if it is the same as the one we
393 already tested, ignore it. */
394 if (object == 0 || object == last_validated)
395 continue;
397 if (MEM_P (object))
399 if (! memory_address_addr_space_p (GET_MODE (object),
400 XEXP (object, 0),
401 MEM_ADDR_SPACE (object)))
402 break;
404 else if (/* changes[i].old might be zero, e.g. when putting a
405 REG_FRAME_RELATED_EXPR into a previously empty list. */
406 changes[i].old
407 && REG_P (changes[i].old)
408 && asm_noperands (PATTERN (object)) > 0
409 && REG_EXPR (changes[i].old) != NULL_TREE
410 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old))
411 && DECL_REGISTER (REG_EXPR (changes[i].old)))
413 /* Don't allow changes of hard register operands to inline
414 assemblies if they have been defined as register asm ("x"). */
415 break;
417 else if (DEBUG_INSN_P (object))
418 continue;
419 else if (insn_invalid_p (as_a <rtx_insn *> (object), true))
421 rtx pat = PATTERN (object);
423 /* Perhaps we couldn't recognize the insn because there were
424 extra CLOBBERs at the end. If so, try to re-recognize
425 without the last CLOBBER (later iterations will cause each of
426 them to be eliminated, in turn). But don't do this if we
427 have an ASM_OPERAND. */
428 if (GET_CODE (pat) == PARALLEL
429 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
430 && asm_noperands (PATTERN (object)) < 0)
432 rtx newpat;
434 if (XVECLEN (pat, 0) == 2)
435 newpat = XVECEXP (pat, 0, 0);
436 else
438 int j;
440 newpat
441 = gen_rtx_PARALLEL (VOIDmode,
442 rtvec_alloc (XVECLEN (pat, 0) - 1));
443 for (j = 0; j < XVECLEN (newpat, 0); j++)
444 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
447 /* Add a new change to this group to replace the pattern
448 with this new pattern. Then consider this change
449 as having succeeded. The change we added will
450 cause the entire call to fail if things remain invalid.
452 Note that this can lose if a later change than the one
453 we are processing specified &XVECEXP (PATTERN (object), 0, X)
454 but this shouldn't occur. */
456 validate_change (object, &PATTERN (object), newpat, 1);
457 continue;
459 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
460 || GET_CODE (pat) == VAR_LOCATION)
461 /* If this insn is a CLOBBER or USE, it is always valid, but is
462 never recognized. */
463 continue;
464 else
465 break;
467 last_validated = object;
470 return (i == num_changes);
473 /* A group of changes has previously been issued with validate_change
474 and verified with verify_changes. Call df_insn_rescan for each of
475 the insn changed and clear num_changes. */
477 void
478 confirm_change_group (void)
480 int i;
481 rtx last_object = NULL;
483 for (i = 0; i < num_changes; i++)
485 rtx object = changes[i].object;
487 if (changes[i].unshare)
488 *changes[i].loc = copy_rtx (*changes[i].loc);
490 /* Avoid unnecessary rescanning when multiple changes to same instruction
491 are made. */
492 if (object)
494 if (object != last_object && last_object && INSN_P (last_object))
495 df_insn_rescan (as_a <rtx_insn *> (last_object));
496 last_object = object;
500 if (last_object && INSN_P (last_object))
501 df_insn_rescan (as_a <rtx_insn *> (last_object));
502 num_changes = 0;
505 /* Apply a group of changes previously issued with `validate_change'.
506 If all changes are valid, call confirm_change_group and return 1,
507 otherwise, call cancel_changes and return 0. */
510 apply_change_group (void)
512 if (verify_changes (0))
514 confirm_change_group ();
515 return 1;
517 else
519 cancel_changes (0);
520 return 0;
525 /* Return the number of changes so far in the current group. */
528 num_validated_changes (void)
530 return num_changes;
533 /* Retract the changes numbered NUM and up. */
535 void
536 cancel_changes (int num)
538 int i;
540 /* Back out all the changes. Do this in the opposite order in which
541 they were made. */
542 for (i = num_changes - 1; i >= num; i--)
544 *changes[i].loc = changes[i].old;
545 if (changes[i].object && !MEM_P (changes[i].object))
546 INSN_CODE (changes[i].object) = changes[i].old_code;
548 num_changes = num;
551 /* Reduce conditional compilation elsewhere. */
552 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
553 rtx. */
555 static void
556 simplify_while_replacing (rtx *loc, rtx to, rtx_insn *object,
557 machine_mode op0_mode)
559 rtx x = *loc;
560 enum rtx_code code = GET_CODE (x);
561 rtx new_rtx = NULL_RTX;
563 if (SWAPPABLE_OPERANDS_P (x)
564 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
566 validate_unshare_change (object, loc,
567 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? code
568 : swap_condition (code),
569 GET_MODE (x), XEXP (x, 1),
570 XEXP (x, 0)), 1);
571 x = *loc;
572 code = GET_CODE (x);
575 /* Canonicalize arithmetics with all constant operands. */
576 switch (GET_RTX_CLASS (code))
578 case RTX_UNARY:
579 if (CONSTANT_P (XEXP (x, 0)))
580 new_rtx = simplify_unary_operation (code, GET_MODE (x), XEXP (x, 0),
581 op0_mode);
582 break;
583 case RTX_COMM_ARITH:
584 case RTX_BIN_ARITH:
585 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
586 new_rtx = simplify_binary_operation (code, GET_MODE (x), XEXP (x, 0),
587 XEXP (x, 1));
588 break;
589 case RTX_COMPARE:
590 case RTX_COMM_COMPARE:
591 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
592 new_rtx = simplify_relational_operation (code, GET_MODE (x), op0_mode,
593 XEXP (x, 0), XEXP (x, 1));
594 break;
595 default:
596 break;
598 if (new_rtx)
600 validate_change (object, loc, new_rtx, 1);
601 return;
604 switch (code)
606 case PLUS:
607 /* If we have a PLUS whose second operand is now a CONST_INT, use
608 simplify_gen_binary to try to simplify it.
609 ??? We may want later to remove this, once simplification is
610 separated from this function. */
611 if (CONST_INT_P (XEXP (x, 1)) && XEXP (x, 1) == to)
612 validate_change (object, loc,
613 simplify_gen_binary
614 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
615 break;
616 case MINUS:
617 if (CONST_SCALAR_INT_P (XEXP (x, 1)))
618 validate_change (object, loc,
619 simplify_gen_binary
620 (PLUS, GET_MODE (x), XEXP (x, 0),
621 simplify_gen_unary (NEG,
622 GET_MODE (x), XEXP (x, 1),
623 GET_MODE (x))), 1);
624 break;
625 case ZERO_EXTEND:
626 case SIGN_EXTEND:
627 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
629 new_rtx = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0),
630 op0_mode);
631 /* If any of the above failed, substitute in something that
632 we know won't be recognized. */
633 if (!new_rtx)
634 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
635 validate_change (object, loc, new_rtx, 1);
637 break;
638 case SUBREG:
639 /* All subregs possible to simplify should be simplified. */
640 new_rtx = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode,
641 SUBREG_BYTE (x));
643 /* Subregs of VOIDmode operands are incorrect. */
644 if (!new_rtx && GET_MODE (SUBREG_REG (x)) == VOIDmode)
645 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
646 if (new_rtx)
647 validate_change (object, loc, new_rtx, 1);
648 break;
649 case ZERO_EXTRACT:
650 case SIGN_EXTRACT:
651 /* If we are replacing a register with memory, try to change the memory
652 to be the mode required for memory in extract operations (this isn't
653 likely to be an insertion operation; if it was, nothing bad will
654 happen, we might just fail in some cases). */
656 if (MEM_P (XEXP (x, 0))
657 && CONST_INT_P (XEXP (x, 1))
658 && CONST_INT_P (XEXP (x, 2))
659 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0),
660 MEM_ADDR_SPACE (XEXP (x, 0)))
661 && !MEM_VOLATILE_P (XEXP (x, 0)))
663 machine_mode wanted_mode = VOIDmode;
664 machine_mode is_mode = GET_MODE (XEXP (x, 0));
665 int pos = INTVAL (XEXP (x, 2));
667 if (GET_CODE (x) == ZERO_EXTRACT && targetm.have_extzv ())
669 wanted_mode = insn_data[targetm.code_for_extzv].operand[1].mode;
670 if (wanted_mode == VOIDmode)
671 wanted_mode = word_mode;
673 else if (GET_CODE (x) == SIGN_EXTRACT && targetm.have_extv ())
675 wanted_mode = insn_data[targetm.code_for_extv].operand[1].mode;
676 if (wanted_mode == VOIDmode)
677 wanted_mode = word_mode;
680 /* If we have a narrower mode, we can do something. */
681 if (wanted_mode != VOIDmode
682 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
684 int offset = pos / BITS_PER_UNIT;
685 rtx newmem;
687 /* If the bytes and bits are counted differently, we
688 must adjust the offset. */
689 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
690 offset =
691 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
692 offset);
694 gcc_assert (GET_MODE_PRECISION (wanted_mode)
695 == GET_MODE_BITSIZE (wanted_mode));
696 pos %= GET_MODE_BITSIZE (wanted_mode);
698 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset);
700 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
701 validate_change (object, &XEXP (x, 0), newmem, 1);
705 break;
707 default:
708 break;
712 /* Replace every occurrence of FROM in X with TO. Mark each change with
713 validate_change passing OBJECT. */
715 static void
716 validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object,
717 bool simplify)
719 int i, j;
720 const char *fmt;
721 rtx x = *loc;
722 enum rtx_code code;
723 machine_mode op0_mode = VOIDmode;
724 int prev_changes = num_changes;
726 if (!x)
727 return;
729 code = GET_CODE (x);
730 fmt = GET_RTX_FORMAT (code);
731 if (fmt[0] == 'e')
732 op0_mode = GET_MODE (XEXP (x, 0));
734 /* X matches FROM if it is the same rtx or they are both referring to the
735 same register in the same mode. Avoid calling rtx_equal_p unless the
736 operands look similar. */
738 if (x == from
739 || (REG_P (x) && REG_P (from)
740 && GET_MODE (x) == GET_MODE (from)
741 && REGNO (x) == REGNO (from))
742 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
743 && rtx_equal_p (x, from)))
745 validate_unshare_change (object, loc, to, 1);
746 return;
749 /* Call ourself recursively to perform the replacements.
750 We must not replace inside already replaced expression, otherwise we
751 get infinite recursion for replacements like (reg X)->(subreg (reg X))
752 so we must special case shared ASM_OPERANDS. */
754 if (GET_CODE (x) == PARALLEL)
756 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
758 if (j && GET_CODE (XVECEXP (x, 0, j)) == SET
759 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == ASM_OPERANDS)
761 /* Verify that operands are really shared. */
762 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0)))
763 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
764 (x, 0, j))));
765 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j)),
766 from, to, object, simplify);
768 else
769 validate_replace_rtx_1 (&XVECEXP (x, 0, j), from, to, object,
770 simplify);
773 else
774 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
776 if (fmt[i] == 'e')
777 validate_replace_rtx_1 (&XEXP (x, i), from, to, object, simplify);
778 else if (fmt[i] == 'E')
779 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
780 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object,
781 simplify);
784 /* If we didn't substitute, there is nothing more to do. */
785 if (num_changes == prev_changes)
786 return;
788 /* ??? The regmove is no more, so is this aberration still necessary? */
789 /* Allow substituted expression to have different mode. This is used by
790 regmove to change mode of pseudo register. */
791 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode)
792 op0_mode = GET_MODE (XEXP (x, 0));
794 /* Do changes needed to keep rtx consistent. Don't do any other
795 simplifications, as it is not our job. */
796 if (simplify)
797 simplify_while_replacing (loc, to, object, op0_mode);
800 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
801 with TO. After all changes have been made, validate by seeing
802 if INSN is still valid. */
805 validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
807 validate_replace_rtx_1 (loc, from, to, insn, true);
808 return apply_change_group ();
811 /* Try replacing every occurrence of FROM in INSN with TO. After all
812 changes have been made, validate by seeing if INSN is still valid. */
815 validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
817 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
818 return apply_change_group ();
821 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
822 is a part of INSN. After all changes have been made, validate by seeing if
823 INSN is still valid.
824 validate_replace_rtx (from, to, insn) is equivalent to
825 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
828 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
830 validate_replace_rtx_1 (where, from, to, insn, true);
831 return apply_change_group ();
834 /* Same as above, but do not simplify rtx afterwards. */
836 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
837 rtx_insn *insn)
839 validate_replace_rtx_1 (where, from, to, insn, false);
840 return apply_change_group ();
844 /* Try replacing every occurrence of FROM in INSN with TO. This also
845 will replace in REG_EQUAL and REG_EQUIV notes. */
847 void
848 validate_replace_rtx_group (rtx from, rtx to, rtx_insn *insn)
850 rtx note;
851 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
852 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
853 if (REG_NOTE_KIND (note) == REG_EQUAL
854 || REG_NOTE_KIND (note) == REG_EQUIV)
855 validate_replace_rtx_1 (&XEXP (note, 0), from, to, insn, true);
858 /* Function called by note_uses to replace used subexpressions. */
859 struct validate_replace_src_data
861 rtx from; /* Old RTX */
862 rtx to; /* New RTX */
863 rtx_insn *insn; /* Insn in which substitution is occurring. */
866 static void
867 validate_replace_src_1 (rtx *x, void *data)
869 struct validate_replace_src_data *d
870 = (struct validate_replace_src_data *) data;
872 validate_replace_rtx_1 (x, d->from, d->to, d->insn, true);
875 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
876 SET_DESTs. */
878 void
879 validate_replace_src_group (rtx from, rtx to, rtx_insn *insn)
881 struct validate_replace_src_data d;
883 d.from = from;
884 d.to = to;
885 d.insn = insn;
886 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
889 /* Try simplify INSN.
890 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
891 pattern and return true if something was simplified. */
893 bool
894 validate_simplify_insn (rtx_insn *insn)
896 int i;
897 rtx pat = NULL;
898 rtx newpat = NULL;
900 pat = PATTERN (insn);
902 if (GET_CODE (pat) == SET)
904 newpat = simplify_rtx (SET_SRC (pat));
905 if (newpat && !rtx_equal_p (SET_SRC (pat), newpat))
906 validate_change (insn, &SET_SRC (pat), newpat, 1);
907 newpat = simplify_rtx (SET_DEST (pat));
908 if (newpat && !rtx_equal_p (SET_DEST (pat), newpat))
909 validate_change (insn, &SET_DEST (pat), newpat, 1);
911 else if (GET_CODE (pat) == PARALLEL)
912 for (i = 0; i < XVECLEN (pat, 0); i++)
914 rtx s = XVECEXP (pat, 0, i);
916 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
918 newpat = simplify_rtx (SET_SRC (s));
919 if (newpat && !rtx_equal_p (SET_SRC (s), newpat))
920 validate_change (insn, &SET_SRC (s), newpat, 1);
921 newpat = simplify_rtx (SET_DEST (s));
922 if (newpat && !rtx_equal_p (SET_DEST (s), newpat))
923 validate_change (insn, &SET_DEST (s), newpat, 1);
926 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
929 /* Return 1 if the insn using CC0 set by INSN does not contain
930 any ordered tests applied to the condition codes.
931 EQ and NE tests do not count. */
934 next_insn_tests_no_inequality (rtx_insn *insn)
936 rtx_insn *next = next_cc0_user (insn);
938 /* If there is no next insn, we have to take the conservative choice. */
939 if (next == 0)
940 return 0;
942 return (INSN_P (next)
943 && ! inequality_comparisons_p (PATTERN (next)));
946 /* Return 1 if OP is a valid general operand for machine mode MODE.
947 This is either a register reference, a memory reference,
948 or a constant. In the case of a memory reference, the address
949 is checked for general validity for the target machine.
951 Register and memory references must have mode MODE in order to be valid,
952 but some constants have no machine mode and are valid for any mode.
954 If MODE is VOIDmode, OP is checked for validity for whatever mode
955 it has.
957 The main use of this function is as a predicate in match_operand
958 expressions in the machine description. */
961 general_operand (rtx op, machine_mode mode)
963 enum rtx_code code = GET_CODE (op);
965 if (mode == VOIDmode)
966 mode = GET_MODE (op);
968 /* Don't accept CONST_INT or anything similar
969 if the caller wants something floating. */
970 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
971 && GET_MODE_CLASS (mode) != MODE_INT
972 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
973 return 0;
975 if (CONST_INT_P (op)
976 && mode != VOIDmode
977 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
978 return 0;
980 if (CONSTANT_P (op))
981 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
982 || mode == VOIDmode)
983 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
984 && targetm.legitimate_constant_p (mode == VOIDmode
985 ? GET_MODE (op)
986 : mode, op));
988 /* Except for certain constants with VOIDmode, already checked for,
989 OP's mode must match MODE if MODE specifies a mode. */
991 if (GET_MODE (op) != mode)
992 return 0;
994 if (code == SUBREG)
996 rtx sub = SUBREG_REG (op);
998 #ifdef INSN_SCHEDULING
999 /* On machines that have insn scheduling, we want all memory
1000 reference to be explicit, so outlaw paradoxical SUBREGs.
1001 However, we must allow them after reload so that they can
1002 get cleaned up by cleanup_subreg_operands. */
1003 if (!reload_completed && MEM_P (sub)
1004 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (sub)))
1005 return 0;
1006 #endif
1007 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1008 may result in incorrect reference. We should simplify all valid
1009 subregs of MEM anyway. But allow this after reload because we
1010 might be called from cleanup_subreg_operands.
1012 ??? This is a kludge. */
1013 if (!reload_completed && SUBREG_BYTE (op) != 0
1014 && MEM_P (sub))
1015 return 0;
1017 #ifdef CANNOT_CHANGE_MODE_CLASS
1018 if (REG_P (sub)
1019 && REGNO (sub) < FIRST_PSEUDO_REGISTER
1020 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
1021 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
1022 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT
1023 /* LRA can generate some invalid SUBREGS just for matched
1024 operand reload presentation. LRA needs to treat them as
1025 valid. */
1026 && ! LRA_SUBREG_P (op))
1027 return 0;
1028 #endif
1030 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1031 create such rtl, and we must reject it. */
1032 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
1033 /* LRA can use subreg to store a floating point value in an
1034 integer mode. Although the floating point and the
1035 integer modes need the same number of hard registers, the
1036 size of floating point mode can be less than the integer
1037 mode. */
1038 && ! lra_in_progress
1039 && GET_MODE_SIZE (GET_MODE (op)) > GET_MODE_SIZE (GET_MODE (sub)))
1040 return 0;
1042 op = sub;
1043 code = GET_CODE (op);
1046 if (code == REG)
1047 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
1048 || in_hard_reg_set_p (operand_reg_set, GET_MODE (op), REGNO (op)));
1050 if (code == MEM)
1052 rtx y = XEXP (op, 0);
1054 if (! volatile_ok && MEM_VOLATILE_P (op))
1055 return 0;
1057 /* Use the mem's mode, since it will be reloaded thus. LRA can
1058 generate move insn with invalid addresses which is made valid
1059 and efficiently calculated by LRA through further numerous
1060 transformations. */
1061 if (lra_in_progress
1062 || memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op)))
1063 return 1;
1066 return 0;
1069 /* Return 1 if OP is a valid memory address for a memory reference
1070 of mode MODE.
1072 The main use of this function is as a predicate in match_operand
1073 expressions in the machine description. */
1076 address_operand (rtx op, machine_mode mode)
1078 return memory_address_p (mode, op);
1081 /* Return 1 if OP is a register reference of mode MODE.
1082 If MODE is VOIDmode, accept a register in any mode.
1084 The main use of this function is as a predicate in match_operand
1085 expressions in the machine description. */
1088 register_operand (rtx op, machine_mode mode)
1090 if (GET_CODE (op) == SUBREG)
1092 rtx sub = SUBREG_REG (op);
1094 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1095 because it is guaranteed to be reloaded into one.
1096 Just make sure the MEM is valid in itself.
1097 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1098 but currently it does result from (SUBREG (REG)...) where the
1099 reg went on the stack.) */
1100 if (!REG_P (sub) && (reload_completed || !MEM_P (sub)))
1101 return 0;
1103 else if (!REG_P (op))
1104 return 0;
1105 return general_operand (op, mode);
1108 /* Return 1 for a register in Pmode; ignore the tested mode. */
1111 pmode_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
1113 return register_operand (op, Pmode);
1116 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1117 or a hard register. */
1120 scratch_operand (rtx op, machine_mode mode)
1122 if (GET_MODE (op) != mode && mode != VOIDmode)
1123 return 0;
1125 return (GET_CODE (op) == SCRATCH
1126 || (REG_P (op)
1127 && (lra_in_progress
1128 || (REGNO (op) < FIRST_PSEUDO_REGISTER
1129 && REGNO_REG_CLASS (REGNO (op)) != NO_REGS))));
1132 /* Return 1 if OP is a valid immediate operand for mode MODE.
1134 The main use of this function is as a predicate in match_operand
1135 expressions in the machine description. */
1138 immediate_operand (rtx op, machine_mode mode)
1140 /* Don't accept CONST_INT or anything similar
1141 if the caller wants something floating. */
1142 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1143 && GET_MODE_CLASS (mode) != MODE_INT
1144 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1145 return 0;
1147 if (CONST_INT_P (op)
1148 && mode != VOIDmode
1149 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1150 return 0;
1152 return (CONSTANT_P (op)
1153 && (GET_MODE (op) == mode || mode == VOIDmode
1154 || GET_MODE (op) == VOIDmode)
1155 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1156 && targetm.legitimate_constant_p (mode == VOIDmode
1157 ? GET_MODE (op)
1158 : mode, op));
1161 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1164 const_int_operand (rtx op, machine_mode mode)
1166 if (!CONST_INT_P (op))
1167 return 0;
1169 if (mode != VOIDmode
1170 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1171 return 0;
1173 return 1;
1176 #if TARGET_SUPPORTS_WIDE_INT
1177 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1178 of mode MODE. */
1180 const_scalar_int_operand (rtx op, machine_mode mode)
1182 if (!CONST_SCALAR_INT_P (op))
1183 return 0;
1185 if (CONST_INT_P (op))
1186 return const_int_operand (op, mode);
1188 if (mode != VOIDmode)
1190 int prec = GET_MODE_PRECISION (mode);
1191 int bitsize = GET_MODE_BITSIZE (mode);
1193 if (CONST_WIDE_INT_NUNITS (op) * HOST_BITS_PER_WIDE_INT > bitsize)
1194 return 0;
1196 if (prec == bitsize)
1197 return 1;
1198 else
1200 /* Multiword partial int. */
1201 HOST_WIDE_INT x
1202 = CONST_WIDE_INT_ELT (op, CONST_WIDE_INT_NUNITS (op) - 1);
1203 return (sext_hwi (x, prec & (HOST_BITS_PER_WIDE_INT - 1)) == x);
1206 return 1;
1209 /* Returns 1 if OP is an operand that is a constant integer or constant
1210 floating-point number of MODE. */
1213 const_double_operand (rtx op, machine_mode mode)
1215 return (GET_CODE (op) == CONST_DOUBLE)
1216 && (GET_MODE (op) == mode || mode == VOIDmode);
1218 #else
1219 /* Returns 1 if OP is an operand that is a constant integer or constant
1220 floating-point number of MODE. */
1223 const_double_operand (rtx op, machine_mode mode)
1225 /* Don't accept CONST_INT or anything similar
1226 if the caller wants something floating. */
1227 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1228 && GET_MODE_CLASS (mode) != MODE_INT
1229 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1230 return 0;
1232 return ((CONST_DOUBLE_P (op) || CONST_INT_P (op))
1233 && (mode == VOIDmode || GET_MODE (op) == mode
1234 || GET_MODE (op) == VOIDmode));
1236 #endif
1237 /* Return 1 if OP is a general operand that is not an immediate
1238 operand of mode MODE. */
1241 nonimmediate_operand (rtx op, machine_mode mode)
1243 return (general_operand (op, mode) && ! CONSTANT_P (op));
1246 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1249 nonmemory_operand (rtx op, machine_mode mode)
1251 if (CONSTANT_P (op))
1252 return immediate_operand (op, mode);
1253 return register_operand (op, mode);
1256 /* Return 1 if OP is a valid operand that stands for pushing a
1257 value of mode MODE onto the stack.
1259 The main use of this function is as a predicate in match_operand
1260 expressions in the machine description. */
1263 push_operand (rtx op, machine_mode mode)
1265 unsigned int rounded_size = GET_MODE_SIZE (mode);
1267 #ifdef PUSH_ROUNDING
1268 rounded_size = PUSH_ROUNDING (rounded_size);
1269 #endif
1271 if (!MEM_P (op))
1272 return 0;
1274 if (mode != VOIDmode && GET_MODE (op) != mode)
1275 return 0;
1277 op = XEXP (op, 0);
1279 if (rounded_size == GET_MODE_SIZE (mode))
1281 if (GET_CODE (op) != STACK_PUSH_CODE)
1282 return 0;
1284 else
1286 if (GET_CODE (op) != PRE_MODIFY
1287 || GET_CODE (XEXP (op, 1)) != PLUS
1288 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1289 || !CONST_INT_P (XEXP (XEXP (op, 1), 1))
1290 || INTVAL (XEXP (XEXP (op, 1), 1))
1291 != ((STACK_GROWS_DOWNWARD ? -1 : 1) * (int) rounded_size))
1292 return 0;
1295 return XEXP (op, 0) == stack_pointer_rtx;
1298 /* Return 1 if OP is a valid operand that stands for popping a
1299 value of mode MODE off the stack.
1301 The main use of this function is as a predicate in match_operand
1302 expressions in the machine description. */
1305 pop_operand (rtx op, machine_mode mode)
1307 if (!MEM_P (op))
1308 return 0;
1310 if (mode != VOIDmode && GET_MODE (op) != mode)
1311 return 0;
1313 op = XEXP (op, 0);
1315 if (GET_CODE (op) != STACK_POP_CODE)
1316 return 0;
1318 return XEXP (op, 0) == stack_pointer_rtx;
1321 /* Return 1 if ADDR is a valid memory address
1322 for mode MODE in address space AS. */
1325 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED,
1326 rtx addr, addr_space_t as)
1328 #ifdef GO_IF_LEGITIMATE_ADDRESS
1329 gcc_assert (ADDR_SPACE_GENERIC_P (as));
1330 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1331 return 0;
1333 win:
1334 return 1;
1335 #else
1336 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
1337 #endif
1340 /* Return 1 if OP is a valid memory reference with mode MODE,
1341 including a valid address.
1343 The main use of this function is as a predicate in match_operand
1344 expressions in the machine description. */
1347 memory_operand (rtx op, machine_mode mode)
1349 rtx inner;
1351 if (! reload_completed)
1352 /* Note that no SUBREG is a memory operand before end of reload pass,
1353 because (SUBREG (MEM...)) forces reloading into a register. */
1354 return MEM_P (op) && general_operand (op, mode);
1356 if (mode != VOIDmode && GET_MODE (op) != mode)
1357 return 0;
1359 inner = op;
1360 if (GET_CODE (inner) == SUBREG)
1361 inner = SUBREG_REG (inner);
1363 return (MEM_P (inner) && general_operand (op, mode));
1366 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1367 that is, a memory reference whose address is a general_operand. */
1370 indirect_operand (rtx op, machine_mode mode)
1372 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1373 if (! reload_completed
1374 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
1376 int offset = SUBREG_BYTE (op);
1377 rtx inner = SUBREG_REG (op);
1379 if (mode != VOIDmode && GET_MODE (op) != mode)
1380 return 0;
1382 /* The only way that we can have a general_operand as the resulting
1383 address is if OFFSET is zero and the address already is an operand
1384 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1385 operand. */
1387 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1388 || (GET_CODE (XEXP (inner, 0)) == PLUS
1389 && CONST_INT_P (XEXP (XEXP (inner, 0), 1))
1390 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1391 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1394 return (MEM_P (op)
1395 && memory_operand (op, mode)
1396 && general_operand (XEXP (op, 0), Pmode));
1399 /* Return 1 if this is an ordered comparison operator (not including
1400 ORDERED and UNORDERED). */
1403 ordered_comparison_operator (rtx op, machine_mode mode)
1405 if (mode != VOIDmode && GET_MODE (op) != mode)
1406 return false;
1407 switch (GET_CODE (op))
1409 case EQ:
1410 case NE:
1411 case LT:
1412 case LTU:
1413 case LE:
1414 case LEU:
1415 case GT:
1416 case GTU:
1417 case GE:
1418 case GEU:
1419 return true;
1420 default:
1421 return false;
1425 /* Return 1 if this is a comparison operator. This allows the use of
1426 MATCH_OPERATOR to recognize all the branch insns. */
1429 comparison_operator (rtx op, machine_mode mode)
1431 return ((mode == VOIDmode || GET_MODE (op) == mode)
1432 && COMPARISON_P (op));
1435 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1438 extract_asm_operands (rtx body)
1440 rtx tmp;
1441 switch (GET_CODE (body))
1443 case ASM_OPERANDS:
1444 return body;
1446 case SET:
1447 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1448 tmp = SET_SRC (body);
1449 if (GET_CODE (tmp) == ASM_OPERANDS)
1450 return tmp;
1451 break;
1453 case PARALLEL:
1454 tmp = XVECEXP (body, 0, 0);
1455 if (GET_CODE (tmp) == ASM_OPERANDS)
1456 return tmp;
1457 if (GET_CODE (tmp) == SET)
1459 tmp = SET_SRC (tmp);
1460 if (GET_CODE (tmp) == ASM_OPERANDS)
1461 return tmp;
1463 break;
1465 default:
1466 break;
1468 return NULL;
1471 /* If BODY is an insn body that uses ASM_OPERANDS,
1472 return the number of operands (both input and output) in the insn.
1473 Otherwise return -1. */
1476 asm_noperands (const_rtx body)
1478 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body));
1479 int n_sets = 0;
1481 if (asm_op == NULL)
1482 return -1;
1484 if (GET_CODE (body) == SET)
1485 n_sets = 1;
1486 else if (GET_CODE (body) == PARALLEL)
1488 int i;
1489 if (GET_CODE (XVECEXP (body, 0, 0)) == SET)
1491 /* Multiple output operands, or 1 output plus some clobbers:
1492 body is
1493 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1494 /* Count backwards through CLOBBERs to determine number of SETs. */
1495 for (i = XVECLEN (body, 0); i > 0; i--)
1497 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1498 break;
1499 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1500 return -1;
1503 /* N_SETS is now number of output operands. */
1504 n_sets = i;
1506 /* Verify that all the SETs we have
1507 came from a single original asm_operands insn
1508 (so that invalid combinations are blocked). */
1509 for (i = 0; i < n_sets; i++)
1511 rtx elt = XVECEXP (body, 0, i);
1512 if (GET_CODE (elt) != SET)
1513 return -1;
1514 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1515 return -1;
1516 /* If these ASM_OPERANDS rtx's came from different original insns
1517 then they aren't allowed together. */
1518 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1519 != ASM_OPERANDS_INPUT_VEC (asm_op))
1520 return -1;
1523 else
1525 /* 0 outputs, but some clobbers:
1526 body is [(asm_operands ...) (clobber (reg ...))...]. */
1527 /* Make sure all the other parallel things really are clobbers. */
1528 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1529 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1530 return -1;
1534 return (ASM_OPERANDS_INPUT_LENGTH (asm_op)
1535 + ASM_OPERANDS_LABEL_LENGTH (asm_op) + n_sets);
1538 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1539 copy its operands (both input and output) into the vector OPERANDS,
1540 the locations of the operands within the insn into the vector OPERAND_LOCS,
1541 and the constraints for the operands into CONSTRAINTS.
1542 Write the modes of the operands into MODES.
1543 Return the assembler-template.
1545 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1546 we don't store that info. */
1548 const char *
1549 decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
1550 const char **constraints, machine_mode *modes,
1551 location_t *loc)
1553 int nbase = 0, n, i;
1554 rtx asmop;
1556 switch (GET_CODE (body))
1558 case ASM_OPERANDS:
1559 /* Zero output asm: BODY is (asm_operands ...). */
1560 asmop = body;
1561 break;
1563 case SET:
1564 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1565 asmop = SET_SRC (body);
1567 /* The output is in the SET.
1568 Its constraint is in the ASM_OPERANDS itself. */
1569 if (operands)
1570 operands[0] = SET_DEST (body);
1571 if (operand_locs)
1572 operand_locs[0] = &SET_DEST (body);
1573 if (constraints)
1574 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1575 if (modes)
1576 modes[0] = GET_MODE (SET_DEST (body));
1577 nbase = 1;
1578 break;
1580 case PARALLEL:
1582 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1584 asmop = XVECEXP (body, 0, 0);
1585 if (GET_CODE (asmop) == SET)
1587 asmop = SET_SRC (asmop);
1589 /* At least one output, plus some CLOBBERs. The outputs are in
1590 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1591 for (i = 0; i < nparallel; i++)
1593 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1594 break; /* Past last SET */
1595 if (operands)
1596 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1597 if (operand_locs)
1598 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1599 if (constraints)
1600 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1601 if (modes)
1602 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1604 nbase = i;
1606 break;
1609 default:
1610 gcc_unreachable ();
1613 n = ASM_OPERANDS_INPUT_LENGTH (asmop);
1614 for (i = 0; i < n; i++)
1616 if (operand_locs)
1617 operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i);
1618 if (operands)
1619 operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i);
1620 if (constraints)
1621 constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1622 if (modes)
1623 modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1625 nbase += n;
1627 n = ASM_OPERANDS_LABEL_LENGTH (asmop);
1628 for (i = 0; i < n; i++)
1630 if (operand_locs)
1631 operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i);
1632 if (operands)
1633 operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i);
1634 if (constraints)
1635 constraints[nbase + i] = "";
1636 if (modes)
1637 modes[nbase + i] = Pmode;
1640 if (loc)
1641 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop);
1643 return ASM_OPERANDS_TEMPLATE (asmop);
1646 /* Parse inline assembly string STRING and determine which operands are
1647 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1648 to true if operand I is referenced.
1650 This is intended to distinguish barrier-like asms such as:
1652 asm ("" : "=m" (...));
1654 from real references such as:
1656 asm ("sw\t$0, %0" : "=m" (...)); */
1658 void
1659 get_referenced_operands (const char *string, bool *used,
1660 unsigned int noperands)
1662 memset (used, 0, sizeof (bool) * noperands);
1663 const char *p = string;
1664 while (*p)
1665 switch (*p)
1667 case '%':
1668 p += 1;
1669 /* A letter followed by a digit indicates an operand number. */
1670 if (ISALPHA (p[0]) && ISDIGIT (p[1]))
1671 p += 1;
1672 if (ISDIGIT (*p))
1674 char *endptr;
1675 unsigned long opnum = strtoul (p, &endptr, 10);
1676 if (endptr != p && opnum < noperands)
1677 used[opnum] = true;
1678 p = endptr;
1680 else
1681 p += 1;
1682 break;
1684 default:
1685 p++;
1686 break;
1690 /* Check if an asm_operand matches its constraints.
1691 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1694 asm_operand_ok (rtx op, const char *constraint, const char **constraints)
1696 int result = 0;
1697 bool incdec_ok = false;
1699 /* Use constrain_operands after reload. */
1700 gcc_assert (!reload_completed);
1702 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1703 many alternatives as required to match the other operands. */
1704 if (*constraint == '\0')
1705 result = 1;
1707 while (*constraint)
1709 enum constraint_num cn;
1710 char c = *constraint;
1711 int len;
1712 switch (c)
1714 case ',':
1715 constraint++;
1716 continue;
1718 case '0': case '1': case '2': case '3': case '4':
1719 case '5': case '6': case '7': case '8': case '9':
1720 /* If caller provided constraints pointer, look up
1721 the matching constraint. Otherwise, our caller should have
1722 given us the proper matching constraint, but we can't
1723 actually fail the check if they didn't. Indicate that
1724 results are inconclusive. */
1725 if (constraints)
1727 char *end;
1728 unsigned long match;
1730 match = strtoul (constraint, &end, 10);
1731 if (!result)
1732 result = asm_operand_ok (op, constraints[match], NULL);
1733 constraint = (const char *) end;
1735 else
1738 constraint++;
1739 while (ISDIGIT (*constraint));
1740 if (! result)
1741 result = -1;
1743 continue;
1745 /* The rest of the compiler assumes that reloading the address
1746 of a MEM into a register will make it fit an 'o' constraint.
1747 That is, if it sees a MEM operand for an 'o' constraint,
1748 it assumes that (mem (base-reg)) will fit.
1750 That assumption fails on targets that don't have offsettable
1751 addresses at all. We therefore need to treat 'o' asm
1752 constraints as a special case and only accept operands that
1753 are already offsettable, thus proving that at least one
1754 offsettable address exists. */
1755 case 'o': /* offsettable */
1756 if (offsettable_nonstrict_memref_p (op))
1757 result = 1;
1758 break;
1760 case 'g':
1761 if (general_operand (op, VOIDmode))
1762 result = 1;
1763 break;
1765 case '<':
1766 case '>':
1767 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1768 to exist, excepting those that expand_call created. Further,
1769 on some machines which do not have generalized auto inc/dec,
1770 an inc/dec is not a memory_operand.
1772 Match any memory and hope things are resolved after reload. */
1773 incdec_ok = true;
1774 default:
1775 cn = lookup_constraint (constraint);
1776 switch (get_constraint_type (cn))
1778 case CT_REGISTER:
1779 if (!result
1780 && reg_class_for_constraint (cn) != NO_REGS
1781 && GET_MODE (op) != BLKmode
1782 && register_operand (op, VOIDmode))
1783 result = 1;
1784 break;
1786 case CT_CONST_INT:
1787 if (!result
1788 && CONST_INT_P (op)
1789 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
1790 result = 1;
1791 break;
1793 case CT_MEMORY:
1794 /* Every memory operand can be reloaded to fit. */
1795 result = result || memory_operand (op, VOIDmode);
1796 break;
1798 case CT_ADDRESS:
1799 /* Every address operand can be reloaded to fit. */
1800 result = result || address_operand (op, VOIDmode);
1801 break;
1803 case CT_FIXED_FORM:
1804 result = result || constraint_satisfied_p (op, cn);
1805 break;
1807 break;
1809 len = CONSTRAINT_LEN (c, constraint);
1811 constraint++;
1812 while (--len && *constraint);
1813 if (len)
1814 return 0;
1817 /* For operands without < or > constraints reject side-effects. */
1818 if (AUTO_INC_DEC && !incdec_ok && result && MEM_P (op))
1819 switch (GET_CODE (XEXP (op, 0)))
1821 case PRE_INC:
1822 case POST_INC:
1823 case PRE_DEC:
1824 case POST_DEC:
1825 case PRE_MODIFY:
1826 case POST_MODIFY:
1827 return 0;
1828 default:
1829 break;
1832 return result;
1835 /* Given an rtx *P, if it is a sum containing an integer constant term,
1836 return the location (type rtx *) of the pointer to that constant term.
1837 Otherwise, return a null pointer. */
1839 rtx *
1840 find_constant_term_loc (rtx *p)
1842 rtx *tem;
1843 enum rtx_code code = GET_CODE (*p);
1845 /* If *P IS such a constant term, P is its location. */
1847 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1848 || code == CONST)
1849 return p;
1851 /* Otherwise, if not a sum, it has no constant term. */
1853 if (GET_CODE (*p) != PLUS)
1854 return 0;
1856 /* If one of the summands is constant, return its location. */
1858 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1859 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1860 return p;
1862 /* Otherwise, check each summand for containing a constant term. */
1864 if (XEXP (*p, 0) != 0)
1866 tem = find_constant_term_loc (&XEXP (*p, 0));
1867 if (tem != 0)
1868 return tem;
1871 if (XEXP (*p, 1) != 0)
1873 tem = find_constant_term_loc (&XEXP (*p, 1));
1874 if (tem != 0)
1875 return tem;
1878 return 0;
1881 /* Return 1 if OP is a memory reference
1882 whose address contains no side effects
1883 and remains valid after the addition
1884 of a positive integer less than the
1885 size of the object being referenced.
1887 We assume that the original address is valid and do not check it.
1889 This uses strict_memory_address_p as a subroutine, so
1890 don't use it before reload. */
1893 offsettable_memref_p (rtx op)
1895 return ((MEM_P (op))
1896 && offsettable_address_addr_space_p (1, GET_MODE (op), XEXP (op, 0),
1897 MEM_ADDR_SPACE (op)));
1900 /* Similar, but don't require a strictly valid mem ref:
1901 consider pseudo-regs valid as index or base regs. */
1904 offsettable_nonstrict_memref_p (rtx op)
1906 return ((MEM_P (op))
1907 && offsettable_address_addr_space_p (0, GET_MODE (op), XEXP (op, 0),
1908 MEM_ADDR_SPACE (op)));
1911 /* Return 1 if Y is a memory address which contains no side effects
1912 and would remain valid for address space AS after the addition of
1913 a positive integer less than the size of that mode.
1915 We assume that the original address is valid and do not check it.
1916 We do check that it is valid for narrower modes.
1918 If STRICTP is nonzero, we require a strictly valid address,
1919 for the sake of use in reload.c. */
1922 offsettable_address_addr_space_p (int strictp, machine_mode mode, rtx y,
1923 addr_space_t as)
1925 enum rtx_code ycode = GET_CODE (y);
1926 rtx z;
1927 rtx y1 = y;
1928 rtx *y2;
1929 int (*addressp) (machine_mode, rtx, addr_space_t) =
1930 (strictp ? strict_memory_address_addr_space_p
1931 : memory_address_addr_space_p);
1932 unsigned int mode_sz = GET_MODE_SIZE (mode);
1934 if (CONSTANT_ADDRESS_P (y))
1935 return 1;
1937 /* Adjusting an offsettable address involves changing to a narrower mode.
1938 Make sure that's OK. */
1940 if (mode_dependent_address_p (y, as))
1941 return 0;
1943 machine_mode address_mode = GET_MODE (y);
1944 if (address_mode == VOIDmode)
1945 address_mode = targetm.addr_space.address_mode (as);
1946 #ifdef POINTERS_EXTEND_UNSIGNED
1947 machine_mode pointer_mode = targetm.addr_space.pointer_mode (as);
1948 #endif
1950 /* ??? How much offset does an offsettable BLKmode reference need?
1951 Clearly that depends on the situation in which it's being used.
1952 However, the current situation in which we test 0xffffffff is
1953 less than ideal. Caveat user. */
1954 if (mode_sz == 0)
1955 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1957 /* If the expression contains a constant term,
1958 see if it remains valid when max possible offset is added. */
1960 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1962 int good;
1964 y1 = *y2;
1965 *y2 = plus_constant (address_mode, *y2, mode_sz - 1);
1966 /* Use QImode because an odd displacement may be automatically invalid
1967 for any wider mode. But it should be valid for a single byte. */
1968 good = (*addressp) (QImode, y, as);
1970 /* In any case, restore old contents of memory. */
1971 *y2 = y1;
1972 return good;
1975 if (GET_RTX_CLASS (ycode) == RTX_AUTOINC)
1976 return 0;
1978 /* The offset added here is chosen as the maximum offset that
1979 any instruction could need to add when operating on something
1980 of the specified mode. We assume that if Y and Y+c are
1981 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1982 go inside a LO_SUM here, so we do so as well. */
1983 if (GET_CODE (y) == LO_SUM
1984 && mode != BLKmode
1985 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
1986 z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0),
1987 plus_constant (address_mode, XEXP (y, 1),
1988 mode_sz - 1));
1989 #ifdef POINTERS_EXTEND_UNSIGNED
1990 /* Likewise for a ZERO_EXTEND from pointer_mode. */
1991 else if (POINTERS_EXTEND_UNSIGNED > 0
1992 && GET_CODE (y) == ZERO_EXTEND
1993 && GET_MODE (XEXP (y, 0)) == pointer_mode)
1994 z = gen_rtx_ZERO_EXTEND (address_mode,
1995 plus_constant (pointer_mode, XEXP (y, 0),
1996 mode_sz - 1));
1997 #endif
1998 else
1999 z = plus_constant (address_mode, y, mode_sz - 1);
2001 /* Use QImode because an odd displacement may be automatically invalid
2002 for any wider mode. But it should be valid for a single byte. */
2003 return (*addressp) (QImode, z, as);
2006 /* Return 1 if ADDR is an address-expression whose effect depends
2007 on the mode of the memory reference it is used in.
2009 ADDRSPACE is the address space associated with the address.
2011 Autoincrement addressing is a typical example of mode-dependence
2012 because the amount of the increment depends on the mode. */
2014 bool
2015 mode_dependent_address_p (rtx addr, addr_space_t addrspace)
2017 /* Auto-increment addressing with anything other than post_modify
2018 or pre_modify always introduces a mode dependency. Catch such
2019 cases now instead of deferring to the target. */
2020 if (GET_CODE (addr) == PRE_INC
2021 || GET_CODE (addr) == POST_INC
2022 || GET_CODE (addr) == PRE_DEC
2023 || GET_CODE (addr) == POST_DEC)
2024 return true;
2026 return targetm.mode_dependent_address_p (addr, addrspace);
2029 /* Return true if boolean attribute ATTR is supported. */
2031 static bool
2032 have_bool_attr (bool_attr attr)
2034 switch (attr)
2036 case BA_ENABLED:
2037 return HAVE_ATTR_enabled;
2038 case BA_PREFERRED_FOR_SIZE:
2039 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_size;
2040 case BA_PREFERRED_FOR_SPEED:
2041 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_speed;
2043 gcc_unreachable ();
2046 /* Return the value of ATTR for instruction INSN. */
2048 static bool
2049 get_bool_attr (rtx_insn *insn, bool_attr attr)
2051 switch (attr)
2053 case BA_ENABLED:
2054 return get_attr_enabled (insn);
2055 case BA_PREFERRED_FOR_SIZE:
2056 return get_attr_enabled (insn) && get_attr_preferred_for_size (insn);
2057 case BA_PREFERRED_FOR_SPEED:
2058 return get_attr_enabled (insn) && get_attr_preferred_for_speed (insn);
2060 gcc_unreachable ();
2063 /* Like get_bool_attr_mask, but don't use the cache. */
2065 static alternative_mask
2066 get_bool_attr_mask_uncached (rtx_insn *insn, bool_attr attr)
2068 /* Temporarily install enough information for get_attr_<foo> to assume
2069 that the insn operands are already cached. As above, the attribute
2070 mustn't depend on the values of operands, so we don't provide their
2071 real values here. */
2072 rtx_insn *old_insn = recog_data.insn;
2073 int old_alternative = which_alternative;
2075 recog_data.insn = insn;
2076 alternative_mask mask = ALL_ALTERNATIVES;
2077 int n_alternatives = insn_data[INSN_CODE (insn)].n_alternatives;
2078 for (int i = 0; i < n_alternatives; i++)
2080 which_alternative = i;
2081 if (!get_bool_attr (insn, attr))
2082 mask &= ~ALTERNATIVE_BIT (i);
2085 recog_data.insn = old_insn;
2086 which_alternative = old_alternative;
2087 return mask;
2090 /* Return the mask of operand alternatives that are allowed for INSN
2091 by boolean attribute ATTR. This mask depends only on INSN and on
2092 the current target; it does not depend on things like the values of
2093 operands. */
2095 static alternative_mask
2096 get_bool_attr_mask (rtx_insn *insn, bool_attr attr)
2098 /* Quick exit for asms and for targets that don't use these attributes. */
2099 int code = INSN_CODE (insn);
2100 if (code < 0 || !have_bool_attr (attr))
2101 return ALL_ALTERNATIVES;
2103 /* Calling get_attr_<foo> can be expensive, so cache the mask
2104 for speed. */
2105 if (!this_target_recog->x_bool_attr_masks[code][attr])
2106 this_target_recog->x_bool_attr_masks[code][attr]
2107 = get_bool_attr_mask_uncached (insn, attr);
2108 return this_target_recog->x_bool_attr_masks[code][attr];
2111 /* Return the set of alternatives of INSN that are allowed by the current
2112 target. */
2114 alternative_mask
2115 get_enabled_alternatives (rtx_insn *insn)
2117 return get_bool_attr_mask (insn, BA_ENABLED);
2120 /* Return the set of alternatives of INSN that are allowed by the current
2121 target and are preferred for the current size/speed optimization
2122 choice. */
2124 alternative_mask
2125 get_preferred_alternatives (rtx_insn *insn)
2127 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
2128 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2129 else
2130 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2133 /* Return the set of alternatives of INSN that are allowed by the current
2134 target and are preferred for the size/speed optimization choice
2135 associated with BB. Passing a separate BB is useful if INSN has not
2136 been emitted yet or if we are considering moving it to a different
2137 block. */
2139 alternative_mask
2140 get_preferred_alternatives (rtx_insn *insn, basic_block bb)
2142 if (optimize_bb_for_speed_p (bb))
2143 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2144 else
2145 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2148 /* Assert that the cached boolean attributes for INSN are still accurate.
2149 The backend is required to define these attributes in a way that only
2150 depends on the current target (rather than operands, compiler phase,
2151 etc.). */
2153 bool
2154 check_bool_attrs (rtx_insn *insn)
2156 int code = INSN_CODE (insn);
2157 if (code >= 0)
2158 for (int i = 0; i <= BA_LAST; ++i)
2160 enum bool_attr attr = (enum bool_attr) i;
2161 if (this_target_recog->x_bool_attr_masks[code][attr])
2162 gcc_assert (this_target_recog->x_bool_attr_masks[code][attr]
2163 == get_bool_attr_mask_uncached (insn, attr));
2165 return true;
2168 /* Like extract_insn, but save insn extracted and don't extract again, when
2169 called again for the same insn expecting that recog_data still contain the
2170 valid information. This is used primary by gen_attr infrastructure that
2171 often does extract insn again and again. */
2172 void
2173 extract_insn_cached (rtx_insn *insn)
2175 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2176 return;
2177 extract_insn (insn);
2178 recog_data.insn = insn;
2181 /* Do uncached extract_insn, constrain_operands and complain about failures.
2182 This should be used when extracting a pre-existing constrained instruction
2183 if the caller wants to know which alternative was chosen. */
2184 void
2185 extract_constrain_insn (rtx_insn *insn)
2187 extract_insn (insn);
2188 if (!constrain_operands (reload_completed, get_enabled_alternatives (insn)))
2189 fatal_insn_not_found (insn);
2192 /* Do cached extract_insn, constrain_operands and complain about failures.
2193 Used by insn_attrtab. */
2194 void
2195 extract_constrain_insn_cached (rtx_insn *insn)
2197 extract_insn_cached (insn);
2198 if (which_alternative == -1
2199 && !constrain_operands (reload_completed,
2200 get_enabled_alternatives (insn)))
2201 fatal_insn_not_found (insn);
2204 /* Do cached constrain_operands on INSN and complain about failures. */
2206 constrain_operands_cached (rtx_insn *insn, int strict)
2208 if (which_alternative == -1)
2209 return constrain_operands (strict, get_enabled_alternatives (insn));
2210 else
2211 return 1;
2214 /* Analyze INSN and fill in recog_data. */
2216 void
2217 extract_insn (rtx_insn *insn)
2219 int i;
2220 int icode;
2221 int noperands;
2222 rtx body = PATTERN (insn);
2224 recog_data.n_operands = 0;
2225 recog_data.n_alternatives = 0;
2226 recog_data.n_dups = 0;
2227 recog_data.is_asm = false;
2229 switch (GET_CODE (body))
2231 case USE:
2232 case CLOBBER:
2233 case ASM_INPUT:
2234 case ADDR_VEC:
2235 case ADDR_DIFF_VEC:
2236 case VAR_LOCATION:
2237 return;
2239 case SET:
2240 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2241 goto asm_insn;
2242 else
2243 goto normal_insn;
2244 case PARALLEL:
2245 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2246 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2247 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
2248 goto asm_insn;
2249 else
2250 goto normal_insn;
2251 case ASM_OPERANDS:
2252 asm_insn:
2253 recog_data.n_operands = noperands = asm_noperands (body);
2254 if (noperands >= 0)
2256 /* This insn is an `asm' with operands. */
2258 /* expand_asm_operands makes sure there aren't too many operands. */
2259 gcc_assert (noperands <= MAX_RECOG_OPERANDS);
2261 /* Now get the operand values and constraints out of the insn. */
2262 decode_asm_operands (body, recog_data.operand,
2263 recog_data.operand_loc,
2264 recog_data.constraints,
2265 recog_data.operand_mode, NULL);
2266 memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
2267 if (noperands > 0)
2269 const char *p = recog_data.constraints[0];
2270 recog_data.n_alternatives = 1;
2271 while (*p)
2272 recog_data.n_alternatives += (*p++ == ',');
2274 recog_data.is_asm = true;
2275 break;
2277 fatal_insn_not_found (insn);
2279 default:
2280 normal_insn:
2281 /* Ordinary insn: recognize it, get the operands via insn_extract
2282 and get the constraints. */
2284 icode = recog_memoized (insn);
2285 if (icode < 0)
2286 fatal_insn_not_found (insn);
2288 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2289 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2290 recog_data.n_dups = insn_data[icode].n_dups;
2292 insn_extract (insn);
2294 for (i = 0; i < noperands; i++)
2296 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2297 recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
2298 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2299 /* VOIDmode match_operands gets mode from their real operand. */
2300 if (recog_data.operand_mode[i] == VOIDmode)
2301 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2304 for (i = 0; i < noperands; i++)
2305 recog_data.operand_type[i]
2306 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2307 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2308 : OP_IN);
2310 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES);
2312 recog_data.insn = NULL;
2313 which_alternative = -1;
2316 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2317 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2318 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2319 has N_OPERANDS entries. */
2321 void
2322 preprocess_constraints (int n_operands, int n_alternatives,
2323 const char **constraints,
2324 operand_alternative *op_alt_base)
2326 for (int i = 0; i < n_operands; i++)
2328 int j;
2329 struct operand_alternative *op_alt;
2330 const char *p = constraints[i];
2332 op_alt = op_alt_base;
2334 for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
2336 op_alt[i].cl = NO_REGS;
2337 op_alt[i].constraint = p;
2338 op_alt[i].matches = -1;
2339 op_alt[i].matched = -1;
2341 if (*p == '\0' || *p == ',')
2343 op_alt[i].anything_ok = 1;
2344 continue;
2347 for (;;)
2349 char c = *p;
2350 if (c == '#')
2352 c = *++p;
2353 while (c != ',' && c != '\0');
2354 if (c == ',' || c == '\0')
2356 p++;
2357 break;
2360 switch (c)
2362 case '?':
2363 op_alt[i].reject += 6;
2364 break;
2365 case '!':
2366 op_alt[i].reject += 600;
2367 break;
2368 case '&':
2369 op_alt[i].earlyclobber = 1;
2370 break;
2372 case '0': case '1': case '2': case '3': case '4':
2373 case '5': case '6': case '7': case '8': case '9':
2375 char *end;
2376 op_alt[i].matches = strtoul (p, &end, 10);
2377 op_alt[op_alt[i].matches].matched = i;
2378 p = end;
2380 continue;
2382 case 'X':
2383 op_alt[i].anything_ok = 1;
2384 break;
2386 case 'g':
2387 op_alt[i].cl =
2388 reg_class_subunion[(int) op_alt[i].cl][(int) GENERAL_REGS];
2389 break;
2391 default:
2392 enum constraint_num cn = lookup_constraint (p);
2393 enum reg_class cl;
2394 switch (get_constraint_type (cn))
2396 case CT_REGISTER:
2397 cl = reg_class_for_constraint (cn);
2398 if (cl != NO_REGS)
2399 op_alt[i].cl = reg_class_subunion[op_alt[i].cl][cl];
2400 break;
2402 case CT_CONST_INT:
2403 break;
2405 case CT_MEMORY:
2406 op_alt[i].memory_ok = 1;
2407 break;
2409 case CT_ADDRESS:
2410 op_alt[i].is_address = 1;
2411 op_alt[i].cl
2412 = (reg_class_subunion
2413 [(int) op_alt[i].cl]
2414 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2415 ADDRESS, SCRATCH)]);
2416 break;
2418 case CT_FIXED_FORM:
2419 break;
2421 break;
2423 p += CONSTRAINT_LEN (c, p);
2429 /* Return an array of operand_alternative instructions for
2430 instruction ICODE. */
2432 const operand_alternative *
2433 preprocess_insn_constraints (unsigned int icode)
2435 gcc_checking_assert (IN_RANGE (icode, 0, NUM_INSN_CODES - 1));
2436 if (this_target_recog->x_op_alt[icode])
2437 return this_target_recog->x_op_alt[icode];
2439 int n_operands = insn_data[icode].n_operands;
2440 if (n_operands == 0)
2441 return 0;
2442 /* Always provide at least one alternative so that which_op_alt ()
2443 works correctly. If the instruction has 0 alternatives (i.e. all
2444 constraint strings are empty) then each operand in this alternative
2445 will have anything_ok set. */
2446 int n_alternatives = MAX (insn_data[icode].n_alternatives, 1);
2447 int n_entries = n_operands * n_alternatives;
2449 operand_alternative *op_alt = XCNEWVEC (operand_alternative, n_entries);
2450 const char **constraints = XALLOCAVEC (const char *, n_operands);
2452 for (int i = 0; i < n_operands; ++i)
2453 constraints[i] = insn_data[icode].operand[i].constraint;
2454 preprocess_constraints (n_operands, n_alternatives, constraints, op_alt);
2456 this_target_recog->x_op_alt[icode] = op_alt;
2457 return op_alt;
2460 /* After calling extract_insn, you can use this function to extract some
2461 information from the constraint strings into a more usable form.
2462 The collected data is stored in recog_op_alt. */
2464 void
2465 preprocess_constraints (rtx_insn *insn)
2467 int icode = INSN_CODE (insn);
2468 if (icode >= 0)
2469 recog_op_alt = preprocess_insn_constraints (icode);
2470 else
2472 int n_operands = recog_data.n_operands;
2473 int n_alternatives = recog_data.n_alternatives;
2474 int n_entries = n_operands * n_alternatives;
2475 memset (asm_op_alt, 0, n_entries * sizeof (operand_alternative));
2476 preprocess_constraints (n_operands, n_alternatives,
2477 recog_data.constraints, asm_op_alt);
2478 recog_op_alt = asm_op_alt;
2482 /* Check the operands of an insn against the insn's operand constraints
2483 and return 1 if they match any of the alternatives in ALTERNATIVES.
2485 The information about the insn's operands, constraints, operand modes
2486 etc. is obtained from the global variables set up by extract_insn.
2488 WHICH_ALTERNATIVE is set to a number which indicates which
2489 alternative of constraints was matched: 0 for the first alternative,
2490 1 for the next, etc.
2492 In addition, when two operands are required to match
2493 and it happens that the output operand is (reg) while the
2494 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2495 make the output operand look like the input.
2496 This is because the output operand is the one the template will print.
2498 This is used in final, just before printing the assembler code and by
2499 the routines that determine an insn's attribute.
2501 If STRICT is a positive nonzero value, it means that we have been
2502 called after reload has been completed. In that case, we must
2503 do all checks strictly. If it is zero, it means that we have been called
2504 before reload has completed. In that case, we first try to see if we can
2505 find an alternative that matches strictly. If not, we try again, this
2506 time assuming that reload will fix up the insn. This provides a "best
2507 guess" for the alternative and is used to compute attributes of insns prior
2508 to reload. A negative value of STRICT is used for this internal call. */
2510 struct funny_match
2512 int this_op, other;
2516 constrain_operands (int strict, alternative_mask alternatives)
2518 const char *constraints[MAX_RECOG_OPERANDS];
2519 int matching_operands[MAX_RECOG_OPERANDS];
2520 int earlyclobber[MAX_RECOG_OPERANDS];
2521 int c;
2523 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2524 int funny_match_index;
2526 which_alternative = 0;
2527 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2528 return 1;
2530 for (c = 0; c < recog_data.n_operands; c++)
2532 constraints[c] = recog_data.constraints[c];
2533 matching_operands[c] = -1;
2538 int seen_earlyclobber_at = -1;
2539 int opno;
2540 int lose = 0;
2541 funny_match_index = 0;
2543 if (!TEST_BIT (alternatives, which_alternative))
2545 int i;
2547 for (i = 0; i < recog_data.n_operands; i++)
2548 constraints[i] = skip_alternative (constraints[i]);
2550 which_alternative++;
2551 continue;
2554 for (opno = 0; opno < recog_data.n_operands; opno++)
2556 rtx op = recog_data.operand[opno];
2557 machine_mode mode = GET_MODE (op);
2558 const char *p = constraints[opno];
2559 int offset = 0;
2560 int win = 0;
2561 int val;
2562 int len;
2564 earlyclobber[opno] = 0;
2566 /* A unary operator may be accepted by the predicate, but it
2567 is irrelevant for matching constraints. */
2568 if (UNARY_P (op))
2569 op = XEXP (op, 0);
2571 if (GET_CODE (op) == SUBREG)
2573 if (REG_P (SUBREG_REG (op))
2574 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2575 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
2576 GET_MODE (SUBREG_REG (op)),
2577 SUBREG_BYTE (op),
2578 GET_MODE (op));
2579 op = SUBREG_REG (op);
2582 /* An empty constraint or empty alternative
2583 allows anything which matched the pattern. */
2584 if (*p == 0 || *p == ',')
2585 win = 1;
2588 switch (c = *p, len = CONSTRAINT_LEN (c, p), c)
2590 case '\0':
2591 len = 0;
2592 break;
2593 case ',':
2594 c = '\0';
2595 break;
2597 case '#':
2598 /* Ignore rest of this alternative as far as
2599 constraint checking is concerned. */
2601 p++;
2602 while (*p && *p != ',');
2603 len = 0;
2604 break;
2606 case '&':
2607 earlyclobber[opno] = 1;
2608 if (seen_earlyclobber_at < 0)
2609 seen_earlyclobber_at = opno;
2610 break;
2612 case '0': case '1': case '2': case '3': case '4':
2613 case '5': case '6': case '7': case '8': case '9':
2615 /* This operand must be the same as a previous one.
2616 This kind of constraint is used for instructions such
2617 as add when they take only two operands.
2619 Note that the lower-numbered operand is passed first.
2621 If we are not testing strictly, assume that this
2622 constraint will be satisfied. */
2624 char *end;
2625 int match;
2627 match = strtoul (p, &end, 10);
2628 p = end;
2630 if (strict < 0)
2631 val = 1;
2632 else
2634 rtx op1 = recog_data.operand[match];
2635 rtx op2 = recog_data.operand[opno];
2637 /* A unary operator may be accepted by the predicate,
2638 but it is irrelevant for matching constraints. */
2639 if (UNARY_P (op1))
2640 op1 = XEXP (op1, 0);
2641 if (UNARY_P (op2))
2642 op2 = XEXP (op2, 0);
2644 val = operands_match_p (op1, op2);
2647 matching_operands[opno] = match;
2648 matching_operands[match] = opno;
2650 if (val != 0)
2651 win = 1;
2653 /* If output is *x and input is *--x, arrange later
2654 to change the output to *--x as well, since the
2655 output op is the one that will be printed. */
2656 if (val == 2 && strict > 0)
2658 funny_match[funny_match_index].this_op = opno;
2659 funny_match[funny_match_index++].other = match;
2662 len = 0;
2663 break;
2665 case 'p':
2666 /* p is used for address_operands. When we are called by
2667 gen_reload, no one will have checked that the address is
2668 strictly valid, i.e., that all pseudos requiring hard regs
2669 have gotten them. */
2670 if (strict <= 0
2671 || (strict_memory_address_p (recog_data.operand_mode[opno],
2672 op)))
2673 win = 1;
2674 break;
2676 /* No need to check general_operand again;
2677 it was done in insn-recog.c. Well, except that reload
2678 doesn't check the validity of its replacements, but
2679 that should only matter when there's a bug. */
2680 case 'g':
2681 /* Anything goes unless it is a REG and really has a hard reg
2682 but the hard reg is not in the class GENERAL_REGS. */
2683 if (REG_P (op))
2685 if (strict < 0
2686 || GENERAL_REGS == ALL_REGS
2687 || (reload_in_progress
2688 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2689 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2690 win = 1;
2692 else if (strict < 0 || general_operand (op, mode))
2693 win = 1;
2694 break;
2696 default:
2698 enum constraint_num cn = lookup_constraint (p);
2699 enum reg_class cl = reg_class_for_constraint (cn);
2700 if (cl != NO_REGS)
2702 if (strict < 0
2703 || (strict == 0
2704 && REG_P (op)
2705 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2706 || (strict == 0 && GET_CODE (op) == SCRATCH)
2707 || (REG_P (op)
2708 && reg_fits_class_p (op, cl, offset, mode)))
2709 win = 1;
2712 else if (constraint_satisfied_p (op, cn))
2713 win = 1;
2715 else if (insn_extra_memory_constraint (cn)
2716 /* Every memory operand can be reloaded to fit. */
2717 && ((strict < 0 && MEM_P (op))
2718 /* Before reload, accept what reload can turn
2719 into a mem. */
2720 || (strict < 0 && CONSTANT_P (op))
2721 /* Before reload, accept a pseudo,
2722 since LRA can turn it into a mem. */
2723 || (strict < 0 && targetm.lra_p () && REG_P (op)
2724 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2725 /* During reload, accept a pseudo */
2726 || (reload_in_progress && REG_P (op)
2727 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
2728 win = 1;
2729 else if (insn_extra_address_constraint (cn)
2730 /* Every address operand can be reloaded to fit. */
2731 && strict < 0)
2732 win = 1;
2733 /* Cater to architectures like IA-64 that define extra memory
2734 constraints without using define_memory_constraint. */
2735 else if (reload_in_progress
2736 && REG_P (op)
2737 && REGNO (op) >= FIRST_PSEUDO_REGISTER
2738 && reg_renumber[REGNO (op)] < 0
2739 && reg_equiv_mem (REGNO (op)) != 0
2740 && constraint_satisfied_p
2741 (reg_equiv_mem (REGNO (op)), cn))
2742 win = 1;
2743 break;
2746 while (p += len, c);
2748 constraints[opno] = p;
2749 /* If this operand did not win somehow,
2750 this alternative loses. */
2751 if (! win)
2752 lose = 1;
2754 /* This alternative won; the operands are ok.
2755 Change whichever operands this alternative says to change. */
2756 if (! lose)
2758 int opno, eopno;
2760 /* See if any earlyclobber operand conflicts with some other
2761 operand. */
2763 if (strict > 0 && seen_earlyclobber_at >= 0)
2764 for (eopno = seen_earlyclobber_at;
2765 eopno < recog_data.n_operands;
2766 eopno++)
2767 /* Ignore earlyclobber operands now in memory,
2768 because we would often report failure when we have
2769 two memory operands, one of which was formerly a REG. */
2770 if (earlyclobber[eopno]
2771 && REG_P (recog_data.operand[eopno]))
2772 for (opno = 0; opno < recog_data.n_operands; opno++)
2773 if ((MEM_P (recog_data.operand[opno])
2774 || recog_data.operand_type[opno] != OP_OUT)
2775 && opno != eopno
2776 /* Ignore things like match_operator operands. */
2777 && *recog_data.constraints[opno] != 0
2778 && ! (matching_operands[opno] == eopno
2779 && operands_match_p (recog_data.operand[opno],
2780 recog_data.operand[eopno]))
2781 && ! safe_from_earlyclobber (recog_data.operand[opno],
2782 recog_data.operand[eopno]))
2783 lose = 1;
2785 if (! lose)
2787 while (--funny_match_index >= 0)
2789 recog_data.operand[funny_match[funny_match_index].other]
2790 = recog_data.operand[funny_match[funny_match_index].this_op];
2793 /* For operands without < or > constraints reject side-effects. */
2794 if (AUTO_INC_DEC && recog_data.is_asm)
2796 for (opno = 0; opno < recog_data.n_operands; opno++)
2797 if (MEM_P (recog_data.operand[opno]))
2798 switch (GET_CODE (XEXP (recog_data.operand[opno], 0)))
2800 case PRE_INC:
2801 case POST_INC:
2802 case PRE_DEC:
2803 case POST_DEC:
2804 case PRE_MODIFY:
2805 case POST_MODIFY:
2806 if (strchr (recog_data.constraints[opno], '<') == NULL
2807 && strchr (recog_data.constraints[opno], '>')
2808 == NULL)
2809 return 0;
2810 break;
2811 default:
2812 break;
2816 return 1;
2820 which_alternative++;
2822 while (which_alternative < recog_data.n_alternatives);
2824 which_alternative = -1;
2825 /* If we are about to reject this, but we are not to test strictly,
2826 try a very loose test. Only return failure if it fails also. */
2827 if (strict == 0)
2828 return constrain_operands (-1, alternatives);
2829 else
2830 return 0;
2833 /* Return true iff OPERAND (assumed to be a REG rtx)
2834 is a hard reg in class CLASS when its regno is offset by OFFSET
2835 and changed to mode MODE.
2836 If REG occupies multiple hard regs, all of them must be in CLASS. */
2838 bool
2839 reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset,
2840 machine_mode mode)
2842 unsigned int regno = REGNO (operand);
2844 if (cl == NO_REGS)
2845 return false;
2847 /* Regno must not be a pseudo register. Offset may be negative. */
2848 return (HARD_REGISTER_NUM_P (regno)
2849 && HARD_REGISTER_NUM_P (regno + offset)
2850 && in_hard_reg_set_p (reg_class_contents[(int) cl], mode,
2851 regno + offset));
2854 /* Split single instruction. Helper function for split_all_insns and
2855 split_all_insns_noflow. Return last insn in the sequence if successful,
2856 or NULL if unsuccessful. */
2858 static rtx_insn *
2859 split_insn (rtx_insn *insn)
2861 /* Split insns here to get max fine-grain parallelism. */
2862 rtx_insn *first = PREV_INSN (insn);
2863 rtx_insn *last = try_split (PATTERN (insn), insn, 1);
2864 rtx insn_set, last_set, note;
2866 if (last == insn)
2867 return NULL;
2869 /* If the original instruction was a single set that was known to be
2870 equivalent to a constant, see if we can say the same about the last
2871 instruction in the split sequence. The two instructions must set
2872 the same destination. */
2873 insn_set = single_set (insn);
2874 if (insn_set)
2876 last_set = single_set (last);
2877 if (last_set && rtx_equal_p (SET_DEST (last_set), SET_DEST (insn_set)))
2879 note = find_reg_equal_equiv_note (insn);
2880 if (note && CONSTANT_P (XEXP (note, 0)))
2881 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0));
2882 else if (CONSTANT_P (SET_SRC (insn_set)))
2883 set_unique_reg_note (last, REG_EQUAL,
2884 copy_rtx (SET_SRC (insn_set)));
2888 /* try_split returns the NOTE that INSN became. */
2889 SET_INSN_DELETED (insn);
2891 /* ??? Coddle to md files that generate subregs in post-reload
2892 splitters instead of computing the proper hard register. */
2893 if (reload_completed && first != last)
2895 first = NEXT_INSN (first);
2896 for (;;)
2898 if (INSN_P (first))
2899 cleanup_subreg_operands (first);
2900 if (first == last)
2901 break;
2902 first = NEXT_INSN (first);
2906 return last;
2909 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2911 void
2912 split_all_insns (void)
2914 sbitmap blocks;
2915 bool changed;
2916 basic_block bb;
2918 blocks = sbitmap_alloc (last_basic_block_for_fn (cfun));
2919 bitmap_clear (blocks);
2920 changed = false;
2922 FOR_EACH_BB_REVERSE_FN (bb, cfun)
2924 rtx_insn *insn, *next;
2925 bool finish = false;
2927 rtl_profile_for_bb (bb);
2928 for (insn = BB_HEAD (bb); !finish ; insn = next)
2930 /* Can't use `next_real_insn' because that might go across
2931 CODE_LABELS and short-out basic blocks. */
2932 next = NEXT_INSN (insn);
2933 finish = (insn == BB_END (bb));
2934 if (INSN_P (insn))
2936 rtx set = single_set (insn);
2938 /* Don't split no-op move insns. These should silently
2939 disappear later in final. Splitting such insns would
2940 break the code that handles LIBCALL blocks. */
2941 if (set && set_noop_p (set))
2943 /* Nops get in the way while scheduling, so delete them
2944 now if register allocation has already been done. It
2945 is too risky to try to do this before register
2946 allocation, and there are unlikely to be very many
2947 nops then anyways. */
2948 if (reload_completed)
2949 delete_insn_and_edges (insn);
2951 else
2953 if (split_insn (insn))
2955 bitmap_set_bit (blocks, bb->index);
2956 changed = true;
2963 default_rtl_profile ();
2964 if (changed)
2965 find_many_sub_basic_blocks (blocks);
2967 checking_verify_flow_info ();
2969 sbitmap_free (blocks);
2972 /* Same as split_all_insns, but do not expect CFG to be available.
2973 Used by machine dependent reorg passes. */
2975 unsigned int
2976 split_all_insns_noflow (void)
2978 rtx_insn *next, *insn;
2980 for (insn = get_insns (); insn; insn = next)
2982 next = NEXT_INSN (insn);
2983 if (INSN_P (insn))
2985 /* Don't split no-op move insns. These should silently
2986 disappear later in final. Splitting such insns would
2987 break the code that handles LIBCALL blocks. */
2988 rtx set = single_set (insn);
2989 if (set && set_noop_p (set))
2991 /* Nops get in the way while scheduling, so delete them
2992 now if register allocation has already been done. It
2993 is too risky to try to do this before register
2994 allocation, and there are unlikely to be very many
2995 nops then anyways.
2997 ??? Should we use delete_insn when the CFG isn't valid? */
2998 if (reload_completed)
2999 delete_insn_and_edges (insn);
3001 else
3002 split_insn (insn);
3005 return 0;
3008 struct peep2_insn_data
3010 rtx_insn *insn;
3011 regset live_before;
3014 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
3015 static int peep2_current;
3017 static bool peep2_do_rebuild_jump_labels;
3018 static bool peep2_do_cleanup_cfg;
3020 /* The number of instructions available to match a peep2. */
3021 int peep2_current_count;
3023 /* A marker indicating the last insn of the block. The live_before regset
3024 for this element is correct, indicating DF_LIVE_OUT for the block. */
3025 #define PEEP2_EOB invalid_insn_rtx
3027 /* Wrap N to fit into the peep2_insn_data buffer. */
3029 static int
3030 peep2_buf_position (int n)
3032 if (n >= MAX_INSNS_PER_PEEP2 + 1)
3033 n -= MAX_INSNS_PER_PEEP2 + 1;
3034 return n;
3037 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3038 does not exist. Used by the recognizer to find the next insn to match
3039 in a multi-insn pattern. */
3041 rtx_insn *
3042 peep2_next_insn (int n)
3044 gcc_assert (n <= peep2_current_count);
3046 n = peep2_buf_position (peep2_current + n);
3048 return peep2_insn_data[n].insn;
3051 /* Return true if REGNO is dead before the Nth non-note insn
3052 after `current'. */
3055 peep2_regno_dead_p (int ofs, int regno)
3057 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3059 ofs = peep2_buf_position (peep2_current + ofs);
3061 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3063 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
3066 /* Similarly for a REG. */
3069 peep2_reg_dead_p (int ofs, rtx reg)
3071 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3073 ofs = peep2_buf_position (peep2_current + ofs);
3075 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3077 unsigned int end_regno = END_REGNO (reg);
3078 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno)
3079 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno))
3080 return 0;
3081 return 1;
3084 /* Regno offset to be used in the register search. */
3085 static int search_ofs;
3087 /* Try to find a hard register of mode MODE, matching the register class in
3088 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3089 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3090 in which case the only condition is that the register must be available
3091 before CURRENT_INSN.
3092 Registers that already have bits set in REG_SET will not be considered.
3094 If an appropriate register is available, it will be returned and the
3095 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3096 returned. */
3099 peep2_find_free_register (int from, int to, const char *class_str,
3100 machine_mode mode, HARD_REG_SET *reg_set)
3102 enum reg_class cl;
3103 HARD_REG_SET live;
3104 df_ref def;
3105 int i;
3107 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
3108 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
3110 from = peep2_buf_position (peep2_current + from);
3111 to = peep2_buf_position (peep2_current + to);
3113 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3114 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3116 while (from != to)
3118 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3120 /* Don't use registers set or clobbered by the insn. */
3121 FOR_EACH_INSN_DEF (def, peep2_insn_data[from].insn)
3122 SET_HARD_REG_BIT (live, DF_REF_REGNO (def));
3124 from = peep2_buf_position (from + 1);
3127 cl = reg_class_for_constraint (lookup_constraint (class_str));
3129 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3131 int raw_regno, regno, success, j;
3133 /* Distribute the free registers as much as possible. */
3134 raw_regno = search_ofs + i;
3135 if (raw_regno >= FIRST_PSEUDO_REGISTER)
3136 raw_regno -= FIRST_PSEUDO_REGISTER;
3137 #ifdef REG_ALLOC_ORDER
3138 regno = reg_alloc_order[raw_regno];
3139 #else
3140 regno = raw_regno;
3141 #endif
3143 /* Can it support the mode we need? */
3144 if (! HARD_REGNO_MODE_OK (regno, mode))
3145 continue;
3147 success = 1;
3148 for (j = 0; success && j < hard_regno_nregs[regno][mode]; j++)
3150 /* Don't allocate fixed registers. */
3151 if (fixed_regs[regno + j])
3153 success = 0;
3154 break;
3156 /* Don't allocate global registers. */
3157 if (global_regs[regno + j])
3159 success = 0;
3160 break;
3162 /* Make sure the register is of the right class. */
3163 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno + j))
3165 success = 0;
3166 break;
3168 /* And that we don't create an extra save/restore. */
3169 if (! call_used_regs[regno + j] && ! df_regs_ever_live_p (regno + j))
3171 success = 0;
3172 break;
3175 if (! targetm.hard_regno_scratch_ok (regno + j))
3177 success = 0;
3178 break;
3181 /* And we don't clobber traceback for noreturn functions. */
3182 if ((regno + j == FRAME_POINTER_REGNUM
3183 || regno + j == HARD_FRAME_POINTER_REGNUM)
3184 && (! reload_completed || frame_pointer_needed))
3186 success = 0;
3187 break;
3190 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3191 || TEST_HARD_REG_BIT (live, regno + j))
3193 success = 0;
3194 break;
3198 if (success)
3200 add_to_hard_reg_set (reg_set, mode, regno);
3202 /* Start the next search with the next register. */
3203 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
3204 raw_regno = 0;
3205 search_ofs = raw_regno;
3207 return gen_rtx_REG (mode, regno);
3211 search_ofs = 0;
3212 return NULL_RTX;
3215 /* Forget all currently tracked instructions, only remember current
3216 LIVE regset. */
3218 static void
3219 peep2_reinit_state (regset live)
3221 int i;
3223 /* Indicate that all slots except the last holds invalid data. */
3224 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3225 peep2_insn_data[i].insn = NULL;
3226 peep2_current_count = 0;
3228 /* Indicate that the last slot contains live_after data. */
3229 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3230 peep2_current = MAX_INSNS_PER_PEEP2;
3232 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3235 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3236 starting at INSN. Perform the replacement, removing the old insns and
3237 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3238 if the replacement is rejected. */
3240 static rtx_insn *
3241 peep2_attempt (basic_block bb, rtx_insn *insn, int match_len, rtx_insn *attempt)
3243 int i;
3244 rtx_insn *last, *before_try, *x;
3245 rtx eh_note, as_note;
3246 rtx_insn *old_insn;
3247 rtx_insn *new_insn;
3248 bool was_call = false;
3250 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3251 match more than one insn, or to be split into more than one insn. */
3252 old_insn = peep2_insn_data[peep2_current].insn;
3253 if (RTX_FRAME_RELATED_P (old_insn))
3255 bool any_note = false;
3256 rtx note;
3258 if (match_len != 0)
3259 return NULL;
3261 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3262 may be in the stream for the purpose of register allocation. */
3263 if (active_insn_p (attempt))
3264 new_insn = attempt;
3265 else
3266 new_insn = next_active_insn (attempt);
3267 if (next_active_insn (new_insn))
3268 return NULL;
3270 /* We have a 1-1 replacement. Copy over any frame-related info. */
3271 RTX_FRAME_RELATED_P (new_insn) = 1;
3273 /* Allow the backend to fill in a note during the split. */
3274 for (note = REG_NOTES (new_insn); note ; note = XEXP (note, 1))
3275 switch (REG_NOTE_KIND (note))
3277 case REG_FRAME_RELATED_EXPR:
3278 case REG_CFA_DEF_CFA:
3279 case REG_CFA_ADJUST_CFA:
3280 case REG_CFA_OFFSET:
3281 case REG_CFA_REGISTER:
3282 case REG_CFA_EXPRESSION:
3283 case REG_CFA_RESTORE:
3284 case REG_CFA_SET_VDRAP:
3285 any_note = true;
3286 break;
3287 default:
3288 break;
3291 /* If the backend didn't supply a note, copy one over. */
3292 if (!any_note)
3293 for (note = REG_NOTES (old_insn); note ; note = XEXP (note, 1))
3294 switch (REG_NOTE_KIND (note))
3296 case REG_FRAME_RELATED_EXPR:
3297 case REG_CFA_DEF_CFA:
3298 case REG_CFA_ADJUST_CFA:
3299 case REG_CFA_OFFSET:
3300 case REG_CFA_REGISTER:
3301 case REG_CFA_EXPRESSION:
3302 case REG_CFA_RESTORE:
3303 case REG_CFA_SET_VDRAP:
3304 add_reg_note (new_insn, REG_NOTE_KIND (note), XEXP (note, 0));
3305 any_note = true;
3306 break;
3307 default:
3308 break;
3311 /* If there still isn't a note, make sure the unwind info sees the
3312 same expression as before the split. */
3313 if (!any_note)
3315 rtx old_set, new_set;
3317 /* The old insn had better have been simple, or annotated. */
3318 old_set = single_set (old_insn);
3319 gcc_assert (old_set != NULL);
3321 new_set = single_set (new_insn);
3322 if (!new_set || !rtx_equal_p (new_set, old_set))
3323 add_reg_note (new_insn, REG_FRAME_RELATED_EXPR, old_set);
3326 /* Copy prologue/epilogue status. This is required in order to keep
3327 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3328 maybe_copy_prologue_epilogue_insn (old_insn, new_insn);
3331 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3332 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3333 cfg-related call notes. */
3334 for (i = 0; i <= match_len; ++i)
3336 int j;
3337 rtx note;
3339 j = peep2_buf_position (peep2_current + i);
3340 old_insn = peep2_insn_data[j].insn;
3341 if (!CALL_P (old_insn))
3342 continue;
3343 was_call = true;
3345 new_insn = attempt;
3346 while (new_insn != NULL_RTX)
3348 if (CALL_P (new_insn))
3349 break;
3350 new_insn = NEXT_INSN (new_insn);
3353 gcc_assert (new_insn != NULL_RTX);
3355 CALL_INSN_FUNCTION_USAGE (new_insn)
3356 = CALL_INSN_FUNCTION_USAGE (old_insn);
3357 SIBLING_CALL_P (new_insn) = SIBLING_CALL_P (old_insn);
3359 for (note = REG_NOTES (old_insn);
3360 note;
3361 note = XEXP (note, 1))
3362 switch (REG_NOTE_KIND (note))
3364 case REG_NORETURN:
3365 case REG_SETJMP:
3366 case REG_TM:
3367 add_reg_note (new_insn, REG_NOTE_KIND (note),
3368 XEXP (note, 0));
3369 break;
3370 default:
3371 /* Discard all other reg notes. */
3372 break;
3375 /* Croak if there is another call in the sequence. */
3376 while (++i <= match_len)
3378 j = peep2_buf_position (peep2_current + i);
3379 old_insn = peep2_insn_data[j].insn;
3380 gcc_assert (!CALL_P (old_insn));
3382 break;
3385 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3386 move those notes over to the new sequence. */
3387 as_note = NULL;
3388 for (i = match_len; i >= 0; --i)
3390 int j = peep2_buf_position (peep2_current + i);
3391 old_insn = peep2_insn_data[j].insn;
3393 as_note = find_reg_note (old_insn, REG_ARGS_SIZE, NULL);
3394 if (as_note)
3395 break;
3398 i = peep2_buf_position (peep2_current + match_len);
3399 eh_note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX);
3401 /* Replace the old sequence with the new. */
3402 rtx_insn *peepinsn = peep2_insn_data[i].insn;
3403 last = emit_insn_after_setloc (attempt,
3404 peep2_insn_data[i].insn,
3405 INSN_LOCATION (peepinsn));
3406 before_try = PREV_INSN (insn);
3407 delete_insn_chain (insn, peep2_insn_data[i].insn, false);
3409 /* Re-insert the EH_REGION notes. */
3410 if (eh_note || (was_call && nonlocal_goto_handler_labels))
3412 edge eh_edge;
3413 edge_iterator ei;
3415 FOR_EACH_EDGE (eh_edge, ei, bb->succs)
3416 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
3417 break;
3419 if (eh_note)
3420 copy_reg_eh_region_note_backward (eh_note, last, before_try);
3422 if (eh_edge)
3423 for (x = last; x != before_try; x = PREV_INSN (x))
3424 if (x != BB_END (bb)
3425 && (can_throw_internal (x)
3426 || can_nonlocal_goto (x)))
3428 edge nfte, nehe;
3429 int flags;
3431 nfte = split_block (bb, x);
3432 flags = (eh_edge->flags
3433 & (EDGE_EH | EDGE_ABNORMAL));
3434 if (CALL_P (x))
3435 flags |= EDGE_ABNORMAL_CALL;
3436 nehe = make_edge (nfte->src, eh_edge->dest,
3437 flags);
3439 nehe->probability = eh_edge->probability;
3440 nfte->probability
3441 = REG_BR_PROB_BASE - nehe->probability;
3443 peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3444 bb = nfte->src;
3445 eh_edge = nehe;
3448 /* Converting possibly trapping insn to non-trapping is
3449 possible. Zap dummy outgoing edges. */
3450 peep2_do_cleanup_cfg |= purge_dead_edges (bb);
3453 /* Re-insert the ARGS_SIZE notes. */
3454 if (as_note)
3455 fixup_args_size_notes (before_try, last, INTVAL (XEXP (as_note, 0)));
3457 /* If we generated a jump instruction, it won't have
3458 JUMP_LABEL set. Recompute after we're done. */
3459 for (x = last; x != before_try; x = PREV_INSN (x))
3460 if (JUMP_P (x))
3462 peep2_do_rebuild_jump_labels = true;
3463 break;
3466 return last;
3469 /* After performing a replacement in basic block BB, fix up the life
3470 information in our buffer. LAST is the last of the insns that we
3471 emitted as a replacement. PREV is the insn before the start of
3472 the replacement. MATCH_LEN is the number of instructions that were
3473 matched, and which now need to be replaced in the buffer. */
3475 static void
3476 peep2_update_life (basic_block bb, int match_len, rtx_insn *last,
3477 rtx_insn *prev)
3479 int i = peep2_buf_position (peep2_current + match_len + 1);
3480 rtx_insn *x;
3481 regset_head live;
3483 INIT_REG_SET (&live);
3484 COPY_REG_SET (&live, peep2_insn_data[i].live_before);
3486 gcc_assert (peep2_current_count >= match_len + 1);
3487 peep2_current_count -= match_len + 1;
3489 x = last;
3492 if (INSN_P (x))
3494 df_insn_rescan (x);
3495 if (peep2_current_count < MAX_INSNS_PER_PEEP2)
3497 peep2_current_count++;
3498 if (--i < 0)
3499 i = MAX_INSNS_PER_PEEP2;
3500 peep2_insn_data[i].insn = x;
3501 df_simulate_one_insn_backwards (bb, x, &live);
3502 COPY_REG_SET (peep2_insn_data[i].live_before, &live);
3505 x = PREV_INSN (x);
3507 while (x != prev);
3508 CLEAR_REG_SET (&live);
3510 peep2_current = i;
3513 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3514 Return true if we added it, false otherwise. The caller will try to match
3515 peepholes against the buffer if we return false; otherwise it will try to
3516 add more instructions to the buffer. */
3518 static bool
3519 peep2_fill_buffer (basic_block bb, rtx_insn *insn, regset live)
3521 int pos;
3523 /* Once we have filled the maximum number of insns the buffer can hold,
3524 allow the caller to match the insns against peepholes. We wait until
3525 the buffer is full in case the target has similar peepholes of different
3526 length; we always want to match the longest if possible. */
3527 if (peep2_current_count == MAX_INSNS_PER_PEEP2)
3528 return false;
3530 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3531 any other pattern, lest it change the semantics of the frame info. */
3532 if (RTX_FRAME_RELATED_P (insn))
3534 /* Let the buffer drain first. */
3535 if (peep2_current_count > 0)
3536 return false;
3537 /* Now the insn will be the only thing in the buffer. */
3540 pos = peep2_buf_position (peep2_current + peep2_current_count);
3541 peep2_insn_data[pos].insn = insn;
3542 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3543 peep2_current_count++;
3545 df_simulate_one_insn_forwards (bb, insn, live);
3546 return true;
3549 /* Perform the peephole2 optimization pass. */
3551 static void
3552 peephole2_optimize (void)
3554 rtx_insn *insn;
3555 bitmap live;
3556 int i;
3557 basic_block bb;
3559 peep2_do_cleanup_cfg = false;
3560 peep2_do_rebuild_jump_labels = false;
3562 df_set_flags (DF_LR_RUN_DCE);
3563 df_note_add_problem ();
3564 df_analyze ();
3566 /* Initialize the regsets we're going to use. */
3567 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3568 peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack);
3569 search_ofs = 0;
3570 live = BITMAP_ALLOC (&reg_obstack);
3572 FOR_EACH_BB_REVERSE_FN (bb, cfun)
3574 bool past_end = false;
3575 int pos;
3577 rtl_profile_for_bb (bb);
3579 /* Start up propagation. */
3580 bitmap_copy (live, DF_LR_IN (bb));
3581 df_simulate_initialize_forwards (bb, live);
3582 peep2_reinit_state (live);
3584 insn = BB_HEAD (bb);
3585 for (;;)
3587 rtx_insn *attempt, *head;
3588 int match_len;
3590 if (!past_end && !NONDEBUG_INSN_P (insn))
3592 next_insn:
3593 insn = NEXT_INSN (insn);
3594 if (insn == NEXT_INSN (BB_END (bb)))
3595 past_end = true;
3596 continue;
3598 if (!past_end && peep2_fill_buffer (bb, insn, live))
3599 goto next_insn;
3601 /* If we did not fill an empty buffer, it signals the end of the
3602 block. */
3603 if (peep2_current_count == 0)
3604 break;
3606 /* The buffer filled to the current maximum, so try to match. */
3608 pos = peep2_buf_position (peep2_current + peep2_current_count);
3609 peep2_insn_data[pos].insn = PEEP2_EOB;
3610 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3612 /* Match the peephole. */
3613 head = peep2_insn_data[peep2_current].insn;
3614 attempt = peephole2_insns (PATTERN (head), head, &match_len);
3615 if (attempt != NULL)
3617 rtx_insn *last = peep2_attempt (bb, head, match_len, attempt);
3618 if (last)
3620 peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
3621 continue;
3625 /* No match: advance the buffer by one insn. */
3626 peep2_current = peep2_buf_position (peep2_current + 1);
3627 peep2_current_count--;
3631 default_rtl_profile ();
3632 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3633 BITMAP_FREE (peep2_insn_data[i].live_before);
3634 BITMAP_FREE (live);
3635 if (peep2_do_rebuild_jump_labels)
3636 rebuild_jump_labels (get_insns ());
3637 if (peep2_do_cleanup_cfg)
3638 cleanup_cfg (CLEANUP_CFG_CHANGED);
3641 /* Common predicates for use with define_bypass. */
3643 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3644 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3645 must be either a single_set or a PARALLEL with SETs inside. */
3648 store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3650 rtx out_set, in_set;
3651 rtx out_pat, in_pat;
3652 rtx out_exp, in_exp;
3653 int i, j;
3655 in_set = single_set (in_insn);
3656 if (in_set)
3658 if (!MEM_P (SET_DEST (in_set)))
3659 return false;
3661 out_set = single_set (out_insn);
3662 if (out_set)
3664 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)))
3665 return false;
3667 else
3669 out_pat = PATTERN (out_insn);
3671 if (GET_CODE (out_pat) != PARALLEL)
3672 return false;
3674 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3676 out_exp = XVECEXP (out_pat, 0, i);
3678 if (GET_CODE (out_exp) == CLOBBER)
3679 continue;
3681 gcc_assert (GET_CODE (out_exp) == SET);
3683 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set)))
3684 return false;
3688 else
3690 in_pat = PATTERN (in_insn);
3691 gcc_assert (GET_CODE (in_pat) == PARALLEL);
3693 for (i = 0; i < XVECLEN (in_pat, 0); i++)
3695 in_exp = XVECEXP (in_pat, 0, i);
3697 if (GET_CODE (in_exp) == CLOBBER)
3698 continue;
3700 gcc_assert (GET_CODE (in_exp) == SET);
3702 if (!MEM_P (SET_DEST (in_exp)))
3703 return false;
3705 out_set = single_set (out_insn);
3706 if (out_set)
3708 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_exp)))
3709 return false;
3711 else
3713 out_pat = PATTERN (out_insn);
3714 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3716 for (j = 0; j < XVECLEN (out_pat, 0); j++)
3718 out_exp = XVECEXP (out_pat, 0, j);
3720 if (GET_CODE (out_exp) == CLOBBER)
3721 continue;
3723 gcc_assert (GET_CODE (out_exp) == SET);
3725 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_exp)))
3726 return false;
3732 return true;
3735 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3736 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3737 or multiple set; IN_INSN should be single_set for truth, but for convenience
3738 of insn categorization may be any JUMP or CALL insn. */
3741 if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3743 rtx out_set, in_set;
3745 in_set = single_set (in_insn);
3746 if (! in_set)
3748 gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn));
3749 return false;
3752 if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE)
3753 return false;
3754 in_set = SET_SRC (in_set);
3756 out_set = single_set (out_insn);
3757 if (out_set)
3759 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3760 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3761 return false;
3763 else
3765 rtx out_pat;
3766 int i;
3768 out_pat = PATTERN (out_insn);
3769 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3771 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3773 rtx exp = XVECEXP (out_pat, 0, i);
3775 if (GET_CODE (exp) == CLOBBER)
3776 continue;
3778 gcc_assert (GET_CODE (exp) == SET);
3780 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3781 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3782 return false;
3786 return true;
3789 static unsigned int
3790 rest_of_handle_peephole2 (void)
3792 if (HAVE_peephole2)
3793 peephole2_optimize ();
3795 return 0;
3798 namespace {
3800 const pass_data pass_data_peephole2 =
3802 RTL_PASS, /* type */
3803 "peephole2", /* name */
3804 OPTGROUP_NONE, /* optinfo_flags */
3805 TV_PEEPHOLE2, /* tv_id */
3806 0, /* properties_required */
3807 0, /* properties_provided */
3808 0, /* properties_destroyed */
3809 0, /* todo_flags_start */
3810 TODO_df_finish, /* todo_flags_finish */
3813 class pass_peephole2 : public rtl_opt_pass
3815 public:
3816 pass_peephole2 (gcc::context *ctxt)
3817 : rtl_opt_pass (pass_data_peephole2, ctxt)
3820 /* opt_pass methods: */
3821 /* The epiphany backend creates a second instance of this pass, so we need
3822 a clone method. */
3823 opt_pass * clone () { return new pass_peephole2 (m_ctxt); }
3824 virtual bool gate (function *) { return (optimize > 0 && flag_peephole2); }
3825 virtual unsigned int execute (function *)
3827 return rest_of_handle_peephole2 ();
3830 }; // class pass_peephole2
3832 } // anon namespace
3834 rtl_opt_pass *
3835 make_pass_peephole2 (gcc::context *ctxt)
3837 return new pass_peephole2 (ctxt);
3840 namespace {
3842 const pass_data pass_data_split_all_insns =
3844 RTL_PASS, /* type */
3845 "split1", /* name */
3846 OPTGROUP_NONE, /* optinfo_flags */
3847 TV_NONE, /* tv_id */
3848 0, /* properties_required */
3849 0, /* properties_provided */
3850 0, /* properties_destroyed */
3851 0, /* todo_flags_start */
3852 0, /* todo_flags_finish */
3855 class pass_split_all_insns : public rtl_opt_pass
3857 public:
3858 pass_split_all_insns (gcc::context *ctxt)
3859 : rtl_opt_pass (pass_data_split_all_insns, ctxt)
3862 /* opt_pass methods: */
3863 /* The epiphany backend creates a second instance of this pass, so
3864 we need a clone method. */
3865 opt_pass * clone () { return new pass_split_all_insns (m_ctxt); }
3866 virtual unsigned int execute (function *)
3868 split_all_insns ();
3869 return 0;
3872 }; // class pass_split_all_insns
3874 } // anon namespace
3876 rtl_opt_pass *
3877 make_pass_split_all_insns (gcc::context *ctxt)
3879 return new pass_split_all_insns (ctxt);
3882 static unsigned int
3883 rest_of_handle_split_after_reload (void)
3885 /* If optimizing, then go ahead and split insns now. */
3886 #ifndef STACK_REGS
3887 if (optimize > 0)
3888 #endif
3889 split_all_insns ();
3890 return 0;
3893 namespace {
3895 const pass_data pass_data_split_after_reload =
3897 RTL_PASS, /* type */
3898 "split2", /* name */
3899 OPTGROUP_NONE, /* optinfo_flags */
3900 TV_NONE, /* tv_id */
3901 0, /* properties_required */
3902 0, /* properties_provided */
3903 0, /* properties_destroyed */
3904 0, /* todo_flags_start */
3905 0, /* todo_flags_finish */
3908 class pass_split_after_reload : public rtl_opt_pass
3910 public:
3911 pass_split_after_reload (gcc::context *ctxt)
3912 : rtl_opt_pass (pass_data_split_after_reload, ctxt)
3915 /* opt_pass methods: */
3916 virtual unsigned int execute (function *)
3918 return rest_of_handle_split_after_reload ();
3921 }; // class pass_split_after_reload
3923 } // anon namespace
3925 rtl_opt_pass *
3926 make_pass_split_after_reload (gcc::context *ctxt)
3928 return new pass_split_after_reload (ctxt);
3931 namespace {
3933 const pass_data pass_data_split_before_regstack =
3935 RTL_PASS, /* type */
3936 "split3", /* name */
3937 OPTGROUP_NONE, /* optinfo_flags */
3938 TV_NONE, /* tv_id */
3939 0, /* properties_required */
3940 0, /* properties_provided */
3941 0, /* properties_destroyed */
3942 0, /* todo_flags_start */
3943 0, /* todo_flags_finish */
3946 class pass_split_before_regstack : public rtl_opt_pass
3948 public:
3949 pass_split_before_regstack (gcc::context *ctxt)
3950 : rtl_opt_pass (pass_data_split_before_regstack, ctxt)
3953 /* opt_pass methods: */
3954 virtual bool gate (function *);
3955 virtual unsigned int execute (function *)
3957 split_all_insns ();
3958 return 0;
3961 }; // class pass_split_before_regstack
3963 bool
3964 pass_split_before_regstack::gate (function *)
3966 #if HAVE_ATTR_length && defined (STACK_REGS)
3967 /* If flow2 creates new instructions which need splitting
3968 and scheduling after reload is not done, they might not be
3969 split until final which doesn't allow splitting
3970 if HAVE_ATTR_length. */
3971 # ifdef INSN_SCHEDULING
3972 return (optimize && !flag_schedule_insns_after_reload);
3973 # else
3974 return (optimize);
3975 # endif
3976 #else
3977 return 0;
3978 #endif
3981 } // anon namespace
3983 rtl_opt_pass *
3984 make_pass_split_before_regstack (gcc::context *ctxt)
3986 return new pass_split_before_regstack (ctxt);
3989 static unsigned int
3990 rest_of_handle_split_before_sched2 (void)
3992 #ifdef INSN_SCHEDULING
3993 split_all_insns ();
3994 #endif
3995 return 0;
3998 namespace {
4000 const pass_data pass_data_split_before_sched2 =
4002 RTL_PASS, /* type */
4003 "split4", /* name */
4004 OPTGROUP_NONE, /* optinfo_flags */
4005 TV_NONE, /* tv_id */
4006 0, /* properties_required */
4007 0, /* properties_provided */
4008 0, /* properties_destroyed */
4009 0, /* todo_flags_start */
4010 0, /* todo_flags_finish */
4013 class pass_split_before_sched2 : public rtl_opt_pass
4015 public:
4016 pass_split_before_sched2 (gcc::context *ctxt)
4017 : rtl_opt_pass (pass_data_split_before_sched2, ctxt)
4020 /* opt_pass methods: */
4021 virtual bool gate (function *)
4023 #ifdef INSN_SCHEDULING
4024 return optimize > 0 && flag_schedule_insns_after_reload;
4025 #else
4026 return false;
4027 #endif
4030 virtual unsigned int execute (function *)
4032 return rest_of_handle_split_before_sched2 ();
4035 }; // class pass_split_before_sched2
4037 } // anon namespace
4039 rtl_opt_pass *
4040 make_pass_split_before_sched2 (gcc::context *ctxt)
4042 return new pass_split_before_sched2 (ctxt);
4045 namespace {
4047 const pass_data pass_data_split_for_shorten_branches =
4049 RTL_PASS, /* type */
4050 "split5", /* name */
4051 OPTGROUP_NONE, /* optinfo_flags */
4052 TV_NONE, /* tv_id */
4053 0, /* properties_required */
4054 0, /* properties_provided */
4055 0, /* properties_destroyed */
4056 0, /* todo_flags_start */
4057 0, /* todo_flags_finish */
4060 class pass_split_for_shorten_branches : public rtl_opt_pass
4062 public:
4063 pass_split_for_shorten_branches (gcc::context *ctxt)
4064 : rtl_opt_pass (pass_data_split_for_shorten_branches, ctxt)
4067 /* opt_pass methods: */
4068 virtual bool gate (function *)
4070 /* The placement of the splitting that we do for shorten_branches
4071 depends on whether regstack is used by the target or not. */
4072 #if HAVE_ATTR_length && !defined (STACK_REGS)
4073 return true;
4074 #else
4075 return false;
4076 #endif
4079 virtual unsigned int execute (function *)
4081 return split_all_insns_noflow ();
4084 }; // class pass_split_for_shorten_branches
4086 } // anon namespace
4088 rtl_opt_pass *
4089 make_pass_split_for_shorten_branches (gcc::context *ctxt)
4091 return new pass_split_for_shorten_branches (ctxt);
4094 /* (Re)initialize the target information after a change in target. */
4096 void
4097 recog_init ()
4099 /* The information is zero-initialized, so we don't need to do anything
4100 first time round. */
4101 if (!this_target_recog->x_initialized)
4103 this_target_recog->x_initialized = true;
4104 return;
4106 memset (this_target_recog->x_bool_attr_masks, 0,
4107 sizeof (this_target_recog->x_bool_attr_masks));
4108 for (unsigned int i = 0; i < NUM_INSN_CODES; ++i)
4109 if (this_target_recog->x_op_alt[i])
4111 free (this_target_recog->x_op_alt[i]);
4112 this_target_recog->x_op_alt[i] = 0;