| blob | f343d92f9f529b8874ec3c486d91d079315514bf |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
70 /* This file should be included last. */
73 /* Defined for convenience. */
74 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
76 /* Classifies an address.
78 ADDRESS_REG_IMM
79 A simple base register plus immediate offset.
81 ADDRESS_REG_WB
82 A base register indexed by immediate offset with writeback.
84 ADDRESS_REG_REG
85 A base register indexed by (optionally scaled) register.
87 ADDRESS_REG_UXTW
88 A base register indexed by (optionally scaled) zero-extended register.
90 ADDRESS_REG_SXTW
91 A base register indexed by (optionally scaled) sign-extended register.
93 ADDRESS_LO_SUM
94 A LO_SUM rtx with a base register and "LO12" symbol relocation.
96 ADDRESS_SYMBOLIC:
97 A constant symbolic address, in pc-relative literal pool. */
100 ADDRESS_REG_IMM,
101 ADDRESS_REG_WB,
102 ADDRESS_REG_REG,
103 ADDRESS_REG_UXTW,
104 ADDRESS_REG_SXTW,
105 ADDRESS_LO_SUM,
106 ADDRESS_SYMBOLIC
107 };
111 rtx base;
112 rtx offset;
115 };
117 struct simd_immediate_info
118 {
119 rtx value;
124 };
126 /* The current code model. */
129 #ifdef HAVE_AS_TLS
130 #undef TARGET_HAVE_TLS
131 #define TARGET_HAVE_TLS 1
132 #endif
136 const_tree,
147 const_tree type,
151 /* Major revision number of the ARM Architecture implemented by the target. */
154 /* The processor for which instructions should be scheduled. */
157 /* Mask to specify which instruction scheduling options should be used. */
160 /* Global flag for PC relative loads. */
163 /* Support for command line parsing of boolean flags in the tuning
164 structures. */
165 struct aarch64_flag_desc
166 {
169 };
171 #define AARCH64_FUSION_PAIR(name, internal_name) \
172 { name, AARCH64_FUSE_##internal_name },
174 {
179 };
181 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
182 { name, AARCH64_EXTRA_TUNE_##internal_name },
184 {
189 };
191 /* Tuning parameters. */
194 {
195 {
200 },
207 };
210 {
211 {
216 },
223 };
226 {
227 {
232 },
239 };
242 {
243 {
248 },
255 };
258 {
259 {
264 },
271 };
274 {
275 {
280 },
287 };
290 {
292 /* Avoid the use of slow int<->fp moves for spilling by setting
293 their cost higher than memmov_cost. */
297 };
300 {
302 /* Avoid the use of slow int<->fp moves for spilling by setting
303 their cost higher than memmov_cost. */
307 };
310 {
312 /* Avoid the use of slow int<->fp moves for spilling by setting
313 their cost higher than memmov_cost. */
317 };
320 {
322 /* Avoid the use of slow int<->fp moves for spilling by setting
323 their cost higher than memmov_cost (actual, 4 and 9). */
327 };
330 {
335 };
338 {
340 /* Avoid the use of slow int<->fp moves for spilling by setting
341 their cost higher than memmov_cost. */
345 };
348 {
350 /* Avoid the use of int<->fp moves for spilling. */
354 };
357 {
359 /* Avoid the use of int<->fp moves for spilling. */
363 };
365 /* Generic costs for vector insn classes. */
367 {
381 };
383 /* ThunderX costs for vector insn classes. */
385 {
399 };
401 /* Generic costs for vector insn classes. */
403 {
417 };
420 {
434 };
436 /* Generic costs for vector insn classes. */
438 {
452 };
454 /* Costs for vector insn classes for Vulcan. */
456 {
470 };
472 /* Generic costs for branch instructions. */
474 {
477 };
479 /* Branch costs for Cortex-A57. */
481 {
484 };
486 /* Branch costs for Vulcan. */
488 {
491 };
493 /* Generic approximation modes. */
495 {
498 AARCH64_APPROX_NONE /* recip_sqrt */
499 };
501 /* Approximation modes for Exynos M1. */
503 {
506 AARCH64_APPROX_ALL /* recip_sqrt */
507 };
509 /* Approximation modes for X-Gene 1. */
511 {
514 AARCH64_APPROX_ALL /* recip_sqrt */
515 };
518 {
540 };
543 {
566 };
569 {
592 };
595 {
618 };
621 {
644 };
647 {
670 };
673 {
695 };
698 {
720 };
723 {
745 };
748 {
771 };
774 {
796 };
798 /* Support for fine-grained override of the tuning structures. */
799 struct aarch64_tuning_override_function
800 {
803 };
808 static const struct aarch64_tuning_override_function
809 aarch64_tuning_override_functions[] =
810 {
814 };
816 /* A processor implementing AArch64. */
817 struct processor
818 {
826 };
828 /* Architectures implementing AArch64. */
830 {
831 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
832 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
835 };
837 /* Processor cores implementing AArch64. */
839 {
840 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
841 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
842 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
843 FLAGS, &COSTS##_tunings},
848 };
851 /* Target specification. These are populated by the -march, -mtune, -mcpu
852 handling code or by target attributes. */
857 /* The current tuning set. */
860 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
862 /* An ISA extension in the co-processor and main instruction set space. */
863 struct aarch64_option_extension
864 {
868 };
871 {
875 }
876 aarch64_cc;
878 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
880 /* The condition codes of the processor, and the inverse function. */
882 {
885 };
887 /* Generate code to enable conditional branches in functions over 1 MiB. */
891 {
908 }
910 void
912 {
916 else
918 }
920 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
921 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
922 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
923 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
924 cost (in this case the best class is the lowest cost one). Using ALL_REGS
925 irrespectively of its cost results in bad allocations with many redundant
926 int<->FP moves which are expensive on various cores.
927 To avoid this we don't allow ALL_REGS as the allocno class, but force a
928 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
929 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
930 Otherwise set the allocno class depending on the mode.
931 The result of this is that it is no longer inefficient to have a higher
932 memory move cost than the register move cost.
933 */
935 static reg_class_t
937 reg_class_t best_class)
938 {
949 }
951 static unsigned int
953 {
957 }
959 static int
962 {
970 }
972 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
973 unsigned
975 {
983 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
984 equivalent DWARF register. */
986 }
988 /* Return TRUE if MODE is any of the large INT modes. */
989 static bool
991 {
993 }
995 /* Return TRUE if MODE is any of the vector modes. */
996 static bool
998 {
1001 }
1003 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1004 static bool
1007 {
1015 }
1017 /* Implement HARD_REGNO_NREGS. */
1019 int
1021 {
1023 {
1029 }
1031 }
1033 /* Implement HARD_REGNO_MODE_OK. */
1035 int
1037 {
1042 /* The purpose of comparing with ptr_mode is to support the
1043 global register variable associated with the stack pointer
1044 register via the syntax of asm ("wsp") in ILP32. */
1054 {
1056 return
1058 else
1060 }
1063 }
1065 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1066 machine_mode
1068 machine_mode mode)
1069 {
1070 /* Handle modes that fit within single registers. */
1072 {
1075 else
1077 }
1078 /* Fall back to generic for multi-reg and very large modes. */
1079 else
1081 }
1083 /* Return true if calls to DECL should be treated as
1084 long-calls (ie called via a register). */
1085 static bool
1087 {
1089 }
1091 /* Return true if calls to symbol-ref SYM should be treated as
1092 long-calls (ie called via a register). */
1093 bool
1095 {
1097 }
1099 /* Return true if calls to symbol-ref SYM should not go through
1100 plt stubs. */
1102 bool
1104 {
1108 && decl
1109 && (!flag_plt
1115 }
1117 /* Return true if the offsets to a zero/sign-extract operation
1118 represent an expression that matches an extend operation. The
1119 operands represent the paramters from
1121 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1122 bool
1124 rtx extract_imm)
1125 {
1142 }
1144 /* Emit an insn that's a simple single-set. Both the operands must be
1145 known to be valid. */
1148 {
1150 }
1152 /* X and Y are two things to compare using CODE. Emit the compare insn and
1153 return the rtx for register 0 in the proper mode. */
1154 rtx
1156 {
1162 }
1164 /* Build the SYMBOL_REF for __tls_get_addr. */
1168 rtx
1170 {
1174 }
1176 /* Return the TLS model to use for ADDR. */
1178 static enum tls_model
1180 {
1185 {
1189 }
1194 }
1196 /* We'll allow lo_sum's in addresses in our legitimate addresses
1197 so that combine would take care of combining addresses where
1198 necessary, but for generation purposes, we'll generate the address
1199 as :
1200 RTL Absolute
1201 tmp = hi (symbol_ref); adrp x1, foo
1202 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1203 nop
1205 PIC TLS
1206 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1207 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1208 bl __tls_get_addr
1209 nop
1211 Load TLS symbol, depending on TLS mechanism and TLS access model.
1213 Global Dynamic - Traditional TLS:
1214 adrp tmp, :tlsgd:imm
1215 add dest, tmp, #:tlsgd_lo12:imm
1216 bl __tls_get_addr
1218 Global Dynamic - TLS Descriptors:
1219 adrp dest, :tlsdesc:imm
1220 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1221 add dest, dest, #:tlsdesc_lo12:imm
1222 blr tmp
1223 mrs tp, tpidr_el0
1224 add dest, dest, tp
1226 Initial Exec:
1227 mrs tp, tpidr_el0
1228 adrp tmp, :gottprel:imm
1229 ldr dest, [tmp, #:gottprel_lo12:imm]
1230 add dest, dest, tp
1232 Local Exec:
1233 mrs tp, tpidr_el0
1234 add t0, tp, #:tprel_hi12:imm, lsl #12
1235 add t0, t0, #:tprel_lo12_nc:imm
1236 */
1238 static void
1241 {
1243 {
1245 {
1246 /* In ILP32, the mode of dest can be either SImode or DImode. */
1258 }
1265 {
1268 rtx insn;
1269 rtx mem;
1271 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1272 here before rtl expand. Tree IVOPT will generate rtl pattern to
1273 decide rtx costs, in which case pic_offset_table_rtx is not
1274 initialized. For that case no need to generate the first adrp
1275 instruction as the final cost for global variable access is
1276 one instruction. */
1278 {
1279 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1280 using the page base as GOT base, the first page may be wasted,
1281 in the worst scenario, there is only 28K space for GOT).
1283 The generate instruction sequence for accessing global variable
1284 is:
1286 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1288 Only one instruction needed. But we must initialize
1289 pic_offset_table_rtx properly. We generate initialize insn for
1290 every global access, and allow CSE to remove all redundant.
1292 The final instruction sequences will look like the following
1293 for multiply global variables access.
1295 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1297 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1298 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1299 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1300 ... */
1309 }
1312 {
1315 else
1319 }
1320 else
1321 {
1326 }
1328 /* The operand is expected to be MEM. Whenever the related insn
1329 pattern changed, above code which calculate mem should be
1330 updated. */
1336 }
1339 {
1340 /* In ILP32, the mode of dest can be either SImode or DImode,
1341 while the got entry is always of SImode size. The mode of
1342 dest depends on how dest is used: if dest is assigned to a
1343 pointer (e.g. in the memory), it has SImode; it may have
1344 DImode if dest is dereferenced to access the memeory.
1345 This is why we have to handle three different ldr_got_small
1346 patterns here (two patterns for ILP32). */
1348 rtx insn;
1349 rtx mem;
1358 {
1361 else
1365 }
1366 else
1367 {
1372 }
1379 }
1382 {
1390 else
1398 }
1401 {
1404 rtx tp;
1408 /* In ILP32, the got entry is always of SImode size. Unlike
1409 small GOT, the dest is fixed at reg 0. */
1412 else
1422 }
1425 {
1426 /* In ILP32, the mode of dest can be either SImode or DImode,
1427 while the got entry is always of SImode size. The mode of
1428 dest depends on how dest is used: if dest is assigned to a
1429 pointer (e.g. in the memory), it has SImode; it may have
1430 DImode if dest is dereferenced to access the memeory.
1431 This is why we have to handle three different tlsie_small
1432 patterns here (two patterns for ILP32). */
1438 {
1441 else
1442 {
1445 }
1446 }
1447 else
1448 {
1451 }
1456 }
1462 {
1470 {
1493 }
1497 }
1504 {
1509 {
1512 else
1513 {
1516 }
1517 }
1518 else
1519 {
1522 }
1526 }
1530 }
1531 }
1533 /* Emit a move from SRC to DEST. Assume that the move expanders can
1534 handle all moves if !can_create_pseudo_p (). The distinction is
1535 important because, unlike emit_move_insn, the move expanders know
1536 how to force Pmode objects into the constant pool even when the
1537 constant pool address is not itself legitimate. */
1538 static rtx
1540 {
1544 }
1546 /* Split a 128-bit move operation into two 64-bit move operations,
1547 taking care to handle partial overlap of register to register
1548 copies. Special cases are needed when moving between GP regs and
1549 FP regs. SRC can be a register, constant or memory; DST a register
1550 or memory. If either operand is memory it must not have any side
1551 effects. */
1552 void
1554 {
1565 {
1569 /* Handle FP <-> GP regs. */
1571 {
1576 {
1579 }
1580 else
1581 {
1584 }
1586 }
1588 {
1593 {
1596 }
1597 else
1598 {
1601 }
1603 }
1604 }
1611 /* At most one pairing may overlap. */
1613 {
1616 }
1617 else
1618 {
1621 }
1622 }
1624 bool
1626 {
1629 }
1631 /* Split a complex SIMD combine. */
1633 void
1635 {
1642 {
1646 {
1670 }
1674 }
1675 }
1677 /* Split a complex SIMD move. */
1679 void
1681 {
1688 {
1694 {
1718 }
1722 }
1723 }
1725 bool
1728 {
1732 }
1735 static rtx
1737 {
1740 else
1741 {
1744 }
1745 }
1748 static rtx
1750 {
1752 {
1753 rtx high;
1754 /* Load the full offset into a register. This
1755 might be improvable in the future. */
1761 }
1763 }
1765 static int
1767 machine_mode mode)
1768 {
1777 {
1781 }
1784 {
1786 {
1791 else
1794 }
1796 }
1798 /* Remaining cases are all for DImode. */
1807 {
1808 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1809 For a 64-bit bitmask try whether changing 16 bits to all ones or
1810 zeroes creates a valid bitmask. To check any repeated bitmask,
1811 try using 16 bits from the other 32-bit half of val. */
1814 {
1825 }
1827 {
1829 {
1833 }
1835 }
1836 }
1838 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1839 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1840 otherwise skip zero bits. */
1852 {
1858 num_insns ++;
1859 }
1862 }
1865 void
1867 {
1872 /* Check on what type of symbol it is. */
1876 {
1880 /* If we have (const (plus symbol offset)), separate out the offset
1881 before we start classifying the symbol. */
1886 {
1890 {
1896 }
1901 /* If we aren't generating PC relative literals, then
1902 we need to expand the literal pool access carefully.
1903 This is something that needs to be done in a number
1904 of places, so could well live as a separate function. */
1906 {
1911 }
1928 {
1934 }
1935 /* FALLTHRU */
1948 }
1949 }
1952 {
1955 else
1956 {
1960 }
1963 }
1966 }
1968 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
1969 temporary value if necessary. FRAME_RELATED_P should be true if
1970 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
1971 to the generated instructions. If SCRATCHREG is known to hold
1972 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
1973 immediate again.
1975 Since this function may be used to adjust the stack pointer, we must
1976 ensure that it cannot cause transient stack deallocation (for example
1977 by first incrementing SP and then decrementing when adjusting by a
1978 large immediate). */
1980 static void
1984 {
1992 /* Single instruction adjustment. */
1994 {
1998 }
2000 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2001 Only do this if mdelta is not a 16-bit move as adjusting using a move
2002 is better. */
2004 {
2013 }
2015 /* Emit a move immediate if required and an addition/subtraction. */
2022 {
2026 }
2027 }
2031 HOST_WIDE_INT delta)
2032 {
2034 }
2038 {
2041 }
2045 {
2048 }
2050 static bool
2052 tree exp ATTRIBUTE_UNUSED)
2053 {
2054 /* Currently, always true. */
2056 }
2058 /* Implement TARGET_PASS_BY_REFERENCE. */
2060 static bool
2062 machine_mode mode,
2063 const_tree type,
2065 {
2066 HOST_WIDE_INT size;
2067 machine_mode dummymode;
2070 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2074 /* Aggregates are passed by reference based on their size. */
2076 {
2078 }
2080 /* Variable sized arguments are always returned by reference. */
2084 /* Can this be a candidate to be passed in fp/simd register(s)? */
2087 NULL))
2090 /* Arguments which are variable sized or larger than 2 registers are
2091 passed by reference unless they are a homogenous floating point
2092 aggregate. */
2094 }
2096 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2097 static bool
2099 {
2100 machine_mode dummy_mode;
2103 /* Never happens in little-endian mode. */
2107 /* Only composite types smaller than or equal to 16 bytes can
2108 be potentially returned in registers. */
2114 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2115 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2116 is always passed/returned in the least significant bits of fp/simd
2117 register(s). */
2123 }
2125 /* Implement TARGET_FUNCTION_VALUE.
2126 Define how to find the value returned by a function. */
2128 static rtx
2131 {
2132 machine_mode mode;
2135 machine_mode ag_mode;
2142 {
2146 {
2149 }
2150 }
2154 {
2156 {
2159 }
2160 else
2161 {
2163 rtx par;
2167 {
2172 }
2174 }
2175 }
2176 else
2178 }
2180 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2181 Return true if REGNO is the number of a hard register in which the values
2182 of called function may come back. */
2184 static bool
2186 {
2187 /* Maximum of 16 bytes can be returned in the general registers. Examples
2188 of 16-byte return values are: 128-bit integers and 16-byte small
2189 structures (excluding homogeneous floating-point aggregates). */
2193 /* Up to four fp/simd registers can return a function value, e.g. a
2194 homogeneous floating-point aggregate having four members. */
2199 }
2201 /* Implement TARGET_RETURN_IN_MEMORY.
2203 If the type T of the result of a function is such that
2204 void func (T arg)
2205 would require that arg be passed as a value in a register (or set of
2206 registers) according to the parameter passing rules, then the result
2207 is returned in the same registers as would be used for such an
2208 argument. */
2210 static bool
2212 {
2213 HOST_WIDE_INT size;
2214 machine_mode ag_mode;
2220 /* Simple scalar types always returned in registers. */
2224 type,
2227 NULL))
2230 /* Types larger than 2 registers returned in memory. */
2233 }
2235 static bool
2238 {
2241 type,
2243 nregs,
2244 NULL);
2245 }
2247 /* Given MODE and TYPE of a function argument, return the alignment in
2248 bits. The idea is to suppress any stronger alignment requested by
2249 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2250 This is a helper function for local use only. */
2252 static unsigned int
2254 {
2274 }
2276 /* Layout a function argument according to the AAPCS64 rules. The rule
2277 numbers refer to the rule numbers in the AAPCS64. */
2279 static void
2281 const_tree type,
2283 {
2287 HOST_WIDE_INT size;
2289 /* We need to do this once per argument. */
2295 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2296 size
2298 UNITS_PER_WORD);
2302 mode,
2303 type,
2306 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2307 The following code thus handles passing by SIMD/FP registers first. */
2311 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2312 and homogenous short-vector aggregates (HVA). */
2314 {
2319 {
2322 {
2325 }
2326 else
2327 {
2328 rtx par;
2332 {
2335 tmp = gen_rtx_EXPR_LIST
2339 }
2341 }
2343 }
2344 else
2345 {
2346 /* C.3 NSRN is set to 8. */
2349 }
2350 }
2355 /* C6 - C9. though the sign and zero extension semantics are
2356 handled elsewhere. This is the case where the argument fits
2357 entirely general registers. */
2359 {
2364 /* C.8 if the argument has an alignment of 16 then the NGRN is
2365 rounded up to the next even number. */
2367 {
2370 }
2371 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2372 A reg is still generated for it, but the caller should be smart
2373 enough not to use it. */
2375 {
2377 }
2378 else
2379 {
2380 rtx par;
2385 {
2390 }
2392 }
2396 }
2398 /* C.11 */
2401 /* The argument is passed on stack; record the needed number of words for
2402 this argument and align the total size if necessary. */
2403 on_stack:
2409 }
2411 /* Implement TARGET_FUNCTION_ARG. */
2413 static rtx
2416 {
2425 }
2427 void
2429 const_tree fntype ATTRIBUTE_UNUSED,
2430 rtx libname ATTRIBUTE_UNUSED,
2431 const_tree fndecl ATTRIBUTE_UNUSED,
2433 {
2447 {
2454 }
2456 }
2458 static void
2460 machine_mode mode,
2461 const_tree type,
2463 {
2466 {
2476 }
2477 }
2479 bool
2481 {
2484 }
2486 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2487 PARM_BOUNDARY bits of alignment, but will be given anything up
2488 to STACK_BOUNDARY bits if the type requires it. This makes sure
2489 that both before and after the layout of each argument, the Next
2490 Stacked Argument Address (NSAA) will have a minimum alignment of
2491 8 bytes. */
2493 static unsigned int
2495 {
2503 }
2505 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2507 Return true if an argument passed on the stack should be padded upwards,
2508 i.e. if the least-significant byte of the stack slot has useful data.
2510 Small aggregate types are placed in the lowest memory address.
2512 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2514 bool
2516 {
2517 /* On little-endian targets, the least significant byte of every stack
2518 argument is passed at the lowest byte address of the stack slot. */
2522 /* Otherwise, integral, floating-point and pointer types are padded downward:
2523 the least significant byte of a stack argument is passed at the highest
2524 byte address of the stack slot. */
2531 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2533 }
2535 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2537 It specifies padding for the last (may also be the only)
2538 element of a block move between registers and memory. If
2539 assuming the block is in the memory, padding upward means that
2540 the last element is padded after its highest significant byte,
2541 while in downward padding, the last element is padded at the
2542 its least significant byte side.
2544 Small aggregates and small complex types are always padded
2545 upwards.
2547 We don't need to worry about homogeneous floating-point or
2548 short-vector aggregates; their move is not affected by the
2549 padding direction determined here. Regardless of endianness,
2550 each element of such an aggregate is put in the least
2551 significant bits of a fp/simd register.
2553 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2554 register has useful data, and return the opposite if the most
2555 significant byte does. */
2557 bool
2560 {
2562 /* Small composite types are always padded upward. */
2564 {
2569 }
2571 /* Otherwise, use the default padding. */
2573 }
2575 static machine_mode
2577 {
2579 }
2581 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2583 /* We use the 12-bit shifted immediate arithmetic instructions so values
2584 must be multiple of (1 << 12), i.e. 4096. */
2585 #define ARITH_FACTOR 4096
2587 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2588 #error Cannot use simple address calculation for stack probing
2589 #endif
2591 /* The pair of scratch registers used for stack probing. */
2592 #define PROBE_STACK_FIRST_REG 9
2593 #define PROBE_STACK_SECOND_REG 10
2595 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2596 inclusive. These are offsets from the current stack pointer. */
2598 static void
2600 {
2603 /* See the same assertion on PROBE_INTERVAL above. */
2606 /* See if we have a constant small number of probes to generate. If so,
2607 that's the easy case. */
2609 {
2616 }
2618 /* The run-time loop is made up of 8 insns in the generic case while the
2619 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2621 {
2626 stack_pointer_rtx,
2630 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2631 it exceeds SIZE. If only two probes are needed, this will not
2632 generate any code. Then probe at FIRST + SIZE. */
2634 {
2638 }
2642 {
2647 }
2648 else
2650 }
2652 /* Otherwise, do the same as above, but in a loop. Note that we must be
2653 extra careful with variables wrapping around because we might be at
2654 the very top (or the very bottom) of the address space and we have
2655 to be able to handle this case properly; in particular, we use an
2656 equality test for the loop condition. */
2657 else
2658 {
2661 /* Step 1: round SIZE to the previous multiple of the interval. */
2666 /* Step 2: compute initial and final value of the loop counter. */
2668 /* TEST_ADDR = SP + FIRST. */
2672 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2678 /* Step 3: the loop
2680 do
2681 {
2682 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2683 probe at TEST_ADDR
2684 }
2685 while (TEST_ADDR != LAST_ADDR)
2687 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2688 until it is equal to ROUNDED_SIZE. */
2692 else
2696 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2697 that SIZE is equal to ROUNDED_SIZE. */
2700 {
2704 {
2709 }
2710 else
2712 }
2713 }
2715 /* Make sure nothing is scheduled before we are done. */
2717 }
2719 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2720 absolute addresses. */
2724 {
2731 /* Loop. */
2734 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2739 /* Probe at TEST_ADDR. */
2742 /* Test if TEST_ADDR == LAST_ADDR. */
2746 /* Branch. */
2752 }
2754 static bool
2756 {
2757 /* In aarch64_override_options_after_change
2758 flag_omit_leaf_frame_pointer turns off the frame pointer by
2759 default. Turn it back on now if we've not got a leaf
2760 function. */
2765 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2770 }
2772 /* Mark the registers that need to be saved by the callee and calculate
2773 the size of the callee-saved registers area and frame record (both FP
2774 and LR may be omitted). */
2775 static void
2777 {
2784 #define SLOT_NOT_REQUIRED (-2)
2785 #define SLOT_REQUIRED (-1)
2790 /* First mark all the registers that really need to be saved... */
2797 /* ... that includes the eh data registers (if needed)... */
2803 /* ... and any callee saved register that dataflow says is live. */
2813 {
2816 }
2819 {
2820 /* FP and LR are placed in the linkage record. */
2826 }
2828 /* Now assign stack slots for them. */
2831 {
2838 }
2846 {
2847 /* If there is an alignment gap between integer and fp callee-saves,
2848 allocate the last fp register to it if possible. */
2850 {
2853 }
2862 }
2868 HOST_WIDE_INT varargs_and_saved_regs_size
2895 {
2896 /* Simple, small frame with no outgoing arguments:
2897 stp reg1, reg2, [sp, -frame_size]!
2898 stp reg3, reg4, [sp, 16] */
2900 }
2905 {
2906 /* Frame with small outgoing arguments:
2907 sub sp, sp, frame_size
2908 stp reg1, reg2, [sp, outgoing_args_size]
2909 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2913 }
2915 {
2916 /* Frame with large outgoing arguments but a small local area:
2917 stp reg1, reg2, [sp, -hard_fp_offset]!
2918 stp reg3, reg4, [sp, 16]
2919 sub sp, sp, outgoing_args_size */
2923 }
2926 {
2927 /* Frame with large local area and outgoing arguments (this pushes the
2928 callee-saves first, followed by the locals and outgoing area):
2929 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
2930 stp reg3, reg4, [sp, 16]
2931 sub sp, sp, frame_size - varargs_and_saved_regs_size */
2937 }
2938 else
2939 {
2940 /* Frame with large local area and outgoing arguments using frame pointer:
2941 sub sp, sp, hard_fp_offset
2942 stp x29, x30, [sp, 0]
2943 add x29, sp, 0
2944 stp reg3, reg4, [sp, 16]
2945 sub sp, sp, outgoing_args_size */
2949 }
2952 }
2954 /* Return true if the register REGNO is saved on entry to
2955 the current function. */
2957 static bool
2959 {
2961 }
2963 /* Return the next register up from REGNO up to LIMIT for the callee
2964 to save. */
2966 static unsigned
2968 {
2970 regno ++;
2972 }
2974 /* Push the register number REGNO of mode MODE to the stack with write-back
2975 adjusting the stack by ADJUSTMENT. */
2977 static void
2979 HOST_WIDE_INT adjustment)
2980 {
2991 }
2993 /* Generate and return an instruction to store the pair of registers
2994 REG and REG2 of mode MODE to location BASE with write-back adjusting
2995 the stack location BASE by ADJUSTMENT. */
2997 static rtx
2999 HOST_WIDE_INT adjustment)
3000 {
3002 {
3013 }
3014 }
3016 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3017 stack pointer by ADJUSTMENT. */
3019 static void
3021 {
3036 }
3038 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3039 adjusting it by ADJUSTMENT afterwards. */
3041 static rtx
3043 HOST_WIDE_INT adjustment)
3044 {
3046 {
3055 }
3056 }
3058 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3059 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3060 into CFI_OPS. */
3062 static void
3065 {
3072 {
3076 }
3077 else
3078 {
3083 }
3084 }
3086 /* Generate and return a store pair instruction of mode MODE to store
3087 register REG1 to MEM1 and register REG2 to MEM2. */
3089 static rtx
3091 rtx reg2)
3092 {
3094 {
3103 }
3104 }
3106 /* Generate and regurn a load pair isntruction of mode MODE to load register
3107 REG1 from MEM1 and register REG2 from MEM2. */
3109 static rtx
3111 rtx mem2)
3112 {
3114 {
3123 }
3124 }
3126 /* Return TRUE if return address signing should be enabled for the current
3127 function, otherwise return FALSE. */
3129 bool
3131 {
3132 /* This function should only be called after frame laid out. */
3135 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
3136 if it's LR is pushed onto stack. */
3140 }
3142 /* Emit code to save the callee-saved registers from register number START
3143 to LIMIT to the stack at the location starting at offset START_OFFSET,
3144 skipping any write-back candidates if SKIP_WB is true. */
3146 static void
3149 {
3159 {
3161 HOST_WIDE_INT offset;
3174 offset));
3183 {
3185 rtx mem2;
3189 offset));
3191 reg2));
3193 /* The first part of a frame-related parallel insn is
3194 always assumed to be relevant to the frame
3195 calculations; subsequent parts, are only
3196 frame-related if explicitly marked. */
3199 }
3200 else
3204 }
3205 }
3207 /* Emit code to restore the callee registers of mode MODE from register
3208 number START up to and including LIMIT. Restore from the stack offset
3209 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3210 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3212 static void
3216 {
3222 HOST_WIDE_INT offset;
3227 {
3248 {
3250 rtx mem2;
3258 }
3259 else
3262 }
3263 }
3267 HOST_WIDE_INT offset)
3268 {
3270 }
3274 {
3278 }
3280 bool
3282 {
3286 }
3288 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3290 static sbitmap
3292 {
3298 /* The registers we need saved to the frame. */
3301 {
3306 /* Check that we can access the stack slot of the register with one
3307 direct load with no adjustments needed. */
3310 }
3312 /* Don't mess with the hard frame pointer. */
3318 /* If aarch64_layout_frame has chosen registers to store/restore with
3319 writeback don't interfere with them to avoid having to output explicit
3320 stack adjustment instructions. */
3330 }
3332 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3334 static sbitmap
3336 {
3344 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3353 }
3355 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3356 Nothing to do for aarch64. */
3358 static void
3360 {
3361 }
3363 /* Return the next set bit in BMP from START onwards. Return the total number
3364 of bits in BMP if no set bit is found at or after START. */
3366 static unsigned int
3368 {
3379 }
3381 /* Do the work for aarch64_emit_prologue_components and
3382 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3383 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3384 for these components or the epilogue sequence. That is, it determines
3385 whether we should emit stores or loads and what kind of CFA notes to attach
3386 to the insns. Otherwise the logic for the two sequences is very
3387 similar. */
3389 static void
3391 {
3393 ? HARD_FRAME_POINTER_REGNUM
3401 {
3402 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3403 so DFmode for the vector registers is enough. */
3415 /* No more registers to handle after REGNO.
3416 Emit a single save/restore and exit. */
3418 {
3423 else
3426 }
3429 /* The next register is not of the same class or its offset is not
3430 mergeable with the current one into a pair. */
3435 {
3440 else
3445 }
3447 /* REGNO2 can be saved/restored in a pair with REGNO. */
3459 else
3464 {
3467 }
3468 else
3469 {
3472 }
3475 }
3476 }
3478 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3480 static void
3482 {
3484 }
3486 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3488 static void
3490 {
3492 }
3494 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3496 static void
3498 {
3502 }
3504 /* AArch64 stack frames generated by this compiler look like:
3506 +-------------------------------+
3507 | |
3508 | incoming stack arguments |
3509 | |
3510 +-------------------------------+
3511 | | <-- incoming stack pointer (aligned)
3512 | callee-allocated save area |
3513 | for register varargs |
3514 | |
3515 +-------------------------------+
3516 | local variables | <-- frame_pointer_rtx
3517 | |
3518 +-------------------------------+
3519 | padding0 | \
3520 +-------------------------------+ |
3521 | callee-saved registers | | frame.saved_regs_size
3522 +-------------------------------+ |
3523 | LR' | |
3524 +-------------------------------+ |
3525 | FP' | / <- hard_frame_pointer_rtx (aligned)
3526 +-------------------------------+
3527 | dynamic allocation |
3528 +-------------------------------+
3529 | padding |
3530 +-------------------------------+
3531 | outgoing stack arguments | <-- arg_pointer
3532 | |
3533 +-------------------------------+
3534 | | <-- stack_pointer_rtx (aligned)
3536 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3537 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3538 unchanged. */
3540 /* Generate the prologue instructions for entry into a function.
3541 Establish the stack frame by decreasing the stack pointer with a
3542 properly calculated size and, if necessary, create a frame record
3543 filled with the values of LR and previous frame pointer. The
3544 current FP is also set up if it is in use. */
3546 void
3548 {
3560 /* Sign return address for functions. */
3562 {
3566 }
3572 {
3574 {
3578 }
3581 }
3589 {
3594 stack_pointer_rtx,
3598 }
3605 }
3607 /* Return TRUE if we can use a simple_return insn.
3609 This function checks whether the callee saved stack is empty, which
3610 means no restore actions are need. The pro_and_epilogue will use
3611 this to check whether shrink-wrapping opt is feasible. */
3613 bool
3615 {
3625 }
3627 /* Generate the epilogue instructions for returning from a function.
3628 This is almost exactly the reverse of the prolog sequence, except
3629 that we need to insert barriers to avoid scheduling loads that read
3630 from a deallocated stack, and we optimize the unwind records by
3631 emitting them all together if possible. */
3632 void
3634 {
3646 /* We need to add memory barrier to prevent read from deallocated stack. */
3650 /* Emit a barrier to prevent loads from a deallocated stack. */
3653 {
3656 }
3658 /* Restore the stack pointer from the frame pointer if it may not
3659 be the same as the stack pointer. */
3661 {
3663 hard_frame_pointer_rtx,
3665 /* If writeback is used when restoring callee-saves, the CFA
3666 is restored on the instruction doing the writeback. */
3668 }
3669 else
3684 {
3685 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3691 }
3696 {
3697 /* Emit delayed restores and reset the CFA to be SP. */
3702 }
3704 /* We prefer to emit the combined return/authenticate instruction RETAA,
3705 however there are three cases in which we must instead emit an explicit
3706 authentication instruction.
3708 1) Sibcalls don't return in a normal way, so if we're about to call one
3709 we must authenticate.
3711 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
3712 generating code for !TARGET_ARMV8_3 we can't use it and must
3713 explicitly authenticate.
3715 3) On an eh_return path we make extra stack adjustments to update the
3716 canonical frame address to be the exception handler's CFA. We want
3717 to authenticate using the CFA of the function which calls eh_return.
3718 */
3721 {
3725 }
3727 /* Stack adjustment for exception handler. */
3729 {
3730 /* We need to unwind the stack by the offset computed by
3731 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3732 to be SP; letting the CFA move during this adjustment
3733 is just as correct as retaining the CFA from the body
3734 of the function. Therefore, do nothing special. */
3736 }
3741 }
3743 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3744 normally or return to a previous frame after unwinding.
3746 An EH return uses a single shared return sequence. The epilogue is
3747 exactly like a normal epilogue except that it has an extra input
3748 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3749 that must be applied after the frame has been destroyed. An extra label
3750 is inserted before the epilogue which initializes this register to zero,
3751 and this is the entry point for a normal return.
3753 An actual EH return updates the return address, initializes the stack
3754 adjustment and jumps directly into the epilogue (bypassing the zeroing
3755 of the adjustment). Since the return address is typically saved on the
3756 stack when a function makes a call, the saved LR must be updated outside
3757 the epilogue.
3759 This poses problems as the store is generated well before the epilogue,
3760 so the offset of LR is not known yet. Also optimizations will remove the
3761 store as it appears dead, even after the epilogue is generated (as the
3762 base or offset for loading LR is different in many cases).
3764 To avoid these problems this implementation forces the frame pointer
3765 in eh_return functions so that the location of LR is fixed and known early.
3766 It also marks the store volatile, so no optimization is permitted to
3767 remove the store. */
3768 rtx
3770 {
3774 /* Mark the store volatile, so no optimization is permitted to remove it. */
3777 }
3779 /* Output code to add DELTA to the first argument, and then jump
3780 to FUNCTION. Used for C++ multiple inheritance. */
3781 static void
3783 HOST_WIDE_INT delta,
3784 HOST_WIDE_INT vcall_offset,
3785 tree function)
3786 {
3787 /* The this pointer is always in x0. Note that this differs from
3788 Arm where the this pointer maybe bumped to r1 if r0 is required
3789 to return a pointer to an aggregate. On AArch64 a result value
3790 pointer will be in x8. */
3800 else
3801 {
3810 {
3814 else
3816 }
3820 else
3827 else
3828 {
3830 Pmode);
3832 }
3836 else
3842 }
3844 /* Generate a tail call to the target function. */
3846 {
3849 }
3861 /* Stop pretending to be a post-reload pass. */
3863 }
3865 static bool
3867 {
3872 {
3876 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3877 TLS offsets, not real symbol references. */
3880 }
3882 }
3885 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3886 a left shift of 0 or 12 bits. */
3887 bool
3889 {
3892 );
3893 }
3896 /* Return true if val is an immediate that can be loaded into a
3897 register by a MOVZ instruction. */
3898 static bool
3900 {
3902 {
3906 }
3907 else
3908 {
3909 /* Ignore sign extension. */
3911 }
3914 }
3916 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3919 {
3925 };
3928 /* Return true if val is a valid bitmask immediate. */
3930 bool
3932 {
3936 /* Check for a single sequence of one bits and return quickly if so.
3937 The special cases of all ones and all zeroes returns false. */
3944 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3948 /* Invert if the immediate doesn't start with a zero bit - this means we
3949 only need to search for sequences of one bits. */
3953 /* Find the first set bit and set tmp to val with the first sequence of one
3954 bits removed. Return success if there is a single sequence of ones. */
3961 /* Find the next set bit and compute the difference in bit position. */
3966 /* Check the bit position difference is a power of 2, and that the first
3967 sequence of one bits fits within 'bits' bits. */
3971 /* Check the sequence of one bits is repeated 64/bits times. */
3973 }
3975 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
3976 Assumed precondition: VAL_IN Is not zero. */
3978 unsigned HOST_WIDE_INT
3980 {
3987 }
3989 /* Create constant where bits outside of lowest bit set to highest bit set
3990 are set to 1. */
3992 unsigned HOST_WIDE_INT
3994 {
3996 }
3998 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
4000 bool
4002 {
4012 }
4014 /* Return true if val is an immediate that can be loaded into a
4015 register in a single instruction. */
4016 bool
4018 {
4022 }
4024 static bool
4026 {
4034 {
4038 else
4039 /* Avoid generating a 64-bit relocation in ILP32; leave
4040 to aarch64_expand_mov_immediate to handle it properly. */
4042 }
4045 }
4047 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4048 The expansion for a table switch is quite expensive due to the number
4049 of instructions, the table lookup and hard to predict indirect jump.
4050 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4051 set, otherwise use tables for > 16 cases as a tradeoff between size and
4052 performance. When optimizing for size, use the default setting. */
4054 static unsigned int
4056 {
4057 /* Use the specified limit for the number of cases before using jump
4058 tables at higher optimization levels. */
4062 else
4064 }
4066 /* Return true if register REGNO is a valid index register.
4067 STRICT_P is true if REG_OK_STRICT is in effect. */
4069 bool
4071 {
4073 {
4081 }
4083 }
4085 /* Return true if register REGNO is a valid base register for mode MODE.
4086 STRICT_P is true if REG_OK_STRICT is in effect. */
4088 bool
4090 {
4092 {
4100 }
4102 /* The fake registers will be eliminated to either the stack or
4103 hard frame pointer, both of which are usually valid base registers.
4104 Reload deals with the cases where the eliminated form isn't valid. */
4109 }
4111 /* Return true if X is a valid base register for mode MODE.
4112 STRICT_P is true if REG_OK_STRICT is in effect. */
4114 static bool
4116 {
4121 }
4123 /* Return true if address offset is a valid index. If it is, fill in INFO
4124 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4126 static bool
4129 {
4131 rtx index;
4134 /* (reg:P) */
4137 {
4141 }
4142 /* (sign_extend:DI (reg:SI)) */
4147 {
4152 }
4153 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4160 {
4165 }
4166 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4173 {
4178 }
4179 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4186 {
4194 }
4195 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4196 (const_int 0xffffffff<<shift)) */
4203 {
4209 }
4210 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4217 {
4225 }
4226 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4227 (const_int 0xffffffff<<shift)) */
4234 {
4240 }
4241 /* (mult:P (reg:P) (const_int scale)) */
4246 {
4250 }
4251 /* (ashift:P (reg:P) (const_int shift)) */
4256 {
4260 }
4261 else
4272 {
4277 }
4280 }
4282 /* Return true if MODE is one of the modes for which we
4283 support LDP/STP operations. */
4285 static bool
4287 {
4292 }
4294 /* Return true if REGNO is a virtual pointer register, or an eliminable
4295 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4296 include stack_pointer or hard_frame_pointer. */
4297 static bool
4299 {
4304 }
4306 /* Return true if X is a valid address for machine mode MODE. If it is,
4307 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4308 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4310 static bool
4314 {
4318 /* On BE, we use load/store pair for all large int mode load/stores.
4319 TI/TFmode may also use a load/store pair. */
4323 || (BYTES_BIG_ENDIAN
4327 !load_store_pair_p
4331 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4332 REG addressing. */
4338 {
4354 {
4360 }
4365 {
4372 /* TImode and TFmode values are allowed in both pairs of X
4373 registers and individual Q registers. The available
4374 address modes are:
4375 X,X: 7-bit signed scaled offset
4376 Q: 9-bit signed offset
4377 We conservatively require an offset representable in either mode.
4378 When performing the check for pairs of X registers i.e. LDP/STP
4379 pass down DImode since that is the natural size of the LDP/STP
4380 instruction memory accesses. */
4386 /* A 7bit offset check because OImode will emit a ldp/stp
4387 instruction (only big endian will get here).
4388 For ldp/stp instructions, the offset is scaled for the size of a
4389 single element of the pair. */
4393 /* Three 9/12 bit offsets checks because CImode will emit three
4394 ldr/str instructions (only big endian will get here). */
4401 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4402 instructions (only big endian will get here). */
4411 else
4414 }
4417 {
4418 /* Look for base + (scaled/extended) index register. */
4421 {
4424 }
4427 {
4430 }
4431 }
4452 {
4453 HOST_WIDE_INT offset;
4457 /* TImode and TFmode values are allowed in both pairs of X
4458 registers and individual Q registers. The available
4459 address modes are:
4460 X,X: 7-bit signed scaled offset
4461 Q: 9-bit signed offset
4462 We conservatively require an offset representable in either mode.
4463 */
4471 else
4473 }
4479 /* load literal: pc-relative constant pool entry. Only supported
4480 for SI mode or larger. */
4484 {
4492 }
4501 {
4506 {
4507 /* The symbol and offset must be aligned to the access size. */
4514 {
4518 }
4524 else
4533 }
4534 }
4539 }
4540 }
4542 bool
4544 {
4545 rtx offset;
4549 }
4551 /* Classify the base of symbolic expression X. */
4553 enum aarch64_symbol_type
4555 {
4556 rtx offset;
4560 }
4563 /* Return TRUE if X is a legitimate address for accessing memory in
4564 mode MODE. */
4565 static bool
4567 {
4571 }
4573 /* Return TRUE if X is a legitimate address for accessing memory in
4574 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4575 pair operation. */
4576 bool
4579 {
4583 }
4585 /* Split an out-of-range address displacement into a base and offset.
4586 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4587 to increase opportunities for sharing the base address of different sizes.
4588 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4589 static bool
4591 {
4602 }
4604 /* Return TRUE if rtx X is immediate constant 0.0 */
4605 bool
4607 {
4614 }
4616 /* Return the fixed registers used for condition codes. */
4618 static bool
4620 {
4624 }
4626 /* Emit call insn with PAT and do aarch64-specific handling. */
4628 void
4630 {
4636 }
4638 machine_mode
4640 {
4641 /* All floating point compares return CCFP if it is an equality
4642 comparison, and CCFPE otherwise. */
4644 {
4646 {
4667 }
4668 }
4670 /* Equality comparisons of short modes against zero can be performed
4671 using the TST instruction with the appropriate bitmask. */
4677 /* Similarly, comparisons of zero_extends from shorter modes can
4678 be performed using an ANDS with an immediate mask. */
4694 /* A compare with a shifted operand. Because of canonicalization,
4695 the comparison will have to be swapped when we emit the assembly
4696 code. */
4704 /* Similarly for a negated operand, but we can only do this for
4705 equalities. */
4712 /* A test for unsigned overflow. */
4719 /* For everything else, return CCmode. */
4721 }
4723 static int
4726 int
4728 {
4735 }
4737 static int
4739 {
4741 {
4745 {
4759 }
4764 {
4776 }
4781 {
4793 }
4798 {
4804 }
4809 {
4813 }
4818 {
4822 }
4827 }
4830 }
4832 bool
4834 HOST_WIDE_INT minval,
4835 HOST_WIDE_INT maxval)
4836 {
4837 HOST_WIDE_INT firstval;
4854 }
4856 bool
4858 {
4860 }
4863 /* N Z C V. */
4864 #define AARCH64_CC_V 1
4865 #define AARCH64_CC_C (1 << 1)
4866 #define AARCH64_CC_Z (1 << 2)
4867 #define AARCH64_CC_N (1 << 3)
4869 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
4871 {
4888 };
4890 static void
4892 {
4894 {
4895 /* An integer or symbol address without a preceding # sign. */
4898 {
4910 {
4913 }
4914 /* Fall through. */
4918 }
4922 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4923 {
4928 {
4931 }
4934 {
4947 }
4948 }
4952 {
4955 /* Print N such that 2^N == X. */
4957 {
4960 }
4963 }
4967 /* Print the number of non-zero bits in X (a const_int). */
4969 {
4972 }
4978 /* Print the higher numbered register of a pair (TImode) of regs. */
4980 {
4983 }
4990 {
4992 /* Print a condition (eq, ne, etc) or its inverse. */
4994 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
4996 {
5000 }
5003 {
5006 }
5013 }
5021 /* Print a scalar FP/SIMD register name. */
5023 {
5024 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5026 }
5034 /* Print the first FP/SIMD register name in a list. */
5036 {
5037 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5039 }
5044 /* Print a scalar FP/SIMD register name + 1. */
5046 {
5047 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5049 }
5054 /* Print bottom 16 bits of integer constant in hex. */
5056 {
5059 }
5065 /* Print a general register name or the zero register (32-bit or
5066 64-bit). */
5069 {
5072 }
5075 {
5078 }
5081 {
5084 }
5086 /* Fall through */
5089 /* Print a normal operand, if it's a general register, then we
5090 assume DImode. */
5092 {
5095 }
5098 {
5119 {
5122 HOST_WIDE_INT_MIN,
5123 HOST_WIDE_INT_MAX));
5125 }
5127 {
5129 }
5130 else
5135 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5136 be getting CONST_DOUBLEs holding integers. */
5139 {
5142 }
5144 {
5145 #define buf_size 20
5153 #undef buf_size
5154 }
5160 }
5168 {
5195 }
5201 {
5236 }
5243 {
5249 }
5254 {
5255 HOST_WIDE_INT cond_code;
5256 /* Print nzcv. */
5259 {
5262 }
5267 }
5273 }
5274 }
5276 static void
5278 {
5283 {
5287 else
5296 else
5305 else
5314 else
5321 {
5348 }
5359 }
5362 }
5364 bool
5366 {
5373 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5374 referencing instruction, but they are constant offsets, not
5375 symbols. */
5381 {
5383 {
5389 }
5392 }
5395 }
5397 /* Implement REGNO_REG_CLASS. */
5399 enum reg_class
5401 {
5416 }
5418 static rtx
5420 {
5421 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5422 where mask is selected by alignment and size of the offset.
5423 We try to pick as large a range for the offset as possible to
5424 maximize the chance of a CSE. However, for aligned addresses
5425 we limit the range to 4k so that structures with different sized
5426 elements are likely to use the same base. We need to be careful
5427 not to split a CONST for some forms of address expression, otherwise
5428 it will generate sub-optimal code. */
5431 {
5437 {
5441 /* Force any scaling into a temp for CSE. */
5445 /* Let the pointer register be in op0. */
5449 /* If the pointer is virtual or frame related, then we know that
5450 virtual register instantiation or register elimination is going
5451 to apply a second constant. We want the two constants folded
5452 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5454 {
5458 }
5460 /* Otherwise, in order to encourage CSE (and thence loop strength
5461 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5465 }
5467 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5468 HOST_WIDE_INT base_offset;
5471 /* For offsets aren't a multiple of the access size, the limit is
5472 -256...255. */
5474 {
5477 /* BLKmode typically uses LDP of X-registers. */
5480 }
5481 /* Small negative offsets are supported. */
5486 /* Use 12-bit offset by access size. */
5487 else
5491 {
5495 }
5496 }
5499 }
5501 /* Return the reload icode required for a constant pool in mode. */
5502 static enum insn_code
5504 {
5506 {
5542 }
5545 }
5546 static reg_class_t
5548 reg_class_t rclass,
5549 machine_mode mode,
5551 {
5553 /* If we have to disable direct literal pool loads and stores because the
5554 function is too big, then we need a scratch register. */
5559 {
5562 }
5564 /* Without the TARGET_SIMD instructions we cannot move a Q register
5565 to a Q register directly. We need a scratch. */
5569 {
5575 }
5577 /* A TFmode or TImode memory access should be handled via an FP_REGS
5578 because AArch64 has richer addressing modes for LDR/STR instructions
5579 than LDP/STP instructions. */
5588 }
5590 static bool
5592 {
5593 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5594 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5597 {
5609 }
5610 else
5611 {
5612 /* If we decided that we didn't need a leaf frame pointer but then used
5613 LR in the function, then we'll want a frame pointer after all, so
5614 prevent this elimination to ensure a frame pointer is used. */
5616 && flag_omit_leaf_frame_pointer
5619 }
5622 }
5624 HOST_WIDE_INT
5626 {
5630 {
5637 }
5640 {
5644 }
5647 }
5649 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5650 previous frame. */
5652 rtx
5654 {
5658 }
5661 static void
5663 {
5665 {
5668 }
5669 else
5670 {
5673 }
5678 }
5680 static void
5682 {
5686 /* Don't need to copy the trailing D-words, we fill those in below. */
5698 /* XXX We should really define a "clear_cache" pattern and use
5699 gen_clear_cache(). */
5704 ptr_mode);
5705 }
5707 static unsigned char
5709 {
5711 {
5718 return
5730 }
5732 }
5734 static reg_class_t
5736 {
5741 {
5747 }
5749 /* If it's an integer immediate that MOVI can't handle, then
5750 FP_REGS is not an option, so we return NO_REGS instead. */
5755 /* Register eliminiation can result in a request for
5756 SP+constant->FP_REGS. We cannot support such operations which
5757 use SP as source and an FP_REG as destination, so reject out
5758 right now. */
5760 {
5763 /* Look through a possible SUBREG introduced by ILP32. */
5769 POINTER_REGS));
5771 }
5774 }
5776 void
5778 {
5780 }
5782 static void
5784 {
5787 else
5788 {
5790 /* While priority is known to be in range [0, 65535], so 18 bytes
5791 would be enough, the compiler might not know that. To avoid
5792 -Wformat-truncation false positive, use a larger size. */
5799 }
5800 }
5802 static void
5804 {
5807 else
5808 {
5810 /* While priority is known to be in range [0, 65535], so 18 bytes
5811 would be enough, the compiler might not know that. To avoid
5812 -Wformat-truncation false positive, use a larger size. */
5819 }
5820 }
5824 {
5830 {
5831 {
5834 },
5835 {
5838 },
5839 {
5842 },
5843 /* We assume that DImode is only generated when not optimizing and
5844 that we don't really need 64-bit address offsets. That would
5845 imply an object file with 8GB of code in a single function! */
5846 {
5849 }
5850 };
5858 /* Need to implement table size reduction, by chaning the code below. */
5868 }
5871 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5872 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5873 operator. */
5875 int
5877 {
5879 {
5882 {
5886 }
5887 }
5889 }
5891 /* Constant pools are per function only when PC relative
5892 literal loads are true or we are in the large memory
5893 model. */
5897 {
5900 }
5902 static bool
5904 {
5905 /* Fixme:: In an ideal world this would work similar
5906 to the logic in aarch64_select_rtx_section but this
5907 breaks bootstrap in gcc go. For now we workaround
5908 this by returning false here. */
5910 }
5912 /* Select appropriate section for constants depending
5913 on where we place literal pools. */
5917 rtx x,
5919 {
5924 }
5926 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
5927 void
5929 HOST_WIDE_INT offset)
5930 {
5931 /* When using per-function literal pools, we must ensure that any code
5932 section is aligned to the minimal instruction length, lest we get
5933 errors from the assembler re "unaligned instructions". */
5936 }
5938 /* Costs. */
5940 /* Helper function for rtx cost calculation. Strip a shift expression
5941 from X. Returns the inner operand if successful, or the original
5942 expression on failure. */
5943 static rtx
5945 {
5948 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5949 we can convert both to ROR during final output. */
5964 }
5966 /* Helper function for rtx cost calculation. Strip an extend
5967 expression from X. Returns the inner operand if successful, or the
5968 original expression on failure. We deal with a number of possible
5969 canonicalization variations here. */
5970 static rtx
5972 {
5975 /* Zero and sign extraction of a widened value. */
5983 /* It can also be represented (for zero-extend) as an AND with an
5984 immediate. */
5993 /* Now handle extended register, as this may also have an optional
5994 left shift by 1..4. */
6008 }
6010 /* Return true iff CODE is a shift supported in combination
6011 with arithmetic instructions. */
6013 static bool
6015 {
6017 }
6019 /* Helper function for rtx cost calculation. Calculate the cost of
6020 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
6021 Return the calculated cost of the expression, recursing manually in to
6022 operands where needed. */
6024 static int
6026 {
6042 /* Integer multiply/fma. */
6044 {
6045 /* The multiply will be canonicalized as a shift, cost it as such. */
6049 {
6053 {
6055 {
6057 /* ARITH + shift-by-register. */
6060 /* ARITH + extended register. We don't have a cost field
6061 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6063 else
6064 /* ARITH + shift-by-immediate. */
6066 }
6067 else
6068 /* LSL (immediate). */
6071 }
6072 /* Strip extends as we will have costed them in the case above. */
6079 }
6081 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6082 compound and let the below cases handle it. After all, MNEG is a
6083 special-case alias of MSUB. */
6085 {
6088 }
6090 /* Integer multiplies or FMAs have zero/sign extending variants. */
6095 {
6100 {
6102 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6104 else
6105 /* MUL/SMULL/UMULL. */
6107 }
6110 }
6112 /* This is either an integer multiply or a MADD. In both cases
6113 we want to recurse and cost the operands. */
6118 {
6120 /* MADD/MSUB. */
6122 else
6123 /* MUL. */
6125 }
6128 }
6129 else
6130 {
6132 {
6133 /* Floating-point FMA/FMUL can also support negations of the
6134 operands, unless the rounding mode is upward or downward in
6135 which case FNMUL is different than FMUL with operand negation. */
6139 {
6144 }
6147 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6149 else
6150 /* FMUL/FNMUL. */
6152 }
6157 }
6158 }
6160 static int
6162 machine_mode mode,
6163 addr_space_t as ATTRIBUTE_UNUSED,
6165 {
6173 {
6175 {
6176 /* This is a CONST or SYMBOL ref which will be split
6177 in a different way depending on the code model in use.
6178 Cost it through the generic infrastructure. */
6180 /* Divide through by the cost of one instruction to
6181 bring it to the same units as the address costs. */
6183 /* The cost is then the cost of preparing the address,
6184 followed by an immediate (possibly 0) offset. */
6186 }
6187 else
6188 {
6189 /* This is most likely a jump table from a case
6190 statement. */
6192 }
6193 }
6196 {
6208 else
6227 }
6231 {
6232 /* For the sake of calculating the cost of the shifted register
6233 component, we can treat same sized modes in the same way. */
6235 {
6248 /* We can't tell, or this is a 128-bit vector. */
6252 }
6253 }
6256 }
6258 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6259 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6260 to be taken. */
6262 int
6264 {
6265 /* When optimizing for speed, use the cost of unpredictable branches. */
6271 else
6273 }
6275 /* Return true if the RTX X in mode MODE is a zero or sign extract
6276 usable in an ADD or SUB (extended register) instruction. */
6277 static bool
6279 {
6280 /* Catch add with a sign extract.
6281 This is add_<optab><mode>_multp2. */
6284 {
6295 op1))
6296 {
6298 }
6299 }
6300 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6301 No shift. */
6307 }
6309 static bool
6311 {
6313 {
6325 }
6326 }
6328 /* Return true iff X is an rtx that will match an extr instruction
6329 i.e. as described in the *extr<mode>5_insn family of patterns.
6330 OP0 and OP1 will be set to the operands of the shifts involved
6331 on success and will be NULL_RTX otherwise. */
6333 static bool
6335 {
6350 {
6351 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6363 {
6367 }
6368 }
6371 }
6373 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6374 storing it in *COST. Result is true if the total cost of the operation
6375 has now been calculated. */
6376 static bool
6378 {
6379 rtx inner;
6380 rtx comparator;
6384 {
6388 }
6389 else
6390 {
6394 }
6397 {
6398 /* Conditional branch. */
6401 else
6402 {
6404 {
6406 {
6407 /* TBZ/TBNZ/CBZ/CBNZ. */
6409 /* TBZ/TBNZ. */
6412 else
6413 /* CBZ/CBNZ. */
6417 }
6418 }
6420 {
6421 /* TBZ/TBNZ. */
6424 }
6425 }
6426 }
6428 {
6429 /* CCMP. */
6431 {
6432 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6436 {
6443 else
6445 }
6447 }
6449 /* It's a conditional operation based on the status flags,
6450 so it must be some flavor of CSEL. */
6452 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6458 {
6459 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6462 }
6467 }
6469 /* We don't know what this is, cost all operands. */
6471 }
6473 /* Check whether X is a bitfield operation of the form shift + extend that
6474 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6475 operand to which the bitfield operation is applied. Otherwise return
6476 NULL_RTX. */
6478 static rtx
6480 {
6494 {
6512 }
6515 }
6517 /* Return true if the mask and a shift amount from an RTX of the form
6518 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6519 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6521 bool
6523 {
6528 }
6530 /* Calculate the cost of calculating X, storing it in *COST. Result
6531 is true if the total cost of the operation has now been calculated. */
6532 static bool
6535 {
6541 /* By default, assume that everything has equivalent cost to the
6542 cheapest instruction. Any additional costs are applied as a delta
6543 above this default. */
6547 {
6549 /* The cost depends entirely on the operands to SET. */
6555 {
6558 {
6572 }
6581 /* Fall through. */
6583 /* The cost is one per vector-register copied. */
6585 {
6589 }
6590 /* const0_rtx is in general free, but we will use an
6591 instruction to set a register to 0. */
6593 {
6594 /* The cost is 1 per register copied. */
6598 }
6599 else
6600 /* Cost is just the cost of the RHS of the set. */
6606 /* Bit-field insertion. Strip any redundant widening of
6607 the RHS to meet the width of the target. */
6618 {
6619 /* MOV immediate is assumed to always be cheap. */
6621 }
6622 else
6623 {
6624 /* BFM. */
6628 }
6633 /* We can't make sense of this, assume default cost. */
6636 }
6640 /* If an instruction can incorporate a constant within the
6641 instruction, the instruction's expression avoids calling
6642 rtx_cost() on the constant. If rtx_cost() is called on a
6643 constant, then it is usually because the constant must be
6644 moved into a register by one or more instructions.
6646 The exception is constant 0, which can be expressed
6647 as XZR/WZR and is therefore free. The exception to this is
6648 if we have (set (reg) (const0_rtx)) in which case we must cost
6649 the move. However, we can catch that when we cost the SET, so
6650 we don't need to consider that here. */
6653 else
6654 {
6655 /* To an approximation, building any other constant is
6656 proportionally expensive to the number of instructions
6657 required to build that constant. This is true whether we
6658 are compiling for SPEED or otherwise. */
6661 }
6666 {
6667 /* mov[df,sf]_aarch64. */
6669 /* FMOV (scalar immediate). */
6672 {
6673 /* This will be a load from memory. */
6676 else
6678 }
6679 else
6680 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6681 or MOV v0.s[0], wzr - neither of which are modeled by the
6682 cost tables. Just use the default cost. */
6683 {
6684 }
6685 }
6691 {
6692 /* For loads we want the base cost of a load, plus an
6693 approximation for the additional cost of the addressing
6694 mode. */
6708 }
6716 {
6718 {
6719 /* FNEG. */
6721 }
6723 }
6726 {
6729 {
6730 /* CSETM. */
6733 }
6735 /* Cost this as SUB wzr, X. */
6739 }
6742 {
6743 /* Support (neg(fma...)) as a single instruction only if
6744 sign of zeros is unimportant. This matches the decision
6745 making in aarch64.md. */
6747 {
6748 /* FNMADD. */
6751 }
6753 {
6754 /* FNMUL. */
6757 }
6759 /* FNEG. */
6762 }
6769 {
6772 else
6774 }
6784 {
6788 }
6791 {
6792 /* TODO: A write to the CC flags possibly costs extra, this
6793 needs encoding in the cost tables. */
6796 /* ANDS. */
6798 {
6801 }
6804 {
6805 /* ADDS (and CMN alias). */
6808 }
6811 {
6812 /* SUBS. */
6815 }
6820 {
6821 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6822 Handle it here directly rather than going to cost_logic
6823 since we know the immediate generated for the TST is valid
6824 so we can avoid creating an intermediate rtx for it only
6825 for costing purposes. */
6832 }
6835 {
6836 /* CMN. */
6843 }
6845 /* CMP.
6847 Compare can freely swap the order of operands, and
6848 canonicalization puts the more complex operation first.
6849 But the integer MINUS logic expects the shift/extend
6850 operation in op1. */
6853 {
6856 }
6858 }
6861 {
6862 /* FCMP. */
6867 {
6869 /* FCMP supports constant 0.0 for no extra cost. */
6871 }
6873 }
6876 {
6877 /* Vector compare. */
6882 {
6883 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6884 cost. */
6886 }
6888 }
6892 {
6896 cost_minus:
6899 /* Detect valid immediates. */
6905 {
6907 /* SUB(S) (immediate). */
6910 }
6912 /* Look for SUB (extended register). */
6914 {
6922 }
6926 /* Cost this as an FMA-alike operation. */
6930 {
6933 speed);
6935 }
6940 {
6942 {
6943 /* Vector SUB. */
6945 }
6947 {
6948 /* SUB(S). */
6950 }
6952 {
6953 /* FSUB. */
6955 }
6956 }
6958 }
6961 {
6962 rtx new_op0;
6967 cost_plus:
6970 {
6971 /* CSINC. */
6975 }
6980 {
6984 /* ADD (immediate). */
6987 }
6991 /* Look for ADD (extended register). */
6993 {
7001 }
7003 /* Strip any extend, leave shifts behind as we will
7004 cost them through mult_cost. */
7009 {
7011 speed);
7013 }
7018 {
7020 {
7021 /* Vector ADD. */
7023 }
7025 {
7026 /* ADD. */
7028 }
7030 {
7031 /* FADD. */
7033 }
7034 }
7036 }
7042 {
7045 else
7047 }
7052 {
7056 {
7059 else
7061 }
7063 }
7066 {
7073 }
7074 /* Fall through. */
7077 cost_logic:
7082 {
7086 }
7094 {
7095 /* This is a UBFM/SBFM. */
7100 }
7103 {
7105 {
7106 /* We have a mask + shift version of a UBFIZ
7107 i.e. the *andim_ashift<mode>_bfiz pattern. */
7111 {
7118 }
7120 {
7121 /* We possibly get the immediate for free, this is not
7122 modelled. */
7128 }
7129 }
7130 else
7131 {
7134 /* Handle ORN, EON, or BIC. */
7140 /* If we had a shift on op0 then this is a logical-shift-
7141 by-register/immediate operation. Otherwise, this is just
7142 a logical operation. */
7144 {
7146 {
7147 /* Shift by immediate. */
7150 else
7152 }
7153 else
7155 }
7157 /* In both cases we want to cost both operands. */
7162 }
7163 }
7171 {
7172 /* Vector NOT. */
7175 }
7177 /* MVN-shifted-reg. */
7179 {
7186 }
7187 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7188 Handle the second form here taking care that 'a' in the above can
7189 be a shift. */
7191 {
7200 {
7203 else
7205 }
7208 }
7209 /* MVN. */
7218 /* If a value is written in SI mode, then zero extended to DI
7219 mode, the operation will in general be free as a write to
7220 a 'w' register implicitly zeroes the upper bits of an 'x'
7221 register. However, if this is
7223 (set (reg) (zero_extend (reg)))
7225 we must cost the explicit register move. */
7229 {
7232 /* If OP_COST is non-zero, then the cost of the zero extend
7233 is effectively the cost of the inner operation. Otherwise
7234 we have a MOV instruction and we take the cost from the MOV
7235 itself. This is true independently of whether we are
7236 optimizing for space or time. */
7241 }
7243 {
7244 /* All loads can zero extend to any size for free. */
7247 }
7251 {
7256 }
7259 {
7261 {
7262 /* UMOV. */
7264 }
7265 else
7266 {
7267 /* We generate an AND instead of UXTB/UXTH. */
7269 }
7270 }
7275 {
7276 /* LDRSH. */
7278 {
7285 }
7287 }
7291 {
7296 }
7299 {
7302 else
7304 }
7312 {
7314 {
7316 {
7317 /* Vector shift (immediate). */
7319 }
7320 else
7321 {
7322 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7323 aliases. */
7325 }
7326 }
7328 /* We can incorporate zero/sign extend for free. */
7335 }
7336 else
7337 {
7339 {
7341 {
7342 /* Vector shift (register). */
7344 }
7345 else
7346 {
7347 /* LSLV. */
7349 }
7350 }
7352 }
7362 {
7363 /* ASR (immediate) and friends. */
7365 {
7368 else
7370 }
7374 }
7375 else
7376 {
7378 /* ASR (register) and friends. */
7380 {
7383 else
7385 }
7387 }
7393 {
7394 /* LDR. */
7397 }
7400 {
7401 /* ADRP, followed by ADD. */
7405 }
7408 {
7409 /* ADR. */
7412 }
7415 {
7416 /* One extra load instruction, after accessing the GOT. */
7420 }
7425 /* ADRP/ADD (immediate). */
7432 /* UBFX/SBFX. */
7434 {
7437 else
7439 }
7441 /* We can trust that the immediates used will be correct (there
7442 are no by-register forms), so we need only cost op0. */
7448 /* aarch64_rtx_mult_cost always handles recursion to its
7449 operands. */
7453 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7454 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7455 an unconditional negate. This case should only ever be reached through
7456 the set_smod_pow2_cheap check in expmed.c. */
7460 {
7461 /* We expand to 4 instructions. Reset the baseline. */
7469 }
7471 /* Fall-through. */
7474 {
7486 }
7493 {
7497 /* There is no integer SQRT, so only DIV and UDIV can get
7498 here. */
7500 else
7502 }
7528 {
7531 else
7533 }
7535 /* FMSUB, FNMADD, and FNMSUB are free. */
7542 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7543 and the by-element operand as operand 0. */
7547 /* Catch vector-by-element operations. The by-element operand can
7548 either be (vec_duplicate (vec_select (x))) or just
7549 (vec_select (x)), depending on whether we are multiplying by
7550 a vector or a scalar.
7552 Canonicalization is not very good in these cases, FMA4 will put the
7553 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7564 /* If the remaining parameters are not registers,
7565 get the cost to put them into registers. */
7579 {
7581 {
7582 /*Vector truncate. */
7584 }
7585 else
7587 }
7592 {
7594 {
7595 /*Vector conversion. */
7597 }
7598 else
7600 }
7606 /* Strip the rounding part. They will all be implemented
7607 by the fcvt* family of instructions anyway. */
7609 {
7618 }
7621 {
7624 else
7626 }
7628 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7629 fixed-point fcvt. */
7634 {
7638 }
7645 {
7646 /* ABS (vector). */
7649 }
7651 {
7654 /* FABD, which is analogous to FADD. */
7656 {
7663 }
7664 /* Simple FABS is analogous to FNEG. */
7667 }
7668 else
7669 {
7670 /* Integer ABS will either be split to
7671 two arithmetic instructions, or will be an ABS
7672 (scalar), which we don't model. */
7676 }
7682 {
7685 else
7686 {
7687 /* FMAXNM/FMINNM/FMAX/FMIN.
7688 TODO: This may not be accurate for all implementations, but
7689 we do not model this in the cost tables. */
7691 }
7692 }
7696 /* The floating point round to integer frint* instructions. */
7698 {
7703 }
7706 {
7711 }
7716 /* Decompose <su>muldi3_highpart. */
7718 mode == DImode
7719 /* (lshiftrt:TI */
7722 /* (mult:TI */
7724 /* (ANY_EXTEND:TI (reg:DI))
7725 (ANY_EXTEND:TI (reg:DI))) */
7732 /* (const_int 64) */
7735 {
7736 /* UMULH/SMULH. */
7744 }
7746 /* Fall through. */
7749 }
7757 }
7759 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7760 calculated for X. This cost is stored in *COST. Returns true
7761 if the total cost of X was calculated. */
7762 static bool
7765 {
7770 {
7775 }
7778 }
7780 static int
7783 {
7789 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7796 /* Moving between GPR and stack cost is the same as GP2GP. */
7801 /* To/From the stack register, we move via the gprs. */
7807 {
7808 /* 128-bit operations on general registers require 2 instructions. */
7816 /* When AdvSIMD instructions are disabled it is not possible to move
7817 a 128-bit value directly between Q registers. This is handled in
7818 secondary reload. A general register is used as a scratch to move
7819 the upper DI value and the lower DI value is moved directly,
7820 hence the cost is the sum of three moves. */
7825 }
7835 }
7837 static int
7839 reg_class_t rclass ATTRIBUTE_UNUSED,
7841 {
7843 }
7845 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
7846 to optimize 1.0/sqrt. */
7848 static bool
7850 {
7852 && flag_unsafe_math_optimizations
7856 }
7858 /* Function to decide when to use the approximate reciprocal square root
7859 builtin. */
7861 static tree
7863 {
7869 }
7873 /* Select reciprocal square root initial estimate insn depending on machine
7874 mode. */
7876 static rsqrte_type
7878 {
7880 {
7887 }
7888 }
7892 /* Select reciprocal square root series step insn depending on machine mode. */
7894 static rsqrts_type
7896 {
7898 {
7905 }
7906 }
7908 /* Emit instruction sequence to compute either the approximate square root
7909 or its approximate reciprocal, depending on the flag RECP, and return
7910 whether the sequence was emitted or not. */
7912 bool
7914 {
7920 machine_mode mmsk = mode_for_vector
7924 && (flag_mlow_precision_sqrt
7928 && (flag_mrecip_low_precision_sqrt
7933 || flag_trapping_math
7934 || !flag_unsafe_math_optimizations
7941 /* When calculating the approximate square root, compare the argument with
7942 0.0 and create a mask. */
7946 /* Estimate the approximate reciprocal square root. */
7950 /* Iterate over the series twice for SF and thrice for DF. */
7953 /* Optionally iterate over the series once less for faster performance
7954 while sacrificing the accuracy. */
7957 iterations--;
7959 /* Iterate over the series to calculate the approximate reciprocal square
7960 root. */
7963 {
7971 }
7974 {
7975 /* Qualify the approximate reciprocal square root when the argument is
7976 0.0 by squashing the intermediary result to 0.0. */
7982 /* Calculate the approximate square root. */
7984 }
7986 /* Finalize the approximation. */
7990 }
7994 /* Select reciprocal initial estimate insn depending on machine mode. */
7996 static recpe_type
7998 {
8000 {
8007 }
8008 }
8012 /* Select reciprocal series step insn depending on machine mode. */
8014 static recps_type
8016 {
8018 {
8025 }
8026 }
8028 /* Emit the instruction sequence to compute the approximation for the division
8029 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
8031 bool
8033 {
8044 || flag_trapping_math
8045 || !flag_unsafe_math_optimizations
8050 /* Estimate the approximate reciprocal. */
8054 /* Iterate over the series twice for SF and thrice for DF. */
8057 /* Optionally iterate over the series once less for faster performance,
8058 while sacrificing the accuracy. */
8060 iterations--;
8062 /* Iterate over the series to calculate the approximate reciprocal. */
8065 {
8070 }
8073 {
8074 /* As the approximate reciprocal of DEN is already calculated, only
8075 calculate the approximate division when NUM is not 1.0. */
8078 }
8080 /* Finalize the approximation. */
8083 }
8085 /* Return the number of instructions that can be issued per cycle. */
8086 static int
8088 {
8090 }
8092 static int
8094 {
8098 }
8101 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8102 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8103 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8105 static int
8108 {
8110 }
8113 /* Vectorizer cost model target hooks. */
8115 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8116 static int
8118 tree vectype,
8120 {
8124 {
8173 }
8174 }
8176 /* Implement targetm.vectorize.add_stmt_cost. */
8177 static unsigned
8181 {
8186 {
8191 /* Statements in an inner loop relative to the loop being
8192 vectorized are weighted more heavily. The value here is
8193 arbitrary and could potentially be improved with analysis. */
8199 }
8202 }
8206 /* Parse the TO_PARSE string and put the architecture struct that it
8207 selects into RES and the architectural features into ISA_FLAGS.
8208 Return an aarch64_parse_opt_result describing the parse result.
8209 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8211 static enum aarch64_parse_opt_result
8214 {
8226 else
8233 /* Loop through the list of supported ARCHes to find a match. */
8235 {
8237 {
8241 {
8242 /* TO_PARSE string contains at least one extension. */
8243 enum aarch64_parse_opt_result ext_res
8248 }
8249 /* Extension parsing was successful. Confirm the result
8250 arch and ISA flags. */
8254 }
8255 }
8257 /* ARCH name not found in list. */
8259 }
8261 /* Parse the TO_PARSE string and put the result tuning in RES and the
8262 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8263 describing the parse result. If there is an error parsing, RES and
8264 ISA_FLAGS are left unchanged. */
8266 static enum aarch64_parse_opt_result
8269 {
8281 else
8288 /* Loop through the list of supported CPUs to find a match. */
8290 {
8292 {
8297 {
8298 /* TO_PARSE string contains at least one extension. */
8299 enum aarch64_parse_opt_result ext_res
8304 }
8305 /* Extension parsing was successfull. Confirm the result
8306 cpu and ISA flags. */
8310 }
8311 }
8313 /* CPU name not found in list. */
8315 }
8317 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8318 Return an aarch64_parse_opt_result describing the parse result.
8319 If the parsing fails the RES does not change. */
8321 static enum aarch64_parse_opt_result
8323 {
8329 /* Loop through the list of supported CPUs to find a match. */
8331 {
8333 {
8336 }
8337 }
8339 /* CPU name not found in list. */
8341 }
8343 /* Parse TOKEN, which has length LENGTH to see if it is an option
8344 described in FLAG. If it is, return the index bit for that fusion type.
8345 If not, error (printing OPTION_NAME) and return zero. */
8347 static unsigned int
8352 {
8354 {
8358 }
8362 }
8364 /* Parse OPTION which is a comma-separated list of flags to enable.
8365 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8366 default state we inherit from the CPU tuning structures. OPTION_NAME
8367 gives the top-level option we are parsing in the -moverride string,
8368 for use in error messages. */
8370 static unsigned int
8375 {
8382 {
8385 token_length,
8386 flags,
8387 option_name);
8388 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8389 in the token stream, reset the supported operations. So:
8391 adrp+add.cmp+branch.none.adrp+add
8393 would have the result of turning on only adrp+add fusion. */
8399 }
8401 /* We ended with a comma, print something. */
8403 {
8406 }
8408 /* We still have one more token to parse. */
8411 token_length,
8412 flags,
8413 option_name);
8419 }
8421 /* Support for overriding instruction fusion. */
8423 static void
8426 {
8428 aarch64_fusible_pairs,
8431 }
8433 /* Support for overriding other tuning flags. */
8435 static void
8438 {
8439 tune->extra_tuning_flags
8441 aarch64_tuning_flags,
8444 }
8446 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8447 we understand. If it is, extract the option string and handoff to
8448 the appropriate function. */
8450 void
8454 {
8460 {
8463 }
8465 /* Get the length of the option name. */
8467 /* Skip the '=' to get to the option string. */
8468 option_part++;
8471 {
8473 {
8476 }
8477 }
8481 }
8483 /* A checking mechanism for the implementation of the tls size. */
8485 static void
8487 {
8492 {
8494 /* Both the default and maximum TLS size allowed under tiny is 1M which
8495 needs two instructions to address, so we clamp the size to 24. */
8500 /* The maximum TLS size allowed under small is 4G. */
8505 /* The maximum TLS size allowed under large is 16E.
8506 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8512 }
8515 }
8517 /* Parse STRING looking for options in the format:
8518 string :: option:string
8519 option :: name=substring
8520 name :: {a-z}
8521 substring :: defined by option. */
8523 static void
8526 {
8537 {
8539 /* Make this substring look like a string. */
8543 }
8545 /* One last option to parse. */
8548 }
8551 static void
8553 {
8554 /* The logic here is that if we are disabling all frame pointer generation
8555 then we do not need to disable leaf frame pointer generation as a
8556 separate operation. But if we are *only* disabling leaf frame pointer
8557 generation then we set flag_omit_frame_pointer to true, but in
8558 aarch64_frame_pointer_required we return false only for leaf functions.
8560 PR 70044: We have to be careful about being called multiple times for the
8561 same function. Once we have decided to set flag_omit_frame_pointer just
8562 so that we can omit leaf frame pointers, we must then not interpret a
8563 second call as meaning that all frame pointer generation should be
8564 omitted. We do this by setting flag_omit_frame_pointer to a special,
8565 non-zero value. */
8574 /* If not optimizing for size, set the default
8575 alignment to what the target wants. */
8577 {
8584 }
8586 /* We default to no pc-relative literal loads. */
8590 /* If -mpc-relative-literal-loads is set on the command line, this
8591 implies that the user asked for PC relative literal loads. */
8595 /* This is PR70113. When building the Linux kernel with
8596 CONFIG_ARM64_ERRATUM_843419, support for relocations
8597 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8598 removed from the kernel to avoid loading objects with possibly
8599 offending sequences. Without -mpc-relative-literal-loads we would
8600 generate such relocations, preventing the kernel build from
8601 succeeding. */
8606 /* In the tiny memory model it makes no sense to disallow PC relative
8607 literal pool loads. */
8612 /* When enabling the lower precision Newton series for the square root, also
8613 enable it for the reciprocal square root, since the latter is an
8614 intermediary step for the former. */
8617 }
8619 /* 'Unpack' up the internal tuning structs and update the options
8620 in OPTS. The caller must have set up selected_tune and selected_arch
8621 as all the other target-specific codegen decisions are
8622 derived from them. */
8624 void
8626 {
8629 /* Make a copy of the tuning parameters attached to the core, which
8630 we may later overwrite. */
8638 /* This target defaults to strict volatile bitfields. */
8647 {
8659 }
8661 /* We don't mind passing in global_options_set here as we don't use
8662 the *options_set structs anyway. */
8664 queue_depth,
8668 /* Set the L1 cache line size. */
8676 }
8678 /* Print a hint with a suggestion for a core or architecture name that
8679 most closely resembles what the user passed in STR. ARCH is true if
8680 the user is asking for an architecture name. ARCH is false if the user
8681 is asking for a core name. */
8683 static void
8685 {
8696 }
8698 /* Print a hint with a suggestion for a core name that most closely resembles
8699 what the user passed in STR. */
8703 {
8705 }
8707 /* Print a hint with a suggestion for an architecture name that most closely
8708 resembles what the user passed in STR. */
8712 {
8714 }
8716 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8717 specified in STR and throw errors if appropriate. Put the results if
8718 they are valid in RES and ISA_FLAGS. Return whether the option is
8719 valid. */
8721 static bool
8724 {
8725 enum aarch64_parse_opt_result parse_res
8732 {
8745 }
8748 }
8750 /* Validate a command-line -march option. Parse the arch and extensions
8751 (if any) specified in STR and throw errors if appropriate. Put the
8752 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8753 option is valid. */
8755 static bool
8758 {
8759 enum aarch64_parse_opt_result parse_res
8766 {
8779 }
8782 }
8784 /* Validate a command-line -mtune option. Parse the cpu
8785 specified in STR and throw errors if appropriate. Put the
8786 result, if it is valid, in RES. Return whether the option is
8787 valid. */
8789 static bool
8791 {
8792 enum aarch64_parse_opt_result parse_res
8799 {
8809 }
8811 }
8813 /* Return the CPU corresponding to the enum CPU.
8814 If it doesn't specify a cpu, return the default. */
8818 {
8822 /* The & 0x3f is to extract the bottom 6 bits that encode the
8823 default cpu as selected by the --with-cpu GCC configure option
8824 in config.gcc.
8825 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8826 flags mechanism should be reworked to make it more sane. */
8828 }
8830 /* Return the architecture corresponding to the enum ARCH.
8831 If it doesn't specify a valid architecture, return the default. */
8835 {
8842 }
8844 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8845 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8846 tuning structs. In particular it must set selected_tune and
8847 aarch64_isa_flags that define the available ISA features and tuning
8848 decisions. It must also set selected_arch as this will be used to
8849 output the .arch asm tags for each function. */
8851 static void
8853 {
8866 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8867 If either of -march or -mtune is given, they override their
8868 respective component of -mcpu. */
8880 /* If the user did not specify a processor, choose the default
8881 one for them. This will be the CPU set during configuration using
8882 --with-cpu, otherwise it is "generic". */
8884 {
8886 {
8890 }
8891 else
8892 {
8893 /* Get default configure-time CPU. */
8896 }
8900 }
8901 /* If both -mcpu and -march are specified check that they are architecturally
8902 compatible, warn if they're not and prefer the -march ISA flags. */
8904 {
8906 {
8910 }
8915 }
8916 else
8917 {
8918 /* -mcpu but no -march. */
8925 }
8927 /* Set the arch as well as we will need it when outputing
8928 the .arch directive in assembly. */
8930 {
8933 }
8938 #ifndef HAVE_AS_MABI_OPTION
8939 /* The compiler may have been configured with 2.23.* binutils, which does
8940 not have support for ILP32. */
8943 #endif
8948 /* Make sure we properly set up the explicit options. */
8959 /* Save these options as the default ones in case we push and pop them later
8960 while processing functions with potential target attributes. */
8961 target_option_default_node = target_option_current_node
8963 }
8965 /* Implement targetm.override_options_after_change. */
8967 static void
8969 {
8971 }
8975 {
8979 }
8981 void
8983 {
8985 }
8987 /* A checking mechanism for the implementation of the various code models. */
8988 static void
8990 {
8992 {
8994 {
8999 #ifdef HAVE_AS_SMALL_PIC_RELOCS
9001 ? AARCH64_CMODEL_SMALL_PIC
9003 #else
9005 #endif
9013 }
9014 }
9015 else
9017 }
9019 /* Implement TARGET_OPTION_SAVE. */
9021 static void
9023 {
9025 }
9027 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9028 using the information saved in PTR. */
9030 static void
9032 {
9040 }
9042 /* Implement TARGET_OPTION_PRINT. */
9044 static void
9046 {
9057 }
9061 void
9063 {
9065 }
9067 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9068 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9069 make sure optab availability predicates are recomputed when necessary. */
9071 void
9073 {
9078 else
9080 }
9082 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9083 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9084 of the function, if such exists. This function may be called multiple
9085 times on a single function so use aarch64_previous_fndecl to avoid
9086 setting up identical state. */
9088 static void
9090 {
9094 tree old_tree = (aarch64_previous_fndecl
9100 /* If current function has no attributes but the previous one did,
9101 use the default node. */
9105 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9106 the default have been handled by aarch64_save_restore_target_globals from
9107 aarch64_pragma_target_parse. */
9113 /* First set the target options. */
9117 }
9119 /* Enum describing the various ways we can handle attributes.
9120 In many cases we can reuse the generic option handling machinery. */
9122 enum aarch64_attr_opt_type
9123 {
9127 aarch64_attr_custom /* Attribute requires a custom handling function. */
9128 };
9130 /* All the information needed to handle a target attribute.
9131 NAME is the name of the attribute.
9132 ATTR_TYPE specifies the type of behavior of the attribute as described
9133 in the definition of enum aarch64_attr_opt_type.
9134 ALLOW_NEG is true if the attribute supports a "no-" form.
9135 HANDLER is the function that takes the attribute string and whether
9136 it is a pragma or attribute and handles the option. It is needed only
9137 when the ATTR_TYPE is aarch64_attr_custom.
9138 OPT_NUM is the enum specifying the option that the attribute modifies.
9139 This is needed for attributes that mirror the behavior of a command-line
9140 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9141 aarch64_attr_enum. */
9143 struct aarch64_attribute_info
9144 {
9150 };
9152 /* Handle the ARCH_STR argument to the arch= target attribute.
9153 PRAGMA_OR_ATTR is used in potential error messages. */
9155 static bool
9157 {
9159 enum aarch64_parse_opt_result parse_res
9163 {
9168 }
9171 {
9185 }
9188 }
9190 /* Handle the argument CPU_STR to the cpu= target attribute.
9191 PRAGMA_OR_ATTR is used in potential error messages. */
9193 static bool
9195 {
9197 enum aarch64_parse_opt_result parse_res
9201 {
9209 }
9212 {
9226 }
9229 }
9231 /* Handle the argument STR to the tune= target attribute.
9232 PRAGMA_OR_ATTR is used in potential error messages. */
9234 static bool
9236 {
9238 enum aarch64_parse_opt_result parse_res
9242 {
9247 }
9250 {
9257 }
9260 }
9262 /* Parse an architecture extensions target attribute string specified in STR.
9263 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9264 if successful. Update aarch64_isa_flags to reflect the ISA features
9265 modified.
9266 PRAGMA_OR_ATTR is used in potential error messages. */
9268 static bool
9270 {
9274 /* We allow "+nothing" in the beginning to clear out all architectural
9275 features if the user wants to handpick specific features. */
9277 {
9280 }
9285 {
9288 }
9291 {
9304 }
9307 }
9309 /* The target attributes that we support. On top of these we also support just
9310 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9311 handled explicitly in aarch64_process_one_target_attr. */
9314 {
9316 OPT_mgeneral_regs_only },
9318 OPT_mfix_cortex_a53_835769 },
9320 OPT_mfix_cortex_a53_843419 },
9324 OPT_momit_leaf_frame_pointer },
9327 OPT_march_ },
9330 OPT_mtune_ },
9332 OPT_msign_return_address_ },
9334 };
9336 /* Parse ARG_STR which contains the definition of one target attribute.
9337 Show appropriate errors if any or return true if the attribute is valid.
9338 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9339 we're processing a target attribute or pragma. */
9341 static bool
9343 {
9349 {
9352 }
9357 /* Skip leading whitespace. */
9359 str_to_check++;
9361 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9362 It is easier to detect and handle it explicitly here rather than going
9363 through the machinery for the rest of the target attributes in this
9364 function. */
9369 {
9372 }
9375 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9376 and point ARG to "foo". */
9378 {
9380 arg++;
9381 }
9385 {
9386 /* If the names don't match up, or the user has given an argument
9387 to an attribute that doesn't accept one, or didn't give an argument
9388 to an attribute that expects one, fail to match. */
9397 {
9401 }
9403 /* If the name matches but the attribute does not allow "no-" versions
9404 then we can't match. */
9406 {
9410 }
9413 {
9414 /* Has a custom handler registered.
9415 For example, cpu=, arch=, tune=. */
9422 /* Either set or unset a boolean option. */
9424 {
9432 }
9433 /* Set or unset a bit in the target_flags. aarch64_handle_option
9434 should know what mask to apply given the option number. */
9436 {
9438 /* We only need to specify the option number.
9439 aarch64_handle_option will know which mask to apply. */
9445 }
9446 /* Use the option setting machinery to set an option to an enum. */
9448 {
9455 {
9458 global_dc);
9459 }
9460 else
9461 {
9464 }
9466 }
9469 }
9470 }
9472 /* If we reached here we either have found an attribute and validated
9473 it or didn't match any. If we matched an attribute but its arguments
9474 were malformed we will have returned false already. */
9476 }
9478 /* Count how many times the character C appears in
9479 NULL-terminated string STR. */
9481 static unsigned int
9483 {
9486 {
9488 res++;
9490 str++;
9491 }
9494 }
9496 /* Parse the tree in ARGS that contains the target attribute information
9497 and update the global target options space. PRAGMA_OR_ATTR is a string
9498 to be used in error messages, specifying whether this is processing
9499 a target attribute or a target pragma. */
9501 bool
9503 {
9505 {
9506 do
9507 {
9510 {
9513 }
9518 }
9519 /* We expect to find a string to parse. */
9527 {
9530 }
9532 /* Used to catch empty spaces between commas i.e.
9533 attribute ((target ("attr1,,attr2"))). */
9536 /* Handle multiple target attributes separated by ','. */
9541 {
9542 num_attrs++;
9544 {
9547 }
9550 }
9553 {
9557 }
9560 }
9562 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9563 process attribute ((target ("..."))). */
9565 static bool
9567 {
9570 tree old_optimize;
9574 /* If what we're processing is the current pragma string then the
9575 target option node is already stored in target_option_current_node
9576 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9577 having to re-parse the string. This is especially useful to keep
9578 arm_neon.h compile times down since that header contains a lot
9579 of intrinsics enclosed in pragmas. */
9581 {
9584 }
9590 /* If the function changed the optimization levels as well as setting
9591 target options, start with the optimizations specified. */
9596 /* Save the current target options to restore at the end. */
9599 /* If fndecl already has some target attributes applied to it, unpack
9600 them so that we add this attribute on top of them, rather than
9601 overwriting them. */
9603 {
9609 }
9610 else
9617 /* Set up any additional state. */
9619 {
9621 /* Initialize SIMD builtins if we haven't already.
9622 Set current_target_pragma to NULL for the duration so that
9623 the builtin initialization code doesn't try to tag the functions
9624 being built with the attributes specified by any current pragma, thus
9625 going into an infinite recursion. */
9627 {
9632 }
9634 }
9635 else
9641 {
9646 }
9654 }
9656 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
9657 tri-bool options (yes, no, don't care) and the default value is
9658 DEF, determine whether to reject inlining. */
9660 static bool
9663 {
9664 /* If the callee doesn't care, always allow inlining. */
9668 /* If the caller doesn't care, always allow inlining. */
9672 /* Otherwise, allow inlining if either the callee and caller values
9673 agree, or if the callee is using the default value. */
9675 }
9677 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
9678 to inline CALLEE into CALLER based on target-specific info.
9679 Make sure that the caller and callee have compatible architectural
9680 features. Then go through the other possible target attributes
9681 and see if they can block inlining. Try not to reject always_inline
9682 callees unless they are incompatible architecturally. */
9684 static bool
9686 {
9690 /* If callee has no option attributes, then it is ok to inline. */
9701 /* Callee's ISA flags should be a subset of the caller's. */
9706 /* Allow non-strict aligned functions inlining into strict
9707 aligned ones. */
9717 /* If the architectural features match up and the callee is always_inline
9718 then the other attributes don't matter. */
9730 /* Honour explicit requests to workaround errata. */
9743 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9744 caller and calle and they don't match up, reject inlining. */
9751 /* If the callee has specific tuning overrides, respect them. */
9756 /* If the user specified tuning override strings for the
9757 caller and callee and they don't match up, reject inlining.
9758 We just do a string compare here, we don't analyze the meaning
9759 of the string, as it would be too costly for little gain. */
9767 }
9769 /* Return true if SYMBOL_REF X binds locally. */
9771 static bool
9773 {
9777 }
9779 /* Return true if SYMBOL_REF X is thread local */
9780 static bool
9782 {
9790 }
9792 /* Classify a TLS symbol into one of the TLS kinds. */
9793 enum aarch64_symbol_type
9795 {
9799 {
9806 {
9812 }
9823 else
9832 }
9833 }
9835 /* Return the method that should be used to access SYMBOL_REF or
9836 LABEL_REF X. */
9838 enum aarch64_symbol_type
9840 {
9842 {
9844 {
9859 }
9860 }
9863 {
9868 {
9870 /* When we retrieve symbol + offset address, we have to make sure
9871 the offset does not cause overflow of the final address. But
9872 we have no way of knowing the address of symbol at compile time
9873 so we can't accurately say if the distance between the PC and
9874 symbol + offset is outside the addressible range of +/-1M in the
9875 TINY code model. So we rely on images not being greater than
9876 1M and cap the offset at 1M and anything beyond 1M will have to
9877 be loaded using an alternative mechanism. Furthermore if the
9878 symbol is a weak reference to something that isn't known to
9879 resolve to a symbol in this module, then force to memory. */
9887 /* Same reasoning as the tiny code model, but the offset cap here is
9888 4G. */
9909 /* This is alright even in PIC code as the constant
9910 pool reference is always PC relative and within
9911 the same translation unit. */
9914 else
9919 }
9920 }
9922 /* By default push everything into the constant pool. */
9924 }
9926 bool
9928 {
9930 }
9932 bool
9934 {
9942 }
9944 /* Return true if X holds either a quarter-precision or
9945 floating-point +0.0 constant. */
9946 static bool
9948 {
9955 /* We only handle moving 0.0 to a TFmode register. */
9960 }
9962 static bool
9964 {
9965 /* Do not allow vector struct mode constants. We could support
9966 0 and -1 easily, but they need support in aarch64-simd.md. */
9970 /* This could probably go away because
9971 we now decompose CONST_INTs according to expand_mov_immediate. */
9982 }
9984 rtx
9986 {
9992 /* Can return in any reg. */
9995 }
9997 /* On AAPCS systems, this is the "struct __va_list". */
10000 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
10001 Return the type to use as __builtin_va_list.
10003 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
10005 struct __va_list
10006 {
10007 void *__stack;
10008 void *__gr_top;
10009 void *__vr_top;
10010 int __gr_offs;
10011 int __vr_offs;
10012 }; */
10014 static tree
10016 {
10017 tree va_list_name;
10020 /* Create the type. */
10022 /* Give it the required name. */
10024 TYPE_DECL,
10026 va_list_type);
10031 /* Create the fields. */
10034 ptr_type_node);
10037 ptr_type_node);
10040 ptr_type_node);
10043 integer_type_node);
10046 integer_type_node);
10048 /* Tell tree-stdarg pass about our internal offset fields.
10049 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
10050 purpose to identify whether the code is updating va_list internal
10051 offset fields through irregular way. */
10073 /* Compute its layout. */
10077 }
10079 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10080 static void
10082 {
10086 tree t;
10100 {
10103 }
10112 NULL_TREE);
10114 NULL_TREE);
10116 NULL_TREE);
10118 NULL_TREE);
10120 NULL_TREE);
10122 /* Emit code to initialize STACK, which points to the next varargs stack
10123 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10124 by named arguments. STACK is 8-byte aligned. */
10131 /* Emit code to initialize GRTOP, the top of the GR save area.
10132 virtual_incoming_args_rtx should have been 16 byte aligned. */
10137 /* Emit code to initialize VRTOP, the top of the VR save area.
10138 This address is gr_save_area_bytes below GRTOP, rounded
10139 down to the next 16-byte boundary. */
10149 /* Emit code to initialize GROFF, the offset from GRTOP of the
10150 next GPR argument. */
10155 /* Likewise emit code to initialize VROFF, the offset from FTOP
10156 of the next VR argument. */
10160 }
10162 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10164 static tree
10167 {
10168 tree addr;
10174 machine_mode mode;
10201 type,
10205 {
10206 /* TYPE passed in fp/simd registers. */
10218 {
10221 }
10224 {
10226 }
10227 }
10228 else
10229 {
10230 /* TYPE passed in general registers. */
10243 {
10245 }
10246 }
10248 /* Get a local temporary for the field value. */
10251 /* Emit code to branch if off >= 0. */
10257 {
10258 /* Emit: offs = (offs + 15) & -16. */
10264 }
10265 else
10268 /* Update ap.__[g|v]r_offs */
10273 /* String up. */
10277 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10282 /* String up: make sure the assignment happens before the use. */
10286 /* Prepare the trees handling the argument that is passed on the stack;
10287 the top level node will store in ON_STACK. */
10290 {
10291 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10299 }
10300 else
10302 /* Advance ap.__stack */
10310 /* String up roundup and advance. */
10313 /* String up with arg */
10315 /* Big-endianness related address adjustment. */
10318 {
10322 }
10327 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10337 {
10338 /* type ha; // treat as "struct {ftype field[n];}"
10339 ... [computing offs]
10340 for (i = 0; i <nregs; ++i, offs += 16)
10341 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10342 return ha; */
10346 /* Declare a local variable. */
10350 /* Establish the base type. */
10352 {
10371 {
10375 }
10379 }
10381 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10389 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10391 {
10401 }
10405 }
10415 }
10417 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10419 static void
10423 {
10425 CUMULATIVE_ARGS local_cum;
10429 /* The caller has advanced CUM up to, but not beyond, the last named
10430 argument. Advance a local copy of CUM past the last "real" named
10431 argument, to find out how many registers are left over. */
10435 /* Found out how many registers we need to save.
10436 Honor tree-stdvar analysis results. */
10445 {
10448 }
10451 {
10453 {
10456 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10464 }
10466 {
10467 /* We can't use move_block_from_reg, because it will use
10468 the wrong mode, storing D regs only. */
10472 /* Set OFF to the offset from virtual_incoming_args_rtx of
10473 the first vector register. The VR save area lies below
10474 the GR one, and is aligned to 16 bytes. */
10481 {
10489 }
10490 }
10491 }
10493 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10494 any complication of having crtl->args.pretend_args_size changed. */
10499 }
10501 static void
10503 {
10506 {
10508 {
10511 }
10512 }
10513 }
10515 /* Walk down the type tree of TYPE counting consecutive base elements.
10516 If *MODEP is VOIDmode, then set it to the first valid floating point
10517 type. If a non-floating point type is found, or if a floating point
10518 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10519 otherwise return the count in the sub-tree. */
10520 static int
10522 {
10523 machine_mode mode;
10524 HOST_WIDE_INT size;
10527 {
10557 /* Use V2SImode and V4SImode as representatives of all 64-bit
10558 and 128-bit vector types. */
10561 {
10570 }
10575 /* Vector modes are considered to be opaque: two vectors are
10576 equivalent for the purposes of being homogeneous aggregates
10577 if they are the same size. */
10584 {
10588 /* Can't handle incomplete types nor sizes that are not
10589 fixed. */
10596 || !index
10607 /* There must be no padding. */
10612 }
10615 {
10618 tree field;
10620 /* Can't handle incomplete types nor sizes that are not
10621 fixed. */
10627 {
10635 }
10637 /* There must be no padding. */
10642 }
10646 {
10647 /* These aren't very interesting except in a degenerate case. */
10650 tree field;
10652 /* Can't handle incomplete types nor sizes that are not
10653 fixed. */
10659 {
10667 }
10669 /* There must be no padding. */
10674 }
10678 }
10681 }
10683 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
10684 type as described in AAPCS64 \S 4.1.2.
10686 See the comment above aarch64_composite_type_p for the notes on MODE. */
10688 static bool
10690 machine_mode mode)
10691 {
10701 }
10703 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
10704 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
10705 array types. The C99 floating-point complex types are also considered
10706 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
10707 types, which are GCC extensions and out of the scope of AAPCS64, are
10708 treated as composite types here as well.
10710 Note that MODE itself is not sufficient in determining whether a type
10711 is such a composite type or not. This is because
10712 stor-layout.c:compute_record_mode may have already changed the MODE
10713 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10714 structure with only one field may have its MODE set to the mode of the
10715 field. Also an integer mode whose size matches the size of the
10716 RECORD_TYPE type may be used to substitute the original mode
10717 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10718 solely relied on. */
10720 static bool
10722 machine_mode mode)
10723 {
10736 }
10738 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10739 shall be passed or returned in simd/fp register(s) (providing these
10740 parameter passing registers are available).
10742 Upon successful return, *COUNT returns the number of needed registers,
10743 *BASE_MODE returns the mode of the individual register and when IS_HAF
10744 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10745 floating-point aggregate or a homogeneous short-vector aggregate. */
10747 static bool
10749 const_tree type,
10753 {
10761 {
10764 }
10766 {
10770 }
10772 {
10776 {
10779 }
10780 else
10782 }
10783 else
10788 }
10790 /* Implement TARGET_STRUCT_VALUE_RTX. */
10792 static rtx
10795 {
10797 }
10799 /* Implements target hook vector_mode_supported_p. */
10800 static bool
10802 {
10814 }
10816 /* Return appropriate SIMD container
10817 for MODE within a vector of WIDTH bits. */
10818 static machine_mode
10820 {
10823 {
10826 {
10841 }
10842 else
10844 {
10855 }
10856 }
10858 }
10860 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10861 static machine_mode
10863 {
10865 }
10867 /* Return the bitmask of possible vector sizes for the vectorizer
10868 to iterate over. */
10869 static unsigned int
10871 {
10873 }
10875 /* Implement TARGET_MANGLE_TYPE. */
10879 {
10880 /* The AArch64 ABI documents say that "__va_list" has to be
10881 managled as if it is in the "std" namespace. */
10885 /* Half-precision float. */
10889 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10890 builtin types. */
10894 /* Use the default mangling. */
10896 }
10899 /* Return true if the rtx_insn contains a MEM RTX somewhere
10900 in it. */
10902 static bool
10904 {
10911 }
10913 /* Find the first rtx_insn before insn that will generate an assembly
10914 instruction. */
10918 {
10922 do
10923 {
10925 }
10929 }
10931 static bool
10933 {
10935 /* A number of these may be AArch32 only. */
10940 };
10943 {
10946 }
10949 }
10951 /* Check if there is a register dependency between a load and the insn
10952 for which we hold recog_data. */
10954 static bool
10956 {
10957 rtx load_reg;
10967 {
10973 }
10975 }
10978 /* When working around the Cortex-A53 erratum 835769,
10979 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10980 instruction and has a preceding memory instruction such that a NOP
10981 should be inserted between them. */
10983 bool
10985 {
10988 rtx body;
11001 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
11002 Restore recog state to INSN to avoid state corruption. */
11010 /* If the previous insn is a memory op and there is no dependency between
11011 it and the DImode madd, emit a NOP between them. If body is NULL then we
11012 have a complex memory operation, probably a load/store pair.
11013 Be conservative for now and emit a NOP. */
11020 }
11023 /* Implement FINAL_PRESCAN_INSN. */
11025 void
11027 {
11030 }
11033 /* Return the equivalent letter for size. */
11034 static char
11036 {
11038 {
11044 }
11045 }
11047 /* Return true iff x is a uniform vector of floating-point
11048 constants, and the constant can be represented in
11049 quarter-precision form. Note, as aarch64_float_const_representable
11050 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
11051 static bool
11053 {
11054 rtx elt;
11058 }
11060 /* Return true for valid and false for invalid. */
11061 bool
11064 {
11065 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11066 matches = 1; \
11067 for (i = 0; i < idx; i += (STRIDE)) \
11068 if (!(TEST)) \
11069 matches = 0; \
11070 if (matches) \
11071 { \
11072 immtype = (CLASS); \
11073 elsize = (ELSIZE); \
11074 eshift = (SHIFT); \
11075 emvn = (NEG); \
11076 break; \
11077 }
11087 {
11093 {
11098 }
11101 }
11103 /* Splat vector constant out into a byte vector. */
11105 {
11106 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11107 it must be laid out in the vector register in reverse order. */
11115 {
11118 }
11120 }
11122 /* Sanity check. */
11125 do
11126 {
11175 }
11182 {
11192 /* Un-invert bytes of recognized vector, if necessary. */
11198 {
11199 /* FIXME: Broken on 32-bit H_W_I hosts. */
11208 }
11209 else
11210 {
11214 /* Construct 'abcdefgh' because the assembler cannot handle
11215 generic constants. */
11220 }
11221 }
11224 #undef CHECK
11225 }
11227 /* Check of immediate shift constants are within range. */
11228 bool
11230 {
11234 else
11236 }
11238 /* Return true if X is a uniform vector where all elements
11239 are either the floating-point constant 0.0 or the
11240 integer constant 0. */
11241 bool
11243 {
11245 }
11248 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11249 operation of width WIDTH at bit position POS. */
11251 rtx
11253 {
11257 unsigned HOST_WIDE_INT mask
11260 }
11262 bool
11264 {
11269 {
11274 }
11277 }
11279 bool
11281 {
11294 }
11296 /* Return a const_int vector of VAL. */
11297 rtx
11299 {
11310 }
11312 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11314 bool
11316 {
11317 machine_mode vmode;
11323 }
11325 /* Construct and return a PARALLEL RTX vector with elements numbering the
11326 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11327 the vector - from the perspective of the architecture. This does not
11328 line up with GCC's perspective on lane numbers, so we end up with
11329 different masks depending on our target endian-ness. The diagram
11330 below may help. We must draw the distinction when building masks
11331 which select one half of the vector. An instruction selecting
11332 architectural low-lanes for a big-endian target, must be described using
11333 a mask selecting GCC high-lanes.
11335 Big-Endian Little-Endian
11337 GCC 0 1 2 3 3 2 1 0
11338 | x | x | x | x | | x | x | x | x |
11339 Architecture 3 2 1 0 3 2 1 0
11341 Low Mask: { 2, 3 } { 0, 1 }
11342 High Mask: { 0, 1 } { 2, 3 }
11343 */
11345 rtx
11347 {
11353 rtx t1;
11358 else
11366 }
11368 /* Check OP for validity as a PARALLEL RTX vector with elements
11369 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11370 from the perspective of the architecture. See the diagram above
11371 aarch64_simd_vect_par_cnst_half for more details. */
11373 bool
11376 {
11389 {
11396 }
11398 }
11400 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11401 HIGH (exclusive). */
11402 void
11404 const_tree exp)
11405 {
11406 HOST_WIDE_INT lane;
11411 {
11414 else
11416 }
11417 }
11419 /* Return TRUE if OP is a valid vector addressing mode. */
11420 bool
11422 {
11425 }
11427 /* Emit a register copy from operand to operand, taking care not to
11428 early-clobber source registers in the process.
11430 COUNT is the number of components into which the copy needs to be
11431 decomposed. */
11432 void
11435 {
11445 else
11449 }
11451 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11452 one of VSTRUCT modes: OI, CI, or XI. */
11453 int
11455 {
11457 }
11459 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11460 alignment of a vector to 128 bits. */
11461 static HOST_WIDE_INT
11463 {
11466 }
11468 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11469 static bool
11471 {
11475 /* We guarantee alignment for vectors up to 128-bits. */
11480 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11482 }
11484 /* Return true if the vector misalignment factor is supported by the
11485 target. */
11486 static bool
11490 {
11492 {
11493 /* Return if movmisalign pattern is not supported for this mode. */
11498 {
11499 /* Misalignment factor is unknown at compile time but we know
11500 it's word aligned. */
11502 {
11507 }
11509 }
11510 }
11512 is_packed);
11513 }
11515 /* If VALS is a vector constant that can be loaded into a register
11516 using DUP, generate instructions to do so and return an RTX to
11517 assign to the register. Otherwise return NULL_RTX. */
11518 static rtx
11520 {
11523 rtx x;
11528 /* We can load this constant by using DUP and a constant in a
11529 single ARM register. This will be cheaper than a vector
11530 load. */
11533 }
11536 /* Generate code to load VALS, which is a PARALLEL containing only
11537 constants (for vec_init) or CONST_VECTOR, efficiently into a
11538 register. Returns an RTX to copy into the register, or NULL_RTX
11539 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11540 static rtx
11542 {
11544 rtx const_dup;
11553 {
11554 /* A CONST_VECTOR must contain only CONST_INTs and
11555 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11556 Only store valid constants in a CONST_VECTOR. */
11558 {
11561 n_const++;
11562 }
11565 }
11566 else
11571 /* Load using MOVI/MVNI. */
11574 /* Loaded using DUP. */
11577 /* Load from constant pool. We can not take advantage of single-cycle
11578 LD1 because we need a PC-relative addressing mode. */
11580 else
11581 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11582 We can not construct an initializer. */
11584 }
11586 /* Expand a vector initialisation sequence, such that TARGET is
11587 initialised to contain VALS. */
11589 void
11591 {
11594 /* The number of vector elements. */
11596 /* The number of vector elements which are not constant. */
11599 /* The first element of vals. */
11603 /* Count the number of variable elements to initialise. */
11605 {
11609 else
11613 }
11615 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11616 how best to handle this. */
11618 {
11621 {
11624 }
11625 }
11627 /* Splat a single non-constant element if we can. */
11629 {
11633 }
11635 /* Initialise a vector which is part-variable. We want to first try
11636 to build those lanes which are constant in the most efficient way we
11637 can. */
11639 {
11642 /* Load constant part of vector. We really don't care what goes into the
11643 parts we will overwrite, but we're more likely to be able to load the
11644 constant efficiently if it has fewer, larger, repeating parts
11645 (see aarch64_simd_valid_immediate). */
11647 {
11653 {
11654 /* Look in the copied vector, as more elements are const. */
11657 {
11660 }
11661 }
11663 }
11665 }
11667 /* Insert the variable lanes directly. */
11673 {
11679 }
11680 }
11682 static unsigned HOST_WIDE_INT
11684 {
11685 return
11686 (!SHIFT_COUNT_TRUNCATED
11689 }
11691 /* Select a format to encode pointers in exception handling data. */
11692 int
11694 {
11697 {
11703 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
11704 for everything. */
11708 /* No assumptions here. 8-byte relocs required. */
11711 }
11713 }
11715 /* The last .arch and .tune assembly strings that we printed. */
11719 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
11720 by the function fndecl. */
11722 void
11724 tree fndecl)
11725 {
11731 else
11742 /* Only update the assembler .arch string if it is distinct from the last
11743 such string we printed. */
11746 {
11749 }
11751 /* Print the cpu name we're tuning for in the comments, might be
11752 useful to readers of the generated asm. Do it only when it changes
11753 from function to function and verbose assembly is requested. */
11758 {
11762 }
11764 /* Don't forget the type directive for ELF. */
11767 }
11769 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
11771 static void
11773 {
11790 }
11792 /* Emit load exclusive. */
11794 static void
11797 {
11801 {
11808 }
11811 }
11813 /* Emit store exclusive. */
11815 static void
11818 {
11822 {
11829 }
11832 }
11834 /* Mark the previous jump instruction as unlikely. */
11836 static void
11838 {
11843 }
11845 /* Expand a compare and swap pattern. */
11847 void
11849 {
11854 gen_cas_fn gen;
11856 {
11857 gen_aarch64_compare_and_swapqi,
11858 gen_aarch64_compare_and_swaphi,
11859 gen_aarch64_compare_and_swapsi,
11860 gen_aarch64_compare_and_swapdi
11861 };
11863 {
11864 gen_aarch64_compare_and_swapqi_lse,
11865 gen_aarch64_compare_and_swaphi_lse,
11866 gen_aarch64_compare_and_swapsi_lse,
11867 gen_aarch64_compare_and_swapdi_lse
11868 };
11881 /* Normally the succ memory model must be stronger than fail, but in the
11882 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11883 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11890 {
11893 /* For short modes, we're going to perform the comparison in SImode,
11894 so do the zero-extension now. */
11898 /* Fall through. */
11902 /* Force the value into a register if needed. */
11909 }
11912 {
11919 }
11922 else
11933 }
11935 /* Test whether the target supports using a atomic load-operate instruction.
11936 CODE is the operation and AFTER is TRUE if the data in memory after the
11937 operation should be returned and FALSE if the data before the operation
11938 should be returned. Returns FALSE if the operation isn't supported by the
11939 architecture. */
11941 bool
11943 {
11948 {
11958 }
11959 }
11961 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
11962 sequence implementing an atomic operation. */
11964 static void
11966 {
11973 {
11975 }
11976 }
11978 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
11979 for the data in memory. EXPECTED is the value expected to be in memory.
11980 DESIRED is the value to store to memory. MEM is the memory location. MODEL
11981 is the memory ordering to use. */
11983 void
11986 rtx model)
11987 {
11989 machine_mode mode;
11994 {
12001 }
12003 /* Move the expected value into the CAS destination register. */
12006 /* Emit the CAS. */
12009 /* Compare the expected value with the value loaded by the CAS, to establish
12010 whether the swap was made. */
12012 }
12014 /* Split a compare and swap pattern. */
12016 void
12018 {
12020 machine_mode mode;
12025 rtx model_rtx;
12039 {
12042 }
12045 /* The initial load can be relaxed for a __sync operation since a final
12046 barrier will be emitted to stop code hoisting. */
12050 else
12062 {
12067 }
12068 else
12069 {
12073 }
12077 /* Emit any final barrier needed for a __sync operation. */
12080 }
12082 /* Emit a BIC instruction. */
12084 static void
12086 {
12091 {
12096 }
12099 }
12101 /* Emit an atomic swap. */
12103 static void
12106 {
12110 {
12117 }
12120 }
12122 /* Operations supported by aarch64_emit_atomic_load_op. */
12124 enum aarch64_atomic_load_op_code
12125 {
12129 AARCH64_LDOP_BIC /* A & ~B */
12130 };
12132 /* Emit an atomic load-operate. */
12134 static void
12138 {
12141 {
12142 gen_aarch64_atomic_loadaddqi,
12143 gen_aarch64_atomic_loadaddhi,
12144 gen_aarch64_atomic_loadaddsi,
12145 gen_aarch64_atomic_loadadddi
12146 };
12148 {
12149 gen_aarch64_atomic_loadeorqi,
12150 gen_aarch64_atomic_loadeorhi,
12151 gen_aarch64_atomic_loadeorsi,
12152 gen_aarch64_atomic_loadeordi
12153 };
12155 {
12156 gen_aarch64_atomic_loadsetqi,
12157 gen_aarch64_atomic_loadsethi,
12158 gen_aarch64_atomic_loadsetsi,
12159 gen_aarch64_atomic_loadsetdi
12160 };
12162 {
12163 gen_aarch64_atomic_loadclrqi,
12164 gen_aarch64_atomic_loadclrhi,
12165 gen_aarch64_atomic_loadclrsi,
12166 gen_aarch64_atomic_loadclrdi
12167 };
12168 aarch64_atomic_load_op_fn gen;
12172 {
12179 }
12182 {
12189 }
12192 }
12194 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12195 location to store the data read from memory. OUT_RESULT is the location to
12196 store the result of the operation. MEM is the memory location to read and
12197 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12198 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12199 be NULL. */
12201 void
12204 {
12208 aarch64_atomic_load_op_code ldop_code;
12209 rtx src;
12210 rtx x;
12218 /* Make sure the value is in a register, putting it into a destination
12219 register if it needs to be manipulated. */
12222 {
12225 }
12226 else
12230 /* Preprocess the data for the operation as necessary. If the operation is
12231 a SET then emit a swap instruction and finish. */
12233 {
12239 /* Negate the value and treat it as a PLUS. */
12240 {
12241 rtx neg_src;
12243 /* Resize the value if necessary. */
12252 }
12253 /* Fall-through. */
12267 {
12268 rtx not_src;
12270 /* Resize the value if necessary. */
12279 }
12284 /* The operation can't be done with atomic instructions. */
12286 }
12290 /* If necessary, calculate the data in memory after the update by redoing the
12291 operation from values in registers. */
12296 {
12300 }
12305 {
12321 }
12326 }
12328 /* Split an atomic operation. */
12330 void
12333 {
12339 rtx x;
12341 /* Split the atomic operation into a sequence. */
12349 else
12353 /* The initial load can be relaxed for a __sync operation since a final
12354 barrier will be emitted to stop code hoisting. */
12358 else
12362 {
12376 {
12379 }
12380 /* Fall through. */
12386 }
12396 /* Emit any final barrier needed for a __sync operation. */
12399 }
12401 static void
12403 {
12404 /* Half-precision float operations. The compiler handles all operations
12405 with NULL libfuncs by converting to SFmode. */
12407 /* Conversions. */
12411 /* Arithmetic. */
12418 /* Comparisons. */
12426 }
12428 /* Target hook for c_mode_for_suffix. */
12429 static machine_mode
12431 {
12436 }
12438 /* We can only represent floating point constants which will fit in
12439 "quarter-precision" values. These values are characterised by
12440 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12441 by:
12443 (-1)^s * (n/16) * 2^r
12445 Where:
12446 's' is the sign bit.
12447 'n' is an integer in the range 16 <= n <= 31.
12448 'r' is an integer in the range -3 <= r <= 4. */
12450 /* Return true iff X can be represented by a quarter-precision
12451 floating point immediate operand X. Note, we cannot represent 0.0. */
12452 bool
12454 {
12455 /* This represents our current view of how many bits
12456 make up the mantissa. */
12466 /* We don't support HFmode constants yet. */
12472 /* We cannot represent infinities, NaNs or +/-zero. We won't
12473 know if we have +zero until we analyse the mantissa, but we
12474 can reject the other invalid values. */
12479 /* Extract exponent. */
12483 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12484 highest (sign) bit, with a fixed binary point at bit point_pos.
12485 m1 holds the low part of the mantissa, m2 the high part.
12486 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12487 bits for the mantissa, this can fail (low bits will be lost). */
12491 /* If the low part of the mantissa has bits set we cannot represent
12492 the value. */
12495 /* We have rejected the lower HOST_WIDE_INT, so update our
12496 understanding of how many bits lie in the mantissa and
12497 look only at the high HOST_WIDE_INT. */
12501 /* We can only represent values with a mantissa of the form 1.xxxx. */
12506 /* Having filtered unrepresentable values, we may now remove all
12507 but the highest 5 bits. */
12510 /* We cannot represent the value 0.0, so reject it. This is handled
12511 elsewhere. */
12515 /* Then, as bit 4 is always set, we can mask it off, leaving
12516 the mantissa in the range [0, 15]. */
12520 /* GCC internally does not use IEEE754-like encoding (where normalized
12521 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12522 Our mantissa values are shifted 4 places to the left relative to
12523 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12524 by 5 places to correct for GCC's representation. */
12528 }
12532 machine_mode mode,
12534 {
12544 /* This will return true to show const_vector is legal for use as either
12545 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12546 also update INFO to show how the immediate should be generated. */
12555 {
12557 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12558 move immediate path. */
12561 else
12562 {
12571 else
12575 }
12576 }
12589 else
12593 }
12597 machine_mode mode)
12598 {
12599 machine_mode vmode;
12605 }
12607 /* Split operands into moves from op[1] + op[2] into op[0]. */
12609 void
12611 {
12622 {
12623 /* No-op move. Can't split to nothing; emit something. */
12626 }
12628 /* Preserve register attributes for variable tracking. */
12633 /* Special case of reversed high/low parts. */
12636 {
12640 }
12642 {
12643 /* Try to avoid unnecessary moves if part of the result
12644 is in the right place already. */
12649 }
12650 else
12651 {
12656 }
12657 }
12659 /* vec_perm support. */
12661 #define MAX_VECT_LEN 16
12663 struct expand_vec_perm_d
12664 {
12667 machine_mode vmode;
12671 };
12673 /* Generate a variable permutation. */
12675 static void
12677 {
12688 {
12690 {
12691 /* Expand the argument to a V16QI mode by duplicating it. */
12695 }
12696 else
12697 {
12699 }
12700 }
12701 else
12702 {
12703 rtx pair;
12706 {
12710 }
12711 else
12712 {
12716 }
12717 }
12718 }
12720 void
12722 {
12726 rtx mask;
12728 /* The TBL instruction does not use a modulo index, so we must take care
12729 of that ourselves. */
12734 /* For big-endian, we also need to reverse the index within the vector
12735 (but not which vector). */
12737 {
12738 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
12743 }
12745 }
12747 /* Recognize patterns suitable for the TRN instructions. */
12748 static bool
12750 {
12759 /* Note that these are little-endian tests.
12760 We correct for big-endian later. */
12765 else
12770 {
12775 }
12777 /* Success! */
12784 {
12787 }
12791 {
12793 {
12808 }
12809 }
12810 else
12811 {
12813 {
12828 }
12829 }
12833 }
12835 /* Recognize patterns suitable for the UZP instructions. */
12836 static bool
12838 {
12847 /* Note that these are little-endian tests.
12848 We correct for big-endian later. */
12853 else
12858 {
12862 }
12864 /* Success! */
12871 {
12874 }
12878 {
12880 {
12895 }
12896 }
12897 else
12898 {
12900 {
12915 }
12916 }
12920 }
12922 /* Recognize patterns suitable for the ZIP instructions. */
12923 static bool
12925 {
12934 /* Note that these are little-endian tests.
12935 We correct for big-endian later. */
12938 /* Do Nothing. */
12939 ;
12942 else
12947 {
12954 }
12956 /* Success! */
12963 {
12966 }
12970 {
12972 {
12987 }
12988 }
12989 else
12990 {
12992 {
13007 }
13008 }
13012 }
13014 /* Recognize patterns for the EXT insn. */
13016 static bool
13018 {
13021 rtx offset;
13025 /* Check if the extracted indices are increasing by one. */
13027 {
13030 {
13031 /* We'll pass the same vector in twice, so allow indices to wrap. */
13033 }
13036 }
13039 {
13054 }
13056 /* Success! */
13060 /* The case where (location == 0) is a no-op for both big- and little-endian,
13061 and is removed by the mid-end at optimization levels -O1 and higher. */
13064 {
13065 /* After setup, we want the high elements of the first vector (stored
13066 at the LSB end of the register), and the low elements of the second
13067 vector (stored at the MSB end of the register). So swap. */
13069 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13071 }
13076 }
13078 /* Recognize patterns for the REV insns. */
13080 static bool
13082 {
13091 {
13094 {
13099 }
13103 {
13110 }
13114 {
13127 }
13131 }
13135 {
13136 /* This is guaranteed to be true as the value of diff
13137 is 7, 3, 1 and we should have enough elements in the
13138 queue to generate this. Getting a vector mask with a
13139 value of diff other than these values implies that
13140 something is wrong by the time we get here. */
13144 }
13146 /* Success! */
13152 }
13154 static bool
13156 {
13159 rtx in0;
13162 rtx lane;
13166 {
13169 }
13171 /* The generic preparation in aarch64_expand_vec_perm_const_1
13172 swaps the operand order and the permute indices if it finds
13173 d->perm[0] to be in the second operand. Thus, we can always
13174 use d->op0 and need not do any extra arithmetic to get the
13175 correct lane number. */
13180 {
13195 }
13199 }
13201 static bool
13203 {
13211 /* Generic code will try constant permutation twice. Once with the
13212 original mode and again with the elements lowered to QImode.
13213 So wait and don't do the selector expansion ourselves. */
13218 {
13221 /* If big-endian and two vectors we end up with a weird mixed-endian
13222 mode on NEON. Reverse the index within each word but not the word
13223 itself. */
13226 }
13232 }
13234 static bool
13236 {
13237 /* The pattern matching functions above are written to look for a small
13238 number to begin the sequence (0, 1, N/2). If we begin with an index
13239 from the second operand, we can swap the operands. */
13241 {
13249 }
13252 {
13266 }
13268 }
13270 /* Expand a vec_perm_const pattern. */
13272 bool
13274 {
13288 {
13293 }
13296 {
13305 /* The elements of PERM do not suggest that only the first operand
13306 is used, but both operands are identical. Allow easier matching
13307 of the permutation by folding the permutation into the single
13308 input vector. */
13309 /* Fall Through. */
13321 }
13324 }
13326 static bool
13329 {
13339 /* Calculate whether all elements are in one vector. */
13341 {
13345 }
13347 /* If all elements are from the second vector, reindex as if from the
13348 first vector. */
13353 /* Check whether the mask can be applied to a single vector. */
13366 }
13368 rtx
13370 {
13371 /* We have to reverse each vector because we dont have
13372 a permuted load that can reverse-load according to ABI rules. */
13373 rtx mask;
13387 }
13389 /* Implement MODES_TIEABLE_P. In principle we should always return true.
13390 However due to issues with register allocation it is preferable to avoid
13391 tieing integer scalar and FP scalar modes. Executing integer operations
13392 in general registers is better than treating them as scalar vector
13393 operations. This reduces latency and avoids redundant int<->FP moves.
13394 So tie modes if they are either the same class, or vector modes with
13395 other vector modes, vector structs or any scalar mode.
13396 */
13398 bool
13400 {
13404 /* We specifically want to allow elements of "structure" modes to
13405 be tieable to the structure. This more general condition allows
13406 other rarer situations too. */
13410 /* Also allow any scalar modes with vectors. */
13416 }
13418 /* Return a new RTX holding the result of moving POINTER forward by
13419 AMOUNT bytes. */
13421 static rtx
13423 {
13428 }
13430 /* Return a new RTX holding the result of moving POINTER forward by the
13431 size of the mode it points to. */
13433 static rtx
13435 {
13439 }
13441 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13442 MODE bytes. */
13444 static void
13446 machine_mode mode)
13447 {
13450 /* "Cast" the pointers to the correct mode. */
13453 /* Emit the memcpy. */
13456 /* Move the pointers forward. */
13459 }
13461 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13462 we succeed, otherwise return false. */
13464 bool
13466 {
13470 rtx base;
13473 /* When optimizing for size, give a better estimate of the length of a
13474 memcpy call, but use the default otherwise. */
13477 /* We can't do anything smart if the amount to copy is not constant. */
13483 /* Try to keep the number of instructions low. For cases below 16 bytes we
13484 need to make at most two moves. For cases above 16 bytes it will be one
13485 move for each 16 byte chunk, then at most two additional moves. */
13495 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13496 1-byte chunk. */
13498 {
13500 {
13503 }
13509 }
13511 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13512 4-byte chunk, partially overlapping with the previously copied chunk. */
13514 {
13518 {
13524 }
13526 }
13528 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13529 them, then (if applicable) an 8-byte chunk. */
13531 {
13533 {
13536 }
13537 else
13538 {
13541 }
13542 }
13544 /* Finish the final bytes of the copy. We can always do this in one
13545 instruction. We either copy the exact amount we need, or partially
13546 overlap with the previous chunk we copied and copy 8-bytes. */
13555 else
13556 {
13558 {
13562 }
13563 else
13564 {
13570 }
13571 }
13574 }
13576 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
13577 SImode stores. Handle the case when the constant has identical
13578 bottom and top halves. This is beneficial when the two stores can be
13579 merged into an STP and we avoid synthesising potentially expensive
13580 immediates twice. Return true if such a split is possible. */
13582 bool
13584 {
13593 unsigned int orig_cost
13595 unsigned int lo_cost
13598 /* We want to transform:
13599 MOV x1, 49370
13600 MOVK x1, 0x140, lsl 16
13601 MOVK x1, 0xc0da, lsl 32
13602 MOVK x1, 0x140, lsl 48
13603 STR x1, [x0]
13604 into:
13605 MOV w1, 49370
13606 MOVK w1, 0x140, lsl 16
13607 STP w1, w1, [x0]
13608 So we want to perform this only when we save two instructions
13609 or more. When optimizing for size, however, accept any code size
13610 savings we can. */
13625 /* Don't emit an explicit store pair as this may not be always profitable.
13626 Let the sched-fusion logic decide whether to merge them. */
13631 }
13633 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13635 static unsigned HOST_WIDE_INT
13637 {
13639 }
13641 static bool
13646 {
13647 /* STORE_BY_PIECES can be used when copying a constant string, but
13648 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13649 For now we always fail this and let the move_by_pieces code copy
13650 the string from read-only memory. */
13655 }
13657 static rtx
13660 {
13664 insn_code icode;
13675 {
13703 }
13708 {
13711 }
13720 {
13723 }
13729 }
13731 static rtx
13734 {
13738 insn_code icode;
13750 {
13778 }
13783 {
13786 }
13794 {
13799 }
13810 {
13813 }
13819 }
13821 #undef TARGET_GEN_CCMP_FIRST
13822 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
13824 #undef TARGET_GEN_CCMP_NEXT
13825 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
13827 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13828 instruction fusion of some sort. */
13830 static bool
13832 {
13834 }
13837 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13838 should be kept together during scheduling. */
13840 static bool
13842 {
13843 rtx set_dest;
13846 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13853 {
13854 /* We are trying to match:
13855 prev (mov) == (set (reg r0) (const_int imm16))
13856 curr (movk) == (set (zero_extract (reg r0)
13857 (const_int 16)
13858 (const_int 16))
13859 (const_int imm16_1)) */
13871 {
13873 }
13874 }
13877 {
13879 /* We're trying to match:
13880 prev (adrp) == (set (reg r1)
13881 (high (symbol_ref ("SYM"))))
13882 curr (add) == (set (reg r0)
13883 (lo_sum (reg r1)
13884 (symbol_ref ("SYM"))))
13885 Note that r0 need not necessarily be the same as r1, especially
13886 during pre-regalloc scheduling. */
13890 {
13898 }
13899 }
13902 {
13904 /* We're trying to match:
13905 prev (movk) == (set (zero_extract (reg r0)
13906 (const_int 16)
13907 (const_int 32))
13908 (const_int imm16_1))
13909 curr (movk) == (set (zero_extract (reg r0)
13910 (const_int 16)
13911 (const_int 48))
13912 (const_int imm16_2)) */
13928 }
13930 {
13931 /* We're trying to match:
13932 prev (adrp) == (set (reg r0)
13933 (high (symbol_ref ("SYM"))))
13934 curr (ldr) == (set (reg r1)
13935 (mem (lo_sum (reg r0)
13936 (symbol_ref ("SYM")))))
13937 or
13938 curr (ldr) == (set (reg r1)
13939 (zero_extend (mem
13940 (lo_sum (reg r0)
13941 (symbol_ref ("SYM")))))) */
13944 {
13957 }
13958 }
13966 {
13969 /* FIXME: this misses some which is considered simple arthematic
13970 instructions for ThunderX. Simple shifts are missed here. */
13976 }
13979 }
13981 /* Return true iff the instruction fusion described by OP is enabled. */
13983 bool
13985 {
13987 }
13989 /* If MEM is in the form of [base+offset], extract the two parts
13990 of address and set to BASE and OFFSET, otherwise return false
13991 after clearing BASE and OFFSET. */
13993 bool
13995 {
13996 rtx addr;
14003 {
14007 }
14011 {
14015 }
14021 }
14023 /* Types for scheduling fusion. */
14024 enum sched_fusion_type
14025 {
14027 SCHED_FUSION_LD_SIGN_EXTEND,
14028 SCHED_FUSION_LD_ZERO_EXTEND,
14029 SCHED_FUSION_LD,
14030 SCHED_FUSION_ST,
14031 SCHED_FUSION_NUM
14032 };
14034 /* If INSN is a load or store of address in the form of [base+offset],
14035 extract the two parts and set to BASE and OFFSET. Return scheduling
14036 fusion type this INSN is. */
14038 static enum sched_fusion_type
14040 {
14058 {
14063 }
14065 {
14070 }
14075 {
14078 }
14079 else
14086 }
14088 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14090 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14091 and PRI are only calculated for these instructions. For other instruction,
14092 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14093 type instruction fusion can be added by returning different priorities.
14095 It's important that irrelevant instructions get the largest FUSION_PRI. */
14097 static void
14100 {
14110 {
14114 }
14116 /* Set FUSION_PRI according to fusion type and base register. */
14119 /* Calculate PRI. */
14122 /* INSN with smaller offset goes first. */
14126 else
14131 }
14133 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14134 Adjust priority of sha1h instructions so they are scheduled before
14135 other SHA1 instructions. */
14137 static int
14139 {
14143 {
14148 }
14151 }
14153 /* Given OPERANDS of consecutive load/store, check if we can merge
14154 them into ldp/stp. LOAD is true if they are load instructions.
14155 MODE is the mode of memory operands. */
14157 bool
14160 {
14166 {
14174 }
14175 else
14176 {
14181 }
14183 /* The mems cannot be volatile. */
14187 /* If we have SImode and slow unaligned ldp,
14188 check the alignment to be at least 8 byte. */
14192 && !optimize_size
14196 /* Check if the addresses are in the form of [base+offset]. */
14204 /* Check if the bases are same. */
14211 /* Check if the offsets are consecutive. */
14215 /* Check if the addresses are clobbered by load. */
14217 {
14221 /* In increasing order, the last load can clobber the address. */
14224 }
14228 else
14233 else
14236 /* Check if the registers are of same class. */
14241 }
14243 /* Given OPERANDS of consecutive load/store, check if we can merge
14244 them into ldp/stp by adjusting the offset. LOAD is true if they
14245 are load instructions. MODE is the mode of memory operands.
14247 Given below consecutive stores:
14249 str w1, [xb, 0x100]
14250 str w1, [xb, 0x104]
14251 str w1, [xb, 0x108]
14252 str w1, [xb, 0x10c]
14254 Though the offsets are out of the range supported by stp, we can
14255 still pair them after adjusting the offset, like:
14257 add scratch, xb, 0x100
14258 stp w1, w1, [scratch]
14259 stp w1, w1, [scratch, 0x8]
14261 The peephole patterns detecting this opportunity should guarantee
14262 the scratch register is avaliable. */
14264 bool
14267 {
14274 {
14287 }
14288 else
14289 {
14298 }
14299 /* Skip if memory operand is by itslef valid for ldp/stp. */
14303 /* The mems cannot be volatile. */
14308 /* Check if the addresses are in the form of [base+offset]. */
14322 /* Check if the bases are same. */
14333 /* Check if the offsets are consecutive. */
14342 /* Check if the addresses are clobbered by load. */
14344 {
14350 /* In increasing order, the last load can clobber the address. */
14353 }
14355 /* If we have SImode and slow unaligned ldp,
14356 check the alignment to be at least 8 byte. */
14360 && !optimize_size
14366 else
14371 else
14376 else
14381 else
14384 /* Check if the registers are of same class. */
14389 }
14391 /* Given OPERANDS of consecutive load/store, this function pairs them
14392 into ldp/stp after adjusting the offset. It depends on the fact
14393 that addresses of load/store instructions are in increasing order.
14394 MODE is the mode of memory operands. CODE is the rtl operator
14395 which should be applied to all memory operands, it's SIGN_EXTEND,
14396 ZERO_EXTEND or UNKNOWN. */
14398 bool
14401 {
14407 {
14412 }
14413 else
14414 {
14420 }
14425 /* Adjust offset thus it can fit in ldp/stp instruction. */
14433 /* Further adjust to make sure all offsets are OK. */
14435 {
14438 }
14440 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14445 {
14448 }
14450 /* Create new memory references. */
14454 /* Check if the adjusted address is OK for ldp/stp. */
14473 {
14478 }
14480 {
14485 }
14488 {
14493 }
14494 else
14495 {
14500 }
14502 /* Emit adjusting instruction. */
14504 /* Emit ldp/stp instructions. */
14512 }
14514 /* Return 1 if pseudo register should be created and used to hold
14515 GOT address for PIC code. */
14517 bool
14519 {
14521 }
14523 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
14525 static int
14527 {
14529 {
14536 }
14539 }
14542 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
14543 return the log2 of that value. Otherwise return -1. */
14545 int
14547 {
14562 }
14564 /* If X is a vector of equal CONST_DOUBLE values and that value is
14565 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
14567 int
14569 {
14585 }
14587 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
14588 to float.
14590 __fp16 always promotes through this hook.
14591 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
14592 through the generic excess precision logic rather than here. */
14594 static tree
14596 {
14602 }
14604 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
14606 static bool
14608 optimization_type opt_type)
14609 {
14611 {
14617 }
14618 }
14620 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
14621 if MODE is HFmode, and punt to the generic implementation otherwise. */
14623 static bool
14625 {
14629 }
14631 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
14632 if MODE is HFmode, and punt to the generic implementation otherwise. */
14634 static bool
14636 {
14640 }
14642 /* Set the value of FLT_EVAL_METHOD.
14643 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
14645 0: evaluate all operations and constants, whose semantic type has at
14646 most the range and precision of type float, to the range and
14647 precision of float; evaluate all other operations and constants to
14648 the range and precision of the semantic type;
14650 N, where _FloatN is a supported interchange floating type
14651 evaluate all operations and constants, whose semantic type has at
14652 most the range and precision of _FloatN type, to the range and
14653 precision of the _FloatN type; evaluate all other operations and
14654 constants to the range and precision of the semantic type;
14656 If we have the ARMv8.2-A extensions then we support _Float16 in native
14657 precision, so we should set this to 16. Otherwise, we support the type,
14658 but want to evaluate expressions in float precision, so set this to
14659 0. */
14661 static enum flt_eval_method
14663 {
14665 {
14668 /* We can calculate either in 16-bit range and precision or
14669 32-bit range and precision. Make that decision based on whether
14670 we have native support for the ARMv8.2-A 16-bit floating-point
14671 instructions or not. */
14673 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
14679 }
14681 }
14683 /* Target-specific selftests. */
14685 #if CHECKING_P
14689 /* Selftest for the RTL loader.
14690 Verify that the RTL loader copes with a dump from
14691 print_rtx_function. This is essentially just a test that class
14692 function_reader can handle a real dump, but it also verifies
14693 that lookup_reg_by_dump_name correctly handles hard regs.
14694 The presence of hard reg names in the dump means that the test is
14695 target-specific, hence it is in this file. */
14697 static void
14699 {
14711 /* Verify crtl->return_rtx. */
14715 }
14717 /* Run all target-specific selftests. */
14719 static void
14721 {
14723 }
14729 #undef TARGET_ADDRESS_COST
14730 #define TARGET_ADDRESS_COST aarch64_address_cost
14732 /* This hook will determines whether unnamed bitfields affect the alignment
14733 of the containing structure. The hook returns true if the structure
14734 should inherit the alignment requirements of an unnamed bitfield's
14735 type. */
14736 #undef TARGET_ALIGN_ANON_BITFIELD
14737 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
14739 #undef TARGET_ASM_ALIGNED_DI_OP
14742 #undef TARGET_ASM_ALIGNED_HI_OP
14745 #undef TARGET_ASM_ALIGNED_SI_OP
14748 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14749 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
14750 hook_bool_const_tree_hwi_hwi_const_tree_true
14752 #undef TARGET_ASM_FILE_START
14753 #define TARGET_ASM_FILE_START aarch64_start_file
14755 #undef TARGET_ASM_OUTPUT_MI_THUNK
14756 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
14758 #undef TARGET_ASM_SELECT_RTX_SECTION
14759 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
14761 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14762 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
14764 #undef TARGET_BUILD_BUILTIN_VA_LIST
14765 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
14767 #undef TARGET_CALLEE_COPIES
14768 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
14770 #undef TARGET_CAN_ELIMINATE
14771 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
14773 #undef TARGET_CAN_INLINE_P
14774 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
14776 #undef TARGET_CANNOT_FORCE_CONST_MEM
14777 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
14779 #undef TARGET_CASE_VALUES_THRESHOLD
14780 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
14782 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14783 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
14785 /* Only the least significant bit is used for initialization guard
14786 variables. */
14787 #undef TARGET_CXX_GUARD_MASK_BIT
14788 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
14790 #undef TARGET_C_MODE_FOR_SUFFIX
14791 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
14793 #ifdef TARGET_BIG_ENDIAN_DEFAULT
14794 #undef TARGET_DEFAULT_TARGET_FLAGS
14795 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
14796 #endif
14798 #undef TARGET_CLASS_MAX_NREGS
14799 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
14801 #undef TARGET_BUILTIN_DECL
14802 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
14804 #undef TARGET_BUILTIN_RECIPROCAL
14805 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
14807 #undef TARGET_C_EXCESS_PRECISION
14808 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
14810 #undef TARGET_EXPAND_BUILTIN
14811 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
14813 #undef TARGET_EXPAND_BUILTIN_VA_START
14814 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
14816 #undef TARGET_FOLD_BUILTIN
14817 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
14819 #undef TARGET_FUNCTION_ARG
14820 #define TARGET_FUNCTION_ARG aarch64_function_arg
14822 #undef TARGET_FUNCTION_ARG_ADVANCE
14823 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
14825 #undef TARGET_FUNCTION_ARG_BOUNDARY
14826 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
14828 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14829 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
14831 #undef TARGET_FUNCTION_VALUE
14832 #define TARGET_FUNCTION_VALUE aarch64_function_value
14834 #undef TARGET_FUNCTION_VALUE_REGNO_P
14835 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
14837 #undef TARGET_FRAME_POINTER_REQUIRED
14838 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
14840 #undef TARGET_GIMPLE_FOLD_BUILTIN
14841 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
14843 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14844 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
14846 #undef TARGET_INIT_BUILTINS
14847 #define TARGET_INIT_BUILTINS aarch64_init_builtins
14849 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
14850 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
14851 aarch64_ira_change_pseudo_allocno_class
14853 #undef TARGET_LEGITIMATE_ADDRESS_P
14854 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
14856 #undef TARGET_LEGITIMATE_CONSTANT_P
14857 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
14859 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
14860 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
14861 aarch64_legitimize_address_displacement
14863 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14864 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
14866 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
14867 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
14868 aarch64_libgcc_floating_mode_supported_p
14870 #undef TARGET_MANGLE_TYPE
14871 #define TARGET_MANGLE_TYPE aarch64_mangle_type
14873 #undef TARGET_MEMORY_MOVE_COST
14874 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
14876 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
14877 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
14879 #undef TARGET_MUST_PASS_IN_STACK
14880 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14882 /* This target hook should return true if accesses to volatile bitfields
14883 should use the narrowest mode possible. It should return false if these
14884 accesses should use the bitfield container type. */
14885 #undef TARGET_NARROW_VOLATILE_BITFIELD
14886 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
14888 #undef TARGET_OPTION_OVERRIDE
14889 #define TARGET_OPTION_OVERRIDE aarch64_override_options
14891 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
14892 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
14893 aarch64_override_options_after_change
14895 #undef TARGET_OPTION_SAVE
14896 #define TARGET_OPTION_SAVE aarch64_option_save
14898 #undef TARGET_OPTION_RESTORE
14899 #define TARGET_OPTION_RESTORE aarch64_option_restore
14901 #undef TARGET_OPTION_PRINT
14902 #define TARGET_OPTION_PRINT aarch64_option_print
14904 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14905 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
14907 #undef TARGET_SET_CURRENT_FUNCTION
14908 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
14910 #undef TARGET_PASS_BY_REFERENCE
14911 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
14913 #undef TARGET_PREFERRED_RELOAD_CLASS
14914 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
14916 #undef TARGET_SCHED_REASSOCIATION_WIDTH
14917 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
14919 #undef TARGET_PROMOTED_TYPE
14920 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
14922 #undef TARGET_SECONDARY_RELOAD
14923 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
14925 #undef TARGET_SHIFT_TRUNCATION_MASK
14926 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
14928 #undef TARGET_SETUP_INCOMING_VARARGS
14929 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
14931 #undef TARGET_STRUCT_VALUE_RTX
14932 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
14934 #undef TARGET_REGISTER_MOVE_COST
14935 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
14937 #undef TARGET_RETURN_IN_MEMORY
14938 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
14940 #undef TARGET_RETURN_IN_MSB
14941 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
14943 #undef TARGET_RTX_COSTS
14944 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
14946 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14947 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
14949 #undef TARGET_SCHED_ISSUE_RATE
14950 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
14952 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14953 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14954 aarch64_sched_first_cycle_multipass_dfa_lookahead
14956 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
14957 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
14958 aarch64_first_cycle_multipass_dfa_lookahead_guard
14960 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
14961 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
14962 aarch64_get_separate_components
14964 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
14965 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
14966 aarch64_components_for_bb
14968 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
14969 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
14970 aarch64_disqualify_components
14972 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
14973 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
14974 aarch64_emit_prologue_components
14976 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
14977 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
14978 aarch64_emit_epilogue_components
14980 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
14981 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
14982 aarch64_set_handled_components
14984 #undef TARGET_TRAMPOLINE_INIT
14985 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
14987 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14988 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
14990 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14991 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
14993 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
14994 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
14995 aarch64_builtin_support_vector_misalignment
14997 #undef TARGET_ARRAY_MODE_SUPPORTED_P
14998 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
15000 #undef TARGET_VECTORIZE_ADD_STMT_COST
15001 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
15003 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
15004 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
15005 aarch64_builtin_vectorization_cost
15007 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
15008 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
15010 #undef TARGET_VECTORIZE_BUILTINS
15011 #define TARGET_VECTORIZE_BUILTINS
15013 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
15014 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
15015 aarch64_builtin_vectorized_function
15017 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
15018 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
15019 aarch64_autovectorize_vector_sizes
15021 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
15022 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
15023 aarch64_atomic_assign_expand_fenv
15025 /* Section anchor support. */
15027 #undef TARGET_MIN_ANCHOR_OFFSET
15028 #define TARGET_MIN_ANCHOR_OFFSET -256
15030 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
15031 byte offset; we can do much more for larger data types, but have no way
15032 to determine the size of the access. We assume accesses are aligned. */
15033 #undef TARGET_MAX_ANCHOR_OFFSET
15034 #define TARGET_MAX_ANCHOR_OFFSET 4095
15036 #undef TARGET_VECTOR_ALIGNMENT
15037 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
15039 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
15040 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
15041 aarch64_simd_vector_alignment_reachable
15043 /* vec_perm support. */
15045 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
15046 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
15047 aarch64_vectorize_vec_perm_const_ok
15049 #undef TARGET_INIT_LIBFUNCS
15050 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
15052 #undef TARGET_FIXED_CONDITION_CODE_REGS
15053 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
15055 #undef TARGET_FLAGS_REGNUM
15056 #define TARGET_FLAGS_REGNUM CC_REGNUM
15058 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15059 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15061 #undef TARGET_ASAN_SHADOW_OFFSET
15062 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15064 #undef TARGET_LEGITIMIZE_ADDRESS
15065 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15067 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15068 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15069 aarch64_use_by_pieces_infrastructure_p
15071 #undef TARGET_CAN_USE_DOLOOP_P
15072 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15074 #undef TARGET_SCHED_ADJUST_PRIORITY
15075 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15077 #undef TARGET_SCHED_MACRO_FUSION_P
15078 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15080 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15081 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15083 #undef TARGET_SCHED_FUSION_PRIORITY
15084 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15086 #undef TARGET_UNSPEC_MAY_TRAP_P
15087 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15089 #undef TARGET_USE_PSEUDO_PIC_REG
15090 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15092 #undef TARGET_PRINT_OPERAND
15093 #define TARGET_PRINT_OPERAND aarch64_print_operand
15095 #undef TARGET_PRINT_OPERAND_ADDRESS
15096 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15098 #undef TARGET_OPTAB_SUPPORTED_P
15099 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15101 #undef TARGET_OMIT_STRUCT_RETURN_REG
15102 #define TARGET_OMIT_STRUCT_RETURN_REG true
15104 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15105 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15106 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15108 #if CHECKING_P
15109 #undef TARGET_RUN_TARGET_SELFTESTS
15110 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests