1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2013 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand 0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return 1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return 1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand 0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return 1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand 0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return 1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand 0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return 1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (and (match_code "reg")
120 (match_test "CA_REGNO_P (REGNO (op))")))
122 ;; Return 1 if op is a signed 5-bit constant integer.
123 (define_predicate "s5bit_cint_operand"
124 (and (match_code "const_int")
125 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
127 ;; Return 1 if op is a unsigned 5-bit constant integer.
128 (define_predicate "u5bit_cint_operand"
129 (and (match_code "const_int")
130 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
132 ;; Return 1 if op is a signed 8-bit constant integer.
133 ;; Integer multiplication complete more quickly
134 (define_predicate "s8bit_cint_operand"
135 (and (match_code "const_int")
136 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
138 ;; Return 1 if op is a constant integer that can fit in a D field.
139 (define_predicate "short_cint_operand"
140 (and (match_code "const_int")
141 (match_test "satisfies_constraint_I (op)")))
143 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
144 (define_predicate "u_short_cint_operand"
145 (and (match_code "const_int")
146 (match_test "satisfies_constraint_K (op)")))
148 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
149 (define_predicate "non_short_cint_operand"
150 (and (match_code "const_int")
151 (match_test "(unsigned HOST_WIDE_INT)
152 (INTVAL (op) + 0x8000) >= 0x10000")))
154 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
155 (define_predicate "exact_log2_cint_operand"
156 (and (match_code "const_int")
157 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
159 ;; Match op = 0 or op = 1.
160 (define_predicate "const_0_to_1_operand"
161 (and (match_code "const_int")
162 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
164 ;; Match op = 2 or op = 3.
165 (define_predicate "const_2_to_3_operand"
166 (and (match_code "const_int")
167 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
170 (define_predicate "const_0_to_15_operand"
171 (and (match_code "const_int")
172 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
174 ;; Return 1 if op is a register that is not special.
175 (define_predicate "gpc_reg_operand"
176 (match_operand 0 "register_operand")
178 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
181 if (GET_CODE (op) == SUBREG)
182 op = SUBREG_REG (op);
187 if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))
190 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
193 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
196 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
197 ;; allow floating point or vector registers.
198 (define_predicate "int_reg_operand"
199 (match_operand 0 "register_operand")
201 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
204 if (GET_CODE (op) == SUBREG)
205 op = SUBREG_REG (op);
210 if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op)))
213 return INT_REGNO_P (REGNO (op));
216 ;; Like int_reg_operand, but only return true for base registers
217 (define_predicate "base_reg_operand"
218 (match_operand 0 "int_reg_operand")
220 if (GET_CODE (op) == SUBREG)
221 op = SUBREG_REG (op);
226 return (REGNO (op) != FIRST_GPR_REGNO);
229 ;; Return 1 if op is a general purpose register that is an even register
230 ;; which suitable for a load/store quad operation
231 (define_predicate "quad_int_reg_operand"
232 (match_operand 0 "register_operand")
236 if (!TARGET_QUAD_MEMORY)
239 if (GET_CODE (op) == SUBREG)
240 op = SUBREG_REG (op);
246 if (r >= FIRST_PSEUDO_REGISTER)
249 return (INT_REGNO_P (r) && ((r & 1) == 0));
252 ;; Return 1 if op is a register that is a condition register field.
253 (define_predicate "cc_reg_operand"
254 (match_operand 0 "register_operand")
256 if (GET_CODE (op) == SUBREG)
257 op = SUBREG_REG (op);
262 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
265 return CR_REGNO_P (REGNO (op));
268 ;; Return 1 if op is a register that is a condition register field not cr0.
269 (define_predicate "cc_reg_not_cr0_operand"
270 (match_operand 0 "register_operand")
272 if (GET_CODE (op) == SUBREG)
273 op = SUBREG_REG (op);
278 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
281 return CR_REGNO_NOT_CR0_P (REGNO (op));
284 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
285 (define_predicate "cc_reg_not_micro_cr0_operand"
286 (match_operand 0 "register_operand")
288 if (GET_CODE (op) == SUBREG)
289 op = SUBREG_REG (op);
294 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
297 if (rs6000_gen_cell_microcode)
298 return CR_REGNO_NOT_CR0_P (REGNO (op));
300 return CR_REGNO_P (REGNO (op));
303 ;; Return 1 if op is a constant integer valid for D field
304 ;; or non-special register register.
305 (define_predicate "reg_or_short_operand"
306 (if_then_else (match_code "const_int")
307 (match_operand 0 "short_cint_operand")
308 (match_operand 0 "gpc_reg_operand")))
310 ;; Return 1 if op is a constant integer valid whose negation is valid for
311 ;; D field or non-special register register.
312 ;; Do not allow a constant zero because all patterns that call this
313 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
314 ;; or equal to const, which does not work for zero.
315 (define_predicate "reg_or_neg_short_operand"
316 (if_then_else (match_code "const_int")
317 (match_test "satisfies_constraint_P (op)
318 && INTVAL (op) != 0")
319 (match_operand 0 "gpc_reg_operand")))
321 ;; Return 1 if op is a constant integer valid for DS field
322 ;; or non-special register.
323 (define_predicate "reg_or_aligned_short_operand"
324 (if_then_else (match_code "const_int")
325 (and (match_operand 0 "short_cint_operand")
326 (match_test "!(INTVAL (op) & 3)"))
327 (match_operand 0 "gpc_reg_operand")))
329 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
330 ;; or non-special register.
331 (define_predicate "reg_or_u_short_operand"
332 (if_then_else (match_code "const_int")
333 (match_operand 0 "u_short_cint_operand")
334 (match_operand 0 "gpc_reg_operand")))
336 ;; Return 1 if op is any constant integer
337 ;; or non-special register.
338 (define_predicate "reg_or_cint_operand"
339 (ior (match_code "const_int")
340 (match_operand 0 "gpc_reg_operand")))
342 ;; Return 1 if op is a constant integer valid for addition
343 ;; or non-special register.
344 (define_predicate "reg_or_add_cint_operand"
345 (if_then_else (match_code "const_int")
346 (match_test "(unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
347 < (unsigned HOST_WIDE_INT) 0x100000000ll")
348 (match_operand 0 "gpc_reg_operand")))
350 ;; Return 1 if op is a constant integer valid for subtraction
351 ;; or non-special register.
352 (define_predicate "reg_or_sub_cint_operand"
353 (if_then_else (match_code "const_int")
354 (match_test "(unsigned HOST_WIDE_INT)
355 (- INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
356 < (unsigned HOST_WIDE_INT) 0x100000000ll")
357 (match_operand 0 "gpc_reg_operand")))
359 ;; Return 1 if op is any 32-bit unsigned constant integer
360 ;; or non-special register.
361 (define_predicate "reg_or_logical_cint_operand"
362 (if_then_else (match_code "const_int")
363 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
365 || ((INTVAL (op) & GET_MODE_MASK (mode)
366 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
367 (match_operand 0 "gpc_reg_operand")))
369 ;; Like reg_or_logical_cint_operand, but allow vsx registers
370 (define_predicate "vsx_reg_or_cint_operand"
371 (ior (match_operand 0 "vsx_register_operand")
372 (match_operand 0 "reg_or_logical_cint_operand")))
374 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
375 ;; with no more than one instruction per word.
376 (define_predicate "easy_fp_constant"
377 (match_code "const_double")
382 if (GET_MODE (op) != mode
383 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
386 /* Consider all constants with -msoft-float to be easy. */
387 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
388 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
392 /* The constant 0.0 is easy under VSX. */
393 if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)
394 && VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))
397 if (DECIMAL_FLOAT_MODE_P (mode))
400 /* If we are using V.4 style PIC, consider all constants to be hard. */
401 if (flag_pic && DEFAULT_ABI == ABI_V4)
404 #ifdef TARGET_RELOCATABLE
405 /* Similarly if we are using -mrelocatable, consider all constants
407 if (TARGET_RELOCATABLE)
414 if (TARGET_E500_DOUBLE)
417 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
418 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
420 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
421 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
422 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
423 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
426 /* The constant 0.f is easy under VSX. */
427 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
430 /* Force constants to memory before reload to utilize
431 compress_float_constant.
432 Avoid this when flag_unsafe_math_optimizations is enabled
433 because RDIV division to reciprocal optimization is not able
434 to regenerate the division. */
435 if (TARGET_E500_DOUBLE
436 || (!reload_in_progress && !reload_completed
437 && !flag_unsafe_math_optimizations))
440 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
441 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
443 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
444 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
447 /* The constant 0.f is easy. */
448 if (op == CONST0_RTX (SFmode))
451 /* Force constants to memory before reload to utilize
452 compress_float_constant.
453 Avoid this when flag_unsafe_math_optimizations is enabled
454 because RDIV division to reciprocal optimization is not able
455 to regenerate the division. */
456 if (!reload_in_progress && !reload_completed
457 && !flag_unsafe_math_optimizations)
460 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
461 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
463 return num_insns_constant_wide (k[0]) == 1;
466 return (num_insns_constant (op, DImode) <= 2);
476 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
477 ;; vector register without using memory.
478 (define_predicate "easy_vector_constant"
479 (match_code "const_vector")
481 /* As the paired vectors are actually FPRs it seems that there is
482 no easy way to load a CONST_VECTOR without using memory. */
483 if (TARGET_PAIRED_FLOAT)
486 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
488 if (zero_constant (op, mode))
491 return easy_altivec_constant (op, mode);
494 if (SPE_VECTOR_MODE (mode))
497 if (zero_constant (op, mode))
499 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
502 /* Limit SPE vectors to 15 bits signed. These we can generate with:
507 I don't know how efficient it would be to allow bigger constants,
508 considering we'll have an extra 'ori' for every 'li'. I doubt 5
509 instructions is better than a 64-bit memory load, but I don't
510 have the e500 timing specs. */
511 if (mode == V2SImode)
513 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
514 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
515 return cst >= -0x7fff && cst <= 0x7fff
516 && cst2 >= -0x7fff && cst2 <= 0x7fff;
523 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
524 (define_predicate "easy_vector_constant_add_self"
525 (and (match_code "const_vector")
526 (and (match_test "TARGET_ALTIVEC")
527 (match_test "easy_altivec_constant (op, mode)")))
530 if (mode == V2DImode || mode == V2DFmode)
532 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
533 val = ((val & 0xff) ^ 0x80) - 0x80;
534 return EASY_VECTOR_15_ADD_SELF (val);
537 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
538 (define_predicate "easy_vector_constant_msb"
539 (and (match_code "const_vector")
540 (and (match_test "TARGET_ALTIVEC")
541 (match_test "easy_altivec_constant (op, mode)")))
544 if (mode == V2DImode || mode == V2DFmode)
546 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
547 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
550 ;; Return 1 if operand is constant zero (scalars and vectors).
551 (define_predicate "zero_constant"
552 (and (match_code "const_int,const_double,const_vector")
553 (match_test "op == CONST0_RTX (mode)")))
555 ;; Return 1 if operand is 0.0.
556 (define_predicate "zero_fp_constant"
557 (and (match_code "const_double")
558 (match_test "SCALAR_FLOAT_MODE_P (mode)
559 && op == CONST0_RTX (mode)")))
561 ;; Return 1 if the operand is in volatile memory. Note that during the
562 ;; RTL generation phase, memory_operand does not return TRUE for volatile
563 ;; memory references. So this function allows us to recognize volatile
564 ;; references where it's safe.
565 (define_predicate "volatile_mem_operand"
566 (and (and (match_code "mem")
567 (match_test "MEM_VOLATILE_P (op)"))
568 (if_then_else (match_test "reload_completed")
569 (match_operand 0 "memory_operand")
570 (if_then_else (match_test "reload_in_progress")
571 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
572 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
574 ;; Return 1 if the operand is an offsettable memory operand.
575 (define_predicate "offsettable_mem_operand"
576 (and (match_operand 0 "memory_operand")
577 (match_test "offsettable_nonstrict_memref_p (op)")))
579 ;; Return 1 if the operand is suitable for load/store quad memory.
580 (define_predicate "quad_memory_operand"
586 if (!TARGET_QUAD_MEMORY)
589 else if (!memory_operand (op, mode))
592 else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
595 else if (MEM_ALIGN (op) < 128)
601 if (int_reg_operand (addr, Pmode))
604 else if (GET_CODE (addr) != PLUS)
609 op0 = XEXP (addr, 0);
610 op1 = XEXP (addr, 1);
611 ret = (int_reg_operand (op0, Pmode)
612 && GET_CODE (op1) == CONST_INT
613 && IN_RANGE (INTVAL (op1), -32768, 32767)
614 && (INTVAL (op1) & 15) == 0);
618 if (TARGET_DEBUG_ADDR)
620 fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");
627 ;; Return 1 if the operand is an indexed or indirect memory operand.
628 (define_predicate "indexed_or_indirect_operand"
632 if (VECTOR_MEM_ALTIVEC_P (mode)
633 && GET_CODE (op) == AND
634 && GET_CODE (XEXP (op, 1)) == CONST_INT
635 && INTVAL (XEXP (op, 1)) == -16)
638 return indexed_or_indirect_address (op, mode);
641 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
642 ;; moves are supported.
643 (define_predicate "reg_or_indexed_operand"
644 (match_code "mem,reg")
647 return indexed_or_indirect_operand (op, mode);
648 else if (TARGET_DIRECT_MOVE)
649 return register_operand (op, mode);
654 ;; Return 1 if the operand is an indexed or indirect memory operand with an
655 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
656 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
657 ;; while VSX uses the full address and traps)
658 (define_predicate "altivec_indexed_or_indirect_operand"
662 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
663 && GET_CODE (op) == AND
664 && GET_CODE (XEXP (op, 1)) == CONST_INT
665 && INTVAL (XEXP (op, 1)) == -16)
666 return indexed_or_indirect_address (XEXP (op, 0), mode);
671 ;; Return 1 if the operand is an indexed or indirect address.
672 (define_special_predicate "indexed_or_indirect_address"
673 (and (match_test "REG_P (op)
674 || (GET_CODE (op) == PLUS
675 /* Omit testing REG_P (XEXP (op, 0)). */
676 && REG_P (XEXP (op, 1)))")
677 (match_operand 0 "address_operand")))
679 ;; Return 1 if the operand is an index-form address.
680 (define_special_predicate "indexed_address"
681 (match_test "(GET_CODE (op) == PLUS
682 && REG_P (XEXP (op, 0))
683 && REG_P (XEXP (op, 1)))"))
685 ;; Return 1 if the operand is a MEM with an update-form address. This may
686 ;; also include update-indexed form.
687 (define_special_predicate "update_address_mem"
688 (match_test "(MEM_P (op)
689 && (GET_CODE (XEXP (op, 0)) == PRE_INC
690 || GET_CODE (XEXP (op, 0)) == PRE_DEC
691 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
693 ;; Return 1 if the operand is a MEM with an update-indexed-form address. Note
694 ;; that PRE_INC/PRE_DEC will always be non-indexed (i.e. non X-form) since the
695 ;; increment is based on the mode size and will therefor always be a const.
696 (define_special_predicate "update_indexed_address_mem"
697 (match_test "(MEM_P (op)
698 && GET_CODE (XEXP (op, 0)) == PRE_MODIFY
699 && indexed_address (XEXP (XEXP (op, 0), 1), mode))"))
701 ;; Used for the destination of the fix_truncdfsi2 expander.
702 ;; If stfiwx will be used, the result goes to memory; otherwise,
703 ;; we're going to emit a store and a load of a subreg, so the dest is a
705 (define_predicate "fix_trunc_dest_operand"
706 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
707 (match_operand 0 "memory_operand")
708 (match_operand 0 "gpc_reg_operand")))
710 ;; Return 1 if the operand is either a non-special register or can be used
711 ;; as the operand of a `mode' add insn.
712 (define_predicate "add_operand"
713 (if_then_else (match_code "const_int")
714 (match_test "satisfies_constraint_I (op)
715 || satisfies_constraint_L (op)")
716 (match_operand 0 "gpc_reg_operand")))
718 ;; Return 1 if OP is a constant but not a valid add_operand.
719 (define_predicate "non_add_cint_operand"
720 (and (match_code "const_int")
721 (match_test "!satisfies_constraint_I (op)
722 && !satisfies_constraint_L (op)")))
724 ;; Return 1 if the operand is a constant that can be used as the operand
726 (define_predicate "logical_const_operand"
727 (match_code "const_int")
731 opl = INTVAL (op) & GET_MODE_MASK (mode);
733 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
734 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
737 ;; Return 1 if the operand is a non-special register or a constant that
738 ;; can be used as the operand of an OR or XOR.
739 (define_predicate "logical_operand"
740 (ior (match_operand 0 "gpc_reg_operand")
741 (match_operand 0 "logical_const_operand")))
743 ;; Return 1 if op is a constant that is not a logical operand, but could
744 ;; be split into one.
745 (define_predicate "non_logical_cint_operand"
746 (and (match_code "const_int,const_double")
747 (and (not (match_operand 0 "logical_operand"))
748 (match_operand 0 "reg_or_logical_cint_operand"))))
750 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
751 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
752 ;; transitions). Reject all ones and all zeros, since these should have
753 ;; been optimized away and confuse the making of MB and ME.
754 (define_predicate "mask_operand"
755 (match_code "const_int")
757 HOST_WIDE_INT c, lsb;
761 if (TARGET_POWERPC64)
763 /* Fail if the mask is not 32-bit. */
764 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
767 /* Fail if the mask wraps around because the upper 32-bits of the
768 mask will all be 1s, contrary to GCC's internal view. */
769 if ((c & 0x80000001) == 0x80000001)
773 /* We don't change the number of transitions by inverting,
774 so make sure we start with the LS bit zero. */
778 /* Reject all zeros or all ones. */
782 /* Find the first transition. */
785 /* Invert to look for a second transition. */
788 /* Erase first transition. */
791 /* Find the second transition (if any). */
794 /* Match if all the bits above are 1's (or c is zero). */
798 ;; Return 1 for the PowerPC64 rlwinm corner case.
799 (define_predicate "mask_operand_wrap"
800 (match_code "const_int")
802 HOST_WIDE_INT c, lsb;
806 if ((c & 0x80000001) != 0x80000001)
820 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
821 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
822 ;; transition). Reject all zeros, since zero should have been
823 ;; optimized away and confuses the making of MB and ME.
824 (define_predicate "mask64_operand"
825 (match_code "const_int")
827 HOST_WIDE_INT c, lsb;
831 /* Reject all zeros. */
835 /* We don't change the number of transitions by inverting,
836 so make sure we start with the LS bit zero. */
840 /* Find the first transition. */
843 /* Match if all the bits above are 1's (or c is zero). */
847 ;; Like mask64_operand, but allow up to three transitions. This
848 ;; predicate is used by insn patterns that generate two rldicl or
849 ;; rldicr machine insns.
850 (define_predicate "mask64_2_operand"
851 (match_code "const_int")
853 HOST_WIDE_INT c, lsb;
857 /* Disallow all zeros. */
861 /* We don't change the number of transitions by inverting,
862 so make sure we start with the LS bit zero. */
866 /* Find the first transition. */
869 /* Invert to look for a second transition. */
872 /* Erase first transition. */
875 /* Find the second transition. */
878 /* Invert to look for a third transition. */
881 /* Erase second transition. */
884 /* Find the third transition (if any). */
887 /* Match if all the bits above are 1's (or c is zero). */
891 ;; Like and_operand, but also match constants that can be implemented
892 ;; with two rldicl or rldicr insns.
893 (define_predicate "and64_2_operand"
894 (ior (match_operand 0 "mask64_2_operand")
895 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
896 (match_operand 0 "gpc_reg_operand")
897 (match_operand 0 "logical_operand"))))
899 ;; Return 1 if the operand is either a non-special register or a
900 ;; constant that can be used as the operand of a logical AND.
901 (define_predicate "and_operand"
902 (ior (match_operand 0 "mask_operand")
903 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
904 (match_operand 0 "mask64_operand"))
905 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
906 (match_operand 0 "gpc_reg_operand")
907 (match_operand 0 "logical_operand")))))
909 ;; Return 1 if the operand is either a logical operand or a short cint operand.
910 (define_predicate "scc_eq_operand"
911 (ior (match_operand 0 "logical_operand")
912 (match_operand 0 "short_cint_operand")))
914 ;; Return 1 if the operand is a general non-special register or memory operand.
915 (define_predicate "reg_or_mem_operand"
916 (ior (match_operand 0 "memory_operand")
917 (ior (and (match_code "mem")
918 (match_test "macho_lo_sum_memory_operand (op, mode)"))
919 (ior (match_operand 0 "volatile_mem_operand")
920 (match_operand 0 "gpc_reg_operand")))))
922 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
923 (define_predicate "reg_or_none500mem_operand"
924 (if_then_else (match_code "mem")
925 (and (match_test "!TARGET_E500_DOUBLE")
926 (ior (match_operand 0 "memory_operand")
927 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
928 (match_operand 0 "volatile_mem_operand"))))
929 (match_operand 0 "gpc_reg_operand")))
931 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
932 (define_predicate "zero_reg_mem_operand"
933 (ior (match_operand 0 "zero_fp_constant")
934 (match_operand 0 "reg_or_mem_operand")))
936 ;; Return 1 if the operand is a general register or memory operand without
937 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
939 (define_predicate "lwa_operand"
940 (match_code "reg,subreg,mem")
942 rtx inner, addr, offset;
945 if (reload_completed && GET_CODE (inner) == SUBREG)
946 inner = SUBREG_REG (inner);
948 if (gpc_reg_operand (inner, mode))
950 if (!memory_operand (inner, mode))
952 addr = XEXP (inner, 0);
953 if (GET_CODE (addr) == PRE_INC
954 || GET_CODE (addr) == PRE_DEC
955 || (GET_CODE (addr) == PRE_MODIFY
956 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
958 if (GET_CODE (addr) == LO_SUM
959 && GET_CODE (XEXP (addr, 0)) == REG
960 && GET_CODE (XEXP (addr, 1)) == CONST)
961 addr = XEXP (XEXP (addr, 1), 0);
962 if (GET_CODE (addr) != PLUS)
964 offset = XEXP (addr, 1);
965 if (GET_CODE (offset) != CONST_INT)
967 return INTVAL (offset) % 4 == 0;
970 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
971 (define_predicate "symbol_ref_operand"
972 (and (match_code "symbol_ref")
973 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
974 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
976 ;; Return 1 if op is an operand that can be loaded via the GOT.
977 ;; or non-special register register field no cr0
978 (define_predicate "got_operand"
979 (match_code "symbol_ref,const,label_ref"))
981 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
982 ;; excluding labels involving addition.
983 (define_predicate "got_no_const_operand"
984 (match_code "symbol_ref,label_ref"))
986 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
987 (define_predicate "rs6000_tls_symbol_ref"
988 (and (match_code "symbol_ref")
989 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
991 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
992 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
993 (define_predicate "call_operand"
994 (if_then_else (match_code "reg")
995 (match_test "REGNO (op) == LR_REGNO
996 || REGNO (op) == CTR_REGNO
997 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
998 (match_code "symbol_ref")))
1000 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1002 (define_predicate "current_file_function_operand"
1003 (and (match_code "symbol_ref")
1004 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1005 && ((SYMBOL_REF_LOCAL_P (op)
1006 && (DEFAULT_ABI != ABI_AIX
1007 || !SYMBOL_REF_EXTERNAL_P (op)))
1008 || (op == XEXP (DECL_RTL (current_function_decl),
1011 ;; Return 1 if this operand is a valid input for a move insn.
1012 (define_predicate "input_operand"
1013 (match_code "symbol_ref,const,reg,subreg,mem,
1014 const_double,const_vector,const_int")
1016 /* Memory is always valid. */
1017 if (memory_operand (op, mode))
1020 /* For floating-point, easy constants are valid. */
1021 if (SCALAR_FLOAT_MODE_P (mode)
1022 && easy_fp_constant (op, mode))
1025 /* Allow any integer constant. */
1026 if (GET_MODE_CLASS (mode) == MODE_INT
1027 && (GET_CODE (op) == CONST_INT
1028 || GET_CODE (op) == CONST_DOUBLE))
1031 /* Allow easy vector constants. */
1032 if (GET_CODE (op) == CONST_VECTOR
1033 && easy_vector_constant (op, mode))
1036 /* Do not allow invalid E500 subregs. */
1037 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1038 && GET_CODE (op) == SUBREG
1039 && invalid_e500_subreg (op, mode))
1042 /* For floating-point or multi-word mode, the only remaining valid type
1044 if (SCALAR_FLOAT_MODE_P (mode)
1045 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1046 return register_operand (op, mode);
1048 /* The only cases left are integral modes one word or smaller (we
1049 do not get called for MODE_CC values). These can be in any
1051 if (register_operand (op, mode))
1054 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1056 if (DEFAULT_ABI == ABI_V4
1057 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1058 && small_data_operand (op, Pmode))
1064 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1065 (define_predicate "splat_input_operand"
1066 (match_code "symbol_ref,const,reg,subreg,mem,
1067 const_double,const_vector,const_int")
1071 if (! volatile_ok && MEM_VOLATILE_P (op))
1075 else if (mode == DImode)
1079 return memory_address_addr_space_p (mode, XEXP (op, 0),
1080 MEM_ADDR_SPACE (op));
1082 return input_operand (op, mode);
1085 ;; Return true if OP is a non-immediate operand and not an invalid
1086 ;; SUBREG operation on the e500.
1087 (define_predicate "rs6000_nonimmediate_operand"
1088 (match_code "reg,subreg,mem")
1090 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1091 && GET_CODE (op) == SUBREG
1092 && invalid_e500_subreg (op, mode))
1095 return nonimmediate_operand (op, mode);
1098 ;; Return true if operand is boolean operator.
1099 (define_predicate "boolean_operator"
1100 (match_code "and,ior,xor"))
1102 ;; Return true if operand is OR-form of boolean operator.
1103 (define_predicate "boolean_or_operator"
1104 (match_code "ior,xor"))
1106 ;; Return true if operand is an equality operator.
1107 (define_special_predicate "equality_operator"
1108 (match_code "eq,ne"))
1110 ;; Return true if operand is MIN or MAX operator.
1111 (define_predicate "min_max_operator"
1112 (match_code "smin,smax,umin,umax"))
1114 ;; Return 1 if OP is a comparison operation that is valid for a branch
1115 ;; instruction. We check the opcode against the mode of the CC value.
1116 ;; validate_condition_mode is an assertion.
1117 (define_predicate "branch_comparison_operator"
1118 (and (match_operand 0 "comparison_operator")
1119 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1120 (match_test "validate_condition_mode (GET_CODE (op),
1121 GET_MODE (XEXP (op, 0))),
1124 ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
1125 ;; If we're assuming that FP operations cannot generate user-visible traps,
1126 ;; then on e500 we can use the ordered-signaling instructions to implement
1127 ;; the unordered-quiet FP comparison predicates modulo a reversal.
1128 (define_predicate "rs6000_cbranch_operator"
1129 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
1130 (if_then_else (match_test "flag_trapping_math")
1131 (match_operand 0 "ordered_comparison_operator")
1132 (ior (match_operand 0 "ordered_comparison_operator")
1133 (match_code ("unlt,unle,ungt,unge"))))
1134 (match_operand 0 "comparison_operator")))
1136 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1137 ;; it must be a positive comparison.
1138 (define_predicate "scc_comparison_operator"
1139 (and (match_operand 0 "branch_comparison_operator")
1140 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1142 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1144 (define_predicate "scc_rev_comparison_operator"
1145 (and (match_operand 0 "branch_comparison_operator")
1146 (match_code "ne,le,ge,leu,geu,ordered")))
1148 ;; Return 1 if OP is a comparison operation that is valid for a branch
1149 ;; insn, which is true if the corresponding bit in the CC register is set.
1150 (define_predicate "branch_positive_comparison_operator"
1151 (and (match_operand 0 "branch_comparison_operator")
1152 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1154 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1155 (define_predicate "load_multiple_operation"
1156 (match_code "parallel")
1158 int count = XVECLEN (op, 0);
1159 unsigned int dest_regno;
1163 /* Perform a quick check so we don't blow up below. */
1165 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1166 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1167 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1170 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1171 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1173 for (i = 1; i < count; i++)
1175 rtx elt = XVECEXP (op, 0, i);
1177 if (GET_CODE (elt) != SET
1178 || GET_CODE (SET_DEST (elt)) != REG
1179 || GET_MODE (SET_DEST (elt)) != SImode
1180 || REGNO (SET_DEST (elt)) != dest_regno + i
1181 || GET_CODE (SET_SRC (elt)) != MEM
1182 || GET_MODE (SET_SRC (elt)) != SImode
1183 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1184 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1185 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1186 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1193 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1194 ;; The second vector element is a CLOBBER.
1195 (define_predicate "store_multiple_operation"
1196 (match_code "parallel")
1198 int count = XVECLEN (op, 0) - 1;
1199 unsigned int src_regno;
1203 /* Perform a quick check so we don't blow up below. */
1205 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1206 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1207 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1210 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1211 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1213 for (i = 1; i < count; i++)
1215 rtx elt = XVECEXP (op, 0, i + 1);
1217 if (GET_CODE (elt) != SET
1218 || GET_CODE (SET_SRC (elt)) != REG
1219 || GET_MODE (SET_SRC (elt)) != SImode
1220 || REGNO (SET_SRC (elt)) != src_regno + i
1221 || GET_CODE (SET_DEST (elt)) != MEM
1222 || GET_MODE (SET_DEST (elt)) != SImode
1223 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1224 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1225 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1226 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1233 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1235 (define_predicate "save_world_operation"
1236 (match_code "parallel")
1241 int count = XVECLEN (op, 0);
1247 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1248 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1251 for (i=1; i <= 18; i++)
1253 elt = XVECEXP (op, 0, index++);
1254 if (GET_CODE (elt) != SET
1255 || GET_CODE (SET_DEST (elt)) != MEM
1256 || ! memory_operand (SET_DEST (elt), DFmode)
1257 || GET_CODE (SET_SRC (elt)) != REG
1258 || GET_MODE (SET_SRC (elt)) != DFmode)
1262 for (i=1; i <= 12; i++)
1264 elt = XVECEXP (op, 0, index++);
1265 if (GET_CODE (elt) != SET
1266 || GET_CODE (SET_DEST (elt)) != MEM
1267 || GET_CODE (SET_SRC (elt)) != REG
1268 || GET_MODE (SET_SRC (elt)) != V4SImode)
1272 for (i=1; i <= 19; i++)
1274 elt = XVECEXP (op, 0, index++);
1275 if (GET_CODE (elt) != SET
1276 || GET_CODE (SET_DEST (elt)) != MEM
1277 || ! memory_operand (SET_DEST (elt), Pmode)
1278 || GET_CODE (SET_SRC (elt)) != REG
1279 || GET_MODE (SET_SRC (elt)) != Pmode)
1283 elt = XVECEXP (op, 0, index++);
1284 if (GET_CODE (elt) != SET
1285 || GET_CODE (SET_DEST (elt)) != MEM
1286 || ! memory_operand (SET_DEST (elt), Pmode)
1287 || GET_CODE (SET_SRC (elt)) != REG
1288 || REGNO (SET_SRC (elt)) != CR2_REGNO
1289 || GET_MODE (SET_SRC (elt)) != Pmode)
1292 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1293 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1298 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1300 (define_predicate "restore_world_operation"
1301 (match_code "parallel")
1306 int count = XVECLEN (op, 0);
1312 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1313 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1314 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1315 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1318 elt = XVECEXP (op, 0, index++);
1319 if (GET_CODE (elt) != SET
1320 || GET_CODE (SET_SRC (elt)) != MEM
1321 || ! memory_operand (SET_SRC (elt), Pmode)
1322 || GET_CODE (SET_DEST (elt)) != REG
1323 || REGNO (SET_DEST (elt)) != CR2_REGNO
1324 || GET_MODE (SET_DEST (elt)) != Pmode)
1327 for (i=1; i <= 19; i++)
1329 elt = XVECEXP (op, 0, index++);
1330 if (GET_CODE (elt) != SET
1331 || GET_CODE (SET_SRC (elt)) != MEM
1332 || ! memory_operand (SET_SRC (elt), Pmode)
1333 || GET_CODE (SET_DEST (elt)) != REG
1334 || GET_MODE (SET_DEST (elt)) != Pmode)
1338 for (i=1; i <= 12; i++)
1340 elt = XVECEXP (op, 0, index++);
1341 if (GET_CODE (elt) != SET
1342 || GET_CODE (SET_SRC (elt)) != MEM
1343 || GET_CODE (SET_DEST (elt)) != REG
1344 || GET_MODE (SET_DEST (elt)) != V4SImode)
1348 for (i=1; i <= 18; i++)
1350 elt = XVECEXP (op, 0, index++);
1351 if (GET_CODE (elt) != SET
1352 || GET_CODE (SET_SRC (elt)) != MEM
1353 || ! memory_operand (SET_SRC (elt), DFmode)
1354 || GET_CODE (SET_DEST (elt)) != REG
1355 || GET_MODE (SET_DEST (elt)) != DFmode)
1359 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1360 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1361 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1362 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1363 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1368 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1369 (define_predicate "vrsave_operation"
1370 (match_code "parallel")
1372 int count = XVECLEN (op, 0);
1373 unsigned int dest_regno, src_regno;
1377 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1378 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1379 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1380 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1383 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1384 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1386 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1389 for (i = 1; i < count; i++)
1391 rtx elt = XVECEXP (op, 0, i);
1393 if (GET_CODE (elt) != CLOBBER
1394 && GET_CODE (elt) != SET)
1401 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1402 (define_predicate "mfcr_operation"
1403 (match_code "parallel")
1405 int count = XVECLEN (op, 0);
1408 /* Perform a quick check so we don't blow up below. */
1410 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1411 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1412 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1415 for (i = 0; i < count; i++)
1417 rtx exp = XVECEXP (op, 0, i);
1422 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1424 if (GET_CODE (src_reg) != REG
1425 || GET_MODE (src_reg) != CCmode
1426 || ! CR_REGNO_P (REGNO (src_reg)))
1429 if (GET_CODE (exp) != SET
1430 || GET_CODE (SET_DEST (exp)) != REG
1431 || GET_MODE (SET_DEST (exp)) != SImode
1432 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1434 unspec = SET_SRC (exp);
1435 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1437 if (GET_CODE (unspec) != UNSPEC
1438 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1439 || XVECLEN (unspec, 0) != 2
1440 || XVECEXP (unspec, 0, 0) != src_reg
1441 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1442 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1448 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1449 (define_predicate "mtcrf_operation"
1450 (match_code "parallel")
1452 int count = XVECLEN (op, 0);
1456 /* Perform a quick check so we don't blow up below. */
1458 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1459 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1460 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1462 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1464 if (GET_CODE (src_reg) != REG
1465 || GET_MODE (src_reg) != SImode
1466 || ! INT_REGNO_P (REGNO (src_reg)))
1469 for (i = 0; i < count; i++)
1471 rtx exp = XVECEXP (op, 0, i);
1475 if (GET_CODE (exp) != SET
1476 || GET_CODE (SET_DEST (exp)) != REG
1477 || GET_MODE (SET_DEST (exp)) != CCmode
1478 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1480 unspec = SET_SRC (exp);
1481 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1483 if (GET_CODE (unspec) != UNSPEC
1484 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1485 || XVECLEN (unspec, 0) != 2
1486 || XVECEXP (unspec, 0, 0) != src_reg
1487 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1488 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1494 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1495 (define_predicate "lmw_operation"
1496 (match_code "parallel")
1498 int count = XVECLEN (op, 0);
1499 unsigned int dest_regno;
1501 unsigned int base_regno;
1502 HOST_WIDE_INT offset;
1505 /* Perform a quick check so we don't blow up below. */
1507 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1508 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1509 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1512 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1513 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1516 || count != 32 - (int) dest_regno)
1519 if (legitimate_indirect_address_p (src_addr, 0))
1522 base_regno = REGNO (src_addr);
1523 if (base_regno == 0)
1526 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1528 offset = INTVAL (XEXP (src_addr, 1));
1529 base_regno = REGNO (XEXP (src_addr, 0));
1534 for (i = 0; i < count; i++)
1536 rtx elt = XVECEXP (op, 0, i);
1539 HOST_WIDE_INT newoffset;
1541 if (GET_CODE (elt) != SET
1542 || GET_CODE (SET_DEST (elt)) != REG
1543 || GET_MODE (SET_DEST (elt)) != SImode
1544 || REGNO (SET_DEST (elt)) != dest_regno + i
1545 || GET_CODE (SET_SRC (elt)) != MEM
1546 || GET_MODE (SET_SRC (elt)) != SImode)
1548 newaddr = XEXP (SET_SRC (elt), 0);
1549 if (legitimate_indirect_address_p (newaddr, 0))
1554 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1556 addr_reg = XEXP (newaddr, 0);
1557 newoffset = INTVAL (XEXP (newaddr, 1));
1561 if (REGNO (addr_reg) != base_regno
1562 || newoffset != offset + 4 * i)
1569 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1570 (define_predicate "stmw_operation"
1571 (match_code "parallel")
1573 int count = XVECLEN (op, 0);
1574 unsigned int src_regno;
1576 unsigned int base_regno;
1577 HOST_WIDE_INT offset;
1580 /* Perform a quick check so we don't blow up below. */
1582 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1583 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1584 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1587 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1588 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1591 || count != 32 - (int) src_regno)
1594 if (legitimate_indirect_address_p (dest_addr, 0))
1597 base_regno = REGNO (dest_addr);
1598 if (base_regno == 0)
1601 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1603 offset = INTVAL (XEXP (dest_addr, 1));
1604 base_regno = REGNO (XEXP (dest_addr, 0));
1609 for (i = 0; i < count; i++)
1611 rtx elt = XVECEXP (op, 0, i);
1614 HOST_WIDE_INT newoffset;
1616 if (GET_CODE (elt) != SET
1617 || GET_CODE (SET_SRC (elt)) != REG
1618 || GET_MODE (SET_SRC (elt)) != SImode
1619 || REGNO (SET_SRC (elt)) != src_regno + i
1620 || GET_CODE (SET_DEST (elt)) != MEM
1621 || GET_MODE (SET_DEST (elt)) != SImode)
1623 newaddr = XEXP (SET_DEST (elt), 0);
1624 if (legitimate_indirect_address_p (newaddr, 0))
1629 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1631 addr_reg = XEXP (newaddr, 0);
1632 newoffset = INTVAL (XEXP (newaddr, 1));
1636 if (REGNO (addr_reg) != base_regno
1637 || newoffset != offset + 4 * i)
1644 ;; Return 1 if OP is a stack tie operand.
1645 (define_predicate "tie_operand"
1646 (match_code "parallel")
1648 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1649 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1650 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1651 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1654 ;; Match a small code model toc reference (or medium and large
1655 ;; model toc references before reload).
1656 (define_predicate "small_toc_ref"
1657 (match_code "unspec,plus")
1659 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
1662 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;