1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
57 /* Define the specific costs for a given cpu. */
59 struct processor_costs
62 const int m
; /* cost of an M instruction. */
63 const int mghi
; /* cost of an MGHI instruction. */
64 const int mh
; /* cost of an MH instruction. */
65 const int mhi
; /* cost of an MHI instruction. */
66 const int ml
; /* cost of an ML instruction. */
67 const int mr
; /* cost of an MR instruction. */
68 const int ms
; /* cost of an MS instruction. */
69 const int msg
; /* cost of an MSG instruction. */
70 const int msgf
; /* cost of an MSGF instruction. */
71 const int msgfr
; /* cost of an MSGFR instruction. */
72 const int msgr
; /* cost of an MSGR instruction. */
73 const int msr
; /* cost of an MSR instruction. */
74 const int mult_df
; /* cost of multiplication in DFmode. */
77 const int sqxbr
; /* cost of square root in TFmode. */
78 const int sqdbr
; /* cost of square root in DFmode. */
79 const int sqebr
; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr
; /* cost of multiply and add in DFmode. */
82 const int maebr
; /* cost of multiply and add in SFmode. */
94 const struct processor_costs
*s390_cost
;
97 struct processor_costs z900_cost
=
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
129 struct processor_costs z990_cost
=
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
161 struct processor_costs z9_109_cost
=
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
193 struct processor_costs z10_cost
=
195 COSTS_N_INSNS (10), /* M */
196 COSTS_N_INSNS (10), /* MGHI */
197 COSTS_N_INSNS (10), /* MH */
198 COSTS_N_INSNS (10), /* MHI */
199 COSTS_N_INSNS (10), /* ML */
200 COSTS_N_INSNS (10), /* MR */
201 COSTS_N_INSNS (10), /* MS */
202 COSTS_N_INSNS (10), /* MSG */
203 COSTS_N_INSNS (10), /* MSGF */
204 COSTS_N_INSNS (10), /* MSGFR */
205 COSTS_N_INSNS (10), /* MSGR */
206 COSTS_N_INSNS (10), /* MSR */
207 COSTS_N_INSNS (10), /* multiplication in DFmode */
208 COSTS_N_INSNS (50), /* MXBR */
209 COSTS_N_INSNS (120), /* SQXBR */
210 COSTS_N_INSNS (52), /* SQDBR */
211 COSTS_N_INSNS (38), /* SQEBR */
212 COSTS_N_INSNS (10), /* MADBR */
213 COSTS_N_INSNS (10), /* MAEBR */
214 COSTS_N_INSNS (111), /* DXBR */
215 COSTS_N_INSNS (39), /* DDBR */
216 COSTS_N_INSNS (32), /* DEBR */
217 COSTS_N_INSNS (160), /* DLGR */
218 COSTS_N_INSNS (71), /* DLR */
219 COSTS_N_INSNS (71), /* DR */
220 COSTS_N_INSNS (71), /* DSGFR */
221 COSTS_N_INSNS (71), /* DSGR */
224 extern int reload_completed
;
226 /* Save information from a "cmpxx" operation until the branch or scc is
227 emitted. A pair of a MODE_CC register and a const0_rtx if a compare
228 has been emitted already. */
229 rtx s390_compare_op0
, s390_compare_op1
;
231 /* Structure used to hold the components of a S/390 memory
232 address. A legitimate address on S/390 is of the general
234 base + index + displacement
235 where any of the components is optional.
237 base and index are registers of the class ADDR_REGS,
238 displacement is an unsigned 12-bit immediate constant. */
249 /* Which cpu are we tuning for. */
250 enum processor_type s390_tune
= PROCESSOR_max
;
251 enum processor_flags s390_tune_flags
;
252 /* Which instruction set architecture to use. */
253 enum processor_type s390_arch
;
254 enum processor_flags s390_arch_flags
;
256 HOST_WIDE_INT s390_warn_framesize
= 0;
257 HOST_WIDE_INT s390_stack_size
= 0;
258 HOST_WIDE_INT s390_stack_guard
= 0;
260 /* The following structure is embedded in the machine
261 specific part of struct function. */
263 struct GTY (()) s390_frame_layout
265 /* Offset within stack frame. */
266 HOST_WIDE_INT gprs_offset
;
267 HOST_WIDE_INT f0_offset
;
268 HOST_WIDE_INT f4_offset
;
269 HOST_WIDE_INT f8_offset
;
270 HOST_WIDE_INT backchain_offset
;
272 /* Number of first and last gpr where slots in the register
273 save area are reserved for. */
274 int first_save_gpr_slot
;
275 int last_save_gpr_slot
;
277 /* Number of first and last gpr to be saved, restored. */
279 int first_restore_gpr
;
281 int last_restore_gpr
;
283 /* Bits standing for floating point registers. Set, if the
284 respective register has to be saved. Starting with reg 16 (f0)
285 at the rightmost bit.
286 Bit 15 - 8 7 6 5 4 3 2 1 0
287 fpr 15 - 8 7 5 3 1 6 4 2 0
288 reg 31 - 24 23 22 21 20 19 18 17 16 */
289 unsigned int fpr_bitmap
;
291 /* Number of floating point registers f8-f15 which must be saved. */
294 /* Set if return address needs to be saved.
295 This flag is set by s390_return_addr_rtx if it could not use
296 the initial value of r14 and therefore depends on r14 saved
298 bool save_return_addr_p
;
300 /* Size of stack frame. */
301 HOST_WIDE_INT frame_size
;
304 /* Define the structure for the machine field in struct function. */
306 struct GTY(()) machine_function
308 struct s390_frame_layout frame_layout
;
310 /* Literal pool base register. */
313 /* True if we may need to perform branch splitting. */
314 bool split_branches_pending_p
;
316 /* Some local-dynamic TLS symbol name. */
317 const char *some_ld_name
;
319 bool has_landing_pad_p
;
322 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
324 #define cfun_frame_layout (cfun->machine->frame_layout)
325 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
326 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
327 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
328 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
330 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
333 /* Number of GPRs and FPRs used for argument passing. */
334 #define GP_ARG_NUM_REG 5
335 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
337 /* A couple of shortcuts. */
338 #define CONST_OK_FOR_J(x) \
339 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
340 #define CONST_OK_FOR_K(x) \
341 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
342 #define CONST_OK_FOR_Os(x) \
343 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
344 #define CONST_OK_FOR_Op(x) \
345 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
346 #define CONST_OK_FOR_On(x) \
347 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
349 #define REGNO_PAIR_OK(REGNO, MODE) \
350 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
352 static enum machine_mode
353 s390_libgcc_cmp_return_mode (void)
355 return TARGET_64BIT
? DImode
: SImode
;
358 static enum machine_mode
359 s390_libgcc_shift_count_mode (void)
361 return TARGET_64BIT
? DImode
: SImode
;
364 /* Return true if the back end supports mode MODE. */
366 s390_scalar_mode_supported_p (enum machine_mode mode
)
368 if (DECIMAL_FLOAT_MODE_P (mode
))
371 return default_scalar_mode_supported_p (mode
);
374 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
377 s390_set_has_landing_pad_p (bool value
)
379 cfun
->machine
->has_landing_pad_p
= value
;
382 /* If two condition code modes are compatible, return a condition code
383 mode which is compatible with both. Otherwise, return
386 static enum machine_mode
387 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
395 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
396 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
417 /* Return true if SET either doesn't set the CC register, or else
418 the source and destination have matching CC modes and that
419 CC mode is at least as constrained as REQ_MODE. */
422 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
424 enum machine_mode set_mode
;
426 gcc_assert (GET_CODE (set
) == SET
);
428 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
431 set_mode
= GET_MODE (SET_DEST (set
));
445 if (req_mode
!= set_mode
)
450 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
451 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
457 if (req_mode
!= CCAmode
)
465 return (GET_MODE (SET_SRC (set
)) == set_mode
);
468 /* Return true if every SET in INSN that sets the CC register
469 has source and destination with matching CC modes and that
470 CC mode is at least as constrained as REQ_MODE.
471 If REQ_MODE is VOIDmode, always return false. */
474 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
478 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
479 if (req_mode
== VOIDmode
)
482 if (GET_CODE (PATTERN (insn
)) == SET
)
483 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
485 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
486 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
488 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
489 if (GET_CODE (set
) == SET
)
490 if (!s390_match_ccmode_set (set
, req_mode
))
497 /* If a test-under-mask instruction can be used to implement
498 (compare (and ... OP1) OP2), return the CC mode required
499 to do that. Otherwise, return VOIDmode.
500 MIXED is true if the instruction can distinguish between
501 CC1 and CC2 for mixed selected bits (TMxx), it is false
502 if the instruction cannot (TM). */
505 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
509 /* ??? Fixme: should work on CONST_DOUBLE as well. */
510 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
513 /* Selected bits all zero: CC0.
514 e.g.: int a; if ((a & (16 + 128)) == 0) */
515 if (INTVAL (op2
) == 0)
518 /* Selected bits all one: CC3.
519 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
520 if (INTVAL (op2
) == INTVAL (op1
))
523 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
525 if ((a & (16 + 128)) == 16) -> CCT1
526 if ((a & (16 + 128)) == 128) -> CCT2 */
529 bit1
= exact_log2 (INTVAL (op2
));
530 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
531 if (bit0
!= -1 && bit1
!= -1)
532 return bit0
> bit1
? CCT1mode
: CCT2mode
;
538 /* Given a comparison code OP (EQ, NE, etc.) and the operands
539 OP0 and OP1 of a COMPARE, return the mode to be used for the
543 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
549 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
550 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
552 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
553 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
555 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
556 || GET_CODE (op1
) == NEG
)
557 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
560 if (GET_CODE (op0
) == AND
)
562 /* Check whether we can potentially do it via TM. */
563 enum machine_mode ccmode
;
564 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
565 if (ccmode
!= VOIDmode
)
567 /* Relax CCTmode to CCZmode to allow fall-back to AND
568 if that turns out to be beneficial. */
569 return ccmode
== CCTmode
? CCZmode
: ccmode
;
573 if (register_operand (op0
, HImode
)
574 && GET_CODE (op1
) == CONST_INT
575 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
577 if (register_operand (op0
, QImode
)
578 && GET_CODE (op1
) == CONST_INT
579 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
588 /* The only overflow condition of NEG and ABS happens when
589 -INT_MAX is used as parameter, which stays negative. So
590 we have an overflow from a positive value to a negative.
591 Using CCAP mode the resulting cc can be used for comparisons. */
592 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
593 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
596 /* If constants are involved in an add instruction it is possible to use
597 the resulting cc for comparisons with zero. Knowing the sign of the
598 constant the overflow behavior gets predictable. e.g.:
599 int a, b; if ((b = a + c) > 0)
600 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
601 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
602 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
604 if (INTVAL (XEXP((op0
), 1)) < 0)
618 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
619 && GET_CODE (op1
) != CONST_INT
)
625 if (GET_CODE (op0
) == PLUS
626 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
629 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
630 && GET_CODE (op1
) != CONST_INT
)
636 if (GET_CODE (op0
) == MINUS
637 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
640 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
641 && GET_CODE (op1
) != CONST_INT
)
650 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
651 that we can implement more efficiently. */
654 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
656 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
657 if ((*code
== EQ
|| *code
== NE
)
658 && *op1
== const0_rtx
659 && GET_CODE (*op0
) == ZERO_EXTRACT
660 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
661 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
662 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
664 rtx inner
= XEXP (*op0
, 0);
665 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
666 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
667 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
669 if (len
> 0 && len
< modesize
670 && pos
>= 0 && pos
+ len
<= modesize
671 && modesize
<= HOST_BITS_PER_WIDE_INT
)
673 unsigned HOST_WIDE_INT block
;
674 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
675 block
<<= modesize
- pos
- len
;
677 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
678 gen_int_mode (block
, GET_MODE (inner
)));
682 /* Narrow AND of memory against immediate to enable TM. */
683 if ((*code
== EQ
|| *code
== NE
)
684 && *op1
== const0_rtx
685 && GET_CODE (*op0
) == AND
686 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
687 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
689 rtx inner
= XEXP (*op0
, 0);
690 rtx mask
= XEXP (*op0
, 1);
692 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
693 if (GET_CODE (inner
) == SUBREG
694 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
695 && (GET_MODE_SIZE (GET_MODE (inner
))
696 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
698 & GET_MODE_MASK (GET_MODE (inner
))
699 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
701 inner
= SUBREG_REG (inner
);
703 /* Do not change volatile MEMs. */
704 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
706 int part
= s390_single_part (XEXP (*op0
, 1),
707 GET_MODE (inner
), QImode
, 0);
710 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
711 inner
= adjust_address_nv (inner
, QImode
, part
);
712 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
717 /* Narrow comparisons against 0xffff to HImode if possible. */
718 if ((*code
== EQ
|| *code
== NE
)
719 && GET_CODE (*op1
) == CONST_INT
720 && INTVAL (*op1
) == 0xffff
721 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
722 && (nonzero_bits (*op0
, GET_MODE (*op0
))
723 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
725 *op0
= gen_lowpart (HImode
, *op0
);
729 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
730 if (GET_CODE (*op0
) == UNSPEC
731 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
732 && XVECLEN (*op0
, 0) == 1
733 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
734 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
735 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
736 && *op1
== const0_rtx
)
738 enum rtx_code new_code
= UNKNOWN
;
741 case EQ
: new_code
= EQ
; break;
742 case NE
: new_code
= NE
; break;
743 case LT
: new_code
= GTU
; break;
744 case GT
: new_code
= LTU
; break;
745 case LE
: new_code
= GEU
; break;
746 case GE
: new_code
= LEU
; break;
750 if (new_code
!= UNKNOWN
)
752 *op0
= XVECEXP (*op0
, 0, 0);
757 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
758 if (GET_CODE (*op0
) == UNSPEC
759 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
760 && XVECLEN (*op0
, 0) == 1
761 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
762 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
763 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
764 && *op1
== const0_rtx
)
766 enum rtx_code new_code
= UNKNOWN
;
769 case EQ
: new_code
= EQ
; break;
770 case NE
: new_code
= NE
; break;
774 if (new_code
!= UNKNOWN
)
776 *op0
= XVECEXP (*op0
, 0, 0);
781 /* Simplify cascaded EQ, NE with const0_rtx. */
782 if ((*code
== NE
|| *code
== EQ
)
783 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
784 && GET_MODE (*op0
) == SImode
785 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
786 && REG_P (XEXP (*op0
, 0))
787 && XEXP (*op0
, 1) == const0_rtx
788 && *op1
== const0_rtx
)
790 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
791 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
795 *op0
= XEXP (*op0
, 0);
798 /* Prefer register over memory as first operand. */
799 if (MEM_P (*op0
) && REG_P (*op1
))
801 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
802 *code
= swap_condition (*code
);
806 /* Emit a compare instruction suitable to implement the comparison
807 OP0 CODE OP1. Return the correct condition RTL to be placed in
808 the IF_THEN_ELSE of the conditional branch testing the result. */
811 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
813 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
816 /* Do not output a redundant compare instruction if a compare_and_swap
817 pattern already computed the result and the machine modes are compatible. */
818 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
820 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
826 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
827 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
830 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
833 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
835 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
836 conditional branch testing the result. */
839 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx new_rtx
)
841 emit_insn (gen_sync_compare_and_swapsi (old
, mem
, cmp
, new_rtx
));
842 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
), const0_rtx
);
845 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
846 unconditional jump, else a conditional jump under condition COND. */
849 s390_emit_jump (rtx target
, rtx cond
)
853 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
855 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
857 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
858 emit_jump_insn (insn
);
861 /* Return branch condition mask to implement a branch
862 specified by CODE. Return -1 for invalid comparisons. */
865 s390_branch_condition_mask (rtx code
)
867 const int CC0
= 1 << 3;
868 const int CC1
= 1 << 2;
869 const int CC2
= 1 << 1;
870 const int CC3
= 1 << 0;
872 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
873 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
874 gcc_assert (XEXP (code
, 1) == const0_rtx
);
876 switch (GET_MODE (XEXP (code
, 0)))
880 switch (GET_CODE (code
))
883 case NE
: return CC1
| CC2
| CC3
;
889 switch (GET_CODE (code
))
892 case NE
: return CC0
| CC2
| CC3
;
898 switch (GET_CODE (code
))
901 case NE
: return CC0
| CC1
| CC3
;
907 switch (GET_CODE (code
))
910 case NE
: return CC0
| CC1
| CC2
;
916 switch (GET_CODE (code
))
918 case EQ
: return CC0
| CC2
;
919 case NE
: return CC1
| CC3
;
925 switch (GET_CODE (code
))
927 case LTU
: return CC2
| CC3
; /* carry */
928 case GEU
: return CC0
| CC1
; /* no carry */
934 switch (GET_CODE (code
))
936 case GTU
: return CC0
| CC1
; /* borrow */
937 case LEU
: return CC2
| CC3
; /* no borrow */
943 switch (GET_CODE (code
))
945 case EQ
: return CC0
| CC2
;
946 case NE
: return CC1
| CC3
;
947 case LTU
: return CC1
;
948 case GTU
: return CC3
;
949 case LEU
: return CC1
| CC2
;
950 case GEU
: return CC2
| CC3
;
955 switch (GET_CODE (code
))
958 case NE
: return CC1
| CC2
| CC3
;
959 case LTU
: return CC1
;
960 case GTU
: return CC2
;
961 case LEU
: return CC0
| CC1
;
962 case GEU
: return CC0
| CC2
;
968 switch (GET_CODE (code
))
971 case NE
: return CC2
| CC1
| CC3
;
972 case LTU
: return CC2
;
973 case GTU
: return CC1
;
974 case LEU
: return CC0
| CC2
;
975 case GEU
: return CC0
| CC1
;
981 switch (GET_CODE (code
))
984 case NE
: return CC1
| CC2
| CC3
;
985 case LT
: return CC1
| CC3
;
987 case LE
: return CC0
| CC1
| CC3
;
988 case GE
: return CC0
| CC2
;
994 switch (GET_CODE (code
))
997 case NE
: return CC1
| CC2
| CC3
;
999 case GT
: return CC2
| CC3
;
1000 case LE
: return CC0
| CC1
;
1001 case GE
: return CC0
| CC2
| CC3
;
1007 switch (GET_CODE (code
))
1009 case EQ
: return CC0
;
1010 case NE
: return CC1
| CC2
| CC3
;
1011 case LT
: return CC1
;
1012 case GT
: return CC2
;
1013 case LE
: return CC0
| CC1
;
1014 case GE
: return CC0
| CC2
;
1015 case UNORDERED
: return CC3
;
1016 case ORDERED
: return CC0
| CC1
| CC2
;
1017 case UNEQ
: return CC0
| CC3
;
1018 case UNLT
: return CC1
| CC3
;
1019 case UNGT
: return CC2
| CC3
;
1020 case UNLE
: return CC0
| CC1
| CC3
;
1021 case UNGE
: return CC0
| CC2
| CC3
;
1022 case LTGT
: return CC1
| CC2
;
1028 switch (GET_CODE (code
))
1030 case EQ
: return CC0
;
1031 case NE
: return CC2
| CC1
| CC3
;
1032 case LT
: return CC2
;
1033 case GT
: return CC1
;
1034 case LE
: return CC0
| CC2
;
1035 case GE
: return CC0
| CC1
;
1036 case UNORDERED
: return CC3
;
1037 case ORDERED
: return CC0
| CC2
| CC1
;
1038 case UNEQ
: return CC0
| CC3
;
1039 case UNLT
: return CC2
| CC3
;
1040 case UNGT
: return CC1
| CC3
;
1041 case UNLE
: return CC0
| CC2
| CC3
;
1042 case UNGE
: return CC0
| CC1
| CC3
;
1043 case LTGT
: return CC2
| CC1
;
1054 /* Return branch condition mask to implement a compare and branch
1055 specified by CODE. Return -1 for invalid comparisons. */
1058 s390_compare_and_branch_condition_mask (rtx code
)
1060 const int CC0
= 1 << 3;
1061 const int CC1
= 1 << 2;
1062 const int CC2
= 1 << 1;
1064 switch (GET_CODE (code
))
1088 /* If INV is false, return assembler mnemonic string to implement
1089 a branch specified by CODE. If INV is true, return mnemonic
1090 for the corresponding inverted branch. */
1093 s390_branch_condition_mnemonic (rtx code
, int inv
)
1097 static const char *const mnemonic
[16] =
1099 NULL
, "o", "h", "nle",
1100 "l", "nhe", "lh", "ne",
1101 "e", "nlh", "he", "nl",
1102 "le", "nh", "no", NULL
1105 if (GET_CODE (XEXP (code
, 0)) == REG
1106 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1107 && XEXP (code
, 1) == const0_rtx
)
1108 mask
= s390_branch_condition_mask (code
);
1110 mask
= s390_compare_and_branch_condition_mask (code
);
1112 gcc_assert (mask
>= 0);
1117 gcc_assert (mask
>= 1 && mask
<= 14);
1119 return mnemonic
[mask
];
1122 /* Return the part of op which has a value different from def.
1123 The size of the part is determined by mode.
1124 Use this function only if you already know that op really
1125 contains such a part. */
1127 unsigned HOST_WIDE_INT
1128 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1130 unsigned HOST_WIDE_INT value
= 0;
1131 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1132 int part_bits
= GET_MODE_BITSIZE (mode
);
1133 unsigned HOST_WIDE_INT part_mask
1134 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1137 for (i
= 0; i
< max_parts
; i
++)
1140 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1142 value
>>= part_bits
;
1144 if ((value
& part_mask
) != (def
& part_mask
))
1145 return value
& part_mask
;
1151 /* If OP is an integer constant of mode MODE with exactly one
1152 part of mode PART_MODE unequal to DEF, return the number of that
1153 part. Otherwise, return -1. */
1156 s390_single_part (rtx op
,
1157 enum machine_mode mode
,
1158 enum machine_mode part_mode
,
1161 unsigned HOST_WIDE_INT value
= 0;
1162 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1163 unsigned HOST_WIDE_INT part_mask
1164 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1167 if (GET_CODE (op
) != CONST_INT
)
1170 for (i
= 0; i
< n_parts
; i
++)
1173 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1175 value
>>= GET_MODE_BITSIZE (part_mode
);
1177 if ((value
& part_mask
) != (def
& part_mask
))
1185 return part
== -1 ? -1 : n_parts
- 1 - part
;
1188 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1189 bits and no other bits are set in IN. POS and LENGTH can be used
1190 to obtain the start position and the length of the bitfield.
1192 POS gives the position of the first bit of the bitfield counting
1193 from the lowest order bit starting with zero. In order to use this
1194 value for S/390 instructions this has to be converted to "bits big
1198 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1199 int *pos
, int *length
)
1204 unsigned HOST_WIDE_INT mask
= 1ULL;
1205 bool contiguous
= false;
1207 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1231 /* Calculate a mask for all bits beyond the contiguous bits. */
1232 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1237 if (tmp_length
+ tmp_pos
- 1 > size
)
1241 *length
= tmp_length
;
1249 /* Check whether we can (and want to) split a double-word
1250 move in mode MODE from SRC to DST into two single-word
1251 moves, moving the subword FIRST_SUBWORD first. */
1254 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1256 /* Floating point registers cannot be split. */
1257 if (FP_REG_P (src
) || FP_REG_P (dst
))
1260 /* We don't need to split if operands are directly accessible. */
1261 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1264 /* Non-offsettable memory references cannot be split. */
1265 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1266 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1269 /* Moving the first subword must not clobber a register
1270 needed to move the second subword. */
1271 if (register_operand (dst
, mode
))
1273 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1274 if (reg_overlap_mentioned_p (subreg
, src
))
1281 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1282 and [MEM2, MEM2 + SIZE] do overlap and false
1286 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1288 rtx addr1
, addr2
, addr_delta
;
1289 HOST_WIDE_INT delta
;
1291 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1297 addr1
= XEXP (mem1
, 0);
1298 addr2
= XEXP (mem2
, 0);
1300 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1302 /* This overlapping check is used by peepholes merging memory block operations.
1303 Overlapping operations would otherwise be recognized by the S/390 hardware
1304 and would fall back to a slower implementation. Allowing overlapping
1305 operations would lead to slow code but not to wrong code. Therefore we are
1306 somewhat optimistic if we cannot prove that the memory blocks are
1308 That's why we return false here although this may accept operations on
1309 overlapping memory areas. */
1310 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1313 delta
= INTVAL (addr_delta
);
1316 || (delta
> 0 && delta
< size
)
1317 || (delta
< 0 && -delta
< size
))
1323 /* Check whether the address of memory reference MEM2 equals exactly
1324 the address of memory reference MEM1 plus DELTA. Return true if
1325 we can prove this to be the case, false otherwise. */
1328 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1330 rtx addr1
, addr2
, addr_delta
;
1332 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1335 addr1
= XEXP (mem1
, 0);
1336 addr2
= XEXP (mem2
, 0);
1338 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1339 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1345 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1348 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1351 enum machine_mode wmode
= mode
;
1352 rtx dst
= operands
[0];
1353 rtx src1
= operands
[1];
1354 rtx src2
= operands
[2];
1357 /* If we cannot handle the operation directly, use a temp register. */
1358 if (!s390_logical_operator_ok_p (operands
))
1359 dst
= gen_reg_rtx (mode
);
1361 /* QImode and HImode patterns make sense only if we have a destination
1362 in memory. Otherwise perform the operation in SImode. */
1363 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1366 /* Widen operands if required. */
1369 if (GET_CODE (dst
) == SUBREG
1370 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1372 else if (REG_P (dst
))
1373 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1375 dst
= gen_reg_rtx (wmode
);
1377 if (GET_CODE (src1
) == SUBREG
1378 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1380 else if (GET_MODE (src1
) != VOIDmode
)
1381 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1383 if (GET_CODE (src2
) == SUBREG
1384 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1386 else if (GET_MODE (src2
) != VOIDmode
)
1387 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1390 /* Emit the instruction. */
1391 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1392 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1393 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1395 /* Fix up the destination if needed. */
1396 if (dst
!= operands
[0])
1397 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1400 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1403 s390_logical_operator_ok_p (rtx
*operands
)
1405 /* If the destination operand is in memory, it needs to coincide
1406 with one of the source operands. After reload, it has to be
1407 the first source operand. */
1408 if (GET_CODE (operands
[0]) == MEM
)
1409 return rtx_equal_p (operands
[0], operands
[1])
1410 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1415 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1416 operand IMMOP to switch from SS to SI type instructions. */
1419 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1421 int def
= code
== AND
? -1 : 0;
1425 gcc_assert (GET_CODE (*memop
) == MEM
);
1426 gcc_assert (!MEM_VOLATILE_P (*memop
));
1428 mask
= s390_extract_part (*immop
, QImode
, def
);
1429 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1430 gcc_assert (part
>= 0);
1432 *memop
= adjust_address (*memop
, QImode
, part
);
1433 *immop
= gen_int_mode (mask
, QImode
);
1437 /* How to allocate a 'struct machine_function'. */
1439 static struct machine_function
*
1440 s390_init_machine_status (void)
1442 return GGC_CNEW (struct machine_function
);
1445 /* Change optimizations to be performed, depending on the
1448 LEVEL is the optimization level specified; 2 if `-O2' is
1449 specified, 1 if `-O' is specified, and 0 if neither is specified.
1451 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1454 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1456 /* ??? There are apparently still problems with -fcaller-saves. */
1457 flag_caller_saves
= 0;
1459 /* By default, always emit DWARF-2 unwind info. This allows debugging
1460 without maintaining a stack frame back-chain. */
1461 flag_asynchronous_unwind_tables
= 1;
1463 /* Use MVCLE instructions to decrease code size if requested. */
1465 target_flags
|= MASK_MVCLE
;
1468 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1469 to the associated processor_type and processor_flags if so. */
1472 s390_handle_arch_option (const char *arg
,
1473 enum processor_type
*type
,
1474 enum processor_flags
*flags
)
1478 const char *const name
; /* processor name or nickname. */
1479 const enum processor_type processor
;
1480 const enum processor_flags flags
;
1482 const processor_alias_table
[] =
1484 {"g5", PROCESSOR_9672_G5
, PF_IEEE_FLOAT
},
1485 {"g6", PROCESSOR_9672_G6
, PF_IEEE_FLOAT
},
1486 {"z900", PROCESSOR_2064_Z900
, PF_IEEE_FLOAT
| PF_ZARCH
},
1487 {"z990", PROCESSOR_2084_Z990
, PF_IEEE_FLOAT
| PF_ZARCH
1488 | PF_LONG_DISPLACEMENT
},
1489 {"z9-109", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1490 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
},
1491 {"z9-ec", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1492 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
},
1493 {"z10", PROCESSOR_2097_Z10
, PF_IEEE_FLOAT
| PF_ZARCH
1494 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
},
1498 for (i
= 0; i
< ARRAY_SIZE (processor_alias_table
); i
++)
1499 if (strcmp (arg
, processor_alias_table
[i
].name
) == 0)
1501 *type
= processor_alias_table
[i
].processor
;
1502 *flags
= processor_alias_table
[i
].flags
;
1508 /* Implement TARGET_HANDLE_OPTION. */
1511 s390_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
1516 return s390_handle_arch_option (arg
, &s390_arch
, &s390_arch_flags
);
1518 case OPT_mstack_guard_
:
1519 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_guard
) != 1)
1521 if (exact_log2 (s390_stack_guard
) == -1)
1522 error ("stack guard value must be an exact power of 2");
1525 case OPT_mstack_size_
:
1526 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_size
) != 1)
1528 if (exact_log2 (s390_stack_size
) == -1)
1529 error ("stack size must be an exact power of 2");
1533 return s390_handle_arch_option (arg
, &s390_tune
, &s390_tune_flags
);
1535 case OPT_mwarn_framesize_
:
1536 return sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_warn_framesize
) == 1;
1544 override_options (void)
1546 /* Set up function hooks. */
1547 init_machine_status
= s390_init_machine_status
;
1549 /* Architecture mode defaults according to ABI. */
1550 if (!(target_flags_explicit
& MASK_ZARCH
))
1553 target_flags
|= MASK_ZARCH
;
1555 target_flags
&= ~MASK_ZARCH
;
1558 /* Determine processor architectural level. */
1559 if (!s390_arch_string
)
1561 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1562 s390_handle_arch_option (s390_arch_string
, &s390_arch
, &s390_arch_flags
);
1565 /* Determine processor to tune for. */
1566 if (s390_tune
== PROCESSOR_max
)
1568 s390_tune
= s390_arch
;
1569 s390_tune_flags
= s390_arch_flags
;
1572 /* Sanity checks. */
1573 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1574 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1575 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1576 error ("64-bit ABI not supported in ESA/390 mode");
1578 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1580 if (target_flags_explicit
& MASK_HARD_DFP
)
1582 if (!TARGET_CPU_DFP
)
1583 error ("Hardware decimal floating point instructions"
1584 " not available on %s", s390_arch_string
);
1586 error ("Hardware decimal floating point instructions"
1587 " not available in ESA/390 mode");
1590 target_flags
&= ~MASK_HARD_DFP
;
1593 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1595 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1596 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1598 target_flags
&= ~MASK_HARD_DFP
;
1601 /* Set processor cost function. */
1604 case PROCESSOR_2084_Z990
:
1605 s390_cost
= &z990_cost
;
1607 case PROCESSOR_2094_Z9_109
:
1608 s390_cost
= &z9_109_cost
;
1610 case PROCESSOR_2097_Z10
:
1611 s390_cost
= &z10_cost
;
1614 s390_cost
= &z900_cost
;
1617 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1618 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1621 if (s390_stack_size
)
1623 if (s390_stack_guard
>= s390_stack_size
)
1624 error ("stack size must be greater than the stack guard value");
1625 else if (s390_stack_size
> 1 << 16)
1626 error ("stack size must not be greater than 64k");
1628 else if (s390_stack_guard
)
1629 error ("-mstack-guard implies use of -mstack-size");
1631 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1632 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1633 target_flags
|= MASK_LONG_DOUBLE_128
;
1637 /* Map for smallest class containing reg regno. */
1639 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1640 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1641 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1642 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1643 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1644 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1645 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1646 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1647 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1648 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1649 ACCESS_REGS
, ACCESS_REGS
1652 /* Return attribute type of insn. */
1654 static enum attr_type
1655 s390_safe_attr_type (rtx insn
)
1657 if (recog_memoized (insn
) >= 0)
1658 return get_attr_type (insn
);
1663 /* Return true if DISP is a valid short displacement. */
1666 s390_short_displacement (rtx disp
)
1668 /* No displacement is OK. */
1672 /* Integer displacement in range. */
1673 if (GET_CODE (disp
) == CONST_INT
)
1674 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1676 /* GOT offset is not OK, the GOT can be large. */
1677 if (GET_CODE (disp
) == CONST
1678 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1679 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1680 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1683 /* All other symbolic constants are literal pool references,
1684 which are OK as the literal pool must be small. */
1685 if (GET_CODE (disp
) == CONST
)
1691 /* Decompose a RTL expression ADDR for a memory address into
1692 its components, returned in OUT.
1694 Returns false if ADDR is not a valid memory address, true
1695 otherwise. If OUT is NULL, don't return the components,
1696 but check for validity only.
1698 Note: Only addresses in canonical form are recognized.
1699 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1700 canonical form so that they will be recognized. */
1703 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1705 HOST_WIDE_INT offset
= 0;
1706 rtx base
= NULL_RTX
;
1707 rtx indx
= NULL_RTX
;
1708 rtx disp
= NULL_RTX
;
1710 bool pointer
= false;
1711 bool base_ptr
= false;
1712 bool indx_ptr
= false;
1713 bool literal_pool
= false;
1715 /* We may need to substitute the literal pool base register into the address
1716 below. However, at this point we do not know which register is going to
1717 be used as base, so we substitute the arg pointer register. This is going
1718 to be treated as holding a pointer below -- it shouldn't be used for any
1720 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1722 /* Decompose address into base + index + displacement. */
1724 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1727 else if (GET_CODE (addr
) == PLUS
)
1729 rtx op0
= XEXP (addr
, 0);
1730 rtx op1
= XEXP (addr
, 1);
1731 enum rtx_code code0
= GET_CODE (op0
);
1732 enum rtx_code code1
= GET_CODE (op1
);
1734 if (code0
== REG
|| code0
== UNSPEC
)
1736 if (code1
== REG
|| code1
== UNSPEC
)
1738 indx
= op0
; /* index + base */
1744 base
= op0
; /* base + displacement */
1749 else if (code0
== PLUS
)
1751 indx
= XEXP (op0
, 0); /* index + base + disp */
1752 base
= XEXP (op0
, 1);
1763 disp
= addr
; /* displacement */
1765 /* Extract integer part of displacement. */
1769 if (GET_CODE (disp
) == CONST_INT
)
1771 offset
= INTVAL (disp
);
1774 else if (GET_CODE (disp
) == CONST
1775 && GET_CODE (XEXP (disp
, 0)) == PLUS
1776 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1778 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1779 disp
= XEXP (XEXP (disp
, 0), 0);
1783 /* Strip off CONST here to avoid special case tests later. */
1784 if (disp
&& GET_CODE (disp
) == CONST
)
1785 disp
= XEXP (disp
, 0);
1787 /* We can convert literal pool addresses to
1788 displacements by basing them off the base register. */
1789 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1791 /* Either base or index must be free to hold the base register. */
1793 base
= fake_pool_base
, literal_pool
= true;
1795 indx
= fake_pool_base
, literal_pool
= true;
1799 /* Mark up the displacement. */
1800 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1801 UNSPEC_LTREL_OFFSET
);
1804 /* Validate base register. */
1807 if (GET_CODE (base
) == UNSPEC
)
1808 switch (XINT (base
, 1))
1812 disp
= gen_rtx_UNSPEC (Pmode
,
1813 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1814 UNSPEC_LTREL_OFFSET
);
1818 base
= XVECEXP (base
, 0, 1);
1821 case UNSPEC_LTREL_BASE
:
1822 if (XVECLEN (base
, 0) == 1)
1823 base
= fake_pool_base
, literal_pool
= true;
1825 base
= XVECEXP (base
, 0, 1);
1833 || (GET_MODE (base
) != SImode
1834 && GET_MODE (base
) != Pmode
))
1837 if (REGNO (base
) == STACK_POINTER_REGNUM
1838 || REGNO (base
) == FRAME_POINTER_REGNUM
1839 || ((reload_completed
|| reload_in_progress
)
1840 && frame_pointer_needed
1841 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1842 || REGNO (base
) == ARG_POINTER_REGNUM
1844 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1845 pointer
= base_ptr
= true;
1847 if ((reload_completed
|| reload_in_progress
)
1848 && base
== cfun
->machine
->base_reg
)
1849 pointer
= base_ptr
= literal_pool
= true;
1852 /* Validate index register. */
1855 if (GET_CODE (indx
) == UNSPEC
)
1856 switch (XINT (indx
, 1))
1860 disp
= gen_rtx_UNSPEC (Pmode
,
1861 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1862 UNSPEC_LTREL_OFFSET
);
1866 indx
= XVECEXP (indx
, 0, 1);
1869 case UNSPEC_LTREL_BASE
:
1870 if (XVECLEN (indx
, 0) == 1)
1871 indx
= fake_pool_base
, literal_pool
= true;
1873 indx
= XVECEXP (indx
, 0, 1);
1881 || (GET_MODE (indx
) != SImode
1882 && GET_MODE (indx
) != Pmode
))
1885 if (REGNO (indx
) == STACK_POINTER_REGNUM
1886 || REGNO (indx
) == FRAME_POINTER_REGNUM
1887 || ((reload_completed
|| reload_in_progress
)
1888 && frame_pointer_needed
1889 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1890 || REGNO (indx
) == ARG_POINTER_REGNUM
1892 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1893 pointer
= indx_ptr
= true;
1895 if ((reload_completed
|| reload_in_progress
)
1896 && indx
== cfun
->machine
->base_reg
)
1897 pointer
= indx_ptr
= literal_pool
= true;
1900 /* Prefer to use pointer as base, not index. */
1901 if (base
&& indx
&& !base_ptr
1902 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1909 /* Validate displacement. */
1912 /* If virtual registers are involved, the displacement will change later
1913 anyway as the virtual registers get eliminated. This could make a
1914 valid displacement invalid, but it is more likely to make an invalid
1915 displacement valid, because we sometimes access the register save area
1916 via negative offsets to one of those registers.
1917 Thus we don't check the displacement for validity here. If after
1918 elimination the displacement turns out to be invalid after all,
1919 this is fixed up by reload in any case. */
1920 if (base
!= arg_pointer_rtx
1921 && indx
!= arg_pointer_rtx
1922 && base
!= return_address_pointer_rtx
1923 && indx
!= return_address_pointer_rtx
1924 && base
!= frame_pointer_rtx
1925 && indx
!= frame_pointer_rtx
1926 && base
!= virtual_stack_vars_rtx
1927 && indx
!= virtual_stack_vars_rtx
)
1928 if (!DISP_IN_RANGE (offset
))
1933 /* All the special cases are pointers. */
1936 /* In the small-PIC case, the linker converts @GOT
1937 and @GOTNTPOFF offsets to possible displacements. */
1938 if (GET_CODE (disp
) == UNSPEC
1939 && (XINT (disp
, 1) == UNSPEC_GOT
1940 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
1946 /* Accept pool label offsets. */
1947 else if (GET_CODE (disp
) == UNSPEC
1948 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
1951 /* Accept literal pool references. */
1952 else if (GET_CODE (disp
) == UNSPEC
1953 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
1955 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
1958 /* If we have an offset, make sure it does not
1959 exceed the size of the constant pool entry. */
1960 rtx sym
= XVECEXP (disp
, 0, 0);
1961 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
1964 orig_disp
= plus_constant (orig_disp
, offset
);
1979 out
->disp
= orig_disp
;
1980 out
->pointer
= pointer
;
1981 out
->literal_pool
= literal_pool
;
1987 /* Decompose a RTL expression OP for a shift count into its components,
1988 and return the base register in BASE and the offset in OFFSET.
1990 Return true if OP is a valid shift count, false if not. */
1993 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
1995 HOST_WIDE_INT off
= 0;
1997 /* We can have an integer constant, an address register,
1998 or a sum of the two. */
1999 if (GET_CODE (op
) == CONST_INT
)
2004 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2006 off
= INTVAL (XEXP (op
, 1));
2009 while (op
&& GET_CODE (op
) == SUBREG
)
2010 op
= SUBREG_REG (op
);
2012 if (op
&& GET_CODE (op
) != REG
)
2024 /* Return true if CODE is a valid address without index. */
2027 s390_legitimate_address_without_index_p (rtx op
)
2029 struct s390_address addr
;
2031 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2040 /* Evaluates constraint strings described by the regular expression
2041 ([A|B](Q|R|S|T))|U|W and returns 1 if OP is a valid operand for the
2042 constraint given in STR, or 0 else. */
2045 s390_mem_constraint (const char *str
, rtx op
)
2047 struct s390_address addr
;
2050 /* Check for offsettable variants of memory constraints. */
2053 /* Only accept non-volatile MEMs. */
2054 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2057 if ((reload_completed
|| reload_in_progress
)
2058 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2064 /* Check for non-literal-pool variants of memory constraints. */
2067 if (GET_CODE (op
) != MEM
)
2069 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2071 if (addr
.literal_pool
)
2080 if (GET_CODE (op
) != MEM
)
2082 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2087 if (TARGET_LONG_DISPLACEMENT
)
2089 if (!s390_short_displacement (addr
.disp
))
2095 if (GET_CODE (op
) != MEM
)
2098 if (TARGET_LONG_DISPLACEMENT
)
2100 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2102 if (!s390_short_displacement (addr
.disp
))
2108 if (!TARGET_LONG_DISPLACEMENT
)
2110 if (GET_CODE (op
) != MEM
)
2112 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2116 if (s390_short_displacement (addr
.disp
))
2121 if (!TARGET_LONG_DISPLACEMENT
)
2123 if (GET_CODE (op
) != MEM
)
2125 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2127 if (s390_short_displacement (addr
.disp
))
2132 if (TARGET_LONG_DISPLACEMENT
)
2134 if (!s390_decompose_address (op
, &addr
))
2136 if (!s390_short_displacement (addr
.disp
))
2142 if (!TARGET_LONG_DISPLACEMENT
)
2144 if (!s390_decompose_address (op
, &addr
))
2146 if (s390_short_displacement (addr
.disp
))
2151 /* Simply check for the basic form of a shift count. Reload will
2152 take care of making sure we have a proper base register. */
2153 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2166 /* Evaluates constraint strings starting with letter O. Input
2167 parameter C is the second letter following the "O" in the constraint
2168 string. Returns 1 if VALUE meets the respective constraint and 0
2172 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2180 return trunc_int_for_mode (value
, SImode
) == value
;
2184 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2187 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2195 /* Evaluates constraint strings starting with letter N. Parameter STR
2196 contains the letters following letter "N" in the constraint string.
2197 Returns true if VALUE matches the constraint. */
2200 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2202 enum machine_mode mode
, part_mode
;
2204 int part
, part_goal
;
2210 part_goal
= str
[0] - '0';
2254 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2257 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2260 if (part_goal
!= -1 && part_goal
!= part
)
2267 /* Returns true if the input parameter VALUE is a float zero. */
2270 s390_float_const_zero_p (rtx value
)
2272 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2273 && value
== CONST0_RTX (GET_MODE (value
)));
2277 /* Compute a (partial) cost for rtx X. Return true if the complete
2278 cost has been computed, and false if subexpressions should be
2279 scanned. In either case, *TOTAL contains the cost result.
2280 CODE contains GET_CODE (x), OUTER_CODE contains the code
2281 of the superexpression of x. */
2284 s390_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2285 bool speed ATTRIBUTE_UNUSED
)
2308 *total
= COSTS_N_INSNS (1);
2313 /* Check for multiply and add. */
2314 if ((GET_MODE (x
) == DFmode
|| GET_MODE (x
) == SFmode
)
2315 && GET_CODE (XEXP (x
, 0)) == MULT
2316 && TARGET_HARD_FLOAT
&& TARGET_FUSED_MADD
)
2318 /* This is the multiply and add case. */
2319 if (GET_MODE (x
) == DFmode
)
2320 *total
= s390_cost
->madbr
;
2322 *total
= s390_cost
->maebr
;
2323 *total
+= (rtx_cost (XEXP (XEXP (x
, 0), 0), MULT
, speed
)
2324 + rtx_cost (XEXP (XEXP (x
, 0), 1), MULT
, speed
)
2325 + rtx_cost (XEXP (x
, 1), (enum rtx_code
) code
, speed
));
2326 return true; /* Do not do an additional recursive descent. */
2328 *total
= COSTS_N_INSNS (1);
2332 switch (GET_MODE (x
))
2336 rtx left
= XEXP (x
, 0);
2337 rtx right
= XEXP (x
, 1);
2338 if (GET_CODE (right
) == CONST_INT
2339 && CONST_OK_FOR_K (INTVAL (right
)))
2340 *total
= s390_cost
->mhi
;
2341 else if (GET_CODE (left
) == SIGN_EXTEND
)
2342 *total
= s390_cost
->mh
;
2344 *total
= s390_cost
->ms
; /* msr, ms, msy */
2349 rtx left
= XEXP (x
, 0);
2350 rtx right
= XEXP (x
, 1);
2353 if (GET_CODE (right
) == CONST_INT
2354 && CONST_OK_FOR_K (INTVAL (right
)))
2355 *total
= s390_cost
->mghi
;
2356 else if (GET_CODE (left
) == SIGN_EXTEND
)
2357 *total
= s390_cost
->msgf
;
2359 *total
= s390_cost
->msg
; /* msgr, msg */
2361 else /* TARGET_31BIT */
2363 if (GET_CODE (left
) == SIGN_EXTEND
2364 && GET_CODE (right
) == SIGN_EXTEND
)
2365 /* mulsidi case: mr, m */
2366 *total
= s390_cost
->m
;
2367 else if (GET_CODE (left
) == ZERO_EXTEND
2368 && GET_CODE (right
) == ZERO_EXTEND
2369 && TARGET_CPU_ZARCH
)
2370 /* umulsidi case: ml, mlr */
2371 *total
= s390_cost
->ml
;
2373 /* Complex calculation is required. */
2374 *total
= COSTS_N_INSNS (40);
2380 *total
= s390_cost
->mult_df
;
2383 *total
= s390_cost
->mxbr
;
2392 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2393 *total
= s390_cost
->dlgr
;
2394 else if (GET_MODE (x
) == DImode
)
2396 rtx right
= XEXP (x
, 1);
2397 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2398 *total
= s390_cost
->dlr
;
2399 else /* 64 by 64 bit division */
2400 *total
= s390_cost
->dlgr
;
2402 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2403 *total
= s390_cost
->dlr
;
2408 if (GET_MODE (x
) == DImode
)
2410 rtx right
= XEXP (x
, 1);
2411 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2413 *total
= s390_cost
->dsgfr
;
2415 *total
= s390_cost
->dr
;
2416 else /* 64 by 64 bit division */
2417 *total
= s390_cost
->dsgr
;
2419 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2420 *total
= s390_cost
->dlr
;
2421 else if (GET_MODE (x
) == SFmode
)
2423 *total
= s390_cost
->debr
;
2425 else if (GET_MODE (x
) == DFmode
)
2427 *total
= s390_cost
->ddbr
;
2429 else if (GET_MODE (x
) == TFmode
)
2431 *total
= s390_cost
->dxbr
;
2436 if (GET_MODE (x
) == SFmode
)
2437 *total
= s390_cost
->sqebr
;
2438 else if (GET_MODE (x
) == DFmode
)
2439 *total
= s390_cost
->sqdbr
;
2441 *total
= s390_cost
->sqxbr
;
2446 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2447 || outer_code
== PLUS
|| outer_code
== MINUS
2448 || outer_code
== COMPARE
)
2453 *total
= COSTS_N_INSNS (1);
2454 if (GET_CODE (XEXP (x
, 0)) == AND
2455 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2456 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2458 rtx op0
= XEXP (XEXP (x
, 0), 0);
2459 rtx op1
= XEXP (XEXP (x
, 0), 1);
2460 rtx op2
= XEXP (x
, 1);
2462 if (memory_operand (op0
, GET_MODE (op0
))
2463 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2465 if (register_operand (op0
, GET_MODE (op0
))
2466 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2476 /* Return the cost of an address rtx ADDR. */
2479 s390_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
2481 struct s390_address ad
;
2482 if (!s390_decompose_address (addr
, &ad
))
2485 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2488 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2489 otherwise return 0. */
2492 tls_symbolic_operand (rtx op
)
2494 if (GET_CODE (op
) != SYMBOL_REF
)
2496 return SYMBOL_REF_TLS_MODEL (op
);
2499 /* Split DImode access register reference REG (on 64-bit) into its constituent
2500 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2501 gen_highpart cannot be used as they assume all registers are word-sized,
2502 while our access registers have only half that size. */
2505 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2507 gcc_assert (TARGET_64BIT
);
2508 gcc_assert (ACCESS_REG_P (reg
));
2509 gcc_assert (GET_MODE (reg
) == DImode
);
2510 gcc_assert (!(REGNO (reg
) & 1));
2512 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2513 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2516 /* Return true if OP contains a symbol reference */
2519 symbolic_reference_mentioned_p (rtx op
)
2524 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2527 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2528 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2534 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2535 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2539 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2546 /* Return true if OP contains a reference to a thread-local symbol. */
2549 tls_symbolic_reference_mentioned_p (rtx op
)
2554 if (GET_CODE (op
) == SYMBOL_REF
)
2555 return tls_symbolic_operand (op
);
2557 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2558 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2564 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2565 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2569 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2577 /* Return true if OP is a legitimate general operand when
2578 generating PIC code. It is given that flag_pic is on
2579 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2582 legitimate_pic_operand_p (rtx op
)
2584 /* Accept all non-symbolic constants. */
2585 if (!SYMBOLIC_CONST (op
))
2588 /* Reject everything else; must be handled
2589 via emit_symbolic_move. */
2593 /* Returns true if the constant value OP is a legitimate general operand.
2594 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2597 legitimate_constant_p (rtx op
)
2599 /* Accept all non-symbolic constants. */
2600 if (!SYMBOLIC_CONST (op
))
2603 /* Accept immediate LARL operands. */
2604 if (TARGET_CPU_ZARCH
&& larl_operand (op
, VOIDmode
))
2607 /* Thread-local symbols are never legal constants. This is
2608 so that emit_call knows that computing such addresses
2609 might require a function call. */
2610 if (TLS_SYMBOLIC_CONST (op
))
2613 /* In the PIC case, symbolic constants must *not* be
2614 forced into the literal pool. We accept them here,
2615 so that they will be handled by emit_symbolic_move. */
2619 /* All remaining non-PIC symbolic constants are
2620 forced into the literal pool. */
2624 /* Determine if it's legal to put X into the constant pool. This
2625 is not possible if X contains the address of a symbol that is
2626 not constant (TLS) or not known at final link time (PIC). */
2629 s390_cannot_force_const_mem (rtx x
)
2631 switch (GET_CODE (x
))
2635 /* Accept all non-symbolic constants. */
2639 /* Labels are OK iff we are non-PIC. */
2640 return flag_pic
!= 0;
2643 /* 'Naked' TLS symbol references are never OK,
2644 non-TLS symbols are OK iff we are non-PIC. */
2645 if (tls_symbolic_operand (x
))
2648 return flag_pic
!= 0;
2651 return s390_cannot_force_const_mem (XEXP (x
, 0));
2654 return s390_cannot_force_const_mem (XEXP (x
, 0))
2655 || s390_cannot_force_const_mem (XEXP (x
, 1));
2658 switch (XINT (x
, 1))
2660 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2661 case UNSPEC_LTREL_OFFSET
:
2669 case UNSPEC_GOTNTPOFF
:
2670 case UNSPEC_INDNTPOFF
:
2673 /* If the literal pool shares the code section, be put
2674 execute template placeholders into the pool as well. */
2676 return TARGET_CPU_ZARCH
;
2688 /* Returns true if the constant value OP is a legitimate general
2689 operand during and after reload. The difference to
2690 legitimate_constant_p is that this function will not accept
2691 a constant that would need to be forced to the literal pool
2692 before it can be used as operand. */
2695 legitimate_reload_constant_p (rtx op
)
2697 /* Accept la(y) operands. */
2698 if (GET_CODE (op
) == CONST_INT
2699 && DISP_IN_RANGE (INTVAL (op
)))
2702 /* Accept l(g)hi/l(g)fi operands. */
2703 if (GET_CODE (op
) == CONST_INT
2704 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2707 /* Accept lliXX operands. */
2709 && GET_CODE (op
) == CONST_INT
2710 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2711 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2715 && GET_CODE (op
) == CONST_INT
2716 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2717 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2720 /* Accept larl operands. */
2721 if (TARGET_CPU_ZARCH
2722 && larl_operand (op
, VOIDmode
))
2725 /* Accept lzXX operands. */
2726 if (GET_CODE (op
) == CONST_DOUBLE
2727 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', "G"))
2730 /* Accept double-word operands that can be split. */
2731 if (GET_CODE (op
) == CONST_INT
2732 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2734 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2735 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2736 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2737 return legitimate_reload_constant_p (hi
)
2738 && legitimate_reload_constant_p (lo
);
2741 /* Everything else cannot be handled without reload. */
2745 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2746 return the class of reg to actually use. */
2749 s390_preferred_reload_class (rtx op
, enum reg_class rclass
)
2751 switch (GET_CODE (op
))
2753 /* Constants we cannot reload must be forced into the
2758 if (legitimate_reload_constant_p (op
))
2763 /* If a symbolic constant or a PLUS is reloaded,
2764 it is most likely being used as an address, so
2765 prefer ADDR_REGS. If 'class' is not a superset
2766 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2771 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2783 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2784 and return these parts in SYMREF and ADDEND. You can pass NULL in
2785 SYMREF and/or ADDEND if you are not interested in these values. */
2788 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2790 HOST_WIDE_INT tmpaddend
= 0;
2792 if (GET_CODE (addr
) == CONST
)
2793 addr
= XEXP (addr
, 0);
2795 if (GET_CODE (addr
) == PLUS
)
2797 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2798 && CONST_INT_P (XEXP (addr
, 1)))
2800 tmpaddend
= INTVAL (XEXP (addr
, 1));
2801 addr
= XEXP (addr
, 0);
2807 if (GET_CODE (addr
) != SYMBOL_REF
)
2813 *addend
= tmpaddend
;
2818 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2819 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2823 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2825 HOST_WIDE_INT addend
;
2828 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2831 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
2832 && !(addend
& (alignment
- 1)));
2835 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2836 operand SCRATCH is used to reload the even part of the address and
2840 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
2842 HOST_WIDE_INT addend
;
2845 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2849 /* Easy case. The addend is even so larl will do fine. */
2850 emit_move_insn (reg
, addr
);
2853 /* We can leave the scratch register untouched if the target
2854 register is a valid base register. */
2855 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
2856 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
2859 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
2860 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
2863 emit_move_insn (scratch
,
2864 gen_rtx_CONST (Pmode
,
2865 gen_rtx_PLUS (Pmode
, symref
,
2866 GEN_INT (addend
- 1))));
2868 emit_move_insn (scratch
, symref
);
2870 /* Increment the address using la in order to avoid clobbering cc. */
2871 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
2875 /* Generate what is necessary to move between REG and MEM using
2876 SCRATCH. The direction is given by TOMEM. */
2879 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
2881 /* Reload might have pulled a constant out of the literal pool.
2882 Force it back in. */
2883 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
2884 || GET_CODE (mem
) == CONST
)
2885 mem
= force_const_mem (GET_MODE (reg
), mem
);
2887 gcc_assert (MEM_P (mem
));
2889 /* For a load from memory we can leave the scratch register
2890 untouched if the target register is a valid base register. */
2892 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
2893 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
2894 && GET_MODE (reg
) == GET_MODE (scratch
))
2897 /* Load address into scratch register. Since we can't have a
2898 secondary reload for a secondary reload we have to cover the case
2899 where larl would need a secondary reload here as well. */
2900 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
2902 /* Now we can use a standard load/store to do the move. */
2904 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
2906 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
2909 /* Inform reload about cases where moving X with a mode MODE to a register in
2910 RCLASS requires an extra scratch or immediate register. Return the class
2911 needed for the immediate register. */
2913 static enum reg_class
2914 s390_secondary_reload (bool in_p
, rtx x
, enum reg_class rclass
,
2915 enum machine_mode mode
, secondary_reload_info
*sri
)
2917 /* Intermediate register needed. */
2918 if (reg_classes_intersect_p (CC_REGS
, rclass
))
2919 return GENERAL_REGS
;
2923 /* On z10 several optimizer steps may generate larl operands with
2926 && s390_symref_operand_p (x
, NULL
, NULL
)
2928 && !s390_check_symref_alignment (x
, 2))
2929 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2930 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
2932 /* On z10 we need a scratch register when moving QI, TI or floating
2933 point mode values from or to a memory location with a SYMBOL_REF
2934 or if the symref addend of a SI or DI move is not aligned to the
2935 width of the access. */
2937 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
2938 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
2939 || (!TARGET_64BIT
&& mode
== DImode
)
2940 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
2941 && (!s390_check_symref_alignment (XEXP (x
, 0),
2942 GET_MODE_SIZE (mode
))))))
2944 #define __SECONDARY_RELOAD_CASE(M,m) \
2947 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2948 CODE_FOR_reload##m##di_tomem_z10; \
2950 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
2951 CODE_FOR_reload##m##si_tomem_z10; \
2954 switch (GET_MODE (x
))
2956 __SECONDARY_RELOAD_CASE (QI
, qi
);
2957 __SECONDARY_RELOAD_CASE (HI
, hi
);
2958 __SECONDARY_RELOAD_CASE (SI
, si
);
2959 __SECONDARY_RELOAD_CASE (DI
, di
);
2960 __SECONDARY_RELOAD_CASE (TI
, ti
);
2961 __SECONDARY_RELOAD_CASE (SF
, sf
);
2962 __SECONDARY_RELOAD_CASE (DF
, df
);
2963 __SECONDARY_RELOAD_CASE (TF
, tf
);
2964 __SECONDARY_RELOAD_CASE (SD
, sd
);
2965 __SECONDARY_RELOAD_CASE (DD
, dd
);
2966 __SECONDARY_RELOAD_CASE (TD
, td
);
2971 #undef __SECONDARY_RELOAD_CASE
2975 /* We need a scratch register when loading a PLUS expression which
2976 is not a legitimate operand of the LOAD ADDRESS instruction. */
2977 if (in_p
&& s390_plus_operand (x
, mode
))
2978 sri
->icode
= (TARGET_64BIT
?
2979 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
2981 /* Performing a multiword move from or to memory we have to make sure the
2982 second chunk in memory is addressable without causing a displacement
2983 overflow. If that would be the case we calculate the address in
2984 a scratch register. */
2986 && GET_CODE (XEXP (x
, 0)) == PLUS
2987 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2988 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
2989 + GET_MODE_SIZE (mode
) - 1))
2991 /* For GENERAL_REGS a displacement overflow is no problem if occurring
2992 in a s_operand address since we may fallback to lm/stm. So we only
2993 have to care about overflows in the b+i+d case. */
2994 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
2995 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
2996 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
2997 /* For FP_REGS no lm/stm is available so this check is triggered
2998 for displacement overflows in b+i+d and b+d like addresses. */
2999 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3000 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3003 sri
->icode
= (TARGET_64BIT
?
3004 CODE_FOR_reloaddi_nonoffmem_in
:
3005 CODE_FOR_reloadsi_nonoffmem_in
);
3007 sri
->icode
= (TARGET_64BIT
?
3008 CODE_FOR_reloaddi_nonoffmem_out
:
3009 CODE_FOR_reloadsi_nonoffmem_out
);
3013 /* A scratch address register is needed when a symbolic constant is
3014 copied to r0 compiling with -fPIC. In other cases the target
3015 register might be used as temporary (see legitimize_pic_address). */
3016 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3017 sri
->icode
= (TARGET_64BIT
?
3018 CODE_FOR_reloaddi_PIC_addr
:
3019 CODE_FOR_reloadsi_PIC_addr
);
3021 /* Either scratch or no register needed. */
3025 /* Generate code to load SRC, which is PLUS that is not a
3026 legitimate operand for the LA instruction, into TARGET.
3027 SCRATCH may be used as scratch register. */
3030 s390_expand_plus_operand (rtx target
, rtx src
,
3034 struct s390_address ad
;
3036 /* src must be a PLUS; get its two operands. */
3037 gcc_assert (GET_CODE (src
) == PLUS
);
3038 gcc_assert (GET_MODE (src
) == Pmode
);
3040 /* Check if any of the two operands is already scheduled
3041 for replacement by reload. This can happen e.g. when
3042 float registers occur in an address. */
3043 sum1
= find_replacement (&XEXP (src
, 0));
3044 sum2
= find_replacement (&XEXP (src
, 1));
3045 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3047 /* If the address is already strictly valid, there's nothing to do. */
3048 if (!s390_decompose_address (src
, &ad
)
3049 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3050 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3052 /* Otherwise, one of the operands cannot be an address register;
3053 we reload its value into the scratch register. */
3054 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3056 emit_move_insn (scratch
, sum1
);
3059 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3061 emit_move_insn (scratch
, sum2
);
3065 /* According to the way these invalid addresses are generated
3066 in reload.c, it should never happen (at least on s390) that
3067 *neither* of the PLUS components, after find_replacements
3068 was applied, is an address register. */
3069 if (sum1
== scratch
&& sum2
== scratch
)
3075 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3078 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3079 is only ever performed on addresses, so we can mark the
3080 sum as legitimate for LA in any case. */
3081 s390_load_address (target
, src
);
3085 /* Return true if ADDR is a valid memory address.
3086 STRICT specifies whether strict register checking applies. */
3089 legitimate_address_p (enum machine_mode mode
, rtx addr
, int strict
)
3091 struct s390_address ad
;
3094 && larl_operand (addr
, VOIDmode
)
3095 && (mode
== VOIDmode
3096 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3099 if (!s390_decompose_address (addr
, &ad
))
3104 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3107 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3113 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3114 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3118 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3119 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3125 /* Return true if OP is a valid operand for the LA instruction.
3126 In 31-bit, we need to prove that the result is used as an
3127 address, as LA performs only a 31-bit addition. */
3130 legitimate_la_operand_p (rtx op
)
3132 struct s390_address addr
;
3133 if (!s390_decompose_address (op
, &addr
))
3136 return (TARGET_64BIT
|| addr
.pointer
);
3139 /* Return true if it is valid *and* preferable to use LA to
3140 compute the sum of OP1 and OP2. */
3143 preferred_la_operand_p (rtx op1
, rtx op2
)
3145 struct s390_address addr
;
3147 if (op2
!= const0_rtx
)
3148 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3150 if (!s390_decompose_address (op1
, &addr
))
3152 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3154 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3157 if (!TARGET_64BIT
&& !addr
.pointer
)
3163 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3164 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3170 /* Emit a forced load-address operation to load SRC into DST.
3171 This will use the LOAD ADDRESS instruction even in situations
3172 where legitimate_la_operand_p (SRC) returns false. */
3175 s390_load_address (rtx dst
, rtx src
)
3178 emit_move_insn (dst
, src
);
3180 emit_insn (gen_force_la_31 (dst
, src
));
3183 /* Return a legitimate reference for ORIG (an address) using the
3184 register REG. If REG is 0, a new pseudo is generated.
3186 There are two types of references that must be handled:
3188 1. Global data references must load the address from the GOT, via
3189 the PIC reg. An insn is emitted to do this load, and the reg is
3192 2. Static data references, constant pool addresses, and code labels
3193 compute the address as an offset from the GOT, whose base is in
3194 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3195 differentiate them from global data objects. The returned
3196 address is the PIC reg + an unspec constant.
3198 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
3199 reg also appears in the address. */
3202 legitimize_pic_address (rtx orig
, rtx reg
)
3208 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3210 if (GET_CODE (addr
) == LABEL_REF
3211 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3213 /* This is a local symbol. */
3214 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3216 /* Access local symbols PC-relative via LARL.
3217 This is the same as in the non-PIC case, so it is
3218 handled automatically ... */
3222 /* Access local symbols relative to the GOT. */
3224 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3226 if (reload_in_progress
|| reload_completed
)
3227 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3229 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3230 addr
= gen_rtx_CONST (Pmode
, addr
);
3231 addr
= force_const_mem (Pmode
, addr
);
3232 emit_move_insn (temp
, addr
);
3234 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3237 s390_load_address (reg
, new_rtx
);
3242 else if (GET_CODE (addr
) == SYMBOL_REF
)
3245 reg
= gen_reg_rtx (Pmode
);
3249 /* Assume GOT offset < 4k. This is handled the same way
3250 in both 31- and 64-bit code (@GOT). */
3252 if (reload_in_progress
|| reload_completed
)
3253 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3255 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3256 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3257 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3258 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3259 emit_move_insn (reg
, new_rtx
);
3262 else if (TARGET_CPU_ZARCH
)
3264 /* If the GOT offset might be >= 4k, we determine the position
3265 of the GOT entry via a PC-relative LARL (@GOTENT). */
3267 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3269 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3270 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3272 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3273 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3274 emit_move_insn (temp
, new_rtx
);
3276 new_rtx
= gen_const_mem (Pmode
, temp
);
3277 emit_move_insn (reg
, new_rtx
);
3282 /* If the GOT offset might be >= 4k, we have to load it
3283 from the literal pool (@GOT). */
3285 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3287 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3288 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3290 if (reload_in_progress
|| reload_completed
)
3291 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3293 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3294 addr
= gen_rtx_CONST (Pmode
, addr
);
3295 addr
= force_const_mem (Pmode
, addr
);
3296 emit_move_insn (temp
, addr
);
3298 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3299 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3300 emit_move_insn (reg
, new_rtx
);
3306 if (GET_CODE (addr
) == CONST
)
3308 addr
= XEXP (addr
, 0);
3309 if (GET_CODE (addr
) == UNSPEC
)
3311 gcc_assert (XVECLEN (addr
, 0) == 1);
3312 switch (XINT (addr
, 1))
3314 /* If someone moved a GOT-relative UNSPEC
3315 out of the literal pool, force them back in. */
3318 new_rtx
= force_const_mem (Pmode
, orig
);
3321 /* @GOT is OK as is if small. */
3324 new_rtx
= force_const_mem (Pmode
, orig
);
3327 /* @GOTENT is OK as is. */
3331 /* @PLT is OK as is on 64-bit, must be converted to
3332 GOT-relative @PLTOFF on 31-bit. */
3334 if (!TARGET_CPU_ZARCH
)
3336 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3338 if (reload_in_progress
|| reload_completed
)
3339 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3341 addr
= XVECEXP (addr
, 0, 0);
3342 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3344 addr
= gen_rtx_CONST (Pmode
, addr
);
3345 addr
= force_const_mem (Pmode
, addr
);
3346 emit_move_insn (temp
, addr
);
3348 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3351 s390_load_address (reg
, new_rtx
);
3357 /* Everything else cannot happen. */
3363 gcc_assert (GET_CODE (addr
) == PLUS
);
3365 if (GET_CODE (addr
) == PLUS
)
3367 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3369 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3370 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3372 /* Check first to see if this is a constant offset
3373 from a local symbol reference. */
3374 if ((GET_CODE (op0
) == LABEL_REF
3375 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3376 && GET_CODE (op1
) == CONST_INT
)
3378 if (TARGET_CPU_ZARCH
3379 && larl_operand (op0
, VOIDmode
)
3380 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3381 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3383 if (INTVAL (op1
) & 1)
3385 /* LARL can't handle odd offsets, so emit a
3386 pair of LARL and LA. */
3387 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3389 if (!DISP_IN_RANGE (INTVAL (op1
)))
3391 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3392 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3393 op0
= gen_rtx_CONST (Pmode
, op0
);
3397 emit_move_insn (temp
, op0
);
3398 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3402 s390_load_address (reg
, new_rtx
);
3408 /* If the offset is even, we can just use LARL.
3409 This will happen automatically. */
3414 /* Access local symbols relative to the GOT. */
3416 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3418 if (reload_in_progress
|| reload_completed
)
3419 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3421 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3423 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3424 addr
= gen_rtx_CONST (Pmode
, addr
);
3425 addr
= force_const_mem (Pmode
, addr
);
3426 emit_move_insn (temp
, addr
);
3428 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3431 s390_load_address (reg
, new_rtx
);
3437 /* Now, check whether it is a GOT relative symbol plus offset
3438 that was pulled out of the literal pool. Force it back in. */
3440 else if (GET_CODE (op0
) == UNSPEC
3441 && GET_CODE (op1
) == CONST_INT
3442 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3444 gcc_assert (XVECLEN (op0
, 0) == 1);
3446 new_rtx
= force_const_mem (Pmode
, orig
);
3449 /* Otherwise, compute the sum. */
3452 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3453 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3454 base
== reg
? NULL_RTX
: reg
);
3455 if (GET_CODE (new_rtx
) == CONST_INT
)
3456 new_rtx
= plus_constant (base
, INTVAL (new_rtx
));
3459 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3461 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3462 new_rtx
= XEXP (new_rtx
, 1);
3464 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3467 if (GET_CODE (new_rtx
) == CONST
)
3468 new_rtx
= XEXP (new_rtx
, 0);
3469 new_rtx
= force_operand (new_rtx
, 0);
3476 /* Load the thread pointer into a register. */
3479 s390_get_thread_pointer (void)
3481 rtx tp
= gen_reg_rtx (Pmode
);
3483 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3484 mark_reg_pointer (tp
, BITS_PER_WORD
);
3489 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3490 in s390_tls_symbol which always refers to __tls_get_offset.
3491 The returned offset is written to RESULT_REG and an USE rtx is
3492 generated for TLS_CALL. */
3494 static GTY(()) rtx s390_tls_symbol
;
3497 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3501 gcc_assert (flag_pic
);
3503 if (!s390_tls_symbol
)
3504 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3506 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3507 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3509 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3510 RTL_CONST_CALL_P (insn
) = 1;
3513 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3514 this (thread-local) address. REG may be used as temporary. */
3517 legitimize_tls_address (rtx addr
, rtx reg
)
3519 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3521 if (GET_CODE (addr
) == SYMBOL_REF
)
3522 switch (tls_symbolic_operand (addr
))
3524 case TLS_MODEL_GLOBAL_DYNAMIC
:
3526 r2
= gen_rtx_REG (Pmode
, 2);
3527 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3528 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3529 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3530 emit_move_insn (r2
, new_rtx
);
3531 s390_emit_tls_call_insn (r2
, tls_call
);
3532 insn
= get_insns ();
3535 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3536 temp
= gen_reg_rtx (Pmode
);
3537 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3539 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3542 s390_load_address (reg
, new_rtx
);
3547 case TLS_MODEL_LOCAL_DYNAMIC
:
3549 r2
= gen_rtx_REG (Pmode
, 2);
3550 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3551 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3552 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3553 emit_move_insn (r2
, new_rtx
);
3554 s390_emit_tls_call_insn (r2
, tls_call
);
3555 insn
= get_insns ();
3558 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3559 temp
= gen_reg_rtx (Pmode
);
3560 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3562 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3563 base
= gen_reg_rtx (Pmode
);
3564 s390_load_address (base
, new_rtx
);
3566 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3567 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3568 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3569 temp
= gen_reg_rtx (Pmode
);
3570 emit_move_insn (temp
, new_rtx
);
3572 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3575 s390_load_address (reg
, new_rtx
);
3580 case TLS_MODEL_INITIAL_EXEC
:
3583 /* Assume GOT offset < 4k. This is handled the same way
3584 in both 31- and 64-bit code. */
3586 if (reload_in_progress
|| reload_completed
)
3587 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3589 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3590 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3591 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3592 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3593 temp
= gen_reg_rtx (Pmode
);
3594 emit_move_insn (temp
, new_rtx
);
3596 else if (TARGET_CPU_ZARCH
)
3598 /* If the GOT offset might be >= 4k, we determine the position
3599 of the GOT entry via a PC-relative LARL. */
3601 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3602 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3603 temp
= gen_reg_rtx (Pmode
);
3604 emit_move_insn (temp
, new_rtx
);
3606 new_rtx
= gen_const_mem (Pmode
, temp
);
3607 temp
= gen_reg_rtx (Pmode
);
3608 emit_move_insn (temp
, new_rtx
);
3612 /* If the GOT offset might be >= 4k, we have to load it
3613 from the literal pool. */
3615 if (reload_in_progress
|| reload_completed
)
3616 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3618 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3619 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3620 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3621 temp
= gen_reg_rtx (Pmode
);
3622 emit_move_insn (temp
, new_rtx
);
3624 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3625 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3627 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3628 temp
= gen_reg_rtx (Pmode
);
3629 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3633 /* In position-dependent code, load the absolute address of
3634 the GOT entry from the literal pool. */
3636 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3637 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3638 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3639 temp
= gen_reg_rtx (Pmode
);
3640 emit_move_insn (temp
, new_rtx
);
3643 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3644 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3645 temp
= gen_reg_rtx (Pmode
);
3646 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3649 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3652 s390_load_address (reg
, new_rtx
);
3657 case TLS_MODEL_LOCAL_EXEC
:
3658 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3659 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3660 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3661 temp
= gen_reg_rtx (Pmode
);
3662 emit_move_insn (temp
, new_rtx
);
3664 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3667 s390_load_address (reg
, new_rtx
);
3676 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3678 switch (XINT (XEXP (addr
, 0), 1))
3680 case UNSPEC_INDNTPOFF
:
3681 gcc_assert (TARGET_CPU_ZARCH
);
3690 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3691 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3693 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3694 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3695 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3697 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3698 new_rtx
= plus_constant (new_rtx
, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3699 new_rtx
= force_operand (new_rtx
, 0);
3703 gcc_unreachable (); /* for now ... */
3708 /* Emit insns making the address in operands[1] valid for a standard
3709 move to operands[0]. operands[1] is replaced by an address which
3710 should be used instead of the former RTX to emit the move
3714 emit_symbolic_move (rtx
*operands
)
3716 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3718 if (GET_CODE (operands
[0]) == MEM
)
3719 operands
[1] = force_reg (Pmode
, operands
[1]);
3720 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3721 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3723 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3726 /* Try machine-dependent ways of modifying an illegitimate address X
3727 to be legitimate. If we find one, return the new, valid address.
3729 OLDX is the address as it was before break_out_memory_refs was called.
3730 In some cases it is useful to look at this to decide what needs to be done.
3732 MODE is the mode of the operand pointed to by X.
3734 When -fpic is used, special handling is needed for symbolic references.
3735 See comments by legitimize_pic_address for details. */
3738 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3739 enum machine_mode mode ATTRIBUTE_UNUSED
)
3741 rtx constant_term
= const0_rtx
;
3743 if (TLS_SYMBOLIC_CONST (x
))
3745 x
= legitimize_tls_address (x
, 0);
3747 if (legitimate_address_p (mode
, x
, FALSE
))
3750 else if (GET_CODE (x
) == PLUS
3751 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3752 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3758 if (SYMBOLIC_CONST (x
)
3759 || (GET_CODE (x
) == PLUS
3760 && (SYMBOLIC_CONST (XEXP (x
, 0))
3761 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3762 x
= legitimize_pic_address (x
, 0);
3764 if (legitimate_address_p (mode
, x
, FALSE
))
3768 x
= eliminate_constant_term (x
, &constant_term
);
3770 /* Optimize loading of large displacements by splitting them
3771 into the multiple of 4K and the rest; this allows the
3772 former to be CSE'd if possible.
3774 Don't do this if the displacement is added to a register
3775 pointing into the stack frame, as the offsets will
3776 change later anyway. */
3778 if (GET_CODE (constant_term
) == CONST_INT
3779 && !TARGET_LONG_DISPLACEMENT
3780 && !DISP_IN_RANGE (INTVAL (constant_term
))
3781 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3783 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3784 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3786 rtx temp
= gen_reg_rtx (Pmode
);
3787 rtx val
= force_operand (GEN_INT (upper
), temp
);
3789 emit_move_insn (temp
, val
);
3791 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3792 constant_term
= GEN_INT (lower
);
3795 if (GET_CODE (x
) == PLUS
)
3797 if (GET_CODE (XEXP (x
, 0)) == REG
)
3799 rtx temp
= gen_reg_rtx (Pmode
);
3800 rtx val
= force_operand (XEXP (x
, 1), temp
);
3802 emit_move_insn (temp
, val
);
3804 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3807 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3809 rtx temp
= gen_reg_rtx (Pmode
);
3810 rtx val
= force_operand (XEXP (x
, 0), temp
);
3812 emit_move_insn (temp
, val
);
3814 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
3818 if (constant_term
!= const0_rtx
)
3819 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
3824 /* Try a machine-dependent way of reloading an illegitimate address AD
3825 operand. If we find one, push the reload and and return the new address.
3827 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3828 and TYPE is the reload type of the current reload. */
3831 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3832 int opnum
, int type
)
3834 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
3837 if (GET_CODE (ad
) == PLUS
)
3839 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
3840 XEXP (ad
, 0), XEXP (ad
, 1));
3845 if (GET_CODE (ad
) == PLUS
3846 && GET_CODE (XEXP (ad
, 0)) == REG
3847 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
3848 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
3850 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
3851 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
3852 rtx cst
, tem
, new_rtx
;
3854 cst
= GEN_INT (upper
);
3855 if (!legitimate_reload_constant_p (cst
))
3856 cst
= force_const_mem (Pmode
, cst
);
3858 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
3859 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
3861 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
3862 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3863 opnum
, (enum reload_type
) type
);
3870 /* Emit code to move LEN bytes from DST to SRC. */
3873 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
3875 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
3877 if (INTVAL (len
) > 0)
3878 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
3881 else if (TARGET_MVCLE
)
3883 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
3888 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
3889 rtx loop_start_label
= gen_label_rtx ();
3890 rtx loop_end_label
= gen_label_rtx ();
3891 rtx end_label
= gen_label_rtx ();
3892 enum machine_mode mode
;
3894 mode
= GET_MODE (len
);
3895 if (mode
== VOIDmode
)
3898 dst_addr
= gen_reg_rtx (Pmode
);
3899 src_addr
= gen_reg_rtx (Pmode
);
3900 count
= gen_reg_rtx (mode
);
3901 blocks
= gen_reg_rtx (mode
);
3903 convert_move (count
, len
, 1);
3904 emit_cmp_and_jump_insns (count
, const0_rtx
,
3905 EQ
, NULL_RTX
, mode
, 1, end_label
);
3907 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
3908 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
3909 dst
= change_address (dst
, VOIDmode
, dst_addr
);
3910 src
= change_address (src
, VOIDmode
, src_addr
);
3912 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
3915 emit_move_insn (count
, temp
);
3917 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
3920 emit_move_insn (blocks
, temp
);
3922 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3923 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3925 emit_label (loop_start_label
);
3927 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
3928 s390_load_address (dst_addr
,
3929 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
3930 s390_load_address (src_addr
,
3931 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
3933 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
3936 emit_move_insn (blocks
, temp
);
3938 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3939 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3941 emit_jump (loop_start_label
);
3942 emit_label (loop_end_label
);
3944 emit_insn (gen_movmem_short (dst
, src
,
3945 convert_to_mode (Pmode
, count
, 1)));
3946 emit_label (end_label
);
3950 /* Emit code to set LEN bytes at DST to VAL.
3951 Make use of clrmem if VAL is zero. */
3954 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
3956 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
3959 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
3961 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
3963 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
3964 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
3967 /* Initialize memory by storing the first byte. */
3968 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
3970 if (INTVAL (len
) > 1)
3972 /* Initiate 1 byte overlap move.
3973 The first byte of DST is propagated through DSTP1.
3974 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3975 DST is set to size 1 so the rest of the memory location
3976 does not count as source operand. */
3977 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
3978 set_mem_size (dst
, const1_rtx
);
3980 emit_insn (gen_movmem_short (dstp1
, dst
,
3981 GEN_INT (INTVAL (len
) - 2)));
3986 else if (TARGET_MVCLE
)
3988 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
3989 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
3994 rtx dst_addr
, src_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
3995 rtx loop_start_label
= gen_label_rtx ();
3996 rtx loop_end_label
= gen_label_rtx ();
3997 rtx end_label
= gen_label_rtx ();
3998 enum machine_mode mode
;
4000 mode
= GET_MODE (len
);
4001 if (mode
== VOIDmode
)
4004 dst_addr
= gen_reg_rtx (Pmode
);
4005 src_addr
= gen_reg_rtx (Pmode
);
4006 count
= gen_reg_rtx (mode
);
4007 blocks
= gen_reg_rtx (mode
);
4009 convert_move (count
, len
, 1);
4010 emit_cmp_and_jump_insns (count
, const0_rtx
,
4011 EQ
, NULL_RTX
, mode
, 1, end_label
);
4013 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4014 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4016 if (val
== const0_rtx
)
4017 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4021 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4022 set_mem_size (dst
, const1_rtx
);
4024 /* Initialize memory by storing the first byte. */
4025 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4027 /* If count is 1 we are done. */
4028 emit_cmp_and_jump_insns (count
, const1_rtx
,
4029 EQ
, NULL_RTX
, mode
, 1, end_label
);
4031 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4035 emit_move_insn (count
, temp
);
4037 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4040 emit_move_insn (blocks
, temp
);
4042 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4043 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4045 emit_label (loop_start_label
);
4047 if (val
== const0_rtx
)
4048 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4050 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4051 s390_load_address (dst_addr
,
4052 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4054 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4057 emit_move_insn (blocks
, temp
);
4059 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4060 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4062 emit_jump (loop_start_label
);
4063 emit_label (loop_end_label
);
4065 if (val
== const0_rtx
)
4066 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4068 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4069 emit_label (end_label
);
4073 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4074 and return the result in TARGET. */
4077 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4079 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4082 /* As the result of CMPINT is inverted compared to what we need,
4083 we have to swap the operands. */
4084 tmp
= op0
; op0
= op1
; op1
= tmp
;
4086 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4088 if (INTVAL (len
) > 0)
4090 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4091 emit_insn (gen_cmpint (target
, ccreg
));
4094 emit_move_insn (target
, const0_rtx
);
4096 else if (TARGET_MVCLE
)
4098 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4099 emit_insn (gen_cmpint (target
, ccreg
));
4103 rtx addr0
, addr1
, count
, blocks
, temp
;
4104 rtx loop_start_label
= gen_label_rtx ();
4105 rtx loop_end_label
= gen_label_rtx ();
4106 rtx end_label
= gen_label_rtx ();
4107 enum machine_mode mode
;
4109 mode
= GET_MODE (len
);
4110 if (mode
== VOIDmode
)
4113 addr0
= gen_reg_rtx (Pmode
);
4114 addr1
= gen_reg_rtx (Pmode
);
4115 count
= gen_reg_rtx (mode
);
4116 blocks
= gen_reg_rtx (mode
);
4118 convert_move (count
, len
, 1);
4119 emit_cmp_and_jump_insns (count
, const0_rtx
,
4120 EQ
, NULL_RTX
, mode
, 1, end_label
);
4122 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4123 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4124 op0
= change_address (op0
, VOIDmode
, addr0
);
4125 op1
= change_address (op1
, VOIDmode
, addr1
);
4127 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4130 emit_move_insn (count
, temp
);
4132 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4135 emit_move_insn (blocks
, temp
);
4137 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4138 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4140 emit_label (loop_start_label
);
4142 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4143 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4144 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4145 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4146 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4147 emit_jump_insn (temp
);
4149 s390_load_address (addr0
,
4150 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4151 s390_load_address (addr1
,
4152 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4154 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4157 emit_move_insn (blocks
, temp
);
4159 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4160 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4162 emit_jump (loop_start_label
);
4163 emit_label (loop_end_label
);
4165 emit_insn (gen_cmpmem_short (op0
, op1
,
4166 convert_to_mode (Pmode
, count
, 1)));
4167 emit_label (end_label
);
4169 emit_insn (gen_cmpint (target
, ccreg
));
4174 /* Expand conditional increment or decrement using alc/slb instructions.
4175 Should generate code setting DST to either SRC or SRC + INCREMENT,
4176 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4177 Returns true if successful, false otherwise.
4179 That makes it possible to implement some if-constructs without jumps e.g.:
4180 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4181 unsigned int a, b, c;
4182 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4183 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4184 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4185 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4187 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4188 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4189 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4190 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4191 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4194 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4195 rtx dst
, rtx src
, rtx increment
)
4197 enum machine_mode cmp_mode
;
4198 enum machine_mode cc_mode
;
4204 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4205 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4207 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4208 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4213 /* Try ADD LOGICAL WITH CARRY. */
4214 if (increment
== const1_rtx
)
4216 /* Determine CC mode to use. */
4217 if (cmp_code
== EQ
|| cmp_code
== NE
)
4219 if (cmp_op1
!= const0_rtx
)
4221 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4222 NULL_RTX
, 0, OPTAB_WIDEN
);
4223 cmp_op1
= const0_rtx
;
4226 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4229 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4234 cmp_code
= swap_condition (cmp_code
);
4251 /* Emit comparison instruction pattern. */
4252 if (!register_operand (cmp_op0
, cmp_mode
))
4253 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4255 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4256 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4257 /* We use insn_invalid_p here to add clobbers if required. */
4258 ret
= insn_invalid_p (emit_insn (insn
));
4261 /* Emit ALC instruction pattern. */
4262 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4263 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4266 if (src
!= const0_rtx
)
4268 if (!register_operand (src
, GET_MODE (dst
)))
4269 src
= force_reg (GET_MODE (dst
), src
);
4271 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4272 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4275 p
= rtvec_alloc (2);
4277 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4279 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4280 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4285 /* Try SUBTRACT LOGICAL WITH BORROW. */
4286 if (increment
== constm1_rtx
)
4288 /* Determine CC mode to use. */
4289 if (cmp_code
== EQ
|| cmp_code
== NE
)
4291 if (cmp_op1
!= const0_rtx
)
4293 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4294 NULL_RTX
, 0, OPTAB_WIDEN
);
4295 cmp_op1
= const0_rtx
;
4298 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4301 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4306 cmp_code
= swap_condition (cmp_code
);
4323 /* Emit comparison instruction pattern. */
4324 if (!register_operand (cmp_op0
, cmp_mode
))
4325 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4327 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4328 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4329 /* We use insn_invalid_p here to add clobbers if required. */
4330 ret
= insn_invalid_p (emit_insn (insn
));
4333 /* Emit SLB instruction pattern. */
4334 if (!register_operand (src
, GET_MODE (dst
)))
4335 src
= force_reg (GET_MODE (dst
), src
);
4337 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4338 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4339 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4340 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4342 p
= rtvec_alloc (2);
4344 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4346 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4347 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4355 /* Expand code for the insv template. Return true if successful. */
4358 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4360 int bitsize
= INTVAL (op1
);
4361 int bitpos
= INTVAL (op2
);
4363 /* On z10 we can use the risbg instruction to implement insv. */
4365 && ((GET_MODE (dest
) == DImode
&& GET_MODE (src
) == DImode
)
4366 || (GET_MODE (dest
) == SImode
&& GET_MODE (src
) == SImode
)))
4371 op
= gen_rtx_SET (GET_MODE(src
),
4372 gen_rtx_ZERO_EXTRACT (GET_MODE (dest
), dest
, op1
, op2
),
4374 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4375 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4380 /* We need byte alignment. */
4381 if (bitsize
% BITS_PER_UNIT
)
4385 && memory_operand (dest
, VOIDmode
)
4386 && (register_operand (src
, word_mode
)
4387 || const_int_operand (src
, VOIDmode
)))
4389 /* Emit standard pattern if possible. */
4390 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4391 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4392 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4394 /* (set (ze (mem)) (const_int)). */
4395 else if (const_int_operand (src
, VOIDmode
))
4397 int size
= bitsize
/ BITS_PER_UNIT
;
4398 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4399 GET_MODE_SIZE (word_mode
) - size
);
4401 dest
= adjust_address (dest
, BLKmode
, 0);
4402 set_mem_size (dest
, GEN_INT (size
));
4403 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4406 /* (set (ze (mem)) (reg)). */
4407 else if (register_operand (src
, word_mode
))
4409 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4410 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4414 /* Emit st,stcmh sequence. */
4415 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4416 int size
= stcmh_width
/ BITS_PER_UNIT
;
4418 emit_move_insn (adjust_address (dest
, SImode
, size
),
4419 gen_lowpart (SImode
, src
));
4420 set_mem_size (dest
, GEN_INT (size
));
4421 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4422 (stcmh_width
), const0_rtx
),
4423 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4424 (GET_MODE_BITSIZE (SImode
))));
4433 /* (set (ze (reg)) (const_int)). */
4435 && register_operand (dest
, word_mode
)
4436 && (bitpos
% 16) == 0
4437 && (bitsize
% 16) == 0
4438 && const_int_operand (src
, VOIDmode
))
4440 HOST_WIDE_INT val
= INTVAL (src
);
4441 int regpos
= bitpos
+ bitsize
;
4443 while (regpos
> bitpos
)
4445 enum machine_mode putmode
;
4448 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4453 putsize
= GET_MODE_BITSIZE (putmode
);
4455 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4458 gen_int_mode (val
, putmode
));
4461 gcc_assert (regpos
== bitpos
);
4468 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4469 register that holds VAL of mode MODE shifted by COUNT bits. */
4472 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4474 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4475 NULL_RTX
, 1, OPTAB_DIRECT
);
4476 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4477 NULL_RTX
, 1, OPTAB_DIRECT
);
4480 /* Structure to hold the initial parameters for a compare_and_swap operation
4481 in HImode and QImode. */
4483 struct alignment_context
4485 rtx memsi
; /* SI aligned memory location. */
4486 rtx shift
; /* Bit offset with regard to lsb. */
4487 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4488 rtx modemaski
; /* ~modemask */
4489 bool aligned
; /* True if memory is aligned, false else. */
4492 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4493 structure AC for transparent simplifying, if the memory alignment is known
4494 to be at least 32bit. MEM is the memory location for the actual operation
4495 and MODE its mode. */
4498 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4499 enum machine_mode mode
)
4501 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4502 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4505 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4508 /* Alignment is unknown. */
4509 rtx byteoffset
, addr
, align
;
4511 /* Force the address into a register. */
4512 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4514 /* Align it to SImode. */
4515 align
= expand_simple_binop (Pmode
, AND
, addr
,
4516 GEN_INT (-GET_MODE_SIZE (SImode
)),
4517 NULL_RTX
, 1, OPTAB_DIRECT
);
4519 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4520 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4521 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4522 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4524 /* Calculate shiftcount. */
4525 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4526 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4527 NULL_RTX
, 1, OPTAB_DIRECT
);
4528 /* As we already have some offset, evaluate the remaining distance. */
4529 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4530 NULL_RTX
, 1, OPTAB_DIRECT
);
4533 /* Shift is the byte count, but we need the bitcount. */
4534 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4535 NULL_RTX
, 1, OPTAB_DIRECT
);
4536 /* Calculate masks. */
4537 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4538 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4539 NULL_RTX
, 1, OPTAB_DIRECT
);
4540 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4543 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4544 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4545 to set if CMP == MEM.
4546 CMP is never in memory for compare_and_swap_cc because
4547 expand_bool_compare_and_swap puts it into a register for later compare. */
4550 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
4552 struct alignment_context ac
;
4553 rtx cmpv
, newv
, val
, resv
, cc
;
4554 rtx res
= gen_reg_rtx (SImode
);
4555 rtx csloop
= gen_label_rtx ();
4556 rtx csend
= gen_label_rtx ();
4558 gcc_assert (register_operand (target
, VOIDmode
));
4559 gcc_assert (MEM_P (mem
));
4561 init_alignment_context (&ac
, mem
, mode
);
4563 /* Shift the values to the correct bit positions. */
4564 if (!(ac
.aligned
&& MEM_P (cmp
)))
4565 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4566 if (!(ac
.aligned
&& MEM_P (new_rtx
)))
4567 new_rtx
= s390_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
4569 /* Load full word. Subsequent loads are performed by CS. */
4570 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4571 NULL_RTX
, 1, OPTAB_DIRECT
);
4573 /* Start CS loop. */
4574 emit_label (csloop
);
4575 /* val = "<mem>00..0<mem>"
4576 * cmp = "00..0<cmp>00..0"
4577 * new = "00..0<new>00..0"
4580 /* Patch cmp and new with val at correct position. */
4581 if (ac
.aligned
&& MEM_P (cmp
))
4583 cmpv
= force_reg (SImode
, val
);
4584 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0, SImode
, cmp
);
4587 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4588 NULL_RTX
, 1, OPTAB_DIRECT
));
4589 if (ac
.aligned
&& MEM_P (new_rtx
))
4591 newv
= force_reg (SImode
, val
);
4592 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0, SImode
, new_rtx
);
4595 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4596 NULL_RTX
, 1, OPTAB_DIRECT
));
4598 /* Jump to end if we're done (likely?). */
4599 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4602 /* Check for changes outside mode. */
4603 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4604 NULL_RTX
, 1, OPTAB_DIRECT
);
4605 cc
= s390_emit_compare (NE
, resv
, val
);
4606 emit_move_insn (val
, resv
);
4607 /* Loop internal if so. */
4608 s390_emit_jump (csloop
, cc
);
4612 /* Return the correct part of the bitfield. */
4613 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4614 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4617 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4618 and VAL the value to play with. If AFTER is true then store the value
4619 MEM holds after the operation, if AFTER is false then store the value MEM
4620 holds before the operation. If TARGET is zero then discard that value, else
4621 store it to TARGET. */
4624 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4625 rtx target
, rtx mem
, rtx val
, bool after
)
4627 struct alignment_context ac
;
4629 rtx new_rtx
= gen_reg_rtx (SImode
);
4630 rtx orig
= gen_reg_rtx (SImode
);
4631 rtx csloop
= gen_label_rtx ();
4633 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4634 gcc_assert (MEM_P (mem
));
4636 init_alignment_context (&ac
, mem
, mode
);
4638 /* Shift val to the correct bit positions.
4639 Preserve "icm", but prevent "ex icm". */
4640 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4641 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4643 /* Further preparation insns. */
4644 if (code
== PLUS
|| code
== MINUS
)
4645 emit_move_insn (orig
, val
);
4646 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4647 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4648 NULL_RTX
, 1, OPTAB_DIRECT
);
4650 /* Load full word. Subsequent loads are performed by CS. */
4651 cmp
= force_reg (SImode
, ac
.memsi
);
4653 /* Start CS loop. */
4654 emit_label (csloop
);
4655 emit_move_insn (new_rtx
, cmp
);
4657 /* Patch new with val at correct position. */
4662 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
4663 NULL_RTX
, 1, OPTAB_DIRECT
);
4664 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4665 NULL_RTX
, 1, OPTAB_DIRECT
);
4668 if (ac
.aligned
&& MEM_P (val
))
4669 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0, SImode
, val
);
4672 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
4673 NULL_RTX
, 1, OPTAB_DIRECT
);
4674 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4675 NULL_RTX
, 1, OPTAB_DIRECT
);
4681 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
4682 NULL_RTX
, 1, OPTAB_DIRECT
);
4684 case MULT
: /* NAND */
4685 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
4686 NULL_RTX
, 1, OPTAB_DIRECT
);
4687 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
4688 NULL_RTX
, 1, OPTAB_DIRECT
);
4694 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4695 ac
.memsi
, cmp
, new_rtx
));
4697 /* Return the correct part of the bitfield. */
4699 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4700 after
? new_rtx
: cmp
, ac
.shift
,
4701 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4704 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4705 We need to emit DTP-relative relocations. */
4707 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4710 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4715 fputs ("\t.long\t", file
);
4718 fputs ("\t.quad\t", file
);
4723 output_addr_const (file
, x
);
4724 fputs ("@DTPOFF", file
);
4727 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4728 /* Implement TARGET_MANGLE_TYPE. */
4731 s390_mangle_type (const_tree type
)
4733 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4734 && TARGET_LONG_DOUBLE_128
)
4737 /* For all other types, use normal C++ mangling. */
4742 /* In the name of slightly smaller debug output, and to cater to
4743 general assembler lossage, recognize various UNSPEC sequences
4744 and turn them back into a direct symbol reference. */
4747 s390_delegitimize_address (rtx orig_x
)
4751 if (GET_CODE (x
) != MEM
)
4755 if (GET_CODE (x
) == PLUS
4756 && GET_CODE (XEXP (x
, 1)) == CONST
4757 && GET_CODE (XEXP (x
, 0)) == REG
4758 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
4760 y
= XEXP (XEXP (x
, 1), 0);
4761 if (GET_CODE (y
) == UNSPEC
4762 && XINT (y
, 1) == UNSPEC_GOT
)
4763 return XVECEXP (y
, 0, 0);
4767 if (GET_CODE (x
) == CONST
)
4770 if (GET_CODE (y
) == UNSPEC
4771 && XINT (y
, 1) == UNSPEC_GOTENT
)
4772 return XVECEXP (y
, 0, 0);
4779 /* Output operand OP to stdio stream FILE.
4780 OP is an address (register + offset) which is not used to address data;
4781 instead the rightmost bits are interpreted as the value. */
4784 print_shift_count_operand (FILE *file
, rtx op
)
4786 HOST_WIDE_INT offset
;
4789 /* Extract base register and offset. */
4790 if (!s390_decompose_shift_count (op
, &base
, &offset
))
4796 gcc_assert (GET_CODE (base
) == REG
);
4797 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
4798 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
4801 /* Offsets are constricted to twelve bits. */
4802 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
4804 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
4807 /* See 'get_some_local_dynamic_name'. */
4810 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4814 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4816 x
= get_pool_constant (x
);
4817 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
4820 if (GET_CODE (x
) == SYMBOL_REF
4821 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4823 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4830 /* Locate some local-dynamic symbol still in use by this function
4831 so that we can print its name in local-dynamic base patterns. */
4834 get_some_local_dynamic_name (void)
4838 if (cfun
->machine
->some_ld_name
)
4839 return cfun
->machine
->some_ld_name
;
4841 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4843 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4844 return cfun
->machine
->some_ld_name
;
4849 /* Output machine-dependent UNSPECs occurring in address constant X
4850 in assembler syntax to stdio stream FILE. Returns true if the
4851 constant X could be recognized, false otherwise. */
4854 s390_output_addr_const_extra (FILE *file
, rtx x
)
4856 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
4857 switch (XINT (x
, 1))
4860 output_addr_const (file
, XVECEXP (x
, 0, 0));
4861 fprintf (file
, "@GOTENT");
4864 output_addr_const (file
, XVECEXP (x
, 0, 0));
4865 fprintf (file
, "@GOT");
4868 output_addr_const (file
, XVECEXP (x
, 0, 0));
4869 fprintf (file
, "@GOTOFF");
4872 output_addr_const (file
, XVECEXP (x
, 0, 0));
4873 fprintf (file
, "@PLT");
4876 output_addr_const (file
, XVECEXP (x
, 0, 0));
4877 fprintf (file
, "@PLTOFF");
4880 output_addr_const (file
, XVECEXP (x
, 0, 0));
4881 fprintf (file
, "@TLSGD");
4884 assemble_name (file
, get_some_local_dynamic_name ());
4885 fprintf (file
, "@TLSLDM");
4888 output_addr_const (file
, XVECEXP (x
, 0, 0));
4889 fprintf (file
, "@DTPOFF");
4892 output_addr_const (file
, XVECEXP (x
, 0, 0));
4893 fprintf (file
, "@NTPOFF");
4895 case UNSPEC_GOTNTPOFF
:
4896 output_addr_const (file
, XVECEXP (x
, 0, 0));
4897 fprintf (file
, "@GOTNTPOFF");
4899 case UNSPEC_INDNTPOFF
:
4900 output_addr_const (file
, XVECEXP (x
, 0, 0));
4901 fprintf (file
, "@INDNTPOFF");
4905 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
4906 switch (XINT (x
, 1))
4908 case UNSPEC_POOL_OFFSET
:
4909 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
4910 output_addr_const (file
, x
);
4916 /* Output address operand ADDR in assembler syntax to
4917 stdio stream FILE. */
4920 print_operand_address (FILE *file
, rtx addr
)
4922 struct s390_address ad
;
4924 if (s390_symref_operand_p (addr
, NULL
, NULL
))
4926 gcc_assert (TARGET_Z10
);
4927 output_addr_const (file
, addr
);
4931 if (!s390_decompose_address (addr
, &ad
)
4932 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4933 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
4934 output_operand_lossage ("cannot decompose address");
4937 output_addr_const (file
, ad
.disp
);
4939 fprintf (file
, "0");
4941 if (ad
.base
&& ad
.indx
)
4942 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
4943 reg_names
[REGNO (ad
.base
)]);
4945 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
4948 /* Output operand X in assembler syntax to stdio stream FILE.
4949 CODE specified the format flag. The following format flags
4952 'C': print opcode suffix for branch condition.
4953 'D': print opcode suffix for inverse branch condition.
4954 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4955 'G': print the size of the operand in bytes.
4956 'O': print only the displacement of a memory reference.
4957 'R': print only the base register of a memory reference.
4958 'S': print S-type memory reference (base+displacement).
4959 'N': print the second word of a DImode operand.
4960 'M': print the second word of a TImode operand.
4961 'Y': print shift count operand.
4963 'b': print integer X as if it's an unsigned byte.
4964 'c': print integer X as if it's an signed byte.
4965 'x': print integer X as if it's an unsigned halfword.
4966 'h': print integer X as if it's a signed halfword.
4967 'i': print the first nonzero HImode part of X.
4968 'j': print the first HImode part unequal to -1 of X.
4969 'k': print the first nonzero SImode part of X.
4970 'm': print the first SImode part unequal to -1 of X.
4971 'o': print integer X as if it's an unsigned 32bit word. */
4974 print_operand (FILE *file
, rtx x
, int code
)
4979 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
4983 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
4987 if (GET_CODE (x
) == SYMBOL_REF
)
4989 fprintf (file
, "%s", ":tls_load:");
4990 output_addr_const (file
, x
);
4992 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
4994 fprintf (file
, "%s", ":tls_gdcall:");
4995 output_addr_const (file
, XVECEXP (x
, 0, 0));
4997 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
4999 fprintf (file
, "%s", ":tls_ldcall:");
5000 assemble_name (file
, get_some_local_dynamic_name ());
5007 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5012 struct s390_address ad
;
5015 gcc_assert (GET_CODE (x
) == MEM
);
5016 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5018 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5019 gcc_assert (!ad
.indx
);
5022 output_addr_const (file
, ad
.disp
);
5024 fprintf (file
, "0");
5030 struct s390_address ad
;
5033 gcc_assert (GET_CODE (x
) == MEM
);
5034 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5036 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5037 gcc_assert (!ad
.indx
);
5040 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5042 fprintf (file
, "0");
5048 struct s390_address ad
;
5051 gcc_assert (GET_CODE (x
) == MEM
);
5052 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5054 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5055 gcc_assert (!ad
.indx
);
5058 output_addr_const (file
, ad
.disp
);
5060 fprintf (file
, "0");
5063 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5068 if (GET_CODE (x
) == REG
)
5069 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5070 else if (GET_CODE (x
) == MEM
)
5071 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
5077 if (GET_CODE (x
) == REG
)
5078 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5079 else if (GET_CODE (x
) == MEM
)
5080 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
5086 print_shift_count_operand (file
, x
);
5090 switch (GET_CODE (x
))
5093 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5097 output_address (XEXP (x
, 0));
5104 output_addr_const (file
, x
);
5109 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5110 else if (code
== 'c')
5111 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5112 else if (code
== 'x')
5113 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5114 else if (code
== 'h')
5115 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5116 else if (code
== 'i')
5117 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5118 s390_extract_part (x
, HImode
, 0));
5119 else if (code
== 'j')
5120 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5121 s390_extract_part (x
, HImode
, -1));
5122 else if (code
== 'k')
5123 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5124 s390_extract_part (x
, SImode
, 0));
5125 else if (code
== 'm')
5126 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5127 s390_extract_part (x
, SImode
, -1));
5128 else if (code
== 'o')
5129 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5131 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5135 gcc_assert (GET_MODE (x
) == VOIDmode
);
5137 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5138 else if (code
== 'x')
5139 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5140 else if (code
== 'h')
5141 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5147 fatal_insn ("UNKNOWN in print_operand !?", x
);
5152 /* Target hook for assembling integer objects. We need to define it
5153 here to work a round a bug in some versions of GAS, which couldn't
5154 handle values smaller than INT_MIN when printed in decimal. */
5157 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5159 if (size
== 8 && aligned_p
5160 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5162 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5166 return default_assemble_integer (x
, size
, aligned_p
);
5169 /* Returns true if register REGNO is used for forming
5170 a memory address in expression X. */
5173 reg_used_in_mem_p (int regno
, rtx x
)
5175 enum rtx_code code
= GET_CODE (x
);
5181 if (refers_to_regno_p (regno
, regno
+1,
5185 else if (code
== SET
5186 && GET_CODE (SET_DEST (x
)) == PC
)
5188 if (refers_to_regno_p (regno
, regno
+1,
5193 fmt
= GET_RTX_FORMAT (code
);
5194 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5197 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5200 else if (fmt
[i
] == 'E')
5201 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5202 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5208 /* Returns true if expression DEP_RTX sets an address register
5209 used by instruction INSN to address memory. */
5212 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5216 if (GET_CODE (dep_rtx
) == INSN
)
5217 dep_rtx
= PATTERN (dep_rtx
);
5219 if (GET_CODE (dep_rtx
) == SET
)
5221 target
= SET_DEST (dep_rtx
);
5222 if (GET_CODE (target
) == STRICT_LOW_PART
)
5223 target
= XEXP (target
, 0);
5224 while (GET_CODE (target
) == SUBREG
)
5225 target
= SUBREG_REG (target
);
5227 if (GET_CODE (target
) == REG
)
5229 int regno
= REGNO (target
);
5231 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5233 pat
= PATTERN (insn
);
5234 if (GET_CODE (pat
) == PARALLEL
)
5236 gcc_assert (XVECLEN (pat
, 0) == 2);
5237 pat
= XVECEXP (pat
, 0, 0);
5239 gcc_assert (GET_CODE (pat
) == SET
);
5240 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5242 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5243 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5249 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5252 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5254 rtx dep_rtx
= PATTERN (dep_insn
);
5257 if (GET_CODE (dep_rtx
) == SET
5258 && addr_generation_dependency_p (dep_rtx
, insn
))
5260 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5262 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5264 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5272 /* A C statement (sans semicolon) to update the integer scheduling priority
5273 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5274 reduce the priority to execute INSN later. Do not define this macro if
5275 you do not need to adjust the scheduling priorities of insns.
5277 A STD instruction should be scheduled earlier,
5278 in order to use the bypass. */
5281 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5283 if (! INSN_P (insn
))
5286 if (s390_tune
!= PROCESSOR_2084_Z990
5287 && s390_tune
!= PROCESSOR_2094_Z9_109
)
5290 switch (s390_safe_attr_type (insn
))
5294 priority
= priority
<< 3;
5298 priority
= priority
<< 1;
5306 /* The number of instructions that can be issued per cycle. */
5309 s390_issue_rate (void)
5313 case PROCESSOR_2084_Z990
:
5314 case PROCESSOR_2094_Z9_109
:
5316 case PROCESSOR_2097_Z10
:
5324 s390_first_cycle_multipass_dfa_lookahead (void)
5330 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5331 Fix up MEMs as required. */
5334 annotate_constant_pool_refs (rtx
*x
)
5339 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5340 || !CONSTANT_POOL_ADDRESS_P (*x
));
5342 /* Literal pool references can only occur inside a MEM ... */
5343 if (GET_CODE (*x
) == MEM
)
5345 rtx memref
= XEXP (*x
, 0);
5347 if (GET_CODE (memref
) == SYMBOL_REF
5348 && CONSTANT_POOL_ADDRESS_P (memref
))
5350 rtx base
= cfun
->machine
->base_reg
;
5351 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5354 *x
= replace_equiv_address (*x
, addr
);
5358 if (GET_CODE (memref
) == CONST
5359 && GET_CODE (XEXP (memref
, 0)) == PLUS
5360 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5361 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5362 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5364 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5365 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5366 rtx base
= cfun
->machine
->base_reg
;
5367 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5370 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
5375 /* ... or a load-address type pattern. */
5376 if (GET_CODE (*x
) == SET
)
5378 rtx addrref
= SET_SRC (*x
);
5380 if (GET_CODE (addrref
) == SYMBOL_REF
5381 && CONSTANT_POOL_ADDRESS_P (addrref
))
5383 rtx base
= cfun
->machine
->base_reg
;
5384 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5387 SET_SRC (*x
) = addr
;
5391 if (GET_CODE (addrref
) == CONST
5392 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5393 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5394 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5395 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5397 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5398 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5399 rtx base
= cfun
->machine
->base_reg
;
5400 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5403 SET_SRC (*x
) = plus_constant (addr
, off
);
5408 /* Annotate LTREL_BASE as well. */
5409 if (GET_CODE (*x
) == UNSPEC
5410 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5412 rtx base
= cfun
->machine
->base_reg
;
5413 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5418 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5419 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5423 annotate_constant_pool_refs (&XEXP (*x
, i
));
5425 else if (fmt
[i
] == 'E')
5427 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5428 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5433 /* Split all branches that exceed the maximum distance.
5434 Returns true if this created a new literal pool entry. */
5437 s390_split_branches (void)
5439 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5440 int new_literal
= 0, ret
;
5441 rtx insn
, pat
, tmp
, target
;
5444 /* We need correct insn addresses. */
5446 shorten_branches (get_insns ());
5448 /* Find all branches that exceed 64KB, and split them. */
5450 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5452 if (GET_CODE (insn
) != JUMP_INSN
)
5455 pat
= PATTERN (insn
);
5456 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5457 pat
= XVECEXP (pat
, 0, 0);
5458 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5461 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5463 label
= &SET_SRC (pat
);
5465 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5467 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5468 label
= &XEXP (SET_SRC (pat
), 1);
5469 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5470 label
= &XEXP (SET_SRC (pat
), 2);
5477 if (get_attr_length (insn
) <= 4)
5480 /* We are going to use the return register as scratch register,
5481 make sure it will be saved/restored by the prologue/epilogue. */
5482 cfun_frame_layout
.save_return_addr_p
= 1;
5487 tmp
= force_const_mem (Pmode
, *label
);
5488 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5489 INSN_ADDRESSES_NEW (tmp
, -1);
5490 annotate_constant_pool_refs (&PATTERN (tmp
));
5497 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5498 UNSPEC_LTREL_OFFSET
);
5499 target
= gen_rtx_CONST (Pmode
, target
);
5500 target
= force_const_mem (Pmode
, target
);
5501 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5502 INSN_ADDRESSES_NEW (tmp
, -1);
5503 annotate_constant_pool_refs (&PATTERN (tmp
));
5505 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5506 cfun
->machine
->base_reg
),
5508 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5511 ret
= validate_change (insn
, label
, target
, 0);
5519 /* Find an annotated literal pool symbol referenced in RTX X,
5520 and store it at REF. Will abort if X contains references to
5521 more than one such pool symbol; multiple references to the same
5522 symbol are allowed, however.
5524 The rtx pointed to by REF must be initialized to NULL_RTX
5525 by the caller before calling this routine. */
5528 find_constant_pool_ref (rtx x
, rtx
*ref
)
5533 /* Ignore LTREL_BASE references. */
5534 if (GET_CODE (x
) == UNSPEC
5535 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5537 /* Likewise POOL_ENTRY insns. */
5538 if (GET_CODE (x
) == UNSPEC_VOLATILE
5539 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5542 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5543 || !CONSTANT_POOL_ADDRESS_P (x
));
5545 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5547 rtx sym
= XVECEXP (x
, 0, 0);
5548 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5549 && CONSTANT_POOL_ADDRESS_P (sym
));
5551 if (*ref
== NULL_RTX
)
5554 gcc_assert (*ref
== sym
);
5559 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5560 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5564 find_constant_pool_ref (XEXP (x
, i
), ref
);
5566 else if (fmt
[i
] == 'E')
5568 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5569 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5574 /* Replace every reference to the annotated literal pool
5575 symbol REF in X by its base plus OFFSET. */
5578 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5583 gcc_assert (*x
!= ref
);
5585 if (GET_CODE (*x
) == UNSPEC
5586 && XINT (*x
, 1) == UNSPEC_LTREF
5587 && XVECEXP (*x
, 0, 0) == ref
)
5589 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5593 if (GET_CODE (*x
) == PLUS
5594 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5595 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5596 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5597 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5599 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5600 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5604 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5605 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5609 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5611 else if (fmt
[i
] == 'E')
5613 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5614 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5619 /* Check whether X contains an UNSPEC_LTREL_BASE.
5620 Return its constant pool symbol if found, NULL_RTX otherwise. */
5623 find_ltrel_base (rtx x
)
5628 if (GET_CODE (x
) == UNSPEC
5629 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5630 return XVECEXP (x
, 0, 0);
5632 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5633 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5637 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5641 else if (fmt
[i
] == 'E')
5643 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5645 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
5655 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5658 replace_ltrel_base (rtx
*x
)
5663 if (GET_CODE (*x
) == UNSPEC
5664 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5666 *x
= XVECEXP (*x
, 0, 1);
5670 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5671 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5675 replace_ltrel_base (&XEXP (*x
, i
));
5677 else if (fmt
[i
] == 'E')
5679 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5680 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
5686 /* We keep a list of constants which we have to add to internal
5687 constant tables in the middle of large functions. */
5689 #define NR_C_MODES 11
5690 enum machine_mode constant_modes
[NR_C_MODES
] =
5692 TFmode
, TImode
, TDmode
,
5693 DFmode
, DImode
, DDmode
,
5694 SFmode
, SImode
, SDmode
,
5701 struct constant
*next
;
5706 struct constant_pool
5708 struct constant_pool
*next
;
5712 rtx emit_pool_after
;
5714 struct constant
*constants
[NR_C_MODES
];
5715 struct constant
*execute
;
5720 /* Allocate new constant_pool structure. */
5722 static struct constant_pool
*
5723 s390_alloc_pool (void)
5725 struct constant_pool
*pool
;
5728 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
5730 for (i
= 0; i
< NR_C_MODES
; i
++)
5731 pool
->constants
[i
] = NULL
;
5733 pool
->execute
= NULL
;
5734 pool
->label
= gen_label_rtx ();
5735 pool
->first_insn
= NULL_RTX
;
5736 pool
->pool_insn
= NULL_RTX
;
5737 pool
->insns
= BITMAP_ALLOC (NULL
);
5739 pool
->emit_pool_after
= NULL_RTX
;
5744 /* Create new constant pool covering instructions starting at INSN
5745 and chain it to the end of POOL_LIST. */
5747 static struct constant_pool
*
5748 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
5750 struct constant_pool
*pool
, **prev
;
5752 pool
= s390_alloc_pool ();
5753 pool
->first_insn
= insn
;
5755 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
5762 /* End range of instructions covered by POOL at INSN and emit
5763 placeholder insn representing the pool. */
5766 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
5768 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
5771 insn
= get_last_insn ();
5773 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
5774 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5777 /* Add INSN to the list of insns covered by POOL. */
5780 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
5782 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
5785 /* Return pool out of POOL_LIST that covers INSN. */
5787 static struct constant_pool
*
5788 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
5790 struct constant_pool
*pool
;
5792 for (pool
= pool_list
; pool
; pool
= pool
->next
)
5793 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
5799 /* Add constant VAL of mode MODE to the constant pool POOL. */
5802 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
5807 for (i
= 0; i
< NR_C_MODES
; i
++)
5808 if (constant_modes
[i
] == mode
)
5810 gcc_assert (i
!= NR_C_MODES
);
5812 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
5813 if (rtx_equal_p (val
, c
->value
))
5818 c
= (struct constant
*) xmalloc (sizeof *c
);
5820 c
->label
= gen_label_rtx ();
5821 c
->next
= pool
->constants
[i
];
5822 pool
->constants
[i
] = c
;
5823 pool
->size
+= GET_MODE_SIZE (mode
);
5827 /* Return an rtx that represents the offset of X from the start of
5831 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
5835 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
5836 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
5837 UNSPEC_POOL_OFFSET
);
5838 return gen_rtx_CONST (GET_MODE (x
), x
);
5841 /* Find constant VAL of mode MODE in the constant pool POOL.
5842 Return an RTX describing the distance from the start of
5843 the pool to the location of the new constant. */
5846 s390_find_constant (struct constant_pool
*pool
, rtx val
,
5847 enum machine_mode mode
)
5852 for (i
= 0; i
< NR_C_MODES
; i
++)
5853 if (constant_modes
[i
] == mode
)
5855 gcc_assert (i
!= NR_C_MODES
);
5857 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
5858 if (rtx_equal_p (val
, c
->value
))
5863 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
5866 /* Check whether INSN is an execute. Return the label_ref to its
5867 execute target template if so, NULL_RTX otherwise. */
5870 s390_execute_label (rtx insn
)
5872 if (GET_CODE (insn
) == INSN
5873 && GET_CODE (PATTERN (insn
)) == PARALLEL
5874 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
5875 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
5876 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
5881 /* Add execute target for INSN to the constant pool POOL. */
5884 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
5888 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
5889 if (INSN_UID (insn
) == INSN_UID (c
->value
))
5894 c
= (struct constant
*) xmalloc (sizeof *c
);
5896 c
->label
= gen_label_rtx ();
5897 c
->next
= pool
->execute
;
5903 /* Find execute target for INSN in the constant pool POOL.
5904 Return an RTX describing the distance from the start of
5905 the pool to the location of the execute target. */
5908 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
5912 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
5913 if (INSN_UID (insn
) == INSN_UID (c
->value
))
5918 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
5921 /* For an execute INSN, extract the execute target template. */
5924 s390_execute_target (rtx insn
)
5926 rtx pattern
= PATTERN (insn
);
5927 gcc_assert (s390_execute_label (insn
));
5929 if (XVECLEN (pattern
, 0) == 2)
5931 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
5935 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
5938 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
5939 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
5941 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
5947 /* Indicate that INSN cannot be duplicated. This is the case for
5948 execute insns that carry a unique label. */
5951 s390_cannot_copy_insn_p (rtx insn
)
5953 rtx label
= s390_execute_label (insn
);
5954 return label
&& label
!= const0_rtx
;
5957 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5958 do not emit the pool base label. */
5961 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
5964 rtx insn
= pool
->pool_insn
;
5967 /* Switch to rodata section. */
5968 if (TARGET_CPU_ZARCH
)
5970 insn
= emit_insn_after (gen_pool_section_start (), insn
);
5971 INSN_ADDRESSES_NEW (insn
, -1);
5974 /* Ensure minimum pool alignment. */
5975 if (TARGET_CPU_ZARCH
)
5976 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
5978 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
5979 INSN_ADDRESSES_NEW (insn
, -1);
5981 /* Emit pool base label. */
5984 insn
= emit_label_after (pool
->label
, insn
);
5985 INSN_ADDRESSES_NEW (insn
, -1);
5988 /* Dump constants in descending alignment requirement order,
5989 ensuring proper alignment for every constant. */
5990 for (i
= 0; i
< NR_C_MODES
; i
++)
5991 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
5993 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5994 rtx value
= copy_rtx (c
->value
);
5995 if (GET_CODE (value
) == CONST
5996 && GET_CODE (XEXP (value
, 0)) == UNSPEC
5997 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
5998 && XVECLEN (XEXP (value
, 0), 0) == 1)
5999 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6001 insn
= emit_label_after (c
->label
, insn
);
6002 INSN_ADDRESSES_NEW (insn
, -1);
6004 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6005 gen_rtvec (1, value
),
6006 UNSPECV_POOL_ENTRY
);
6007 insn
= emit_insn_after (value
, insn
);
6008 INSN_ADDRESSES_NEW (insn
, -1);
6011 /* Ensure minimum alignment for instructions. */
6012 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6013 INSN_ADDRESSES_NEW (insn
, -1);
6015 /* Output in-pool execute template insns. */
6016 for (c
= pool
->execute
; c
; c
= c
->next
)
6018 insn
= emit_label_after (c
->label
, insn
);
6019 INSN_ADDRESSES_NEW (insn
, -1);
6021 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6022 INSN_ADDRESSES_NEW (insn
, -1);
6025 /* Switch back to previous section. */
6026 if (TARGET_CPU_ZARCH
)
6028 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6029 INSN_ADDRESSES_NEW (insn
, -1);
6032 insn
= emit_barrier_after (insn
);
6033 INSN_ADDRESSES_NEW (insn
, -1);
6035 /* Remove placeholder insn. */
6036 remove_insn (pool
->pool_insn
);
6039 /* Free all memory used by POOL. */
6042 s390_free_pool (struct constant_pool
*pool
)
6044 struct constant
*c
, *next
;
6047 for (i
= 0; i
< NR_C_MODES
; i
++)
6048 for (c
= pool
->constants
[i
]; c
; c
= next
)
6054 for (c
= pool
->execute
; c
; c
= next
)
6060 BITMAP_FREE (pool
->insns
);
6065 /* Collect main literal pool. Return NULL on overflow. */
6067 static struct constant_pool
*
6068 s390_mainpool_start (void)
6070 struct constant_pool
*pool
;
6073 pool
= s390_alloc_pool ();
6075 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6077 if (GET_CODE (insn
) == INSN
6078 && GET_CODE (PATTERN (insn
)) == SET
6079 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6080 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6082 gcc_assert (!pool
->pool_insn
);
6083 pool
->pool_insn
= insn
;
6086 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6088 s390_add_execute (pool
, insn
);
6090 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6092 rtx pool_ref
= NULL_RTX
;
6093 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6096 rtx constant
= get_pool_constant (pool_ref
);
6097 enum machine_mode mode
= get_pool_mode (pool_ref
);
6098 s390_add_constant (pool
, constant
, mode
);
6102 /* If hot/cold partitioning is enabled we have to make sure that
6103 the literal pool is emitted in the same section where the
6104 initialization of the literal pool base pointer takes place.
6105 emit_pool_after is only used in the non-overflow case on non
6106 Z cpus where we can emit the literal pool at the end of the
6107 function body within the text section. */
6109 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6110 && !pool
->emit_pool_after
)
6111 pool
->emit_pool_after
= PREV_INSN (insn
);
6114 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6116 if (pool
->size
>= 4096)
6118 /* We're going to chunkify the pool, so remove the main
6119 pool placeholder insn. */
6120 remove_insn (pool
->pool_insn
);
6122 s390_free_pool (pool
);
6126 /* If the functions ends with the section where the literal pool
6127 should be emitted set the marker to its end. */
6128 if (pool
&& !pool
->emit_pool_after
)
6129 pool
->emit_pool_after
= get_last_insn ();
6134 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6135 Modify the current function to output the pool constants as well as
6136 the pool register setup instruction. */
6139 s390_mainpool_finish (struct constant_pool
*pool
)
6141 rtx base_reg
= cfun
->machine
->base_reg
;
6144 /* If the pool is empty, we're done. */
6145 if (pool
->size
== 0)
6147 /* We don't actually need a base register after all. */
6148 cfun
->machine
->base_reg
= NULL_RTX
;
6150 if (pool
->pool_insn
)
6151 remove_insn (pool
->pool_insn
);
6152 s390_free_pool (pool
);
6156 /* We need correct insn addresses. */
6157 shorten_branches (get_insns ());
6159 /* On zSeries, we use a LARL to load the pool register. The pool is
6160 located in the .rodata section, so we emit it after the function. */
6161 if (TARGET_CPU_ZARCH
)
6163 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6164 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6165 INSN_ADDRESSES_NEW (insn
, -1);
6166 remove_insn (pool
->pool_insn
);
6168 insn
= get_last_insn ();
6169 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6170 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6172 s390_dump_pool (pool
, 0);
6175 /* On S/390, if the total size of the function's code plus literal pool
6176 does not exceed 4096 bytes, we use BASR to set up a function base
6177 pointer, and emit the literal pool at the end of the function. */
6178 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6179 + pool
->size
+ 8 /* alignment slop */ < 4096)
6181 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6182 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6183 INSN_ADDRESSES_NEW (insn
, -1);
6184 remove_insn (pool
->pool_insn
);
6186 insn
= emit_label_after (pool
->label
, insn
);
6187 INSN_ADDRESSES_NEW (insn
, -1);
6189 /* emit_pool_after will be set by s390_mainpool_start to the
6190 last insn of the section where the literal pool should be
6192 insn
= pool
->emit_pool_after
;
6194 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6195 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6197 s390_dump_pool (pool
, 1);
6200 /* Otherwise, we emit an inline literal pool and use BASR to branch
6201 over it, setting up the pool register at the same time. */
6204 rtx pool_end
= gen_label_rtx ();
6206 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6207 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6208 INSN_ADDRESSES_NEW (insn
, -1);
6209 remove_insn (pool
->pool_insn
);
6211 insn
= emit_label_after (pool
->label
, insn
);
6212 INSN_ADDRESSES_NEW (insn
, -1);
6214 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6215 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6217 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6218 INSN_ADDRESSES_NEW (insn
, -1);
6220 s390_dump_pool (pool
, 1);
6224 /* Replace all literal pool references. */
6226 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6229 replace_ltrel_base (&PATTERN (insn
));
6231 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6233 rtx addr
, pool_ref
= NULL_RTX
;
6234 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6237 if (s390_execute_label (insn
))
6238 addr
= s390_find_execute (pool
, insn
);
6240 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6241 get_pool_mode (pool_ref
));
6243 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6244 INSN_CODE (insn
) = -1;
6250 /* Free the pool. */
6251 s390_free_pool (pool
);
6254 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6255 We have decided we cannot use this pool, so revert all changes
6256 to the current function that were done by s390_mainpool_start. */
6258 s390_mainpool_cancel (struct constant_pool
*pool
)
6260 /* We didn't actually change the instruction stream, so simply
6261 free the pool memory. */
6262 s390_free_pool (pool
);
6266 /* Chunkify the literal pool. */
6268 #define S390_POOL_CHUNK_MIN 0xc00
6269 #define S390_POOL_CHUNK_MAX 0xe00
6271 static struct constant_pool
*
6272 s390_chunkify_start (void)
6274 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6277 rtx pending_ltrel
= NULL_RTX
;
6280 rtx (*gen_reload_base
) (rtx
, rtx
) =
6281 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6284 /* We need correct insn addresses. */
6286 shorten_branches (get_insns ());
6288 /* Scan all insns and move literals to pool chunks. */
6290 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6292 bool section_switch_p
= false;
6294 /* Check for pending LTREL_BASE. */
6297 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6300 gcc_assert (ltrel_base
== pending_ltrel
);
6301 pending_ltrel
= NULL_RTX
;
6305 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6308 curr_pool
= s390_start_pool (&pool_list
, insn
);
6310 s390_add_execute (curr_pool
, insn
);
6311 s390_add_pool_insn (curr_pool
, insn
);
6313 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6315 rtx pool_ref
= NULL_RTX
;
6316 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6319 rtx constant
= get_pool_constant (pool_ref
);
6320 enum machine_mode mode
= get_pool_mode (pool_ref
);
6323 curr_pool
= s390_start_pool (&pool_list
, insn
);
6325 s390_add_constant (curr_pool
, constant
, mode
);
6326 s390_add_pool_insn (curr_pool
, insn
);
6328 /* Don't split the pool chunk between a LTREL_OFFSET load
6329 and the corresponding LTREL_BASE. */
6330 if (GET_CODE (constant
) == CONST
6331 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6332 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6334 gcc_assert (!pending_ltrel
);
6335 pending_ltrel
= pool_ref
;
6340 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6343 s390_add_pool_insn (curr_pool
, insn
);
6344 /* An LTREL_BASE must follow within the same basic block. */
6345 gcc_assert (!pending_ltrel
);
6348 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
6349 section_switch_p
= true;
6352 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6353 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6356 if (TARGET_CPU_ZARCH
)
6358 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6361 s390_end_pool (curr_pool
, NULL_RTX
);
6366 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6367 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6370 /* We will later have to insert base register reload insns.
6371 Those will have an effect on code size, which we need to
6372 consider here. This calculation makes rather pessimistic
6373 worst-case assumptions. */
6374 if (GET_CODE (insn
) == CODE_LABEL
)
6377 if (chunk_size
< S390_POOL_CHUNK_MIN
6378 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6379 && !section_switch_p
)
6382 /* Pool chunks can only be inserted after BARRIERs ... */
6383 if (GET_CODE (insn
) == BARRIER
)
6385 s390_end_pool (curr_pool
, insn
);
6390 /* ... so if we don't find one in time, create one. */
6391 else if (chunk_size
> S390_POOL_CHUNK_MAX
6392 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6393 || section_switch_p
)
6395 rtx label
, jump
, barrier
;
6397 if (!section_switch_p
)
6399 /* We can insert the barrier only after a 'real' insn. */
6400 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6402 if (get_attr_length (insn
) == 0)
6404 /* Don't separate LTREL_BASE from the corresponding
6405 LTREL_OFFSET load. */
6411 gcc_assert (!pending_ltrel
);
6413 /* The old pool has to end before the section switch
6414 note in order to make it part of the current
6416 insn
= PREV_INSN (insn
);
6419 label
= gen_label_rtx ();
6420 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
6421 barrier
= emit_barrier_after (jump
);
6422 insn
= emit_label_after (label
, barrier
);
6423 JUMP_LABEL (jump
) = label
;
6424 LABEL_NUSES (label
) = 1;
6426 INSN_ADDRESSES_NEW (jump
, -1);
6427 INSN_ADDRESSES_NEW (barrier
, -1);
6428 INSN_ADDRESSES_NEW (insn
, -1);
6430 s390_end_pool (curr_pool
, barrier
);
6438 s390_end_pool (curr_pool
, NULL_RTX
);
6439 gcc_assert (!pending_ltrel
);
6441 /* Find all labels that are branched into
6442 from an insn belonging to a different chunk. */
6444 far_labels
= BITMAP_ALLOC (NULL
);
6446 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6448 /* Labels marked with LABEL_PRESERVE_P can be target
6449 of non-local jumps, so we have to mark them.
6450 The same holds for named labels.
6452 Don't do that, however, if it is the label before
6455 if (GET_CODE (insn
) == CODE_LABEL
6456 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6458 rtx vec_insn
= next_real_insn (insn
);
6459 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6460 PATTERN (vec_insn
) : NULL_RTX
;
6462 || !(GET_CODE (vec_pat
) == ADDR_VEC
6463 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6464 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6467 /* If we have a direct jump (conditional or unconditional)
6468 or a casesi jump, check all potential targets. */
6469 else if (GET_CODE (insn
) == JUMP_INSN
)
6471 rtx pat
= PATTERN (insn
);
6472 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6473 pat
= XVECEXP (pat
, 0, 0);
6475 if (GET_CODE (pat
) == SET
)
6477 rtx label
= JUMP_LABEL (insn
);
6480 if (s390_find_pool (pool_list
, label
)
6481 != s390_find_pool (pool_list
, insn
))
6482 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6485 else if (GET_CODE (pat
) == PARALLEL
6486 && XVECLEN (pat
, 0) == 2
6487 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6488 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6489 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6491 /* Find the jump table used by this casesi jump. */
6492 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6493 rtx vec_insn
= next_real_insn (vec_label
);
6494 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6495 PATTERN (vec_insn
) : NULL_RTX
;
6497 && (GET_CODE (vec_pat
) == ADDR_VEC
6498 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6500 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6502 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6504 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6506 if (s390_find_pool (pool_list
, label
)
6507 != s390_find_pool (pool_list
, insn
))
6508 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6515 /* Insert base register reload insns before every pool. */
6517 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6519 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6521 rtx insn
= curr_pool
->first_insn
;
6522 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6525 /* Insert base register reload insns at every far label. */
6527 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6528 if (GET_CODE (insn
) == CODE_LABEL
6529 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6531 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6534 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6536 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6541 BITMAP_FREE (far_labels
);
6544 /* Recompute insn addresses. */
6546 init_insn_lengths ();
6547 shorten_branches (get_insns ());
6552 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6553 After we have decided to use this list, finish implementing
6554 all changes to the current function as required. */
6557 s390_chunkify_finish (struct constant_pool
*pool_list
)
6559 struct constant_pool
*curr_pool
= NULL
;
6563 /* Replace all literal pool references. */
6565 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6568 replace_ltrel_base (&PATTERN (insn
));
6570 curr_pool
= s390_find_pool (pool_list
, insn
);
6574 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6576 rtx addr
, pool_ref
= NULL_RTX
;
6577 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6580 if (s390_execute_label (insn
))
6581 addr
= s390_find_execute (curr_pool
, insn
);
6583 addr
= s390_find_constant (curr_pool
,
6584 get_pool_constant (pool_ref
),
6585 get_pool_mode (pool_ref
));
6587 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6588 INSN_CODE (insn
) = -1;
6593 /* Dump out all literal pools. */
6595 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6596 s390_dump_pool (curr_pool
, 0);
6598 /* Free pool list. */
6602 struct constant_pool
*next
= pool_list
->next
;
6603 s390_free_pool (pool_list
);
6608 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6609 We have decided we cannot use this list, so revert all changes
6610 to the current function that were done by s390_chunkify_start. */
6613 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6615 struct constant_pool
*curr_pool
= NULL
;
6618 /* Remove all pool placeholder insns. */
6620 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6622 /* Did we insert an extra barrier? Remove it. */
6623 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6624 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6625 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6627 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6628 && barrier
&& GET_CODE (barrier
) == BARRIER
6629 && label
&& GET_CODE (label
) == CODE_LABEL
6630 && GET_CODE (PATTERN (jump
)) == SET
6631 && SET_DEST (PATTERN (jump
)) == pc_rtx
6632 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6633 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6636 remove_insn (barrier
);
6637 remove_insn (label
);
6640 remove_insn (curr_pool
->pool_insn
);
6643 /* Remove all base register reload insns. */
6645 for (insn
= get_insns (); insn
; )
6647 rtx next_insn
= NEXT_INSN (insn
);
6649 if (GET_CODE (insn
) == INSN
6650 && GET_CODE (PATTERN (insn
)) == SET
6651 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
6652 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
6658 /* Free pool list. */
6662 struct constant_pool
*next
= pool_list
->next
;
6663 s390_free_pool (pool_list
);
6668 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6671 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
6675 switch (GET_MODE_CLASS (mode
))
6678 case MODE_DECIMAL_FLOAT
:
6679 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
6681 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
6682 assemble_real (r
, mode
, align
);
6686 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
6687 mark_symbol_refs_as_used (exp
);
6696 /* Return an RTL expression representing the value of the return address
6697 for the frame COUNT steps up from the current frame. FRAME is the
6698 frame pointer of that frame. */
6701 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
6706 /* Without backchain, we fail for all but the current frame. */
6708 if (!TARGET_BACKCHAIN
&& count
> 0)
6711 /* For the current frame, we need to make sure the initial
6712 value of RETURN_REGNUM is actually saved. */
6716 /* On non-z architectures branch splitting could overwrite r14. */
6717 if (TARGET_CPU_ZARCH
)
6718 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
6721 cfun_frame_layout
.save_return_addr_p
= true;
6722 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
6726 if (TARGET_PACKED_STACK
)
6727 offset
= -2 * UNITS_PER_WORD
;
6729 offset
= RETURN_REGNUM
* UNITS_PER_WORD
;
6731 addr
= plus_constant (frame
, offset
);
6732 addr
= memory_address (Pmode
, addr
);
6733 return gen_rtx_MEM (Pmode
, addr
);
6736 /* Return an RTL expression representing the back chain stored in
6737 the current stack frame. */
6740 s390_back_chain_rtx (void)
6744 gcc_assert (TARGET_BACKCHAIN
);
6746 if (TARGET_PACKED_STACK
)
6747 chain
= plus_constant (stack_pointer_rtx
,
6748 STACK_POINTER_OFFSET
- UNITS_PER_WORD
);
6750 chain
= stack_pointer_rtx
;
6752 chain
= gen_rtx_MEM (Pmode
, chain
);
6756 /* Find first call clobbered register unused in a function.
6757 This could be used as base register in a leaf function
6758 or for holding the return address before epilogue. */
6761 find_unused_clobbered_reg (void)
6764 for (i
= 0; i
< 6; i
++)
6765 if (!df_regs_ever_live_p (i
))
6771 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6772 clobbered hard regs in SETREG. */
6775 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
6777 int *regs_ever_clobbered
= (int *)data
;
6778 unsigned int i
, regno
;
6779 enum machine_mode mode
= GET_MODE (setreg
);
6781 if (GET_CODE (setreg
) == SUBREG
)
6783 rtx inner
= SUBREG_REG (setreg
);
6784 if (!GENERAL_REG_P (inner
))
6786 regno
= subreg_regno (setreg
);
6788 else if (GENERAL_REG_P (setreg
))
6789 regno
= REGNO (setreg
);
6794 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
6796 regs_ever_clobbered
[i
] = 1;
6799 /* Walks through all basic blocks of the current function looking
6800 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6801 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6802 each of those regs. */
6805 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
6811 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
6813 /* For non-leaf functions we have to consider all call clobbered regs to be
6815 if (!current_function_is_leaf
)
6817 for (i
= 0; i
< 16; i
++)
6818 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
6821 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6822 this work is done by liveness analysis (mark_regs_live_at_end).
6823 Special care is needed for functions containing landing pads. Landing pads
6824 may use the eh registers, but the code which sets these registers is not
6825 contained in that function. Hence s390_regs_ever_clobbered is not able to
6826 deal with this automatically. */
6827 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
6828 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
6829 if (crtl
->calls_eh_return
6830 || (cfun
->machine
->has_landing_pad_p
6831 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
6832 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
6834 /* For nonlocal gotos all call-saved registers have to be saved.
6835 This flag is also set for the unwinding code in libgcc.
6836 See expand_builtin_unwind_init. For regs_ever_live this is done by
6838 if (cfun
->has_nonlocal_label
)
6839 for (i
= 0; i
< 16; i
++)
6840 if (!call_really_used_regs
[i
])
6841 regs_ever_clobbered
[i
] = 1;
6843 FOR_EACH_BB (cur_bb
)
6845 FOR_BB_INSNS (cur_bb
, cur_insn
)
6847 if (INSN_P (cur_insn
))
6848 note_stores (PATTERN (cur_insn
),
6849 s390_reg_clobbered_rtx
,
6850 regs_ever_clobbered
);
6855 /* Determine the frame area which actually has to be accessed
6856 in the function epilogue. The values are stored at the
6857 given pointers AREA_BOTTOM (address of the lowest used stack
6858 address) and AREA_TOP (address of the first item which does
6859 not belong to the stack frame). */
6862 s390_frame_area (int *area_bottom
, int *area_top
)
6870 if (cfun_frame_layout
.first_restore_gpr
!= -1)
6872 b
= (cfun_frame_layout
.gprs_offset
6873 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_WORD
);
6874 t
= b
+ (cfun_frame_layout
.last_restore_gpr
6875 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_WORD
;
6878 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
6880 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
6881 t
= MAX (t
, (cfun_frame_layout
.f8_offset
6882 + cfun_frame_layout
.high_fprs
* 8));
6886 for (i
= 2; i
< 4; i
++)
6887 if (cfun_fpr_bit_p (i
))
6889 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
6890 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
6897 /* Fill cfun->machine with info about register usage of current function.
6898 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6901 s390_register_info (int clobbered_regs
[])
6905 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6906 cfun_frame_layout
.fpr_bitmap
= 0;
6907 cfun_frame_layout
.high_fprs
= 0;
6909 for (i
= 24; i
< 32; i
++)
6910 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
6912 cfun_set_fpr_bit (i
- 16);
6913 cfun_frame_layout
.high_fprs
++;
6916 /* Find first and last gpr to be saved. We trust regs_ever_live
6917 data, except that we don't save and restore global registers.
6919 Also, all registers with special meaning to the compiler need
6920 to be handled extra. */
6922 s390_regs_ever_clobbered (clobbered_regs
);
6924 for (i
= 0; i
< 16; i
++)
6925 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
6927 if (frame_pointer_needed
)
6928 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
6931 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
6932 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
6934 clobbered_regs
[BASE_REGNUM
]
6935 |= (cfun
->machine
->base_reg
6936 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
6938 clobbered_regs
[RETURN_REGNUM
]
6939 |= (!current_function_is_leaf
6940 || TARGET_TPF_PROFILING
6941 || cfun
->machine
->split_branches_pending_p
6942 || cfun_frame_layout
.save_return_addr_p
6943 || crtl
->calls_eh_return
6946 clobbered_regs
[STACK_POINTER_REGNUM
]
6947 |= (!current_function_is_leaf
6948 || TARGET_TPF_PROFILING
6949 || cfun_save_high_fprs_p
6950 || get_frame_size () > 0
6951 || cfun
->calls_alloca
6954 for (i
= 6; i
< 16; i
++)
6955 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
6957 for (j
= 15; j
> i
; j
--)
6958 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
6963 /* Nothing to save/restore. */
6964 cfun_frame_layout
.first_save_gpr_slot
= -1;
6965 cfun_frame_layout
.last_save_gpr_slot
= -1;
6966 cfun_frame_layout
.first_save_gpr
= -1;
6967 cfun_frame_layout
.first_restore_gpr
= -1;
6968 cfun_frame_layout
.last_save_gpr
= -1;
6969 cfun_frame_layout
.last_restore_gpr
= -1;
6973 /* Save slots for gprs from i to j. */
6974 cfun_frame_layout
.first_save_gpr_slot
= i
;
6975 cfun_frame_layout
.last_save_gpr_slot
= j
;
6977 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
6978 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
6980 if (clobbered_regs
[i
])
6983 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
6984 if (clobbered_regs
[j
])
6987 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
6989 /* Nothing to save/restore. */
6990 cfun_frame_layout
.first_save_gpr
= -1;
6991 cfun_frame_layout
.first_restore_gpr
= -1;
6992 cfun_frame_layout
.last_save_gpr
= -1;
6993 cfun_frame_layout
.last_restore_gpr
= -1;
6997 /* Save / Restore from gpr i to j. */
6998 cfun_frame_layout
.first_save_gpr
= i
;
6999 cfun_frame_layout
.first_restore_gpr
= i
;
7000 cfun_frame_layout
.last_save_gpr
= j
;
7001 cfun_frame_layout
.last_restore_gpr
= j
;
7007 /* Varargs functions need to save gprs 2 to 6. */
7008 if (cfun
->va_list_gpr_size
7009 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7011 int min_gpr
= crtl
->args
.info
.gprs
;
7012 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7013 if (max_gpr
> GP_ARG_NUM_REG
)
7014 max_gpr
= GP_ARG_NUM_REG
;
7016 if (cfun_frame_layout
.first_save_gpr
== -1
7017 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7019 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7020 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7023 if (cfun_frame_layout
.last_save_gpr
== -1
7024 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7026 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7027 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7031 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7032 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7033 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7035 int min_fpr
= crtl
->args
.info
.fprs
;
7036 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7037 if (max_fpr
> FP_ARG_NUM_REG
)
7038 max_fpr
= FP_ARG_NUM_REG
;
7040 /* ??? This is currently required to ensure proper location
7041 of the fpr save slots within the va_list save area. */
7042 if (TARGET_PACKED_STACK
)
7045 for (i
= min_fpr
; i
< max_fpr
; i
++)
7046 cfun_set_fpr_bit (i
);
7051 for (i
= 2; i
< 4; i
++)
7052 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7053 cfun_set_fpr_bit (i
);
7056 /* Fill cfun->machine with info about frame of current function. */
7059 s390_frame_info (void)
7063 cfun_frame_layout
.frame_size
= get_frame_size ();
7064 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7065 fatal_error ("total size of local variables exceeds architecture limit");
7067 if (!TARGET_PACKED_STACK
)
7069 cfun_frame_layout
.backchain_offset
= 0;
7070 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_WORD
;
7071 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7072 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7073 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7076 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7078 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7080 cfun_frame_layout
.gprs_offset
7081 = (cfun_frame_layout
.backchain_offset
7082 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7087 cfun_frame_layout
.f4_offset
7088 = (cfun_frame_layout
.gprs_offset
7089 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7091 cfun_frame_layout
.f0_offset
7092 = (cfun_frame_layout
.f4_offset
7093 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7097 /* On 31 bit we have to care about alignment of the
7098 floating point regs to provide fastest access. */
7099 cfun_frame_layout
.f0_offset
7100 = ((cfun_frame_layout
.gprs_offset
7101 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7102 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7104 cfun_frame_layout
.f4_offset
7105 = (cfun_frame_layout
.f0_offset
7106 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7109 else /* no backchain */
7111 cfun_frame_layout
.f4_offset
7112 = (STACK_POINTER_OFFSET
7113 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7115 cfun_frame_layout
.f0_offset
7116 = (cfun_frame_layout
.f4_offset
7117 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7119 cfun_frame_layout
.gprs_offset
7120 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7123 if (current_function_is_leaf
7124 && !TARGET_TPF_PROFILING
7125 && cfun_frame_layout
.frame_size
== 0
7126 && !cfun_save_high_fprs_p
7127 && !cfun
->calls_alloca
7131 if (!TARGET_PACKED_STACK
)
7132 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7133 + crtl
->outgoing_args_size
7134 + cfun_frame_layout
.high_fprs
* 8);
7137 if (TARGET_BACKCHAIN
)
7138 cfun_frame_layout
.frame_size
+= UNITS_PER_WORD
;
7140 /* No alignment trouble here because f8-f15 are only saved under
7142 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7143 cfun_frame_layout
.f4_offset
),
7144 cfun_frame_layout
.gprs_offset
)
7145 - cfun_frame_layout
.high_fprs
* 8);
7147 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7149 for (i
= 0; i
< 8; i
++)
7150 if (cfun_fpr_bit_p (i
))
7151 cfun_frame_layout
.frame_size
+= 8;
7153 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7155 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7156 the frame size to sustain 8 byte alignment of stack frames. */
7157 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7158 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7159 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7161 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7165 /* Generate frame layout. Fills in register and frame data for the current
7166 function in cfun->machine. This routine can be called multiple times;
7167 it will re-do the complete frame layout every time. */
7170 s390_init_frame_layout (void)
7172 HOST_WIDE_INT frame_size
;
7174 int clobbered_regs
[16];
7176 /* On S/390 machines, we may need to perform branch splitting, which
7177 will require both base and return address register. We have no
7178 choice but to assume we're going to need them until right at the
7179 end of the machine dependent reorg phase. */
7180 if (!TARGET_CPU_ZARCH
)
7181 cfun
->machine
->split_branches_pending_p
= true;
7185 frame_size
= cfun_frame_layout
.frame_size
;
7187 /* Try to predict whether we'll need the base register. */
7188 base_used
= cfun
->machine
->split_branches_pending_p
7189 || crtl
->uses_const_pool
7190 || (!DISP_IN_RANGE (frame_size
)
7191 && !CONST_OK_FOR_K (frame_size
));
7193 /* Decide which register to use as literal pool base. In small
7194 leaf functions, try to use an unused call-clobbered register
7195 as base register to avoid save/restore overhead. */
7197 cfun
->machine
->base_reg
= NULL_RTX
;
7198 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
7199 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7201 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7203 s390_register_info (clobbered_regs
);
7206 while (frame_size
!= cfun_frame_layout
.frame_size
);
7209 /* Update frame layout. Recompute actual register save data based on
7210 current info and update regs_ever_live for the special registers.
7211 May be called multiple times, but may never cause *more* registers
7212 to be saved than s390_init_frame_layout allocated room for. */
7215 s390_update_frame_layout (void)
7217 int clobbered_regs
[16];
7219 s390_register_info (clobbered_regs
);
7221 df_set_regs_ever_live (BASE_REGNUM
,
7222 clobbered_regs
[BASE_REGNUM
] ? true : false);
7223 df_set_regs_ever_live (RETURN_REGNUM
,
7224 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7225 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7226 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7228 if (cfun
->machine
->base_reg
)
7229 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7232 /* Return true if it is legal to put a value with MODE into REGNO. */
7235 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7237 switch (REGNO_REG_CLASS (regno
))
7240 if (REGNO_PAIR_OK (regno
, mode
))
7242 if (mode
== SImode
|| mode
== DImode
)
7245 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7250 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7255 if (REGNO_PAIR_OK (regno
, mode
))
7258 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7263 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7267 if (REGNO_PAIR_OK (regno
, mode
))
7269 if (mode
== SImode
|| mode
== Pmode
)
7280 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7283 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7285 /* Once we've decided upon a register to use as base register, it must
7286 no longer be used for any other purpose. */
7287 if (cfun
->machine
->base_reg
)
7288 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7289 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7295 /* Maximum number of registers to represent a value of mode MODE
7296 in a register of class RCLASS. */
7299 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7304 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7305 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7307 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7309 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7313 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7316 /* Return true if register FROM can be eliminated via register TO. */
7319 s390_can_eliminate (int from
, int to
)
7321 /* On zSeries machines, we have not marked the base register as fixed.
7322 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7323 If a function requires the base register, we say here that this
7324 elimination cannot be performed. This will cause reload to free
7325 up the base register (as if it were fixed). On the other hand,
7326 if the current function does *not* require the base register, we
7327 say here the elimination succeeds, which in turn allows reload
7328 to allocate the base register for any other purpose. */
7329 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7331 if (TARGET_CPU_ZARCH
)
7333 s390_init_frame_layout ();
7334 return cfun
->machine
->base_reg
== NULL_RTX
;
7340 /* Everything else must point into the stack frame. */
7341 gcc_assert (to
== STACK_POINTER_REGNUM
7342 || to
== HARD_FRAME_POINTER_REGNUM
);
7344 gcc_assert (from
== FRAME_POINTER_REGNUM
7345 || from
== ARG_POINTER_REGNUM
7346 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7348 /* Make sure we actually saved the return address. */
7349 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7350 if (!crtl
->calls_eh_return
7352 && !cfun_frame_layout
.save_return_addr_p
)
7358 /* Return offset between register FROM and TO initially after prolog. */
7361 s390_initial_elimination_offset (int from
, int to
)
7363 HOST_WIDE_INT offset
;
7366 /* ??? Why are we called for non-eliminable pairs? */
7367 if (!s390_can_eliminate (from
, to
))
7372 case FRAME_POINTER_REGNUM
:
7373 offset
= (get_frame_size()
7374 + STACK_POINTER_OFFSET
7375 + crtl
->outgoing_args_size
);
7378 case ARG_POINTER_REGNUM
:
7379 s390_init_frame_layout ();
7380 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7383 case RETURN_ADDRESS_POINTER_REGNUM
:
7384 s390_init_frame_layout ();
7385 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7386 gcc_assert (index
>= 0);
7387 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7388 offset
+= index
* UNITS_PER_WORD
;
7402 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7403 to register BASE. Return generated insn. */
7406 save_fpr (rtx base
, int offset
, int regnum
)
7409 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7411 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7412 set_mem_alias_set (addr
, get_varargs_alias_set ());
7414 set_mem_alias_set (addr
, get_frame_alias_set ());
7416 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7419 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7420 to register BASE. Return generated insn. */
7423 restore_fpr (rtx base
, int offset
, int regnum
)
7426 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7427 set_mem_alias_set (addr
, get_frame_alias_set ());
7429 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7432 /* Generate insn to save registers FIRST to LAST into
7433 the register save area located at offset OFFSET
7434 relative to register BASE. */
7437 save_gprs (rtx base
, int offset
, int first
, int last
)
7439 rtx addr
, insn
, note
;
7442 addr
= plus_constant (base
, offset
);
7443 addr
= gen_rtx_MEM (Pmode
, addr
);
7445 set_mem_alias_set (addr
, get_frame_alias_set ());
7447 /* Special-case single register. */
7451 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7453 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7455 RTX_FRAME_RELATED_P (insn
) = 1;
7460 insn
= gen_store_multiple (addr
,
7461 gen_rtx_REG (Pmode
, first
),
7462 GEN_INT (last
- first
+ 1));
7464 if (first
<= 6 && cfun
->stdarg
)
7465 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7467 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7470 set_mem_alias_set (mem
, get_varargs_alias_set ());
7473 /* We need to set the FRAME_RELATED flag on all SETs
7474 inside the store-multiple pattern.
7476 However, we must not emit DWARF records for registers 2..5
7477 if they are stored for use by variable arguments ...
7479 ??? Unfortunately, it is not enough to simply not the
7480 FRAME_RELATED flags for those SETs, because the first SET
7481 of the PARALLEL is always treated as if it had the flag
7482 set, even if it does not. Therefore we emit a new pattern
7483 without those registers as REG_FRAME_RELATED_EXPR note. */
7487 rtx pat
= PATTERN (insn
);
7489 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7490 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
7491 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7493 RTX_FRAME_RELATED_P (insn
) = 1;
7497 addr
= plus_constant (base
, offset
+ (6 - first
) * UNITS_PER_WORD
);
7498 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7499 gen_rtx_REG (Pmode
, 6),
7500 GEN_INT (last
- 6 + 1));
7501 note
= PATTERN (note
);
7503 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
7505 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7506 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
)
7507 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7509 RTX_FRAME_RELATED_P (insn
) = 1;
7515 /* Generate insn to restore registers FIRST to LAST from
7516 the register save area located at offset OFFSET
7517 relative to register BASE. */
7520 restore_gprs (rtx base
, int offset
, int first
, int last
)
7524 addr
= plus_constant (base
, offset
);
7525 addr
= gen_rtx_MEM (Pmode
, addr
);
7526 set_mem_alias_set (addr
, get_frame_alias_set ());
7528 /* Special-case single register. */
7532 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7534 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7539 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7541 GEN_INT (last
- first
+ 1));
7545 /* Return insn sequence to load the GOT register. */
7547 static GTY(()) rtx got_symbol
;
7549 s390_load_got (void)
7555 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7556 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7561 if (TARGET_CPU_ZARCH
)
7563 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7569 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7570 UNSPEC_LTREL_OFFSET
);
7571 offset
= gen_rtx_CONST (Pmode
, offset
);
7572 offset
= force_const_mem (Pmode
, offset
);
7574 emit_move_insn (pic_offset_table_rtx
, offset
);
7576 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7578 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
7580 emit_move_insn (pic_offset_table_rtx
, offset
);
7583 insns
= get_insns ();
7588 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7589 and the change to the stack pointer. */
7592 s390_emit_stack_tie (void)
7594 rtx mem
= gen_frame_mem (BLKmode
,
7595 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
7597 emit_insn (gen_stack_tie (mem
));
7600 /* Expand the prologue into a bunch of separate insns. */
7603 s390_emit_prologue (void)
7611 /* Complete frame layout. */
7613 s390_update_frame_layout ();
7615 /* Annotate all constant pool references to let the scheduler know
7616 they implicitly use the base register. */
7618 push_topmost_sequence ();
7620 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7623 annotate_constant_pool_refs (&PATTERN (insn
));
7624 df_insn_rescan (insn
);
7627 pop_topmost_sequence ();
7629 /* Choose best register to use for temp use within prologue.
7630 See below for why TPF must use the register 1. */
7632 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
7633 && !current_function_is_leaf
7634 && !TARGET_TPF_PROFILING
)
7635 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7637 temp_reg
= gen_rtx_REG (Pmode
, 1);
7639 /* Save call saved gprs. */
7640 if (cfun_frame_layout
.first_save_gpr
!= -1)
7642 insn
= save_gprs (stack_pointer_rtx
,
7643 cfun_frame_layout
.gprs_offset
+
7644 UNITS_PER_WORD
* (cfun_frame_layout
.first_save_gpr
7645 - cfun_frame_layout
.first_save_gpr_slot
),
7646 cfun_frame_layout
.first_save_gpr
,
7647 cfun_frame_layout
.last_save_gpr
);
7651 /* Dummy insn to mark literal pool slot. */
7653 if (cfun
->machine
->base_reg
)
7654 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
7656 offset
= cfun_frame_layout
.f0_offset
;
7658 /* Save f0 and f2. */
7659 for (i
= 0; i
< 2; i
++)
7661 if (cfun_fpr_bit_p (i
))
7663 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7666 else if (!TARGET_PACKED_STACK
)
7670 /* Save f4 and f6. */
7671 offset
= cfun_frame_layout
.f4_offset
;
7672 for (i
= 2; i
< 4; i
++)
7674 if (cfun_fpr_bit_p (i
))
7676 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7679 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7680 therefore are not frame related. */
7681 if (!call_really_used_regs
[i
+ 16])
7682 RTX_FRAME_RELATED_P (insn
) = 1;
7684 else if (!TARGET_PACKED_STACK
)
7688 if (TARGET_PACKED_STACK
7689 && cfun_save_high_fprs_p
7690 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
7692 offset
= (cfun_frame_layout
.f8_offset
7693 + (cfun_frame_layout
.high_fprs
- 1) * 8);
7695 for (i
= 15; i
> 7 && offset
>= 0; i
--)
7696 if (cfun_fpr_bit_p (i
))
7698 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7700 RTX_FRAME_RELATED_P (insn
) = 1;
7703 if (offset
>= cfun_frame_layout
.f8_offset
)
7707 if (!TARGET_PACKED_STACK
)
7708 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
7710 /* Decrement stack pointer. */
7712 if (cfun_frame_layout
.frame_size
> 0)
7714 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
7717 if (s390_stack_size
)
7719 HOST_WIDE_INT stack_guard
;
7721 if (s390_stack_guard
)
7722 stack_guard
= s390_stack_guard
;
7725 /* If no value for stack guard is provided the smallest power of 2
7726 larger than the current frame size is chosen. */
7728 while (stack_guard
< cfun_frame_layout
.frame_size
)
7732 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
7734 warning (0, "frame size of function %qs is "
7735 HOST_WIDE_INT_PRINT_DEC
7736 " bytes exceeding user provided stack limit of "
7737 HOST_WIDE_INT_PRINT_DEC
" bytes. "
7738 "An unconditional trap is added.",
7739 current_function_name(), cfun_frame_layout
.frame_size
,
7741 emit_insn (gen_trap ());
7745 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
7746 & ~(stack_guard
- 1));
7747 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
7748 GEN_INT (stack_check_mask
));
7750 gen_cmpdi (t
, const0_rtx
);
7752 gen_cmpsi (t
, const0_rtx
);
7754 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode
,
7755 gen_rtx_REG (CCmode
,
7762 if (s390_warn_framesize
> 0
7763 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
7764 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC
" bytes",
7765 current_function_name (), cfun_frame_layout
.frame_size
);
7767 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
7768 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7770 /* Save incoming stack pointer into temp reg. */
7771 if (TARGET_BACKCHAIN
|| next_fpr
)
7772 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
7774 /* Subtract frame size from stack pointer. */
7776 if (DISP_IN_RANGE (INTVAL (frame_off
)))
7778 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7779 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7781 insn
= emit_insn (insn
);
7785 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
7786 frame_off
= force_const_mem (Pmode
, frame_off
);
7788 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
7789 annotate_constant_pool_refs (&PATTERN (insn
));
7792 RTX_FRAME_RELATED_P (insn
) = 1;
7793 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
7794 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
7795 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7796 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7799 /* Set backchain. */
7801 if (TARGET_BACKCHAIN
)
7803 if (cfun_frame_layout
.backchain_offset
)
7804 addr
= gen_rtx_MEM (Pmode
,
7805 plus_constant (stack_pointer_rtx
,
7806 cfun_frame_layout
.backchain_offset
));
7808 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
7809 set_mem_alias_set (addr
, get_frame_alias_set ());
7810 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
7813 /* If we support asynchronous exceptions (e.g. for Java),
7814 we need to make sure the backchain pointer is set up
7815 before any possibly trapping memory access. */
7817 if (TARGET_BACKCHAIN
&& flag_non_call_exceptions
)
7819 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
7820 emit_clobber (addr
);
7824 /* Save fprs 8 - 15 (64 bit ABI). */
7826 if (cfun_save_high_fprs_p
&& next_fpr
)
7828 /* If the stack might be accessed through a different register
7829 we have to make sure that the stack pointer decrement is not
7830 moved below the use of the stack slots. */
7831 s390_emit_stack_tie ();
7833 insn
= emit_insn (gen_add2_insn (temp_reg
,
7834 GEN_INT (cfun_frame_layout
.f8_offset
)));
7838 for (i
= 24; i
<= next_fpr
; i
++)
7839 if (cfun_fpr_bit_p (i
- 16))
7841 rtx addr
= plus_constant (stack_pointer_rtx
,
7842 cfun_frame_layout
.frame_size
7843 + cfun_frame_layout
.f8_offset
7846 insn
= save_fpr (temp_reg
, offset
, i
);
7848 RTX_FRAME_RELATED_P (insn
) = 1;
7849 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
7850 gen_rtx_SET (VOIDmode
,
7851 gen_rtx_MEM (DFmode
, addr
),
7852 gen_rtx_REG (DFmode
, i
)));
7856 /* Set frame pointer, if needed. */
7858 if (frame_pointer_needed
)
7860 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
7861 RTX_FRAME_RELATED_P (insn
) = 1;
7864 /* Set up got pointer, if needed. */
7866 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
7868 rtx insns
= s390_load_got ();
7870 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
7871 annotate_constant_pool_refs (&PATTERN (insn
));
7876 if (TARGET_TPF_PROFILING
)
7878 /* Generate a BAS instruction to serve as a function
7879 entry intercept to facilitate the use of tracing
7880 algorithms located at the branch target. */
7881 emit_insn (gen_prologue_tpf ());
7883 /* Emit a blockage here so that all code
7884 lies between the profiling mechanisms. */
7885 emit_insn (gen_blockage ());
7889 /* Expand the epilogue into a bunch of separate insns. */
7892 s390_emit_epilogue (bool sibcall
)
7894 rtx frame_pointer
, return_reg
;
7895 int area_bottom
, area_top
, offset
= 0;
7900 if (TARGET_TPF_PROFILING
)
7903 /* Generate a BAS instruction to serve as a function
7904 entry intercept to facilitate the use of tracing
7905 algorithms located at the branch target. */
7907 /* Emit a blockage here so that all code
7908 lies between the profiling mechanisms. */
7909 emit_insn (gen_blockage ());
7911 emit_insn (gen_epilogue_tpf ());
7914 /* Check whether to use frame or stack pointer for restore. */
7916 frame_pointer
= (frame_pointer_needed
7917 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
7919 s390_frame_area (&area_bottom
, &area_top
);
7921 /* Check whether we can access the register save area.
7922 If not, increment the frame pointer as required. */
7924 if (area_top
<= area_bottom
)
7926 /* Nothing to restore. */
7928 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
7929 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
7931 /* Area is in range. */
7932 offset
= cfun_frame_layout
.frame_size
;
7936 rtx insn
, frame_off
;
7938 offset
= area_bottom
< 0 ? -area_bottom
: 0;
7939 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
7941 if (DISP_IN_RANGE (INTVAL (frame_off
)))
7943 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
7944 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
7945 insn
= emit_insn (insn
);
7949 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
7950 frame_off
= force_const_mem (Pmode
, frame_off
);
7952 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
7953 annotate_constant_pool_refs (&PATTERN (insn
));
7957 /* Restore call saved fprs. */
7961 if (cfun_save_high_fprs_p
)
7963 next_offset
= cfun_frame_layout
.f8_offset
;
7964 for (i
= 24; i
< 32; i
++)
7966 if (cfun_fpr_bit_p (i
- 16))
7968 restore_fpr (frame_pointer
,
7969 offset
+ next_offset
, i
);
7978 next_offset
= cfun_frame_layout
.f4_offset
;
7979 for (i
= 18; i
< 20; i
++)
7981 if (cfun_fpr_bit_p (i
- 16))
7983 restore_fpr (frame_pointer
,
7984 offset
+ next_offset
, i
);
7987 else if (!TARGET_PACKED_STACK
)
7993 /* Return register. */
7995 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7997 /* Restore call saved gprs. */
7999 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8004 /* Check for global register and save them
8005 to stack location from where they get restored. */
8007 for (i
= cfun_frame_layout
.first_restore_gpr
;
8008 i
<= cfun_frame_layout
.last_restore_gpr
;
8011 /* These registers are special and need to be
8012 restored in any case. */
8013 if (i
== STACK_POINTER_REGNUM
8014 || i
== RETURN_REGNUM
8016 || (flag_pic
&& i
== (int)PIC_OFFSET_TABLE_REGNUM
))
8021 addr
= plus_constant (frame_pointer
,
8022 offset
+ cfun_frame_layout
.gprs_offset
8023 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8025 addr
= gen_rtx_MEM (Pmode
, addr
);
8026 set_mem_alias_set (addr
, get_frame_alias_set ());
8027 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8033 /* Fetch return address from stack before load multiple,
8034 this will do good for scheduling. */
8036 if (cfun_frame_layout
.save_return_addr_p
8037 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8038 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8040 int return_regnum
= find_unused_clobbered_reg();
8043 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8045 addr
= plus_constant (frame_pointer
,
8046 offset
+ cfun_frame_layout
.gprs_offset
8048 - cfun_frame_layout
.first_save_gpr_slot
)
8050 addr
= gen_rtx_MEM (Pmode
, addr
);
8051 set_mem_alias_set (addr
, get_frame_alias_set ());
8052 emit_move_insn (return_reg
, addr
);
8056 insn
= restore_gprs (frame_pointer
,
8057 offset
+ cfun_frame_layout
.gprs_offset
8058 + (cfun_frame_layout
.first_restore_gpr
8059 - cfun_frame_layout
.first_save_gpr_slot
)
8061 cfun_frame_layout
.first_restore_gpr
,
8062 cfun_frame_layout
.last_restore_gpr
);
8069 /* Return to caller. */
8071 p
= rtvec_alloc (2);
8073 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
8074 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8075 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8080 /* Return the size in bytes of a function argument of
8081 type TYPE and/or mode MODE. At least one of TYPE or
8082 MODE must be specified. */
8085 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8088 return int_size_in_bytes (type
);
8090 /* No type info available for some library calls ... */
8091 if (mode
!= BLKmode
)
8092 return GET_MODE_SIZE (mode
);
8094 /* If we have neither type nor mode, abort */
8098 /* Return true if a function argument of type TYPE and mode MODE
8099 is to be passed in a floating-point register, if available. */
8102 s390_function_arg_float (enum machine_mode mode
, tree type
)
8104 int size
= s390_function_arg_size (mode
, type
);
8108 /* Soft-float changes the ABI: no floating-point registers are used. */
8109 if (TARGET_SOFT_FLOAT
)
8112 /* No type info available for some library calls ... */
8114 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8116 /* The ABI says that record types with a single member are treated
8117 just like that member would be. */
8118 while (TREE_CODE (type
) == RECORD_TYPE
)
8120 tree field
, single
= NULL_TREE
;
8122 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8124 if (TREE_CODE (field
) != FIELD_DECL
)
8127 if (single
== NULL_TREE
)
8128 single
= TREE_TYPE (field
);
8133 if (single
== NULL_TREE
)
8139 return TREE_CODE (type
) == REAL_TYPE
;
8142 /* Return true if a function argument of type TYPE and mode MODE
8143 is to be passed in an integer register, or a pair of integer
8144 registers, if available. */
8147 s390_function_arg_integer (enum machine_mode mode
, tree type
)
8149 int size
= s390_function_arg_size (mode
, type
);
8153 /* No type info available for some library calls ... */
8155 return GET_MODE_CLASS (mode
) == MODE_INT
8156 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8158 /* We accept small integral (and similar) types. */
8159 if (INTEGRAL_TYPE_P (type
)
8160 || POINTER_TYPE_P (type
)
8161 || TREE_CODE (type
) == OFFSET_TYPE
8162 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8165 /* We also accept structs of size 1, 2, 4, 8 that are not
8166 passed in floating-point registers. */
8167 if (AGGREGATE_TYPE_P (type
)
8168 && exact_log2 (size
) >= 0
8169 && !s390_function_arg_float (mode
, type
))
8175 /* Return 1 if a function argument of type TYPE and mode MODE
8176 is to be passed by reference. The ABI specifies that only
8177 structures of size 1, 2, 4, or 8 bytes are passed by value,
8178 all other structures (and complex numbers) are passed by
8182 s390_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
8183 enum machine_mode mode
, const_tree type
,
8184 bool named ATTRIBUTE_UNUSED
)
8186 int size
= s390_function_arg_size (mode
, type
);
8192 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8195 if (TREE_CODE (type
) == COMPLEX_TYPE
8196 || TREE_CODE (type
) == VECTOR_TYPE
)
8203 /* Update the data in CUM to advance over an argument of mode MODE and
8204 data type TYPE. (TYPE is null for libcalls where that information
8205 may not be available.). The boolean NAMED specifies whether the
8206 argument is a named argument (as opposed to an unnamed argument
8207 matching an ellipsis). */
8210 s390_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8211 tree type
, int named ATTRIBUTE_UNUSED
)
8213 if (s390_function_arg_float (mode
, type
))
8217 else if (s390_function_arg_integer (mode
, type
))
8219 int size
= s390_function_arg_size (mode
, type
);
8220 cum
->gprs
+= ((size
+ UNITS_PER_WORD
-1) / UNITS_PER_WORD
);
8226 /* Define where to put the arguments to a function.
8227 Value is zero to push the argument on the stack,
8228 or a hard register in which to store the argument.
8230 MODE is the argument's machine mode.
8231 TYPE is the data type of the argument (as a tree).
8232 This is null for libcalls where that information may
8234 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8235 the preceding args and about the function being called.
8236 NAMED is nonzero if this argument is a named parameter
8237 (otherwise it is an extra parameter matching an ellipsis).
8239 On S/390, we use general purpose registers 2 through 6 to
8240 pass integer, pointer, and certain structure arguments, and
8241 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8242 to pass floating point arguments. All remaining arguments
8243 are pushed to the stack. */
8246 s390_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
8247 int named ATTRIBUTE_UNUSED
)
8249 if (s390_function_arg_float (mode
, type
))
8251 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8254 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8256 else if (s390_function_arg_integer (mode
, type
))
8258 int size
= s390_function_arg_size (mode
, type
);
8259 int n_gprs
= (size
+ UNITS_PER_WORD
-1) / UNITS_PER_WORD
;
8261 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8264 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8267 /* After the real arguments, expand_call calls us once again
8268 with a void_type_node type. Whatever we return here is
8269 passed as operand 2 to the call expanders.
8271 We don't need this feature ... */
8272 else if (type
== void_type_node
)
8278 /* Return true if return values of type TYPE should be returned
8279 in a memory buffer whose address is passed by the caller as
8280 hidden first argument. */
8283 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8285 /* We accept small integral (and similar) types. */
8286 if (INTEGRAL_TYPE_P (type
)
8287 || POINTER_TYPE_P (type
)
8288 || TREE_CODE (type
) == OFFSET_TYPE
8289 || TREE_CODE (type
) == REAL_TYPE
)
8290 return int_size_in_bytes (type
) > 8;
8292 /* Aggregates and similar constructs are always returned
8294 if (AGGREGATE_TYPE_P (type
)
8295 || TREE_CODE (type
) == COMPLEX_TYPE
8296 || TREE_CODE (type
) == VECTOR_TYPE
)
8299 /* ??? We get called on all sorts of random stuff from
8300 aggregate_value_p. We can't abort, but it's not clear
8301 what's safe to return. Pretend it's a struct I guess. */
8305 /* Define where to return a (scalar) value of type TYPE.
8306 If TYPE is null, define where to return a (scalar)
8307 value of mode MODE from a libcall. */
8310 s390_function_value (const_tree type
, enum machine_mode mode
)
8314 int unsignedp
= TYPE_UNSIGNED (type
);
8315 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
, 1);
8318 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8319 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8321 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8322 return gen_rtx_REG (mode
, 16);
8324 return gen_rtx_REG (mode
, 2);
8328 /* Create and return the va_list datatype.
8330 On S/390, va_list is an array type equivalent to
8332 typedef struct __va_list_tag
8336 void *__overflow_arg_area;
8337 void *__reg_save_area;
8340 where __gpr and __fpr hold the number of general purpose
8341 or floating point arguments used up to now, respectively,
8342 __overflow_arg_area points to the stack location of the
8343 next argument passed on the stack, and __reg_save_area
8344 always points to the start of the register area in the
8345 call frame of the current function. The function prologue
8346 saves all registers used for argument passing into this
8347 area if the function uses variable arguments. */
8350 s390_build_builtin_va_list (void)
8352 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8354 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
8357 build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8359 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("__gpr"),
8360 long_integer_type_node
);
8361 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("__fpr"),
8362 long_integer_type_node
);
8363 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("__overflow_arg_area"),
8365 f_sav
= build_decl (FIELD_DECL
, get_identifier ("__reg_save_area"),
8368 va_list_gpr_counter_field
= f_gpr
;
8369 va_list_fpr_counter_field
= f_fpr
;
8371 DECL_FIELD_CONTEXT (f_gpr
) = record
;
8372 DECL_FIELD_CONTEXT (f_fpr
) = record
;
8373 DECL_FIELD_CONTEXT (f_ovf
) = record
;
8374 DECL_FIELD_CONTEXT (f_sav
) = record
;
8376 TREE_CHAIN (record
) = type_decl
;
8377 TYPE_NAME (record
) = type_decl
;
8378 TYPE_FIELDS (record
) = f_gpr
;
8379 TREE_CHAIN (f_gpr
) = f_fpr
;
8380 TREE_CHAIN (f_fpr
) = f_ovf
;
8381 TREE_CHAIN (f_ovf
) = f_sav
;
8383 layout_type (record
);
8385 /* The correct type is an array type of one element. */
8386 return build_array_type (record
, build_index_type (size_zero_node
));
8389 /* Implement va_start by filling the va_list structure VALIST.
8390 STDARG_P is always true, and ignored.
8391 NEXTARG points to the first anonymous stack argument.
8393 The following global variables are used to initialize
8394 the va_list structure:
8397 holds number of gprs and fprs used for named arguments.
8398 crtl->args.arg_offset_rtx:
8399 holds the offset of the first anonymous stack argument
8400 (relative to the virtual arg pointer). */
8403 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
8405 HOST_WIDE_INT n_gpr
, n_fpr
;
8407 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8408 tree gpr
, fpr
, ovf
, sav
, t
;
8410 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8411 f_fpr
= TREE_CHAIN (f_gpr
);
8412 f_ovf
= TREE_CHAIN (f_fpr
);
8413 f_sav
= TREE_CHAIN (f_ovf
);
8415 valist
= build_va_arg_indirect_ref (valist
);
8416 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8417 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8418 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8419 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8421 /* Count number of gp and fp argument registers used. */
8423 n_gpr
= crtl
->args
.info
.gprs
;
8424 n_fpr
= crtl
->args
.info
.fprs
;
8426 if (cfun
->va_list_gpr_size
)
8428 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
8429 build_int_cst (NULL_TREE
, n_gpr
));
8430 TREE_SIDE_EFFECTS (t
) = 1;
8431 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8434 if (cfun
->va_list_fpr_size
)
8436 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
8437 build_int_cst (NULL_TREE
, n_fpr
));
8438 TREE_SIDE_EFFECTS (t
) = 1;
8439 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8442 /* Find the overflow area. */
8443 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8444 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8446 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8448 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
8449 off
= off
< 0 ? 0 : off
;
8450 if (TARGET_DEBUG_ARG
)
8451 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8452 (int)n_gpr
, (int)n_fpr
, off
);
8454 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
, size_int (off
));
8456 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
8457 TREE_SIDE_EFFECTS (t
) = 1;
8458 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8461 /* Find the register save area. */
8462 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8463 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8465 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8466 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
8467 size_int (-RETURN_REGNUM
* UNITS_PER_WORD
));
8469 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
8470 TREE_SIDE_EFFECTS (t
) = 1;
8471 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8475 /* Implement va_arg by updating the va_list structure
8476 VALIST as required to retrieve an argument of type
8477 TYPE, and returning that argument.
8479 Generates code equivalent to:
8481 if (integral value) {
8482 if (size <= 4 && args.gpr < 5 ||
8483 size > 4 && args.gpr < 4 )
8484 ret = args.reg_save_area[args.gpr+8]
8486 ret = *args.overflow_arg_area++;
8487 } else if (float value) {
8489 ret = args.reg_save_area[args.fpr+64]
8491 ret = *args.overflow_arg_area++;
8492 } else if (aggregate value) {
8494 ret = *args.reg_save_area[args.gpr]
8496 ret = **args.overflow_arg_area++;
8500 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
8501 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8503 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8504 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
8505 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
8506 tree lab_false
, lab_over
, addr
;
8508 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8509 f_fpr
= TREE_CHAIN (f_gpr
);
8510 f_ovf
= TREE_CHAIN (f_fpr
);
8511 f_sav
= TREE_CHAIN (f_ovf
);
8513 valist
= build_va_arg_indirect_ref (valist
);
8514 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8515 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8516 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8518 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8519 both appear on a lhs. */
8520 valist
= unshare_expr (valist
);
8521 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8523 size
= int_size_in_bytes (type
);
8525 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
8527 if (TARGET_DEBUG_ARG
)
8529 fprintf (stderr
, "va_arg: aggregate type");
8533 /* Aggregates are passed by reference. */
8538 /* kernel stack layout on 31 bit: It is assumed here that no padding
8539 will be added by s390_frame_info because for va_args always an even
8540 number of gprs has to be saved r15-r2 = 14 regs. */
8541 sav_ofs
= 2 * UNITS_PER_WORD
;
8542 sav_scale
= UNITS_PER_WORD
;
8543 size
= UNITS_PER_WORD
;
8544 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8546 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
8548 if (TARGET_DEBUG_ARG
)
8550 fprintf (stderr
, "va_arg: float type");
8554 /* FP args go in FP registers, if present. */
8558 sav_ofs
= 16 * UNITS_PER_WORD
;
8560 max_reg
= FP_ARG_NUM_REG
- n_reg
;
8564 if (TARGET_DEBUG_ARG
)
8566 fprintf (stderr
, "va_arg: other type");
8570 /* Otherwise into GP registers. */
8573 n_reg
= (size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8575 /* kernel stack layout on 31 bit: It is assumed here that no padding
8576 will be added by s390_frame_info because for va_args always an even
8577 number of gprs has to be saved r15-r2 = 14 regs. */
8578 sav_ofs
= 2 * UNITS_PER_WORD
;
8580 if (size
< UNITS_PER_WORD
)
8581 sav_ofs
+= UNITS_PER_WORD
- size
;
8583 sav_scale
= UNITS_PER_WORD
;
8584 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8587 /* Pull the value out of the saved registers ... */
8589 lab_false
= create_artificial_label ();
8590 lab_over
= create_artificial_label ();
8591 addr
= create_tmp_var (ptr_type_node
, "addr");
8592 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
8594 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
8595 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
8596 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
8597 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
8598 gimplify_and_add (t
, pre_p
);
8600 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
,
8601 size_int (sav_ofs
));
8602 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
8603 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
8604 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, fold_convert (sizetype
, u
));
8606 gimplify_assign (addr
, t
, pre_p
);
8608 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
8610 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
8613 /* ... Otherwise out of the overflow area. */
8616 if (size
< UNITS_PER_WORD
)
8617 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8618 size_int (UNITS_PER_WORD
- size
));
8620 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
8622 gimplify_assign (addr
, t
, pre_p
);
8624 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8626 gimplify_assign (ovf
, t
, pre_p
);
8628 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
8631 /* Increment register save count. */
8633 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
8634 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
8635 gimplify_and_add (u
, pre_p
);
8639 t
= build_pointer_type (build_pointer_type (type
));
8640 addr
= fold_convert (t
, addr
);
8641 addr
= build_va_arg_indirect_ref (addr
);
8645 t
= build_pointer_type (type
);
8646 addr
= fold_convert (t
, addr
);
8649 return build_va_arg_indirect_ref (addr
);
8657 S390_BUILTIN_THREAD_POINTER
,
8658 S390_BUILTIN_SET_THREAD_POINTER
,
8663 static unsigned int const code_for_builtin_64
[S390_BUILTIN_max
] = {
8668 static unsigned int const code_for_builtin_31
[S390_BUILTIN_max
] = {
8674 s390_init_builtins (void)
8678 ftype
= build_function_type (ptr_type_node
, void_list_node
);
8679 add_builtin_function ("__builtin_thread_pointer", ftype
,
8680 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
8683 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
8684 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
8685 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
8689 /* Expand an expression EXP that calls a built-in function,
8690 with result going to TARGET if that's convenient
8691 (and in mode MODE if that's convenient).
8692 SUBTARGET may be used as the target for computing one of EXP's operands.
8693 IGNORE is nonzero if the value is to be ignored. */
8696 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8697 enum machine_mode mode ATTRIBUTE_UNUSED
,
8698 int ignore ATTRIBUTE_UNUSED
)
8702 unsigned int const *code_for_builtin
=
8703 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
8705 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8706 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8707 enum insn_code icode
;
8708 rtx op
[MAX_ARGS
], pat
;
8712 call_expr_arg_iterator iter
;
8714 if (fcode
>= S390_BUILTIN_max
)
8715 internal_error ("bad builtin fcode");
8716 icode
= code_for_builtin
[fcode
];
8718 internal_error ("bad builtin fcode");
8720 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
8723 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
8725 const struct insn_operand_data
*insn_op
;
8727 if (arg
== error_mark_node
)
8729 if (arity
> MAX_ARGS
)
8732 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
8734 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
8736 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
8737 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
8743 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8745 || GET_MODE (target
) != tmode
8746 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8747 target
= gen_reg_rtx (tmode
);
8753 pat
= GEN_FCN (icode
) (target
);
8757 pat
= GEN_FCN (icode
) (target
, op
[0]);
8759 pat
= GEN_FCN (icode
) (op
[0]);
8762 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
8778 /* Output assembly code for the trampoline template to
8781 On S/390, we use gpr 1 internally in the trampoline code;
8782 gpr 0 is used to hold the static chain. */
8785 s390_trampoline_template (FILE *file
)
8788 op
[0] = gen_rtx_REG (Pmode
, 0);
8789 op
[1] = gen_rtx_REG (Pmode
, 1);
8793 output_asm_insn ("basr\t%1,0", op
);
8794 output_asm_insn ("lmg\t%0,%1,14(%1)", op
);
8795 output_asm_insn ("br\t%1", op
);
8796 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
8800 output_asm_insn ("basr\t%1,0", op
);
8801 output_asm_insn ("lm\t%0,%1,6(%1)", op
);
8802 output_asm_insn ("br\t%1", op
);
8803 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
8807 /* Emit RTL insns to initialize the variable parts of a trampoline.
8808 FNADDR is an RTX for the address of the function's pure code.
8809 CXT is an RTX for the static chain value for the function. */
8812 s390_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
8814 emit_move_insn (gen_rtx_MEM (Pmode
,
8815 memory_address (Pmode
,
8816 plus_constant (addr
, (TARGET_64BIT
? 16 : 8)))), cxt
);
8817 emit_move_insn (gen_rtx_MEM (Pmode
,
8818 memory_address (Pmode
,
8819 plus_constant (addr
, (TARGET_64BIT
? 24 : 12)))), fnaddr
);
8822 /* Output assembler code to FILE to increment profiler label # LABELNO
8823 for profiling a function entry. */
8826 s390_function_profiler (FILE *file
, int labelno
)
8831 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
8833 fprintf (file
, "# function profiler \n");
8835 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8836 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
8837 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_WORD
));
8839 op
[2] = gen_rtx_REG (Pmode
, 1);
8840 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
8841 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
8843 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
8846 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
8847 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
8852 output_asm_insn ("stg\t%0,%1", op
);
8853 output_asm_insn ("larl\t%2,%3", op
);
8854 output_asm_insn ("brasl\t%0,%4", op
);
8855 output_asm_insn ("lg\t%0,%1", op
);
8859 op
[6] = gen_label_rtx ();
8861 output_asm_insn ("st\t%0,%1", op
);
8862 output_asm_insn ("bras\t%2,%l6", op
);
8863 output_asm_insn (".long\t%4", op
);
8864 output_asm_insn (".long\t%3", op
);
8865 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
8866 output_asm_insn ("l\t%0,0(%2)", op
);
8867 output_asm_insn ("l\t%2,4(%2)", op
);
8868 output_asm_insn ("basr\t%0,%0", op
);
8869 output_asm_insn ("l\t%0,%1", op
);
8873 op
[5] = gen_label_rtx ();
8874 op
[6] = gen_label_rtx ();
8876 output_asm_insn ("st\t%0,%1", op
);
8877 output_asm_insn ("bras\t%2,%l6", op
);
8878 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
8879 output_asm_insn (".long\t%4-%l5", op
);
8880 output_asm_insn (".long\t%3-%l5", op
);
8881 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
8882 output_asm_insn ("lr\t%0,%2", op
);
8883 output_asm_insn ("a\t%0,0(%2)", op
);
8884 output_asm_insn ("a\t%2,4(%2)", op
);
8885 output_asm_insn ("basr\t%0,%0", op
);
8886 output_asm_insn ("l\t%0,%1", op
);
8890 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8891 into its SYMBOL_REF_FLAGS. */
8894 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
8896 default_encode_section_info (decl
, rtl
, first
);
8898 if (TREE_CODE (decl
) == VAR_DECL
)
8900 /* If a variable has a forced alignment to < 2 bytes, mark it
8901 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
8903 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
8904 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
8905 if (!DECL_SIZE (decl
)
8906 || !DECL_ALIGN (decl
)
8907 || !host_integerp (DECL_SIZE (decl
), 0)
8908 || (DECL_ALIGN (decl
) <= 64
8909 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
8910 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
8913 /* Literal pool references don't have a decl so they are handled
8914 differently here. We rely on the information in the MEM_ALIGN
8915 entry to decide upon natural alignment. */
8917 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
8918 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
8919 && (MEM_ALIGN (rtl
) == 0
8920 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
8921 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
8924 /* Output thunk to FILE that implements a C++ virtual function call (with
8925 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8926 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8927 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8928 relative to the resulting this pointer. */
8931 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
8932 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8938 /* Operand 0 is the target function. */
8939 op
[0] = XEXP (DECL_RTL (function
), 0);
8940 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
8943 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
8944 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
8945 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
8948 /* Operand 1 is the 'this' pointer. */
8949 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8950 op
[1] = gen_rtx_REG (Pmode
, 3);
8952 op
[1] = gen_rtx_REG (Pmode
, 2);
8954 /* Operand 2 is the delta. */
8955 op
[2] = GEN_INT (delta
);
8957 /* Operand 3 is the vcall_offset. */
8958 op
[3] = GEN_INT (vcall_offset
);
8960 /* Operand 4 is the temporary register. */
8961 op
[4] = gen_rtx_REG (Pmode
, 1);
8963 /* Operands 5 to 8 can be used as labels. */
8969 /* Operand 9 can be used for temporary register. */
8972 /* Generate code. */
8975 /* Setup literal pool pointer if required. */
8976 if ((!DISP_IN_RANGE (delta
)
8977 && !CONST_OK_FOR_K (delta
)
8978 && !CONST_OK_FOR_Os (delta
))
8979 || (!DISP_IN_RANGE (vcall_offset
)
8980 && !CONST_OK_FOR_K (vcall_offset
)
8981 && !CONST_OK_FOR_Os (vcall_offset
)))
8983 op
[5] = gen_label_rtx ();
8984 output_asm_insn ("larl\t%4,%5", op
);
8987 /* Add DELTA to this pointer. */
8990 if (CONST_OK_FOR_J (delta
))
8991 output_asm_insn ("la\t%1,%2(%1)", op
);
8992 else if (DISP_IN_RANGE (delta
))
8993 output_asm_insn ("lay\t%1,%2(%1)", op
);
8994 else if (CONST_OK_FOR_K (delta
))
8995 output_asm_insn ("aghi\t%1,%2", op
);
8996 else if (CONST_OK_FOR_Os (delta
))
8997 output_asm_insn ("agfi\t%1,%2", op
);
9000 op
[6] = gen_label_rtx ();
9001 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9005 /* Perform vcall adjustment. */
9008 if (DISP_IN_RANGE (vcall_offset
))
9010 output_asm_insn ("lg\t%4,0(%1)", op
);
9011 output_asm_insn ("ag\t%1,%3(%4)", op
);
9013 else if (CONST_OK_FOR_K (vcall_offset
))
9015 output_asm_insn ("lghi\t%4,%3", op
);
9016 output_asm_insn ("ag\t%4,0(%1)", op
);
9017 output_asm_insn ("ag\t%1,0(%4)", op
);
9019 else if (CONST_OK_FOR_Os (vcall_offset
))
9021 output_asm_insn ("lgfi\t%4,%3", op
);
9022 output_asm_insn ("ag\t%4,0(%1)", op
);
9023 output_asm_insn ("ag\t%1,0(%4)", op
);
9027 op
[7] = gen_label_rtx ();
9028 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9029 output_asm_insn ("ag\t%4,0(%1)", op
);
9030 output_asm_insn ("ag\t%1,0(%4)", op
);
9034 /* Jump to target. */
9035 output_asm_insn ("jg\t%0", op
);
9037 /* Output literal pool if required. */
9040 output_asm_insn (".align\t4", op
);
9041 targetm
.asm_out
.internal_label (file
, "L",
9042 CODE_LABEL_NUMBER (op
[5]));
9046 targetm
.asm_out
.internal_label (file
, "L",
9047 CODE_LABEL_NUMBER (op
[6]));
9048 output_asm_insn (".long\t%2", op
);
9052 targetm
.asm_out
.internal_label (file
, "L",
9053 CODE_LABEL_NUMBER (op
[7]));
9054 output_asm_insn (".long\t%3", op
);
9059 /* Setup base pointer if required. */
9061 || (!DISP_IN_RANGE (delta
)
9062 && !CONST_OK_FOR_K (delta
)
9063 && !CONST_OK_FOR_Os (delta
))
9064 || (!DISP_IN_RANGE (delta
)
9065 && !CONST_OK_FOR_K (vcall_offset
)
9066 && !CONST_OK_FOR_Os (vcall_offset
)))
9068 op
[5] = gen_label_rtx ();
9069 output_asm_insn ("basr\t%4,0", op
);
9070 targetm
.asm_out
.internal_label (file
, "L",
9071 CODE_LABEL_NUMBER (op
[5]));
9074 /* Add DELTA to this pointer. */
9077 if (CONST_OK_FOR_J (delta
))
9078 output_asm_insn ("la\t%1,%2(%1)", op
);
9079 else if (DISP_IN_RANGE (delta
))
9080 output_asm_insn ("lay\t%1,%2(%1)", op
);
9081 else if (CONST_OK_FOR_K (delta
))
9082 output_asm_insn ("ahi\t%1,%2", op
);
9083 else if (CONST_OK_FOR_Os (delta
))
9084 output_asm_insn ("afi\t%1,%2", op
);
9087 op
[6] = gen_label_rtx ();
9088 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9092 /* Perform vcall adjustment. */
9095 if (CONST_OK_FOR_J (vcall_offset
))
9097 output_asm_insn ("l\t%4,0(%1)", op
);
9098 output_asm_insn ("a\t%1,%3(%4)", op
);
9100 else if (DISP_IN_RANGE (vcall_offset
))
9102 output_asm_insn ("l\t%4,0(%1)", op
);
9103 output_asm_insn ("ay\t%1,%3(%4)", op
);
9105 else if (CONST_OK_FOR_K (vcall_offset
))
9107 output_asm_insn ("lhi\t%4,%3", op
);
9108 output_asm_insn ("a\t%4,0(%1)", op
);
9109 output_asm_insn ("a\t%1,0(%4)", op
);
9111 else if (CONST_OK_FOR_Os (vcall_offset
))
9113 output_asm_insn ("iilf\t%4,%3", op
);
9114 output_asm_insn ("a\t%4,0(%1)", op
);
9115 output_asm_insn ("a\t%1,0(%4)", op
);
9119 op
[7] = gen_label_rtx ();
9120 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9121 output_asm_insn ("a\t%4,0(%1)", op
);
9122 output_asm_insn ("a\t%1,0(%4)", op
);
9125 /* We had to clobber the base pointer register.
9126 Re-setup the base pointer (with a different base). */
9127 op
[5] = gen_label_rtx ();
9128 output_asm_insn ("basr\t%4,0", op
);
9129 targetm
.asm_out
.internal_label (file
, "L",
9130 CODE_LABEL_NUMBER (op
[5]));
9133 /* Jump to target. */
9134 op
[8] = gen_label_rtx ();
9137 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9139 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9140 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9141 else if (flag_pic
== 1)
9143 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9144 output_asm_insn ("l\t%4,%0(%4)", op
);
9146 else if (flag_pic
== 2)
9148 op
[9] = gen_rtx_REG (Pmode
, 0);
9149 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9150 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9151 output_asm_insn ("ar\t%4,%9", op
);
9152 output_asm_insn ("l\t%4,0(%4)", op
);
9155 output_asm_insn ("br\t%4", op
);
9157 /* Output literal pool. */
9158 output_asm_insn (".align\t4", op
);
9160 if (nonlocal
&& flag_pic
== 2)
9161 output_asm_insn (".long\t%0", op
);
9164 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9165 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9168 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9170 output_asm_insn (".long\t%0", op
);
9172 output_asm_insn (".long\t%0-%5", op
);
9176 targetm
.asm_out
.internal_label (file
, "L",
9177 CODE_LABEL_NUMBER (op
[6]));
9178 output_asm_insn (".long\t%2", op
);
9182 targetm
.asm_out
.internal_label (file
, "L",
9183 CODE_LABEL_NUMBER (op
[7]));
9184 output_asm_insn (".long\t%3", op
);
9190 s390_valid_pointer_mode (enum machine_mode mode
)
9192 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9195 /* Checks whether the given CALL_EXPR would use a caller
9196 saved register. This is used to decide whether sibling call
9197 optimization could be performed on the respective function
9201 s390_call_saved_register_used (tree call_expr
)
9203 CUMULATIVE_ARGS cum
;
9205 enum machine_mode mode
;
9210 INIT_CUMULATIVE_ARGS (cum
, NULL
, NULL
, 0, 0);
9212 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9214 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9215 gcc_assert (parameter
);
9217 /* For an undeclared variable passed as parameter we will get
9218 an ERROR_MARK node here. */
9219 if (TREE_CODE (parameter
) == ERROR_MARK
)
9222 type
= TREE_TYPE (parameter
);
9225 mode
= TYPE_MODE (type
);
9228 if (pass_by_reference (&cum
, mode
, type
, true))
9231 type
= build_pointer_type (type
);
9234 parm_rtx
= s390_function_arg (&cum
, mode
, type
, 0);
9236 s390_function_arg_advance (&cum
, mode
, type
, 0);
9238 if (parm_rtx
&& REG_P (parm_rtx
))
9241 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9243 if (! call_used_regs
[reg
+ REGNO (parm_rtx
)])
9250 /* Return true if the given call expression can be
9251 turned into a sibling call.
9252 DECL holds the declaration of the function to be called whereas
9253 EXP is the call expression itself. */
9256 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9258 /* The TPF epilogue uses register 1. */
9259 if (TARGET_TPF_PROFILING
)
9262 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9263 which would have to be restored before the sibcall. */
9264 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9267 /* Register 6 on s390 is available as an argument register but unfortunately
9268 "caller saved". This makes functions needing this register for arguments
9269 not suitable for sibcalls. */
9270 return !s390_call_saved_register_used (exp
);
9273 /* Return the fixed registers used for condition codes. */
9276 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9279 *p2
= INVALID_REGNUM
;
9284 /* This function is used by the call expanders of the machine description.
9285 It emits the call insn itself together with the necessary operations
9286 to adjust the target address and returns the emitted insn.
9287 ADDR_LOCATION is the target address rtx
9288 TLS_CALL the location of the thread-local symbol
9289 RESULT_REG the register where the result of the call should be stored
9290 RETADDR_REG the register where the return address should be stored
9291 If this parameter is NULL_RTX the call is considered
9292 to be a sibling call. */
9295 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9298 bool plt_call
= false;
9304 /* Direct function calls need special treatment. */
9305 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9307 /* When calling a global routine in PIC mode, we must
9308 replace the symbol itself with the PLT stub. */
9309 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9311 addr_location
= gen_rtx_UNSPEC (Pmode
,
9312 gen_rtvec (1, addr_location
),
9314 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9318 /* Unless we can use the bras(l) insn, force the
9319 routine address into a register. */
9320 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9323 addr_location
= legitimize_pic_address (addr_location
, 0);
9325 addr_location
= force_reg (Pmode
, addr_location
);
9329 /* If it is already an indirect call or the code above moved the
9330 SYMBOL_REF to somewhere else make sure the address can be found in
9332 if (retaddr_reg
== NULL_RTX
9333 && GET_CODE (addr_location
) != SYMBOL_REF
9336 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9337 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9340 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9341 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9343 if (result_reg
!= NULL_RTX
)
9344 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9346 if (retaddr_reg
!= NULL_RTX
)
9348 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9350 if (tls_call
!= NULL_RTX
)
9351 vec
= gen_rtvec (3, call
, clobber
,
9352 gen_rtx_USE (VOIDmode
, tls_call
));
9354 vec
= gen_rtvec (2, call
, clobber
);
9356 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9359 insn
= emit_call_insn (call
);
9361 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9362 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9364 /* s390_function_ok_for_sibcall should
9365 have denied sibcalls in this case. */
9366 gcc_assert (retaddr_reg
!= NULL_RTX
);
9368 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
9373 /* Implement CONDITIONAL_REGISTER_USAGE. */
9376 s390_conditional_register_usage (void)
9382 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9383 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9385 if (TARGET_CPU_ZARCH
)
9387 fixed_regs
[BASE_REGNUM
] = 0;
9388 call_used_regs
[BASE_REGNUM
] = 0;
9389 fixed_regs
[RETURN_REGNUM
] = 0;
9390 call_used_regs
[RETURN_REGNUM
] = 0;
9394 for (i
= 24; i
< 32; i
++)
9395 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9399 for (i
= 18; i
< 20; i
++)
9400 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9403 if (TARGET_SOFT_FLOAT
)
9405 for (i
= 16; i
< 32; i
++)
9406 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9410 /* Corresponding function to eh_return expander. */
9412 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9414 s390_emit_tpf_eh_return (rtx target
)
9418 if (!s390_tpf_eh_return_symbol
)
9419 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
9421 reg
= gen_rtx_REG (Pmode
, 2);
9423 emit_move_insn (reg
, target
);
9424 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
9425 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
9426 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
9428 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
9431 /* Rework the prologue/epilogue to avoid saving/restoring
9432 registers unnecessarily. */
9435 s390_optimize_prologue (void)
9437 rtx insn
, new_insn
, next_insn
;
9439 /* Do a final recompute of the frame-related data. */
9441 s390_update_frame_layout ();
9443 /* If all special registers are in fact used, there's nothing we
9444 can do, so no point in walking the insn list. */
9446 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
9447 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
9448 && (TARGET_CPU_ZARCH
9449 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
9450 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
9453 /* Search for prologue/epilogue insns and replace them. */
9455 for (insn
= get_insns (); insn
; insn
= next_insn
)
9457 int first
, last
, off
;
9458 rtx set
, base
, offset
;
9460 next_insn
= NEXT_INSN (insn
);
9462 if (GET_CODE (insn
) != INSN
)
9465 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9466 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
9468 set
= XVECEXP (PATTERN (insn
), 0, 0);
9469 first
= REGNO (SET_SRC (set
));
9470 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9471 offset
= const0_rtx
;
9472 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9473 off
= INTVAL (offset
);
9475 if (GET_CODE (base
) != REG
|| off
< 0)
9477 if (cfun_frame_layout
.first_save_gpr
!= -1
9478 && (cfun_frame_layout
.first_save_gpr
< first
9479 || cfun_frame_layout
.last_save_gpr
> last
))
9481 if (REGNO (base
) != STACK_POINTER_REGNUM
9482 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9484 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9487 if (cfun_frame_layout
.first_save_gpr
!= -1)
9489 new_insn
= save_gprs (base
,
9490 off
+ (cfun_frame_layout
.first_save_gpr
9491 - first
) * UNITS_PER_WORD
,
9492 cfun_frame_layout
.first_save_gpr
,
9493 cfun_frame_layout
.last_save_gpr
);
9494 new_insn
= emit_insn_before (new_insn
, insn
);
9495 INSN_ADDRESSES_NEW (new_insn
, -1);
9502 if (cfun_frame_layout
.first_save_gpr
== -1
9503 && GET_CODE (PATTERN (insn
)) == SET
9504 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
9505 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
9506 || (!TARGET_CPU_ZARCH
9507 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
9508 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
9510 set
= PATTERN (insn
);
9511 first
= REGNO (SET_SRC (set
));
9512 offset
= const0_rtx
;
9513 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9514 off
= INTVAL (offset
);
9516 if (GET_CODE (base
) != REG
|| off
< 0)
9518 if (REGNO (base
) != STACK_POINTER_REGNUM
9519 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9526 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9527 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
9529 set
= XVECEXP (PATTERN (insn
), 0, 0);
9530 first
= REGNO (SET_DEST (set
));
9531 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9532 offset
= const0_rtx
;
9533 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9534 off
= INTVAL (offset
);
9536 if (GET_CODE (base
) != REG
|| off
< 0)
9538 if (cfun_frame_layout
.first_restore_gpr
!= -1
9539 && (cfun_frame_layout
.first_restore_gpr
< first
9540 || cfun_frame_layout
.last_restore_gpr
> last
))
9542 if (REGNO (base
) != STACK_POINTER_REGNUM
9543 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9545 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9548 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9550 new_insn
= restore_gprs (base
,
9551 off
+ (cfun_frame_layout
.first_restore_gpr
9552 - first
) * UNITS_PER_WORD
,
9553 cfun_frame_layout
.first_restore_gpr
,
9554 cfun_frame_layout
.last_restore_gpr
);
9555 new_insn
= emit_insn_before (new_insn
, insn
);
9556 INSN_ADDRESSES_NEW (new_insn
, -1);
9563 if (cfun_frame_layout
.first_restore_gpr
== -1
9564 && GET_CODE (PATTERN (insn
)) == SET
9565 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
9566 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
9567 || (!TARGET_CPU_ZARCH
9568 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
9569 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
9571 set
= PATTERN (insn
);
9572 first
= REGNO (SET_DEST (set
));
9573 offset
= const0_rtx
;
9574 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9575 off
= INTVAL (offset
);
9577 if (GET_CODE (base
) != REG
|| off
< 0)
9579 if (REGNO (base
) != STACK_POINTER_REGNUM
9580 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9589 /* Returns 1 if INSN reads the value of REG for purposes not related
9590 to addressing of memory, and 0 otherwise. */
9592 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
9594 return reg_referenced_p (reg
, PATTERN (insn
))
9595 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
9598 /* Starting from INSN find_cond_jump looks downwards in the insn
9599 stream for a single jump insn which is the last user of the
9600 condition code set in INSN. */
9602 find_cond_jump (rtx insn
)
9604 for (; insn
; insn
= NEXT_INSN (insn
))
9613 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
9618 /* This will be triggered by a return. */
9619 if (GET_CODE (PATTERN (insn
)) != SET
)
9622 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
9623 ite
= SET_SRC (PATTERN (insn
));
9625 if (GET_CODE (ite
) != IF_THEN_ELSE
)
9628 cc
= XEXP (XEXP (ite
, 0), 0);
9629 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
9632 if (find_reg_note (insn
, REG_DEAD
, cc
))
9640 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9641 the semantics does not change. If NULL_RTX is passed as COND the
9642 function tries to find the conditional jump starting with INSN. */
9644 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
9648 if (cond
== NULL_RTX
)
9650 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
9651 jump
= jump
? single_set (jump
) : NULL_RTX
;
9653 if (jump
== NULL_RTX
)
9656 cond
= XEXP (XEXP (jump
, 1), 0);
9661 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
9664 /* On z10, instructions of the compare-and-branch family have the
9665 property to access the register occurring as second operand with
9666 its bits complemented. If such a compare is grouped with a second
9667 instruction that accesses the same register non-complemented, and
9668 if that register's value is delivered via a bypass, then the
9669 pipeline recycles, thereby causing significant performance decline.
9670 This function locates such situations and exchanges the two
9671 operands of the compare. */
9673 s390_z10_optimize_cmp (void)
9675 rtx insn
, prev_insn
, next_insn
;
9678 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9680 rtx cond
, *op0
, *op1
;
9682 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
9685 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
9687 /* Handle compare and branch and branch on count
9689 rtx pattern
= single_set (insn
);
9692 || SET_DEST (pattern
) != pc_rtx
9693 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
9696 cond
= XEXP (SET_SRC (pattern
), 0);
9697 op0
= &XEXP (cond
, 0);
9698 op1
= &XEXP (cond
, 1);
9700 else if (GET_CODE (PATTERN (insn
)) == SET
)
9704 /* Handle normal compare instructions. */
9705 src
= SET_SRC (PATTERN (insn
));
9706 dest
= SET_DEST (PATTERN (insn
));
9709 || !CC_REGNO_P (REGNO (dest
))
9710 || GET_CODE (src
) != COMPARE
)
9713 /* s390_swap_cmp will try to find the conditional
9714 jump when passing NULL_RTX as condition. */
9716 op0
= &XEXP (src
, 0);
9717 op1
= &XEXP (src
, 1);
9722 if (!REG_P (*op0
) || !REG_P (*op1
))
9725 /* Swap the COMPARE arguments and its mask if there is a
9726 conflicting access in the previous insn. */
9727 prev_insn
= PREV_INSN (insn
);
9728 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
9729 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
9730 s390_swap_cmp (cond
, op0
, op1
, insn
);
9732 /* Check if there is a conflict with the next insn. If there
9733 was no conflict with the previous insn, then swap the
9734 COMPARE arguments and its mask. If we already swapped
9735 the operands, or if swapping them would cause a conflict
9736 with the previous insn, issue a NOP after the COMPARE in
9737 order to separate the two instuctions. */
9738 next_insn
= NEXT_INSN (insn
);
9739 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
9740 && s390_non_addr_reg_read_p (*op1
, next_insn
))
9742 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
9743 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
9745 if (REGNO (*op1
) == 0)
9746 emit_insn_after (gen_nop1 (), insn
);
9748 emit_insn_after (gen_nop (), insn
);
9752 s390_swap_cmp (cond
, op0
, op1
, insn
);
9756 /* Adjust branches if we added new instructions. */
9758 shorten_branches (get_insns ());
9762 /* Perform machine-dependent processing. */
9767 bool pool_overflow
= false;
9769 /* Make sure all splits have been performed; splits after
9770 machine_dependent_reorg might confuse insn length counts. */
9771 split_all_insns_noflow ();
9773 /* Install the main literal pool and the associated base
9774 register load insns.
9776 In addition, there are two problematic situations we need
9779 - the literal pool might be > 4096 bytes in size, so that
9780 some of its elements cannot be directly accessed
9782 - a branch target might be > 64K away from the branch, so that
9783 it is not possible to use a PC-relative instruction.
9785 To fix those, we split the single literal pool into multiple
9786 pool chunks, reloading the pool base register at various
9787 points throughout the function to ensure it always points to
9788 the pool chunk the following code expects, and / or replace
9789 PC-relative branches by absolute branches.
9791 However, the two problems are interdependent: splitting the
9792 literal pool can move a branch further away from its target,
9793 causing the 64K limit to overflow, and on the other hand,
9794 replacing a PC-relative branch by an absolute branch means
9795 we need to put the branch target address into the literal
9796 pool, possibly causing it to overflow.
9798 So, we loop trying to fix up both problems until we manage
9799 to satisfy both conditions at the same time. Note that the
9800 loop is guaranteed to terminate as every pass of the loop
9801 strictly decreases the total number of PC-relative branches
9802 in the function. (This is not completely true as there
9803 might be branch-over-pool insns introduced by chunkify_start.
9804 Those never need to be split however.) */
9808 struct constant_pool
*pool
= NULL
;
9810 /* Collect the literal pool. */
9813 pool
= s390_mainpool_start ();
9815 pool_overflow
= true;
9818 /* If literal pool overflowed, start to chunkify it. */
9820 pool
= s390_chunkify_start ();
9822 /* Split out-of-range branches. If this has created new
9823 literal pool entries, cancel current chunk list and
9824 recompute it. zSeries machines have large branch
9825 instructions, so we never need to split a branch. */
9826 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
9829 s390_chunkify_cancel (pool
);
9831 s390_mainpool_cancel (pool
);
9836 /* If we made it up to here, both conditions are satisfied.
9837 Finish up literal pool related changes. */
9839 s390_chunkify_finish (pool
);
9841 s390_mainpool_finish (pool
);
9843 /* We're done splitting branches. */
9844 cfun
->machine
->split_branches_pending_p
= false;
9848 /* Generate out-of-pool execute target insns. */
9849 if (TARGET_CPU_ZARCH
)
9851 rtx insn
, label
, target
;
9853 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9855 label
= s390_execute_label (insn
);
9859 gcc_assert (label
!= const0_rtx
);
9861 target
= emit_label (XEXP (label
, 0));
9862 INSN_ADDRESSES_NEW (target
, -1);
9864 target
= emit_insn (s390_execute_target (insn
));
9865 INSN_ADDRESSES_NEW (target
, -1);
9869 /* Try to optimize prologue and epilogue further. */
9870 s390_optimize_prologue ();
9872 /* Eliminate z10-specific pipeline recycles related to some compare
9874 if (s390_tune
== PROCESSOR_2097_Z10
)
9875 s390_z10_optimize_cmp ();
9879 /* Initialize GCC target structure. */
9881 #undef TARGET_ASM_ALIGNED_HI_OP
9882 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9883 #undef TARGET_ASM_ALIGNED_DI_OP
9884 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9885 #undef TARGET_ASM_INTEGER
9886 #define TARGET_ASM_INTEGER s390_assemble_integer
9888 #undef TARGET_ASM_OPEN_PAREN
9889 #define TARGET_ASM_OPEN_PAREN ""
9891 #undef TARGET_ASM_CLOSE_PAREN
9892 #define TARGET_ASM_CLOSE_PAREN ""
9894 #undef TARGET_DEFAULT_TARGET_FLAGS
9895 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9896 #undef TARGET_HANDLE_OPTION
9897 #define TARGET_HANDLE_OPTION s390_handle_option
9899 #undef TARGET_ENCODE_SECTION_INFO
9900 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9903 #undef TARGET_HAVE_TLS
9904 #define TARGET_HAVE_TLS true
9906 #undef TARGET_CANNOT_FORCE_CONST_MEM
9907 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9909 #undef TARGET_DELEGITIMIZE_ADDRESS
9910 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9912 #undef TARGET_RETURN_IN_MEMORY
9913 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9915 #undef TARGET_INIT_BUILTINS
9916 #define TARGET_INIT_BUILTINS s390_init_builtins
9917 #undef TARGET_EXPAND_BUILTIN
9918 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9920 #undef TARGET_ASM_OUTPUT_MI_THUNK
9921 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9922 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9923 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
9925 #undef TARGET_SCHED_ADJUST_PRIORITY
9926 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9927 #undef TARGET_SCHED_ISSUE_RATE
9928 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9929 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9930 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9932 #undef TARGET_CANNOT_COPY_INSN_P
9933 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9934 #undef TARGET_RTX_COSTS
9935 #define TARGET_RTX_COSTS s390_rtx_costs
9936 #undef TARGET_ADDRESS_COST
9937 #define TARGET_ADDRESS_COST s390_address_cost
9939 #undef TARGET_MACHINE_DEPENDENT_REORG
9940 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9942 #undef TARGET_VALID_POINTER_MODE
9943 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9945 #undef TARGET_BUILD_BUILTIN_VA_LIST
9946 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9947 #undef TARGET_EXPAND_BUILTIN_VA_START
9948 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
9949 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9950 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9952 #undef TARGET_PROMOTE_FUNCTION_ARGS
9953 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
9954 #undef TARGET_PROMOTE_FUNCTION_RETURN
9955 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
9956 #undef TARGET_PASS_BY_REFERENCE
9957 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9959 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9960 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9962 #undef TARGET_FIXED_CONDITION_CODE_REGS
9963 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9965 #undef TARGET_CC_MODES_COMPATIBLE
9966 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9968 #undef TARGET_INVALID_WITHIN_DOLOOP
9969 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
9972 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9973 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9976 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9977 #undef TARGET_MANGLE_TYPE
9978 #define TARGET_MANGLE_TYPE s390_mangle_type
9981 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9982 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
9984 #undef TARGET_SECONDARY_RELOAD
9985 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
9987 #undef TARGET_LIBGCC_CMP_RETURN_MODE
9988 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
9990 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
9991 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
9993 struct gcc_target targetm
= TARGET_INITIALIZER
;
9995 #include "gt-s390.h"