| blob | e9f961d41faa4b82b8e5ebc0207a80b390e41067 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2021 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
80 /* This file should be included last. */
83 /* Defined for convenience. */
84 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
86 /* Information about a legitimate vector immediate operand. */
87 struct simd_immediate_info
88 {
100 /* The mode of the elements. */
101 scalar_mode elt_mode;
103 /* The instruction to use to move the immediate into a vector. */
104 insn_type insn;
106 union
107 {
108 /* For MOV and MVN. */
109 struct
110 {
111 /* The value of each element. */
112 rtx value;
114 /* The kind of shift modifier to use, and the number of bits to shift.
115 This is (LSL, 0) if no shift is needed. */
116 modifier_type modifier;
120 /* For INDEX. */
121 struct
122 {
123 /* The value of the first element and the step to be added for each
124 subsequent element. */
128 /* For PTRUE. */
129 aarch64_svpattern pattern;
131 };
133 /* Construct a floating-point immediate in which each element has mode
134 ELT_MODE_IN and value VALUE_IN. */
135 inline simd_immediate_info
138 {
142 }
144 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
145 and value VALUE_IN. The other parameters are as for the structure
146 fields. */
147 inline simd_immediate_info
153 {
157 }
159 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
160 and where element I is equal to BASE_IN + I * STEP_IN. */
161 inline simd_immediate_info
164 {
167 }
169 /* Construct a predicate that controls elements of mode ELT_MODE_IN
170 and has PTRUE pattern PATTERN_IN. */
171 inline simd_immediate_info
173 aarch64_svpattern pattern_in)
175 {
177 }
181 /* Describes types that map to Pure Scalable Types (PSTs) in the AAPCS64. */
182 class pure_scalable_type_info
183 {
185 /* Represents the result of analyzing a type. All values are nonzero,
186 in the possibly forlorn hope that accidental conversions to bool
187 trigger a warning. */
188 enum analysis_result
189 {
190 /* The type does not have an ABI identity; i.e. it doesn't contain
191 at least one object whose type is a Fundamental Data Type. */
194 /* The type is definitely a Pure Scalable Type. */
195 IS_PST,
197 /* The type is definitely not a Pure Scalable Type. */
198 ISNT_PST,
200 /* It doesn't matter for PCS purposes whether the type is a Pure
201 Scalable Type or not, since the type will be handled the same
202 way regardless.
204 Specifically, this means that if the type is a Pure Scalable Type,
205 there aren't enough argument registers to hold it, and so it will
206 need to be passed or returned in memory. If the type isn't a
207 Pure Scalable Type, it's too big to be passed or returned in core
208 or SIMD&FP registers, and so again will need to go in memory. */
209 DOESNT_MATTER
210 };
212 /* Aggregates of 17 bytes or more are normally passed and returned
213 in memory, so aggregates of that size can safely be analyzed as
214 DOESNT_MATTER. We need to be able to collect enough pieces to
215 represent a PST that is smaller than that. Since predicates are
216 2 bytes in size for -msve-vector-bits=128, that means we need to be
217 able to store at least 8 pieces.
219 We also need to be able to store enough pieces to represent
220 a single vector in each vector argument register and a single
221 predicate in each predicate argument register. This means that
222 we need at least 12 pieces. */
226 /* Describes one piece of a PST. Each piece is one of:
228 - a single Scalable Vector Type (SVT)
229 - a single Scalable Predicate Type (SPT)
230 - a PST containing 2, 3 or 4 SVTs, with no padding
232 It either represents a single built-in type or a PST formed from
233 multiple homogeneous built-in types. */
234 struct piece
235 {
238 /* The number of vector and predicate registers that the piece
239 occupies. One of the two is always zero. */
243 /* The mode of the registers described above. */
244 machine_mode mode;
246 /* If this piece is formed from multiple homogeneous built-in types,
247 this is the mode of the built-in types, otherwise it is MODE. */
248 machine_mode orig_mode;
250 /* The offset in bytes of the piece from the start of the type. */
251 poly_uint64_pod offset;
252 };
254 /* Divides types analyzed as IS_PST into individual pieces. The pieces
255 are in memory order. */
270 };
271 }
273 /* The current code model. */
276 /* The number of 64-bit elements in an SVE vector. */
277 poly_uint16 aarch64_sve_vg;
279 #ifdef HAVE_AS_TLS
280 #undef TARGET_HAVE_TLS
281 #define TARGET_HAVE_TLS 1
282 #endif
287 const_tree,
296 const_tree type,
301 aarch64_addr_query_type);
304 /* Major revision number of the ARM Architecture implemented by the target. */
307 /* The processor for which instructions should be scheduled. */
310 /* Mask to specify which instruction scheduling options should be used. */
313 /* Global flag for PC relative loads. */
316 /* Global flag for whether frame pointer is enabled. */
319 #define BRANCH_PROTECT_STR_MAX 255
322 static enum aarch64_parse_opt_result
325 /* Support for command line parsing of boolean flags in the tuning
326 structures. */
327 struct aarch64_flag_desc
328 {
331 };
333 #define AARCH64_FUSION_PAIR(name, internal_name) \
334 { name, AARCH64_FUSE_##internal_name },
336 {
341 };
343 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
344 { name, AARCH64_EXTRA_TUNE_##internal_name },
346 {
351 };
353 /* Tuning parameters. */
356 {
357 {
362 },
371 };
374 {
375 {
380 },
389 };
392 {
393 {
398 },
407 };
410 {
411 {
416 },
425 };
428 {
429 {
434 },
443 };
446 {
447 {
452 },
461 };
464 {
465 {
470 },
479 };
482 {
483 {
488 },
497 };
500 {
501 {
506 },
515 };
518 {
520 /* Avoid the use of slow int<->fp moves for spilling by setting
521 their cost higher than memmov_cost. */
525 };
528 {
530 /* Avoid the use of slow int<->fp moves for spilling by setting
531 their cost higher than memmov_cost. */
535 };
538 {
540 /* Avoid the use of slow int<->fp moves for spilling by setting
541 their cost higher than memmov_cost. */
545 };
548 {
550 /* Avoid the use of slow int<->fp moves for spilling by setting
551 their cost higher than memmov_cost (actual, 4 and 9). */
555 };
558 {
563 };
566 {
568 /* Avoid the use of slow int<->fp moves for spilling by setting
569 their cost higher than memmov_cost. */
573 };
576 {
578 /* Avoid the use of int<->fp moves for spilling. */
582 };
585 {
587 /* Avoid the use of int<->fp moves for spilling. */
591 };
594 {
596 /* Avoid the use of int<->fp moves for spilling. */
600 };
603 {
605 /* Avoid the use of slow int<->fp moves for spilling by setting
606 their cost higher than memmov_cost. */
610 };
613 {
615 /* Avoid the use of slow int<->fp moves for spilling by setting
616 their cost higher than memmov_cost. */
620 };
622 /* Generic costs for Advanced SIMD vector operations. */
624 {
645 };
647 /* Generic costs for SVE vector operations. */
649 {
650 {
671 },
677 };
679 /* Generic costs for vector insn classes. */
681 {
691 };
694 {
715 };
718 {
719 {
740 },
746 };
749 {
759 };
762 {
783 };
785 /* QDF24XX costs for vector insn classes. */
787 {
797 };
801 {
822 };
824 /* ThunderX costs for vector insn classes. */
826 {
836 };
839 {
860 };
863 {
873 };
876 {
897 };
899 /* Cortex-A57 costs for vector insn classes. */
901 {
911 };
914 {
935 };
938 {
948 };
951 {
972 };
974 /* Generic costs for vector insn classes. */
976 {
986 };
989 {
1010 };
1012 /* Costs for vector insn classes for Vulcan. */
1014 {
1024 };
1027 {
1048 };
1051 {
1061 };
1064 /* Generic costs for branch instructions. */
1066 {
1069 };
1071 /* Generic approximation modes. */
1073 {
1076 AARCH64_APPROX_NONE /* recip_sqrt */
1077 };
1079 /* Approximation modes for Exynos M1. */
1081 {
1084 AARCH64_APPROX_ALL /* recip_sqrt */
1085 };
1087 /* Approximation modes for X-Gene 1. */
1089 {
1092 AARCH64_APPROX_ALL /* recip_sqrt */
1093 };
1095 /* Generic prefetch settings (which disable prefetch). */
1097 {
1105 };
1108 {
1116 };
1119 {
1127 };
1130 {
1138 };
1141 {
1149 };
1152 {
1160 };
1163 {
1171 };
1174 {
1182 };
1185 {
1193 };
1196 {
1204 };
1207 {
1228 /* Enabling AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS significantly benefits
1229 Neoverse V1. It does not have a noticeable effect on A64FX and should
1230 have at most a very minor effect on SVE2 cores. */
1232 &generic_prefetch_tune
1233 };
1236 {
1259 &generic_prefetch_tune
1260 };
1263 {
1286 &generic_prefetch_tune
1287 };
1290 {
1313 &generic_prefetch_tune
1314 };
1317 {
1340 &generic_prefetch_tune
1341 };
1344 {
1367 &generic_prefetch_tune
1368 };
1373 {
1395 &exynosm1_prefetch_tune
1396 };
1399 {
1421 &thunderxt88_prefetch_tune
1422 };
1425 {
1446 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
1448 &thunderx_prefetch_tune
1449 };
1452 {
1475 &tsv110_prefetch_tune
1476 };
1479 {
1501 &xgene1_prefetch_tune
1502 };
1505 {
1512 SVE_NOT_IMPLEMENTED,
1527 &xgene1_prefetch_tune
1528 };
1531 {
1554 &qdf24xx_prefetch_tune
1555 };
1557 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
1558 for now. */
1560 {
1583 &generic_prefetch_tune
1584 };
1587 {
1610 &thunderx2t99_prefetch_tune
1611 };
1614 {
1637 &thunderx3t110_prefetch_tune
1638 };
1641 {
1663 &generic_prefetch_tune
1664 };
1667 {
1682 /* This value is just inherited from the Cortex-A57 table. */
1684 /* This depends very much on what the scalar value is and
1685 where it comes from. E.g. some constants take two dependent
1686 instructions or a load, while others might be moved from a GPR.
1687 4 seems to be a reasonable compromise in practice. */
1691 /* Although stores have a latency of 2 and compete for the
1692 vector pipes, in practice it's better not to model that. */
1695 };
1698 {
1699 {
1706 /* Theoretically, a reduction involving 31 scalar ADDs could
1707 complete in ~9 cycles and would have a cost of 31. [SU]ADDV
1708 completes in 14 cycles, so give it a cost of 31 + 5. */
1710 /* Likewise for 15 scalar ADDs (~5 cycles) vs. 12: 15 + 7. */
1712 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 10: 7 + 7. */
1714 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 10: 3 + 8. */
1716 /* Theoretically, a reduction involving 15 scalar FADDs could
1717 complete in ~9 cycles and would have a cost of 30. FADDV
1718 completes in 13 cycles, so give it a cost of 30 + 4. */
1720 /* Likewise for 7 scalar FADDs (~6 cycles) vs. 11: 14 + 5. */
1722 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 9: 6 + 5. */
1725 /* This value is just inherited from the Cortex-A57 table. */
1727 /* See the comment above the Advanced SIMD versions. */
1731 /* Although stores have a latency of 2 and compete for the
1732 vector pipes, in practice it's better not to model that. */
1735 },
1741 };
1744 {
1750 };
1753 {
1754 {
1760 },
1764 };
1767 {
1768 {
1769 {
1775 },
1779 },
1786 };
1789 {
1792 &neoversev1_sve_issue_info
1793 };
1795 /* Neoverse V1 costs for vector insn classes. */
1797 {
1807 };
1810 {
1831 (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
1832 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
1834 &generic_prefetch_tune
1835 };
1838 {
1860 &generic_prefetch_tune
1861 };
1864 {
1886 &a64fx_prefetch_tune
1887 };
1889 /* Support for fine-grained override of the tuning structures. */
1890 struct aarch64_tuning_override_function
1891 {
1894 };
1900 static const struct aarch64_tuning_override_function
1901 aarch64_tuning_override_functions[] =
1902 {
1907 };
1909 /* A processor implementing AArch64. */
1910 struct processor
1911 {
1919 };
1921 /* Architectures implementing AArch64. */
1923 {
1924 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
1925 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
1928 };
1930 /* Processor cores implementing AArch64. */
1932 {
1933 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
1934 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
1935 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
1936 FLAGS, &COSTS##_tunings},
1941 };
1944 /* Target specification. These are populated by the -march, -mtune, -mcpu
1945 handling code or by target attributes. */
1952 /* The current tuning set. */
1955 /* Check whether an 'aarch64_vector_pcs' attribute is valid. */
1957 static tree
1960 {
1961 /* Since we set fn_type_req to true, the caller should have checked
1962 this for us. */
1965 {
1972 name);
1979 }
1981 }
1983 /* Table of machine attributes. */
1985 {
1986 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1987 affects_type_identity, handler, exclude } */
1992 NULL },
1997 };
1999 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
2001 /* An ISA extension in the co-processor and main instruction set space. */
2002 struct aarch64_option_extension
2003 {
2007 };
2010 {
2014 }
2015 aarch64_cc;
2017 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
2019 struct aarch64_branch_protect_type
2020 {
2021 /* The type's name that the user passes to the branch-protection option
2022 string. */
2024 /* Function to handle the protection type and set global variables.
2025 First argument is the string token corresponding with this type and the
2026 second argument is the next token in the option string.
2027 Return values:
2028 * AARCH64_PARSE_OK: Handling was sucessful.
2029 * AARCH64_INVALID_ARG: The type is invalid in this context and the caller
2030 should print an error.
2031 * AARCH64_INVALID_FEATURE: The type is invalid and the handler prints its
2032 own error. */
2034 /* A list of types that can follow this type in the option string. */
2037 };
2039 static enum aarch64_parse_opt_result
2041 {
2045 {
2048 }
2050 }
2052 static enum aarch64_parse_opt_result
2054 {
2059 {
2062 }
2064 }
2066 static enum aarch64_parse_opt_result
2069 {
2073 }
2075 static enum aarch64_parse_opt_result
2078 {
2081 }
2083 static enum aarch64_parse_opt_result
2086 {
2089 }
2091 static enum aarch64_parse_opt_result
2094 {
2097 }
2103 };
2112 };
2114 /* The condition codes of the processor, and the inverse function. */
2116 {
2119 };
2121 /* The preferred condition codes for SVE conditions. */
2123 {
2126 };
2128 /* Return the assembly token for svpattern value VALUE. */
2132 {
2134 {
2135 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
2137 #undef CASE
2140 }
2142 }
2144 /* Return the location of a piece that is known to be passed or returned
2145 in registers. FIRST_ZR is the first unused vector argument register
2146 and FIRST_PR is the first unused predicate argument register. */
2148 rtx
2151 {
2163 }
2165 /* Return the total number of vector registers required by the PST. */
2167 unsigned int
2169 {
2174 }
2176 /* Return the total number of predicate registers required by the PST. */
2178 unsigned int
2180 {
2185 }
2187 /* Return the location of a PST that is known to be passed or returned
2188 in registers. FIRST_ZR is the first unused vector argument register
2189 and FIRST_PR is the first unused predicate argument register. */
2191 rtx
2195 {
2196 /* Try to return a single REG if possible. This leads to better
2197 code generation; it isn't required for correctness. */
2199 {
2202 }
2204 /* Build up a PARALLEL that contains the individual pieces. */
2207 {
2213 }
2215 }
2217 /* Analyze whether TYPE is a Pure Scalable Type according to the rules
2218 in the AAPCS64. */
2222 {
2223 /* Prevent accidental reuse. */
2226 /* No code will be generated for erroneous types, so we won't establish
2227 an ABI mapping. */
2231 /* Zero-sized types disappear in the language->ABI mapping. */
2235 /* Check for SVTs, SPTs, and built-in tuple types that map to PSTs. */
2236 piece p = {};
2238 {
2246 }
2248 /* Check for user-defined PSTs. */
2255 }
2257 /* Analyze a type that is known not to be passed or returned in memory.
2258 Return true if it has an ABI identity and is a Pure Scalable Type. */
2260 bool
2262 {
2266 }
2268 /* Subroutine of analyze for handling ARRAY_TYPEs. */
2272 {
2273 /* Analyze the element type. */
2274 pure_scalable_type_info element_info;
2279 /* An array of unknown, flexible or variable length will be passed and
2280 returned by reference whatever we do. */
2285 /* Likewise if the array is constant-sized but too big to be interesting.
2286 The double checks against MAX_PIECES are to protect against overflow. */
2294 /* The above checks should have weeded out elements of unknown size. */
2295 poly_uint64 element_bytes;
2299 /* Build up the list of individual vectors and predicates. */
2303 {
2307 }
2309 }
2311 /* Subroutine of analyze for handling RECORD_TYPEs. */
2315 {
2317 {
2321 /* Zero-sized fields disappear in the language->ABI mapping. */
2325 /* All fields with an ABI identity must be PSTs for the record as
2326 a whole to be a PST. If any individual field is too big to be
2327 interesting then the record is too. */
2328 pure_scalable_type_info field_info;
2335 /* Since all previous fields are PSTs, we ought to be able to track
2336 the field offset using poly_ints. */
2340 /* For the same reason, it shouldn't be possible to create a PST field
2341 whose offset isn't byte-aligned. */
2343 BITS_PER_UNIT);
2345 /* Punt if the record is too big to be interesting. */
2346 poly_uint64 bytepos;
2351 /* Add the individual vectors and predicates in the field to the
2352 record's list. */
2355 {
2359 }
2360 }
2361 /* Empty structures disappear in the language->ABI mapping. */
2363 }
2365 /* Add P to the list of pieces in the type. */
2367 void
2369 {
2370 /* Try to fold the new piece into the previous one to form a
2371 single-mode PST. For example, if we see three consecutive vectors
2372 of the same mode, we can represent them using the corresponding
2373 3-tuple mode.
2375 This is purely an optimization. */
2377 {
2389 {
2393 }
2394 }
2396 }
2398 /* Return true if at least one possible value of type TYPE includes at
2399 least one object of Pure Scalable Type, in the sense of the AAPCS64.
2401 This is a relatively expensive test for some types, so it should
2402 generally be made as late as possible. */
2404 static bool
2406 {
2423 }
2425 /* Return the descriptor of the SIMD ABI. */
2429 {
2432 {
2433 HARD_REG_SET full_reg_clobbers
2439 }
2441 }
2443 /* Return the descriptor of the SVE PCS. */
2447 {
2450 {
2451 HARD_REG_SET full_reg_clobbers
2458 }
2460 }
2462 /* If X is an UNSPEC_SALT_ADDR expression, return the address that it
2463 wraps, otherwise return X itself. */
2465 static rtx
2467 {
2474 }
2476 /* Like strip_offset, but also strip any UNSPEC_SALT_ADDR from the
2477 expression. */
2479 static rtx
2481 {
2483 }
2485 /* Generate code to enable conditional branches in functions over 1 MiB. */
2489 {
2506 }
2508 void
2510 {
2515 else
2518 else
2522 else
2525 }
2527 /* Report when we try to do something that requires SVE when SVE is disabled.
2528 This is an error of last resort and isn't very high-quality. It usually
2529 involves attempts to measure the vector length in some way. */
2530 static void
2532 {
2535 /* Avoid reporting a slew of messages for a single oversight. */
2541 " option %<-march%>, or by using the %<target%>"
2544 }
2546 /* Return true if REGNO is P0-P15 or one of the special FFR-related
2547 registers. */
2550 {
2552 }
2554 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
2555 The register allocator chooses POINTER_AND_FP_REGS if FP_REGS and
2556 GENERAL_REGS have the same cost - even if POINTER_AND_FP_REGS has a much
2557 higher cost. POINTER_AND_FP_REGS is also used if the cost of both FP_REGS
2558 and GENERAL_REGS is lower than the memory cost (in this case the best class
2559 is the lowest cost one). Using POINTER_AND_FP_REGS irrespectively of its
2560 cost results in bad allocations with many redundant int<->FP moves which
2561 are expensive on various cores.
2562 To avoid this we don't allow POINTER_AND_FP_REGS as the allocno class, but
2563 force a decision between FP_REGS and GENERAL_REGS. We use the allocno class
2564 if it isn't POINTER_AND_FP_REGS. Similarly, use the best class if it isn't
2565 POINTER_AND_FP_REGS. Otherwise set the allocno class depending on the mode.
2566 The result of this is that it is no longer inefficient to have a higher
2567 memory move cost than the register move cost.
2568 */
2570 static reg_class_t
2572 reg_class_t best_class)
2573 {
2574 machine_mode mode;
2586 }
2588 static unsigned int
2590 {
2594 }
2596 /* Return the reassociation width of treeop OPC with mode MODE. */
2597 static int
2599 {
2604 /* Avoid reassociating floating point addition so we emit more FMAs. */
2608 }
2610 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
2611 unsigned
2613 {
2625 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
2626 equivalent DWARF register. */
2628 }
2630 /* If X is a CONST_DOUBLE, return its bit representation as a constant
2631 integer, otherwise return X unmodified. */
2632 static rtx
2634 {
2638 }
2640 /* Return an estimate for the number of quadwords in an SVE vector. This is
2641 equivalent to the number of Advanced SIMD vectors in an SVE vector. */
2642 static unsigned int
2644 {
2646 }
2648 /* Return true if MODE is any of the Advanced SIMD structure modes. */
2649 static bool
2651 {
2654 }
2656 /* Return true if MODE is an SVE predicate mode. */
2657 static bool
2659 {
2665 }
2667 /* Three mutually-exclusive flags describing a vector or predicate type. */
2671 /* Can be used in combination with VEC_ADVSIMD or VEC_SVE_DATA to indicate
2672 a structure of 2, 3 or 4 vectors. */
2674 /* Can be used in combination with VEC_SVE_DATA to indicate that the
2675 vector has fewer significant bytes than a full SVE vector. */
2677 /* Useful combinations of the above. */
2681 /* Return a set of flags describing the vector properties of mode MODE.
2682 Ignore modes that are not supported by the current target. */
2683 static unsigned int
2685 {
2692 /* Make the decision based on the mode's enum value rather than its
2693 properties, so that we keep the correct classification regardless
2694 of -msve-vector-bits. */
2696 {
2697 /* Partial SVE QI vectors. */
2701 /* Partial SVE HI vectors. */
2704 /* Partial SVE SI vector. */
2706 /* Partial SVE HF vectors. */
2709 /* Partial SVE BF vectors. */
2712 /* Partial SVE SF vector. */
2726 /* x2 SVE vectors. */
2735 /* x3 SVE vectors. */
2744 /* x4 SVE vectors. */
2755 /* 64-bit Advanced SIMD vectors. */
2759 /* ...E_V1DImode doesn't exist. */
2764 /* 128-bit Advanced SIMD vectors. */
2777 }
2778 }
2780 /* Return true if MODE is any of the data vector modes, including
2781 structure modes. */
2782 static bool
2784 {
2786 }
2788 /* Return true if MODE is any form of SVE mode, including predicates,
2789 vectors and structures. */
2790 bool
2792 {
2794 }
2796 /* Return true if MODE is an SVE data vector mode; either a single vector
2797 or a structure of vectors. */
2798 static bool
2800 {
2802 }
2804 /* Return the number of defined bytes in one constituent vector of
2805 SVE mode MODE, which has vector flags VEC_FLAGS. */
2806 static poly_int64
2808 {
2810 /* A single partial vector. */
2814 /* A single vector or a tuple. */
2817 /* A single predicate. */
2820 }
2822 /* Implement target hook TARGET_ARRAY_MODE. */
2823 static opt_machine_mode
2825 {
2832 }
2834 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
2835 static bool
2838 {
2846 }
2848 /* MODE is some form of SVE vector mode. For data modes, return the number
2849 of vector register bits that each element of MODE occupies, such as 64
2850 for both VNx2DImode and VNx2SImode (where each 32-bit value is stored
2851 in a 64-bit container). For predicate modes, return the number of
2852 data bits controlled by each significant predicate bit. */
2854 static unsigned int
2856 {
2859 ? BITS_PER_SVE_VECTOR
2862 }
2864 /* Return the SVE predicate mode to use for elements that have
2865 ELEM_NBYTES bytes, if such a mode exists. */
2867 opt_machine_mode
2869 {
2871 {
2880 }
2882 }
2884 /* Return the SVE predicate mode that should be used to control
2885 SVE mode MODE. */
2887 machine_mode
2889 {
2892 }
2894 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
2896 static opt_machine_mode
2898 {
2904 }
2906 /* Return the SVE vector mode that has NUNITS elements of mode INNER_MODE. */
2908 opt_machine_mode
2910 {
2913 machine_mode mode;
2920 }
2922 /* Return the integer element mode associated with SVE mode MODE. */
2924 static scalar_int_mode
2926 {
2928 ? BITS_PER_SVE_VECTOR
2933 }
2935 /* Return an integer element mode that contains exactly
2936 aarch64_sve_container_bits (MODE) bits. This is wider than
2937 aarch64_sve_element_int_mode if MODE is a partial vector,
2938 otherwise it's the same. */
2940 static scalar_int_mode
2942 {
2944 }
2946 /* Return the integer vector mode associated with SVE mode MODE.
2947 Unlike related_int_vector_mode, this can handle the case in which
2948 MODE is a predicate (and thus has a different total size). */
2950 machine_mode
2952 {
2955 }
2957 /* Implement TARGET_VECTORIZE_RELATED_MODE. */
2959 static opt_machine_mode
2961 scalar_mode element_mode,
2962 poly_uint64 nunits)
2963 {
2966 /* If we're operating on SVE vectors, try to return an SVE mode. */
2967 poly_uint64 sve_nunits;
2971 {
2972 machine_mode sve_mode;
2974 {
2975 /* Try to find a full or partial SVE mode with exactly
2976 NUNITS units. */
2981 }
2982 else
2983 {
2984 /* Take the preferred number of units from the number of bytes
2985 that fit in VECTOR_MODE. We always start by "autodetecting"
2986 a full vector mode with preferred_simd_mode, so vectors
2987 chosen here will also be full vector modes. Then
2988 autovectorize_vector_modes tries smaller starting modes
2989 and thus smaller preferred numbers of units. */
2994 }
2995 }
2997 /* Prefer to use 1 128-bit vector instead of 2 64-bit vectors. */
3003 {
3007 }
3010 }
3012 /* Implement TARGET_PREFERRED_ELSE_VALUE. For binary operations,
3013 prefer to use the first arithmetic operand as the else value if
3014 the else value doesn't matter, since that exactly matches the SVE
3015 destructive merging form. For ternary operations we could either
3016 pick the first operand and use FMAD-like instructions or the last
3017 operand and use FMLA-like instructions; the latter seems more
3018 natural. */
3020 static tree
3022 {
3024 }
3026 /* Implement TARGET_HARD_REGNO_NREGS. */
3028 static unsigned int
3030 {
3031 /* ??? Logically we should only need to provide a value when
3032 HARD_REGNO_MODE_OK says that the combination is valid,
3033 but at the moment we need to handle all modes. Just ignore
3034 any runtime parts for registers that can't store them. */
3037 {
3041 {
3047 }
3056 }
3058 }
3060 /* Implement TARGET_HARD_REGNO_MODE_OK. */
3062 static bool
3064 {
3069 /* This must have the same size as _Unwind_Word. */
3080 /* The purpose of comparing with ptr_mode is to support the
3081 global register variable associated with the stack pointer
3082 register via the syntax of asm ("wsp") in ILP32. */
3089 {
3096 }
3098 {
3101 else
3103 }
3106 }
3108 /* Return true if a function with type FNTYPE returns its value in
3109 SVE vector or predicate registers. */
3111 static bool
3113 {
3116 pure_scalable_type_info pst_info;
3118 {
3130 }
3132 }
3134 /* Return true if a function with type FNTYPE takes arguments in
3135 SVE vector or predicate registers. */
3137 static bool
3139 {
3140 CUMULATIVE_ARGS args_so_far_v;
3148 {
3155 pure_scalable_type_info pst_info;
3157 {
3162 }
3165 }
3167 }
3169 /* Implement TARGET_FNTYPE_ABI. */
3173 {
3182 }
3184 /* Implement TARGET_COMPATIBLE_VECTOR_TYPES_P. */
3186 static bool
3188 {
3191 }
3193 /* Return true if we should emit CFI for register REGNO. */
3195 static bool
3197 {
3200 }
3202 /* Return the mode we should use to save and restore register REGNO. */
3204 static machine_mode
3206 {
3212 {
3214 /* Only the low 64 bits are saved by the base PCS. */
3218 /* The vector PCS saves the low 128 bits (which is the full
3219 register on non-SVE targets). */
3223 /* Use vectors of DImode for registers that need frame
3224 information, so that the first 64 bytes of the save slot
3225 are always the equivalent of what storing D<n> would give. */
3229 /* Use vectors of bytes otherwise, so that the layout is
3230 endian-agnostic, and so that we can use LDR and STR for
3231 big-endian targets. */
3237 }
3240 /* Save the full predicate register. */
3244 }
3246 /* Implement TARGET_INSN_CALLEE_ABI. */
3250 {
3257 }
3259 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
3260 the lower 64 bits of a 128-bit register. Tell the compiler the callee
3261 clobbers the top 64 bits when restoring the bottom 64 bits. */
3263 static bool
3266 machine_mode mode)
3267 {
3269 {
3277 }
3279 }
3281 /* Implement REGMODE_NATURAL_SIZE. */
3282 poly_uint64
3284 {
3285 /* The natural size for SVE data modes is one SVE data vector,
3286 and similarly for predicates. We can't independently modify
3287 anything smaller than that. */
3288 /* ??? For now, only do this for variable-width SVE registers.
3289 Doing it for constant-sized registers breaks lower-subreg.c. */
3290 /* ??? And once that's fixed, we should probably have similar
3291 code for Advanced SIMD. */
3293 {
3299 }
3301 }
3303 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
3304 machine_mode
3306 machine_mode mode)
3307 {
3308 /* The predicate mode determines which bits are significant and
3309 which are "don't care". Decreasing the number of lanes would
3310 lose data while increasing the number of lanes would make bits
3311 unnecessarily significant. */
3316 else
3318 }
3320 /* Return true if I's bits are consecutive ones from the MSB. */
3321 bool
3323 {
3325 }
3327 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
3328 that strcpy from constants will be faster. */
3330 static HOST_WIDE_INT
3332 {
3336 }
3338 /* Return true if calls to DECL should be treated as
3339 long-calls (ie called via a register). */
3340 static bool
3342 {
3344 }
3346 /* Return true if calls to symbol-ref SYM should be treated as
3347 long-calls (ie called via a register). */
3348 bool
3350 {
3352 }
3354 /* Return true if calls to symbol-ref SYM should not go through
3355 plt stubs. */
3357 bool
3359 {
3363 && decl
3364 && (!flag_plt
3370 }
3372 /* Emit an insn that's a simple single-set. Both the operands must be
3373 known to be valid. */
3376 {
3378 }
3380 /* X and Y are two things to compare using CODE. Emit the compare insn and
3381 return the rtx for register 0 in the proper mode. */
3382 rtx
3384 {
3386 machine_mode cc_mode;
3387 rtx cc_reg;
3390 {
3405 }
3406 else
3407 {
3411 }
3413 }
3415 /* Similarly, but maybe zero-extend Y if Y_MODE < SImode. */
3417 static rtx
3419 machine_mode y_mode)
3420 {
3422 {
3424 {
3427 }
3428 else
3429 {
3431 machine_mode cc_mode;
3439 }
3440 }
3446 }
3448 /* Build the SYMBOL_REF for __tls_get_addr. */
3452 rtx
3454 {
3458 }
3460 /* Return the TLS model to use for ADDR. */
3462 static enum tls_model
3464 {
3466 poly_int64 offset;
3472 }
3474 /* We'll allow lo_sum's in addresses in our legitimate addresses
3475 so that combine would take care of combining addresses where
3476 necessary, but for generation purposes, we'll generate the address
3477 as :
3478 RTL Absolute
3479 tmp = hi (symbol_ref); adrp x1, foo
3480 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
3481 nop
3483 PIC TLS
3484 adrp x1, :got:foo adrp tmp, :tlsgd:foo
3485 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
3486 bl __tls_get_addr
3487 nop
3489 Load TLS symbol, depending on TLS mechanism and TLS access model.
3491 Global Dynamic - Traditional TLS:
3492 adrp tmp, :tlsgd:imm
3493 add dest, tmp, #:tlsgd_lo12:imm
3494 bl __tls_get_addr
3496 Global Dynamic - TLS Descriptors:
3497 adrp dest, :tlsdesc:imm
3498 ldr tmp, [dest, #:tlsdesc_lo12:imm]
3499 add dest, dest, #:tlsdesc_lo12:imm
3500 blr tmp
3501 mrs tp, tpidr_el0
3502 add dest, dest, tp
3504 Initial Exec:
3505 mrs tp, tpidr_el0
3506 adrp tmp, :gottprel:imm
3507 ldr dest, [tmp, #:gottprel_lo12:imm]
3508 add dest, dest, tp
3510 Local Exec:
3511 mrs tp, tpidr_el0
3512 add t0, tp, #:tprel_hi12:imm, lsl #12
3513 add t0, t0, #:tprel_lo12_nc:imm
3514 */
3516 static void
3519 {
3521 {
3523 {
3524 /* In ILP32, the mode of dest can be either SImode or DImode. */
3536 }
3543 {
3546 rtx insn;
3547 rtx mem;
3549 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
3550 here before rtl expand. Tree IVOPT will generate rtl pattern to
3551 decide rtx costs, in which case pic_offset_table_rtx is not
3552 initialized. For that case no need to generate the first adrp
3553 instruction as the final cost for global variable access is
3554 one instruction. */
3556 {
3557 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
3558 using the page base as GOT base, the first page may be wasted,
3559 in the worst scenario, there is only 28K space for GOT).
3561 The generate instruction sequence for accessing global variable
3562 is:
3564 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
3566 Only one instruction needed. But we must initialize
3567 pic_offset_table_rtx properly. We generate initialize insn for
3568 every global access, and allow CSE to remove all redundant.
3570 The final instruction sequences will look like the following
3571 for multiply global variables access.
3573 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
3575 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
3576 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
3577 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
3578 ... */
3587 }
3590 {
3593 else
3597 }
3598 else
3599 {
3604 }
3606 /* The operand is expected to be MEM. Whenever the related insn
3607 pattern changed, above code which calculate mem should be
3608 updated. */
3614 }
3617 {
3618 /* In ILP32, the mode of dest can be either SImode or DImode,
3619 while the got entry is always of SImode size. The mode of
3620 dest depends on how dest is used: if dest is assigned to a
3621 pointer (e.g. in the memory), it has SImode; it may have
3622 DImode if dest is dereferenced to access the memeory.
3623 This is why we have to handle three different ldr_got_small
3624 patterns here (two patterns for ILP32). */
3626 rtx insn;
3627 rtx mem;
3636 {
3639 else
3643 }
3644 else
3645 {
3650 }
3657 }
3660 {
3662 /* The return type of __tls_get_addr is the C pointer type
3663 so use ptr_mode. */
3673 else
3680 /* Convert back to the mode of the dest adding a zero_extend
3681 from SImode (ptr_mode) to DImode (Pmode). */
3685 }
3688 {
3691 rtx tp;
3695 /* In ILP32, the got entry is always of SImode size. Unlike
3696 small GOT, the dest is fixed at reg 0. */
3699 else
3710 }
3713 {
3714 /* In ILP32, the mode of dest can be either SImode or DImode,
3715 while the got entry is always of SImode size. The mode of
3716 dest depends on how dest is used: if dest is assigned to a
3717 pointer (e.g. in the memory), it has SImode; it may have
3718 DImode if dest is dereferenced to access the memeory.
3719 This is why we have to handle three different tlsie_small
3720 patterns here (two patterns for ILP32). */
3726 {
3729 else
3730 {
3733 }
3734 }
3735 else
3736 {
3739 }
3745 }
3751 {
3759 {
3782 }
3787 }
3790 {
3791 rtx insn;
3796 else
3797 {
3800 }
3804 }
3807 {
3812 {
3815 else
3816 {
3819 }
3820 }
3821 else
3822 {
3825 }
3830 }
3834 }
3835 }
3837 /* Emit a move from SRC to DEST. Assume that the move expanders can
3838 handle all moves if !can_create_pseudo_p (). The distinction is
3839 important because, unlike emit_move_insn, the move expanders know
3840 how to force Pmode objects into the constant pool even when the
3841 constant pool address is not itself legitimate. */
3842 static rtx
3844 {
3848 }
3850 /* Apply UNOPTAB to OP and store the result in DEST. */
3852 static void
3854 {
3858 }
3860 /* Apply BINOPTAB to OP0 and OP1 and store the result in DEST. */
3862 static void
3864 {
3866 OPTAB_DIRECT);
3869 }
3871 /* Split a 128-bit move operation into two 64-bit move operations,
3872 taking care to handle partial overlap of register to register
3873 copies. Special cases are needed when moving between GP regs and
3874 FP regs. SRC can be a register, constant or memory; DST a register
3875 or memory. If either operand is memory it must not have any side
3876 effects. */
3877 void
3879 {
3890 {
3894 /* Handle FP <-> GP regs. */
3896 {
3903 }
3905 {
3912 }
3913 }
3920 /* At most one pairing may overlap. */
3922 {
3925 }
3926 else
3927 {
3930 }
3931 }
3933 /* Return true if we should split a move from 128-bit value SRC
3934 to 128-bit register DEST. */
3936 bool
3938 {
3941 /* All moves to GPRs need to be split. */
3943 }
3945 /* Split a complex SIMD combine. */
3947 void
3949 {
3960 }
3962 /* Split a complex SIMD move. */
3964 void
3966 {
3973 {
3976 }
3977 }
3979 bool
3982 {
3986 }
3988 /* Return TARGET if it is nonnull and a register of mode MODE.
3989 Otherwise, return a fresh register of mode MODE if we can,
3990 or TARGET reinterpreted as MODE if we can't. */
3992 static rtx
3994 {
3998 {
4001 }
4003 }
4005 /* Return a register that contains the constant in BUILDER, given that
4006 the constant is a legitimate move operand. Use TARGET as the register
4007 if it is nonnull and convenient. */
4009 static rtx
4011 {
4016 }
4018 static rtx
4020 {
4023 else
4024 {
4028 }
4029 }
4031 /* Return true if predicate value X is a constant in which every element
4032 is a CONST_INT. When returning true, describe X in BUILDER as a VNx16BI
4033 value, i.e. as a predicate in which all bits are significant. */
4035 static bool
4037 {
4049 {
4057 }
4060 }
4062 /* BUILDER contains a predicate constant of mode VNx16BI. Return the
4063 widest predicate element size it can have (that is, the largest size
4064 for which each element would still be 0 or 1). */
4066 unsigned int
4068 {
4069 /* Start with the most optimistic assumption: that we only need
4070 one bit per pattern. This is what we will use if only the first
4071 bit in each pattern is ever set. */
4075 /* Look for set bits. */
4079 {
4083 }
4085 }
4087 /* If VNx16BImode rtx X is a canonical PTRUE for a predicate mode,
4088 return that predicate mode, otherwise return opt_machine_mode (). */
4090 opt_machine_mode
4092 {
4106 }
4108 /* BUILDER is a predicate constant of mode VNx16BI. Consider the value
4109 that the constant would have with predicate element size ELT_SIZE
4110 (ignoring the upper bits in each element) and return:
4112 * -1 if all bits are set
4113 * N if the predicate has N leading set bits followed by all clear bits
4114 * 0 if the predicate does not have any of these forms. */
4116 int
4119 {
4120 /* If nelts_per_pattern is 3, we have set bits followed by clear bits
4121 followed by set bits. */
4125 /* Skip over leading set bits. */
4133 /* Check for the all-true case. */
4137 /* If nelts_per_pattern is 1, then either VL is zero, or we have a
4138 repeating pattern of set bits followed by clear bits. */
4142 /* We have a "foreground" value and a duplicated "background" value.
4143 If the background might repeat and the last set bit belongs to it,
4144 we might have set bits followed by clear bits followed by set bits. */
4148 /* Make sure that the rest are all clear. */
4154 }
4156 /* See if there is an svpattern that encodes an SVE predicate of mode
4157 PRED_MODE in which the first VL bits are set and the rest are clear.
4158 Return the pattern if so, otherwise return AARCH64_NUM_SVPATTERNS.
4159 A VL of -1 indicates an all-true vector. */
4161 aarch64_svpattern
4163 {
4178 {
4181 /* These would only trigger for non-power-of-2 lengths. */
4188 }
4190 }
4192 /* Return a VNx16BImode constant in which every sequence of ELT_SIZE
4193 bits has the lowest bit set and the upper bits clear. This is the
4194 VNx16BImode equivalent of a PTRUE for controlling elements of
4195 ELT_SIZE bytes. However, because the constant is VNx16BImode,
4196 all bits are significant, even the upper zeros. */
4198 rtx
4200 {
4206 }
4208 /* Return an all-true predicate register of mode MODE. */
4210 rtx
4212 {
4216 }
4218 /* Return an all-false predicate register of mode MODE. */
4220 rtx
4222 {
4226 }
4228 /* PRED1[0] is a PTEST predicate and PRED1[1] is an aarch64_sve_ptrue_flag
4229 for it. PRED2[0] is the predicate for the instruction whose result
4230 is tested by the PTEST and PRED2[1] is again an aarch64_sve_ptrue_flag
4231 for it. Return true if we can prove that the two predicates are
4232 equivalent for PTEST purposes; that is, if we can replace PRED2[0]
4233 with PRED1[0] without changing behavior. */
4235 bool
4237 {
4249 }
4251 /* Emit a comparison CMP between OP0 and OP1, both of which have mode
4252 DATA_MODE, and return the result in a predicate of mode PRED_MODE.
4253 Use TARGET as the target register if nonnull and convenient. */
4255 static rtx
4258 {
4268 }
4270 /* Use a comparison to convert integer vector SRC into MODE, which is
4271 the corresponding SVE predicate mode. Use TARGET for the result
4272 if it's nonnull and convenient. */
4274 rtx
4276 {
4280 }
4282 /* Return the assembly token for svprfop value PRFOP. */
4286 {
4288 {
4289 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
4291 #undef CASE
4294 }
4296 }
4298 /* Return the assembly string for an SVE prefetch operation with
4299 mnemonic MNEMONIC, given that PRFOP_RTX is the prefetch operation
4300 and that SUFFIX is the format for the remaining operands. */
4305 {
4312 }
4314 /* Check whether we can calculate the number of elements in PATTERN
4315 at compile time, given that there are NELTS_PER_VQ elements per
4316 128-bit block. Return the value if so, otherwise return -1. */
4318 HOST_WIDE_INT
4320 {
4327 {
4328 /* There are two vector granules per quadword. */
4331 {
4337 }
4338 }
4339 else
4342 /* There are two vector granules per quadword. */
4347 /* Requesting more elements than are available results in a PFALSE. */
4352 }
4354 /* Return true if we can move VALUE into a register using a single
4355 CNT[BHWD] instruction. */
4357 static bool
4359 {
4361 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
4366 }
4368 /* Likewise for rtx X. */
4370 bool
4372 {
4373 poly_int64 value;
4375 }
4377 /* Return the asm string for an instruction with a CNT-like vector size
4378 operand (a vector pattern followed by a multiplier in the range [1, 16]).
4379 PREFIX is the mnemonic without the size suffix and OPERANDS is the
4380 first part of the operands template (the part that comes before the
4381 vector size itself). PATTERN is the pattern to use. FACTOR is the
4382 number of quadwords. NELTS_PER_VQ, if nonzero, is the number of elements
4383 in each quadword. If it is zero, we can use any element size. */
4387 aarch64_svpattern pattern,
4390 {
4394 /* There is some overlap in the ranges of the four CNT instructions.
4395 Here we always use the smallest possible element size, so that the
4396 multiplier is 1 whereever possible. */
4410 else
4413 factor);
4416 }
4418 /* Return the asm string for an instruction with a CNT-like vector size
4419 operand (a vector pattern followed by a multiplier in the range [1, 16]).
4420 PREFIX is the mnemonic without the size suffix and OPERANDS is the
4421 first part of the operands template (the part that comes before the
4422 vector size itself). X is the value of the vector size operand,
4423 as a polynomial integer rtx; we need to convert this into an "all"
4424 pattern with a multiplier. */
4428 rtx x)
4429 {
4434 }
4436 /* Return the asm string for an instruction with a CNT-like vector size
4437 operand (a vector pattern followed by a multiplier in the range [1, 16]).
4438 PREFIX is the mnemonic without the size suffix and OPERANDS is the
4439 first part of the operands template (the part that comes before the
4440 vector size itself). CNT_PAT[0..2] are the operands of the
4441 UNSPEC_SVE_CNT_PAT; see aarch64_sve_cnt_pat for details. */
4446 {
4452 }
4454 /* Return true if we can add X using a single SVE INC or DEC instruction. */
4456 bool
4458 {
4459 poly_int64 value;
4463 }
4465 /* Return the asm string for adding SVE INC/DEC immediate OFFSET to
4466 operand 0. */
4470 {
4476 else
4479 }
4481 /* Return true if we can add VALUE to a register using a single ADDVL
4482 or ADDPL instruction. */
4484 static bool
4486 {
4490 /* FACTOR counts VG / 2, so a value of 2 is one predicate width
4491 and a value of 16 is one vector width. */
4494 }
4496 /* Likewise for rtx X. */
4498 bool
4500 {
4501 poly_int64 value;
4504 }
4506 /* Return the asm string for adding ADDVL or ADDPL immediate OFFSET
4507 to operand 1 and storing the result in operand 0. */
4511 {
4519 else
4522 }
4524 /* Return true if X is a valid immediate for an SVE vector INC or DEC
4525 instruction. If it is, store the number of elements in each vector
4526 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
4527 factor in *FACTOR_OUT (if nonnull). */
4529 bool
4532 {
4533 rtx elt;
4534 poly_int64 value;
4542 /* There's no vector INCB. */
4549 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
4559 }
4561 /* Return true if X is a valid immediate for an SVE vector INC or DEC
4562 instruction. */
4564 bool
4566 {
4568 }
4570 /* Return the asm template for an SVE vector INC or DEC instruction.
4571 OPERANDS gives the operands before the vector count and X is the
4572 value of the vector count operand itself. */
4576 {
4584 else
4587 }
4589 static int
4591 scalar_int_mode mode)
4592 {
4601 {
4605 }
4607 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
4608 (with XXXX non-zero). In that case check to see if the move can be done in
4609 a smaller mode. */
4614 {
4618 /* Check if we have to emit a second instruction by checking to see
4619 if any of the upper 32 bits of the original DI mode value is set. */
4630 }
4633 {
4635 {
4640 else
4643 }
4645 }
4647 /* Remaining cases are all for DImode. */
4656 {
4657 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
4658 For a 64-bit bitmask try whether changing 16 bits to all ones or
4659 zeroes creates a valid bitmask. To check any repeated bitmask,
4660 try using 16 bits from the other 32-bit half of val. */
4663 {
4674 }
4676 {
4678 {
4682 }
4684 }
4685 }
4687 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
4688 are emitted by the initial mov. If one_match > zero_match, skip set bits,
4689 otherwise skip zero bits. */
4701 {
4707 num_insns ++;
4708 }
4711 }
4713 /* Return whether imm is a 128-bit immediate which is simple enough to
4714 expand inline. */
4715 bool
4717 {
4728 }
4731 /* Return the number of temporary registers that aarch64_add_offset_1
4732 would need to add OFFSET to a register. */
4734 static unsigned int
4736 {
4738 }
4740 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
4741 a non-polynomial OFFSET. MODE is the mode of the addition.
4742 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
4743 be set and CFA adjustments added to the generated instructions.
4745 TEMP1, if nonnull, is a register of mode MODE that can be used as a
4746 temporary if register allocation is already complete. This temporary
4747 register may overlap DEST but must not overlap SRC. If TEMP1 is known
4748 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
4749 the immediate again.
4751 Since this function may be used to adjust the stack pointer, we must
4752 ensure that it cannot cause transient stack deallocation (for example
4753 by first incrementing SP and then decrementing when adjusting by a
4754 large immediate). */
4756 static void
4760 {
4768 {
4770 {
4773 }
4775 }
4777 /* Single instruction adjustment. */
4779 {
4783 }
4785 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
4786 and either:
4788 a) the offset cannot be loaded by a 16-bit move or
4789 b) there is no spare register into which we can move it. */
4793 {
4802 }
4804 /* Emit a move immediate if required and an addition/subtraction. */
4806 {
4810 }
4815 {
4819 }
4820 }
4822 /* Return the number of temporary registers that aarch64_add_offset
4823 would need to move OFFSET into a register or add OFFSET to a register;
4824 ADD_P is true if we want the latter rather than the former. */
4826 static unsigned int
4828 {
4829 /* This follows the same structure as aarch64_add_offset. */
4838 /* Need one register for the ADDVL/ADDPL result. */
4841 {
4844 /* Need one register for the CNT result and one for the multiplication
4845 factor. If necessary, the second temporary can be reused for the
4846 constant part of the offset. */
4848 /* Need one register for the CNT result (which might then
4849 be shifted). */
4851 }
4853 }
4855 /* If X can be represented as a poly_int64, return the number
4856 of temporaries that are required to add it to a register.
4857 Return -1 otherwise. */
4859 int
4861 {
4862 poly_int64 offset;
4866 }
4868 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
4869 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
4870 be set and CFA adjustments added to the generated instructions.
4872 TEMP1, if nonnull, is a register of mode MODE that can be used as a
4873 temporary if register allocation is already complete. This temporary
4874 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
4875 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
4876 false to avoid emitting the immediate again.
4878 TEMP2, if nonnull, is a second temporary register that doesn't
4879 overlap either DEST or REG.
4881 Since this function may be used to adjust the stack pointer, we must
4882 ensure that it cannot cause transient stack deallocation (for example
4883 by first incrementing SP and then decrementing when adjusting by a
4884 large immediate). */
4886 static void
4890 {
4894 || !frame_related_p
4898 /* Try using ADDVL or ADDPL to add the whole value. */
4900 {
4905 }
4907 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
4908 SVE vector register, over and above the minimum size of 128 bits.
4909 This is equivalent to half the value returned by CNTD with a
4910 vector shape of ALL. */
4914 /* Try using ADDVL or ADDPL to add the VG-based part. */
4918 {
4921 {
4925 }
4926 else
4927 {
4932 }
4933 }
4934 /* Otherwise use a CNT-based sequence. */
4936 {
4937 /* Use a subtraction if we have a negative factor. */
4940 {
4943 }
4945 /* Calculate CNTD * FACTOR / 2. First try to fold the division
4946 into the multiplication. */
4947 rtx val;
4950 /* Use a right shift by 1. */
4952 else
4956 {
4958 {
4959 /* "CNTB Xn, ALL, MUL #FACTOR" is out of range, so calculate
4960 the value with the minimum multiplier and shift it into
4961 position. */
4965 }
4967 }
4968 else
4969 {
4970 /* Base the factor on LOW_BIT if we can calculate LOW_BIT
4971 directly, since that should increase the chances of being
4972 able to use a shift and add sequence. If LOW_BIT itself
4973 is out of range, just use CNTD. */
4976 else
4983 {
4986 }
4987 else
4988 {
4989 /* Go back to using a negative multiplication factor if we have
4990 no register from which to subtract. */
4992 {
4995 }
4999 }
5000 }
5003 {
5004 /* Multiply by 1 << SHIFT. */
5007 }
5009 {
5010 /* Divide by 2. */
5013 }
5015 /* Calculate SRC +/- CNTD * FACTOR / 2. */
5017 {
5020 }
5022 {
5025 }
5028 {
5031 {
5035 poly_offset)));
5036 }
5040 }
5041 else
5042 {
5046 }
5049 }
5053 }
5055 /* Like aarch64_add_offset, but the offset is given as an rtx rather
5056 than a poly_int64. */
5058 void
5061 {
5064 }
5066 /* Add DELTA to the stack pointer, marking the instructions frame-related.
5067 TEMP1 is available as a temporary if nonnull. EMIT_MOVE_IMM is false
5068 if TEMP1 already contains abs (DELTA). */
5072 {
5075 }
5077 /* Subtract DELTA from the stack pointer, marking the instructions
5078 frame-related if FRAME_RELATED_P. TEMP1 is available as a temporary
5079 if nonnull. */
5084 {
5087 }
5089 /* Set DEST to (vec_series BASE STEP). */
5091 static void
5093 {
5097 /* Each operand can be a register or an immediate in the range [-16, 15]. */
5104 }
5106 /* Duplicate 128-bit Advanced SIMD vector SRC so that it fills an SVE
5107 register of mode MODE. Use TARGET for the result if it's nonnull
5108 and convenient.
5110 The two vector modes must have the same element mode. The behavior
5111 is to duplicate architectural lane N of SRC into architectural lanes
5112 N + I * STEP of the result. On big-endian targets, architectural
5113 lane 0 of an Advanced SIMD vector is the last element of the vector
5114 in memory layout, so for big-endian targets this operation has the
5115 effect of reversing SRC before duplicating it. Callers need to
5116 account for this. */
5118 rtx
5120 {
5123 insn_code icode = (BYTES_BIG_ENDIAN
5132 {
5133 /* Create a PARALLEL describing the reversal of SRC. */
5138 }
5141 }
5143 /* Try to force 128-bit vector value SRC into memory and use LD1RQ to fetch
5144 the memory image into DEST. Return true on success. */
5146 static bool
5148 {
5153 /* Make sure that the address is legitimate. */
5155 {
5158 }
5165 }
5167 /* SRC is an SVE CONST_VECTOR that contains N "foreground" values followed
5168 by N "background" values. Try to move it into TARGET using:
5170 PTRUE PRED.<T>, VL<N>
5171 MOV TRUE.<T>, #<foreground>
5172 MOV FALSE.<T>, #<background>
5173 SEL TARGET.<T>, PRED.<T>, TRUE.<T>, FALSE.<T>
5175 The PTRUE is always a single instruction but the MOVs might need a
5176 longer sequence. If the background value is zero (as it often is),
5177 the sequence can sometimes collapse to a PTRUE followed by a
5178 zero-predicated move.
5180 Return the target on success, otherwise return null. */
5182 static rtx
5184 {
5187 /* Make sure that the PTRUE is valid. */
5199 {
5202 }
5204 {
5207 }
5215 }
5217 /* Return a register containing CONST_VECTOR SRC, given that SRC has an
5218 SVE data mode and isn't a legitimate constant. Use TARGET for the
5219 result if convenient.
5221 The returned register can have whatever mode seems most natural
5222 given the contents of SRC. */
5224 static rtx
5226 {
5238 {
5239 /* We have a partial vector mode and a constant whose full-vector
5240 equivalent would occupy a repeating 128-bit sequence. Build that
5241 full-vector equivalent instead, so that we have the option of
5242 using LD1RQ and Advanced SIMD operations. */
5251 }
5254 {
5255 /* The constant is a duplicated quadword but can't be narrowed
5256 beyond a quadword. Get the memory image of the first quadword
5257 as a 128-bit vector and try using LD1RQ to load it from memory.
5259 The effect for both endiannesses is to load memory lane N into
5260 architectural lanes N + I * STEP of the result. On big-endian
5261 targets, the layout of the 128-bit vector in an Advanced SIMD
5262 register would be different from its layout in an SVE register,
5263 but this 128-bit vector is a memory value only. */
5268 }
5271 {
5272 /* The vector is a repeating sequence of 64 bits or fewer.
5273 See if we can load them using an Advanced SIMD move and then
5274 duplicate it to fill a vector. This is better than using a GPR
5275 move because it keeps everything in the same register file. */
5279 {
5280 /* We want memory lane N to go into architectural lane N,
5281 so reverse for big-endian targets. The DUP .Q pattern
5282 has a compensating reverse built-in. */
5285 }
5288 {
5291 }
5293 /* Get an integer representation of the repeating part of Advanced
5294 SIMD vector VQ_SRC. This preserves the endianness of VQ_SRC,
5295 which for big-endian targets is lane-swapped wrt a normal
5296 Advanced SIMD vector. This means that for both endiannesses,
5297 memory lane N of SVE vector SRC corresponds to architectural
5298 lane N of a register holding VQ_SRC. This in turn means that
5299 memory lane 0 of SVE vector SRC is in the lsb of VQ_SRC (viewed
5300 as a single 128-bit value) and thus that memory lane 0 of SRC is
5301 in the lsb of the integer. Duplicating the integer therefore
5302 ensures that memory lane N of SRC goes into architectural lane
5303 N + I * INDEX of the SVE register. */
5307 {
5308 /* Pretend that we had a vector of INT_MODE to start with. */
5312 /* If the integer can be moved into a general register by a
5313 single instruction, do that and duplicate the result. */
5316 {
5319 }
5320 }
5322 /* We're duplicating a single value, but can't do better than
5323 force it to memory and load from there. This handles things
5324 like symbolic constants. */
5328 {
5329 /* Load the element from memory if we can, otherwise move it into
5330 a register and use a DUP. */
5335 }
5336 }
5338 /* Try using INDEX. */
5341 {
5344 }
5346 /* From here on, it's better to force the whole constant to memory
5347 if we can. */
5355 /* Expand each pattern individually. */
5357 rtx_vector_builder builder;
5360 {
5365 }
5367 /* Use permutes to interleave the separate vectors. */
5369 {
5372 {
5377 }
5378 }
5381 }
5383 /* Use WHILE to set a predicate register of mode MODE in which the first
5384 VL bits are set and the rest are clear. Use TARGET for the register
5385 if it's nonnull and convenient. */
5387 static rtx
5390 {
5396 }
5398 static rtx
5401 /* BUILDER is a constant predicate in which the index of every set bit
5402 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
5403 by inverting every element at a multiple of ELT_SIZE and EORing the
5404 result with an ELT_SIZE PTRUE.
5406 Return a register that contains the constant on success, otherwise
5407 return null. Use TARGET as the register if it is nonnull and
5408 convenient. */
5410 static rtx
5413 {
5414 /* Invert every element at a multiple of ELT_SIZE, keeping the
5415 other bits zero. */
5421 else
5425 /* See if we can load the constant cheaply. */
5430 /* EOR the result with an ELT_SIZE PTRUE. */
5437 }
5439 /* BUILDER is a constant predicate in which the index of every set bit
5440 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
5441 using a TRN1 of size PERMUTE_SIZE, which is >= ELT_SIZE. Return the
5442 register on success, otherwise return null. Use TARGET as the register
5443 if nonnull and convenient. */
5445 static rtx
5449 {
5450 /* We're going to split the constant into two new constants A and B,
5451 with element I of BUILDER going into A if (I & PERMUTE_SIZE) == 0
5452 and into B otherwise. E.g. for PERMUTE_SIZE == 4 && ELT_SIZE == 1:
5454 A: { 0, 1, 2, 3, _, _, _, _, 8, 9, 10, 11, _, _, _, _ }
5455 B: { 4, 5, 6, 7, _, _, _, _, 12, 13, 14, 15, _, _, _, _ }
5457 where _ indicates elements that will be discarded by the permute.
5459 First calculate the ELT_SIZEs for A and B. */
5464 {
5467 else
5469 }
5473 /* Now construct the vectors themselves. */
5481 {
5484 }
5486 {
5487 /* The A and B elements are significant. */
5490 }
5491 else
5492 {
5493 /* The A and B elements are going to be discarded, so pick whatever
5494 is likely to give a nice constant. We are targeting element
5495 sizes A_ELT_SIZE and B_ELT_SIZE for A and B respectively,
5496 with the aim of each being a sequence of ones followed by
5497 a sequence of zeros. So:
5499 * if X_ELT_SIZE <= PERMUTE_SIZE, the best approach is to
5500 duplicate the last X_ELT_SIZE element, to extend the
5501 current sequence of ones or zeros.
5503 * if X_ELT_SIZE > PERMUTE_SIZE, the best approach is to add a
5504 zero, so that the constant really does have X_ELT_SIZE and
5505 not a smaller size. */
5508 else
5512 else
5514 }
5518 /* Try loading A into a register. */
5524 /* Try loading B into a register. */
5527 {
5530 {
5533 }
5534 }
5536 /* Emit the TRN1 itself. We emit a TRN that operates on VNx16BI
5537 operands but permutes them as though they had mode MODE. */
5543 }
5545 /* Subroutine of aarch64_expand_sve_const_pred. Try to load the VNx16BI
5546 constant in BUILDER into an SVE predicate register. Return the register
5547 on success, otherwise return null. Use TARGET for the register if
5548 nonnull and convenient.
5550 ALLOW_RECURSE_P is true if we can use methods that would call this
5551 function recursively. */
5553 static rtx
5556 {
5558 /* A PFALSE or a PTRUE .B ALL. */
5563 {
5564 /* If we can load the constant using PTRUE, use it as-is. */
5569 /* Otherwise use WHILE to set the first VL bits. */
5571 }
5576 /* Try inverting the vector in element size ELT_SIZE and then EORing
5577 the result with an ELT_SIZE PTRUE. */
5580 elt_size))
5583 /* Try using TRN1 to permute two simpler constants. */
5590 }
5592 /* Return an SVE predicate register that contains the VNx16BImode
5593 constant in BUILDER, without going through the move expanders.
5595 The returned register can have whatever mode seems most natural
5596 given the contents of BUILDER. Use TARGET for the result if
5597 convenient. */
5599 static rtx
5601 {
5602 /* Try loading the constant using pure predicate operations. */
5606 /* Try forcing the constant to memory. */
5609 {
5613 }
5615 /* The last resort is to load the constant as an integer and then
5616 compare it against zero. Use -1 for set bits in order to increase
5617 the changes of using SVE DUPM or an Advanced SIMD byte mask. */
5625 }
5627 /* Set DEST to immediate IMM. */
5629 void
5631 {
5634 /* Check on what type of symbol it is. */
5635 scalar_int_mode int_mode;
5641 {
5642 rtx mem;
5643 poly_int64 offset;
5644 HOST_WIDE_INT const_offset;
5647 /* If we have (const (plus symbol offset)), separate out the offset
5648 before we start classifying the symbol. */
5651 /* We must always add an offset involving VL separately, rather than
5652 folding it into the relocation. */
5654 {
5656 {
5659 }
5662 else
5663 {
5664 /* Do arithmetic on 32-bit values if the result is smaller
5665 than that. */
5667 {
5668 /* It is invalid to do symbol calculations in modes
5669 narrower than SImode. */
5673 }
5675 {
5679 }
5680 else
5683 }
5685 }
5689 {
5696 {
5702 }
5707 /* If we aren't generating PC relative literals, then
5708 we need to expand the literal pool access carefully.
5709 This is something that needs to be done in a number
5710 of places, so could well live as a separate function. */
5712 {
5719 }
5736 {
5742 }
5743 /* FALLTHRU */
5756 }
5757 }
5760 {
5762 {
5763 /* Only the low bit of each .H, .S and .D element is defined,
5764 so we can set the upper bits to whatever we like. If the
5765 predicate is all-true in MODE, prefer to set all the undefined
5766 bits as well, so that we can share a single .B predicate for
5767 all modes. */
5771 /* All methods for constructing predicate modes wider than VNx16BI
5772 will set the upper bits of each element to zero. Expose this
5773 by moving such constants as a VNx16BI, so that all bits are
5774 significant and so that constants for different modes can be
5775 shared. The wider constant will still be available as a
5776 REG_EQUAL note. */
5777 rtx_vector_builder builder;
5779 {
5784 }
5785 }
5789 {
5792 }
5796 {
5800 }
5806 }
5810 }
5812 /* Return the MEM rtx that provides the canary value that should be used
5813 for stack-smashing protection. MODE is the mode of the memory.
5814 For SSP_GLOBAL, DECL_RTL is the MEM rtx for the canary variable
5815 (__stack_chk_guard), otherwise it has no useful value. SALT_TYPE
5816 indicates whether the caller is performing a SET or a TEST operation. */
5818 rtx
5820 aarch64_salt_type salt_type)
5821 {
5822 rtx addr;
5824 {
5827 poly_int64 offset;
5836 }
5837 else
5838 {
5839 /* Calculate the address from the system register. */
5844 else
5845 {
5848 }
5850 }
5852 }
5854 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
5855 that is known to contain PTRUE. */
5857 void
5859 {
5867 }
5869 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
5870 operand is in memory. In this case we need to use the predicated LD1
5871 and ST1 instead of LDR and STR, both for correctness on big-endian
5872 targets and because LD1 and ST1 support a wider range of addressing modes.
5873 PRED_MODE is the mode of the predicate.
5875 See the comment at the head of aarch64-sve.md for details about the
5876 big-endian handling. */
5878 void
5880 {
5885 {
5889 else
5892 }
5894 }
5896 /* Called only on big-endian targets. See whether an SVE vector move
5897 from SRC to DEST is effectively a REV[BHW] instruction, because at
5898 least one operand is a subreg of an SVE vector that has wider or
5899 narrower elements. Return true and emit the instruction if so.
5901 For example:
5903 (set (reg:VNx8HI R1) (subreg:VNx8HI (reg:VNx16QI R2) 0))
5905 represents a VIEW_CONVERT between the following vectors, viewed
5906 in memory order:
5908 R2: { [0].high, [0].low, [1].high, [1].low, ... }
5909 R1: { [0], [1], [2], [3], ... }
5911 The high part of lane X in R2 should therefore correspond to lane X*2
5912 of R1, but the register representations are:
5914 msb lsb
5915 R2: ...... [1].high [1].low [0].high [0].low
5916 R1: ...... [3] [2] [1] [0]
5918 where the low part of lane X in R2 corresponds to lane X*2 in R1.
5919 We therefore need a reverse operation to swap the high and low values
5920 around.
5922 This is purely an optimization. Without it we would spill the
5923 subreg operand to the stack in one mode and reload it in the
5924 other mode, which has the same effect as the REV. */
5926 bool
5928 {
5931 /* Do not try to optimize subregs that LRA has created for matched
5932 reloads. These subregs only exist as a temporary measure to make
5933 the RTL well-formed, but they are exempt from the usual
5934 TARGET_CAN_CHANGE_MODE_CLASS rules.
5936 For example, if we have:
5938 (set (reg:VNx8HI R1) (foo:VNx8HI (reg:VNx4SI R2)))
5940 and the constraints require R1 and R2 to be in the same register,
5941 LRA may need to create RTL such as:
5943 (set (subreg:VNx4SI (reg:VNx8HI TMP) 0) (reg:VNx4SI R2))
5944 (set (reg:VNx8HI TMP) (foo:VNx8HI (subreg:VNx4SI (reg:VNx8HI TMP) 0)))
5945 (set (reg:VNx8HI R1) (reg:VNx8HI TMP))
5947 which forces both the input and output of the original instruction
5948 to use the same hard register. But for this to work, the normal
5949 rules have to be suppressed on the subreg input, otherwise LRA
5950 would need to reload that input too, meaning that the process
5951 would never terminate. To compensate for this, the normal rules
5952 are also suppressed for the subreg output of the first move.
5953 Ignoring the special case and handling the first move normally
5954 would therefore generate wrong code: we would reverse the elements
5955 for the first subreg but not reverse them back for the second subreg. */
5961 /* The optimization handles two single SVE REGs with different element
5962 sizes. */
5971 /* Generate *aarch64_sve_mov<mode>_subreg_be. */
5974 UNSPEC_REV_SUBREG);
5977 }
5979 /* Return a copy of X with mode MODE, without changing its other
5980 attributes. Unlike gen_lowpart, this doesn't care whether the
5981 mode change is valid. */
5983 rtx
5985 {
5992 }
5994 /* Return the SVE REV[BHW] unspec for reversing quantites of mode MODE
5995 stored in wider integer containers. */
5997 static unsigned int
5999 {
6001 {
6005 }
6007 }
6009 /* Split a *aarch64_sve_mov<mode>_subreg_be pattern with the given
6010 operands. */
6012 void
6014 {
6015 /* Decide which REV operation we need. The mode with wider elements
6016 determines the mode of the operands and the mode with the narrower
6017 elements determines the reverse width. */
6027 /* Get the operands in the appropriate modes and emit the instruction. */
6033 }
6035 static bool
6037 {
6042 }
6044 /* Subroutine of aarch64_pass_by_reference for arguments that are not
6045 passed in SVE registers. */
6047 static bool
6050 {
6051 HOST_WIDE_INT size;
6052 machine_mode dummymode;
6055 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
6058 else
6059 /* No frontends can create types with variable-sized modes, so we
6060 shouldn't be asked to pass or return them. */
6063 /* Aggregates are passed by reference based on their size. */
6067 /* Variable sized arguments are always returned by reference. */
6071 /* Can this be a candidate to be passed in fp/simd register(s)? */
6077 /* Arguments which are variable sized or larger than 2 registers are
6078 passed by reference unless they are a homogenous floating point
6079 aggregate. */
6081 }
6083 /* Implement TARGET_PASS_BY_REFERENCE. */
6085 static bool
6088 {
6094 pure_scalable_type_info pst_info;
6096 {
6099 /* We can't gracefully recover at this point, so make this a
6100 fatal error. */
6104 /* Variadic SVE types are passed by reference. Normal non-variadic
6105 arguments are too if we've run out of registers. */
6117 }
6119 }
6121 /* Return TRUE if VALTYPE is padded to its least significant bits. */
6122 static bool
6124 {
6125 machine_mode dummy_mode;
6128 /* Never happens in little-endian mode. */
6132 /* Only composite types smaller than or equal to 16 bytes can
6133 be potentially returned in registers. */
6139 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
6140 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
6141 is always passed/returned in the least significant bits of fp/simd
6142 register(s). */
6148 /* Likewise pure scalable types for SVE vector and predicate registers. */
6149 pure_scalable_type_info pst_info;
6154 }
6156 /* Implement TARGET_FUNCTION_VALUE.
6157 Define how to find the value returned by a function. */
6159 static rtx
6162 {
6163 machine_mode mode;
6170 pure_scalable_type_info pst_info;
6174 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
6175 are returned in memory, not by value. */
6180 {
6184 {
6187 }
6188 }
6191 machine_mode ag_mode;
6194 {
6197 {
6200 }
6201 else
6202 {
6204 rtx par;
6208 {
6213 }
6215 }
6216 }
6217 else
6218 {
6220 {
6221 /* Vector types can acquire a partial SVE mode using things like
6222 __attribute__((vector_size(N))), and this is potentially useful.
6223 However, the choice of mode doesn't affect the type's ABI
6224 identity, so we should treat the types as though they had
6225 the associated integer mode, just like they did before SVE
6226 was introduced.
6228 We know that the vector must be 128 bits or smaller,
6229 otherwise we'd have returned it in memory instead. */
6238 }
6240 }
6241 }
6243 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
6244 Return true if REGNO is the number of a hard register in which the values
6245 of called function may come back. */
6247 static bool
6249 {
6250 /* Maximum of 16 bytes can be returned in the general registers. Examples
6251 of 16-byte return values are: 128-bit integers and 16-byte small
6252 structures (excluding homogeneous floating-point aggregates). */
6256 /* Up to four fp/simd registers can return a function value, e.g. a
6257 homogeneous floating-point aggregate having four members. */
6262 }
6264 /* Subroutine for aarch64_return_in_memory for types that are not returned
6265 in SVE registers. */
6267 static bool
6269 {
6270 HOST_WIDE_INT size;
6271 machine_mode ag_mode;
6277 /* Simple scalar types always returned in registers. */
6284 /* Types larger than 2 registers returned in memory. */
6287 }
6289 /* Implement TARGET_RETURN_IN_MEMORY.
6291 If the type T of the result of a function is such that
6292 void func (T arg)
6293 would require that arg be passed as a value in a register (or set of
6294 registers) according to the parameter passing rules, then the result
6295 is returned in the same registers as would be used for such an
6296 argument. */
6298 static bool
6300 {
6301 pure_scalable_type_info pst_info;
6303 {
6315 }
6317 }
6319 static bool
6322 {
6327 }
6329 /* Given MODE and TYPE of a function argument, return the alignment in
6330 bits. The idea is to suppress any stronger alignment requested by
6331 the user and opt for the natural alignment (specified in AAPCS64 \S
6332 4.1). ABI_BREAK is set to true if the alignment was incorrectly
6333 calculated in versions of GCC prior to GCC-9. This is a helper
6334 function for local use only. */
6336 static unsigned int
6339 {
6359 {
6360 /* Note that we explicitly consider zero-sized fields here,
6361 even though they don't map to AAPCS64 machine types.
6362 For example, in:
6364 struct __attribute__((aligned(8))) empty {};
6366 struct s {
6367 [[no_unique_address]] empty e;
6368 int x;
6369 };
6371 "s" contains only one Fundamental Data Type (the int field)
6372 but gains 8-byte alignment and size thanks to "e". */
6375 bitfield_alignment
6378 }
6381 {
6384 }
6387 }
6389 /* Layout a function argument according to the AAPCS64 rules. The rule
6390 numbers refer to the rule numbers in the AAPCS64. ORIG_MODE is the
6391 mode that was originally given to us by the target hook, whereas the
6392 mode in ARG might be the result of replacing partial SVE modes with
6393 the equivalent integer mode. */
6395 static void
6397 {
6403 HOST_WIDE_INT size;
6406 /* We need to do this once per argument. */
6412 pure_scalable_type_info pst_info;
6414 {
6415 /* The PCS says that it is invalid to pass an SVE value to an
6416 unprototyped function. There is no ABI-defined location we
6417 can return in this case, so we have no real choice but to raise
6418 an error immediately, even though this is only a query function. */
6420 {
6424 /* Avoid repeating the message, and avoid tripping the assert
6425 below. */
6427 }
6429 /* We would have converted the argument into pass-by-reference
6430 form if it didn't fit in registers. */
6440 }
6442 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
6443 are passed by reference, not by value. */
6447 /* Vector types can acquire a partial SVE mode using things like
6448 __attribute__((vector_size(N))), and this is potentially useful.
6449 However, the choice of mode doesn't affect the type's ABI
6450 identity, so we should treat the types as though they had
6451 the associated integer mode, just like they did before SVE
6452 was introduced.
6454 We know that the vector must be 128 bits or smaller,
6455 otherwise we'd have passed it in memory instead. */
6460 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
6463 else
6464 /* No frontends can create types with variable-sized modes, so we
6465 shouldn't be asked to pass or return them. */
6471 mode,
6472 type,
6476 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
6477 The following code thus handles passing by SIMD/FP registers first. */
6481 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
6482 and homogenous short-vector aggregates (HVA). */
6484 {
6489 {
6492 {
6495 }
6496 else
6497 {
6498 rtx par;
6502 {
6505 rtx offset = gen_int_mode
6509 }
6511 }
6513 }
6514 else
6515 {
6516 /* C.3 NSRN is set to 8. */
6519 }
6520 }
6525 /* C6 - C9. though the sign and zero extension semantics are
6526 handled elsewhere. This is the case where the argument fits
6527 entirely general registers. */
6529 {
6532 /* C.8 if the argument has an alignment of 16 then the NGRN is
6533 rounded up to the next even number. */
6536 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
6537 comparison is there because for > 16 * BITS_PER_UNIT
6538 alignment nregs should be > 2 and therefore it should be
6539 passed by reference rather than value. */
6542 {
6548 }
6550 /* If an argument with an SVE mode needs to be shifted up to the
6551 high part of the register, treat it as though it had an integer mode.
6552 Using the normal (parallel [...]) would suppress the shifting. */
6554 && BYTES_BIG_ENDIAN
6557 {
6560 }
6562 /* NREGS can be 0 when e.g. an empty structure is to be passed.
6563 A reg is still generated for it, but the caller should be smart
6564 enough not to use it. */
6569 else
6570 {
6571 rtx par;
6576 {
6584 }
6586 }
6590 }
6592 /* C.11 */
6595 /* The argument is passed on stack; record the needed number of words for
6596 this argument and align the total size if necessary. */
6597 on_stack:
6602 {
6605 {
6610 }
6611 }
6613 }
6615 /* Implement TARGET_FUNCTION_ARG. */
6617 static rtx
6619 {
6630 }
6632 void
6634 const_tree fntype,
6635 rtx libname ATTRIBUTE_UNUSED,
6636 const_tree fndecl ATTRIBUTE_UNUSED,
6639 {
6648 else
6657 && !TARGET_FLOAT
6659 {
6666 }
6669 && !TARGET_SVE
6671 {
6672 /* We can't gracefully recover at this point, so make this a
6673 fatal error. */
6676 fndecl);
6677 else
6680 }
6681 }
6683 static void
6686 {
6691 {
6702 }
6703 }
6705 bool
6707 {
6710 }
6712 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
6713 PARM_BOUNDARY bits of alignment, but will be given anything up
6714 to STACK_BOUNDARY bits if the type requires it. This makes sure
6715 that both before and after the layout of each argument, the Next
6716 Stacked Argument Address (NSAA) will have a minimum alignment of
6717 8 bytes. */
6719 static unsigned int
6721 {
6727 {
6732 }
6735 }
6737 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
6739 static fixed_size_mode
6741 {
6743 /* Don't use the SVE part of the register for __builtin_apply and
6744 __builtin_return. The SVE registers aren't used by the normal PCS,
6745 so using them there would be a waste of time. The PCS extensions
6746 for SVE types are fundamentally incompatible with the
6747 __builtin_return/__builtin_apply interface. */
6750 }
6752 /* Implement TARGET_FUNCTION_ARG_PADDING.
6754 Small aggregate types are placed in the lowest memory address.
6756 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
6758 static pad_direction
6760 {
6761 /* On little-endian targets, the least significant byte of every stack
6762 argument is passed at the lowest byte address of the stack slot. */
6766 /* Otherwise, integral, floating-point and pointer types are padded downward:
6767 the least significant byte of a stack argument is passed at the highest
6768 byte address of the stack slot. */
6775 /* Everything else padded upward, i.e. data in first byte of stack slot. */
6777 }
6779 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
6781 It specifies padding for the last (may also be the only)
6782 element of a block move between registers and memory. If
6783 assuming the block is in the memory, padding upward means that
6784 the last element is padded after its highest significant byte,
6785 while in downward padding, the last element is padded at the
6786 its least significant byte side.
6788 Small aggregates and small complex types are always padded
6789 upwards.
6791 We don't need to worry about homogeneous floating-point or
6792 short-vector aggregates; their move is not affected by the
6793 padding direction determined here. Regardless of endianness,
6794 each element of such an aggregate is put in the least
6795 significant bits of a fp/simd register.
6797 Return !BYTES_BIG_ENDIAN if the least significant byte of the
6798 register has useful data, and return the opposite if the most
6799 significant byte does. */
6801 bool
6804 {
6806 /* Aside from pure scalable types, small composite types are always
6807 padded upward. */
6809 {
6810 HOST_WIDE_INT size;
6813 else
6814 /* No frontends can create types with variable-sized modes, so we
6815 shouldn't be asked to pass or return them. */
6818 {
6819 pure_scalable_type_info pst_info;
6823 }
6824 }
6826 /* Otherwise, use the default padding. */
6828 }
6830 static scalar_int_mode
6832 {
6834 }
6836 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
6838 /* We use the 12-bit shifted immediate arithmetic instructions so values
6839 must be multiple of (1 << 12), i.e. 4096. */
6840 #define ARITH_FACTOR 4096
6842 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
6843 #error Cannot use simple address calculation for stack probing
6844 #endif
6846 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
6847 inclusive. These are offsets from the current stack pointer. */
6849 static void
6851 {
6852 HOST_WIDE_INT size;
6854 {
6857 }
6861 /* See the same assertion on PROBE_INTERVAL above. */
6864 /* See if we have a constant small number of probes to generate. If so,
6865 that's the easy case. */
6867 {
6874 }
6876 /* The run-time loop is made up of 8 insns in the generic case while the
6877 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
6879 {
6884 stack_pointer_rtx,
6888 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
6889 it exceeds SIZE. If only two probes are needed, this will not
6890 generate any code. Then probe at FIRST + SIZE. */
6892 {
6896 }
6900 {
6905 }
6906 else
6908 }
6910 /* Otherwise, do the same as above, but in a loop. Note that we must be
6911 extra careful with variables wrapping around because we might be at
6912 the very top (or the very bottom) of the address space and we have
6913 to be able to handle this case properly; in particular, we use an
6914 equality test for the loop condition. */
6915 else
6916 {
6919 /* Step 1: round SIZE to the previous multiple of the interval. */
6924 /* Step 2: compute initial and final value of the loop counter. */
6926 /* TEST_ADDR = SP + FIRST. */
6930 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
6933 {
6937 }
6938 else
6942 /* Step 3: the loop
6944 do
6945 {
6946 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
6947 probe at TEST_ADDR
6948 }
6949 while (TEST_ADDR != LAST_ADDR)
6951 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
6952 until it is equal to ROUNDED_SIZE. */
6957 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
6958 that SIZE is equal to ROUNDED_SIZE. */
6961 {
6965 {
6970 }
6971 else
6973 }
6974 }
6976 /* Make sure nothing is scheduled before we are done. */
6978 }
6980 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
6981 absolute addresses. */
6985 {
6992 /* Loop. */
6995 HOST_WIDE_INT stack_clash_probe_interval
6998 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
7000 HOST_WIDE_INT interval;
7003 else
7011 /* If doing stack clash protection then we probe up by the ABI specified
7012 amount. We do this because we're dropping full pages at a time in the
7013 loop. But if we're doing non-stack clash probing, probe at SP 0. */
7016 else
7019 /* Probe at TEST_ADDR. If we're inside the loop it is always safe to probe
7020 by this amount for each iteration. */
7023 /* Test if TEST_ADDR == LAST_ADDR. */
7027 /* Branch. */
7033 }
7035 /* Emit the probe loop for doing stack clash probes and stack adjustments for
7036 SVE. This emits probes from BASE to BASE - ADJUSTMENT based on a guard size
7037 of GUARD_SIZE. When a probe is emitted it is done at most
7038 MIN_PROBE_THRESHOLD bytes from the current BASE at an interval of
7039 at most MIN_PROBE_THRESHOLD. By the end of this function
7040 BASE = BASE - ADJUSTMENT. */
7045 {
7046 /* This function is not allowed to use any instruction generation function
7047 like gen_ and friends. If you do you'll likely ICE during CFG validation,
7048 so instead emit the code you want using output_asm_insn. */
7053 /* The minimum required allocation before the residual requires probing. */
7056 /* Clamp the value down to the nearest value that can be used with a cmp. */
7071 /* Emit loop start label. */
7074 /* ADJUSTMENT < RESIDUAL_PROBE_GUARD. */
7079 /* Branch to end if not enough adjustment to probe. */
7084 /* BASE = BASE - RESIDUAL_PROBE_GUARD. */
7089 /* Probe at BASE. */
7093 /* ADJUSTMENT = ADJUSTMENT - RESIDUAL_PROBE_GUARD. */
7098 /* Branch to start if still more bytes to allocate. */
7103 /* No probe leave. */
7106 /* BASE = BASE - ADJUSTMENT. */
7111 }
7113 /* Determine whether a frame chain needs to be generated. */
7114 static bool
7116 {
7117 /* Force a frame chain for EH returns so the return address is at FP+8. */
7121 /* A leaf function cannot have calls or write LR. */
7124 /* Don't use a frame chain in leaf functions if leaf frame pointers
7125 are disabled. */
7130 }
7132 /* Mark the registers that need to be saved by the callee and calculate
7133 the size of the callee-saved registers area and frame record (both FP
7134 and LR may be omitted). */
7135 static void
7137 {
7147 /* Adjust the outgoing arguments size if required. Keep it in sync with what
7148 the mid-end is doing. */
7151 #define SLOT_NOT_REQUIRED (-2)
7152 #define SLOT_REQUIRED (-1)
7158 /* First mark all the registers that really need to be saved... */
7162 /* ... that includes the eh data registers (if needed)... */
7167 /* ... and any callee saved register that dataflow says is live. */
7179 {
7184 }
7186 /* Big-endian SVE frames need a spare predicate register in order
7187 to save Z8-Z15. Decide which register they should use. Prefer
7188 an unused argument register if possible, so that we don't force P4
7189 to be saved unnecessarily. */
7193 {
7202 }
7210 /* With stack-clash, LR must be saved in non-leaf functions. The saving of
7211 LR counts as an implicit probe which allows us to maintain the invariant
7212 described in the comment at expand_prologue. */
7216 /* Now assign stack slots for the registers. Start with the predicate
7217 registers, since predicate LDR and STR have a relatively small
7218 offset range. These saves happen below the hard frame pointer. */
7221 {
7224 }
7227 {
7228 /* If we have any vector registers to save above the predicate registers,
7229 the offset of the vector register save slots need to be a multiple
7230 of the vector size. This lets us use the immediate forms of LDR/STR
7231 (or LD1/ST1 for big-endian).
7233 A vector register is 8 times the size of a predicate register,
7234 and we need to save a maximum of 12 predicate registers, so the
7235 first vector register will be at either #1, MUL VL or #2, MUL VL.
7237 If we don't have any vector registers to save, and we know how
7238 big the predicate save area is, we can just round it up to the
7239 next 16-byte boundary. */
7242 else
7243 {
7248 else
7250 }
7251 }
7253 /* If we need to save any SVE vector registers, add them next. */
7257 {
7260 }
7262 /* OFFSET is now the offset of the hard frame pointer from the bottom
7263 of the callee save area. */
7267 {
7268 /* FP and LR are placed in the linkage record. */
7274 }
7278 {
7285 }
7293 {
7294 /* If there is an alignment gap between integer and fp callee-saves,
7295 allocate the last fp register to it if possible. */
7297 && has_align_gap
7300 {
7303 }
7312 }
7320 poly_int64 above_outgoing_args
7325 frame.hard_fp_offset
7328 /* Both these values are already aligned. */
7348 HOST_WIDE_INT const_saved_regs_size;
7352 {
7353 /* Simple, small frame with no outgoing arguments:
7355 stp reg1, reg2, [sp, -frame_size]!
7356 stp reg3, reg4, [sp, 16] */
7358 }
7362 /* We could handle this case even with outgoing args, provided
7363 that the number of args left us with valid offsets for all
7364 predicate and vector save slots. It's such a rare case that
7365 it hardly seems worth the effort though. */
7370 {
7371 /* Frame with small outgoing arguments:
7373 sub sp, sp, frame_size
7374 stp reg1, reg2, [sp, outgoing_args_size]
7375 stp reg3, reg4, [sp, outgoing_args_size + 16] */
7378 }
7382 {
7383 /* Frame in which all saves are SVE saves:
7385 sub sp, sp, hard_fp_offset + below_hard_fp_saved_regs_size
7386 save SVE registers relative to SP
7387 sub sp, sp, outgoing_args_size */
7391 }
7394 {
7395 /* Frame with large outgoing arguments or SVE saves, but with
7396 a small local area:
7398 stp reg1, reg2, [sp, -hard_fp_offset]!
7399 stp reg3, reg4, [sp, 16]
7400 [sub sp, sp, below_hard_fp_saved_regs_size]
7401 [save SVE registers relative to SP]
7402 sub sp, sp, outgoing_args_size */
7406 }
7407 else
7408 {
7409 /* Frame with large local area and outgoing arguments or SVE saves,
7410 using frame pointer:
7412 sub sp, sp, hard_fp_offset
7413 stp x29, x30, [sp, 0]
7414 add x29, sp, 0
7415 stp reg3, reg4, [sp, 16]
7416 [sub sp, sp, below_hard_fp_saved_regs_size]
7417 [save SVE registers relative to SP]
7418 sub sp, sp, outgoing_args_size */
7422 }
7424 /* Make sure the individual adjustments add up to the full frame size. */
7431 {
7432 /* We've decided not to associate any register saves with the initial
7433 stack allocation. */
7436 }
7439 }
7441 /* Return true if the register REGNO is saved on entry to
7442 the current function. */
7444 static bool
7446 {
7448 }
7450 /* Return the next register up from REGNO up to LIMIT for the callee
7451 to save. */
7453 static unsigned
7455 {
7457 regno ++;
7459 }
7461 /* Push the register number REGNO of mode MODE to the stack with write-back
7462 adjusting the stack by ADJUSTMENT. */
7464 static void
7466 HOST_WIDE_INT adjustment)
7467 {
7478 }
7480 /* Generate and return an instruction to store the pair of registers
7481 REG and REG2 of mode MODE to location BASE with write-back adjusting
7482 the stack location BASE by ADJUSTMENT. */
7484 static rtx
7486 HOST_WIDE_INT adjustment)
7487 {
7489 {
7504 }
7505 }
7507 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
7508 stack pointer by ADJUSTMENT. */
7510 static void
7512 {
7527 }
7529 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
7530 adjusting it by ADJUSTMENT afterwards. */
7532 static rtx
7534 HOST_WIDE_INT adjustment)
7535 {
7537 {
7549 }
7550 }
7552 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
7553 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
7554 into CFI_OPS. */
7556 static void
7559 {
7566 {
7570 }
7571 else
7572 {
7577 }
7578 }
7580 /* Generate and return a store pair instruction of mode MODE to store
7581 register REG1 to MEM1 and register REG2 to MEM2. */
7583 static rtx
7585 rtx reg2)
7586 {
7588 {
7606 }
7607 }
7609 /* Generate and regurn a load pair isntruction of mode MODE to load register
7610 REG1 from MEM1 and register REG2 from MEM2. */
7612 static rtx
7614 rtx mem2)
7615 {
7617 {
7632 }
7633 }
7635 /* Return TRUE if return address signing should be enabled for the current
7636 function, otherwise return FALSE. */
7638 bool
7640 {
7641 /* This function should only be called after frame laid out. */
7644 /* Turn return address signing off in any function that uses
7645 __builtin_eh_return. The address passed to __builtin_eh_return
7646 is not signed so either it has to be signed (with original sp)
7647 or the code path that uses it has to avoid authenticating it.
7648 Currently eh return introduces a return to anywhere gadget, no
7649 matter what we do here since it uses ret with user provided
7650 address. An ideal fix for that is to use indirect branch which
7651 can be protected with BTI j (to some extent). */
7655 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
7656 if its LR is pushed onto stack. */
7660 }
7662 /* Return TRUE if Branch Target Identification Mechanism is enabled. */
7663 bool
7665 {
7667 }
7669 /* The caller is going to use ST1D or LD1D to save or restore an SVE
7670 register in mode MODE at BASE_RTX + OFFSET, where OFFSET is in
7671 the range [1, 16] * GET_MODE_SIZE (MODE). Prepare for this by:
7673 (1) updating BASE_RTX + OFFSET so that it is a legitimate ST1D
7674 or LD1D address
7676 (2) setting PRED to a valid predicate register for the ST1D or LD1D,
7677 if the variable isn't already nonnull
7679 (1) is needed when OFFSET is in the range [8, 16] * GET_MODE_SIZE (MODE).
7680 Handle this case using a temporary base register that is suitable for
7681 all offsets in that range. Use ANCHOR_REG as this base register if it
7682 is nonnull, otherwise create a new register and store it in ANCHOR_REG. */
7688 {
7690 {
7691 /* This is the maximum valid offset of the anchor from the base.
7692 Lower values would be valid too. */
7695 {
7699 }
7702 }
7704 {
7709 }
7710 }
7712 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
7713 is saved at BASE + OFFSET. */
7715 static void
7718 {
7722 }
7724 /* Emit code to save the callee-saved registers from register number START
7725 to LIMIT to the stack at the location starting at offset START_OFFSET,
7726 skipping any write-back candidates if SKIP_WB is true. HARD_FP_VALID_P
7727 is true if the hard frame pointer has been set up. */
7729 static void
7733 {
7742 {
7744 poly_int64 offset;
7761 HOST_WIDE_INT const_offset;
7767 {
7769 poly_int64 fp_offset
7773 else
7774 {
7776 {
7780 }
7782 }
7784 }
7794 {
7796 rtx mem2;
7801 reg2));
7803 /* The first part of a frame-related parallel insn is
7804 always assumed to be relevant to the frame
7805 calculations; subsequent parts, are only
7806 frame-related if explicitly marked. */
7808 {
7812 else
7814 }
7817 }
7819 {
7822 }
7825 else
7831 }
7832 }
7834 /* Emit code to restore the callee registers from register number START
7835 up to and including LIMIT. Restore from the stack offset START_OFFSET,
7836 skipping any write-back candidates if SKIP_WB is true. Write the
7837 appropriate REG_CFA_RESTORE notes into CFI_OPS. */
7839 static void
7842 {
7845 poly_int64 offset;
7851 {
7878 {
7880 rtx mem2;
7888 }
7893 else
7897 }
7898 }
7900 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
7901 of MODE. */
7905 {
7906 HOST_WIDE_INT multiple;
7909 }
7911 /* Return true if OFFSET is a signed 6-bit value multiplied by the size
7912 of MODE. */
7916 {
7917 HOST_WIDE_INT multiple;
7920 }
7922 /* Return true if OFFSET is an unsigned 6-bit value multiplied by the size
7923 of MODE. */
7927 {
7928 HOST_WIDE_INT multiple;
7931 }
7933 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
7934 of MODE. */
7936 bool
7938 {
7939 HOST_WIDE_INT multiple;
7942 }
7944 /* Return true if OFFSET is a signed 9-bit value. */
7946 bool
7948 poly_int64 offset)
7949 {
7950 HOST_WIDE_INT const_offset;
7953 }
7955 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
7956 of MODE. */
7960 {
7961 HOST_WIDE_INT multiple;
7964 }
7966 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
7967 of MODE. */
7971 {
7972 HOST_WIDE_INT multiple;
7975 }
7977 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
7979 static sbitmap
7981 {
7985 /* The registers we need saved to the frame. */
7988 {
7989 /* Punt on saves and restores that use ST1D and LD1D. We could
7990 try to be smarter, but it would involve making sure that the
7991 spare predicate register itself is safe to use at the save
7992 and restore points. Also, when a frame pointer is being used,
7993 the slots are often out of reach of ST1D and LD1D anyway. */
8000 /* If the register is saved in the first SVE save slot, we use
8001 it as a stack probe for -fstack-clash-protection. */
8007 /* Get the offset relative to the register we'll use. */
8010 else
8013 /* Check that we can access the stack slot of the register with one
8014 direct load with no adjustments needed. */
8019 }
8021 /* Don't mess with the hard frame pointer. */
8025 /* If the spare predicate register used by big-endian SVE code
8026 is call-preserved, it must be saved in the main prologue
8027 before any saves that use it. */
8033 /* If registers have been chosen to be stored/restored with
8034 writeback don't interfere with them to avoid having to output explicit
8035 stack adjustment instructions. */
8045 }
8047 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
8049 static sbitmap
8051 {
8059 /* Clobbered registers don't generate values in any meaningful sense,
8060 since nothing after the clobber can rely on their value. And we can't
8061 say that partially-clobbered registers are unconditionally killed,
8062 because whether they're killed or not depends on the mode of the
8063 value they're holding. Thus partially call-clobbered registers
8064 appear in neither the kill set nor the gen set.
8066 Check manually for any calls that clobber more of a register than the
8067 current function can. */
8068 function_abi_aggregator callee_abis;
8075 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
8083 {
8086 /* If there is a callee-save at an adjacent offset, add it too
8087 to increase the use of LDP/STP. */
8092 {
8098 }
8099 }
8102 }
8104 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
8105 Nothing to do for aarch64. */
8107 static void
8109 {
8110 }
8112 /* Return the next set bit in BMP from START onwards. Return the total number
8113 of bits in BMP if no set bit is found at or after START. */
8115 static unsigned int
8117 {
8128 }
8130 /* Do the work for aarch64_emit_prologue_components and
8131 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
8132 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
8133 for these components or the epilogue sequence. That is, it determines
8134 whether we should emit stores or loads and what kind of CFA notes to attach
8135 to the insns. Otherwise the logic for the two sequences is very
8136 similar. */
8138 static void
8140 {
8142 ? HARD_FRAME_POINTER_REGNUM
8150 {
8158 else
8166 /* No more registers to handle after REGNO.
8167 Emit a single save/restore and exit. */
8169 {
8172 {
8176 else
8178 }
8180 }
8183 /* The next register is not of the same class or its offset is not
8184 mergeable with the current one into a pair. */
8191 {
8194 {
8198 else
8200 }
8204 }
8208 /* REGNO2 can be saved/restored in a pair with REGNO. */
8212 else
8221 else
8225 {
8228 {
8233 }
8234 else
8235 {
8240 }
8241 }
8244 }
8245 }
8247 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
8249 static void
8251 {
8253 }
8255 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
8257 static void
8259 {
8261 }
8263 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
8265 static void
8267 {
8271 }
8273 /* On AArch64 we have an ABI defined safe buffer. This constant is used to
8274 determining the probe offset for alloca. */
8276 static HOST_WIDE_INT
8278 {
8280 }
8283 /* Allocate POLY_SIZE bytes of stack space using TEMP1 and TEMP2 as scratch
8284 registers. If POLY_SIZE is not large enough to require a probe this function
8285 will only adjust the stack. When allocating the stack space
8286 FRAME_RELATED_P is then used to indicate if the allocation is frame related.
8287 FINAL_ADJUSTMENT_P indicates whether we are allocating the outgoing
8288 arguments. If we are then we ensure that any allocation larger than the ABI
8289 defined buffer needs a probe so that the invariant of having a 1KB buffer is
8290 maintained.
8292 We emit barriers after each stack adjustment to prevent optimizations from
8293 breaking the invariant that we never drop the stack more than a page. This
8294 invariant is needed to make it easier to correctly handle asynchronous
8295 events, e.g. if we were to allow the stack to be dropped by more than a page
8296 and then have multiple probes up and we take a signal somewhere in between
8297 then the signal handler doesn't know the state of the stack and can make no
8298 assumptions about which pages have been probed. */
8300 static void
8302 poly_int64 poly_size,
8305 {
8306 HOST_WIDE_INT guard_size
8309 HOST_WIDE_INT min_probe_threshold
8310 = (final_adjustment_p
8311 ? guard_used_by_caller
8313 /* When doing the final adjustment for the outgoing arguments, take into
8314 account any unprobed space there is above the current SP. There are
8315 two cases:
8317 - When saving SVE registers below the hard frame pointer, we force
8318 the lowest save to take place in the prologue before doing the final
8319 adjustment (i.e. we don't allow the save to be shrink-wrapped).
8320 This acts as a probe at SP, so there is no unprobed space.
8322 - When there are no SVE register saves, we use the store of the link
8323 register as a probe. We can't assume that LR was saved at position 0
8324 though, so treat any space below it as unprobed. */
8327 {
8331 else
8333 }
8337 /* We should always have a positive probe threshold. */
8341 {
8347 {
8349 }
8353 {
8355 }
8356 }
8358 /* If SIZE is not large enough to require probing, just adjust the stack and
8359 exit. */
8362 {
8365 }
8367 HOST_WIDE_INT size;
8368 /* Handle the SVE non-constant case first. */
8370 {
8372 {
8376 }
8378 /* First calculate the amount of bytes we're actually spilling. */
8385 {
8386 /* This is done to provide unwinding information for the stack
8387 adjustments we're about to do, however to prevent the optimizers
8388 from removing the R11 move and leaving the CFA note (which would be
8389 very wrong) we tie the old and new stack pointer together.
8390 The tie will expand to nothing but the optimizers will not touch
8391 the instruction. */
8396 /* We want the CFA independent of the stack pointer for the
8397 duration of the loop. */
8400 }
8409 /* Now reset the CFA register if needed. */
8411 {
8416 }
8419 }
8423 "Stack clash AArch64 prologue: " HOST_WIDE_INT_PRINT_DEC
8426 /* Round size to the nearest multiple of guard_size, and calculate the
8427 residual as the difference between the original size and the rounded
8428 size. */
8432 /* We can handle a small number of allocations/probes inline. Otherwise
8433 punt to a loop. */
8435 {
8437 {
8440 guard_used_by_caller));
8442 }
8444 }
8445 else
8446 {
8447 /* Compute the ending address. */
8452 /* For the initial allocation, we don't have a frame pointer
8453 set up, so we always need CFI notes. If we're doing the
8454 final allocation, then we may have a frame pointer, in which
8455 case it is the CFA, otherwise we need CFI notes.
8457 We can determine which allocation we are doing by looking at
8458 the value of FRAME_RELATED_P since the final allocations are not
8459 frame related. */
8461 {
8462 /* We want the CFA independent of the stack pointer for the
8463 duration of the loop. */
8467 }
8469 /* This allocates and probes the stack. Note that this re-uses some of
8470 the existing Ada stack protection code. However we are guaranteed not
8471 to enter the non loop or residual branches of that code.
8473 The non-loop part won't be entered because if our allocation amount
8474 doesn't require a loop, the case above would handle it.
8476 The residual amount won't be entered because TEMP1 is a mutliple of
8477 the allocation size. The residual will always be 0. As such, the only
8478 part we are actually using from that code is the loop setup. The
8479 actual probing is done in aarch64_output_probe_stack_range. */
8483 /* Now reset the CFA register if needed. */
8485 {
8489 }
8493 }
8495 /* Handle any residuals. Residuals of at least MIN_PROBE_THRESHOLD have to
8496 be probed. This maintains the requirement that each page is probed at
8497 least once. For initial probing we probe only if the allocation is
8498 more than GUARD_SIZE - buffer, and for the outgoing arguments we probe
8499 if the amount is larger than buffer. GUARD_SIZE - buffer + buffer ==
8500 GUARD_SIZE. This works that for any allocation that is large enough to
8501 trigger a probe here, we'll have at least one, and if they're not large
8502 enough for this code to emit anything for them, The page would have been
8503 probed by the saving of FP/LR either by this function or any callees. If
8504 we don't have any callees then we won't have more stack adjustments and so
8505 are still safe. */
8507 {
8509 /* If we're doing final adjustments, and we've done any full page
8510 allocations then any residual needs to be probed. */
8513 /* If doing a small final adjustment, we always probe at offset 0.
8514 This is done to avoid issues when LR is not at position 0 or when
8515 the final adjustment is smaller than the probing offset. */
8521 {
8524 "Stack clash AArch64 prologue residuals: "
8525 HOST_WIDE_INT_PRINT_DEC " bytes, probing will be required."
8529 residual_probe_offset));
8531 }
8532 }
8533 }
8535 /* Return 1 if the register is used by the epilogue. We need to say the
8536 return register is used, but only after epilogue generation is complete.
8537 Note that in the case of sibcalls, the values "used by the epilogue" are
8538 considered live at the start of the called function.
8540 For SIMD functions we need to return 1 for FP registers that are saved and
8541 restored by a function but are not zero in call_used_regs. If we do not do
8542 this optimizations may remove the restore of the register. */
8544 int
8546 {
8548 {
8551 }
8553 }
8555 /* AArch64 stack frames generated by this compiler look like:
8557 +-------------------------------+
8558 | |
8559 | incoming stack arguments |
8560 | |
8561 +-------------------------------+
8562 | | <-- incoming stack pointer (aligned)
8563 | callee-allocated save area |
8564 | for register varargs |
8565 | |
8566 +-------------------------------+
8567 | local variables | <-- frame_pointer_rtx
8568 | |
8569 +-------------------------------+
8570 | padding | \
8571 +-------------------------------+ |
8572 | callee-saved registers | | frame.saved_regs_size
8573 +-------------------------------+ |
8574 | LR' | |
8575 +-------------------------------+ |
8576 | FP' | |
8577 +-------------------------------+ |<- hard_frame_pointer_rtx (aligned)
8578 | SVE vector registers | | \
8579 +-------------------------------+ | | below_hard_fp_saved_regs_size
8580 | SVE predicate registers | / /
8581 +-------------------------------+
8582 | dynamic allocation |
8583 +-------------------------------+
8584 | padding |
8585 +-------------------------------+
8586 | outgoing stack arguments | <-- arg_pointer
8587 | |
8588 +-------------------------------+
8589 | | <-- stack_pointer_rtx (aligned)
8591 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
8592 but leave frame_pointer_rtx and hard_frame_pointer_rtx
8593 unchanged.
8595 By default for stack-clash we assume the guard is at least 64KB, but this
8596 value is configurable to either 4KB or 64KB. We also force the guard size to
8597 be the same as the probing interval and both values are kept in sync.
8599 With those assumptions the callee can allocate up to 63KB (or 3KB depending
8600 on the guard size) of stack space without probing.
8602 When probing is needed, we emit a probe at the start of the prologue
8603 and every PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE bytes thereafter.
8605 We have to track how much space has been allocated and the only stores
8606 to the stack we track as implicit probes are the FP/LR stores.
8608 For outgoing arguments we probe if the size is larger than 1KB, such that
8609 the ABI specified buffer is maintained for the next callee.
8611 The following registers are reserved during frame layout and should not be
8612 used for any other purpose:
8614 - r11: Used by stack clash protection when SVE is enabled, and also
8615 as an anchor register when saving and restoring registers
8616 - r12(EP0) and r13(EP1): Used as temporaries for stack adjustment.
8617 - r14 and r15: Used for speculation tracking.
8618 - r16(IP0), r17(IP1): Used by indirect tailcalls.
8619 - r30(LR), r29(FP): Used by standard frame layout.
8621 These registers must be avoided in frame layout related code unless the
8622 explicit intention is to interact with one of the features listed above. */
8624 /* Generate the prologue instructions for entry into a function.
8625 Establish the stack frame by decreasing the stack pointer with a
8626 properly calculated size and, if necessary, create a frame record
8627 filled with the values of LR and previous frame pointer. The
8628 current FP is also set up if it is in use. */
8630 void
8632 {
8639 poly_int64 below_hard_fp_saved_regs_size
8647 {
8648 /* Fold the SVE allocation into the initial allocation.
8649 We don't do this in aarch64_layout_arg to avoid pessimizing
8650 the epilogue code. */
8653 }
8655 /* Sign return address for functions. */
8657 {
8659 {
8668 }
8671 }
8677 {
8679 {
8683 (frame_size
8685 }
8688 }
8693 /* In theory we should never have both an initial adjustment
8694 and a callee save adjustment. Verify that is the case since the
8695 code below does not handle it for -fstack-clash-protection. */
8698 /* Will only probe if the initial adjustment is larger than the guard
8699 less the amount of the guard reserved for use by the caller's
8700 outgoing args. */
8707 /* The offset of the frame chain record (if any) from the current SP. */
8712 /* The offset of the bottom of the save area from the current SP. */
8716 {
8718 {
8723 }
8724 else
8730 {
8731 /* Variable-sized frames need to describe the save slot
8732 address using DW_CFA_expression rather than DW_CFA_offset.
8733 This means that, without taking further action, the
8734 locations of the registers that we've already saved would
8735 remain based on the stack pointer even after we redefine
8736 the CFA based on the frame pointer. We therefore need new
8737 DW_CFA_expressions to re-express the save slots with addresses
8738 based on the frame pointer. */
8742 /* Add an explicit CFA definition if this was previously
8743 implicit. */
8745 {
8747 callee_offset);
8750 }
8752 /* Change the save slot expressions for the registers that
8753 we've already saved. */
8758 }
8760 }
8764 emit_frame_chain);
8766 {
8770 sve_callee_adjust,
8773 }
8778 emit_frame_chain);
8780 /* We may need to probe the final adjustment if it is larger than the guard
8781 that is assumed by the called. */
8784 }
8786 /* Return TRUE if we can use a simple_return insn.
8788 This function checks whether the callee saved stack is empty, which
8789 means no restore actions are need. The pro_and_epilogue will use
8790 this to check whether shrink-wrapping opt is feasible. */
8792 bool
8794 {
8802 }
8804 /* Generate the epilogue instructions for returning from a function.
8805 This is almost exactly the reverse of the prolog sequence, except
8806 that we need to insert barriers to avoid scheduling loads that read
8807 from a deallocated stack, and we optimize the unwind records by
8808 emitting them all together if possible. */
8809 void
8811 {
8817 poly_int64 below_hard_fp_saved_regs_size
8823 /* A stack clash protection prologue may not have left EP0_REGNUM or
8824 EP1_REGNUM in a usable state. The same is true for allocations
8825 with an SVE component, since we then need both temporary registers
8826 for each allocation. For stack clash we are in a usable state if
8827 the adjustment is less than GUARD_SIZE - GUARD_USED_BY_CALLER. */
8828 HOST_WIDE_INT guard_size
8832 /* We can re-use the registers when:
8834 (a) the deallocation amount is the same as the corresponding
8835 allocation amount (which is false if we combine the initial
8836 and SVE callee save allocations in the prologue); and
8838 (b) the allocation amount doesn't need a probe (which is false
8839 if the amount is guard_size - guard_used_by_caller or greater).
8841 In such situations the register should remain live with the correct
8842 value. */
8845 && (!flag_stack_clash_protection
8850 /* We need to add memory barrier to prevent read from deallocated stack. */
8851 bool need_barrier_p
8855 /* Emit a barrier to prevent loads from a deallocated stack. */
8859 {
8862 }
8864 /* Restore the stack pointer from the frame pointer if it may not
8865 be the same as the stack pointer. */
8870 /* If writeback is used when restoring callee-saves, the CFA
8871 is restored on the instruction doing the writeback. */
8873 hard_frame_pointer_rtx,
8876 else
8877 /* The case where we need to re-use the register here is very rare, so
8878 avoid the complicated condition and just always emit a move if the
8879 immediate doesn't fit. */
8882 /* Restore the vector registers before the predicate registers,
8883 so that we can use P4 as a temporary for big-endian SVE frames. */
8900 /* If we have no register restore information, the CFA must have been
8901 defined in terms of the stack pointer since the end of the prologue. */
8905 {
8906 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
8912 }
8914 /* Liveness of EP0_REGNUM can not be trusted across function calls either, so
8915 add restriction on emit_move optimization to leaf functions. */
8921 {
8922 /* Emit delayed restores and reset the CFA to be SP. */
8927 }
8929 /* We prefer to emit the combined return/authenticate instruction RETAA,
8930 however there are three cases in which we must instead emit an explicit
8931 authentication instruction.
8933 1) Sibcalls don't return in a normal way, so if we're about to call one
8934 we must authenticate.
8936 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
8937 generating code for !TARGET_ARMV8_3 we can't use it and must
8938 explicitly authenticate.
8940 3) On an eh_return path we make extra stack adjustments to update the
8941 canonical frame address to be the exception handler's CFA. We want
8942 to authenticate using the CFA of the function which calls eh_return.
8943 */
8946 {
8948 {
8957 }
8960 }
8962 /* Stack adjustment for exception handler. */
8964 {
8965 /* We need to unwind the stack by the offset computed by
8966 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
8967 to be SP; letting the CFA move during this adjustment
8968 is just as correct as retaining the CFA from the body
8969 of the function. Therefore, do nothing special. */
8971 }
8976 }
8978 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
8979 normally or return to a previous frame after unwinding.
8981 An EH return uses a single shared return sequence. The epilogue is
8982 exactly like a normal epilogue except that it has an extra input
8983 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
8984 that must be applied after the frame has been destroyed. An extra label
8985 is inserted before the epilogue which initializes this register to zero,
8986 and this is the entry point for a normal return.
8988 An actual EH return updates the return address, initializes the stack
8989 adjustment and jumps directly into the epilogue (bypassing the zeroing
8990 of the adjustment). Since the return address is typically saved on the
8991 stack when a function makes a call, the saved LR must be updated outside
8992 the epilogue.
8994 This poses problems as the store is generated well before the epilogue,
8995 so the offset of LR is not known yet. Also optimizations will remove the
8996 store as it appears dead, even after the epilogue is generated (as the
8997 base or offset for loading LR is different in many cases).
8999 To avoid these problems this implementation forces the frame pointer
9000 in eh_return functions so that the location of LR is fixed and known early.
9001 It also marks the store volatile, so no optimization is permitted to
9002 remove the store. */
9003 rtx
9005 {
9009 /* Mark the store volatile, so no optimization is permitted to remove it. */
9012 }
9014 /* Output code to add DELTA to the first argument, and then jump
9015 to FUNCTION. Used for C++ multiple inheritance. */
9016 static void
9018 HOST_WIDE_INT delta,
9019 HOST_WIDE_INT vcall_offset,
9020 tree function)
9021 {
9022 /* The this pointer is always in x0. Note that this differs from
9023 Arm where the this pointer maybe bumped to r1 if r0 is required
9024 to return a pointer to an aggregate. On AArch64 a result value
9025 pointer will be in x8. */
9043 else
9044 {
9049 {
9053 else
9056 }
9060 else
9067 else
9068 {
9070 Pmode);
9072 }
9076 else
9082 }
9084 /* Generate a tail call to the target function. */
9086 {
9089 }
9105 /* Stop pretending to be a post-reload pass. */
9107 }
9109 static bool
9111 {
9116 {
9120 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
9121 TLS offsets, not real symbol references. */
9124 }
9126 }
9129 /* Return true if val can be encoded as a 12-bit unsigned immediate with
9130 a left shift of 0 or 12 bits. */
9131 bool
9133 {
9136 );
9137 }
9139 /* Returns the nearest value to VAL that will fit as a 12-bit unsigned immediate
9140 that can be created with a left shift of 0 or 12. */
9141 static HOST_WIDE_INT
9143 {
9144 /* Check to see if the value fits in 24 bits, as that is the maximum we can
9145 handle correctly. */
9152 }
9154 /* Return true if val is an immediate that can be loaded into a
9155 register by a MOVZ instruction. */
9156 static bool
9158 {
9160 {
9164 }
9165 else
9166 {
9167 /* Ignore sign extension. */
9169 }
9172 }
9174 /* Test whether:
9176 X = (X & AND_VAL) | IOR_VAL;
9178 can be implemented using:
9180 MOVK X, #(IOR_VAL >> shift), LSL #shift
9182 Return the shift if so, otherwise return -1. */
9183 int
9186 {
9190 {
9194 }
9196 }
9198 /* VAL is a value with the inner mode of MODE. Replicate it to fill a
9199 64-bit (DImode) integer. */
9201 static unsigned HOST_WIDE_INT
9203 {
9206 {
9210 }
9212 }
9214 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
9217 {
9223 };
9226 /* Return true if val is a valid bitmask immediate. */
9228 bool
9230 {
9234 /* Check for a single sequence of one bits and return quickly if so.
9235 The special cases of all ones and all zeroes returns false. */
9242 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
9246 /* Invert if the immediate doesn't start with a zero bit - this means we
9247 only need to search for sequences of one bits. */
9251 /* Find the first set bit and set tmp to val with the first sequence of one
9252 bits removed. Return success if there is a single sequence of ones. */
9259 /* Find the next set bit and compute the difference in bit position. */
9264 /* Check the bit position difference is a power of 2, and that the first
9265 sequence of one bits fits within 'bits' bits. */
9269 /* Check the sequence of one bits is repeated 64/bits times. */
9271 }
9273 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
9274 Assumed precondition: VAL_IN Is not zero. */
9276 unsigned HOST_WIDE_INT
9278 {
9285 }
9287 /* Create constant where bits outside of lowest bit set to highest bit set
9288 are set to 1. */
9290 unsigned HOST_WIDE_INT
9292 {
9294 }
9296 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
9298 bool
9300 {
9301 scalar_int_mode int_mode;
9314 }
9316 /* Return true if val is an immediate that can be loaded into a
9317 register in a single instruction. */
9318 bool
9320 {
9321 scalar_int_mode int_mode;
9328 }
9330 static bool
9332 {
9336 /* There's no way to calculate VL-based values using relocations. */
9342 poly_int64 offset;
9345 {
9346 /* We checked for POLY_INT_CST offsets above. */
9350 else
9351 /* Avoid generating a 64-bit relocation in ILP32; leave
9352 to aarch64_expand_mov_immediate to handle it properly. */
9354 }
9357 }
9359 /* Implement TARGET_CASE_VALUES_THRESHOLD.
9360 The expansion for a table switch is quite expensive due to the number
9361 of instructions, the table lookup and hard to predict indirect jump.
9362 When optimizing for speed, and -O3 enabled, use the per-core tuning if
9363 set, otherwise use tables for > 16 cases as a tradeoff between size and
9364 performance. When optimizing for size, use the default setting. */
9366 static unsigned int
9368 {
9369 /* Use the specified limit for the number of cases before using jump
9370 tables at higher optimization levels. */
9374 else
9376 }
9378 /* Return true if register REGNO is a valid index register.
9379 STRICT_P is true if REG_OK_STRICT is in effect. */
9381 bool
9383 {
9385 {
9393 }
9395 }
9397 /* Return true if register REGNO is a valid base register for mode MODE.
9398 STRICT_P is true if REG_OK_STRICT is in effect. */
9400 bool
9402 {
9404 {
9412 }
9414 /* The fake registers will be eliminated to either the stack or
9415 hard frame pointer, both of which are usually valid base registers.
9416 Reload deals with the cases where the eliminated form isn't valid. */
9421 }
9423 /* Return true if X is a valid base register for mode MODE.
9424 STRICT_P is true if REG_OK_STRICT is in effect. */
9426 static bool
9428 {
9435 }
9437 /* Return true if address offset is a valid index. If it is, fill in INFO
9438 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
9440 static bool
9443 {
9445 rtx index;
9448 /* (reg:P) */
9451 {
9455 }
9456 /* (sign_extend:DI (reg:SI)) */
9461 {
9466 }
9467 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
9474 {
9479 }
9480 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
9487 {
9492 }
9493 /* (and:DI (mult:DI (reg:DI) (const_int scale))
9494 (const_int 0xffffffff<<shift)) */
9501 {
9507 }
9508 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
9509 (const_int 0xffffffff<<shift)) */
9516 {
9522 }
9523 /* (mult:P (reg:P) (const_int scale)) */
9528 {
9532 }
9533 /* (ashift:P (reg:P) (const_int shift)) */
9538 {
9542 }
9543 else
9552 {
9556 }
9557 else
9558 {
9563 }
9567 {
9572 }
9575 }
9577 /* Return true if MODE is one of the modes for which we
9578 support LDP/STP operations. */
9580 static bool
9582 {
9590 }
9592 /* Return true if REGNO is a virtual pointer register, or an eliminable
9593 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
9594 include stack_pointer or hard_frame_pointer. */
9595 static bool
9597 {
9602 }
9604 /* Return true if X is a valid address of type TYPE for machine mode MODE.
9605 If it is, fill in INFO appropriately. STRICT_P is true if
9606 REG_OK_STRICT is in effect. */
9608 bool
9611 aarch64_addr_query_type type)
9612 {
9615 poly_int64 offset;
9617 HOST_WIDE_INT const_size;
9619 /* Whether a vector mode is partial doesn't affect address legitimacy.
9620 Partial vectors like VNx8QImode allow the same indexed addressing
9621 mode and MUL VL addressing mode as full vectors like VNx16QImode;
9622 in both cases, MUL VL counts multiples of GET_MODE_SIZE. */
9626 /* On BE, we use load/store pair for all large int mode load/stores.
9627 TI/TFmode may also use a load/store pair. */
9635 /* If we are dealing with ADDR_QUERY_LDP_STP_N that means the incoming mode
9636 corresponds to the actual size of the memory being loaded/stored and the
9637 mode of the corresponding addressing mode is half of that. */
9647 /* For SVE, only accept [Rn], [Rn, Rm, LSL #shift] and
9648 [Rn, #offset, MUL VL]. */
9653 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
9654 REG addressing. */
9656 && !BYTES_BIG_ENDIAN
9664 {
9681 {
9688 }
9693 {
9699 /* TImode and TFmode values are allowed in both pairs of X
9700 registers and individual Q registers. The available
9701 address modes are:
9702 X,X: 7-bit signed scaled offset
9703 Q: 9-bit signed offset
9704 We conservatively require an offset representable in either mode.
9705 When performing the check for pairs of X registers i.e. LDP/STP
9706 pass down DImode since that is the natural size of the LDP/STP
9707 instruction memory accesses. */
9713 /* A 7bit offset check because OImode will emit a ldp/stp
9714 instruction (only big endian will get here).
9715 For ldp/stp instructions, the offset is scaled for the size of a
9716 single element of the pair. */
9720 /* Three 9/12 bit offsets checks because CImode will emit three
9721 ldr/str instructions (only big endian will get here). */
9729 /* Two 7bit offsets checks because XImode will emit two ldp/stp
9730 instructions (only big endian will get here). */
9736 /* Make "m" use the LD1 offset range for SVE data modes, so
9737 that pre-RTL optimizers like ivopts will work to that
9738 instead of the wider LDR/STR range. */
9745 {
9746 poly_int64 end_offset = (offset
9753 end_offset)));
9754 }
9764 else
9767 }
9770 {
9771 /* Look for base + (scaled/extended) index register. */
9774 {
9777 }
9780 {
9783 }
9784 }
9805 {
9809 /* TImode and TFmode values are allowed in both pairs of X
9810 registers and individual Q registers. The available
9811 address modes are:
9812 X,X: 7-bit signed scaled offset
9813 Q: 9-bit signed offset
9814 We conservatively require an offset representable in either mode.
9815 */
9825 else
9827 }
9833 /* load literal: pc-relative constant pool entry. Only supported
9834 for SI mode or larger. */
9840 {
9841 poly_int64 offset;
9847 }
9856 {
9857 poly_int64 offset;
9858 HOST_WIDE_INT const_offset;
9864 {
9865 /* The symbol and offset must be aligned to the access size. */
9871 {
9875 }
9881 else
9890 }
9891 }
9896 }
9897 }
9899 /* Return true if the address X is valid for a PRFM instruction.
9900 STRICT_P is true if we should do strict checking with
9901 aarch64_classify_address. */
9903 bool
9905 {
9908 /* PRFM accepts the same addresses as DImode... */
9913 /* ... except writeback forms. */
9915 }
9917 bool
9919 {
9920 poly_int64 offset;
9923 }
9925 /* Classify the base of symbolic expression X. */
9927 enum aarch64_symbol_type
9929 {
9930 rtx offset;
9934 }
9937 /* Return TRUE if X is a legitimate address for accessing memory in
9938 mode MODE. */
9939 static bool
9941 {
9945 }
9947 /* Return TRUE if X is a legitimate address of type TYPE for accessing
9948 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
9949 bool
9951 aarch64_addr_query_type type)
9952 {
9956 }
9958 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
9960 static bool
9962 poly_int64 orig_offset,
9963 machine_mode mode)
9964 {
9965 HOST_WIDE_INT size;
9967 {
9970 /* A general SVE offset is A * VQ + B. Remove the A component from
9971 coefficient 0 in order to get the constant B. */
9974 /* Split an out-of-range address displacement into a base and
9975 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
9976 range otherwise to increase opportunities for sharing the base
9977 address of different sizes. Unaligned accesses use the signed
9978 9-bit range, TImode/TFmode use the intersection of signed
9979 scaled 7-bit and signed 9-bit offset. */
9984 else
9990 /* Split the offset into second_offset and the rest. */
9994 }
9995 else
9996 {
9997 /* Get the mode we should use as the basis of the range. For structure
9998 modes this is the mode of one vector. */
10000 machine_mode step_mode
10003 /* Get the "mul vl" multiplier we'd like to use. */
10007 /* LDR supports a 9-bit range, but the move patterns for
10008 structure modes require all vectors to be in range of the
10009 same base. The simplest way of accomodating that while still
10010 promoting reuse of anchor points between different modes is
10011 to use an 8-bit range unconditionally. */
10013 else
10014 /* Predicates are only handled singly, so we might as well use
10015 the full range. */
10020 /* Convert the "mul vl" multiplier into a byte offset. */
10025 /* Split the offset into second_offset and the rest. */
10029 }
10030 }
10032 /* Return the binary representation of floating point constant VALUE in INTVAL.
10033 If the value cannot be converted, return false without setting INTVAL.
10034 The conversion is done in the given MODE. */
10035 bool
10037 {
10039 /* We make a general exception for 0. */
10041 {
10044 }
10046 scalar_float_mode mode;
10050 /* Only support up to DF mode. */
10062 {
10066 }
10067 else
10072 }
10074 /* Return TRUE if rtx X is an immediate constant that can be moved using a
10075 single MOV(+MOVK) followed by an FMOV. */
10076 bool
10078 {
10083 /* Determine whether it's cheaper to write float constants as
10084 mov/movk pairs over ldr/adrp pairs. */
10090 {
10092 ? SImode
10097 }
10100 }
10102 /* Return TRUE if rtx X is immediate constant 0.0 */
10103 bool
10105 {
10112 }
10114 /* Return TRUE if rtx X is immediate constant that fits in a single
10115 MOVI immediate operation. */
10116 bool
10118 {
10122 machine_mode vmode;
10123 scalar_int_mode imode;
10128 {
10132 /* We make a general exception for 0. */
10137 }
10141 else
10144 /* use a 64 bit mode for everything except for DI/DF mode, where we use
10145 a 128 bit vector mode. */
10152 }
10155 /* Return the fixed registers used for condition codes. */
10157 static bool
10159 {
10163 }
10165 /* This function is used by the call expanders of the machine description.
10166 RESULT is the register in which the result is returned. It's NULL for
10167 "call" and "sibcall".
10168 MEM is the location of the function call.
10169 CALLEE_ABI is a const_int that gives the arm_pcs of the callee.
10170 SIBCALL indicates whether this function call is normal call or sibling call.
10171 It will generate different pattern accordingly. */
10173 void
10175 {
10177 rtvec vec;
10178 machine_mode mode;
10185 /* Decide if we should generate indirect calls by loading the
10186 address of the callee into a register before performing
10187 the branch-and-link. */
10201 else
10206 UNSPEC_CALLEE_ABI);
10212 }
10214 /* Emit call insn with PAT and do aarch64-specific handling. */
10216 void
10218 {
10224 }
10226 machine_mode
10228 {
10232 /* All floating point compares return CCFP if it is an equality
10233 comparison, and CCFPE otherwise. */
10235 {
10237 {
10258 }
10259 }
10261 /* Equality comparisons of short modes against zero can be performed
10262 using the TST instruction with the appropriate bitmask. */
10268 /* Similarly, comparisons of zero_extends from shorter modes can
10269 be performed using an ANDS with an immediate mask. */
10285 /* A compare with a shifted operand. Because of canonicalization,
10286 the comparison will have to be swapped when we emit the assembly
10287 code. */
10295 /* Similarly for a negated operand, but we can only do this for
10296 equalities. */
10303 /* A test for unsigned overflow from an addition. */
10310 /* A test for unsigned overflow from an add with carry. */
10320 /* A test for signed overflow. */
10327 /* For everything else, return CCmode. */
10329 }
10331 static int
10334 int
10336 {
10343 }
10345 static int
10347 {
10349 {
10353 {
10367 }
10372 {
10384 }
10389 {
10401 }
10406 {
10416 }
10421 {
10427 }
10432 {
10436 }
10441 {
10445 }
10450 {
10454 }
10459 {
10463 }
10468 }
10471 }
10473 bool
10475 HOST_WIDE_INT minval,
10476 HOST_WIDE_INT maxval)
10477 {
10478 rtx elt;
10482 }
10484 bool
10486 {
10488 }
10490 /* Return true if VEC is a constant in which every element is in the range
10491 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
10493 static bool
10495 HOST_WIDE_INT minval,
10496 HOST_WIDE_INT maxval)
10497 {
10509 {
10514 }
10516 }
10518 /* N Z C V. */
10519 #define AARCH64_CC_V 1
10520 #define AARCH64_CC_C (1 << 1)
10521 #define AARCH64_CC_Z (1 << 2)
10522 #define AARCH64_CC_N (1 << 3)
10524 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
10526 {
10543 };
10545 /* Print floating-point vector immediate operand X to F, negating it
10546 first if NEGATE is true. Return true on success, false if it isn't
10547 a constant we can handle. */
10549 static bool
10551 {
10552 rtx elt;
10561 /* Handle the SVE single-bit immediates specially, since they have a
10562 fixed form in the assembly syntax. */
10571 else
10572 {
10578 }
10581 }
10583 /* Return the equivalent letter for size. */
10584 static char
10586 {
10588 {
10594 }
10595 }
10597 /* Print operand X to file F in a target specific manner according to CODE.
10598 The acceptable formatting commands given by CODE are:
10599 'c': An integer or symbol address without a preceding #
10600 sign.
10601 'C': Take the duplicated element in a vector constant
10602 and print it in hex.
10603 'D': Take the duplicated element in a vector constant
10604 and print it as an unsigned integer, in decimal.
10605 'e': Print the sign/zero-extend size as a character 8->b,
10606 16->h, 32->w. Can also be used for masks:
10607 0xff->b, 0xffff->h, 0xffffffff->w.
10608 'I': If the operand is a duplicated vector constant,
10609 replace it with the duplicated scalar. If the
10610 operand is then a floating-point constant, replace
10611 it with the integer bit representation. Print the
10612 transformed constant as a signed decimal number.
10613 'p': Prints N such that 2^N == X (X must be power of 2 and
10614 const int).
10615 'P': Print the number of non-zero bits in X (a const_int).
10616 'H': Print the higher numbered register of a pair (TImode)
10617 of regs.
10618 'm': Print a condition (eq, ne, etc).
10619 'M': Same as 'm', but invert condition.
10620 'N': Take the duplicated element in a vector constant
10621 and print the negative of it in decimal.
10622 'b/h/s/d/q': Print a scalar FP/SIMD register name.
10623 'S/T/U/V': Print a FP/SIMD register name for a register list.
10624 The register printed is the FP/SIMD register name
10625 of X + 0/1/2/3 for S/T/U/V.
10626 'R': Print a scalar Integer/FP/SIMD register name + 1.
10627 'X': Print bottom 16 bits of integer constant in hex.
10628 'w/x': Print a general register name or the zero register
10629 (32-bit or 64-bit).
10630 '0': Print a normal operand, if it's a general register,
10631 then we assume DImode.
10632 'k': Print NZCV for conditional compare instructions.
10633 'A': Output address constant representing the first
10634 argument of X, specifying a relocation offset
10635 if appropriate.
10636 'L': Output constant address specified by X
10637 with a relocation offset if appropriate.
10638 'G': Prints address of X, specifying a PC relative
10639 relocation mode if appropriate.
10640 'y': Output address of LDP or STP - this is used for
10641 some LDP/STPs which don't use a PARALLEL in their
10642 pattern (so the mode needs to be adjusted).
10643 'z': Output address of a typical LDP or STP. */
10645 static void
10647 {
10648 rtx elt;
10650 {
10654 else
10655 {
10656 poly_int64 offset;
10660 else
10662 }
10666 {
10669 {
10672 }
10681 else
10682 {
10685 }
10686 }
10690 {
10694 {
10697 }
10700 }
10705 {
10708 }
10715 {
10718 }
10721 {
10724 }
10730 {
10734 else
10735 {
10738 }
10740 }
10744 {
10746 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
10748 {
10752 }
10755 {
10758 }
10766 else
10768 }
10773 {
10776 }
10782 ;
10783 else
10784 {
10787 }
10796 {
10797 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
10799 }
10808 {
10809 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
10811 }
10822 else
10824 code);
10829 {
10832 }
10837 {
10838 /* Print a replicated constant in hex. */
10840 {
10843 }
10846 }
10850 {
10851 /* Print a replicated constant in decimal, treating it as
10852 unsigned. */
10854 {
10857 }
10860 }
10867 {
10870 }
10873 {
10876 }
10879 {
10882 }
10884 /* Fall through */
10888 {
10891 }
10894 {
10897 {
10900 else
10901 {
10902 char suffix
10907 }
10908 }
10909 else
10928 {
10931 }
10932 /* fall through */
10936 {
10939 }
10945 ;
10946 else
10947 {
10950 }
10954 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
10955 be getting CONST_DOUBLEs holding integers. */
10958 {
10961 }
10963 {
10964 #define buf_size 20
10972 #undef buf_size
10973 }
10979 }
10987 {
11014 }
11020 {
11055 }
11061 {
11067 }
11072 {
11073 HOST_WIDE_INT cond_code;
11076 {
11079 }
11084 }
11089 {
11094 {
11097 }
11101 ? ADDR_QUERY_LDP_STP_N
11104 }
11110 }
11111 }
11113 /* Print address 'x' of a memory access with mode 'mode'.
11114 'op' is the context required by aarch64_classify_address. It can either be
11115 MEM for a normal memory access or PARALLEL for LDP/STP. */
11116 static bool
11118 aarch64_addr_query_type type)
11119 {
11123 /* Check all addresses are Pmode - including ILP32. */
11127 {
11130 }
11134 {
11137 {
11140 }
11144 {
11145 HOST_WIDE_INT vnum
11151 }
11161 else
11170 else
11179 else
11185 /* Writeback is only supported for fixed-width modes. */
11188 {
11211 }
11223 }
11226 }
11228 /* Print address 'x' of a memory access with mode 'mode'. */
11229 static void
11231 {
11234 }
11236 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
11238 static bool
11240 {
11242 {
11245 }
11247 }
11249 bool
11251 {
11258 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
11259 referencing instruction, but they are constant offsets, not
11260 symbols. */
11266 {
11268 {
11274 }
11277 }
11280 }
11282 /* Implement REGNO_REG_CLASS. */
11284 enum reg_class
11286 {
11311 }
11313 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
11314 If OFFSET is out of range, return an offset of an anchor point
11315 that is in range. Return 0 otherwise. */
11317 static HOST_WIDE_INT
11319 machine_mode mode)
11320 {
11321 /* Does it look like we'll need a 16-byte load/store-pair operation? */
11325 /* For offsets that aren't a multiple of the access size, the limit is
11326 -256...255. */
11328 {
11329 /* BLKmode typically uses LDP of X-registers. */
11333 }
11335 /* Small negative offsets are supported. */
11342 /* Use 12-bit offset by access size. */
11344 }
11346 static rtx
11348 {
11349 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
11350 where mask is selected by alignment and size of the offset.
11351 We try to pick as large a range for the offset as possible to
11352 maximize the chance of a CSE. However, for aligned addresses
11353 we limit the range to 4k so that structures with different sized
11354 elements are likely to use the same base. We need to be careful
11355 not to split a CONST for some forms of address expression, otherwise
11356 it will generate sub-optimal code. */
11359 {
11365 {
11369 /* Force any scaling into a temp for CSE. */
11373 /* Let the pointer register be in op0. */
11377 /* If the pointer is virtual or frame related, then we know that
11378 virtual register instantiation or register elimination is going
11379 to apply a second constant. We want the two constants folded
11380 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
11382 {
11386 }
11388 /* Otherwise, in order to encourage CSE (and thence loop strength
11389 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
11393 }
11395 HOST_WIDE_INT size;
11397 {
11399 mode);
11401 {
11405 }
11406 }
11407 }
11410 }
11412 static reg_class_t
11414 reg_class_t rclass,
11415 machine_mode mode,
11417 {
11418 /* Use aarch64_sve_reload_mem for SVE memory reloads that cannot use
11419 LDR and STR. See the comment at the head of aarch64-sve.md for
11420 more details about the big-endian handling. */
11425 {
11429 {
11432 }
11433 }
11435 /* If we have to disable direct literal pool loads and stores because the
11436 function is too big, then we need a scratch register. */
11441 {
11444 }
11446 /* Without the TARGET_SIMD instructions we cannot move a Q register
11447 to a Q register directly. We need a scratch. */
11451 {
11454 }
11456 /* A TFmode or TImode memory access should be handled via an FP_REGS
11457 because AArch64 has richer addressing modes for LDR/STR instructions
11458 than LDP/STP instructions. */
11467 }
11469 static bool
11471 {
11474 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
11475 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
11479 }
11481 poly_int64
11483 {
11485 {
11492 }
11495 {
11499 }
11502 }
11505 /* Get return address without mangling. */
11507 rtx
11509 {
11511 /* Note: aarch64_return_address_signing_enabled only
11512 works after cfun->machine->frame.laid_out is set,
11513 so here we don't know if the return address will
11514 be signed or not. */
11519 }
11522 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
11523 previous frame. */
11525 rtx
11527 {
11531 }
11533 static void
11535 {
11536 /* Even if the current function doesn't have branch protection, some
11537 later function might, so since this template is only generated once
11538 we have to add a BTI just in case. */
11542 {
11545 }
11546 else
11547 {
11550 }
11553 /* We always emit a speculation barrier.
11554 This is because the same trampoline template is used for every nested
11555 function. Since nested functions are not particularly common or
11556 performant we don't worry too much about the extra instructions to copy
11557 around.
11558 This is not yet a problem, since we have not yet implemented function
11559 specific attributes to choose between hardening against straight line
11560 speculation or not, but such function specific attributes are likely to
11561 happen in the future. */
11566 }
11568 static void
11570 {
11574 /* Don't need to copy the trailing D-words, we fill those in below. */
11575 /* We create our own memory address in Pmode so that `emit_block_move` can
11576 use parts of the backend which expect Pmode addresses. */
11590 /* XXX We should really define a "clear_cache" pattern and use
11591 gen_clear_cache(). */
11595 a_tramp,
11596 TRAMPOLINE_SIZE));
11597 }
11599 static unsigned char
11601 {
11602 /* ??? Logically we should only need to provide a value when
11603 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
11604 can hold MODE, but at the moment we need to handle all modes.
11605 Just ignore any runtime parts for registers that can't store them. */
11609 {
11640 }
11642 }
11644 static reg_class_t
11646 {
11651 {
11657 }
11659 /* Register eliminiation can result in a request for
11660 SP+constant->FP_REGS. We cannot support such operations which
11661 use SP as source and an FP_REG as destination, so reject out
11662 right now. */
11664 {
11667 /* Look through a possible SUBREG introduced by ILP32. */
11673 POINTER_REGS));
11675 }
11678 }
11680 void
11682 {
11684 }
11686 static void
11688 {
11691 else
11692 {
11694 /* While priority is known to be in range [0, 65535], so 18 bytes
11695 would be enough, the compiler might not know that. To avoid
11696 -Wformat-truncation false positive, use a larger size. */
11703 }
11704 }
11706 static void
11708 {
11711 else
11712 {
11714 /* While priority is known to be in range [0, 65535], so 18 bytes
11715 would be enough, the compiler might not know that. To avoid
11716 -Wformat-truncation false positive, use a larger size. */
11723 }
11724 }
11728 {
11734 {
11735 {
11738 },
11739 {
11742 },
11743 {
11746 },
11747 /* We assume that DImode is only generated when not optimizing and
11748 that we don't really need 64-bit address offsets. That would
11749 imply an object file with 8GB of code in a single function! */
11750 {
11753 }
11754 };
11763 /* Need to implement table size reduction, by chaning the code below. */
11772 operands);
11775 }
11778 /* Return size in bits of an arithmetic operand which is shifted/scaled and
11779 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
11780 operator. */
11782 int
11784 {
11786 {
11789 {
11793 }
11794 }
11796 }
11798 /* Constant pools are per function only when PC relative
11799 literal loads are true or we are in the large memory
11800 model. */
11804 {
11807 }
11809 static bool
11811 {
11812 /* We can't use blocks for constants when we're using a per-function
11813 constant pool. */
11815 }
11817 /* Select appropriate section for constants depending
11818 on where we place literal pools. */
11822 rtx x,
11824 {
11829 }
11831 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
11832 void
11834 HOST_WIDE_INT offset)
11835 {
11836 /* When using per-function literal pools, we must ensure that any code
11837 section is aligned to the minimal instruction length, lest we get
11838 errors from the assembler re "unaligned instructions". */
11841 }
11843 /* Costs. */
11845 /* Helper function for rtx cost calculation. Strip a shift expression
11846 from X. Returns the inner operand if successful, or the original
11847 expression on failure. */
11848 static rtx
11850 {
11853 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
11854 we can convert both to ROR during final output. */
11869 }
11871 /* Helper function for rtx cost calculation. Strip an extend
11872 expression from X. Returns the inner operand if successful, or the
11873 original expression on failure. We deal with a number of possible
11874 canonicalization variations here. If STRIP_SHIFT is true, then
11875 we can strip off a shift also. */
11876 static rtx
11878 {
11879 scalar_int_mode mode;
11893 /* Now handle extended register, as this may also have an optional
11894 left shift by 1..4. */
11909 }
11911 /* Return true iff CODE is a shift supported in combination
11912 with arithmetic instructions. */
11914 static bool
11916 {
11918 }
11921 /* Return true iff X is a cheap shift without a sign extend. */
11923 static bool
11925 {
11951 }
11953 /* Helper function for rtx cost calculation. Calculate the cost of
11954 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
11955 Return the calculated cost of the expression, recursing manually in to
11956 operands where needed. */
11958 static int
11960 {
11974 {
11977 {
11978 /* The by-element versions of the instruction have the same costs as
11979 the normal 3-vector version. So don't add the costs of the
11980 duplicate into the costs of the multiply. We make an assumption
11981 that the input to the VEC_DUPLICATE is already on the FP & SIMD
11982 side. This means costing of a MUL by element pre RA is a bit
11983 optimistic. */
11988 }
11992 {
11995 /* This is to catch the SSRA costing currently flowing here. */
11996 else
11998 }
12000 }
12002 /* Integer multiply/fma. */
12004 {
12005 /* The multiply will be canonicalized as a shift, cost it as such. */
12009 {
12013 {
12015 {
12016 /* If the shift is considered cheap,
12017 then don't add any cost. */
12019 ;
12021 /* ARITH + shift-by-register. */
12024 /* ARITH + extended register. We don't have a cost field
12025 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
12027 else
12028 /* ARITH + shift-by-immediate. */
12030 }
12031 else
12032 /* LSL (immediate). */
12035 }
12036 /* Strip extends as we will have costed them in the case above. */
12043 }
12045 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
12046 compound and let the below cases handle it. After all, MNEG is a
12047 special-case alias of MSUB. */
12049 {
12052 }
12054 /* Integer multiplies or FMAs have zero/sign extending variants. */
12059 {
12064 {
12066 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
12068 else
12069 /* MUL/SMULL/UMULL. */
12071 }
12074 }
12076 /* This is either an integer multiply or a MADD. In both cases
12077 we want to recurse and cost the operands. */
12082 {
12084 /* MADD/MSUB. */
12086 else
12087 /* MUL. */
12089 }
12092 }
12093 else
12094 {
12096 {
12097 /* Floating-point FMA/FMUL can also support negations of the
12098 operands, unless the rounding mode is upward or downward in
12099 which case FNMUL is different than FMUL with operand negation. */
12103 {
12108 }
12111 /* FMADD/FNMADD/FNMSUB/FMSUB. */
12113 else
12114 /* FMUL/FNMUL. */
12116 }
12121 }
12122 }
12124 static int
12126 machine_mode mode,
12127 addr_space_t as ATTRIBUTE_UNUSED,
12129 {
12137 {
12139 {
12140 /* This is a CONST or SYMBOL ref which will be split
12141 in a different way depending on the code model in use.
12142 Cost it through the generic infrastructure. */
12144 /* Divide through by the cost of one instruction to
12145 bring it to the same units as the address costs. */
12147 /* The cost is then the cost of preparing the address,
12148 followed by an immediate (possibly 0) offset. */
12150 }
12151 else
12152 {
12153 /* This is most likely a jump table from a case
12154 statement. */
12156 }
12157 }
12160 {
12171 {
12176 else
12178 }
12179 else
12198 }
12202 {
12203 /* For the sake of calculating the cost of the shifted register
12204 component, we can treat same sized modes in the same way. */
12211 else
12212 /* We can't tell, or this is a 128-bit vector. */
12214 }
12217 }
12219 /* Return the cost of a branch. If SPEED_P is true then the compiler is
12220 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
12221 to be taken. */
12223 int
12225 {
12226 /* When optimizing for speed, use the cost of unpredictable branches. */
12232 else
12234 }
12236 /* Return true if X is a zero or sign extract
12237 usable in an ADD or SUB (extended register) instruction. */
12238 static bool
12240 {
12241 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
12242 No shift. */
12248 }
12250 static bool
12252 {
12254 {
12266 }
12267 }
12269 /* Return true iff X is an rtx that will match an extr instruction
12270 i.e. as described in the *extr<mode>5_insn family of patterns.
12271 OP0 and OP1 will be set to the operands of the shifts involved
12272 on success and will be NULL_RTX otherwise. */
12274 static bool
12276 {
12278 scalar_int_mode mode;
12293 {
12294 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
12306 {
12310 }
12311 }
12314 }
12316 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
12317 storing it in *COST. Result is true if the total cost of the operation
12318 has now been calculated. */
12319 static bool
12321 {
12322 rtx inner;
12323 rtx comparator;
12329 {
12333 }
12334 else
12335 {
12339 }
12342 {
12343 /* Conditional branch. */
12346 else
12347 {
12349 {
12351 {
12352 /* TBZ/TBNZ/CBZ/CBNZ. */
12354 /* TBZ/TBNZ. */
12357 else
12358 /* CBZ/CBNZ. */
12362 }
12365 {
12366 /* SUB and SUBS. */
12371 }
12372 }
12374 {
12375 /* TBZ/TBNZ. */
12378 }
12379 }
12380 }
12382 {
12383 /* CCMP. */
12385 {
12386 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
12390 {
12395 else
12397 }
12399 }
12401 /* It's a conditional operation based on the status flags,
12402 so it must be some flavor of CSEL. */
12404 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
12410 {
12411 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
12414 }
12416 {
12419 /* CSINV/NEG with zero extend + const 0 (*csinv3_uxtw_insn3). */
12421 }
12426 }
12428 /* We don't know what this is, cost all operands. */
12430 }
12432 /* Check whether X is a bitfield operation of the form shift + extend that
12433 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
12434 operand to which the bitfield operation is applied. Otherwise return
12435 NULL_RTX. */
12437 static rtx
12439 {
12453 {
12471 }
12474 }
12476 /* Return true if the mask and a shift amount from an RTX of the form
12477 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
12478 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
12480 bool
12482 rtx shft_amnt)
12483 {
12490 }
12492 /* Return true if the masks and a shift amount from an RTX of the form
12493 ((x & MASK1) | ((y << SHIFT_AMNT) & MASK2)) are valid to combine into
12494 a BFI instruction of mode MODE. See *arch64_bfi patterns. */
12496 bool
12501 {
12504 /* Verify that there is no overlap in what bits are set in the two masks. */
12508 /* Verify that mask2 is not all zeros or ones. */
12512 /* The shift amount should always be less than the mode size. */
12515 /* Verify that the mask being shifted is contiguous and would be in the
12516 least significant bits after shifting by shft_amnt. */
12519 }
12521 /* Calculate the cost of calculating X, storing it in *COST. Result
12522 is true if the total cost of the operation has now been calculated. */
12523 static bool
12526 {
12531 scalar_int_mode int_mode;
12533 /* By default, assume that everything has equivalent cost to the
12534 cheapest instruction. Any additional costs are applied as a delta
12535 above this default. */
12539 {
12541 /* The cost depends entirely on the operands to SET. */
12547 {
12550 {
12564 }
12573 /* Fall through. */
12575 /* The cost is one per vector-register copied. */
12577 {
12580 }
12581 /* const0_rtx is in general free, but we will use an
12582 instruction to set a register to 0. */
12584 {
12585 /* The cost is 1 per register copied. */
12588 }
12589 else
12590 /* Cost is just the cost of the RHS of the set. */
12596 /* Bit-field insertion. Strip any redundant widening of
12597 the RHS to meet the width of the target. */
12608 {
12609 /* MOV immediate is assumed to always be cheap. */
12611 }
12612 else
12613 {
12614 /* BFM. */
12618 }
12623 /* We can't make sense of this, assume default cost. */
12626 }
12630 /* If an instruction can incorporate a constant within the
12631 instruction, the instruction's expression avoids calling
12632 rtx_cost() on the constant. If rtx_cost() is called on a
12633 constant, then it is usually because the constant must be
12634 moved into a register by one or more instructions.
12636 The exception is constant 0, which can be expressed
12637 as XZR/WZR and is therefore free. The exception to this is
12638 if we have (set (reg) (const0_rtx)) in which case we must cost
12639 the move. However, we can catch that when we cost the SET, so
12640 we don't need to consider that here. */
12643 else
12644 {
12645 /* To an approximation, building any other constant is
12646 proportionally expensive to the number of instructions
12647 required to build that constant. This is true whether we
12648 are compiling for SPEED or otherwise. */
12653 }
12658 /* First determine number of instructions to do the move
12659 as an integer constant. */
12663 {
12669 ? SImode
12675 }
12678 {
12679 /* mov[df,sf]_aarch64. */
12681 /* FMOV (scalar immediate). */
12684 {
12685 /* This will be a load from memory. */
12688 else
12690 }
12691 else
12692 /* Otherwise this is +0.0. We get this using MOVI d0, #0
12693 or MOV v0.s[0], wzr - neither of which are modeled by the
12694 cost tables. Just use the default cost. */
12695 {
12696 }
12697 }
12703 {
12704 /* For loads we want the base cost of a load, plus an
12705 approximation for the additional cost of the addressing
12706 mode. */
12720 }
12728 {
12730 {
12731 /* FNEG. */
12733 }
12735 }
12738 {
12741 {
12742 /* CSETM. */
12745 }
12747 /* Cost this as SUB wzr, X. */
12751 }
12754 {
12755 /* Support (neg(fma...)) as a single instruction only if
12756 sign of zeros is unimportant. This matches the decision
12757 making in aarch64.md. */
12759 {
12760 /* FNMADD. */
12763 }
12765 {
12766 /* FNMUL. */
12769 }
12771 /* FNEG. */
12774 }
12781 {
12784 else
12786 }
12803 {
12807 }
12810 {
12811 /* TODO: A write to the CC flags possibly costs extra, this
12812 needs encoding in the cost tables. */
12815 /* ANDS. */
12817 {
12820 }
12823 {
12824 /* ADDS (and CMN alias). */
12827 }
12830 {
12831 /* SUBS. */
12834 }
12839 {
12840 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
12841 Handle it here directly rather than going to cost_logic
12842 since we know the immediate generated for the TST is valid
12843 so we can avoid creating an intermediate rtx for it only
12844 for costing purposes. */
12851 }
12854 {
12855 /* CMN. */
12862 }
12864 /* CMP.
12866 Compare can freely swap the order of operands, and
12867 canonicalization puts the more complex operation first.
12868 But the integer MINUS logic expects the shift/extend
12869 operation in op1. */
12872 {
12875 }
12877 }
12880 {
12881 /* FCMP. */
12886 {
12888 /* FCMP supports constant 0.0 for no extra cost. */
12890 }
12892 }
12895 {
12896 /* Vector compare. */
12901 {
12902 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
12903 cost. */
12905 }
12907 }
12911 {
12915 cost_minus:
12918 /* Detect valid immediates. */
12924 {
12926 /* SUB(S) (immediate). */
12929 }
12931 /* Look for SUB (extended register). */
12934 {
12942 }
12946 /* Cost this as an FMA-alike operation. */
12950 {
12953 speed);
12955 }
12960 {
12962 {
12963 /* Vector SUB. */
12965 }
12967 {
12968 /* SUB(S). */
12970 }
12972 {
12973 /* FSUB. */
12975 }
12976 }
12978 }
12981 {
12982 rtx new_op0;
12987 cost_plus:
12990 {
12991 /* CSINC. */
12995 }
13000 {
13004 {
13005 /* ADD (immediate). */
13008 /* Some tunings prefer to not use the VL-based scalar ops.
13009 Increase the cost of the poly immediate to prevent their
13010 formation. */
13015 }
13017 }
13021 /* Look for ADD (extended register). */
13024 {
13032 }
13034 /* Strip any extend, leave shifts behind as we will
13035 cost them through mult_cost. */
13040 {
13042 speed);
13044 }
13049 {
13051 {
13052 /* Vector ADD. */
13054 }
13056 {
13057 /* ADD. */
13059 }
13061 {
13062 /* FADD. */
13064 }
13065 }
13067 }
13073 {
13076 else
13078 }
13083 {
13087 {
13090 else
13092 }
13094 }
13097 {
13104 }
13105 /* Fall through. */
13108 cost_logic:
13113 {
13117 }
13125 {
13126 /* This is a UBFM/SBFM. */
13131 }
13134 {
13136 {
13137 /* We have a mask + shift version of a UBFIZ
13138 i.e. the *andim_ashift<mode>_bfiz pattern. */
13142 {
13149 }
13151 {
13152 /* We possibly get the immediate for free, this is not
13153 modelled. */
13160 }
13161 }
13162 else
13163 {
13166 /* Handle ORN, EON, or BIC. */
13172 /* If we had a shift on op0 then this is a logical-shift-
13173 by-register/immediate operation. Otherwise, this is just
13174 a logical operation. */
13176 {
13178 {
13179 /* Shift by immediate. */
13182 else
13184 }
13185 else
13187 }
13189 /* In both cases we want to cost both operands. */
13196 }
13197 }
13205 {
13206 /* Vector NOT. */
13209 }
13211 /* MVN-shifted-reg. */
13213 {
13220 }
13221 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
13222 Handle the second form here taking care that 'a' in the above can
13223 be a shift. */
13225 {
13234 {
13237 else
13239 }
13242 }
13243 /* MVN. */
13252 /* If a value is written in SI mode, then zero extended to DI
13253 mode, the operation will in general be free as a write to
13254 a 'w' register implicitly zeroes the upper bits of an 'x'
13255 register. However, if this is
13257 (set (reg) (zero_extend (reg)))
13259 we must cost the explicit register move. */
13263 {
13266 /* If OP_COST is non-zero, then the cost of the zero extend
13267 is effectively the cost of the inner operation. Otherwise
13268 we have a MOV instruction and we take the cost from the MOV
13269 itself. This is true independently of whether we are
13270 optimizing for space or time. */
13275 }
13277 {
13278 /* All loads can zero extend to any size for free. */
13281 }
13285 {
13290 }
13293 {
13295 {
13296 /* UMOV. */
13298 }
13299 else
13300 {
13301 /* We generate an AND instead of UXTB/UXTH. */
13303 }
13304 }
13309 {
13310 /* LDRSH. */
13312 {
13319 }
13321 }
13325 {
13330 }
13333 {
13336 else
13338 }
13346 {
13348 {
13350 {
13351 /* Vector shift (immediate). */
13353 }
13354 else
13355 {
13356 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
13357 aliases. */
13359 }
13360 }
13362 /* We can incorporate zero/sign extend for free. */
13369 }
13370 else
13371 {
13373 {
13375 /* Vector shift (register). */
13377 }
13378 else
13379 {
13381 /* LSLV. */
13388 {
13390 /* We already demanded XEXP (op1, 0) to be REG_P, so
13391 don't recurse into it. */
13393 }
13394 }
13396 }
13406 {
13407 /* ASR (immediate) and friends. */
13409 {
13412 else
13414 }
13418 }
13419 else
13420 {
13422 {
13424 /* Vector shift (register). */
13426 }
13427 else
13428 {
13430 /* ASR (register) and friends. */
13437 {
13439 /* We already demanded XEXP (op1, 0) to be REG_P, so
13440 don't recurse into it. */
13442 }
13443 }
13445 }
13451 {
13452 /* LDR. */
13455 }
13458 {
13459 /* ADRP, followed by ADD. */
13463 }
13466 {
13467 /* ADR. */
13470 }
13473 {
13474 /* One extra load instruction, after accessing the GOT. */
13478 }
13483 /* ADRP/ADD (immediate). */
13490 /* UBFX/SBFX. */
13492 {
13495 else
13497 }
13499 /* We can trust that the immediates used will be correct (there
13500 are no by-register forms), so we need only cost op0. */
13506 /* aarch64_rtx_mult_cost always handles recursion to its
13507 operands. */
13511 /* We can expand signed mod by power of 2 using a NEGS, two parallel
13512 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
13513 an unconditional negate. This case should only ever be reached through
13514 the set_smod_pow2_cheap check in expmed.c. */
13518 {
13519 /* We expand to 4 instructions. Reset the baseline. */
13527 }
13529 /* Fall-through. */
13532 {
13533 /* Slighly prefer UMOD over SMOD. */
13540 }
13547 {
13551 /* There is no integer SQRT, so only DIV and UDIV can get
13552 here. */
13554 /* Slighly prefer UDIV over SDIV. */
13556 else
13558 }
13584 {
13587 else
13589 }
13591 /* FMSUB, FNMADD, and FNMSUB are free. */
13598 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
13599 and the by-element operand as operand 0. */
13603 /* Catch vector-by-element operations. The by-element operand can
13604 either be (vec_duplicate (vec_select (x))) or just
13605 (vec_select (x)), depending on whether we are multiplying by
13606 a vector or a scalar.
13608 Canonicalization is not very good in these cases, FMA4 will put the
13609 by-element operand as operand 0, FNMA4 will have it as operand 1. */
13620 /* If the remaining parameters are not registers,
13621 get the cost to put them into registers. */
13635 {
13637 {
13638 /*Vector truncate. */
13640 }
13641 else
13643 }
13648 {
13650 {
13651 /*Vector conversion. */
13653 }
13654 else
13656 }
13662 /* Strip the rounding part. They will all be implemented
13663 by the fcvt* family of instructions anyway. */
13665 {
13674 }
13677 {
13680 else
13682 }
13684 /* We can combine fmul by a power of 2 followed by a fcvt into a single
13685 fixed-point fcvt. */
13690 {
13694 }
13701 {
13702 /* ABS (vector). */
13705 }
13707 {
13710 /* FABD, which is analogous to FADD. */
13712 {
13719 }
13720 /* Simple FABS is analogous to FNEG. */
13723 }
13724 else
13725 {
13726 /* Integer ABS will either be split to
13727 two arithmetic instructions, or will be an ABS
13728 (scalar), which we don't model. */
13732 }
13738 {
13741 else
13742 {
13743 /* FMAXNM/FMINNM/FMAX/FMIN.
13744 TODO: This may not be accurate for all implementations, but
13745 we do not model this in the cost tables. */
13747 }
13748 }
13752 /* The floating point round to integer frint* instructions. */
13754 {
13759 }
13762 {
13767 }
13772 /* Decompose <su>muldi3_highpart. */
13774 mode == DImode
13775 /* (lshiftrt:TI */
13778 /* (mult:TI */
13780 /* (ANY_EXTEND:TI (reg:DI))
13781 (ANY_EXTEND:TI (reg:DI))) */
13788 /* (const_int 64) */
13791 {
13792 /* UMULH/SMULH. */
13800 }
13802 /* Fall through. */
13805 }
13813 }
13815 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
13816 calculated for X. This cost is stored in *COST. Returns true
13817 if the total cost of X was calculated. */
13818 static bool
13821 {
13826 {
13831 }
13834 }
13836 static int
13839 {
13845 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
13854 /* Make RDFFR very expensive. In particular, if we know that the FFR
13855 contains a PTRUE (e.g. after a SETFFR), we must never use RDFFR
13856 as a way of obtaining a PTRUE. */
13862 /* Moving between GPR and stack cost is the same as GP2GP. */
13867 /* To/From the stack register, we move via the gprs. */
13873 {
13874 /* 128-bit operations on general registers require 2 instructions. */
13882 /* When AdvSIMD instructions are disabled it is not possible to move
13883 a 128-bit value directly between Q registers. This is handled in
13884 secondary reload. A general register is used as a scratch to move
13885 the upper DI value and the lower DI value is moved directly,
13886 hence the cost is the sum of three moves. */
13891 }
13901 }
13903 static int
13905 reg_class_t rclass ATTRIBUTE_UNUSED,
13907 {
13909 }
13911 /* Implement TARGET_INIT_BUILTINS. */
13912 static void
13914 {
13917 #ifdef SUBTARGET_INIT_BUILTINS
13918 SUBTARGET_INIT_BUILTINS;
13919 #endif
13920 }
13922 /* Implement TARGET_FOLD_BUILTIN. */
13923 static tree
13925 {
13930 {
13936 }
13938 }
13940 /* Implement TARGET_GIMPLE_FOLD_BUILTIN. */
13941 static bool
13943 {
13950 {
13958 }
13965 }
13967 /* Implement TARGET_EXPAND_BUILTIN. */
13968 static rtx
13970 {
13975 {
13981 }
13983 }
13985 /* Implement TARGET_BUILTIN_DECL. */
13986 static tree
13988 {
13991 {
13997 }
13999 }
14001 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
14002 to optimize 1.0/sqrt. */
14004 static bool
14006 {
14008 && flag_unsafe_math_optimizations
14012 }
14014 /* Function to decide when to use the approximate reciprocal square root
14015 builtin. */
14017 static tree
14019 {
14027 {
14033 }
14035 }
14037 /* Emit code to perform the floating-point operation:
14039 DST = SRC1 * SRC2
14041 where all three operands are already known to be registers.
14042 If the operation is an SVE one, PTRUE is a suitable all-true
14043 predicate. */
14045 static void
14047 {
14052 else
14054 }
14056 /* Emit instruction sequence to compute either the approximate square root
14057 or its approximate reciprocal, depending on the flag RECP, and return
14058 whether the sequence was emitted or not. */
14060 bool
14062 {
14066 {
14069 }
14072 {
14079 || flag_trapping_math
14080 || !flag_unsafe_math_optimizations
14083 }
14084 else
14085 /* Caller assumes we cannot fail. */
14096 {
14097 /* When calculating the approximate square root, compare the
14098 argument with 0.0 and create a mask. */
14101 {
14106 }
14107 else
14108 {
14113 }
14114 }
14116 /* Estimate the approximate reciprocal square root. */
14120 /* Iterate over the series twice for SF and thrice for DF. */
14123 /* Optionally iterate over the series once less for faster performance
14124 while sacrificing the accuracy. */
14127 iterations--;
14129 /* Iterate over the series to calculate the approximate reciprocal square
14130 root. */
14133 {
14141 }
14144 {
14146 /* Multiply nonzero source values by the corresponding intermediate
14147 result elements, so that the final calculation is the approximate
14148 square root rather than its reciprocal. Select a zero result for
14149 zero source values, to avoid the Inf * 0 -> NaN that we'd get
14150 otherwise. */
14153 else
14154 {
14155 /* Qualify the approximate reciprocal square root when the
14156 argument is 0.0 by squashing the intermediary result to 0.0. */
14162 /* Calculate the approximate square root. */
14164 }
14165 }
14167 /* Finalize the approximation. */
14171 }
14173 /* Emit the instruction sequence to compute the approximation for the division
14174 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
14176 bool
14178 {
14189 || flag_trapping_math
14190 || !flag_unsafe_math_optimizations
14202 /* Estimate the approximate reciprocal. */
14206 /* Iterate over the series twice for SF and thrice for DF. */
14209 /* Optionally iterate over the series less for faster performance,
14210 while sacrificing the accuracy. The default is 2 for DF and 1 for SF. */
14213 ? aarch64_double_recp_precision
14216 /* Iterate over the series to calculate the approximate reciprocal. */
14219 {
14224 }
14227 {
14228 /* As the approximate reciprocal of DEN is already calculated, only
14229 calculate the approximate division when NUM is not 1.0. */
14232 }
14234 /* Finalize the approximation. */
14237 }
14239 /* Return the number of instructions that can be issued per cycle. */
14240 static int
14242 {
14244 }
14246 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
14247 static int
14249 {
14261 }
14263 static int
14265 {
14269 }
14272 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
14273 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
14274 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
14276 static int
14279 {
14281 }
14284 /* Vectorizer cost model target hooks. */
14286 /* Information about how the CPU would issue the scalar, Advanced SIMD
14287 or SVE version of a vector loop, using the scheme defined by the
14288 aarch64_base_vec_issue_info hierarchy of structures. */
14289 struct aarch64_vec_op_count
14290 {
14293 /* The number of individual "general" operations. See the comments
14294 in aarch64_base_vec_issue_info for details. */
14297 /* The number of load and store operations, under the same scheme
14298 as above. */
14302 /* The minimum number of cycles needed to execute all loop-carried
14303 operations, which in the vector code become associated with
14304 reductions. */
14306 };
14308 /* Extends aarch64_vec_op_count with SVE-specific information. */
14310 {
14313 /* The number of individual predicate operations. See the comments
14314 in aarch64_sve_vec_issue_info for details. */
14316 };
14318 /* Information about vector code that we're in the process of costing. */
14319 struct aarch64_vector_costs
14320 {
14321 /* The normal latency-based costs for each region (prologue, body and
14322 epilogue), indexed by vect_cost_model_location. */
14325 /* True if we have performed one-time initialization based on the vec_info.
14327 This variable exists because the vec_info is not passed to the
14328 init_cost hook. We therefore have to defer initialization based on
14329 it till later. */
14332 /* True if we're costing a vector loop, false if we're costing block-level
14333 vectorization. */
14336 /* True if we've seen an SVE operation that we cannot currently vectorize
14337 using Advanced SIMD. */
14340 /* - If VEC_FLAGS is zero then we're costing the original scalar code.
14341 - If VEC_FLAGS & VEC_ADVSIMD is nonzero then we're costing Advanced
14342 SIMD code.
14343 - If VEC_FLAGS & VEC_ANY_SVE is nonzero then we're costing SVE code. */
14346 /* On some CPUs, SVE and Advanced SIMD provide the same theoretical vector
14347 throughput, such as 4x128 Advanced SIMD vs. 2x256 SVE. In those
14348 situations, we try to predict whether an Advanced SIMD implementation
14349 of the loop could be completely unrolled and become straight-line code.
14350 If so, it is generally better to use the Advanced SIMD version rather
14351 than length-agnostic SVE, since the SVE loop would execute an unknown
14352 number of times and so could not be completely unrolled in the same way.
14354 If we're applying this heuristic, UNROLLED_ADVSIMD_NITERS is the
14355 number of Advanced SIMD loop iterations that would be unrolled and
14356 UNROLLED_ADVSIMD_STMTS estimates the total number of statements
14357 in the unrolled loop. Both values are zero if we're not applying
14358 the heuristic. */
14362 /* If we're vectorizing a loop that executes a constant number of times,
14363 this variable gives the number of times that the vector loop would
14364 iterate, otherwise it is zero. */
14367 /* Used only when vectorizing loops. Estimates the number and kind of scalar
14368 operations that would be needed to perform the same work as one iteration
14369 of the vector loop. */
14370 aarch64_vec_op_count scalar_ops;
14372 /* Used only when vectorizing loops. If VEC_FLAGS & VEC_ADVSIMD,
14373 this structure estimates the number and kind of operations that the
14374 vector loop would contain. If VEC_FLAGS & VEC_SVE, the structure
14375 estimates what the equivalent Advanced SIMD-only code would need in
14376 order to perform the same work as one iteration of the SVE loop. */
14377 aarch64_vec_op_count advsimd_ops;
14379 /* Used only when vectorizing loops with SVE. It estimates the number and
14380 kind of operations that the SVE loop would contain. */
14381 aarch64_sve_op_count sve_ops;
14383 /* Used to detect cases in which we end up costing the same load twice,
14384 once to account for results that are actually used and once to account
14385 for unused results. */
14387 };
14389 /* Implement TARGET_VECTORIZE_INIT_COST. */
14392 {
14394 }
14396 /* Return true if the current CPU should use the new costs defined
14397 in GCC 11. This should be removed for GCC 12 and above, with the
14398 costs applying to all CPUs instead. */
14399 static bool
14401 {
14404 }
14406 /* Return the appropriate SIMD costs for vectors of type VECTYPE. */
14409 {
14416 }
14418 /* Return the appropriate SIMD costs for vectors with VEC_* flags FLAGS. */
14421 {
14426 }
14428 /* Decide whether to use the unrolling heuristic described above
14429 aarch64_vector_costs::unrolled_advsimd_niters, updating that
14430 field if so. LOOP_VINFO describes the loop that we're vectorizing
14431 and COSTS are the costs that we're calculating for it. */
14432 static void
14435 {
14436 /* The heuristic only makes sense on targets that have the same
14437 vector throughput for SVE and Advanced SIMD. */
14442 /* We only want to apply the heuristic if LOOP_VINFO is being
14443 vectorized for SVE. */
14447 /* Check whether it is possible in principle to use Advanced SIMD
14448 instead. */
14452 /* We don't want to apply the heuristic to outer loops, since it's
14453 harder to track two levels of unrolling. */
14457 /* Only handle cases in which the number of Advanced SIMD iterations
14458 would be known at compile time but the number of SVE iterations
14459 would not. */
14464 /* Guess how many times the Advanced SIMD loop would iterate and make
14465 sure that it is within the complete unrolling limit. Even if the
14466 number of iterations is small enough, the number of statements might
14467 not be, which is why we need to estimate the number of statements too. */
14470 unsigned HOST_WIDE_INT unrolled_advsimd_niters
14475 /* Record that we're applying the heuristic and should try to estimate
14476 the number of statements in the Advanced SIMD loop. */
14478 }
14480 /* Do one-time initialization of COSTS given that we're costing the loop
14481 vectorization described by LOOP_VINFO. */
14482 static void
14485 {
14488 /* Record the number of times that the vector loop would execute,
14489 if known. */
14493 {
14497 else
14499 }
14501 /* Detect whether we're costing the scalar code or the vector code.
14502 This is a bit hacky: it would be better if the vectorizer told
14503 us directly.
14505 If we're costing the vector code, record whether we're vectorizing
14506 for Advanced SIMD or SVE. */
14509 else
14512 /* Detect whether we're vectorizing for SVE and should
14513 apply the unrolling heuristic described above
14514 aarch64_vector_costs::unrolled_advsimd_niters. */
14517 /* Record the issue information for any SVE WHILE instructions that the
14518 loop needs. */
14523 {
14531 }
14532 }
14534 /* Do one-time initialization of COSTS given that we're costing the block
14535 vectorization described by BB_VINFO. */
14536 static void
14538 {
14539 /* Unfortunately, there's no easy way of telling whether we're costing
14540 the vector code or the scalar code, so just assume that we're costing
14541 the vector code. */
14543 }
14545 /* Implement targetm.vectorize.builtin_vectorization_cost. */
14546 static int
14548 tree vectype,
14550 {
14561 {
14614 }
14615 }
14617 /* Return true if STMT_INFO represents part of a reduction. */
14618 static bool
14620 {
14623 }
14625 /* If STMT_INFO describes a reduction, return the type of reduction
14626 it describes, otherwise return -1. */
14627 static int
14629 {
14632 {
14635 }
14637 }
14639 /* Return true if an access of kind KIND for STMT_INFO represents one
14640 vector of an LD[234] or ST[234] operation. Return the total number of
14641 vectors (2, 3 or 4) if so, otherwise return a value outside that range. */
14642 static int
14644 {
14650 {
14655 }
14657 }
14659 /* If STMT_INFO is a COND_EXPR that includes an embedded comparison, return the
14660 scalar type of the values being compared. Return null otherwise. */
14661 static tree
14663 {
14666 {
14670 }
14672 }
14674 /* If STMT_INFO is a comparison or contains an embedded comparison, return the
14675 scalar type of the values being compared. Return null otherwise. */
14676 static tree
14678 {
14683 }
14685 /* Return true if creating multiple copies of STMT_INFO for Advanced SIMD
14686 vectors would produce a series of LDP or STP operations. KIND is the
14687 kind of statement that STMT_INFO represents. */
14688 static bool
14690 stmt_vec_info stmt_info)
14691 {
14693 {
14702 }
14709 }
14711 /* Return true if STMT_INFO extends the result of a load. */
14712 static bool
14714 {
14731 }
14733 /* Return true if STMT_INFO is an integer truncation. */
14734 static bool
14736 {
14746 }
14748 /* Return true if STMT_INFO is the second part of a two-statement multiply-add
14749 or multiply-subtract sequence that might be suitable for fusing into a
14750 single instruction. */
14751 static bool
14753 {
14766 {
14768 /* ??? Should we try to check for a single use as well? */
14781 }
14783 }
14785 /* Return true if the vectorized form of STMT_INFO is something that is only
14786 possible when using SVE instead of Advanced SIMD. VECTYPE is the type of
14787 the vector that STMT_INFO is operating on. */
14788 static bool
14790 {
14795 {
14796 /* Check for true gathers and scatters (rather than just strided accesses
14797 that we've chosen to implement using gathers and scatters). Although
14798 in principle we could use elementwise accesses for Advanced SIMD,
14799 the vectorizer doesn't yet support that. */
14803 /* Check for masked loads and stores. */
14808 }
14810 /* Check for 64-bit integer multiplications. */
14819 }
14821 /* We are considering implementing STMT_INFO using SVE vector type VECTYPE.
14822 If STMT_INFO is an in-loop reduction that SVE supports directly, return
14823 its latency in cycles, otherwise return zero. SVE_COSTS specifies the
14824 latencies of the relevant instructions. */
14825 static unsigned int
14827 stmt_vec_info stmt_info,
14828 tree vectype,
14830 {
14832 {
14838 {
14851 }
14853 }
14856 }
14858 /* STMT_INFO describes a loop-carried operation in the original scalar code
14859 that we are considering implementing as a reduction. Return one of the
14860 following values, depending on VEC_FLAGS:
14862 - If VEC_FLAGS is zero, return the loop carry latency of the original
14863 scalar operation.
14865 - If VEC_FLAGS & VEC_ADVSIMD, return the loop carry latency of the
14866 the Advanced SIMD implementation.
14868 - If VEC_FLAGS & VEC_ANY_SVE, return the loop carry latency of the
14869 SVE implementation.
14871 VECTYPE is the type of vector that the vectorizer is considering using
14872 for STMT_INFO, which might be different from the type of vector described
14873 by VEC_FLAGS. */
14874 static unsigned int
14877 {
14883 /* If the caller is asking for the SVE latency, check for forms of reduction
14884 that only SVE can handle directly. */
14886 {
14887 unsigned int latency
14889 sve_costs);
14892 }
14894 /* Handle scalar costs. */
14896 {
14900 }
14902 /* Otherwise, the loop body just contains normal integer or FP operations,
14903 with a vector reduction outside the loop. */
14909 }
14911 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
14912 for STMT_INFO, which has cost kind KIND. If this is a scalar operation,
14913 try to subdivide the target-independent categorization provided by KIND
14914 to get a more accurate cost. */
14915 static unsigned int
14917 stmt_vec_info stmt_info,
14919 {
14920 /* Detect an extension of a loaded value. In general, we'll be able to fuse
14921 the extension with the load. */
14926 }
14928 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
14929 for the vectorized form of STMT_INFO, which has cost kind KIND and which
14930 when vectorized would operate on vector type VECTYPE. Try to subdivide
14931 the target-independent categorization provided by KIND to get a more
14932 accurate cost. WHERE specifies where the cost associated with KIND
14933 occurs. */
14934 static unsigned int
14939 {
14945 /* It's generally better to avoid costing inductions, since the induction
14946 will usually be hidden by other operations. This is particularly true
14947 for things like COND_REDUCTIONS. */
14951 /* Detect cases in which vec_to_scalar is describing the extraction of a
14952 vector element in preparation for a scalar store. The store itself is
14953 costed separately. */
14959 /* Detect cases in which a scalar_store is really storing one element
14960 in a scatter operation. */
14962 && sve_costs
14966 /* Detect cases in which vec_to_scalar represents an in-loop reduction. */
14970 {
14971 unsigned int latency
14973 sve_costs);
14976 }
14978 /* Detect cases in which vec_to_scalar represents a single reduction
14979 instruction like FADDP or MAXV. */
14984 {
15009 }
15011 /* Otherwise stick with the original categorization. */
15013 }
15015 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
15016 for STMT_INFO, which has cost kind KIND and which when vectorized would
15017 operate on vector type VECTYPE. Adjust the cost as necessary for SVE
15018 targets. */
15019 static unsigned int
15023 {
15024 /* Unlike vec_promote_demote, vector_stmt conversions do not change the
15025 vector register size or number of units. Integer promotions of this
15026 type therefore map to SXT[BHW] or UXT[BHW].
15028 Most loads have extending forms that can do the sign or zero extension
15029 on the fly. Optimistically assume that a load followed by an extension
15030 will fold to this form during combine, and that the extension therefore
15031 comes for free. */
15035 /* For similar reasons, vector_stmt integer truncations are a no-op,
15036 because we can just ignore the unused upper bits of the source. */
15040 /* Advanced SIMD can load and store pairs of registers using LDP and STP,
15041 but there are no equivalent instructions for SVE. This means that
15042 (all other things being equal) 128-bit SVE needs twice as many load
15043 and store instructions as Advanced SIMD in order to process vector pairs.
15045 Also, scalar code can often use LDP and STP to access pairs of values,
15046 so it is too simplistic to say that one SVE load or store replaces
15047 VF scalar loads and stores.
15049 Ideally we would account for this in the scalar and Advanced SIMD
15050 costs by making suitable load/store pairs as cheap as a single
15051 load/store. However, that would be a very invasive change and in
15052 practice it tends to stress other parts of the cost model too much.
15053 E.g. stores of scalar constants currently count just a store,
15054 whereas stores of vector constants count a store and a vec_init.
15055 This is an artificial distinction for AArch64, where stores of
15056 nonzero scalar constants need the same kind of register invariant
15057 as vector stores.
15059 An alternative would be to double the cost of any SVE loads and stores
15060 that could be paired in Advanced SIMD (and possibly also paired in
15061 scalar code). But this tends to stress other parts of the cost model
15062 in the same way. It also means that we can fall back to Advanced SIMD
15063 even if full-loop predication would have been useful.
15065 Here we go for a more conservative version: double the costs of SVE
15066 loads and stores if one iteration of the scalar loop processes enough
15067 elements for it to use a whole number of Advanced SIMD LDP or STP
15068 instructions. This makes it very likely that the VF would be 1 for
15069 Advanced SIMD, and so no epilogue should be needed. */
15071 {
15078 }
15081 }
15083 /* STMT_COST is the cost calculated for STMT_INFO, which has cost kind KIND
15084 and which when vectorized would operate on vector type VECTYPE. Add the
15085 cost of any embedded operations. */
15086 static unsigned int
15089 {
15091 {
15094 /* Detect cases in which a vector load or store represents an
15095 LD[234] or ST[234] instruction. */
15097 {
15109 }
15113 {
15116 else
15118 }
15119 }
15123 {
15126 else
15128 }
15131 }
15133 /* VINFO, COSTS, COUNT, KIND, STMT_INFO and VECTYPE are the same as for
15134 TARGET_VECTORIZE_ADD_STMT_COST and they describe an operation in the
15135 body of a vector loop. Record issue information relating to the vector
15136 operation in OPS, where OPS is one of COSTS->scalar_ops, COSTS->advsimd_ops
15137 or COSTS->sve_ops; see the comments above those variables for details.
15138 In addition:
15140 - VEC_FLAGS is zero if OPS is COSTS->scalar_ops.
15142 - VEC_FLAGS & VEC_ADVSIMD is nonzero if OPS is COSTS->advsimd_ops.
15144 - VEC_FLAGS & VEC_ANY_SVE is nonzero if OPS is COSTS->sve_ops.
15146 ISSUE_INFO provides the scalar, Advanced SIMD or SVE issue information
15147 associated with OPS and VEC_FLAGS. FACTOR says how many iterations of
15148 the loop described by VEC_FLAGS would be needed to match one iteration
15149 of the vector loop in VINFO. */
15150 static void
15157 {
15169 /* Calculate the minimum cycles per iteration imposed by a reduction
15170 operation. */
15173 {
15174 unsigned int base
15176 vec_flags);
15178 {
15180 {
15181 /* When costing an SVE FADDA, the vectorizer treats vec_to_scalar
15182 as a single operation, whereas for Advanced SIMD it is a
15183 per-element one. Increase the factor accordingly, both for
15184 the reduction_latency calculation and for the op couting. */
15187 }
15188 else
15189 /* An Advanced SIMD fold-left reduction is the same as a
15190 scalar one and the vectorizer therefore treats vec_to_scalar
15191 as a per-element cost. There is no extra factor to apply for
15192 scalar code, either for reduction_latency or for the op
15193 counting below. */
15195 }
15197 /* ??? Ideally for vector code we'd do COUNT * FACTOR reductions in
15198 parallel, but unfortunately that's not yet the case. */
15201 }
15203 /* Assume that multiply-adds will become a single operation. */
15207 /* When costing scalar statements in vector code, the count already
15208 includes the number of scalar elements in the vector, so we don't
15209 need to apply the factor as well. */
15213 /* This can go negative with the load handling below. */
15216 /* Count the basic operation cost associated with KIND. */
15218 {
15223 /* We currently don't expect these to be used in a loop body. */
15231 /* Assume that these operations have no overhead in the original
15232 scalar code. */
15235 /* Fallthrough. */
15244 /* When costing scalars, detect cases in which we are called twice for
15245 the same load. This happens for LD[234] operations if only some of
15246 the results are used. The first time represents the cost of loading
15247 the unused vectors, while the second time represents the cost of
15248 loading the useful parts. Only the latter should count towards the
15249 scalar costs. */
15251 {
15257 else
15259 }
15272 }
15274 /* Add any embedded comparison operations. */
15279 /* Detect COND_REDUCTIONs and things that would need to become
15280 COND_REDUCTIONs if they were implemented using Advanced SIMD.
15281 There are then two sets of VEC_COND_EXPRs, whereas so far we
15282 have only accounted for one. */
15284 {
15289 }
15291 /* Count the predicate operations needed by an SVE comparison. */
15294 {
15299 }
15301 /* Add any extra overhead associated with LD[234] and ST[234] operations. */
15304 {
15316 }
15318 /* Add any overhead associated with gather loads and scatter stores. */
15322 {
15327 }
15328 }
15330 /* Implement targetm.vectorize.add_stmt_cost. */
15331 static unsigned
15336 {
15341 {
15342 int stmt_cost
15345 /* Do one-time initialization based on the vinfo. */
15349 {
15352 else
15355 }
15357 /* Try to get a more accurate cost by looking at STMT_INFO instead
15358 of just looking at KIND. */
15360 {
15364 stmt_cost = aarch64_detect_scalar_stmt_subtype
15371 }
15373 /* Do any SVE-specific adjustments to the cost. */
15379 {
15380 /* Account for any extra "embedded" costs that apply additively
15381 to the base cost calculated above. */
15383 stmt_cost);
15385 /* If we're recording a nonzero vector loop body cost, also estimate
15386 the operations that would need to be issued by all relevant
15387 implementations of the loop. */
15390 && issue_info
15393 && vectype
15395 {
15396 /* Record estimates for the scalar code. */
15402 {
15403 /* Record estimates for a possible Advanced SIMD version
15404 of the SVE code. */
15410 /* Record estimates for the SVE code itself. */
15414 }
15415 else
15416 /* Record estimates for the Advanced SIMD code. Treat SVE like
15417 Advanced SIMD if the CPU has no specific SVE costs. */
15421 }
15423 /* If we're applying the SVE vs. Advanced SIMD unrolling heuristic,
15424 estimate the number of statements in the unrolled Advanced SIMD
15425 loop. For simplicitly, we assume that one iteration of the
15426 Advanced SIMD loop would need the same number of statements
15427 as one iteration of the SVE loop. */
15429 costs->unrolled_advsimd_stmts
15431 }
15433 /* Statements in an inner loop relative to the loop being
15434 vectorized are weighted more heavily. The value here is
15435 arbitrary and could potentially be improved with analysis. */
15438 {
15441 }
15445 }
15448 }
15450 /* Dump information about the structure. */
15451 void
15453 {
15462 }
15464 /* Dump information about the structure. */
15465 void
15467 {
15471 }
15473 /* Use ISSUE_INFO to estimate the minimum number of cycles needed to issue
15474 the operations described by OPS. This is a very simplistic model! */
15475 static unsigned int
15476 aarch64_estimate_min_cycles_per_iter
15479 {
15487 }
15489 /* BODY_COST is the cost of a vector loop body recorded in COSTS.
15490 Adjust the cost as necessary and return the new cost. */
15491 static unsigned int
15493 {
15502 {
15508 /* Apply the Advanced SIMD vs. SVE unrolling heuristic described above
15509 aarch64_vector_costs::unrolled_advsimd_niters.
15511 The balance here is tricky. On the one hand, we can't be sure whether
15512 the code is vectorizable with Advanced SIMD or not. However, even if
15513 it isn't vectorizable with Advanced SIMD, there's a possibility that
15514 the scalar code could also be unrolled. Some of the code might then
15515 benefit from SLP, or from using LDP and STP. We therefore apply
15516 the heuristic regardless of can_use_advsimd_p. */
15520 {
15524 {
15527 "Increasing body cost to %d to account for"
15531 }
15532 }
15533 }
15539 unsigned int scalar_cycles_per_iter
15542 unsigned int advsimd_cycles_per_iter
15545 bool could_use_advsimd
15553 {
15562 scalar_cycles_per_iter);
15564 {
15570 advsimd_cycles_per_iter);
15571 }
15572 else
15575 }
15580 {
15581 /* Estimate the minimum number of cycles per iteration needed to issue
15582 non-predicate operations. */
15583 unsigned int sve_cycles_per_iter
15587 /* Separately estimate the minimum number of cycles per iteration needed
15588 to issue the predicate operations. */
15589 unsigned int pred_cycles_per_iter
15593 {
15597 " estimated cycles per iteration for non-predicate"
15602 pred_cycles_per_iter);
15603 }
15608 /* If the scalar version of the loop could issue at least as
15609 quickly as the predicate parts of the SVE loop, make the SVE loop
15610 prohibitively expensive. In this case vectorization is adding an
15611 overhead that the original scalar code didn't have.
15613 This is mostly intended to detect cases in which WHILELOs dominate
15614 for very tight loops, which is something that normal latency-based
15615 costs would not model. Adding this kind of cliffedge would be
15616 too drastic for scalar_cycles_per_iter vs. sve_cycles_per_iter;
15617 code later in the function handles that case in a more
15618 conservative way. */
15621 {
15622 unsigned int min_cost
15625 {
15628 "Increasing body cost to %d because the"
15629 " scalar code could issue within the limit"
15631 min_cost);
15634 }
15635 }
15637 /* If it appears that the Advanced SIMD version of a loop could issue
15638 more quickly than the SVE one, increase the SVE cost in proportion
15639 to the difference. The intention is to make Advanced SIMD preferable
15640 in cases where an Advanced SIMD version exists, without increasing
15641 the costs so much that SVE won't be used at all.
15643 The reasoning is similar to the scalar vs. predicate comparison above:
15644 if the issue rate of the SVE code is limited by predicate operations
15645 (i.e. if pred_cycles_per_iter > sve_cycles_per_iter), and if the
15646 Advanced SIMD code could issue within the limit imposed by the
15647 predicate operations, the predicate operations are adding an
15648 overhead that the original code didn't have and so we should prefer
15649 the Advanced SIMD version. However, if the predicate operations
15650 do not dominate in this way, we should only increase the cost of
15651 the SVE code if sve_cycles_per_iter is strictly greater than
15652 advsimd_cycles_per_iter. Given rounding effects, this should mean
15653 that Advanced SIMD is either better or at least no worse. */
15657 {
15658 /* This ensures that min_cost > orig_body_cost * 2. */
15659 unsigned int min_cost
15662 {
15665 "Increasing body cost to %d because Advanced"
15667 min_cost);
15670 }
15671 }
15672 }
15674 /* Decide whether to stick to latency-based costs or whether to try to
15675 take issue rates into account. */
15682 {
15685 "Low iteration count, so using pure latency"
15687 }
15688 /* Increase the cost of the vector code if it looks like the scalar code
15689 could issue more quickly. These values are only rough estimates,
15690 so minor differences should only result in minor changes. */
15692 {
15694 scalar_cycles_per_iter);
15697 "Increasing body cost to %d because scalar code"
15699 }
15700 /* In general, it's expected that the proposed vector code would be able
15701 to issue more quickly than the original scalar code. This should
15702 already be reflected to some extent in the latency-based costs.
15704 However, the latency-based costs effectively assume that the scalar
15705 code and the vector code execute serially, which tends to underplay
15706 one important case: if the real (non-serialized) execution time of
15707 a scalar iteration is dominated by loop-carried dependencies,
15708 and if the vector code is able to reduce both the length of
15709 the loop-carried dependencies *and* the number of cycles needed
15710 to issue the code in general, we can be more confident that the
15711 vector code is an improvement, even if adding the other (non-loop-carried)
15712 latencies tends to hide this saving. We therefore reduce the cost of the
15713 vector loop body in proportion to the saving. */
15718 {
15720 scalar_cycles_per_iter);
15723 "Decreasing body cost to %d account for smaller"
15725 }
15728 }
15730 /* Implement TARGET_VECTORIZE_FINISH_COST. */
15731 static void
15734 {
15744 }
15746 /* Implement TARGET_VECTORIZE_DESTROY_COST_DATA. */
15747 static void
15749 {
15751 }
15755 /* Parse the TO_PARSE string and put the architecture struct that it
15756 selects into RES and the architectural features into ISA_FLAGS.
15757 Return an aarch64_parse_opt_result describing the parse result.
15758 If there is an error parsing, RES and ISA_FLAGS are left unchanged.
15759 When the TO_PARSE string contains an invalid extension,
15760 a copy of the string is created and stored to INVALID_EXTENSION. */
15762 static enum aarch64_parse_opt_result
15765 {
15774 else
15781 /* Loop through the list of supported ARCHes to find a match. */
15783 {
15786 {
15790 {
15791 /* TO_PARSE string contains at least one extension. */
15792 enum aarch64_parse_opt_result ext_res
15797 }
15798 /* Extension parsing was successful. Confirm the result
15799 arch and ISA flags. */
15803 }
15804 }
15806 /* ARCH name not found in list. */
15808 }
15810 /* Parse the TO_PARSE string and put the result tuning in RES and the
15811 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
15812 describing the parse result. If there is an error parsing, RES and
15813 ISA_FLAGS are left unchanged.
15814 When the TO_PARSE string contains an invalid extension,
15815 a copy of the string is created and stored to INVALID_EXTENSION. */
15817 static enum aarch64_parse_opt_result
15820 {
15829 else
15836 /* Loop through the list of supported CPUs to find a match. */
15838 {
15840 {
15845 {
15846 /* TO_PARSE string contains at least one extension. */
15847 enum aarch64_parse_opt_result ext_res
15852 }
15853 /* Extension parsing was successfull. Confirm the result
15854 cpu and ISA flags. */
15858 }
15859 }
15861 /* CPU name not found in list. */
15863 }
15865 /* Parse the TO_PARSE string and put the cpu it selects into RES.
15866 Return an aarch64_parse_opt_result describing the parse result.
15867 If the parsing fails the RES does not change. */
15869 static enum aarch64_parse_opt_result
15871 {
15874 /* Loop through the list of supported CPUs to find a match. */
15876 {
15878 {
15881 }
15882 }
15884 /* CPU name not found in list. */
15886 }
15888 /* Parse TOKEN, which has length LENGTH to see if it is an option
15889 described in FLAG. If it is, return the index bit for that fusion type.
15890 If not, error (printing OPTION_NAME) and return zero. */
15892 static unsigned int
15897 {
15899 {
15903 }
15907 }
15909 /* Parse OPTION which is a comma-separated list of flags to enable.
15910 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
15911 default state we inherit from the CPU tuning structures. OPTION_NAME
15912 gives the top-level option we are parsing in the -moverride string,
15913 for use in error messages. */
15915 static unsigned int
15920 {
15927 {
15930 token_length,
15931 flags,
15932 option_name);
15933 /* If we find "none" (or, for simplicity's sake, an error) anywhere
15934 in the token stream, reset the supported operations. So:
15936 adrp+add.cmp+branch.none.adrp+add
15938 would have the result of turning on only adrp+add fusion. */
15944 }
15946 /* We ended with a comma, print something. */
15948 {
15951 }
15953 /* We still have one more token to parse. */
15956 token_length,
15957 flags,
15958 option_name);
15964 }
15966 /* Support for overriding instruction fusion. */
15968 static void
15971 {
15973 aarch64_fusible_pairs,
15976 }
15978 /* Support for overriding other tuning flags. */
15980 static void
15983 {
15984 tune->extra_tuning_flags
15986 aarch64_tuning_flags,
15989 }
15991 /* Parse the sve_width tuning moverride string in TUNE_STRING.
15992 Accept the valid SVE vector widths allowed by
15993 aarch64_sve_vector_bits_enum and use it to override sve_width
15994 in TUNE. */
15996 static void
15999 {
16004 {
16007 }
16009 {
16018 }
16020 }
16022 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
16023 we understand. If it is, extract the option string and handoff to
16024 the appropriate function. */
16026 void
16030 {
16036 {
16039 }
16041 /* Get the length of the option name. */
16043 /* Skip the '=' to get to the option string. */
16044 option_part++;
16047 {
16049 {
16052 }
16053 }
16057 }
16059 /* A checking mechanism for the implementation of the tls size. */
16061 static void
16063 {
16068 {
16070 /* Both the default and maximum TLS size allowed under tiny is 1M which
16071 needs two instructions to address, so we clamp the size to 24. */
16076 /* The maximum TLS size allowed under small is 4G. */
16081 /* The maximum TLS size allowed under large is 16E.
16082 FIXME: 16E should be 64bit, we only support 48bit offset now. */
16088 }
16091 }
16093 /* Parse STRING looking for options in the format:
16094 string :: option:string
16095 option :: name=substring
16096 name :: {a-z}
16097 substring :: defined by option. */
16099 static void
16102 {
16113 {
16115 /* Make this substring look like a string. */
16119 }
16121 /* One last option to parse. */
16124 }
16126 /* Adjust CURRENT_TUNE (a generic tuning struct) with settings that
16127 are best for a generic target with the currently-enabled architecture
16128 extensions. */
16129 static void
16131 {
16132 /* Neoverse V1 is the only core that is known to benefit from
16133 AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. There is therefore no
16134 point enabling it for SVE2 and above. */
16136 current_tune.extra_tuning_flags
16138 }
16140 static void
16142 {
16144 {
16145 opts->x_aarch64_branch_protection_string
16147 }
16149 /* PR 70044: We have to be careful about being called multiple times for the
16150 same function. This means all changes should be repeatable. */
16152 /* Set aarch64_use_frame_pointer based on -fno-omit-frame-pointer.
16153 Disable the frame pointer flag so the mid-end will not use a frame
16154 pointer in leaf functions in order to support -fomit-leaf-frame-pointer.
16155 Set x_flag_omit_frame_pointer to the special value 2 to differentiate
16156 between -fomit-frame-pointer (1) and -fno-omit-frame-pointer (2). */
16161 /* If not optimizing for size, set the default
16162 alignment to what the target wants. */
16164 {
16171 }
16173 /* We default to no pc-relative literal loads. */
16177 /* If -mpc-relative-literal-loads is set on the command line, this
16178 implies that the user asked for PC relative literal loads. */
16182 /* In the tiny memory model it makes no sense to disallow PC relative
16183 literal pool loads. */
16188 /* When enabling the lower precision Newton series for the square root, also
16189 enable it for the reciprocal square root, since the latter is an
16190 intermediary step for the former. */
16193 }
16195 /* 'Unpack' up the internal tuning structs and update the options
16196 in OPTS. The caller must have set up selected_tune and selected_arch
16197 as all the other target-specific codegen decisions are
16198 derived from them. */
16200 void
16202 {
16205 /* Make a copy of the tuning parameters attached to the core, which
16206 we may later overwrite. */
16216 /* This target defaults to strict volatile bitfields. */
16222 {
16225 aarch64_stack_protector_guard_offset_str);
16226 }
16231 {
16233 "%<-mstack-protector-guard-reg%> must be used "
16235 }
16238 {
16241 }
16244 {
16253 }
16260 {
16272 }
16274 /* We don't mind passing in global_options_set here as we don't use
16275 the *options_set structs anyway. */
16279 /* If using Advanced SIMD only for autovectorization disable SVE vector costs
16280 comparison. */
16285 /* Set up parameters to be used in prefetching algorithm. Do not
16286 override the defaults unless we are tuning for a core we have
16287 researched values for. */
16290 param_simultaneous_prefetches,
16294 param_l1_cache_size,
16298 param_l1_cache_line_size,
16302 param_l2_cache_size,
16309 param_prefetch_minimum_stride,
16312 /* Use the alternative scheduling-pressure algorithm by default. */
16314 param_sched_pressure_algorithm,
16315 SCHED_PRESSURE_MODEL);
16317 /* Validate the guard size. */
16325 /* Enforce that interval is the same size as size so the mid-end does the
16326 right thing. */
16328 param_stack_clash_protection_probe_interval,
16329 guard_size);
16331 /* The maybe_set calls won't update the value if the user has explicitly set
16332 one. Which means we need to validate that probing interval and guard size
16333 are equal. */
16334 int probe_interval
16340 /* Enable sw prefetching at specified optimization level for
16341 CPUS that have prefetch. Lower optimization level threshold by 1
16342 when profiling is enabled. */
16357 }
16359 /* Print a hint with a suggestion for a core or architecture name that
16360 most closely resembles what the user passed in STR. ARCH is true if
16361 the user is asking for an architecture name. ARCH is false if the user
16362 is asking for a core name. */
16364 static void
16366 {
16372 #ifdef HAVE_LOCAL_CPU_DETECT
16373 /* Add also "native" as possible value. */
16376 #endif
16383 else
16387 }
16389 /* Print a hint with a suggestion for a core name that most closely resembles
16390 what the user passed in STR. */
16394 {
16396 }
16398 /* Print a hint with a suggestion for an architecture name that most closely
16399 resembles what the user passed in STR. */
16403 {
16405 }
16408 /* Print a hint with a suggestion for an extension name
16409 that most closely resembles what the user passed in STR. */
16411 void
16413 {
16421 else
16425 }
16427 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
16428 specified in STR and throw errors if appropriate. Put the results if
16429 they are valid in RES and ISA_FLAGS. Return whether the option is
16430 valid. */
16432 static bool
16435 {
16437 enum aarch64_parse_opt_result parse_res
16444 {
16459 }
16462 }
16464 /* Straight line speculation indicators. */
16465 enum aarch64_sls_hardening_type
16466 {
16471 };
16474 /* Return whether we should mitigatate Straight Line Speculation for the RET
16475 and BR instructions. */
16476 bool
16478 {
16480 }
16482 /* Return whether we should mitigatate Straight Line Speculation for the BLR
16483 instruction. */
16484 bool
16486 {
16488 }
16490 /* As of yet we only allow setting these options globally, in the future we may
16491 allow setting them per function. */
16492 static void
16494 {
16499 {
16502 }
16504 {
16507 }
16516 {
16522 {
16525 }
16526 else
16527 {
16530 }
16532 }
16535 }
16537 /* Parses CONST_STR for branch protection features specified in
16538 aarch64_branch_protect_types, and set any global variables required. Returns
16539 the parsing result and assigns LAST_STR to the last processed token from
16540 CONST_STR so that it can be used for error reporting. */
16542 static enum
16545 {
16552 else
16553 {
16555 /* Reset the branch protection features to their defaults. */
16559 {
16562 /* Search for this type. */
16564 {
16566 {
16571 }
16572 else
16573 type++;
16574 }
16576 {
16578 /* Loop through each token until we find one that isn't a
16579 subtype. */
16581 {
16584 /* Search for the subtype. */
16587 {
16589 {
16594 }
16595 else
16596 subtype++;
16597 }
16598 }
16599 }
16602 }
16603 }
16604 /* Copy the last processed token into the argument to pass it back.
16605 Used by option and attribute validation to print the offending token. */
16607 {
16610 }
16612 {
16613 /* If needed, alloc the accepted string then copy in const_str.
16614 Used by override_option_after_change_1. */
16617 BRANCH_PROTECT_STR_MAX
16621 /* Forcibly null-terminate. */
16623 }
16625 }
16627 static bool
16629 {
16639 }
16641 /* Validate a command-line -march option. Parse the arch and extensions
16642 (if any) specified in STR and throw errors if appropriate. Put the
16643 results, if they are valid, in RES and ISA_FLAGS. Return whether the
16644 option is valid. */
16646 static bool
16649 {
16651 enum aarch64_parse_opt_result parse_res
16658 {
16673 }
16676 }
16678 /* Validate a command-line -mtune option. Parse the cpu
16679 specified in STR and throw errors if appropriate. Put the
16680 result, if it is valid, in RES. Return whether the option is
16681 valid. */
16683 static bool
16685 {
16686 enum aarch64_parse_opt_result parse_res
16693 {
16703 }
16705 }
16707 /* Return the CPU corresponding to the enum CPU.
16708 If it doesn't specify a cpu, return the default. */
16712 {
16716 /* The & 0x3f is to extract the bottom 6 bits that encode the
16717 default cpu as selected by the --with-cpu GCC configure option
16718 in config.gcc.
16719 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
16720 flags mechanism should be reworked to make it more sane. */
16722 }
16724 /* Return the architecture corresponding to the enum ARCH.
16725 If it doesn't specify a valid architecture, return the default. */
16729 {
16736 }
16738 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
16740 static poly_uint16
16742 {
16743 /* 128-bit SVE and Advanced SIMD modes use different register layouts
16744 on big-endian targets, so we would need to forbid subregs that convert
16745 from one to the other. By default a reinterpret sequence would then
16746 involve a store to memory in one mode and a load back in the other.
16747 Even if we optimize that sequence using reverse instructions,
16748 it would still be a significant potential overhead.
16750 For now, it seems better to generate length-agnostic code for that
16751 case instead. */
16755 else
16757 }
16759 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
16760 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
16761 tuning structs. In particular it must set selected_tune and
16762 aarch64_isa_flags that define the available ISA features and tuning
16763 decisions. It must also set selected_arch as this will be used to
16764 output the .arch asm tags for each function. */
16766 static void
16768 {
16787 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
16788 If either of -march or -mtune is given, they override their
16789 respective component of -mcpu. */
16801 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16802 SUBTARGET_OVERRIDE_OPTIONS;
16803 #endif
16805 /* If the user did not specify a processor, choose the default
16806 one for them. This will be the CPU set during configuration using
16807 --with-cpu, otherwise it is "generic". */
16809 {
16811 {
16815 }
16816 else
16817 {
16818 /* Get default configure-time CPU. */
16821 }
16825 }
16826 /* If both -mcpu and -march are specified check that they are architecturally
16827 compatible, warn if they're not and prefer the -march ISA flags. */
16829 {
16831 {
16833 aarch64_cpu_string,
16834 aarch64_arch_string);
16835 }
16840 }
16841 else
16842 {
16843 /* -mcpu but no -march. */
16850 }
16852 /* Set the arch as well as we will need it when outputing
16853 the .arch directive in assembly. */
16855 {
16858 }
16864 {
16865 #ifdef TARGET_ENABLE_BTI
16867 #else
16869 #endif
16870 }
16872 /* Return address signing is currently not supported for ILP32 targets. For
16873 LP64 targets use the configured option in the absence of a command-line
16874 option for -mbranch-protection. */
16876 {
16877 #ifdef TARGET_ENABLE_PAC_RET
16879 #else
16881 #endif
16882 }
16884 #ifndef HAVE_AS_MABI_OPTION
16885 /* The compiler may have been configured with 2.23.* binutils, which does
16886 not have support for ILP32. */
16889 #endif
16891 /* Convert -msve-vector-bits to a VG count. */
16897 /* Make sure we properly set up the explicit options. */
16906 /* The pass to insert speculation tracking runs before
16907 shrink-wrapping and the latter does not know how to update the
16908 tracking status. So disable it in this case. */
16914 /* Save these options as the default ones in case we push and pop them later
16915 while processing functions with potential target attributes. */
16916 target_option_default_node = target_option_current_node
16918 }
16920 /* Implement targetm.override_options_after_change. */
16922 static void
16924 {
16926 }
16928 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
16931 {
16934 else
16936 }
16940 {
16944 }
16946 void
16948 {
16950 }
16952 /* A checking mechanism for the implementation of the various code models. */
16953 static void
16955 {
16958 {
16965 {
16966 #ifdef HAVE_AS_SMALL_PIC_RELOCS
16968 ? AARCH64_CMODEL_SMALL_PIC
16970 #else
16972 #endif
16973 }
16986 }
16987 }
16989 /* Implement TARGET_OPTION_SAVE. */
16991 static void
16994 {
16996 ptr->x_aarch64_branch_protection_string
16998 }
17000 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
17001 using the information saved in PTR. */
17003 static void
17007 {
17014 else
17017 opts->x_aarch64_branch_protection_string
17020 {
17022 NULL);
17023 }
17026 }
17028 /* Implement TARGET_OPTION_PRINT. */
17030 static void
17032 {
17043 }
17047 void
17049 {
17051 }
17053 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
17054 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
17055 make sure optab availability predicates are recomputed when necessary. */
17057 void
17059 {
17064 else
17066 }
17068 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
17069 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
17070 of the function, if such exists. This function may be called multiple
17071 times on a single function so use aarch64_previous_fndecl to avoid
17072 setting up identical state. */
17074 static void
17076 {
17080 tree old_tree = (aarch64_previous_fndecl
17086 /* If current function has no attributes but the previous one did,
17087 use the default node. */
17091 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
17092 the default have been handled by aarch64_save_restore_target_globals from
17093 aarch64_pragma_target_parse. */
17099 /* First set the target options. */
17104 }
17106 /* Enum describing the various ways we can handle attributes.
17107 In many cases we can reuse the generic option handling machinery. */
17109 enum aarch64_attr_opt_type
17110 {
17114 aarch64_attr_custom /* Attribute requires a custom handling function. */
17115 };
17117 /* All the information needed to handle a target attribute.
17118 NAME is the name of the attribute.
17119 ATTR_TYPE specifies the type of behavior of the attribute as described
17120 in the definition of enum aarch64_attr_opt_type.
17121 ALLOW_NEG is true if the attribute supports a "no-" form.
17122 HANDLER is the function that takes the attribute string as an argument
17123 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
17124 OPT_NUM is the enum specifying the option that the attribute modifies.
17125 This is needed for attributes that mirror the behavior of a command-line
17126 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
17127 aarch64_attr_enum. */
17129 struct aarch64_attribute_info
17130 {
17136 };
17138 /* Handle the ARCH_STR argument to the arch= target attribute. */
17140 static bool
17142 {
17145 enum aarch64_parse_opt_result parse_res
17149 {
17154 }
17157 {
17172 }
17175 }
17177 /* Handle the argument CPU_STR to the cpu= target attribute. */
17179 static bool
17181 {
17184 enum aarch64_parse_opt_result parse_res
17188 {
17196 }
17199 {
17214 }
17217 }
17219 /* Handle the argument STR to the branch-protection= attribute. */
17221 static bool
17223 {
17229 {
17240 /* Fall through. */
17245 }
17248 }
17250 /* Handle the argument STR to the tune= target attribute. */
17252 static bool
17254 {
17256 enum aarch64_parse_opt_result parse_res
17260 {
17265 }
17268 {
17275 }
17278 }
17280 /* Parse an architecture extensions target attribute string specified in STR.
17281 For example "+fp+nosimd". Show any errors if needed. Return TRUE
17282 if successful. Update aarch64_isa_flags to reflect the ISA features
17283 modified. */
17285 static bool
17287 {
17291 /* We allow "+nothing" in the beginning to clear out all architectural
17292 features if the user wants to handpick specific features. */
17294 {
17297 }
17303 {
17306 }
17309 {
17321 }
17324 }
17326 /* The target attributes that we support. On top of these we also support just
17327 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
17328 handled explicitly in aarch64_process_one_target_attr. */
17331 {
17333 OPT_mgeneral_regs_only },
17335 OPT_mfix_cortex_a53_835769 },
17337 OPT_mfix_cortex_a53_843419 },
17341 OPT_momit_leaf_frame_pointer },
17344 OPT_march_ },
17347 OPT_mtune_ },
17351 OPT_msign_return_address_ },
17353 OPT_moutline_atomics},
17355 };
17357 /* Parse ARG_STR which contains the definition of one target attribute.
17358 Show appropriate errors if any or return true if the attribute is valid. */
17360 static bool
17362 {
17368 {
17371 }
17376 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
17377 It is easier to detect and handle it explicitly here rather than going
17378 through the machinery for the rest of the target attributes in this
17379 function. */
17384 {
17387 }
17390 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
17391 and point ARG to "foo". */
17393 {
17395 arg++;
17396 }
17400 {
17401 /* If the names don't match up, or the user has given an argument
17402 to an attribute that doesn't accept one, or didn't give an argument
17403 to an attribute that expects one, fail to match. */
17412 {
17415 }
17417 /* If the name matches but the attribute does not allow "no-" versions
17418 then we can't match. */
17420 {
17423 }
17426 {
17427 /* Has a custom handler registered.
17428 For example, cpu=, arch=, tune=. */
17435 /* Either set or unset a boolean option. */
17437 {
17445 }
17446 /* Set or unset a bit in the target_flags. aarch64_handle_option
17447 should know what mask to apply given the option number. */
17449 {
17451 /* We only need to specify the option number.
17452 aarch64_handle_option will know which mask to apply. */
17458 }
17459 /* Use the option setting machinery to set an option to an enum. */
17461 {
17468 {
17471 global_dc);
17472 }
17473 else
17474 {
17476 }
17478 }
17481 }
17482 }
17484 /* If we reached here we either have found an attribute and validated
17485 it or didn't match any. If we matched an attribute but its arguments
17486 were malformed we will have returned false already. */
17488 }
17490 /* Count how many times the character C appears in
17491 NULL-terminated string STR. */
17493 static unsigned int
17495 {
17498 {
17500 res++;
17502 str++;
17503 }
17506 }
17508 /* Parse the tree in ARGS that contains the target attribute information
17509 and update the global target options space. */
17511 bool
17513 {
17515 {
17516 do
17517 {
17520 {
17523 }
17528 }
17531 {
17534 }
17541 {
17544 }
17546 /* Used to catch empty spaces between commas i.e.
17547 attribute ((target ("attr1,,attr2"))). */
17550 /* Handle multiple target attributes separated by ','. */
17555 {
17556 num_attrs++;
17558 {
17561 }
17564 }
17567 {
17570 }
17573 }
17575 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
17576 process attribute ((target ("..."))). */
17578 static bool
17580 {
17583 tree old_optimize;
17587 /* If what we're processing is the current pragma string then the
17588 target option node is already stored in target_option_current_node
17589 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
17590 having to re-parse the string. This is especially useful to keep
17591 arm_neon.h compile times down since that header contains a lot
17592 of intrinsics enclosed in pragmas. */
17594 {
17597 }
17600 old_optimize
17604 /* If the function changed the optimization levels as well as setting
17605 target options, start with the optimizations specified. */
17610 /* Save the current target options to restore at the end. */
17613 /* If fndecl already has some target attributes applied to it, unpack
17614 them so that we add this attribute on top of them, rather than
17615 overwriting them. */
17617 {
17623 existing_options);
17624 }
17625 else
17631 /* Set up any additional state. */
17633 {
17635 /* Initialize SIMD builtins if we haven't already.
17636 Set current_target_pragma to NULL for the duration so that
17637 the builtin initialization code doesn't try to tag the functions
17638 being built with the attributes specified by any current pragma, thus
17639 going into an infinite recursion. */
17641 {
17646 }
17649 }
17650 else
17657 {
17662 }
17670 }
17672 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
17673 tri-bool options (yes, no, don't care) and the default value is
17674 DEF, determine whether to reject inlining. */
17676 static bool
17679 {
17680 /* If the callee doesn't care, always allow inlining. */
17684 /* If the caller doesn't care, always allow inlining. */
17688 /* Otherwise, allow inlining if either the callee and caller values
17689 agree, or if the callee is using the default value. */
17691 }
17693 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
17694 to inline CALLEE into CALLER based on target-specific info.
17695 Make sure that the caller and callee have compatible architectural
17696 features. Then go through the other possible target attributes
17697 and see if they can block inlining. Try not to reject always_inline
17698 callees unless they are incompatible architecturally. */
17700 static bool
17702 {
17714 /* Callee's ISA flags should be a subset of the caller's. */
17719 /* Allow non-strict aligned functions inlining into strict
17720 aligned ones. */
17730 /* If the architectural features match up and the callee is always_inline
17731 then the other attributes don't matter. */
17743 /* Honour explicit requests to workaround errata. */
17756 /* If the user explicitly specified -momit-leaf-frame-pointer for the
17757 caller and calle and they don't match up, reject inlining. */
17764 /* If the callee has specific tuning overrides, respect them. */
17769 /* If the user specified tuning override strings for the
17770 caller and callee and they don't match up, reject inlining.
17771 We just do a string compare here, we don't analyze the meaning
17772 of the string, as it would be too costly for little gain. */
17780 }
17782 /* Return the ID of the TLDESC ABI, initializing the descriptor if hasn't
17783 been already. */
17785 unsigned int
17787 {
17790 {
17791 HARD_REG_SET full_reg_clobbers;
17798 }
17800 }
17802 /* Return true if SYMBOL_REF X binds locally. */
17804 static bool
17806 {
17810 }
17812 /* Return true if SYMBOL_REF X is thread local */
17813 static bool
17815 {
17824 }
17826 /* Classify a TLS symbol into one of the TLS kinds. */
17827 enum aarch64_symbol_type
17829 {
17833 {
17840 {
17846 }
17857 else
17866 }
17867 }
17869 /* Return the correct method for accessing X + OFFSET, where X is either
17870 a SYMBOL_REF or LABEL_REF. */
17872 enum aarch64_symbol_type
17874 {
17878 {
17880 {
17895 }
17896 }
17899 {
17904 {
17907 /* With -fPIC non-local symbols use the GOT. For orthogonality
17908 always use the GOT for extern weak symbols. */
17913 /* When we retrieve symbol + offset address, we have to make sure
17914 the offset does not cause overflow of the final address. But
17915 we have no way of knowing the address of symbol at compile time
17916 so we can't accurately say if the distance between the PC and
17917 symbol + offset is outside the addressible range of +/-1MB in the
17918 TINY code model. So we limit the maximum offset to +/-64KB and
17919 assume the offset to the symbol is not larger than +/-(1MB - 64KB).
17920 If offset_within_block_p is true we allow larger offsets. */
17936 /* Same reasoning as the tiny code model, but the offset cap here is
17937 1MB, allowing +/-3.9GB for the offset to the symbol. */
17945 /* This is alright even in PIC code as the constant
17946 pool reference is always PC relative and within
17947 the same translation unit. */
17950 else
17955 }
17956 }
17958 /* By default push everything into the constant pool. */
17960 }
17962 bool
17964 {
17966 }
17968 bool
17970 {
17971 poly_int64 offset;
17977 }
17979 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
17980 that should be rematerialized rather than spilled. */
17982 static bool
17984 {
17985 /* Support CSE and rematerialization of common constants. */
17990 /* Only accept variable-length vector constants if they can be
17991 handled directly.
17993 ??? It would be possible (but complex) to handle rematerialization
17994 of other constants via secondary reloads. */
17998 /* Otherwise, accept any CONST_VECTOR that, if all else fails, can at
17999 least be forced to memory and loaded from there. */
18003 /* Do not allow vector struct mode constants for Advanced SIMD.
18004 We could support 0 and -1 easily, but they need support in
18005 aarch64-simd.md. */
18013 /* Accept polynomial constants that can be calculated by using the
18014 destination of a move as the sole temporary. Constants that
18015 require a second temporary cannot be rematerialized (they can't be
18016 forced to memory and also aren't legitimate constants). */
18017 poly_int64 offset;
18021 /* If an offset is being added to something else, we need to allow the
18022 base to be moved into the destination register, meaning that there
18023 are no free temporaries for the offset. */
18028 /* Do not allow const (plus (anchor_symbol, const_int)). */
18032 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
18033 so spilling them is better than rematerialization. */
18037 /* Label references are always constant. */
18042 }
18044 rtx
18046 {
18052 /* Can return in any reg. */
18055 }
18057 /* On AAPCS systems, this is the "struct __va_list". */
18060 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
18061 Return the type to use as __builtin_va_list.
18063 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
18065 struct __va_list
18066 {
18067 void *__stack;
18068 void *__gr_top;
18069 void *__vr_top;
18070 int __gr_offs;
18071 int __vr_offs;
18072 }; */
18074 static tree
18076 {
18077 tree va_list_name;
18080 /* Create the type. */
18082 /* Give it the required name. */
18084 TYPE_DECL,
18086 va_list_type);
18091 /* Create the fields. */
18094 ptr_type_node);
18097 ptr_type_node);
18100 ptr_type_node);
18103 integer_type_node);
18106 integer_type_node);
18108 /* Tell tree-stdarg pass about our internal offset fields.
18109 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
18110 purpose to identify whether the code is updating va_list internal
18111 offset fields through irregular way. */
18133 /* Compute its layout. */
18137 }
18139 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
18140 static void
18142 {
18146 tree t;
18160 {
18163 }
18172 NULL_TREE);
18174 NULL_TREE);
18176 NULL_TREE);
18178 NULL_TREE);
18180 NULL_TREE);
18182 /* Emit code to initialize STACK, which points to the next varargs stack
18183 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
18184 by named arguments. STACK is 8-byte aligned. */
18191 /* Emit code to initialize GRTOP, the top of the GR save area.
18192 virtual_incoming_args_rtx should have been 16 byte aligned. */
18197 /* Emit code to initialize VRTOP, the top of the VR save area.
18198 This address is gr_save_area_bytes below GRTOP, rounded
18199 down to the next 16-byte boundary. */
18209 /* Emit code to initialize GROFF, the offset from GRTOP of the
18210 next GPR argument. */
18215 /* Likewise emit code to initialize VROFF, the offset from FTOP
18216 of the next VR argument. */
18220 }
18222 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
18224 static tree
18227 {
18228 tree addr;
18234 machine_mode mode;
18258 align
18265 {
18266 /* No frontends can create types with variable-sized modes, so we
18267 shouldn't be asked to pass or return them. */
18270 /* TYPE passed in fp/simd registers. */
18282 {
18285 }
18288 {
18290 }
18291 }
18292 else
18293 {
18294 /* TYPE passed in general registers. */
18303 {
18308 }
18312 {
18314 }
18315 }
18317 /* Get a local temporary for the field value. */
18320 /* Emit code to branch if off >= 0. */
18326 {
18327 /* Emit: offs = (offs + 15) & -16. */
18333 }
18334 else
18337 /* Update ap.__[g|v]r_offs */
18342 /* String up. */
18346 /* [cond2] if (ap.__[g|v]r_offs > 0) */
18351 /* String up: make sure the assignment happens before the use. */
18355 /* Prepare the trees handling the argument that is passed on the stack;
18356 the top level node will store in ON_STACK. */
18359 {
18360 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
18365 }
18366 else
18368 /* Advance ap.__stack */
18373 /* String up roundup and advance. */
18376 /* String up with arg */
18378 /* Big-endianness related address adjustment. */
18381 {
18385 }
18390 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
18400 {
18401 /* type ha; // treat as "struct {ftype field[n];}"
18402 ... [computing offs]
18403 for (i = 0; i <nregs; ++i, offs += 16)
18404 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
18405 return ha; */
18409 /* Declare a local variable. */
18413 /* Establish the base type. */
18415 {
18438 {
18442 }
18446 }
18448 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
18457 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
18459 {
18469 }
18473 }
18483 }
18485 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
18487 static void
18491 {
18493 CUMULATIVE_ARGS local_cum;
18497 /* The caller has advanced CUM up to, but not beyond, the last named
18498 argument. Advance a local copy of CUM past the last "real" named
18499 argument, to find out how many registers are left over. */
18503 /* Found out how many registers we need to save.
18504 Honor tree-stdvar analysis results. */
18513 {
18516 }
18519 {
18521 {
18524 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
18532 }
18534 {
18535 /* We can't use move_block_from_reg, because it will use
18536 the wrong mode, storing D regs only. */
18540 /* Set OFF to the offset from virtual_incoming_args_rtx of
18541 the first vector register. The VR save area lies below
18542 the GR one, and is aligned to 16 bytes. */
18549 {
18557 }
18558 }
18559 }
18561 /* We don't save the size into *PRETEND_SIZE because we want to avoid
18562 any complication of having crtl->args.pretend_args_size changed. */
18567 }
18569 static void
18571 {
18574 {
18576 {
18579 }
18580 }
18583 {
18586 }
18588 /* Only allow the FFR and FFRT to be accessed via special patterns. */
18592 /* When tracking speculation, we need a couple of call-clobbered registers
18593 to track the speculation state. It would be nice to just use
18594 IP0 and IP1, but currently there are numerous places that just
18595 assume these registers are free for other uses (eg pointer
18596 authentication). */
18598 {
18603 }
18604 }
18606 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. */
18608 bool
18610 {
18611 /* For records we're passed a FIELD_DECL, for arrays we're passed
18612 an ARRAY_TYPE. In both cases we're interested in the TREE_TYPE. */
18615 /* Assign BLKmode to anything that contains multiple SVE predicates.
18616 For structures, the "multiple" case is indicated by MODE being
18617 VOIDmode. */
18620 {
18625 }
18628 }
18630 /* Bitmasks that indicate whether earlier versions of GCC would have
18631 taken a different path through the ABI logic. This should result in
18632 a -Wpsabi warning if the earlier path led to a different ABI decision.
18634 WARN_PSABI_EMPTY_CXX17_BASE
18635 Indicates that the type includes an artificial empty C++17 base field
18636 that, prior to GCC 10.1, would prevent the type from being treated as
18637 a HFA or HVA. See PR94383 for details.
18639 WARN_PSABI_NO_UNIQUE_ADDRESS
18640 Indicates that the type includes an empty [[no_unique_address]] field
18641 that, prior to GCC 10.1, would prevent the type from being treated as
18642 a HFA or HVA. */
18646 /* Walk down the type tree of TYPE counting consecutive base elements.
18647 If *MODEP is VOIDmode, then set it to the first valid floating point
18648 type. If a non-floating point type is found, or if a floating point
18649 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
18650 otherwise return the count in the sub-tree.
18652 The WARN_PSABI_FLAGS argument allows the caller to check whether this
18653 function has changed its behavior relative to earlier versions of GCC.
18654 Normally the argument should be nonnull and point to a zero-initialized
18655 variable. The function then records whether the ABI decision might
18656 be affected by a known fix to the ABI logic, setting the associated
18657 WARN_PSABI_* bits if so.
18659 When the argument is instead a null pointer, the function tries to
18660 simulate the behavior of GCC before all such ABI fixes were made.
18661 This is useful to check whether the function returns something
18662 different after the ABI fixes. */
18663 static int
18666 {
18667 machine_mode mode;
18668 HOST_WIDE_INT size;
18674 {
18704 /* Use V2SImode and V4SImode as representatives of all 64-bit
18705 and 128-bit vector types. */
18708 {
18717 }
18722 /* Vector modes are considered to be opaque: two vectors are
18723 equivalent for the purposes of being homogeneous aggregates
18724 if they are the same size. */
18731 {
18735 /* Can't handle incomplete types nor sizes that are not
18736 fixed. */
18742 warn_psabi_flags);
18744 || !index
18755 /* There must be no padding. */
18761 }
18764 {
18767 tree field;
18769 /* Can't handle incomplete types nor sizes that are not
18770 fixed. */
18776 {
18781 {
18782 /* See whether this is something that earlier versions of
18783 GCC failed to ignore. */
18790 else
18791 /* No compatibility problem. */
18794 /* Simulate the old behavior when WARN_PSABI_FLAGS is null. */
18796 {
18799 }
18800 }
18803 warn_psabi_flags);
18807 }
18809 /* There must be no padding. */
18815 }
18819 {
18820 /* These aren't very interesting except in a degenerate case. */
18823 tree field;
18825 /* Can't handle incomplete types nor sizes that are not
18826 fixed. */
18832 {
18837 warn_psabi_flags);
18841 }
18843 /* There must be no padding. */
18849 }
18853 }
18856 }
18858 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
18859 type as described in AAPCS64 \S 4.1.2.
18861 See the comment above aarch64_composite_type_p for the notes on MODE. */
18863 static bool
18865 machine_mode mode)
18866 {
18870 {
18874 }
18877 {
18878 /* Rely only on the type, not the mode, when processing SVE types. */
18880 /* Leave later code to report an error if SVE is disabled. */
18882 else
18884 }
18886 {
18887 /* 64-bit and 128-bit vectors should only acquire an SVE mode if
18888 they are being treated as scalable AAPCS64 types. */
18891 }
18893 }
18895 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
18896 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
18897 array types. The C99 floating-point complex types are also considered
18898 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
18899 types, which are GCC extensions and out of the scope of AAPCS64, are
18900 treated as composite types here as well.
18902 Note that MODE itself is not sufficient in determining whether a type
18903 is such a composite type or not. This is because
18904 stor-layout.c:compute_record_mode may have already changed the MODE
18905 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
18906 structure with only one field may have its MODE set to the mode of the
18907 field. Also an integer mode whose size matches the size of the
18908 RECORD_TYPE type may be used to substitute the original mode
18909 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
18910 solely relied on. */
18912 static bool
18914 machine_mode mode)
18915 {
18928 }
18930 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
18931 shall be passed or returned in simd/fp register(s) (providing these
18932 parameter passing registers are available).
18934 Upon successful return, *COUNT returns the number of needed registers,
18935 *BASE_MODE returns the mode of the individual register and when IS_HA
18936 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
18937 floating-point aggregate or a homogeneous short-vector aggregate.
18939 SILENT_P is true if the function should refrain from reporting any
18940 diagnostics. This should only be used if the caller is certain that
18941 any ABI decisions would eventually come through this function with
18942 SILENT_P set to false. */
18944 static bool
18946 const_tree type,
18951 {
18959 {
18962 }
18964 {
18968 }
18970 {
18975 {
18980 && warn_psabi
18981 && warn_psabi_flags
18985 {
18990 /* Use TYPE_MAIN_VARIANT to strip any redundant const
18991 qualification. */
18994 "type %qT with %<[[no_unique_address]]%> members "
18999 "type %qT when C++17 is enabled changed to match "
19002 }
19006 }
19007 else
19009 }
19010 else
19016 }
19018 /* Implement TARGET_STRUCT_VALUE_RTX. */
19020 static rtx
19023 {
19025 }
19027 /* Implements target hook vector_mode_supported_p. */
19028 static bool
19030 {
19033 }
19035 /* Return the full-width SVE vector mode for element mode MODE, if one
19036 exists. */
19037 opt_machine_mode
19039 {
19041 {
19060 }
19061 }
19063 /* Return the 128-bit Advanced SIMD vector mode for element mode MODE,
19064 if it exists. */
19065 opt_machine_mode
19067 {
19069 {
19088 }
19089 }
19091 /* Return appropriate SIMD container
19092 for MODE within a vector of WIDTH bits. */
19093 static machine_mode
19095 {
19103 {
19106 else
19108 {
19123 }
19124 }
19126 }
19128 /* Compare an SVE mode SVE_M and an Advanced SIMD mode ASIMD_M
19129 and return whether the SVE mode should be preferred over the
19130 Advanced SIMD one in aarch64_autovectorize_vector_modes. */
19131 static bool
19133 {
19134 /* Take into account the aarch64-autovec-preference param if non-zero. */
19143 /* The preference in case of a tie in costs. */
19151 /* If the CPU information does not have an SVE width registered use the
19152 generic poly_int comparison that prefers SVE. If a preference is
19153 explicitly requested avoid this path. */
19155 && !prefer_asimd
19159 /* Otherwise estimate the runtime width of the modes involved. */
19163 /* Preferring SVE means picking it first unless the Advanced SIMD mode
19164 is clearly wider. */
19167 /* Conversely, preferring Advanced SIMD means picking SVE only if SVE
19168 is clearly wider. */
19172 /* In the default case prefer Advanced SIMD over SVE in case of a tie. */
19174 }
19176 /* Return 128-bit container as the preferred SIMD mode for MODE. */
19177 static machine_mode
19179 {
19180 /* Take into account explicit auto-vectorization ISA preferences through
19181 aarch64_cmp_autovec_modes. */
19187 }
19189 /* Return a list of possible vector sizes for the vectorizer
19190 to iterate over. */
19191 static unsigned int
19193 {
19195 /* Try using full vectors for all element types. */
19196 VNx16QImode,
19198 /* Try using 16-bit containers for 8-bit elements and full vectors
19199 for wider elements. */
19200 VNx8QImode,
19202 /* Try using 32-bit containers for 8-bit and 16-bit elements and
19203 full vectors for wider elements. */
19204 VNx4QImode,
19206 /* Try using 64-bit containers for all element types. */
19207 VNx2QImode
19208 };
19211 /* Try using 128-bit vectors for all element types. */
19212 V16QImode,
19214 /* Try using 64-bit vectors for 8-bit elements and 128-bit vectors
19215 for wider elements. */
19216 V8QImode,
19218 /* Try using 64-bit vectors for 16-bit elements and 128-bit vectors
19219 for wider elements.
19221 TODO: We could support a limited form of V4QImode too, so that
19222 we use 32-bit vectors for 8-bit elements. */
19223 V4HImode,
19225 /* Try using 64-bit vectors for 32-bit elements and 128-bit vectors
19226 for 64-bit elements.
19228 TODO: We could similarly support limited forms of V2QImode and V2HImode
19229 for this case. */
19230 V2SImode
19231 };
19233 /* Try using N-byte SVE modes only after trying N-byte Advanced SIMD mode.
19234 This is because:
19236 - If we can't use N-byte Advanced SIMD vectors then the placement
19237 doesn't matter; we'll just continue as though the Advanced SIMD
19238 entry didn't exist.
19240 - If an SVE main loop with N bytes ends up being cheaper than an
19241 Advanced SIMD main loop with N bytes then by default we'll replace
19242 the Advanced SIMD version with the SVE one.
19244 - If an Advanced SIMD main loop with N bytes ends up being cheaper
19245 than an SVE main loop with N bytes then by default we'll try to
19246 use the SVE loop to vectorize the epilogue instead. */
19255 {
19260 else
19262 }
19267 /* Consider enabling VECT_COMPARE_COSTS for SVE, both so that we
19268 can compare SVE against Advanced SIMD and so that we can compare
19269 multiple SVE vectorization approaches against each other. There's
19270 not really any point doing this for Advanced SIMD only, since the
19271 first mode that works should always be the best. */
19275 }
19277 /* Implement TARGET_MANGLE_TYPE. */
19281 {
19282 /* The AArch64 ABI documents say that "__va_list" has to be
19283 mangled as if it is in the "std" namespace. */
19287 /* Half-precision floating point types. */
19289 {
19292 else
19294 }
19296 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
19297 builtin types. */
19299 {
19304 }
19306 /* Use the default mangling. */
19308 }
19310 /* Implement TARGET_VERIFY_TYPE_CONTEXT. */
19312 static bool
19315 {
19317 }
19319 /* Find the first rtx_insn before insn that will generate an assembly
19320 instruction. */
19324 {
19328 do
19329 {
19331 }
19335 }
19337 static bool
19339 {
19341 /* A number of these may be AArch32 only. */
19346 };
19349 {
19352 }
19355 }
19357 /* Check if there is a register dependency between a load and the insn
19358 for which we hold recog_data. */
19360 static bool
19362 {
19363 rtx load_reg;
19373 {
19379 }
19381 }
19384 /* When working around the Cortex-A53 erratum 835769,
19385 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
19386 instruction and has a preceding memory instruction such that a NOP
19387 should be inserted between them. */
19389 bool
19391 {
19394 rtx body;
19407 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
19408 Restore recog state to INSN to avoid state corruption. */
19416 /* If the previous insn is a memory op and there is no dependency between
19417 it and the DImode madd, emit a NOP between them. If body is NULL then we
19418 have a complex memory operation, probably a load/store pair.
19419 Be conservative for now and emit a NOP. */
19426 }
19429 /* Implement FINAL_PRESCAN_INSN. */
19431 void
19433 {
19436 }
19439 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
19440 instruction. */
19442 bool
19444 {
19447 }
19449 /* Return true if X is a valid immediate for the SVE ADD and SUB instructions
19450 when applied to mode MODE. Negate X first if NEGATE_P is true. */
19452 bool
19454 {
19467 }
19469 /* Return true if X is a valid immediate for the SVE SQADD and SQSUB
19470 instructions when applied to mode MODE. Negate X first if NEGATE_P
19471 is true. */
19473 bool
19475 {
19479 /* After the optional negation, the immediate must be nonnegative.
19480 E.g. a saturating add of -127 must be done via SQSUB Zn.B, Zn.B, #127
19481 instead of SQADD Zn.B, Zn.B, #129. */
19484 }
19486 /* Return true if X is a valid immediate operand for an SVE logical
19487 instruction such as AND. */
19489 bool
19491 {
19492 rtx elt;
19498 }
19500 /* Return true if X is a valid immediate for the SVE DUP and CPY
19501 instructions. */
19503 bool
19505 {
19514 }
19516 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
19517 SIGNED_P says whether the operand is signed rather than unsigned. */
19519 bool
19521 {
19524 && (signed_p
19527 }
19529 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
19530 instruction. Negate X first if NEGATE_P is true. */
19532 bool
19534 {
19535 rtx elt;
19536 REAL_VALUE_TYPE r;
19552 }
19554 /* Return true if X is a valid immediate operand for an SVE FMUL
19555 instruction. */
19557 bool
19559 {
19560 rtx elt;
19566 }
19568 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
19569 for the Advanced SIMD operation described by WHICH and INSN. If INFO
19570 is nonnull, use it to describe valid immediates. */
19571 static bool
19576 {
19577 /* Try a 4-byte immediate with LSL. */
19580 {
19585 }
19587 /* Try a 2-byte immediate with LSL. */
19592 {
19597 }
19599 /* Try a 4-byte immediate with MSL, except for cases that MVN
19600 can handle. */
19603 {
19606 {
19611 }
19612 }
19615 }
19617 /* Return true if replicating VAL64 is a valid immediate for the
19618 Advanced SIMD operation described by WHICH. If INFO is nonnull,
19619 use it to describe valid immediates. */
19620 static bool
19624 {
19630 {
19641 /* Try using a replicated byte. */
19645 {
19649 }
19650 }
19652 /* Try using a bit-to-bytemask. */
19654 {
19657 {
19661 }
19663 {
19667 }
19668 }
19670 }
19672 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
19673 instruction. If INFO is nonnull, use it to describe valid immediates. */
19675 static bool
19678 {
19682 {
19686 {
19691 }
19692 }
19695 {
19696 /* DUP with no shift. */
19700 }
19702 {
19703 /* DUP with LSL #8. */
19707 }
19709 {
19710 /* DUPM. */
19714 }
19716 }
19718 /* Return true if X is an UNSPEC_PTRUE constant of the form:
19720 (const (unspec [PATTERN ZERO] UNSPEC_PTRUE))
19722 where PATTERN is the svpattern as a CONST_INT and where ZERO
19723 is a zero constant of the required PTRUE mode (which can have
19724 fewer elements than X's mode, if zero bits are significant).
19726 If so, and if INFO is nonnull, describe the immediate in INFO. */
19727 bool
19729 {
19738 {
19739 aarch64_svpattern pattern
19744 }
19746 }
19748 /* Return true if X is a valid SVE predicate. If INFO is nonnull, use
19749 it to describe valid immediates. */
19751 static bool
19753 {
19758 {
19762 }
19764 /* Analyze the value as a VNx16BImode. This should be relatively
19765 efficient, since rtx_vector_builder has enough built-in capacity
19766 to store all VLA predicate constants without needing the heap. */
19767 rtx_vector_builder builder;
19773 {
19777 {
19779 {
19782 }
19784 }
19785 }
19787 }
19789 /* Return true if OP is a valid SIMD immediate for the operation
19790 described by WHICH. If INFO is nonnull, use it to describe valid
19791 immediates. */
19792 bool
19795 {
19812 {
19819 {
19820 /* Get the corresponding container mode. E.g. an INDEX on V2SI
19821 should yield two integer values per 128-bit block, meaning
19822 that we need to treat it in the same way as V2DI and then
19823 ignore the upper 32 bits of each element. */
19826 }
19828 }
19832 else
19835 scalar_float_mode elt_float_mode;
19838 {
19842 {
19846 }
19847 }
19849 /* If all elements in an SVE vector have the same value, we have a free
19850 choice between using the element mode and using the container mode.
19851 Using the element mode means that unused parts of the vector are
19852 duplicates of the used elements, while using the container mode means
19853 that the unused parts are an extension of the used elements. Using the
19854 element mode is better for (say) VNx4HI 0x101, since 0x01010101 is valid
19855 for its container mode VNx4SI while 0x00000101 isn't.
19857 If not all elements in an SVE vector have the same value, we need the
19858 transition from one element to the next to occur at container boundaries.
19859 E.g. a fixed-length VNx4HI containing { 1, 2, 3, 4 } should be treated
19860 in the same way as a VNx4SI containing { 1, 2, 3, 4 }. */
19861 scalar_int_mode elt_int_mode;
19864 else
19871 /* Expand the vector constant out into a byte vector, with the least
19872 significant byte of the register first. */
19876 {
19877 /* The vector is provided in gcc endian-neutral fashion.
19878 For aarch64_be Advanced SIMD, it must be laid out in the vector
19879 register in reverse order. */
19891 {
19894 }
19895 }
19897 /* The immediate must repeat every eight bytes. */
19903 /* Get the repeating 8-byte value as an integer. No endian correction
19904 is needed here because bytes is already in lsb-first order. */
19912 else
19914 }
19916 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
19917 has a step in the range of INDEX. Return the index expression if so,
19918 otherwise return null. */
19919 rtx
19921 {
19928 }
19930 /* Check of immediate shift constants are within range. */
19931 bool
19933 {
19940 else
19942 }
19944 /* Return the bitmask CONST_INT to select the bits required by a zero extract
19945 operation of width WIDTH at bit position POS. */
19947 rtx
19949 {
19953 unsigned HOST_WIDE_INT mask
19956 }
19958 bool
19960 {
19969 {
19970 /* Require predicate constants to be VNx16BI before RA, so that we
19971 force everything to have a canonical form. */
19973 && !reload_completed
19979 }
19990 }
19992 /* Return a const_int vector of VAL. */
19993 rtx
19995 {
19998 }
20000 /* Check OP is a legal scalar immediate for the MOVI instruction. */
20002 bool
20004 {
20005 machine_mode vmode;
20010 }
20012 /* Construct and return a PARALLEL RTX vector with elements numbering the
20013 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
20014 the vector - from the perspective of the architecture. This does not
20015 line up with GCC's perspective on lane numbers, so we end up with
20016 different masks depending on our target endian-ness. The diagram
20017 below may help. We must draw the distinction when building masks
20018 which select one half of the vector. An instruction selecting
20019 architectural low-lanes for a big-endian target, must be described using
20020 a mask selecting GCC high-lanes.
20022 Big-Endian Little-Endian
20024 GCC 0 1 2 3 3 2 1 0
20025 | x | x | x | x | | x | x | x | x |
20026 Architecture 3 2 1 0 3 2 1 0
20028 Low Mask: { 2, 3 } { 0, 1 }
20029 High Mask: { 0, 1 } { 2, 3 }
20031 MODE Is the mode of the vector and NUNITS is the number of units in it. */
20033 rtx
20035 {
20040 rtx t1;
20045 else
20053 }
20055 /* Check OP for validity as a PARALLEL RTX vector with elements
20056 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
20057 from the perspective of the architecture. See the diagram above
20058 aarch64_simd_vect_par_cnst_half for more details. */
20060 bool
20063 {
20077 {
20084 }
20086 }
20088 /* Return a PARALLEL containing NELTS elements, with element I equal
20089 to BASE + I * STEP. */
20091 rtx
20093 {
20098 }
20100 /* Return true if OP is a PARALLEL of CONST_INTs that form a linear
20101 series with step STEP. */
20103 bool
20105 {
20116 }
20118 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
20119 HIGH (exclusive). */
20120 void
20122 const_tree exp)
20123 {
20124 HOST_WIDE_INT lane;
20129 {
20132 else
20134 }
20135 }
20137 /* Peform endian correction on lane number N, which indexes a vector
20138 of mode MODE, and return the result as an SImode rtx. */
20140 rtx
20142 {
20144 }
20146 /* Return TRUE if OP is a valid vector addressing mode. */
20148 bool
20150 {
20153 }
20155 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
20157 bool
20159 {
20161 scalar_mode mode;
20168 }
20170 /* Return true if OP is a valid MEM operand for an SVE LD1R{Q,O} instruction
20171 where the size of the read data is specified by `mode` and the size of the
20172 vector elements are specified by `elem_mode`. */
20173 bool
20175 scalar_mode elem_mode)
20176 {
20189 }
20191 /* Return true if OP is a valid MEM operand for an SVE LD1RQ instruction. */
20192 bool
20194 {
20197 }
20199 /* Return true if OP is a valid MEM operand for an SVE LD1RO instruction for
20200 accessing a vector where the element size is specified by `elem_mode`. */
20201 bool
20203 {
20205 }
20207 /* Return true if OP is a valid MEM operand for an SVE LDFF1 instruction. */
20208 bool
20210 {
20222 }
20224 /* Return true if OP is a valid MEM operand for an SVE LDNF1 instruction. */
20225 bool
20227 {
20234 }
20236 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
20237 The conditions for STR are the same. */
20238 bool
20240 {
20247 }
20249 /* Return true if OP is a valid address for an SVE PRF[BHWD] instruction,
20250 addressing memory of mode MODE. */
20251 bool
20253 {
20262 }
20264 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
20265 We need to be able to access the individual pieces, so the range
20266 is different from LD[234] and ST[234]. */
20267 bool
20269 {
20276 ADDR_QUERY_ANY)
20284 }
20286 /* Emit a register copy from operand to operand, taking care not to
20287 early-clobber source registers in the process.
20289 COUNT is the number of components into which the copy needs to be
20290 decomposed. */
20291 void
20294 {
20304 else
20308 }
20310 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
20311 one of VSTRUCT modes: OI, CI, or XI. */
20312 int
20314 {
20315 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
20317 }
20319 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
20320 alignment of a vector to 128 bits. SVE predicates have an alignment of
20321 16 bits. */
20322 static HOST_WIDE_INT
20324 {
20325 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
20326 be set for non-predicate vectors of booleans. Modes are the most
20327 direct way we have of identifying real SVE predicate types. */
20330 widest_int min_size
20333 }
20335 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
20336 static poly_uint64
20338 {
20340 {
20341 /* If the length of the vector is a fixed power of 2, try to align
20342 to that length, otherwise don't try to align at all. */
20343 HOST_WIDE_INT result;
20348 }
20350 }
20352 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
20353 static bool
20355 {
20359 /* For fixed-length vectors, check that the vectorizer will aim for
20360 full-vector alignment. This isn't true for generic GCC vectors
20361 that are wider than the ABI maximum of 128 bits. */
20362 poly_uint64 preferred_alignment =
20366 preferred_alignment))
20369 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
20371 }
20373 /* Return true if the vector misalignment factor is supported by the
20374 target. */
20375 static bool
20379 {
20381 {
20382 /* Return if movmisalign pattern is not supported for this mode. */
20386 /* Misalignment factor is unknown at compile time. */
20389 }
20391 is_packed);
20392 }
20394 /* If VALS is a vector constant that can be loaded into a register
20395 using DUP, generate instructions to do so and return an RTX to
20396 assign to the register. Otherwise return NULL_RTX. */
20397 static rtx
20399 {
20402 rtx x;
20407 /* We can load this constant by using DUP and a constant in a
20408 single ARM register. This will be cheaper than a vector
20409 load. */
20412 }
20415 /* Generate code to load VALS, which is a PARALLEL containing only
20416 constants (for vec_init) or CONST_VECTOR, efficiently into a
20417 register. Returns an RTX to copy into the register, or NULL_RTX
20418 for a PARALLEL that cannot be converted into a CONST_VECTOR. */
20419 static rtx
20421 {
20423 rtx const_dup;
20431 {
20432 /* A CONST_VECTOR must contain only CONST_INTs and
20433 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
20434 Only store valid constants in a CONST_VECTOR. */
20437 {
20440 n_const++;
20441 }
20444 }
20445 else
20450 /* Load using MOVI/MVNI. */
20453 /* Loaded using DUP. */
20456 /* Load from constant pool. We cannot take advantage of single-cycle
20457 LD1 because we need a PC-relative addressing mode. */
20459 else
20460 /* A PARALLEL containing something not valid inside CONST_VECTOR.
20461 We cannot construct an initializer. */
20463 }
20465 /* Expand a vector initialisation sequence, such that TARGET is
20466 initialised to contain VALS. */
20468 void
20470 {
20473 /* The number of vector elements. */
20475 /* The number of vector elements which are not constant. */
20478 /* The first element of vals. */
20482 /* This is a special vec_init<M><N> where N is not an element mode but a
20483 vector mode with half the elements of M. We expect to find two entries
20484 of mode N in VALS and we must put their concatentation into TARGET. */
20486 {
20495 /* When we want to concatenate a half-width vector with zeroes we can
20496 use the aarch64_combinez[_be] patterns. Just make sure that the
20497 zeroes are in the right half. */
20506 else
20507 {
20508 /* Else create the two half-width registers and combine them. */
20517 }
20519 }
20521 /* Count the number of variable elements to initialise. */
20523 {
20527 else
20531 }
20533 /* No variable elements, hand off to aarch64_simd_make_constant which knows
20534 how best to handle this. */
20536 {
20539 {
20542 }
20543 }
20545 /* Splat a single non-constant element if we can. */
20547 {
20551 }
20556 /* If there are only variable elements, try to optimize
20557 the insertion using dup for the most common element
20558 followed by insertions. */
20560 /* The algorithm will fill matches[*][0] with the earliest matching element,
20561 and matches[X][1] with the count of duplicate elements (if X is the
20562 earliest element which has duplicates). */
20565 {
20568 {
20570 {
20572 {
20576 }
20577 }
20578 }
20583 {
20586 }
20588 /* Create a duplicate of the most common element, unless all elements
20589 are equally useless to us, in which case just immediately set the
20590 vector register using the first element. */
20593 {
20594 /* For vectors of two 64-bit elements, we can do even better. */
20599 {
20602 /* Combine can pick up this case, but handling it directly
20603 here leaves clearer RTL.
20605 This is load_pair_lanes<mode>, and also gives us a clean-up
20606 for store_pair_lanes<mode>. */
20609 && !STRICT_ALIGNMENT
20614 {
20615 rtx t;
20618 else
20622 }
20623 }
20624 /* The subreg-move sequence below will move into lane zero of the
20625 vector register. For big-endian we want that position to hold
20626 the last element of VALS. */
20630 }
20631 else
20632 {
20635 }
20637 /* Insert the rest. */
20639 {
20645 }
20647 }
20649 /* Initialise a vector which is part-variable. We want to first try
20650 to build those lanes which are constant in the most efficient way we
20651 can. */
20653 {
20656 /* Load constant part of vector. We really don't care what goes into the
20657 parts we will overwrite, but we're more likely to be able to load the
20658 constant efficiently if it has fewer, larger, repeating parts
20659 (see aarch64_simd_valid_immediate). */
20661 {
20667 {
20668 /* Look in the copied vector, as more elements are const. */
20671 {
20674 }
20675 }
20677 }
20679 }
20681 /* Insert the variable lanes directly. */
20683 {
20689 }
20690 }
20692 /* Emit RTL corresponding to:
20693 insr TARGET, ELEM. */
20695 static void
20697 {
20705 }
20707 /* Subroutine of aarch64_sve_expand_vector_init for handling
20708 trailing constants.
20709 This function works as follows:
20710 (a) Create a new vector consisting of trailing constants.
20711 (b) Initialize TARGET with the constant vector using emit_move_insn.
20712 (c) Insert remaining elements in TARGET using insr.
20713 NELTS is the total number of elements in original vector while
20714 while NELTS_REQD is the number of elements that are actually
20715 significant.
20717 ??? The heuristic used is to do above only if number of constants
20718 is at least half the total number of elements. May need fine tuning. */
20720 static bool
20721 aarch64_sve_expand_vector_init_handle_trailing_constants
20723 {
20730 i--)
20731 n_trailing_constants++;
20734 {
20735 /* Try to use the natural pattern of BUILDER to extend the trailing
20736 constant elements to a full vector. Replace any variables in the
20737 extra elements with zeros.
20739 ??? It would be better if the builders supported "don't care"
20740 elements, with the builder filling in whichever elements
20741 give the most compact encoding. */
20744 {
20749 }
20757 }
20760 }
20762 /* Subroutine of aarch64_sve_expand_vector_init.
20763 Works as follows:
20764 (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
20765 (b) Skip trailing elements from BUILDER, which are the same as
20766 element NELTS_REQD - 1.
20767 (c) Insert earlier elements in reverse order in TARGET using insr. */
20769 static void
20773 {
20788 }
20790 /* Subroutine of aarch64_sve_expand_vector_init to handle case
20791 when all trailing elements of builder are same.
20792 This works as follows:
20793 (a) Use expand_insn interface to broadcast last vector element in TARGET.
20794 (b) Insert remaining elements in TARGET using insr.
20796 ??? The heuristic used is to do above if number of same trailing elements
20797 is at least 3/4 of total number of elements, loosely based on
20798 heuristic from mostly_zeros_p. May need fine-tuning. */
20800 static bool
20801 aarch64_sve_expand_vector_init_handle_trailing_same_elem
20803 {
20806 {
20810 }
20813 }
20815 /* Initialize register TARGET from BUILDER. NELTS is the constant number
20816 of elements in BUILDER.
20818 The function tries to initialize TARGET from BUILDER if it fits one
20819 of the special cases outlined below.
20821 Failing that, the function divides BUILDER into two sub-vectors:
20822 v_even = even elements of BUILDER;
20823 v_odd = odd elements of BUILDER;
20825 and recursively calls itself with v_even and v_odd.
20827 if (recursive call succeeded for v_even or v_odd)
20828 TARGET = zip (v_even, v_odd)
20830 The function returns true if it managed to build TARGET from BUILDER
20831 with one of the special cases, false otherwise.
20833 Example: {a, 1, b, 2, c, 3, d, 4}
20835 The vector gets divided into:
20836 v_even = {a, b, c, d}
20837 v_odd = {1, 2, 3, 4}
20839 aarch64_sve_expand_vector_init(v_odd) hits case 1 and
20840 initialize tmp2 from constant vector v_odd using emit_move_insn.
20842 aarch64_sve_expand_vector_init(v_even) fails since v_even contains
20843 4 elements, so we construct tmp1 from v_even using insr:
20844 tmp1 = dup(d)
20845 insr tmp1, c
20846 insr tmp1, b
20847 insr tmp1, a
20849 And finally:
20850 TARGET = zip (tmp1, tmp2)
20851 which sets TARGET to {a, 1, b, 2, c, 3, d, 4}. */
20853 static bool
20856 {
20859 /* Case 1: Vector contains trailing constants. */
20865 /* Case 2: Vector contains leading constants. */
20874 {
20877 }
20879 /* Case 3: Vector contains trailing same element. */
20885 /* Case 4: Vector contains leading same element. */
20889 {
20892 }
20894 /* Avoid recursing below 4-elements.
20895 ??? The threshold 4 may need fine-tuning. */
20904 {
20907 }
20923 /* Initialize v_even and v_odd using INSR if it didn't match any of the
20924 special cases and zip v_even, v_odd. */
20935 }
20937 /* Initialize register TARGET from the elements in PARALLEL rtx VALS. */
20939 void
20941 {
20950 /* If neither sub-vectors of v could be initialized specially,
20951 then use INSR to insert all elements from v into TARGET.
20952 ??? This might not be optimal for vectors with large
20953 initializers like 16-element or above.
20954 For nelts < 4, it probably isn't useful to handle specially. */
20959 }
20961 /* Check whether VALUE is a vector constant in which every element
20962 is either a power of 2 or a negated power of 2. If so, return
20963 a constant vector of log2s, and flip CODE between PLUS and MINUS
20964 if VALUE contains negated powers of 2. Return NULL_RTX otherwise. */
20966 static rtx
20968 {
20972 rtx_vector_builder builder;
20977 /* 1 if the result of the multiplication must be negated,
20978 0 if it mustn't, or -1 if we don't yet care. */
20982 {
20989 {
20990 /* It matters whether we negate or not. Make that choice,
20991 and make sure that it's consistent with previous elements. */
20997 }
20998 /* POW2 is now the value that we want to be a power of 2. */
21003 }
21005 /* PLUS and MINUS are equivalent; canonicalize on PLUS. */
21010 }
21012 /* Prepare for an integer SVE multiply-add or multiply-subtract pattern;
21013 CODE is PLUS for the former and MINUS for the latter. OPERANDS is the
21014 operands array, in the same order as for fma_optab. Return true if
21015 the function emitted all the necessary instructions, false if the caller
21016 should generate the pattern normally with the new OPERANDS array. */
21018 bool
21020 {
21023 {
21028 OPTAB_DIRECT);
21030 }
21033 }
21035 /* Likewise, but for a conditional pattern. */
21037 bool
21039 {
21042 {
21048 }
21051 }
21053 static unsigned HOST_WIDE_INT
21055 {
21059 }
21061 /* Select a format to encode pointers in exception handling data. */
21062 int
21064 {
21067 {
21073 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
21074 for everything. */
21078 /* No assumptions here. 8-byte relocs required. */
21081 }
21083 }
21085 /* Output .variant_pcs for aarch64_vector_pcs function symbols. */
21087 static void
21089 {
21091 {
21094 {
21098 }
21099 }
21100 }
21102 /* The last .arch and .tune assembly strings that we printed. */
21106 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
21107 by the function fndecl. */
21109 void
21111 tree fndecl)
21112 {
21118 else
21129 /* Only update the assembler .arch string if it is distinct from the last
21130 such string we printed. */
21133 {
21136 }
21138 /* Print the cpu name we're tuning for in the comments, might be
21139 useful to readers of the generated asm. Do it only when it changes
21140 from function to function and verbose assembly is requested. */
21145 {
21149 }
21153 /* Don't forget the type directive for ELF. */
21158 }
21160 /* Implement PRINT_PATCHABLE_FUNCTION_ENTRY. Check if the patch area is after
21161 the function label and emit a BTI if necessary. */
21163 void
21167 {
21171 {
21172 /* Remove the BTI that follows the patch area and insert a new BTI
21173 before the patch area right after the function label. */
21181 }
21184 }
21186 /* Implement ASM_OUTPUT_DEF_FROM_DECLS. Output .variant_pcs for aliases. */
21188 void
21190 {
21195 }
21197 /* Implement ASM_OUTPUT_EXTERNAL. Output .variant_pcs for undefined
21198 function symbol references. */
21200 void
21202 {
21205 }
21207 /* Triggered after a .cfi_startproc directive is emitted into the assembly file.
21208 Used to output the .cfi_b_key_frame directive when signing the current
21209 function with the B key. */
21211 void
21213 {
21217 }
21219 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
21221 static void
21223 {
21240 }
21242 /* Emit load exclusive. */
21244 static void
21247 {
21252 else
21254 }
21256 /* Emit store exclusive. */
21258 static void
21261 {
21266 else
21268 }
21270 /* Mark the previous jump instruction as unlikely. */
21272 static void
21274 {
21277 }
21279 /* We store the names of the various atomic helpers in a 5x4 array.
21280 Return the libcall function given MODE, MODEL and NAMES. */
21282 rtx
21285 {
21290 {
21308 }
21311 {
21328 }
21331 VISIBILITY_HIDDEN);
21332 }
21334 #define DEF0(B, N) \
21340 #define DEF4(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), \
21341 { NULL, NULL, NULL, NULL }
21342 #define DEF5(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), DEF0(B, 16)
21351 #undef DEF0
21352 #undef DEF4
21353 #undef DEF5
21355 /* Expand a compare and swap pattern. */
21357 void
21359 {
21373 /* Normally the succ memory model must be stronger than fail, but in the
21374 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
21375 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
21382 {
21385 }
21388 {
21389 /* The CAS insn requires oldval and rval overlap, but we need to
21390 have a copy of oldval saved across the operation to tell if
21391 the operation is successful. */
21394 else
21400 }
21402 {
21403 /* Oldval must satisfy compare afterward. */
21411 }
21412 else
21413 {
21414 /* The oldval predicate varies by mode. Test it and force to reg. */
21422 }
21430 }
21432 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
21433 sequence implementing an atomic operation. */
21435 static void
21437 {
21444 {
21446 }
21447 }
21449 /* Split a compare and swap pattern. */
21451 void
21453 {
21454 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
21458 machine_mode mode;
21473 /* When OLDVAL is zero and we want the strong version we can emit a tighter
21474 loop:
21475 .label1:
21476 LD[A]XR rval, [mem]
21477 CBNZ rval, .label2
21478 ST[L]XR scratch, newval, [mem]
21479 CBNZ scratch, .label1
21480 .label2:
21481 CMP rval, 0. */
21487 {
21490 }
21493 /* The initial load can be relaxed for a __sync operation since a final
21494 barrier will be emitted to stop code hoisting. */
21497 else
21502 else
21503 {
21506 }
21514 {
21516 {
21517 /* Emit an explicit compare instruction, so that we can correctly
21518 track the condition codes. */
21521 }
21522 else
21528 }
21529 else
21534 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
21535 to set the condition flags. If this is not used it will be removed by
21536 later passes. */
21540 /* Emit any final barrier needed for a __sync operation. */
21543 }
21545 /* Split an atomic operation. */
21547 void
21550 {
21551 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
21559 rtx x;
21561 /* Split the atomic operation into a sequence. */
21569 else
21573 /* The initial load can be relaxed for a __sync operation since a final
21574 barrier will be emitted to stop code hoisting. */
21578 else
21582 {
21596 {
21599 }
21600 /* Fall through. */
21606 }
21612 {
21613 /* Emit an explicit compare instruction, so that we can correctly
21614 track the condition codes. */
21617 }
21618 else
21625 /* Emit any final barrier needed for a __sync operation. */
21628 }
21630 static void
21632 {
21633 /* Half-precision float operations. The compiler handles all operations
21634 with NULL libfuncs by converting to SFmode. */
21636 /* Conversions. */
21640 /* Arithmetic. */
21647 /* Comparisons. */
21655 }
21657 /* Target hook for c_mode_for_suffix. */
21658 static machine_mode
21660 {
21665 }
21667 /* We can only represent floating point constants which will fit in
21668 "quarter-precision" values. These values are characterised by
21669 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
21670 by:
21672 (-1)^s * (n/16) * 2^r
21674 Where:
21675 's' is the sign bit.
21676 'n' is an integer in the range 16 <= n <= 31.
21677 'r' is an integer in the range -3 <= r <= 4. */
21679 /* Return true iff X can be represented by a quarter-precision
21680 floating point immediate operand X. Note, we cannot represent 0.0. */
21681 bool
21683 {
21684 /* This represents our current view of how many bits
21685 make up the mantissa. */
21702 /* We cannot represent infinities, NaNs or +/-zero. We won't
21703 know if we have +zero until we analyse the mantissa, but we
21704 can reject the other invalid values. */
21709 /* Extract exponent. */
21713 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
21714 highest (sign) bit, with a fixed binary point at bit point_pos.
21715 m1 holds the low part of the mantissa, m2 the high part.
21716 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
21717 bits for the mantissa, this can fail (low bits will be lost). */
21721 /* If the low part of the mantissa has bits set we cannot represent
21722 the value. */
21725 /* We have rejected the lower HOST_WIDE_INT, so update our
21726 understanding of how many bits lie in the mantissa and
21727 look only at the high HOST_WIDE_INT. */
21731 /* We can only represent values with a mantissa of the form 1.xxxx. */
21736 /* Having filtered unrepresentable values, we may now remove all
21737 but the highest 5 bits. */
21740 /* We cannot represent the value 0.0, so reject it. This is handled
21741 elsewhere. */
21745 /* Then, as bit 4 is always set, we can mask it off, leaving
21746 the mantissa in the range [0, 15]. */
21750 /* GCC internally does not use IEEE754-like encoding (where normalized
21751 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
21752 Our mantissa values are shifted 4 places to the left relative to
21753 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
21754 by 5 places to correct for GCC's representation. */
21758 }
21760 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
21761 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
21762 output MOVI/MVNI, ORR or BIC immediate. */
21766 {
21776 /* This will return true to show const_vector is legal for use as either
21777 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
21778 It will also update INFO to show how the immediate should be generated.
21779 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
21787 {
21790 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
21791 move immediate path. */
21794 else
21795 {
21804 else
21808 }
21809 }
21814 {
21826 else
21830 }
21831 else
21832 {
21833 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
21840 else
21844 }
21846 }
21850 {
21852 /* If a floating point number was passed and we desire to use it in an
21853 integer mode do the conversion to integer. */
21855 {
21860 }
21862 machine_mode vmode;
21863 /* use a 64 bit mode for everything except for DI/DF mode, where we use
21864 a 128 bit vector mode. */
21870 }
21872 /* Return the output string to use for moving immediate CONST_VECTOR
21873 into an SVE register. */
21877 {
21889 {
21892 {
21895 }
21896 else
21897 {
21904 else
21907 }
21909 }
21912 {
21918 }
21921 {
21924 else
21925 {
21935 }
21936 }
21941 }
21943 /* Return the asm template for a PTRUES. CONST_UNSPEC is the
21944 aarch64_sve_ptrue_svpattern_immediate that describes the predicate
21945 pattern. */
21949 {
21960 }
21962 /* Split operands into moves from op[1] + op[2] into op[0]. */
21964 void
21966 {
21977 {
21978 /* No-op move. Can't split to nothing; emit something. */
21981 }
21983 /* Preserve register attributes for variable tracking. */
21988 /* Special case of reversed high/low parts. */
21991 {
21995 }
21997 {
21998 /* Try to avoid unnecessary moves if part of the result
21999 is in the right place already. */
22004 }
22005 else
22006 {
22011 }
22012 }
22014 /* vec_perm support. */
22016 struct expand_vec_perm_d
22017 {
22019 vec_perm_indices perm;
22020 machine_mode vmode;
22024 };
22028 /* Generate a variable permutation. */
22030 static void
22032 {
22043 {
22045 {
22046 /* Expand the argument to a V16QI mode by duplicating it. */
22050 }
22051 else
22052 {
22054 }
22055 }
22056 else
22057 {
22058 rtx pair;
22061 {
22065 }
22066 else
22067 {
22071 }
22072 }
22073 }
22075 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
22076 NELT is the number of elements in the vector. */
22078 void
22081 {
22084 rtx mask;
22086 /* The TBL instruction does not use a modulo index, so we must take care
22087 of that ourselves. */
22092 /* For big-endian, we also need to reverse the index within the vector
22093 (but not which vector). */
22095 {
22096 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
22101 }
22103 }
22105 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
22107 static void
22109 {
22113 }
22115 /* Expand an SVE vec_perm with the given operands. */
22117 void
22119 {
22122 /* Enforced by the pattern condition. */
22125 /* Note: vec_perm indices are supposed to wrap when they go beyond the
22126 size of the two value vectors, i.e. the upper bits of the indices
22127 are effectively ignored. SVE TBL instead produces 0 for any
22128 out-of-range indices, so we need to modulo all the vec_perm indices
22129 to ensure they are all in range. */
22132 /* Check if the sel only references the first values vector. */
22135 {
22138 }
22140 /* Check if the two values vectors are the same. */
22142 {
22148 }
22150 /* Run TBL on for each value vector and combine the results. */
22157 {
22162 }
22169 else
22171 }
22173 /* Recognize patterns suitable for the TRN instructions. */
22174 static bool
22176 {
22177 HOST_WIDE_INT odd;
22185 /* Note that these are little-endian tests.
22186 We correct for big-endian later. */
22193 /* Success! */
22199 /* We don't need a big-endian lane correction for SVE; see the comment
22200 at the head of aarch64-sve.md for details. */
22202 {
22205 }
22211 }
22213 /* Try to re-encode the PERM constant so it combines odd and even elements.
22214 This rewrites constants such as {0, 1, 4, 5}/V4SF to {0, 2}/V2DI.
22215 We retry with this new constant with the full suite of patterns. */
22216 static bool
22218 {
22219 expand_vec_perm_d newd;
22225 /* Get the new mode. Always twice the size of the inner
22226 and half the elements. */
22235 /* to_constant is safe since this routine is specific to Advanced SIMD
22236 vectors. */
22239 vec_perm_builder newpermconst;
22242 /* Convert the perm constant if we can. Require even, odd as the pairs. */
22244 {
22247 poly_int64 newelt;
22251 }
22264 }
22266 /* Recognize patterns suitable for the UZP instructions. */
22267 static bool
22269 {
22270 HOST_WIDE_INT odd;
22277 /* Note that these are little-endian tests.
22278 We correct for big-endian later. */
22284 /* Success! */
22290 /* We don't need a big-endian lane correction for SVE; see the comment
22291 at the head of aarch64-sve.md for details. */
22293 {
22296 }
22302 }
22304 /* Recognize patterns suitable for the ZIP instructions. */
22305 static bool
22307 {
22316 /* Note that these are little-endian tests.
22317 We correct for big-endian later. */
22325 /* Success! */
22331 /* We don't need a big-endian lane correction for SVE; see the comment
22332 at the head of aarch64-sve.md for details. */
22334 {
22337 }
22343 }
22345 /* Recognize patterns for the EXT insn. */
22347 static bool
22349 {
22350 HOST_WIDE_INT location;
22351 rtx offset;
22353 /* The first element always refers to the first vector.
22354 Check if the extracted indices are increasing by one. */
22360 /* Success! */
22364 /* The case where (location == 0) is a no-op for both big- and little-endian,
22365 and is removed by the mid-end at optimization levels -O1 and higher.
22367 We don't need a big-endian lane correction for SVE; see the comment
22368 at the head of aarch64-sve.md for details. */
22370 {
22371 /* After setup, we want the high elements of the first vector (stored
22372 at the LSB end of the register), and the low elements of the second
22373 vector (stored at the MSB end of the register). So swap. */
22375 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
22376 to_constant () is safe since this is restricted to Advanced SIMD
22377 vectors. */
22379 }
22385 UNSPEC_EXT));
22387 }
22389 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
22390 within each 64-bit, 32-bit or 16-bit granule. */
22392 static bool
22394 {
22395 HOST_WIDE_INT diff;
22397 machine_mode pred_mode;
22407 else
22410 {
22413 }
22415 {
22418 }
22420 {
22423 }
22424 else
22432 /* Success! */
22437 {
22442 }
22446 }
22448 /* Recognize patterns for the REV insn, which reverses elements within
22449 a full vector. */
22451 static bool
22453 {
22462 /* Success! */
22469 }
22471 static bool
22473 {
22475 rtx in0;
22476 HOST_WIDE_INT elt;
22478 rtx lane;
22489 /* Success! */
22493 /* The generic preparation in aarch64_expand_vec_perm_const_1
22494 swaps the operand order and the permute indices if it finds
22495 d->perm[0] to be in the second operand. Thus, we can always
22496 use d->op0 and need not do any extra arithmetic to get the
22497 correct lane number. */
22505 }
22507 static bool
22509 {
22513 /* Make sure that the indices are constant. */
22522 /* Generic code will try constant permutation twice. Once with the
22523 original mode and again with the elements lowered to QImode.
22524 So wait and don't do the selector expansion ourselves. */
22528 /* to_constant is safe since this routine is specific to Advanced SIMD
22529 vectors. */
22532 /* If big-endian and two vectors we end up with a weird mixed-endian
22533 mode on NEON. Reverse the index within each word but not the word
22534 itself. to_constant is safe because we checked is_constant above. */
22544 }
22546 /* Try to implement D using an SVE TBL instruction. */
22548 static bool
22550 {
22553 /* Permuting two variable-length vectors could overflow the
22554 index range. */
22565 else
22568 }
22570 /* Try to implement D using SVE SEL instruction. */
22572 static bool
22574 {
22600 /* Build a predicate that is true when op0 elements should be used. */
22603 {
22607 }
22611 /* TARGET = PRED ? OP0 : OP1. */
22614 }
22616 /* Recognize patterns suitable for the INS instructions. */
22617 static bool
22619 {
22626 /* to_constant is safe since this routine is specific to Advanced SIMD
22627 vectors. */
22634 {
22635 HOST_WIDE_INT elt;
22641 {
22644 }
22646 }
22649 {
22652 {
22658 }
22662 }
22672 {
22675 }
22689 }
22691 static bool
22693 {
22694 /* The pattern matching functions above are written to look for a small
22695 number to begin the sequence (0, 1, N/2). If we begin with an index
22696 from the second operand, we can swap the operands. */
22699 {
22702 }
22709 {
22734 }
22736 }
22738 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
22740 static bool
22743 {
22746 /* Check whether the mask can be applied to a single vector. */
22751 {
22754 }
22756 {
22759 }
22760 else
22771 else
22783 }
22785 /* Generate a byte permute mask for a register of mode MODE,
22786 which has NUNITS units. */
22788 rtx
22790 {
22791 /* We have to reverse each vector because we dont have
22792 a permuted load that can reverse-load according to ABI rules. */
22793 rtx mask;
22806 }
22808 /* Expand an SVE integer comparison using the SVE equivalent of:
22810 (set TARGET (CODE OP0 OP1)). */
22812 void
22814 {
22821 }
22823 /* Return the UNSPEC_COND_* code for comparison CODE. */
22825 static unsigned int
22827 {
22829 {
22846 }
22847 }
22849 /* Emit:
22851 (set TARGET (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
22853 where <X> is the operation associated with comparison CODE.
22854 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
22856 static void
22859 {
22865 }
22867 /* Emit the SVE equivalent of:
22869 (set TMP1 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X1>))
22870 (set TMP2 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X2>))
22871 (set TARGET (ior:PRED_MODE TMP1 TMP2))
22873 where <Xi> is the operation associated with comparison CODEi.
22874 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
22876 static void
22879 {
22886 }
22888 /* Emit the SVE equivalent of:
22890 (set TMP (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
22891 (set TARGET (not TMP))
22893 where <X> is the operation associated with comparison CODE.
22894 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
22896 static void
22899 {
22904 }
22906 /* Expand an SVE floating-point comparison using the SVE equivalent of:
22908 (set TARGET (CODE OP0 OP1))
22910 If CAN_INVERT_P is true, the caller can also handle inverted results;
22911 return true if the result is in fact inverted. */
22913 bool
22916 {
22922 {
22924 /* UNORDERED has no immediate form. */
22926 /* fall through */
22933 {
22934 /* There is native support for the comparison. */
22937 }
22940 /* This is a trapping operation (LT or GT). */
22946 {
22947 /* This would trap for signaling NaNs. */
22952 }
22953 /* fall through */
22959 {
22960 /* Work out which elements are ordered. */
22966 /* Test the opposite condition for the ordered elements,
22967 then invert the result. */
22970 else
22973 {
22977 }
22981 }
22985 /* ORDERED has no immediate form. */
22991 }
22993 /* There is native support for the inverse comparison. */
22996 {
22999 }
23002 }
23004 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
23005 of the data being selected and CMP_MODE is the mode of the values being
23006 compared. */
23008 void
23011 {
23015 {
23019 }
23020 else
23025 /* The "false" value can only be zero if the "true" value is a constant. */
23032 }
23034 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
23035 true. However due to issues with register allocation it is preferable
23036 to avoid tieing integer scalar and FP scalar modes. Executing integer
23037 operations in general registers is better than treating them as scalar
23038 vector operations. This reduces latency and avoids redundant int<->FP
23039 moves. So tie modes if they are either the same class, or vector modes
23040 with other vector modes, vector structs or any scalar mode. */
23042 static bool
23044 {
23048 /* We specifically want to allow elements of "structure" modes to
23049 be tieable to the structure. This more general condition allows
23050 other rarer situations too. The reason we don't extend this to
23051 predicate modes is that there are no predicate structure modes
23052 nor any specific instructions for extracting part of a predicate
23053 register. */
23058 /* Also allow any scalar modes with vectors. */
23064 }
23066 /* Return a new RTX holding the result of moving POINTER forward by
23067 AMOUNT bytes. */
23069 static rtx
23071 {
23076 }
23078 /* Return a new RTX holding the result of moving POINTER forward by the
23079 size of the mode it points to. */
23081 static rtx
23083 {
23085 }
23087 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
23088 MODE bytes. */
23090 static void
23092 machine_mode mode)
23093 {
23094 /* Handle 256-bit memcpy separately. We do this by making 2 adjacent memory
23095 address copies using V4SImode so that we can use Q registers. */
23097 {
23101 /* "Cast" the pointers to the correct mode. */
23104 /* Emit the memcpy. */
23109 /* Move the pointers forward. */
23113 }
23117 /* "Cast" the pointers to the correct mode. */
23120 /* Emit the memcpy. */
23123 /* Move the pointers forward. */
23126 }
23128 /* Expand cpymem, as if from a __builtin_memcpy. Return true if
23129 we succeed, otherwise return false. */
23131 bool
23133 {
23137 rtx base;
23140 /* Only expand fixed-size copies. */
23146 /* Inline up to 256 bytes when optimizing for speed. */
23154 /* Default to 256-bit LDP/STP on large copies, however small copies, no SIMD
23155 support or slow 256-bit LDP/STP fall back to 128-bit chunks. */
23157 || !TARGET_SIMD
23160 {
23163 }
23174 /* Convert size to bits to make the rest of the code simpler. */
23178 {
23179 /* Find the largest mode in which to do the copy in without over reading
23180 or writing. */
23181 opt_scalar_int_mode mode_iter;
23190 /* Prefer Q-register accesses for the last bytes. */
23198 /* Emit trailing copies using overlapping unaligned accesses - this is
23199 smaller and faster. */
23201 {
23208 }
23209 }
23212 }
23214 /* Like aarch64_copy_one_block_and_progress_pointers, except for memset where
23215 SRC is a register we have created with the duplicated value to be set. */
23216 static void
23218 machine_mode mode)
23219 {
23220 /* If we are copying 128bits or 256bits, we can do that straight from
23221 the SIMD register we prepared. */
23223 {
23225 /* "Cast" the *dst to the correct mode. */
23227 /* Emit the memset. */
23231 /* Move the pointers forward. */
23234 }
23236 {
23237 /* "Cast" the *dst to the correct mode. */
23239 /* Emit the memset. */
23241 /* Move the pointers forward. */
23244 }
23245 /* For copying less, we have to extract the right amount from src. */
23248 /* "Cast" the *dst to the correct mode. */
23250 /* Emit the memset. */
23252 /* Move the pointer forward. */
23254 }
23256 /* Expand setmem, as if from a __builtin_memset. Return true if
23257 we succeed, otherwise return false. */
23259 bool
23261 {
23266 rtx base;
23269 /* We can't do anything smart if the amount to copy is not constant. */
23275 /* Default the maximum to 256-bytes. */
23278 /* In case we are optimizing for size or if the core does not
23279 want to use STP Q regs, lower the max_set_size. */
23280 max_set_size = (!speed_p
23287 /* Upper bound check. */
23294 /* Prepare the val using a DUP/MOVI v0.16B, val. */
23298 /* Convert len to bits to make the rest of the code simpler. */
23301 /* Maximum amount to copy in one go. We allow 256-bit chunks based on the
23302 AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS tuning parameter. setmem expand
23303 pattern is only turned on for TARGET_SIMD. */
23310 {
23311 /* Find the largest mode in which to do the copy without
23312 over writing. */
23313 opt_scalar_int_mode mode_iter;
23325 /* Do certain trailing copies as overlapping if it's going to be
23326 cheaper. i.e. less instructions to do so. For instance doing a 15
23327 byte copy it's more efficient to do two overlapping 8 byte copies than
23328 8 + 4 + 2 + 1. */
23330 {
23336 }
23337 }
23340 }
23343 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
23344 SImode stores. Handle the case when the constant has identical
23345 bottom and top halves. This is beneficial when the two stores can be
23346 merged into an STP and we avoid synthesising potentially expensive
23347 immediates twice. Return true if such a split is possible. */
23349 bool
23351 {
23360 unsigned int orig_cost
23362 unsigned int lo_cost
23365 /* We want to transform:
23366 MOV x1, 49370
23367 MOVK x1, 0x140, lsl 16
23368 MOVK x1, 0xc0da, lsl 32
23369 MOVK x1, 0x140, lsl 48
23370 STR x1, [x0]
23371 into:
23372 MOV w1, 49370
23373 MOVK w1, 0x140, lsl 16
23374 STP w1, w1, [x0]
23375 So we want to perform this only when we save two instructions
23376 or more. When optimizing for size, however, accept any code size
23377 savings we can. */
23392 /* Don't emit an explicit store pair as this may not be always profitable.
23393 Let the sched-fusion logic decide whether to merge them. */
23398 }
23400 /* Generate RTL for a conditional branch with rtx comparison CODE in
23401 mode CC_MODE. The destination of the unlikely conditional branch
23402 is LABEL_REF. */
23404 void
23406 rtx label_ref)
23407 {
23408 rtx x;
23411 const0_rtx);
23415 pc_rtx);
23417 }
23419 /* Generate DImode scratch registers for 128-bit (TImode) addition.
23421 OP1 represents the TImode destination operand 1
23422 OP2 represents the TImode destination operand 2
23423 LOW_DEST represents the low half (DImode) of TImode operand 0
23424 LOW_IN1 represents the low half (DImode) of TImode operand 1
23425 LOW_IN2 represents the low half (DImode) of TImode operand 2
23426 HIGH_DEST represents the high half (DImode) of TImode operand 0
23427 HIGH_IN1 represents the high half (DImode) of TImode operand 1
23428 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
23430 void
23435 {
23444 }
23446 /* Generate DImode scratch registers for 128-bit (TImode) subtraction.
23448 This function differs from 'arch64_addti_scratch_regs' in that
23449 OP1 can be an immediate constant (zero). We must call
23450 subreg_highpart_offset with DImode and TImode arguments, otherwise
23451 VOIDmode will be used for the const_int which generates an internal
23452 error from subreg_size_highpart_offset which does not expect a size of zero.
23454 OP1 represents the TImode destination operand 1
23455 OP2 represents the TImode destination operand 2
23456 LOW_DEST represents the low half (DImode) of TImode operand 0
23457 LOW_IN1 represents the low half (DImode) of TImode operand 1
23458 LOW_IN2 represents the low half (DImode) of TImode operand 2
23459 HIGH_DEST represents the high half (DImode) of TImode operand 0
23460 HIGH_IN1 represents the high half (DImode) of TImode operand 1
23461 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
23464 void
23469 {
23482 }
23484 /* Generate RTL for 128-bit (TImode) subtraction with overflow.
23486 OP0 represents the TImode destination operand 0
23487 LOW_DEST represents the low half (DImode) of TImode operand 0
23488 LOW_IN1 represents the low half (DImode) of TImode operand 1
23489 LOW_IN2 represents the low half (DImode) of TImode operand 2
23490 HIGH_DEST represents the high half (DImode) of TImode operand 0
23491 HIGH_IN1 represents the high half (DImode) of TImode operand 1
23492 HIGH_IN2 represents the high half (DImode) of TImode operand 2
23493 UNSIGNED_P is true if the operation is being performed on unsigned
23494 values. */
23495 void
23499 {
23501 {
23506 else
23508 }
23509 else
23510 {
23514 else
23515 {
23518 }
23523 else
23525 }
23530 }
23532 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
23534 static unsigned HOST_WIDE_INT
23536 {
23539 else
23541 }
23543 static rtx
23546 {
23550 insn_code icode;
23561 {
23589 }
23594 {
23597 }
23606 {
23609 }
23615 }
23617 static rtx
23620 {
23624 insn_code icode;
23636 {
23660 }
23667 {
23670 }
23678 {
23679 /* Treat the ccmp patterns as canonical and use them where possible,
23680 but fall back to ccmp_rev patterns if there's no other option. */
23689 else
23690 {
23693 }
23695 }
23706 {
23709 }
23715 }
23717 #undef TARGET_GEN_CCMP_FIRST
23718 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
23720 #undef TARGET_GEN_CCMP_NEXT
23721 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
23723 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
23724 instruction fusion of some sort. */
23726 static bool
23728 {
23730 }
23733 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
23734 should be kept together during scheduling. */
23736 static bool
23738 {
23739 rtx set_dest;
23742 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
23749 {
23750 /* We are trying to match:
23751 prev (mov) == (set (reg r0) (const_int imm16))
23752 curr (movk) == (set (zero_extract (reg r0)
23753 (const_int 16)
23754 (const_int 16))
23755 (const_int imm16_1)) */
23767 {
23769 }
23770 }
23773 {
23775 /* We're trying to match:
23776 prev (adrp) == (set (reg r1)
23777 (high (symbol_ref ("SYM"))))
23778 curr (add) == (set (reg r0)
23779 (lo_sum (reg r1)
23780 (symbol_ref ("SYM"))))
23781 Note that r0 need not necessarily be the same as r1, especially
23782 during pre-regalloc scheduling. */
23786 {
23794 }
23795 }
23798 {
23800 /* We're trying to match:
23801 prev (movk) == (set (zero_extract (reg r0)
23802 (const_int 16)
23803 (const_int 32))
23804 (const_int imm16_1))
23805 curr (movk) == (set (zero_extract (reg r0)
23806 (const_int 16)
23807 (const_int 48))
23808 (const_int imm16_2)) */
23824 }
23826 {
23827 /* We're trying to match:
23828 prev (adrp) == (set (reg r0)
23829 (high (symbol_ref ("SYM"))))
23830 curr (ldr) == (set (reg r1)
23831 (mem (lo_sum (reg r0)
23832 (symbol_ref ("SYM")))))
23833 or
23834 curr (ldr) == (set (reg r1)
23835 (zero_extend (mem
23836 (lo_sum (reg r0)
23837 (symbol_ref ("SYM")))))) */
23840 {
23853 }
23854 }
23856 /* Fuse compare (CMP/CMN/TST/BICS) and conditional branch. */
23864 /* Fuse flag-setting ALU instructions and conditional branch. */
23867 {
23869 rtx cc_reg_1;
23874 && prev
23876 {
23879 /* FIXME: this misses some which is considered simple arthematic
23880 instructions for ThunderX. Simple shifts are missed here. */
23886 }
23887 }
23889 /* Fuse ALU instructions and CBZ/CBNZ. */
23891 && curr_set
23894 {
23895 /* We're trying to match:
23896 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
23897 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
23898 (const_int 0))
23899 (label_ref ("SYM"))
23900 (pc)) */
23907 {
23908 /* Fuse ALU operations followed by conditional branch instruction. */
23910 {
23931 }
23932 }
23933 }
23936 }
23938 /* Return true iff the instruction fusion described by OP is enabled. */
23940 bool
23942 {
23944 }
23946 /* If MEM is in the form of [base+offset], extract the two parts
23947 of address and set to BASE and OFFSET, otherwise return false
23948 after clearing BASE and OFFSET. */
23950 bool
23952 {
23953 rtx addr;
23960 {
23964 }
23968 {
23972 }
23978 }
23980 /* Types for scheduling fusion. */
23981 enum sched_fusion_type
23982 {
23984 SCHED_FUSION_LD_SIGN_EXTEND,
23985 SCHED_FUSION_LD_ZERO_EXTEND,
23986 SCHED_FUSION_LD,
23987 SCHED_FUSION_ST,
23988 SCHED_FUSION_NUM
23989 };
23991 /* If INSN is a load or store of address in the form of [base+offset],
23992 extract the two parts and set to BASE and OFFSET. Return scheduling
23993 fusion type this INSN is. */
23995 static enum sched_fusion_type
23997 {
24015 {
24020 }
24022 {
24027 }
24032 {
24035 }
24036 else
24043 }
24045 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
24047 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
24048 and PRI are only calculated for these instructions. For other instruction,
24049 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
24050 type instruction fusion can be added by returning different priorities.
24052 It's important that irrelevant instructions get the largest FUSION_PRI. */
24054 static void
24057 {
24067 {
24071 }
24073 /* Set FUSION_PRI according to fusion type and base register. */
24076 /* Calculate PRI. */
24079 /* INSN with smaller offset goes first. */
24083 else
24088 }
24090 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
24091 Adjust priority of sha1h instructions so they are scheduled before
24092 other SHA1 instructions. */
24094 static int
24096 {
24100 {
24105 }
24108 }
24110 /* Given OPERANDS of consecutive load/store, check if we can merge
24111 them into ldp/stp. LOAD is true if they are load instructions.
24112 MODE is the mode of memory operands. */
24114 bool
24116 machine_mode mode)
24117 {
24123 {
24131 }
24132 else
24133 {
24138 }
24140 /* The mems cannot be volatile. */
24144 /* If we have SImode and slow unaligned ldp,
24145 check the alignment to be at least 8 byte. */
24149 && !optimize_size
24153 /* Check if the addresses are in the form of [base+offset]. */
24161 /* Check if the bases are same. */
24165 /* The operands must be of the same size. */
24171 /* We should only be trying this for fixed-sized modes. There is no
24172 SVE LDP/STP instruction. */
24174 /* Check if the offsets are consecutive. */
24178 /* Check if the addresses are clobbered by load. */
24180 {
24184 /* In increasing order, the last load can clobber the address. */
24187 }
24189 /* One of the memory accesses must be a mempair operand.
24190 If it is not the first one, they need to be swapped by the
24191 peephole. */
24198 else
24203 else
24206 /* Check if the registers are of same class. */
24211 }
24213 /* Given OPERANDS of consecutive load/store that can be merged,
24214 swap them if they are not in ascending order. */
24215 void
24217 {
24222 {
24225 }
24226 else
24227 {
24230 }
24239 {
24240 /* Irrespective of whether this is a load or a store,
24241 we do the same swap. */
24244 }
24245 }
24247 /* Taking X and Y to be HOST_WIDE_INT pointers, return the result of a
24248 comparison between the two. */
24249 int
24251 {
24254 }
24256 /* Taking X and Y to be pairs of RTX, one pointing to a MEM rtx and the
24257 other pointing to a REG rtx containing an offset, compare the offsets
24258 of the two pairs.
24260 Return:
24262 1 iff offset (X) > offset (Y)
24263 0 iff offset (X) == offset (Y)
24264 -1 iff offset (X) < offset (Y) */
24265 int
24267 {
24274 else
24279 else
24282 /* Extract the offsets. */
24289 }
24291 /* Given OPERANDS of consecutive load/store, check if we can merge
24292 them into ldp/stp by adjusting the offset. LOAD is true if they
24293 are load instructions. MODE is the mode of memory operands.
24295 Given below consecutive stores:
24297 str w1, [xb, 0x100]
24298 str w1, [xb, 0x104]
24299 str w1, [xb, 0x108]
24300 str w1, [xb, 0x10c]
24302 Though the offsets are out of the range supported by stp, we can
24303 still pair them after adjusting the offset, like:
24305 add scratch, xb, 0x100
24306 stp w1, w1, [scratch]
24307 stp w1, w1, [scratch, 0x8]
24309 The peephole patterns detecting this opportunity should guarantee
24310 the scratch register is avaliable. */
24312 bool
24314 machine_mode mode)
24315 {
24322 {
24324 {
24329 }
24331 /* Do not attempt to merge the loads if the loads clobber each other. */
24336 }
24337 else
24339 {
24342 }
24344 /* Skip if memory operand is by itself valid for ldp/stp. */
24349 {
24350 /* The mems cannot be volatile. */
24354 /* Check if the addresses are in the form of [base+offset]. */
24358 }
24360 /* Check if the registers are of same class. */
24366 {
24369 }
24370 else
24371 {
24374 }
24376 /* Only the last register in the order in which they occur
24377 may be clobbered by the load. */
24383 /* Check if the bases are same. */
24393 /* Check if the offsets can be put in the right order to do a ldp/stp. */
24395 aarch64_host_wide_int_compare);
24401 /* Check that offsets are within range of each other. The ldp/stp
24402 instructions have 7 bit immediate offsets, so use 0x80. */
24406 /* The offsets must be aligned with respect to each other. */
24410 /* If we have SImode and slow unaligned ldp,
24411 check the alignment to be at least 8 byte. */
24415 && !optimize_size
24420 }
24422 /* Given OPERANDS of consecutive load/store, this function pairs them
24423 into LDP/STP after adjusting the offset. It depends on the fact
24424 that the operands can be sorted so the offsets are correct for STP.
24425 MODE is the mode of memory operands. CODE is the rtl operator
24426 which should be applied to all memory operands, it's SIGN_EXTEND,
24427 ZERO_EXTEND or UNKNOWN. */
24429 bool
24432 {
24439 /* We make changes on a copy as we may still bail out. */
24443 /* Sort the operands. */
24446 /* Copy the memory operands so that if we have to bail for some
24447 reason the original addresses are unchanged. */
24449 {
24454 }
24455 else
24456 {
24462 }
24469 /* Adjust offset so it can fit in LDP/STP instruction. */
24477 /* The base offset is optimally half way between the two STP/LDP offsets. */
24480 else
24481 /* However, due to issues with negative LDP/STP offset generation for
24482 larger modes, for DF, DI and vector modes. we must not use negative
24483 addresses smaller than 9 signed unadjusted bits can store. This
24484 provides the most range in this case. */
24487 /* Adjust the base so that it is aligned with the addresses but still
24488 optimal. */
24490 /* Fix the offset, bearing in mind we want to make it bigger not
24491 smaller. */
24494 /* The negative range of LDP/STP is one larger than the positive range. */
24497 /* Check if base offset is too big or too small. We can attempt to resolve
24498 this issue by setting it to the maximum value and seeing if the offsets
24499 still fit. */
24501 {
24503 /* We must still make sure that the base offset is aligned with respect
24504 to the address. But it may not be made any bigger. */
24506 }
24508 /* Likewise for the case where the base is too small. */
24510 {
24513 }
24515 /* Offset of the first STP/LDP. */
24518 /* Offset of the second STP/LDP. */
24521 /* The offsets must be within the range of the LDP/STP instructions. */
24540 {
24545 }
24547 {
24552 }
24555 {
24564 }
24565 else
24566 {
24575 }
24577 /* Emit adjusting instruction. */
24579 /* Emit ldp/stp instructions. */
24587 }
24589 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
24590 it isn't worth branching around empty masked ops (including masked
24591 stores). */
24593 static bool
24595 {
24597 }
24599 /* Return 1 if pseudo register should be created and used to hold
24600 GOT address for PIC code. */
24602 bool
24604 {
24606 }
24608 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
24610 static int
24612 {
24614 {
24621 }
24624 }
24627 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
24628 return the log2 of that value. Otherwise return -1. */
24630 int
24632 {
24647 }
24649 /* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a
24650 power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n)
24651 return n. Otherwise return -1. */
24653 int
24655 {
24656 REAL_VALUE_TYPE r0;
24664 {
24668 }
24670 }
24672 /* If X is a vector of equal CONST_DOUBLE values and that value is
24673 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
24675 int
24677 {
24695 }
24697 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
24698 to float.
24700 __fp16 always promotes through this hook.
24701 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
24702 through the generic excess precision logic rather than here. */
24704 static tree
24706 {
24712 }
24714 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
24716 static bool
24718 optimization_type opt_type)
24719 {
24721 {
24727 }
24728 }
24730 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
24732 static unsigned int
24735 {
24736 /* Polynomial invariant 1 == (VG / 2) - 1. */
24741 }
24743 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
24744 if MODE is HFmode, and punt to the generic implementation otherwise. */
24746 static bool
24748 {
24752 }
24754 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
24755 if MODE is HFmode, and punt to the generic implementation otherwise. */
24757 static bool
24759 {
24763 }
24765 /* Set the value of FLT_EVAL_METHOD.
24766 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
24768 0: evaluate all operations and constants, whose semantic type has at
24769 most the range and precision of type float, to the range and
24770 precision of float; evaluate all other operations and constants to
24771 the range and precision of the semantic type;
24773 N, where _FloatN is a supported interchange floating type
24774 evaluate all operations and constants, whose semantic type has at
24775 most the range and precision of _FloatN type, to the range and
24776 precision of the _FloatN type; evaluate all other operations and
24777 constants to the range and precision of the semantic type;
24779 If we have the ARMv8.2-A extensions then we support _Float16 in native
24780 precision, so we should set this to 16. Otherwise, we support the type,
24781 but want to evaluate expressions in float precision, so set this to
24782 0. */
24784 static enum flt_eval_method
24786 {
24788 {
24791 /* We can calculate either in 16-bit range and precision or
24792 32-bit range and precision. Make that decision based on whether
24793 we have native support for the ARMv8.2-A 16-bit floating-point
24794 instructions or not. */
24796 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
24802 }
24804 }
24806 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
24807 scheduled for speculative execution. Reject the long-running division
24808 and square-root instructions. */
24810 static bool
24812 {
24814 {
24832 }
24833 }
24835 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
24837 static int
24839 {
24843 /* PR_REGS isn't a useful pressure class because many predicate pseudo
24844 registers need to go in PR_LO_REGS at some point during their
24845 lifetime. Splitting it into two halves has the effect of making
24846 all predicates count against PR_LO_REGS, so that we try whenever
24847 possible to restrict the number of live predicates to 8. This
24848 greatly reduces the amount of spilling in certain loops. */
24852 }
24854 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
24856 static bool
24859 {
24872 /* Don't allow changes between predicate modes and other modes.
24873 Only predicate registers can hold predicate modes and only
24874 non-predicate registers can hold non-predicate modes, so any
24875 attempt to mix them would require a round trip through memory. */
24879 /* Don't allow changes between partial SVE modes and other modes.
24880 The contents of partial SVE modes are distributed evenly across
24881 the register, whereas GCC expects them to be clustered together. */
24885 /* Similarly reject changes between partial SVE modes that have
24886 different patterns of significant and insignificant bits. */
24893 {
24894 /* Don't allow changes between SVE modes and other modes that might
24895 be bigger than 128 bits. In particular, OImode, CImode and XImode
24896 divide into 128-bit quantities while SVE modes divide into
24897 BITS_PER_SVE_VECTOR quantities. */
24902 }
24905 {
24906 /* Don't allow changes between SVE data modes and non-SVE modes.
24907 See the comment at the head of aarch64-sve.md for details. */
24911 /* Don't allow changes in element size: lane 0 of the new vector
24912 would not then be lane 0 of the old vector. See the comment
24913 above aarch64_maybe_expand_sve_subreg_move for a more detailed
24914 description.
24916 In the worst case, this forces a register to be spilled in
24917 one mode and reloaded in the other, which handles the
24918 endianness correctly. */
24921 }
24923 }
24925 /* Implement TARGET_EARLY_REMAT_MODES. */
24927 static void
24929 {
24930 /* SVE values are not normally live across a call, so it should be
24931 worth doing early rematerialization even in VL-specific mode. */
24935 }
24937 /* Override the default target speculation_safe_value. */
24938 static rtx
24941 {
24942 /* Maybe we should warn if falling back to hard barriers. They are
24943 likely to be noticably more expensive than the alternative below. */
24955 }
24957 /* Implement TARGET_ESTIMATED_POLY_VALUE.
24958 Look into the tuning structure for an estimate.
24959 KIND specifies the type of requested estimate: min, max or likely.
24960 For cores with a known SVE width all three estimates are the same.
24961 For generic SVE tuning we want to distinguish the maximum estimate from
24962 the minimum and likely ones.
24963 The likely estimate is the same as the minimum in that case to give a
24964 conservative behavior of auto-vectorizing with SVE when it is a win
24965 even for 128-bit SVE.
24966 When SVE width information is available VAL.coeffs[1] is multiplied by
24967 the number of VQ chunks over the initial Advanced SIMD 128 bits. */
24969 static HOST_WIDE_INT
24971 poly_value_estimate_kind kind
24973 {
24974 enum aarch64_sve_vector_bits_enum width_source
24977 /* If there is no core-specific information then the minimum and likely
24978 values are based on 128-bit vectors and the maximum is based on
24979 the architectural maximum of 2048 bits. */
24982 {
24988 }
24990 /* If the core provides width information, use that. */
24993 }
24996 /* Return true for types that could be supported as SIMD return or
24997 argument types. */
24999 static bool
25001 {
25003 {
25006 }
25008 }
25010 /* Return true for types that currently are supported as SIMD return
25011 or argument types. */
25013 static bool
25015 {
25023 }
25025 /* Implement TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN. */
25027 static int
25031 {
25035 poly_uint64 vec_bits;
25040 /* For now, SVE simdclones won't produce illegal simdlen, So only check
25041 const simdlens here. */
25047 {
25051 }
25056 {
25059 "GCC does not currently support mixed size types "
25063 "GCC does not currently support return type %qT "
25065 else
25068 ret_type);
25070 }
25078 {
25083 {
25086 "GCC does not currently support mixed size types "
25088 else
25090 "GCC does not currently support argument type %qT "
25093 }
25094 }
25100 {
25104 }
25105 else
25106 {
25109 /* For now, SVE simdclones won't produce illegal simdlen, So only check
25110 const simdlens here. */
25113 {
25118 }
25119 }
25123 }
25125 /* Implement TARGET_SIMD_CLONE_ADJUST. */
25127 static void
25129 {
25130 /* Add aarch64_vector_pcs target attribute to SIMD clones so they
25131 use the correct ABI. */
25136 }
25138 /* Implement TARGET_SIMD_CLONE_USABLE. */
25140 static int
25142 {
25144 {
25151 }
25152 }
25154 /* Implement TARGET_COMP_TYPE_ATTRIBUTES */
25156 static int
25158 {
25166 };
25177 }
25179 /* Implement TARGET_GET_MULTILIB_ABI_NAME */
25183 {
25187 }
25189 /* Implement TARGET_STACK_PROTECT_GUARD. In case of a
25190 global variable based guard use the default else
25191 return a null tree. */
25192 static tree
25194 {
25199 }
25201 /* Return the diagnostic message string if conversion from FROMTYPE to
25202 TOTYPE is not allowed, NULL otherwise. */
25206 {
25208 {
25209 /* Do no allow conversions to/from BFmode scalar types. */
25214 }
25216 /* Conversion allowed. */
25218 }
25220 /* Return the diagnostic message string if the unary operation OP is
25221 not permitted on TYPE, NULL otherwise. */
25225 {
25226 /* Reject all single-operand operations on BFmode except for &. */
25230 /* Operation allowed. */
25232 }
25234 /* Return the diagnostic message string if the binary operation OP is
25235 not permitted on TYPE1 and TYPE2, NULL otherwise. */
25239 const_tree type2)
25240 {
25241 /* Reject all 2-operand operations on BFmode. */
25254 /* Operation allowed. */
25256 }
25258 /* Implement TARGET_MEMTAG_CAN_TAG_ADDRESSES. Here we tell the rest of the
25259 compiler that we automatically ignore the top byte of our pointers, which
25260 allows using -fsanitize=hwaddress. */
25261 bool
25263 {
25265 }
25267 /* Implement TARGET_ASM_FILE_END for AArch64. This adds the AArch64 GNU NOTE
25268 section at the end if needed. */
25269 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
25270 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
25271 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
25272 void
25274 {
25285 {
25286 /* Generate .note.gnu.property section. */
25290 /* PT_NOTE header: namesz, descsz, type.
25291 namesz = 4 ("GNU\0")
25292 descsz = 16 (Size of the program property array)
25293 [(12 + padding) * Number of array elements]
25294 type = 5 (NT_GNU_PROPERTY_TYPE_0). */
25300 /* PT_NOTE name. */
25303 /* PT_NOTE contents for NT_GNU_PROPERTY_TYPE_0:
25304 type = GNU_PROPERTY_AARCH64_FEATURE_1_AND
25305 datasz = 4
25306 data = feature_1_and. */
25311 /* Pad the size of the note to the required alignment. */
25313 }
25314 }
25315 #undef GNU_PROPERTY_AARCH64_FEATURE_1_PAC
25316 #undef GNU_PROPERTY_AARCH64_FEATURE_1_BTI
25317 #undef GNU_PROPERTY_AARCH64_FEATURE_1_AND
25319 /* Helper function for straight line speculation.
25320 Return what barrier should be emitted for straight line speculation
25321 mitigation.
25322 When not mitigating against straight line speculation this function returns
25323 an empty string.
25324 When mitigating against straight line speculation, use:
25325 * SB when the v8.5-A SB extension is enabled.
25326 * DSB+ISB otherwise. */
25329 {
25330 return mitigation_required
25333 }
25368 };
25370 /* Function to create a BLR thunk. This thunk is used to mitigate straight
25371 line speculation. Instead of a simple BLR that can be speculated past,
25372 we emit a BL to this thunk, and this thunk contains a BR to the relevant
25373 register. These thunks have the relevant speculation barries put after
25374 their indirect branch so that speculation is blocked.
25376 We use such a thunk so the speculation barriers are kept off the
25377 architecturally executed path in order to reduce the performance overhead.
25379 When optimizing for size we use stubs shared by the linked object.
25380 When optimizing for performance we emit stubs for each function in the hope
25381 that the branch predictor can better train on jumps specific for a given
25382 function. */
25383 rtx
25385 {
25388 {
25389 /* For the thunks shared between different functions in this compilation
25390 unit we use a named symbol -- this is just for users to more easily
25391 understand the generated assembly. */
25395 {
25396 /* Build a decl representing this function stub and record it for
25397 later. We build a decl here so we can use the GCC machinery for
25398 handling sections automatically (through `get_named_section` and
25399 `make_decl_one_only`). That saves us a lot of trouble handling
25400 the specifics of different output file formats. */
25404 NULL_TREE));
25414 }
25417 }
25423 }
25425 /* Helper function for aarch64_sls_emit_blr_function_thunks and
25426 aarch64_sls_emit_shared_blr_thunks below. */
25427 static void
25429 {
25430 /* Save in x16 and branch to that function so this transformation does
25431 not prevent jumping to `BTI c` instructions. */
25434 }
25436 /* Emit all BLR stubs for this particular function.
25437 Here we emit all the BLR stubs needed for the current function. Since we
25438 emit these stubs in a consecutive block we know there will be no speculation
25439 gadgets between each stub, and hence we only emit a speculation barrier at
25440 the end of the stub sequences.
25442 This is called in the TARGET_ASM_FUNCTION_EPILOGUE hook. */
25443 void
25445 {
25450 /* We must save and restore the current function section since this assembly
25451 is emitted at the end of the function. This means it can be emitted *just
25452 after* the cold section of a function. That cold part would be emitted in
25453 a different section. That switch would trigger a `.cfi_endproc` directive
25454 to be emitted in the original section and a `.cfi_startproc` directive to
25455 be emitted in the new section. Switching to the original section without
25456 restoring would mean that the `.cfi_endproc` emitted as a function ends
25457 would happen in a different section -- leaving an unmatched
25458 `.cfi_startproc` in the cold text section and an unmatched `.cfi_endproc`
25459 in the standard text section. */
25463 {
25472 }
25474 /* Can use the SB if needs be here, since this stub will only be used
25475 by the current function, and hence for the current target. */
25478 }
25480 /* Emit shared BLR stubs for the current compilation unit.
25481 Over the course of compiling this unit we may have converted some BLR
25482 instructions to a BL to a shared stub function. This is where we emit those
25483 stub functions.
25484 This function is for the stubs shared between different functions in this
25485 compilation unit. We share when optimizing for size instead of speed.
25487 This function is called through the TARGET_ASM_FILE_END hook. */
25488 void
25490 {
25495 {
25504 /* Only emits if the compiler is configured for an assembler that can
25505 handle visibility directives. */
25510 /* Use the most conservative target to ensure it can always be used by any
25511 function in the translation unit. */
25514 }
25515 }
25517 /* Implement TARGET_ASM_FILE_END. */
25518 void
25520 {
25522 /* Since this function will be called for the ASM_FILE_END hook, we ensure
25523 that what would be called otherwise (e.g. `file_end_indicate_exec_stack`
25524 for FreeBSD) still gets called. */
25525 #ifdef TARGET_ASM_FILE_END
25527 #endif
25528 }
25532 {
25535 {
25538 }
25539 else
25542 }
25544 /* Target-specific selftests. */
25546 #if CHECKING_P
25550 /* Selftest for the RTL loader.
25551 Verify that the RTL loader copes with a dump from
25552 print_rtx_function. This is essentially just a test that class
25553 function_reader can handle a real dump, but it also verifies
25554 that lookup_reg_by_dump_name correctly handles hard regs.
25555 The presence of hard reg names in the dump means that the test is
25556 target-specific, hence it is in this file. */
25558 static void
25560 {
25572 /* Verify crtl->return_rtx. */
25576 }
25578 /* Run all target-specific selftests. */
25580 static void
25582 {
25584 }
25590 #undef TARGET_STACK_PROTECT_GUARD
25591 #define TARGET_STACK_PROTECT_GUARD aarch64_stack_protect_guard
25593 #undef TARGET_ADDRESS_COST
25594 #define TARGET_ADDRESS_COST aarch64_address_cost
25596 /* This hook will determines whether unnamed bitfields affect the alignment
25597 of the containing structure. The hook returns true if the structure
25598 should inherit the alignment requirements of an unnamed bitfield's
25599 type. */
25600 #undef TARGET_ALIGN_ANON_BITFIELD
25601 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
25603 #undef TARGET_ASM_ALIGNED_DI_OP
25606 #undef TARGET_ASM_ALIGNED_HI_OP
25609 #undef TARGET_ASM_ALIGNED_SI_OP
25612 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
25613 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
25614 hook_bool_const_tree_hwi_hwi_const_tree_true
25616 #undef TARGET_ASM_FILE_START
25617 #define TARGET_ASM_FILE_START aarch64_start_file
25619 #undef TARGET_ASM_OUTPUT_MI_THUNK
25620 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
25622 #undef TARGET_ASM_SELECT_RTX_SECTION
25623 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
25625 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
25626 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
25628 #undef TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY
25629 #define TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY aarch64_print_patchable_function_entry
25631 #undef TARGET_BUILD_BUILTIN_VA_LIST
25632 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
25634 #undef TARGET_CALLEE_COPIES
25635 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_arg_info_false
25637 #undef TARGET_CAN_ELIMINATE
25638 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
25640 #undef TARGET_CAN_INLINE_P
25641 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
25643 #undef TARGET_CANNOT_FORCE_CONST_MEM
25644 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
25646 #undef TARGET_CASE_VALUES_THRESHOLD
25647 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
25649 #undef TARGET_CONDITIONAL_REGISTER_USAGE
25650 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
25652 #undef TARGET_MEMBER_TYPE_FORCES_BLK
25653 #define TARGET_MEMBER_TYPE_FORCES_BLK aarch64_member_type_forces_blk
25655 /* Only the least significant bit is used for initialization guard
25656 variables. */
25657 #undef TARGET_CXX_GUARD_MASK_BIT
25658 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
25660 #undef TARGET_C_MODE_FOR_SUFFIX
25661 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
25663 #ifdef TARGET_BIG_ENDIAN_DEFAULT
25664 #undef TARGET_DEFAULT_TARGET_FLAGS
25665 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
25666 #endif
25668 #undef TARGET_CLASS_MAX_NREGS
25669 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
25671 #undef TARGET_BUILTIN_DECL
25672 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
25674 #undef TARGET_BUILTIN_RECIPROCAL
25675 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
25677 #undef TARGET_C_EXCESS_PRECISION
25678 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
25680 #undef TARGET_EXPAND_BUILTIN
25681 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
25683 #undef TARGET_EXPAND_BUILTIN_VA_START
25684 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
25686 #undef TARGET_FOLD_BUILTIN
25687 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
25689 #undef TARGET_FUNCTION_ARG
25690 #define TARGET_FUNCTION_ARG aarch64_function_arg
25692 #undef TARGET_FUNCTION_ARG_ADVANCE
25693 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
25695 #undef TARGET_FUNCTION_ARG_BOUNDARY
25696 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
25698 #undef TARGET_FUNCTION_ARG_PADDING
25699 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
25701 #undef TARGET_GET_RAW_RESULT_MODE
25702 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
25703 #undef TARGET_GET_RAW_ARG_MODE
25704 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
25706 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
25707 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
25709 #undef TARGET_FUNCTION_VALUE
25710 #define TARGET_FUNCTION_VALUE aarch64_function_value
25712 #undef TARGET_FUNCTION_VALUE_REGNO_P
25713 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
25715 #undef TARGET_GIMPLE_FOLD_BUILTIN
25716 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
25718 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
25719 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
25721 #undef TARGET_INIT_BUILTINS
25722 #define TARGET_INIT_BUILTINS aarch64_init_builtins
25724 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
25725 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
25726 aarch64_ira_change_pseudo_allocno_class
25728 #undef TARGET_LEGITIMATE_ADDRESS_P
25729 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
25731 #undef TARGET_LEGITIMATE_CONSTANT_P
25732 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
25734 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
25735 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
25736 aarch64_legitimize_address_displacement
25738 #undef TARGET_LIBGCC_CMP_RETURN_MODE
25739 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
25741 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
25742 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
25743 aarch64_libgcc_floating_mode_supported_p
25745 #undef TARGET_MANGLE_TYPE
25746 #define TARGET_MANGLE_TYPE aarch64_mangle_type
25748 #undef TARGET_INVALID_CONVERSION
25749 #define TARGET_INVALID_CONVERSION aarch64_invalid_conversion
25751 #undef TARGET_INVALID_UNARY_OP
25752 #define TARGET_INVALID_UNARY_OP aarch64_invalid_unary_op
25754 #undef TARGET_INVALID_BINARY_OP
25755 #define TARGET_INVALID_BINARY_OP aarch64_invalid_binary_op
25757 #undef TARGET_VERIFY_TYPE_CONTEXT
25758 #define TARGET_VERIFY_TYPE_CONTEXT aarch64_verify_type_context
25760 #undef TARGET_MEMORY_MOVE_COST
25761 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
25763 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
25764 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
25766 #undef TARGET_MUST_PASS_IN_STACK
25767 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
25769 /* This target hook should return true if accesses to volatile bitfields
25770 should use the narrowest mode possible. It should return false if these
25771 accesses should use the bitfield container type. */
25772 #undef TARGET_NARROW_VOLATILE_BITFIELD
25773 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
25775 #undef TARGET_OPTION_OVERRIDE
25776 #define TARGET_OPTION_OVERRIDE aarch64_override_options
25778 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
25779 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
25780 aarch64_override_options_after_change
25782 #undef TARGET_OFFLOAD_OPTIONS
25783 #define TARGET_OFFLOAD_OPTIONS aarch64_offload_options
25785 #undef TARGET_OPTION_SAVE
25786 #define TARGET_OPTION_SAVE aarch64_option_save
25788 #undef TARGET_OPTION_RESTORE
25789 #define TARGET_OPTION_RESTORE aarch64_option_restore
25791 #undef TARGET_OPTION_PRINT
25792 #define TARGET_OPTION_PRINT aarch64_option_print
25794 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
25795 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
25797 #undef TARGET_SET_CURRENT_FUNCTION
25798 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
25800 #undef TARGET_PASS_BY_REFERENCE
25801 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
25803 #undef TARGET_PREFERRED_RELOAD_CLASS
25804 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
25806 #undef TARGET_SCHED_REASSOCIATION_WIDTH
25807 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
25809 #undef TARGET_PROMOTED_TYPE
25810 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
25812 #undef TARGET_SECONDARY_RELOAD
25813 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
25815 #undef TARGET_SHIFT_TRUNCATION_MASK
25816 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
25818 #undef TARGET_SETUP_INCOMING_VARARGS
25819 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
25821 #undef TARGET_STRUCT_VALUE_RTX
25822 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
25824 #undef TARGET_REGISTER_MOVE_COST
25825 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
25827 #undef TARGET_RETURN_IN_MEMORY
25828 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
25830 #undef TARGET_RETURN_IN_MSB
25831 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
25833 #undef TARGET_RTX_COSTS
25834 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
25836 #undef TARGET_SCALAR_MODE_SUPPORTED_P
25837 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
25839 #undef TARGET_SCHED_ISSUE_RATE
25840 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
25842 #undef TARGET_SCHED_VARIABLE_ISSUE
25843 #define TARGET_SCHED_VARIABLE_ISSUE aarch64_sched_variable_issue
25845 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
25846 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
25847 aarch64_sched_first_cycle_multipass_dfa_lookahead
25849 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
25850 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
25851 aarch64_first_cycle_multipass_dfa_lookahead_guard
25853 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
25854 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
25855 aarch64_get_separate_components
25857 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
25858 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
25859 aarch64_components_for_bb
25861 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
25862 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
25863 aarch64_disqualify_components
25865 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
25866 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
25867 aarch64_emit_prologue_components
25869 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
25870 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
25871 aarch64_emit_epilogue_components
25873 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
25874 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
25875 aarch64_set_handled_components
25877 #undef TARGET_TRAMPOLINE_INIT
25878 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
25880 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
25881 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
25883 #undef TARGET_VECTOR_MODE_SUPPORTED_P
25884 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
25886 #undef TARGET_COMPATIBLE_VECTOR_TYPES_P
25887 #define TARGET_COMPATIBLE_VECTOR_TYPES_P aarch64_compatible_vector_types_p
25889 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
25890 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
25891 aarch64_builtin_support_vector_misalignment
25893 #undef TARGET_ARRAY_MODE
25894 #define TARGET_ARRAY_MODE aarch64_array_mode
25896 #undef TARGET_ARRAY_MODE_SUPPORTED_P
25897 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
25899 #undef TARGET_VECTORIZE_INIT_COST
25900 #define TARGET_VECTORIZE_INIT_COST aarch64_init_cost
25902 #undef TARGET_VECTORIZE_ADD_STMT_COST
25903 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
25905 #undef TARGET_VECTORIZE_FINISH_COST
25906 #define TARGET_VECTORIZE_FINISH_COST aarch64_finish_cost
25908 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
25909 #define TARGET_VECTORIZE_DESTROY_COST_DATA aarch64_destroy_cost_data
25911 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
25912 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
25913 aarch64_builtin_vectorization_cost
25915 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
25916 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
25918 #undef TARGET_VECTORIZE_BUILTINS
25919 #define TARGET_VECTORIZE_BUILTINS
25921 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
25922 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
25923 aarch64_builtin_vectorized_function
25925 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
25926 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES \
25927 aarch64_autovectorize_vector_modes
25929 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
25930 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
25931 aarch64_atomic_assign_expand_fenv
25933 /* Section anchor support. */
25935 #undef TARGET_MIN_ANCHOR_OFFSET
25936 #define TARGET_MIN_ANCHOR_OFFSET -256
25938 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
25939 byte offset; we can do much more for larger data types, but have no way
25940 to determine the size of the access. We assume accesses are aligned. */
25941 #undef TARGET_MAX_ANCHOR_OFFSET
25942 #define TARGET_MAX_ANCHOR_OFFSET 4095
25944 #undef TARGET_VECTOR_ALIGNMENT
25945 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
25947 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
25948 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
25949 aarch64_vectorize_preferred_vector_alignment
25950 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
25951 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
25952 aarch64_simd_vector_alignment_reachable
25954 /* vec_perm support. */
25956 #undef TARGET_VECTORIZE_VEC_PERM_CONST
25957 #define TARGET_VECTORIZE_VEC_PERM_CONST \
25958 aarch64_vectorize_vec_perm_const
25960 #undef TARGET_VECTORIZE_RELATED_MODE
25961 #define TARGET_VECTORIZE_RELATED_MODE aarch64_vectorize_related_mode
25962 #undef TARGET_VECTORIZE_GET_MASK_MODE
25963 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
25964 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
25965 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
25966 aarch64_empty_mask_is_expensive
25967 #undef TARGET_PREFERRED_ELSE_VALUE
25968 #define TARGET_PREFERRED_ELSE_VALUE \
25969 aarch64_preferred_else_value
25971 #undef TARGET_INIT_LIBFUNCS
25972 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
25974 #undef TARGET_FIXED_CONDITION_CODE_REGS
25975 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
25977 #undef TARGET_FLAGS_REGNUM
25978 #define TARGET_FLAGS_REGNUM CC_REGNUM
25980 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
25981 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
25983 #undef TARGET_ASAN_SHADOW_OFFSET
25984 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
25986 #undef TARGET_LEGITIMIZE_ADDRESS
25987 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
25989 #undef TARGET_SCHED_CAN_SPECULATE_INSN
25990 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
25992 #undef TARGET_CAN_USE_DOLOOP_P
25993 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
25995 #undef TARGET_SCHED_ADJUST_PRIORITY
25996 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
25998 #undef TARGET_SCHED_MACRO_FUSION_P
25999 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
26001 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
26002 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
26004 #undef TARGET_SCHED_FUSION_PRIORITY
26005 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
26007 #undef TARGET_UNSPEC_MAY_TRAP_P
26008 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
26010 #undef TARGET_USE_PSEUDO_PIC_REG
26011 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
26013 #undef TARGET_PRINT_OPERAND
26014 #define TARGET_PRINT_OPERAND aarch64_print_operand
26016 #undef TARGET_PRINT_OPERAND_ADDRESS
26017 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
26019 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
26020 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA aarch64_output_addr_const_extra
26022 #undef TARGET_OPTAB_SUPPORTED_P
26023 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
26025 #undef TARGET_OMIT_STRUCT_RETURN_REG
26026 #define TARGET_OMIT_STRUCT_RETURN_REG true
26028 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
26029 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
26030 aarch64_dwarf_poly_indeterminate_value
26032 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
26033 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
26034 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
26036 #undef TARGET_HARD_REGNO_NREGS
26037 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
26038 #undef TARGET_HARD_REGNO_MODE_OK
26039 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
26041 #undef TARGET_MODES_TIEABLE_P
26042 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
26044 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
26045 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
26046 aarch64_hard_regno_call_part_clobbered
26048 #undef TARGET_INSN_CALLEE_ABI
26049 #define TARGET_INSN_CALLEE_ABI aarch64_insn_callee_abi
26051 #undef TARGET_CONSTANT_ALIGNMENT
26052 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
26054 #undef TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE
26055 #define TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE \
26056 aarch64_stack_clash_protection_alloca_probe_range
26058 #undef TARGET_COMPUTE_PRESSURE_CLASSES
26059 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
26061 #undef TARGET_CAN_CHANGE_MODE_CLASS
26062 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
26064 #undef TARGET_SELECT_EARLY_REMAT_MODES
26065 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
26067 #undef TARGET_SPECULATION_SAFE_VALUE
26068 #define TARGET_SPECULATION_SAFE_VALUE aarch64_speculation_safe_value
26070 #undef TARGET_ESTIMATED_POLY_VALUE
26071 #define TARGET_ESTIMATED_POLY_VALUE aarch64_estimated_poly_value
26073 #undef TARGET_ATTRIBUTE_TABLE
26074 #define TARGET_ATTRIBUTE_TABLE aarch64_attribute_table
26076 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
26077 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
26078 aarch64_simd_clone_compute_vecsize_and_simdlen
26080 #undef TARGET_SIMD_CLONE_ADJUST
26081 #define TARGET_SIMD_CLONE_ADJUST aarch64_simd_clone_adjust
26083 #undef TARGET_SIMD_CLONE_USABLE
26084 #define TARGET_SIMD_CLONE_USABLE aarch64_simd_clone_usable
26086 #undef TARGET_COMP_TYPE_ATTRIBUTES
26087 #define TARGET_COMP_TYPE_ATTRIBUTES aarch64_comp_type_attributes
26089 #undef TARGET_GET_MULTILIB_ABI_NAME
26090 #define TARGET_GET_MULTILIB_ABI_NAME aarch64_get_multilib_abi_name
26092 #undef TARGET_FNTYPE_ABI
26093 #define TARGET_FNTYPE_ABI aarch64_fntype_abi
26095 #undef TARGET_MEMTAG_CAN_TAG_ADDRESSES
26096 #define TARGET_MEMTAG_CAN_TAG_ADDRESSES aarch64_can_tag_addresses
26098 #if CHECKING_P
26099 #undef TARGET_RUN_TARGET_SELFTESTS
26100 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests
26103 #undef TARGET_ASM_POST_CFI_STARTPROC
26104 #define TARGET_ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc
26106 #undef TARGET_STRICT_ARGUMENT_NAMING
26107 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
26109 #undef TARGET_MD_ASM_ADJUST
26110 #define TARGET_MD_ASM_ADJUST arm_md_asm_adjust
26112 #undef TARGET_ASM_FILE_END
26113 #define TARGET_ASM_FILE_END aarch64_asm_file_end
26115 #undef TARGET_ASM_FUNCTION_EPILOGUE
26116 #define TARGET_ASM_FUNCTION_EPILOGUE aarch64_sls_emit_blr_function_thunks