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[official-gcc.git] / gcc / config / arm / arm.h
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1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
23 /* Sometimes the directive `riscos' is checked. This does not imply that this
24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
27 extern void output_func_prologue ();
28 extern void output_func_epilogue ();
29 extern char *output_add_immediate ();
30 extern char *output_call ();
31 extern char *output_call_mem ();
32 extern char *output_move_double ();
33 extern char *output_mov_double_fpu_from_arm ();
34 extern char *output_mov_double_arm_from_fpu ();
35 extern char *output_mov_long_double_fpu_from_arm ();
36 extern char *output_mov_long_double_arm_from_fpu ();
37 extern char *output_mov_long_double_arm_from_arm ();
38 extern char *output_mov_immediate ();
39 extern char *output_multi_immediate ();
40 extern char *output_return_instruction ();
41 extern char *output_load_symbol ();
42 extern char *fp_immediate_constant ();
43 extern struct rtx_def *gen_compare_reg ();
44 extern struct rtx_def *arm_gen_store_multiple ();
45 extern struct rtx_def *arm_gen_load_multiple ();
46
47 extern char *arm_condition_codes[];
48
49 /* This is needed by the tail-calling peepholes */
50 extern int frame_pointer_needed;
51
52 \f
53 #ifndef CPP_PREDEFINES
54 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
55 #endif
56
57 #ifndef CPP_SPEC
58 #define CPP_SPEC "%{m6:-D__arm6__}"
59 #endif
60 \f
61 /* Run-time Target Specification. */
62 #ifndef TARGET_VERSION
63 #define TARGET_VERSION \
64 fputs (" (ARM/generic)", stderr);
65 #endif
66
67 /* Run-time compilation parameters selecting different hardware subsets.
68 On the ARM, misuse it in a different way. */
69 extern int target_flags;
70
71 /* Nonzero if the function prologue (and epilogue) should obey
72 the ARM Procedure Call Standard. */
73 #define TARGET_APCS (target_flags & 1)
74
75 /* Nonzero if the function prologue should output the function name to enable
76 the post mortem debugger to print a backtrace (very useful on RISCOS,
77 unused on RISCiX). Specifying this flag also enables -mapcs.
78 XXX Must still be implemented in the prologue. */
79 #define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
80
81 /* Nonzero if floating point instructions are emulated by the FPE, in which
82 case instruction scheduling becomes very uninteresting. */
83 #define TARGET_FPE (target_flags & 4)
84
85 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
86 of condition flags when returning from a branch & link (ie. a function) */
87 #define TARGET_6 (target_flags & 8)
88
89 /* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which
90 are passed to the preprocessor and the assembler post-processor. They
91 aren't needed in the main pass of the compiler, but if we don't define
92 them in target switches cc1 complains about them. For the sake of
93 argument lets allocate bit 31 of target flags for such options. */
94
95 #ifndef ARM_EXTRA_TARGET_SWITCHES
96 #define ARM_EXTRA_TARGET_SWITCHES
97 #endif
98
99 #define TARGET_SWITCHES \
100 { \
101 {"apcs", 1}, \
102 {"poke-function-name", 2}, \
103 {"fpe", 4}, \
104 {"6", 8}, \
105 {"2", -8}, \
106 {"3", -8}, \
107 ARM_EXTRA_TARGET_SWITCHES \
108 {"", TARGET_DEFAULT } \
109 }
110
111 /* Which processor we are running on. Currently this is only used to
112 get the condition code clobbering attribute right when we are running on
113 an arm 6 */
114
115 enum processor_type
116 {
117 PROCESSOR_ARM2,
118 PROCESSOR_ARM3,
119 PROCESSOR_ARM6
120 };
121
122 /* Recast the cpu class to be the cpu attribute. */
123
124 /* Recast the cpu class to be the cpu attribute. */
125 #define arm_cpu_attr ((enum attr_cpu)arm_cpu)
126
127 extern enum processor_type arm_cpu;
128
129 #define TARGET_DEFAULT 0
130
131 #define TARGET_MEM_FUNCTIONS 1
132
133 /* OVERRIDE_OPTIONS takes care of the following:
134 - if -mpoke-function-name, then -mapcs.
135 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
136 - if floating point is done by emulation, forget about instruction
137 scheduling. Note that this only saves compilation time; it doesn't
138 matter for the final code. */
139
140 #define OVERRIDE_OPTIONS \
141 { \
142 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
143 warning ("-g without a frame pointer may not give sensible debugging");\
144 if (TARGET_POKE_FUNCTION_NAME) \
145 target_flags |= 1; \
146 if (TARGET_FPE) \
147 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
148 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
149 }
150 \f
151 /* Target machine storage Layout. */
152
153
154 /* Define this macro if it is advisable to hold scalars in registers
155 in a wider mode than that declared by the program. In such cases,
156 the value is constrained to be within the bounds of the declared
157 type, but kept valid in the wider mode. The signedness of the
158 extension may differ from that of the type. */
159
160 /* It is far faster to zero extend chars than to sign extend them */
161
162 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
163 if (GET_MODE_CLASS (MODE) == MODE_INT \
164 && GET_MODE_SIZE (MODE) < 4) \
165 { \
166 if (MODE == QImode) \
167 UNSIGNEDP = 1; \
168 else if (MODE == HImode) \
169 UNSIGNEDP = 0; \
170 (MODE) = SImode; \
171 }
172
173 /* Define for XFmode extended real floating point support.
174 This will automatically cause REAL_ARITHMETIC to be defined. */
175 /* For the ARM:
176 I think I have added all the code to make this work. Unfortunately,
177 early releases of the floating point emulation code on RISCiX used a
178 different format for extended precision numbers. On my RISCiX box there
179 is a bug somewhere which causes the machine to lock up when running enquire
180 with long doubles. There is the additional aspect that Norcroft C
181 treats long doubles as doubles and we ought to remain compatible.
182 Perhaps someone with an FPA coprocessor and not running RISCiX would like
183 to try this someday. */
184 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
185
186 /* Disable XFmode patterns in md file */
187 #define ENABLE_XF_PATTERNS 0
188
189 /* Define if you don't want extended real, but do want to use the
190 software floating point emulator for REAL_ARITHMETIC and
191 decimal <-> binary conversion. */
192 /* See comment above */
193 #define REAL_ARITHMETIC
194
195 /* Define this if most significant bit is lowest numbered
196 in instructions that operate on numbered bit-fields. */
197 #define BITS_BIG_ENDIAN 0
198
199 /* Define this if most significant byte of a word is the lowest numbered.
200 Most ARM processors are run in little endian mode, but it should now be
201 possible to build the compiler to support big endian code. (Note: This
202 is currently a compiler-build-time option, not a run-time one. */
203 #ifndef BYTES_BIG_ENDIAN
204 #define BYTES_BIG_ENDIAN 0
205 #endif
206
207 /* Define this if most significant word of a multiword number is the lowest
208 numbered. */
209 #define WORDS_BIG_ENDIAN 0
210
211 /* Define this if most significant word of doubles is the lowest numbered */
212 #define FLOAT_WORDS_BIG_ENDIAN 1
213
214 /* Number of bits in an addressable storage unit */
215 #define BITS_PER_UNIT 8
216
217 #define BITS_PER_WORD 32
218
219 #define UNITS_PER_WORD 4
220
221 #define POINTER_SIZE 32
222
223 #define PARM_BOUNDARY 32
224
225 #define STACK_BOUNDARY 32
226
227 #define FUNCTION_BOUNDARY 32
228
229 #define EMPTY_FIELD_BOUNDARY 32
230
231 #define BIGGEST_ALIGNMENT 32
232
233 /* Make strings word-aligned so strcpy from constants will be faster. */
234 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
235 (TREE_CODE (EXP) == STRING_CST \
236 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
237
238 /* Every structures size must be a multiple of 32 bits. */
239 #define STRUCTURE_SIZE_BOUNDARY 32
240
241 /* Non-zero if move instructions will actually fail to work
242 when given unaligned data. */
243 #define STRICT_ALIGNMENT 1
244
245 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
246
247 /* Define number of bits in most basic integer type.
248 (If undefined, default is BITS_PER_WORD). */
249 /* #define INT_TYPE_SIZE */
250 \f
251 /* Standard register usage. */
252
253 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
254 (S - saved over call).
255
256 r0 * argument word/integer result
257 r1-r3 argument word
258
259 r4-r8 S register variable
260 r9 S (rfp) register variable (real frame pointer)
261
262 r10 F S (sl) stack limit (not currently used)
263 r11 F S (fp) argument pointer
264 r12 (ip) temp workspace
265 r13 F S (sp) lower end of current stack frame
266 r14 (lr) link address/workspace
267 r15 F (pc) program counter
268
269 f0 floating point result
270 f1-f3 floating point scratch
271
272 f4-f7 S floating point variable
273
274 cc This is NOT a real register, but is used internally
275 to represent things that use or set the condition
276 codes.
277 sfp This isn't either. It is used during rtl generation
278 since the offset between the frame pointer and the
279 auto's isn't known until after register allocation.
280 afp Nor this, we only need this because of non-local
281 goto. Without it fp appears to be used and the
282 elimination code won't get rid of sfp. It tracks
283 fp exactly at all times.
284
285 *: See CONDITIONAL_REGISTER_USAGE */
286
287 /* The stack backtrace structure is as follows:
288 fp points to here: | save code pointer | [fp]
289 | return link value | [fp, #-4]
290 | return sp value | [fp, #-8]
291 | return fp value | [fp, #-12]
292 [| saved r10 value |]
293 [| saved r9 value |]
294 [| saved r8 value |]
295 [| saved r7 value |]
296 [| saved r6 value |]
297 [| saved r5 value |]
298 [| saved r4 value |]
299 [| saved r3 value |]
300 [| saved r2 value |]
301 [| saved r1 value |]
302 [| saved r0 value |]
303 [| saved f7 value |] three words
304 [| saved f6 value |] three words
305 [| saved f5 value |] three words
306 [| saved f4 value |] three words
307 r0-r3 are not normally saved in a C function. */
308
309 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
310 #define FIRST_PSEUDO_REGISTER 27
311
312 /* 1 for registers that have pervasive standard uses
313 and are not available for the register allocator. */
314 #define FIXED_REGISTERS \
315 { \
316 0,0,0,0,0,0,0,0, \
317 0,0,1,1,0,1,0,1, \
318 0,0,0,0,0,0,0,0, \
319 1,1,1 \
320 }
321
322 /* 1 for registers not available across function calls.
323 These must include the FIXED_REGISTERS and also any
324 registers that can be used without being saved.
325 The latter must include the registers where values are returned
326 and the register where structure-value addresses are passed.
327 Aside from that, you can include as many other registers as you like.
328 The CC is not preserved over function calls on the ARM 6, so it is
329 easier to assume this for all. SFP is preserved, since FP is. */
330 #define CALL_USED_REGISTERS \
331 { \
332 1,1,1,1,0,0,0,0, \
333 0,0,1,1,1,1,1,1, \
334 1,1,1,1,0,0,0,0, \
335 1,1,1 \
336 }
337
338 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
339 trampled. This effectively reduces the number of available registers by 1.
340 XXX It is a hack, I know.
341 XXX Is this still needed? */
342 #define CONDITIONAL_REGISTER_USAGE \
343 { \
344 if (obey_regdecls) \
345 fixed_regs[0] = 1; \
346 }
347
348 /* Return number of consecutive hard regs needed starting at reg REGNO
349 to hold something of mode MODE.
350 This is ordinarily the length in words of a value of mode MODE
351 but can be less for certain modes in special long registers.
352
353 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
354 mode. */
355 #define HARD_REGNO_NREGS(REGNO, MODE) \
356 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
357 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
358 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
359
360 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
361 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
362 regs holding FP. */
363 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
364 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
365 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
366 || REGNO == ARG_POINTER_REGNUM \
367 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
368
369 /* Value is 1 if it is a good idea to tie two pseudo registers
370 when one has mode MODE1 and one has mode MODE2.
371 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
372 for any hard reg, then this must be 0 for correct output. */
373 #define MODES_TIEABLE_P(MODE1, MODE2) \
374 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
375
376 /* Specify the registers used for certain standard purposes.
377 The values of these macros are register numbers. */
378
379 /* Define this if the program counter is overloaded on a register. */
380 #define PC_REGNUM 15
381
382 /* Register to use for pushing function arguments. */
383 #define STACK_POINTER_REGNUM 13
384
385 /* Base register for access to local variables of the function. */
386 #define FRAME_POINTER_REGNUM 25
387
388 /* Define this to be where the real frame pointer is if it is not possible to
389 work out the offset between the frame pointer and the automatic variables
390 until after register allocation has taken place. FRAME_POINTER_REGNUM
391 should point to a special register that we will make sure is eliminated. */
392 #define HARD_FRAME_POINTER_REGNUM 11
393
394 /* Value should be nonzero if functions must have frame pointers.
395 Zero means the frame pointer need not be set up (and parms may be accessed
396 via the stack pointer) in functions that seem suitable.
397 If we have to have a frame pointer we might as well make use of it.
398 APCS says that the frame pointer does not need to be pushed in leaf
399 functions. */
400 #define FRAME_POINTER_REQUIRED (TARGET_APCS && !leaf_function_p ())
401
402 /* Base register for access to arguments of the function. */
403 #define ARG_POINTER_REGNUM 26
404
405 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
406 as an invisible last argument (possible since varargs don't exist in
407 Pascal), so the following is not true. */
408 #define STATIC_CHAIN_REGNUM 8
409
410 /* Register in which address to store a structure value
411 is passed to a function. */
412 #define STRUCT_VALUE_REGNUM 0
413
414 /* Internal, so that we don't need to refer to a raw number */
415 #define CC_REGNUM 24
416
417 /* The order in which register should be allocated. It is good to use ip
418 since no saving is required (though calls clobber it) and it never contains
419 function parameters. It is quite good to use lr since other calls may
420 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
421 least likely to contain a function parameter; in addition results are
422 returned in r0.
423 */
424 #define REG_ALLOC_ORDER \
425 { \
426 3, 2, 1, 0, 12, 14, 4, 5, \
427 6, 7, 8, 10, 9, 11, 13, 15, \
428 16, 17, 18, 19, 20, 21, 22, 23, \
429 24, 25 \
430 }
431 \f
432 /* Register and constant classes. */
433
434 /* Register classes: all ARM regs or all FPU regs---simple! */
435 enum reg_class
436 {
437 NO_REGS,
438 FPU_REGS,
439 GENERAL_REGS,
440 ALL_REGS,
441 LIM_REG_CLASSES
442 };
443
444 #define N_REG_CLASSES (int) LIM_REG_CLASSES
445
446 /* Give names of register classes as strings for dump file. */
447 #define REG_CLASS_NAMES \
448 { \
449 "NO_REGS", \
450 "FPU_REGS", \
451 "GENERAL_REGS", \
452 "ALL_REGS", \
453 }
454
455 /* Define which registers fit in which classes.
456 This is an initializer for a vector of HARD_REG_SET
457 of length N_REG_CLASSES. */
458 #define REG_CLASS_CONTENTS \
459 { \
460 0x0000000, /* NO_REGS */ \
461 0x0FF0000, /* FPU_REGS */ \
462 0x200FFFF, /* GENERAL_REGS */ \
463 0x2FFFFFF /* ALL_REGS */ \
464 }
465
466 /* The same information, inverted:
467 Return the class number of the smallest class containing
468 reg number REGNO. This could be a conditional expression
469 or could index an array. */
470 #define REGNO_REG_CLASS(REGNO) \
471 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
472 || REGNO == ARG_POINTER_REGNUM) \
473 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
474 ? NO_REGS : FPU_REGS)
475
476 /* The class value for index registers, and the one for base regs. */
477 #define INDEX_REG_CLASS GENERAL_REGS
478 #define BASE_REG_CLASS GENERAL_REGS
479
480 /* Get reg_class from a letter such as appears in the machine description.
481 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
482 #define REG_CLASS_FROM_LETTER(C) \
483 ((C)=='f' ? FPU_REGS : NO_REGS)
484
485 /* The letters I, J, K, L and M in a register constraint string
486 can be used to stand for particular ranges of immediate operands.
487 This macro defines what the ranges are.
488 C is the letter, and VALUE is a constant value.
489 Return 1 if VALUE is in the range specified by C.
490 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
491 J: valid indexing constants.
492 K: ~value ok in rhs argument of data operand.
493 L: -value ok in rhs argument of data operand.
494 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
495 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
496 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
497 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
498 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
499 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
500 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
501 || (((VALUE) & ((VALUE) - 1)) == 0)) \
502 : 0)
503
504 /* For the ARM, `Q' means that this is a memory operand that is just
505 an offset from a register.
506 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
507 address. This means that the symbol is in the text segment and can be
508 accessed without using a load. */
509
510 #define EXTRA_CONSTRAINT(OP, C) \
511 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
512 : (C) == 'R' ? (GET_CODE (OP) == MEM \
513 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
514 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
515 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0)
516
517 /* Constant letter 'G' for the FPU immediate constants.
518 'H' means the same constant negated. */
519 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
520 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
521 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
522
523 /* Given an rtx X being reloaded into a reg required to be
524 in class CLASS, return the class of reg to actually use.
525 In general this is just CLASS; but on some machines
526 in some cases it is preferable to use a more restrictive class. */
527 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
528
529 /* Return the register class of a scratch register needed to copy IN into
530 or out of a register in CLASS in MODE. If it can be done directly,
531 NO_REGS is returned. */
532 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
533 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
534 && true_regnum (X) == -1) ? GENERAL_REGS \
535 : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS)
536
537 /* Return the maximum number of consecutive registers
538 needed to represent mode MODE in a register of class CLASS.
539 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
540 #define CLASS_MAX_NREGS(CLASS, MODE) \
541 ((CLASS) == FPU_REGS ? 1 \
542 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
543
544 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
545 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
546 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
547 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
548 ? 20 : 2)
549 \f
550 /* Stack layout; function entry, exit and calling. */
551
552 /* Define this if pushing a word on the stack
553 makes the stack pointer a smaller address. */
554 #define STACK_GROWS_DOWNWARD 1
555
556 /* Define this if the nominal address of the stack frame
557 is at the high-address end of the local variables;
558 that is, each additional local variable allocated
559 goes at a more negative offset in the frame. */
560 #define FRAME_GROWS_DOWNWARD 1
561
562 /* Offset within stack frame to start allocating local variables at.
563 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
564 first local allocated. Otherwise, it is the offset to the BEGINNING
565 of the first local allocated. */
566 #define STARTING_FRAME_OFFSET 0
567
568 /* If we generate an insn to push BYTES bytes,
569 this says how many the stack pointer really advances by. */
570 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
571
572 /* Offset of first parameter from the argument pointer register value. */
573 #define FIRST_PARM_OFFSET(FNDECL) 4
574
575 /* Value is the number of byte of arguments automatically
576 popped when returning from a subroutine call.
577 FUNTYPE is the data type of the function (as a tree),
578 or for a library call it is an identifier node for the subroutine name.
579 SIZE is the number of bytes of arguments passed on the stack.
580
581 On the ARM, the caller does not pop any of its arguments that were passed
582 on the stack. */
583 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
584
585 /* Define how to find the value returned by a function.
586 VALTYPE is the data type of the value (as a tree).
587 If the precise function being called is known, FUNC is its FUNCTION_DECL;
588 otherwise, FUNC is 0. */
589 #define FUNCTION_VALUE(VALTYPE, FUNC) \
590 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
591 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
592 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
593
594 /* Define how to find the value returned by a library function
595 assuming the value has mode MODE. */
596 #define LIBCALL_VALUE(MODE) \
597 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
598 ? gen_rtx (REG, MODE, 16) \
599 : gen_rtx (REG, MODE, 0))
600
601 /* 1 if N is a possible register number for a function value.
602 On the ARM, only r0 and f0 can return results. */
603 #define FUNCTION_VALUE_REGNO_P(REGNO) \
604 ((REGNO) == 0 || (REGNO) == 16)
605
606 /* Define where to put the arguments to a function.
607 Value is zero to push the argument on the stack,
608 or a hard register in which to store the argument.
609
610 MODE is the argument's machine mode.
611 TYPE is the data type of the argument (as a tree).
612 This is null for libcalls where that information may
613 not be available.
614 CUM is a variable of type CUMULATIVE_ARGS which gives info about
615 the preceding args and about the function being called.
616 NAMED is nonzero if this argument is a named parameter
617 (otherwise it is an extra parameter matching an ellipsis).
618
619 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
620 other arguments are passed on the stack. If (NAMED == 0) (which happens
621 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
622 passed in the stack (function_prologue will indeed make it pass in the
623 stack if necessary). */
624 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
625 ((NAMED) \
626 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
627 : 0)
628
629 /* For an arg passed partly in registers and partly in memory,
630 this is the number of registers used.
631 For args passed entirely in registers or entirely in memory, zero. */
632 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
633 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
634 ? GET_MODE_SIZE (MODE) \
635 : int_size_in_bytes (TYPE)) \
636 ? 4 - (CUM) / 4 : 0)
637
638 /* A C type for declaring a variable that is used as the first argument of
639 `FUNCTION_ARG' and other related values. For some target machines, the
640 type `int' suffices and can hold the number of bytes of argument so far.
641
642 On the ARM, this is the number of bytes of arguments scanned so far. */
643 #define CUMULATIVE_ARGS int
644
645 /* Initialize a variable CUM of type CUMULATIVE_ARGS
646 for a call to a function whose data type is FNTYPE.
647 For a library call, FNTYPE is 0.
648 On the ARM, the offset starts at 0. */
649 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
650 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
651
652 /* Update the data in CUM to advance over an argument
653 of mode MODE and data type TYPE.
654 (TYPE is null for libcalls where that information may not be available.) */
655 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
656 (CUM) += ((MODE) != BLKmode \
657 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
658 : (int_size_in_bytes (TYPE) + 3) & ~3) \
659
660 /* 1 if N is a possible register number for function argument passing.
661 On the ARM, r0-r3 are used to pass args. */
662 #define FUNCTION_ARG_REGNO_P(REGNO) \
663 ((REGNO) >= 0 && (REGNO) <= 3)
664
665 /* Perform any actions needed for a function that is receiving a variable
666 number of arguments. CUM is as above. MODE and TYPE are the mode and type
667 of the current parameter. PRETEND_SIZE is a variable that should be set to
668 the amount of stack that must be pushed by the prolog to pretend that our
669 caller pushed it.
670
671 Normally, this macro will push all remaining incoming registers on the
672 stack and set PRETEND_SIZE to the length of the registers pushed.
673
674 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
675 named arg and all anonymous args onto the stack.
676 XXX I know the prologue shouldn't be pushing registers, but it is faster
677 that way. */
678 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
679 { \
680 extern int current_function_anonymous_args; \
681 current_function_anonymous_args = 1; \
682 if ((CUM) < 16) \
683 (PRETEND_SIZE) = 16 - (CUM); \
684 }
685
686 /* Generate assembly output for the start of a function. */
687 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
688 output_func_prologue ((STREAM), (SIZE))
689
690 /* Call the function profiler with a given profile label. The Acorn compiler
691 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
692 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
693 to mind about this! */
694 #define FUNCTION_PROFILER(STREAM,LABELNO) \
695 { \
696 fprintf(STREAM, "\tmov\t%sip, %slr\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
697 fprintf(STREAM, "\tbl\tmcount\n"); \
698 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
699 }
700
701 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
702 the stack pointer does not matter. The value is tested only in
703 functions that have frame pointers.
704 No definition is equivalent to always zero.
705
706 On the ARM, the function epilogue recovers the stack pointer from the
707 frame. */
708 #define EXIT_IGNORE_STACK 1
709
710 /* Generate the assembly code for function exit. */
711 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
712 output_func_epilogue ((STREAM), (SIZE))
713
714 /* Determine if the epilogue should be output as RTL.
715 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
716 #define USE_RETURN_INSN use_return_insn ()
717
718 /* Definitions for register eliminations.
719
720 This is an array of structures. Each structure initializes one pair
721 of eliminable registers. The "from" register number is given first,
722 followed by "to". Eliminations of the same "from" register are listed
723 in order of preference.
724
725 We have two registers that can be eliminated on the ARM. First, the
726 arg pointer register can often be eliminated in favor of the stack
727 pointer register. Secondly, the pseudo frame pointer register can always
728 be eliminated; it is replaced with either the stack or the real frame
729 pointer. */
730
731 #define ELIMINABLE_REGS \
732 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
733 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
734 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
735 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
736
737 /* Given FROM and TO register numbers, say whether this elimination is allowed.
738 Frame pointer elimination is automatically handled.
739
740 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
741 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
742 pointer, we must eliminate FRAME_POINTER_REGNUM into
743 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
744 #define CAN_ELIMINATE(FROM, TO) \
745 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
746
747 /* Define the offset between two registers, one to be eliminated, and the other
748 its replacement, at the start of a routine. */
749 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
750 { \
751 int volatile_func = arm_volatile_func (); \
752 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
753 (OFFSET) = 0; \
754 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
755 (OFFSET) = (get_frame_size () + 3 & ~3); \
756 else \
757 { \
758 int regno; \
759 int offset = 12; \
760 int saved_hard_reg = 0; \
761 \
762 if (! volatile_func) \
763 { \
764 for (regno = 0; regno <= 10; regno++) \
765 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
766 saved_hard_reg = 1, offset += 4; \
767 for (regno = 16; regno <=23; regno++) \
768 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
769 offset += 12; \
770 } \
771 if ((FROM) == FRAME_POINTER_REGNUM) \
772 (OFFSET) = -offset; \
773 else \
774 { \
775 if (! regs_ever_live[HARD_FRAME_POINTER_REGNUM]) \
776 offset -= 16; \
777 if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \
778 offset += 4; \
779 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
780 } \
781 } \
782 }
783
784 /* Output assembler code for a block containing the constant parts
785 of a trampoline, leaving space for the variable parts.
786
787 On the ARM, (if r8 is the static chain regnum, and remembering that
788 referencing pc adds an offset of 8) the trampoline looks like:
789 ldr r8, [pc, #0]
790 ldr pc, [pc]
791 .word static chain value
792 .word function's address */
793 #define TRAMPOLINE_TEMPLATE(FILE) \
794 { \
795 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", ARM_REG_PREFIX, \
796 ARM_REG_PREFIX); \
797 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", ARM_REG_PREFIX, \
798 ARM_REG_PREFIX); \
799 fprintf ((FILE), "\t.word\t0\n"); \
800 fprintf ((FILE), "\t.word\t0\n"); \
801 }
802
803 /* Length in units of the trampoline for entering a nested function. */
804 #define TRAMPOLINE_SIZE 16
805
806 /* Alignment required for a trampoline in units. */
807 #define TRAMPOLINE_ALIGN 4
808
809 /* Emit RTL insns to initialize the variable parts of a trampoline.
810 FNADDR is an RTX for the address of the function's pure code.
811 CXT is an RTX for the static chain value for the function. */
812 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
813 { \
814 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
815 (CXT)); \
816 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
817 (FNADDR)); \
818 }
819
820 \f
821 /* Addressing modes, and classification of registers for them. */
822
823 #define HAVE_POST_INCREMENT 1
824 #define HAVE_PRE_INCREMENT 1
825 #define HAVE_POST_DECREMENT 1
826 #define HAVE_PRE_DECREMENT 1
827
828 /* Macros to check register numbers against specific register classes. */
829
830 /* These assume that REGNO is a hard or pseudo reg number.
831 They give nonzero only if REGNO is a hard reg of the suitable class
832 or a pseudo reg currently allocated to a suitable hard reg.
833 Since they use reg_renumber, they are safe only once reg_renumber
834 has been allocated, which happens in local-alloc.c.
835
836 On the ARM, don't allow the pc to be used. */
837 #define REGNO_OK_FOR_BASE_P(REGNO) \
838 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
839 || (REGNO) == ARG_POINTER_REGNUM \
840 || (unsigned) reg_renumber[(REGNO)] < 15 \
841 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
842 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
843 #define REGNO_OK_FOR_INDEX_P(REGNO) \
844 REGNO_OK_FOR_BASE_P(REGNO)
845
846 /* Maximum number of registers that can appear in a valid memory address.
847 Shifts in addresses can't be by a register. */
848
849 #define MAX_REGS_PER_ADDRESS 2
850
851 /* Recognize any constant value that is a valid address. */
852 /* XXX We can address any constant, eventually... */
853 #if 0
854 #define CONSTANT_ADDRESS_P(X) \
855 ( GET_CODE(X) == LABEL_REF \
856 || GET_CODE(X) == SYMBOL_REF \
857 || GET_CODE(X) == CONST_INT \
858 || GET_CODE(X) == CONST )
859 #endif
860
861 #define CONSTANT_ADDRESS_P(X) \
862 (GET_CODE (X) == SYMBOL_REF \
863 && (CONSTANT_POOL_ADDRESS_P (X) \
864 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
865
866 /* Nonzero if the constant value X is a legitimate general operand.
867 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
868
869 On the ARM, allow any integer (invalid ones are removed later by insn
870 patterns), nice doubles and symbol_refs which refer to the function's
871 constant pool XXX. */
872 #define LEGITIMATE_CONSTANT_P(X) \
873 (GET_CODE (X) == CONST_INT \
874 || (GET_CODE (X) == CONST_DOUBLE \
875 && (const_double_rtx_ok_for_fpu (X) \
876 || neg_const_double_rtx_ok_for_fpu (X))) \
877 || CONSTANT_ADDRESS_P (X))
878
879 /* Symbols in the text segment can be accessed without indirecting via the
880 constant pool; it may take an extra binary operation, but this is still
881 faster than indirecting via memory. Don't do this when not optimizing,
882 since we won't be calculating al of the offsets necessary to do this
883 simplification. */
884
885 #define ENCODE_SECTION_INFO(decl) \
886 { \
887 if (optimize > 0 && TREE_CONSTANT (decl) \
888 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
889 { \
890 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
891 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
892 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
893 } \
894 }
895
896 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
897 and check its validity for a certain class.
898 We have two alternate definitions for each of them.
899 The usual definition accepts all pseudo regs; the other rejects
900 them unless they have been allocated suitable hard regs.
901 The symbol REG_OK_STRICT causes the latter definition to be used. */
902 #ifndef REG_OK_STRICT
903
904 /* Nonzero if X is a hard reg that can be used as a base reg
905 or if it is a pseudo reg. */
906 #define REG_OK_FOR_BASE_P(X) \
907 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
908 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
909
910 /* Nonzero if X is a hard reg that can be used as an index
911 or if it is a pseudo reg. */
912 #define REG_OK_FOR_INDEX_P(X) \
913 REG_OK_FOR_BASE_P(X)
914
915 #define REG_OK_FOR_PRE_POST_P(X) \
916 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
917 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
918
919 #else
920
921 /* Nonzero if X is a hard reg that can be used as a base reg. */
922 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
923
924 /* Nonzero if X is a hard reg that can be used as an index. */
925 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
926
927 #define REG_OK_FOR_PRE_POST_P(X) \
928 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
929 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
930 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
931 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
932
933 #endif
934 \f
935 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
936 that is a valid memory address for an instruction.
937 The MODE argument is the machine mode for the MEM expression
938 that wants to use this address.
939
940 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
941 #define BASE_REGISTER_RTX_P(X) \
942 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
943
944 #define INDEX_REGISTER_RTX_P(X) \
945 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
946
947 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
948 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
949 only be small constants. */
950 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
951 do \
952 { \
953 HOST_WIDE_INT range; \
954 enum rtx_code code = GET_CODE (INDEX); \
955 \
956 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
957 { \
958 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
959 && INTVAL (INDEX) > -1024 \
960 && (INTVAL (INDEX) & 3) == 0) \
961 goto LABEL; \
962 } \
963 else \
964 { \
965 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
966 goto LABEL; \
967 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
968 { \
969 rtx xiop0 = XEXP (INDEX, 0); \
970 rtx xiop1 = XEXP (INDEX, 1); \
971 if (INDEX_REGISTER_RTX_P (xiop0) \
972 && power_of_two_operand (xiop1, SImode)) \
973 goto LABEL; \
974 if (INDEX_REGISTER_RTX_P (xiop1) \
975 && power_of_two_operand (xiop0, SImode)) \
976 goto LABEL; \
977 } \
978 if (GET_MODE_SIZE (MODE) <= 4 \
979 && (code == LSHIFTRT || code == ASHIFTRT \
980 || code == ASHIFT || code == ROTATERT)) \
981 { \
982 rtx op = XEXP (INDEX, 1); \
983 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
984 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
985 && INTVAL (op) <= 31) \
986 goto LABEL; \
987 } \
988 range = (MODE) == HImode ? 4095 : 4096; \
989 if (code == CONST_INT && INTVAL (INDEX) < range \
990 && INTVAL (INDEX) > -range) \
991 goto LABEL; \
992 } \
993 } while (0)
994
995 /* Jump to LABEL if X is a valid address RTX. This must also take
996 REG_OK_STRICT into account when deciding about valid registers, but it uses
997 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
998 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
999 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1000 refs must be forced though a static cell to ensure addressability. */
1001 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1002 { \
1003 if (BASE_REGISTER_RTX_P (X)) \
1004 goto LABEL; \
1005 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1006 && GET_CODE (XEXP (X, 0)) == REG \
1007 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1008 goto LABEL; \
1009 else if ((MODE) == TImode) \
1010 ; \
1011 else if (GET_CODE (X) == PLUS) \
1012 { \
1013 rtx xop0 = XEXP(X,0); \
1014 rtx xop1 = XEXP(X,1); \
1015 \
1016 if (BASE_REGISTER_RTX_P (xop0)) \
1017 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1018 else if (BASE_REGISTER_RTX_P (xop1)) \
1019 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1020 } \
1021 else if (GET_CODE (X) == MINUS) \
1022 { \
1023 rtx xop0 = XEXP (X,0); \
1024 rtx xop1 = XEXP (X,1); \
1025 \
1026 if (BASE_REGISTER_RTX_P (xop0)) \
1027 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1028 } \
1029 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1030 && GET_CODE (X) == SYMBOL_REF \
1031 && CONSTANT_POOL_ADDRESS_P (X)) \
1032 goto LABEL; \
1033 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1034 && GET_CODE (XEXP (X, 0)) == REG \
1035 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1036 goto LABEL; \
1037 }
1038 \f
1039 /* Try machine-dependent ways of modifying an illegitimate address
1040 to be legitimate. If we find one, return the new, valid address.
1041 This macro is used in only one place: `memory_address' in explow.c.
1042
1043 OLDX is the address as it was before break_out_memory_refs was called.
1044 In some cases it is useful to look at this to decide what needs to be done.
1045
1046 MODE and WIN are passed so that this macro can use
1047 GO_IF_LEGITIMATE_ADDRESS.
1048
1049 It is always safe for this macro to do nothing. It exists to recognize
1050 opportunities to optimize the output.
1051
1052 On the ARM, try to convert [REG, #BIGCONST]
1053 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1054 where VALIDCONST == 0 in case of TImode. */
1055 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1056 { \
1057 if (GET_CODE (X) == PLUS) \
1058 { \
1059 rtx xop0 = XEXP (X, 0); \
1060 rtx xop1 = XEXP (X, 1); \
1061 \
1062 if (CONSTANT_P (xop0) && ! LEGITIMATE_CONSTANT_P (xop0)) \
1063 xop0 = force_reg (SImode, xop0); \
1064 if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \
1065 xop1 = force_reg (SImode, xop1); \
1066 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1067 { \
1068 HOST_WIDE_INT n, low_n; \
1069 rtx base_reg, val; \
1070 n = INTVAL (xop1); \
1071 \
1072 if (MODE == DImode) \
1073 { \
1074 low_n = n & 0x0f; \
1075 n &= ~0x0f; \
1076 if (low_n > 4) \
1077 { \
1078 n += 16; \
1079 low_n -= 16; \
1080 } \
1081 } \
1082 else \
1083 { \
1084 low_n = ((MODE) == TImode ? 0 \
1085 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1086 n -= low_n; \
1087 } \
1088 base_reg = gen_reg_rtx (SImode); \
1089 val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1090 GEN_INT (n)), NULL_RTX); \
1091 emit_move_insn (base_reg, val); \
1092 (X) = (low_n == 0 ? base_reg \
1093 : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \
1094 } \
1095 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1096 (X) = gen_rtx (PLUS, SImode, xop0, xop1); \
1097 } \
1098 else if (GET_CODE (X) == MINUS) \
1099 { \
1100 rtx xop0 = XEXP (X, 0); \
1101 rtx xop1 = XEXP (X, 1); \
1102 \
1103 if (CONSTANT_P (xop0)) \
1104 xop0 = force_reg (SImode, xop0); \
1105 if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \
1106 xop1 = force_reg (SImode, xop1); \
1107 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1108 (X) = gen_rtx (MINUS, SImode, xop0, xop1); \
1109 } \
1110 if (memory_address_p (MODE, X)) \
1111 goto WIN; \
1112 }
1113
1114
1115 /* Go to LABEL if ADDR (a legitimate address expression)
1116 has an effect that depends on the machine mode it is used for. */
1117 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1118 { \
1119 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1120 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1121 goto LABEL; \
1122 }
1123 \f
1124 /* Specify the machine mode that this machine uses
1125 for the index in the tablejump instruction. */
1126 #define CASE_VECTOR_MODE SImode
1127
1128 /* Define this if the tablejump instruction expects the table
1129 to contain offsets from the address of the table.
1130 Do not define this if the table should contain absolute addresses. */
1131 /* #define CASE_VECTOR_PC_RELATIVE */
1132
1133 /* Specify the tree operation to be used to convert reals to integers. */
1134 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1135
1136 /* This is the kind of divide that is easiest to do in the general case. */
1137 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1138
1139 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1140 unsigned is probably best, but may break some code. */
1141 #ifndef DEFAULT_SIGNED_CHAR
1142 #define DEFAULT_SIGNED_CHAR 0
1143 #endif
1144
1145 /* Don't cse the address of the function being compiled. */
1146 #define NO_RECURSIVE_FUNCTION_CSE 1
1147
1148 /* Max number of bytes we can move from memory to memory
1149 in one reasonably fast instruction. */
1150 #define MOVE_MAX 4
1151
1152 /* Define if operations between registers always perform the operation
1153 on the full register even if a narrower mode is specified. */
1154 #define WORD_REGISTER_OPERATIONS
1155
1156 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1157 will either zero-extend or sign-extend. The value of this macro should
1158 be the code that says which one of the two operations is implicitly
1159 done, NIL if none. */
1160 #define LOAD_EXTEND_OP(MODE) \
1161 ((MODE) == QImode ? ZERO_EXTEND \
1162 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1163
1164 /* Define this if zero-extension is slow (more than one real instruction).
1165 On the ARM, it is more than one instruction only if not fetching from
1166 memory. */
1167 /* #define SLOW_ZERO_EXTEND */
1168
1169 /* Nonzero if access to memory by bytes is slow and undesirable. */
1170 #define SLOW_BYTE_ACCESS 0
1171
1172 /* Immediate shift counts are truncated by the output routines (or was it
1173 the assembler?). Shift counts in a register are truncated by ARM. Note
1174 that the native compiler puts too large (> 32) immediate shift counts
1175 into a register and shifts by the register, letting the ARM decide what
1176 to do instead of doing that itself. */
1177 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1178 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1179 On the arm, Y in a register is used modulo 256 for the shift. Only for
1180 rotates is modulo 32 used. */
1181 /* #define SHIFT_COUNT_TRUNCATED 1 */
1182
1183 /* XX This is not true, is it? */
1184 /* All integers have the same format so truncation is easy. */
1185 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1186
1187 /* Calling from registers is a massive pain. */
1188 #define NO_FUNCTION_CSE 1
1189
1190 /* Chars and shorts should be passed as ints. */
1191 #define PROMOTE_PROTOTYPES 1
1192
1193 /* The machine modes of pointers and functions */
1194 #define Pmode SImode
1195 #define FUNCTION_MODE Pmode
1196
1197 /* The structure type of the machine dependent info field of insns
1198 No uses for this yet. */
1199 /* #define INSN_MACHINE_INFO struct machine_info */
1200
1201 /* The relative costs of various types of constants. Note that cse.c defines
1202 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1203 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1204 case CONST_INT: \
1205 if (const_ok_for_arm (INTVAL (RTX))) \
1206 return (OUTER_CODE) == SET ? 2 : -1; \
1207 else if (OUTER_CODE == AND \
1208 && const_ok_for_arm (~INTVAL (RTX))) \
1209 return -1; \
1210 else if ((OUTER_CODE == COMPARE \
1211 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1212 && const_ok_for_arm (-INTVAL (RTX))) \
1213 return -1; \
1214 else \
1215 return 5; \
1216 case CONST: \
1217 case LABEL_REF: \
1218 case SYMBOL_REF: \
1219 return 6; \
1220 case CONST_DOUBLE: \
1221 if (const_double_rtx_ok_for_fpu (RTX)) \
1222 return (OUTER_CODE) == SET ? 2 : -1; \
1223 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1224 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1225 return -1; \
1226 return(7);
1227
1228 #define ARM_FRAME_RTX(X) \
1229 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1230 || (X) == arg_pointer_rtx)
1231
1232 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1233 default: \
1234 return arm_rtx_costs (X, CODE, OUTER_CODE);
1235
1236 /* Moves to and from memory are quite expensive */
1237 #define MEMORY_MOVE_COST(MODE) 10
1238
1239 /* All address computations that can be done are free, but rtx cost returns
1240 the same for practically all of them. So we weight the differnt types
1241 of address here in the order (most pref first):
1242 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1243 #define ADDRESS_COST(X) \
1244 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1245 || GET_CODE (X) == SYMBOL_REF) \
1246 ? 0 \
1247 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1248 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1249 ? 10 \
1250 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1251 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1252 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1253 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1254 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1255 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1256 ? 1 : 0)) \
1257 : 4)))))
1258
1259
1260
1261 /* Try to generate sequences that don't involve branches, we can then use
1262 conditional instructions */
1263 #define BRANCH_COST 4
1264 \f
1265 /* Condition code information. */
1266 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1267 return the mode to be used for the comparison.
1268 CCFPEmode should be used with floating inequalites,
1269 CCFPmode should be used with floating equalities.
1270 CC_NOOVmode should be used with SImode integer equalites
1271 CCmode should be used otherwise. */
1272
1273 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1274
1275 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1276
1277 #define SELECT_CC_MODE(OP,X,Y) \
1278 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1279 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1280 : ((GET_MODE (X) == SImode) \
1281 && ((OP) == EQ || (OP) == NE) \
1282 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1283 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1284 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1285 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
1286 || GET_CODE (X) == LSHIFTRT \
1287 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1288 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1289 ? CC_NOOVmode \
1290 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1291
1292 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1293
1294 #define STORE_FLAG_VALUE 1
1295
1296 /* Define the information needed to generate branch insns. This is
1297 stored from the compare operation. Note that we can't use "rtx" here
1298 since it hasn't been defined! */
1299
1300 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1301 extern int arm_compare_fp;
1302
1303 /* Define the codes that are matched by predicates in arm.c */
1304 #define PREDICATE_CODES \
1305 {"s_register_operand", {SUBREG, REG}}, \
1306 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1307 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1308 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1309 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1310 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1311 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1312 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1313 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1314 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1315 {"load_multiple_operation", {PARALLEL}}, \
1316 {"store_multiple_operation", {PARALLEL}}, \
1317 {"equality_operator", {EQ, NE}}, \
1318 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1319 {"const_shift_operand", {CONST_INT}}, \
1320 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1321 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1322 {"multi_register_push", {PARALLEL}}, \
1323 {"cc_register", {REG}},
1324
1325 \f
1326 /* Assembler output control */
1327
1328 #ifndef ARM_OS_NAME
1329 #define ARM_OS_NAME "(generic)"
1330 #endif
1331
1332 /* The text to go at the start of the assembler file */
1333 #define ASM_FILE_START(STREAM) \
1334 { \
1335 extern char *version_string; \
1336 fprintf (STREAM,"%c Generated by gcc %s for ARM/%s\n", \
1337 ARM_COMMENT_CHAR, version_string, ARM_OS_NAME); \
1338 fprintf (STREAM,"%srfp\t.req\t%sr9\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1339 fprintf (STREAM,"%ssl\t.req\t%sr10\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1340 fprintf (STREAM,"%sfp\t.req\t%sr11\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1341 fprintf (STREAM,"%sip\t.req\t%sr12\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1342 fprintf (STREAM,"%ssp\t.req\t%sr13\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1343 fprintf (STREAM,"%slr\t.req\t%sr14\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1344 fprintf (STREAM,"%spc\t.req\t%sr15\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1345 }
1346
1347 #define ASM_APP_ON ""
1348 #define ASM_APP_OFF ""
1349
1350 /* Switch to the text or data segment. */
1351 #define TEXT_SECTION_ASM_OP ".text"
1352 #define DATA_SECTION_ASM_OP ".data"
1353
1354 /* The assembler's names for the registers. */
1355 #ifndef REGISTER_NAMES
1356 #define REGISTER_NAMES \
1357 { \
1358 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1359 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
1360 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1361 "cc", "sfp", "afp" \
1362 }
1363 #endif
1364
1365 #ifndef ADDITIONAL_REGISTER_NAMES
1366 #define ADDITIONAL_REGISTER_NAMES \
1367 { \
1368 {"a1", 0}, \
1369 {"a2", 1}, \
1370 {"a3", 2}, \
1371 {"a4", 3}, \
1372 {"v1", 4}, \
1373 {"v2", 5}, \
1374 {"v3", 6}, \
1375 {"v4", 7}, \
1376 {"v5", 8}, \
1377 {"v6", 9}, \
1378 {"rfp", 9}, /* Gcc used to call it this */ \
1379 {"sb", 9}, \
1380 {"v7", 10}, \
1381 {"r10", 10}, \
1382 {"r11", 11}, /* fp */ \
1383 {"r12", 12}, /* ip */ \
1384 {"r13", 13}, /* sp */ \
1385 {"r14", 14}, /* lr */ \
1386 {"r15", 15} /* pc */ \
1387 }
1388 #endif
1389
1390 /* Arm Assembler barfs on dollars */
1391 #define DOLLARS_IN_IDENTIFIERS 0
1392
1393 #define NO_DOLLAR_IN_LABEL
1394
1395 /* DBX register number for a given compiler register number */
1396 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1397
1398 /* Generate DBX debugging information. riscix.h will undefine this because
1399 the native assembler does not support stabs. */
1400 #define DBX_DEBUGGING_INFO 1
1401
1402 /* Acorn dbx moans about continuation chars, so don't use any. */
1403 #ifndef DBX_CONTIN_LENGTH
1404 #define DBX_CONTIN_LENGTH 0
1405 #endif
1406
1407 /* Output a source filename for the debugger. RISCiX dbx insists that the
1408 ``desc'' field is set to compiler version number >= 315 (sic). */
1409 #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1410 do { \
1411 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1412 &ltext_label_name[1]); \
1413 text_section (); \
1414 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1415 } while (0)
1416
1417 /* Output a label definition. */
1418 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
1419 arm_asm_output_label ((STREAM), (NAME))
1420
1421 /* Output a function label definition. */
1422 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1423 ASM_OUTPUT_LABEL(STREAM, NAME)
1424
1425 /* Output a globalising directive for a label. */
1426 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1427 (fprintf (STREAM, "\t.global\t"), \
1428 assemble_name (STREAM, NAME), \
1429 fputc ('\n',STREAM)) \
1430
1431 /* Output a reference to a label. */
1432 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1433 fprintf (STREAM, "_%s", NAME)
1434
1435 /* Make an internal label into a string. */
1436 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1437 sprintf (STRING, "*%s%d", PREFIX, NUM)
1438
1439 /* Output an internal label definition. */
1440 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1441 do \
1442 { \
1443 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1444 extern int arm_target_label, arm_ccfsm_state; \
1445 extern rtx arm_target_insn; \
1446 \
1447 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1448 && !strcmp (PREFIX, "L")) \
1449 { \
1450 arm_ccfsm_state = 0; \
1451 arm_target_insn = NULL; \
1452 } \
1453 strcpy (s, "*"); \
1454 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1455 arm_asm_output_label (STREAM, s); \
1456 } while (0)
1457
1458 /* Nothing special is done about jump tables */
1459 /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1460 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1461
1462 /* Construct a private name. */
1463 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1464 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1465 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1466
1467 /* Output a push or a pop instruction (only used when profiling). */
1468 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1469 fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1470 reg_names[REGNO])
1471
1472 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1473 fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1474 reg_names[REGNO])
1475
1476 /* Output a relative address. Not needed since jump tables are absolute
1477 but we must define it anyway. */
1478 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1479 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1480
1481 /* Output an element of a dispatch table. */
1482 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1483 fprintf (STREAM, "\t.word\tL%d\n", VALUE)
1484
1485 /* Output various types of constants. For real numbers we output hex, with
1486 a comment containing the "human" value, this allows us to pass NaN's which
1487 the riscix assembler doesn't understand (it also makes cross-assembling
1488 less likely to fail). */
1489
1490 #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
1491 do { char dstr[30]; \
1492 long l[3]; \
1493 arm_increase_location (12); \
1494 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1495 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1496 if (sizeof (int) == sizeof (long)) \
1497 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t%c long double %s\n", \
1498 l[2], l[1], l[0], ARM_COMMENT_CHAR, dstr); \
1499 else \
1500 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%c long double %s\n",\
1501 l[0], l[1], l[2], ARM_COMMENT_CHAR, dstr); \
1502 } while (0)
1503
1504
1505 #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1506 do { char dstr[30]; \
1507 long l[2]; \
1508 arm_increase_location (8); \
1509 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1510 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
1511 if (sizeof (int) == sizeof (long)) \
1512 fprintf (STREAM, "\t.long 0x%x, 0x%x\t%c double %s\n", l[0], \
1513 l[1], ARM_COMMENT_CHAR, dstr); \
1514 else \
1515 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%c double %s\n", l[0], \
1516 l[1], ARM_COMMENT_CHAR, dstr); \
1517 } while (0)
1518
1519 #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1520 do { char dstr[30]; \
1521 long l; \
1522 arm_increase_location (4); \
1523 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1524 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
1525 if (sizeof (int) == sizeof (long)) \
1526 fprintf (STREAM, "\t.word 0x%x\t%c float %s\n", l, \
1527 ARM_COMMENT_CHAR, dstr); \
1528 else \
1529 fprintf (STREAM, "\t.word 0x%lx\t%c float %s\n", l, \
1530 ARM_COMMENT_CHAR, dstr); \
1531 } while (0);
1532
1533 #define ASM_OUTPUT_INT(STREAM, EXP) \
1534 (fprintf (STREAM, "\t.word\t"), \
1535 output_addr_const (STREAM, (EXP)), \
1536 arm_increase_location (4), \
1537 fputc ('\n', STREAM))
1538
1539 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1540 (fprintf (STREAM, "\t.short\t"), \
1541 output_addr_const (STREAM, (EXP)), \
1542 arm_increase_location (2), \
1543 fputc ('\n', STREAM))
1544
1545 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1546 (fprintf (STREAM, "\t.byte\t"), \
1547 output_addr_const (STREAM, (EXP)), \
1548 arm_increase_location (1), \
1549 fputc ('\n', STREAM))
1550
1551 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1552 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1553 arm_increase_location (1))
1554
1555 #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
1556 output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN))
1557
1558 /* Output a gap. In fact we fill it with nulls. */
1559 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1560 (arm_increase_location (NBYTES), \
1561 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1562
1563 /* Align output to a power of two. Horrible /bin/as. */
1564 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1565 do \
1566 { \
1567 register int amount = 1 << (POWER); \
1568 extern int arm_text_location; \
1569 \
1570 if (amount == 2) \
1571 fprintf (STREAM, "\t.even\n"); \
1572 else \
1573 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1574 \
1575 if (in_text_section ()) \
1576 arm_text_location = ((arm_text_location + amount - 1) \
1577 & ~(amount - 1)); \
1578 } while (0)
1579
1580 /* Output a common block */
1581 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1582 (fprintf (STREAM, "\t.comm\t"), \
1583 assemble_name ((STREAM), (NAME)), \
1584 fprintf(STREAM, ", %d\t%c%d\n", ROUNDED, ARM_COMMENT_CHAR, SIZE))
1585
1586 /* Output a local common block. /bin/as can't do this, so hack a `.space' into
1587 the bss segment. Note that this is *bad* practice. */
1588 #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1589 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1590
1591 /* Output a source line for the debugger. */
1592 /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1593
1594 /* Output a #ident directive. */
1595 #define ASM_OUTPUT_IDENT(STREAM,STRING) \
1596 fprintf (STREAM,"- - - ident %s\n",STRING)
1597
1598 /* The assembler's parentheses characters. */
1599 #define ASM_OPEN_PAREN "("
1600 #define ASM_CLOSE_PAREN ")"
1601
1602 /* Target characters. */
1603 #define TARGET_BELL 007
1604 #define TARGET_BS 010
1605 #define TARGET_TAB 011
1606 #define TARGET_NEWLINE 012
1607 #define TARGET_VT 013
1608 #define TARGET_FF 014
1609 #define TARGET_CR 015
1610 \f
1611 /* Only perform branch elimination (by making instructions conditional) if
1612 we're optimising. Otherwise it's of no use anyway. */
1613 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1614 if (optimize) \
1615 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1616
1617 #ifndef ARM_COMMENT_CHAR
1618 #define ARM_COMMENT_CHAR '@'
1619 #endif
1620
1621 /* Default is for register names not to have a prefix. */
1622 #ifndef ARM_REG_PREFIX
1623 #define ARM_REG_PREFIX ""
1624 #endif
1625
1626 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1627 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1628 /* Output an operand of an instruction. */
1629 #define PRINT_OPERAND(STREAM, X, CODE) \
1630 arm_print_operand (STREAM, X, CODE)
1631
1632 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1633 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1634 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1635 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1636 ? ((~ (HOST_WIDE_INT) 0) \
1637 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1638 : 0))))
1639
1640 /* Output the address of an operand. */
1641 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1642 { \
1643 int is_minus = GET_CODE (X) == MINUS; \
1644 \
1645 if (GET_CODE (X) == REG) \
1646 fprintf (STREAM, "[%s%s, #0]", ARM_REG_PREFIX, \
1647 reg_names[REGNO (X)]); \
1648 else if (GET_CODE (X) == PLUS || is_minus) \
1649 { \
1650 rtx base = XEXP (X, 0); \
1651 rtx index = XEXP (X, 1); \
1652 char *base_reg_name; \
1653 HOST_WIDE_INT offset = 0; \
1654 if (GET_CODE (base) != REG) \
1655 { \
1656 /* Ensure that BASE is a register (one of them must be). */ \
1657 rtx temp = base; \
1658 base = index; \
1659 index = temp; \
1660 } \
1661 base_reg_name = reg_names[REGNO (base)]; \
1662 switch (GET_CODE (index)) \
1663 { \
1664 case CONST_INT: \
1665 offset = INTVAL (index); \
1666 if (is_minus) \
1667 offset = -offset; \
1668 fprintf (STREAM, "[%s%s, #%d]", ARM_REG_PREFIX, \
1669 base_reg_name, offset); \
1670 break; \
1671 \
1672 case REG: \
1673 fprintf (STREAM, "[%s%s, %s%s%s]", ARM_REG_PREFIX, \
1674 base_reg_name, is_minus ? "-" : "", \
1675 ARM_REG_PREFIX, reg_names[REGNO (index)] ); \
1676 break; \
1677 \
1678 case MULT: \
1679 case ASHIFTRT: \
1680 case LSHIFTRT: \
1681 case ASHIFT: \
1682 case ROTATERT: \
1683 { \
1684 fprintf (STREAM, "[%s%s, %s%s%s", ARM_REG_PREFIX, \
1685 base_reg_name, is_minus ? "-" : "", ARM_REG_PREFIX,\
1686 reg_names[REGNO (XEXP (index, 0))]); \
1687 arm_print_operand (STREAM, index, 'S'); \
1688 fputs ("]", STREAM); \
1689 break; \
1690 } \
1691 \
1692 default: \
1693 abort(); \
1694 } \
1695 } \
1696 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1697 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1698 { \
1699 extern int output_memory_reference_mode; \
1700 \
1701 if (GET_CODE (XEXP (X, 0)) != REG) \
1702 abort (); \
1703 \
1704 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1705 fprintf (STREAM, "[%s%s, #%s%d]!", ARM_REG_PREFIX, \
1706 reg_names[REGNO (XEXP (X, 0))], \
1707 GET_CODE (X) == PRE_DEC ? "-" : "", \
1708 GET_MODE_SIZE (output_memory_reference_mode)); \
1709 else \
1710 fprintf (STREAM, "[%s%s], #%s%d", ARM_REG_PREFIX, \
1711 reg_names[REGNO (XEXP (X, 0))], \
1712 GET_CODE (X) == POST_DEC ? "-" : "", \
1713 GET_MODE_SIZE (output_memory_reference_mode)); \
1714 } \
1715 else output_addr_const(STREAM, X); \
1716 }
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