1 2024-02-02 Tamar Christina <tamar.christina@arm.com>
3 PR tree-optimization/113588
4 PR tree-optimization/113467
5 * tree-vect-data-refs.cc
6 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
7 (vect_analyze_early_break_dependences): Update comments.
9 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
12 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
13 and PA_BUILTIN_SET_FPSR builtins.
14 * (pa_builtins_icode): Declare.
15 * (def_builtin, pa_fpu_init_builtins): New.
16 * (pa_init_builtins): Initialize FPU builtins.
17 * (pa_builtin_decl, pa_expand_builtin_1): New.
18 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
19 PA_BUILTIN_SET_FPSR builtins.
20 * (pa_atomic_assign_expand_fenv): New.
21 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
23 (get_fpsr, put_fpsr): New expanders.
24 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
27 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
30 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
32 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
34 * doc/extend.texi (Common Type Attributes): Fix typo in
35 description of hardbool.
37 2024-02-02 Jakub Jelinek <jakub@redhat.com>
39 PR tree-optimization/113692
40 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
41 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
44 2024-02-02 Jakub Jelinek <jakub@redhat.com>
47 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
48 uninitialized large/huge _BitInt SSA_NAME inputs.
50 2024-02-02 Jakub Jelinek <jakub@redhat.com>
53 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
54 around wi::to_wide in order to compare value in prec precision.
56 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
59 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
61 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
63 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
65 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
67 2024-02-02 Pan Li <pan2.li@intel.com>
69 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
70 (riscv_pass_by_reference): Ditto.
71 (riscv_fntype_abi): Ditto.
73 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
75 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
76 (pre_vsetvl::cleaup): Remove vsetvl_pre.
77 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
79 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
81 * config/loongarch/larchintrin.h
82 (__frecipe_s): Update function return type.
87 2024-02-02 Li Wei <liwei@loongson.cn>
89 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
90 (loongarch_vector_costs::add_stmt_cost): Adjust.
92 2024-02-02 Xi Ruoyao <xry111@xry111.site>
94 * config/loongarch/loongarch.md (unspec): Add
95 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
96 (la_pcrel64_two_parts): New define_insn.
97 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
99 (loongarch_call_tls_get_addr): If -mcmodel=extreme
100 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
101 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
102 note to allow CSE addressing __tls_get_addr.
103 (loongarch_legitimize_tls_address): If -mcmodel=extreme
104 -mexplicit-relocs={always,auto}, address TLS IE symbols with
105 la_pcrel64_two_parts.
106 (loongarch_split_symbol): If -mcmodel=extreme
107 -mexplicit-relocs={always,auto}, address symbols with
108 la_pcrel64_two_parts.
109 (loongarch_output_mi_thunk): Clean up unreachable code. If
110 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
111 thunks with la_pcrel64_two_parts.
113 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
115 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
116 Add support for call36.
118 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
120 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
121 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
122 the macro instruction loading symbol address is not applicable.
123 (loongarch_call_tls_get_addr): Adjust code.
124 (loongarch_legitimize_tls_address): Likewise.
126 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
128 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
129 Add function declaration.
130 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
131 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
133 (loongarch_load_tls): Added macro support in extreme mode.
134 (loongarch_call_tls_get_addr): Likewise.
135 (loongarch_legitimize_tls_address): Likewise.
136 (loongarch_force_address): Likewise.
137 (loongarch_legitimize_move): Likewise.
138 (loongarch_output_mi_thunk): Likewise.
139 (loongarch_option_override_internal): Remove the code that detects
140 explicit relocs status.
141 (loongarch_handle_model_attribute): Likewise.
142 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
143 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
144 (symbolic_off64_or_reg_operand): Likewise.
146 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
148 * config/loongarch/loongarch.cc (loongarch_load_tls):
149 Load all types of tls symbols through one function.
150 (loongarch_got_load_tls_gd): Delete.
151 (loongarch_got_load_tls_ld): Delete.
152 (loongarch_got_load_tls_ie): Delete.
153 (loongarch_got_load_tls_le): Delete.
154 (loongarch_call_tls_get_addr): Modify the called function name.
155 (loongarch_legitimize_tls_address): Likewise.
156 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
157 (@load_tls<mode>): New template.
158 (@got_load_tls_ld<mode>): Delete.
159 (@got_load_tls_le<mode>): Delete.
160 (@got_load_tls_ie<mode>): Delete.
162 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
164 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
165 (loongarch_legitimize_address): Add logical transformation code.
167 2024-02-01 Marek Polacek <polacek@redhat.com>
169 * doc/invoke.texi: Update -Wdangling-reference documentation.
171 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
174 * config/i386/i386.md (*cmp<dwi>_doubleword):
175 Do not force SUBREG pieces to pseudos.
177 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
179 * config/pa/pa.md (atomic_storedi_1): Fix bug in
182 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
184 * config/avr/avr.cc: Tabify.
186 2024-02-01 Richard Ball <richard.ball@arm.com>
188 PR tree-optimization/111268
189 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
190 Add variable-length check for vector input arguments
193 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
195 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
196 hard-code number of SGPR/VGPR/AVGPR registers.
197 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
198 SGPR/VGPR/AVGPR registers.
200 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
202 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
203 attribute, and include sifive-p600.md.
204 * config/riscv/generic-ooo.md: Update type attribute.
205 * config/riscv/generic.md: Update type attribute.
206 * config/riscv/sifive-7.md: Update type attribute.
207 * config/riscv/sifive-p600.md: New file.
208 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
209 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
211 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
212 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
213 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
215 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
217 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
218 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
219 * config/riscv/riscv.opt: New macro for 7 new unprivileged
221 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
222 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
224 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
226 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
227 -static-libasan. Add missing whitespace.
229 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
231 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
232 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
233 Don't 'define_constants'.
235 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
237 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
239 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
241 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
242 [TARGET_RDNA3]: Adjust.
244 2024-02-01 Richard Biener <rguenther@suse.de>
246 PR tree-optimization/113693
247 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
250 2024-02-01 Jakub Jelinek <jakub@redhat.com>
251 Jason Merrill <jason@redhat.com>
254 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
255 on variables which were promoted to TREE_STATIC.
257 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
258 Richard Biener <rguenther@suse.de>
261 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
262 information via tree_non_zero_bits to check if this operand
263 is suitably extended for a widening (or highpart) multiplication.
264 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
265 isn't already of the claimed type.
267 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
270 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
272 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
273 (generic_ooo_branch): ditto
274 * config/riscv/generic.md (generic_sfb_alu): ditto
275 (generic_fmul_half): ditto
276 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
277 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
278 (sifive_7_popcount): ditto
279 * config/riscv/vector.md: change rdfrm to fmove
280 * config/riscv/zc.md: change pushpop to load/store
282 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
285 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
286 Robin Dapp <rdapp.gcc@gmail.com>
288 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
289 (generic_ooo_vec_load): ditto
290 (generic_ooo_vec_store): ditto
291 (generic_ooo_vec_loadstore_seg): ditto
292 (generic_ooo_vec_alu): ditto
293 (generic_ooo_vec_fcmp): ditto
294 (generic_ooo_vec_imul): ditto
295 (generic_ooo_vec_fadd): ditto
296 (generic_ooo_vec_fmul): ditto
297 (generic_ooo_crypto): ditto
298 (generic_ooo_perm): ditto
299 (generic_ooo_vec_reduction): ditto
300 (generic_ooo_vec_ordered_reduction): ditto
301 (generic_ooo_vec_idiv): ditto
302 (generic_ooo_vec_float_divsqrt): ditto
303 (generic_ooo_vec_mask): ditto
304 (generic_ooo_vec_vesetvl): ditto
305 (generic_ooo_vec_setrm): ditto
306 (generic_ooo_vec_readlen): ditto
307 * config/riscv/riscv.md: include generic-vector-ooo
308 * config/riscv/generic-vector-ooo.md: New file. to here
310 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
313 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
315 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
317 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
319 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
321 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
322 Robin Dapp <rdapp.gcc@gmail.com>
324 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
325 (generic_ooo_vec_load): ditto
326 (generic_ooo_vec_store): ditto
327 (generic_ooo_vec_loadstore_seg): ditto
328 (generic_ooo_vec_alu): ditto
329 (generic_ooo_vec_fcmp): ditto
330 (generic_ooo_vec_imul): ditto
331 (generic_ooo_vec_fadd): ditto
332 (generic_ooo_vec_fmul): ditto
333 (generic_ooo_crypto): ditto
334 (generic_ooo_perm): ditto
335 (generic_ooo_vec_reduction): ditto
336 (generic_ooo_vec_ordered_reduction): ditto
337 (generic_ooo_vec_idiv): ditto
338 (generic_ooo_vec_float_divsqrt): ditto
339 (generic_ooo_vec_mask): ditto
340 (generic_ooo_vec_vesetvl): ditto
341 (generic_ooo_vec_setrm): ditto
342 (generic_ooo_vec_readlen): ditto
343 * config/riscv/riscv.md: include generic-vector-ooo
344 * config/riscv/generic-vector-ooo.md: New file. to here
346 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
348 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
349 (generic_ooo_branch): ditto
350 * config/riscv/generic.md (generic_sfb_alu): ditto
351 (generic_fmul_half): ditto
352 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
353 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
354 (sifive_7_popcount): ditto
355 * config/riscv/vector.md: change rdfrm to fmove
356 * config/riscv/zc.md: change pushpop to load/store
358 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
361 * config/aarch64/aarch64-simd.md (split for movv8di):
362 For strict aligned mode, use DImode instead of TImode.
364 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
367 * match.pd: Make sure else values match when folding a
368 vec_cond into a conditional operation.
370 2024-01-31 Marek Polacek <polacek@redhat.com>
372 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
374 2024-01-31 Tamar Christina <tamar.christina@arm.com>
375 Matthew Malcomson <matthew.malcomson@arm.com>
378 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
380 * builtins.cc (expand_builtin): Include HWASAN when checking for
383 2024-01-31 Richard Biener <rguenther@suse.de>
386 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
387 to match INTEGER_CST only without outstanding conversion.
389 2024-01-31 Alex Coplan <alex.coplan@arm.com>
392 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
393 V16QImode for the full 16-byte FPR saves in the vector PCS case.
395 2024-01-31 Richard Biener <rguenther@suse.de>
397 PR tree-optimization/111444
398 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
399 vn_reference_lookup_2 when optimistically skipping may-defs.
401 2024-01-31 Richard Biener <rguenther@suse.de>
403 PR tree-optimization/113630
404 * tree-ssa-pre.cc (compute_avail): Avoid registering a
405 reference with a representation with not matching base
408 2024-01-31 Jakub Jelinek <jakub@redhat.com>
410 PR rtl-optimization/113656
411 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
412 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
414 2024-01-31 Jakub Jelinek <jakub@redhat.com>
417 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
418 with BLKmode are larger than DWARF2_ADDR_SIZE.
420 2024-01-31 Jakub Jelinek <jakub@redhat.com>
422 PR tree-optimization/113639
423 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
424 For VIEW_CONVERT_EXPR set rhs1 to its operand.
426 2024-01-31 Richard Biener <rguenther@suse.de>
428 PR tree-optimization/113670
429 * tree-vect-data-refs.cc (vect_check_gather_scatter):
430 Make sure we can take the address of the reference base.
432 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
434 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
435 ATA5835, ATtiny64AUTO, ATA5700M322.
436 * doc/avr-mmcu.texi: Rebuild.
438 2024-01-31 Alexandre Oliva <oliva@adacore.com>
441 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
444 2024-01-31 Alexandre Oliva <oliva@adacore.com>
448 * builtins.cc (expand_builtin_stack_address): Use
449 STACK_ADDRESS_OFFSET.
450 * doc/extend.texi (__builtin_stack_address): Adjust.
451 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
452 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
453 * doc/tm.texi: Rebuilt.
455 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
458 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
459 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
460 (pre_vsetvl::compute_transparent): New function.
461 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
463 2024-01-30 Fangrui Song <maskray@google.com>
466 * config/i386/constraints.md: Define constraint "Ws".
467 * doc/md.texi: Document it.
469 2024-01-30 Marek Polacek <polacek@redhat.com>
473 * doc/invoke.texi: Update -Wdangling-reference description.
475 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
477 * config/xtensa/constraints.md (R, T, U):
478 Change define_constraint to define_memory_constraint.
479 * config/xtensa/predicates.md (move_operand): Don't check that a
480 constant pool operand size is a multiple of UNITS_PER_WORD.
481 * config/xtensa/xtensa.cc
482 (xtensa_lra_p, TARGET_LRA_P): Remove.
483 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
484 clause as it can no longer be true.
485 (fixup_subreg_mem): Drop function.
486 (xtensa_output_integer_literal_parts): Consider 16-bit wide
488 (xtensa_legitimate_constant_p): Add short-circuit path for
489 integer load instructions. Don't check that mode size is
490 at least UNITS_PER_WORD.
491 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
492 rather reload_in_progress and reload_completed.
493 (doloop_end): Drop operand 2.
494 (movhi_internal): Add alternative loading constant from a
496 (define_split for DI register_operand): Don't limit to
497 !TARGET_AUTO_LITPOOLS.
498 * config/xtensa/xtensa.opt (mlra): Change to no effect.
500 2024-01-30 Pan Li <pan2.li@intel.com>
502 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
503 calculate the gpr count required by vls mode.
504 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
505 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
507 (riscv_get_arg_info): Add vls mode handling.
508 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
510 2024-01-30 Richard Biener <rguenther@suse.de>
512 PR tree-optimization/113659
513 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
514 Handle main exit without virtual use.
516 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
518 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
520 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
523 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
524 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
525 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
526 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
527 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
528 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
530 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
533 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
534 Mark all registers that occur in addresses as needing a GPR.
536 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
539 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
540 the containing insn as an extra parameter. Reset debug instructions
541 if they reference a register that is no longer used by real insns.
542 (early_ra::apply_allocation): Update calls accordingly.
544 2024-01-30 Jakub Jelinek <jakub@redhat.com>
546 PR tree-optimization/113603
547 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
548 count_nonzero_bytes call refetch si using get_strinfo in case it
549 has been unshared in the meantime.
551 2024-01-30 Jakub Jelinek <jakub@redhat.com>
554 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
555 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
557 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
559 * config/riscv/thead.cc (th_print_operand_address): Change %ld
562 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
563 Manolis Tsamis <manolis.tsamis@vrull.eu>
564 Philipp Tomsich <philipp.tomsich@vrull.eu>
566 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
567 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
569 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
570 Call on framework moved later.
572 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
574 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
575 instruction in naked function epilogues.
577 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
580 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
581 gcc_cv_as_mips_explicit_relocs.
582 * configure: Regnerated.
584 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
587 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
588 Correct generated RTL.
589 (arm_rev16si2_alt1): Correctly handle conditional execution.
590 (arm_rev16si2_alt2): Likewise.
592 2024-01-29 Richard Biener <rguenther@suse.de>
595 * expr.cc (expand_assignment): Spill hard registers if
596 we index them with a variable offset.
598 2024-01-29 Richard Biener <rguenther@suse.de>
601 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
602 Also allow DECL_HARD_REGISTER variables.
604 2024-01-29 Alex Coplan <alex.coplan@arm.com>
607 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
608 Use iterate_safely when iterating over debug uses.
609 (fixup_debug_uses): Likewise.
610 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
611 over nondebug insns instead of manually maintaining the next insn.
612 * iterator-utils.h (class safe_iterator): New.
613 (iterate_safely): New.
615 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
618 * config/i386/i386-options.cc (ix86_set_func_type): Save
619 callee-saved registers in noreturn functions for -O0/-Og.
621 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
624 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
625 define for !TARGET_RDNA2_PLUS.
627 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
630 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
631 workaround for right shifts.
632 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
633 (vect_determine_precisions_from_range): Be more selective about
634 which codes can be narrowed based on their input and output ranges.
635 For shifts, require at least one more bit of precision than the
636 maximum shift amount.
638 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
640 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
642 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
644 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
645 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
648 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
651 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
652 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
653 (SET_SRAM_ECC_UNSET): ... this.
654 (copy_early_debug_info): Remove gfx900 special case, now handled as
655 part of the generic handling.
656 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
658 2024-01-29 Jakub Jelinek <jakub@redhat.com>
660 PR tree-optimization/110603
661 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
662 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
663 overwritten anyway). Avoid creating invalid range with minlen
664 larger than maxlen. Formatting fix.
666 2024-01-29 Richard Biener <rguenther@suse.de>
669 * tree-inline.cc (initialize_inlined_parameters): Reverse
670 the decl chain of inlined parameters.
672 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
674 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
675 alignment of CFString constants by setting DECL_USER_ALIGN.
677 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
678 Jakub Jelinek <jakub@redhat.com>
681 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
682 and BUILT_IN_GCC_NESTED_PTR_DELETED.
683 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
684 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
685 rename the library fallbacks to __gcc_nested_func_ptr_created and
686 __gcc_nested_func_ptr_deleted.
687 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
688 and __gcc_nested_func_ptr_deleted.
689 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
690 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
691 * tree.cc (build_common_builtin_nodes): Build the
692 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
693 builtins only for non-explicit.
695 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
697 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
699 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
702 * config/i386/i386-options.cc (ix86_set_func_type): Don't
703 save and restore callee saved registers for a noreturn function
704 with nothrow or compiled with -fno-exceptions.
706 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
710 * config/i386/i386-expand.cc (ix86_expand_call): Replace
711 no_caller_saved_registers check with call_saved_registers check.
712 Clobber all registers that are not used by the callee with
713 no_callee_saved_registers attribute.
714 * config/i386/i386-options.cc (ix86_set_func_type): Set
715 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
716 noreturn function. Disallow no_callee_saved_registers with
717 interrupt or no_caller_saved_registers attributes together.
718 (ix86_set_current_function): Replace no_caller_saved_registers
719 check with call_saved_registers check.
720 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
721 (ix86_handle_call_saved_registers_attribute): This.
722 (ix86_gnu_attributes): Add
723 ix86_handle_call_saved_registers_attribute.
724 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
725 no_caller_saved_registers check with call_saved_registers check.
726 (ix86_function_ok_for_sibcall): Don't allow callee with
727 no_callee_saved_registers attribute when the calling function
728 has callee-saved registers.
729 (ix86_comp_type_attributes): Also check
730 no_callee_saved_registers.
731 (ix86_epilogue_uses): Replace no_caller_saved_registers check
732 with call_saved_registers check.
733 (ix86_hard_regno_scratch_ok): Likewise.
734 (ix86_save_reg): Replace no_caller_saved_registers check with
735 call_saved_registers check. Don't save any registers for
736 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
737 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
738 no_callee_saved_registers attribute is called.
739 (find_drap_reg): Replace no_caller_saved_registers check with
740 call_saved_registers check.
741 * config/i386/i386.h (call_saved_registers_type): New enum.
742 (machine_function): Replace no_caller_saved_registers with
743 call_saved_registers.
744 * doc/extend.texi: Document no_callee_saved_registers attribute.
746 2024-01-27 Jakub Jelinek <jakub@redhat.com>
748 PR tree-optimization/113614
749 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
750 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
751 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
753 2024-01-27 Jakub Jelinek <jakub@redhat.com>
755 PR tree-optimization/113568
756 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
757 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
758 in the widening extension checks.
760 2024-01-27 Jakub Jelinek <jakub@redhat.com>
762 * gimple-lower-bitint.cc (gimple_lower_bitint): For
763 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
765 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
767 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
768 the warning for an attribute-always_inline without inline declaration.
770 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
773 * genopinit.cc (main): Split init_all_optabs into functions
774 of 1000 patterns each.
776 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
778 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
780 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
781 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
784 2024-01-26 Andrew Stubbs <ams@baylibre.com>
786 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
787 * config/gcn/gcn-valu.md (all_convert): New iterator.
788 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
789 define_expand, and rename the old one to ...
790 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
791 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
792 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
793 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
794 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
795 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
796 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
797 (<u>mulqihi3_scalar): Likewise.
799 2024-01-26 Richard Biener <rguenther@suse.de>
801 PR tree-optimization/113602
802 * tree-data-ref.cc (dr_analyze_innermost): Fail when
803 the base object isn't addressable.
805 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
807 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
808 "--amdhsa-code-object-version=" argument.
809 (ASM_SPEC): Use it; replace previous version of it.
811 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
813 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
814 (pre_vsetvl::emit_vsetvl): Ditto.
816 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
818 * config/loongarch/lasx.md (vec_extract<mode>_0):
819 New define_insn_and_split patten.
821 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
823 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
825 2024-01-26 Li Wei <liwei@loongson.cn>
827 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
829 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
832 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
834 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
837 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
838 undefined shift after the call to exact_log2.
840 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
843 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
844 before taking the negative of it.
846 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
849 * lra-constraints.cc (curr_insn_transform): Change class even for
850 spilled pseudo successfully matched with with NO_REGS.
852 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
855 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
857 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
860 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
861 (aarch64_expand_epilogue): Use the new function.
862 (aarch64_split_compare_and_swap): Likewise.
863 (aarch64_split_atomic_op): Likewise.
865 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
868 * fold-const.cc (simplify_const_binop): New function for binop
869 simplification of two constant vectors when element-wise
870 handling is not necessary.
871 (const_binop): Call new function.
873 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
875 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
876 * config/riscv/constraints.md: Likewise.
877 * config/riscv/corev.def: Likewise.
878 * config/riscv/corev.md: Likewise.
879 * config/riscv/predicates.md: Likewise.
880 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
881 * config/riscv/riscv-ftypes.def: Likewise.
882 * config/riscv/riscv.opt: Likewise.
883 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
884 * doc/extend.texi: Add XCVbitmanip builtin documentation.
885 * doc/sourcebuild.texi: Likewise.
887 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
889 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
891 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
894 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
895 (riscv_fntype_abi): Ditto.
896 * config/riscv/riscv.opt: Ditto.
898 2024-01-25 Jakub Jelinek <jakub@redhat.com>
901 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
902 count against TYPE_PRECISION rather than TYPE_SIZE.
904 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
907 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
908 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
910 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
913 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
914 whether each split instruction is a load that clobbers the source
915 address. Emit that instruction last if so.
917 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
920 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
922 (<optab><Vnarrowq><mode>2): Use it instead of generating a
923 paradoxical subreg for the input.
925 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
927 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
928 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
929 predecessors dump information.
931 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
933 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
934 redundant full available computation.
935 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
937 2024-01-25 Jakub Jelinek <jakub@redhat.com>
939 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
940 * doc/rtl.texi (CONST_VECTOR): Likewise.
942 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
944 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
945 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
946 (pass_vsetvl::execute): Ditto.
947 * config/riscv/riscv.opt: Ditto.
949 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
951 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
952 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
954 2024-01-25 Richard Biener <rguenther@suse.de>
956 PR tree-optimization/113576
957 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
958 exits with may_be_zero niters when its the last one.
960 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
962 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
963 For symbols of type tls, non-zero Offset is not generated.
965 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
967 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
968 P9 with m32 and mpowerpc64.
970 2024-01-25 liuhongt <hongtao.liu@intel.com>
972 * config/i386/i386-options.cc (ix86_option_override_internal):
973 Enable -mlam=u57 by default when compiled with
974 -fsanitize=hwaddress.
976 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
978 * common/config/riscv/riscv-common.cc (riscv_implied_info):
979 Remove {"ztso", "a"}.
981 2024-01-24 Martin Jambor <mjambor@suse.cz>
985 * cgraph.h (cgraph_edge): Add a parameter to
986 redirect_call_stmt_to_callee.
987 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
988 parameter to modify_call.
989 (ipa_release_ssas_in_hash): Declare.
990 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
991 parameter killed_ssas, pass it to padjs->modify_call.
992 * ipa-param-manipulation.cc (purge_all_uses): New function.
993 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
994 Instead of substituting uses, invoke purge_all_uses. If
995 hash of killed SSAs has not been provided, create a temporary one
996 and release SSAs that have been added to it.
997 (compare_ssa_versions): New function.
998 (ipa_release_ssas_in_hash): Likewise.
999 * tree-inline.cc (redirect_all_calls): Create
1000 id->killed_new_ssa_names earlier, pass it to edge redirection,
1002 (copy_body): Release SSAs in id->killed_new_ssa_names.
1004 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
1007 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
1008 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
1010 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
1013 * config/riscv/sfb.md: New splitters to rewrite single bit
1014 sign extension as the condition to SFB instructions.
1016 2024-01-24 Jan Hubicka <jh@suse.cz>
1019 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
1020 (fmin-function-alignment): New parameter.
1021 * doc/invoke.texi: (-fmin-function-alignment): Document.
1022 (-falign-functions,-falign-loops,-falign-labels): Mention that
1023 aglinments are ignored in cold code.
1024 * varasm.cc (assemble_start_function): Handle min-function-alignment.
1026 2024-01-24 Tamar Christina <tamar.christina@arm.com>
1029 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
1031 * config/aarch64/iterators.md (VQDIV): Remove.
1032 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
1033 SVE_I_SIMD_DI): New.
1034 (VPRED, sve_lane_con): Add V4SI and V2DI.
1035 * config/aarch64/aarch64-sve.md (<optab><mode>3,
1036 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
1037 (mul<mode>3): New, split from <optab><mode>3.
1038 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
1039 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
1040 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
1041 SVE_FULL_HSDI_SIMD_DI.
1043 2024-01-24 Tamar Christina <tamar.christina@arm.com>
1045 PR tree-optimization/113552
1046 * config/aarch64/aarch64.cc
1047 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
1049 2024-01-24 Martin Jambor <mjambor@suse.cz>
1052 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
1053 count is equal or greater than the limit. Use the limit from the
1056 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
1058 * configure.ac: Detect the explicit relocs support for
1059 mips, and define C macro MIPS_EXPLICIT_RELOCS.
1060 * config.in: Regenerated.
1061 * configure: Regenerated.
1062 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
1063 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
1064 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
1065 !TARGET_EXPLICIT_RELOCS instead of just set it.
1066 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
1067 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
1068 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
1069 and define -m(no-)explicit-relocs as aliases.
1071 2024-01-24 Alex Coplan <alex.coplan@arm.com>
1073 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
1075 (-mlate-ldp-fusion): Likewise.
1077 2024-01-24 Tamar Christina <tamar.christina@arm.com>
1079 * tree-vect-loop.cc (vect_get_vect_def,
1080 vect_create_epilog_for_reduction): Rename main_exit_p to
1083 2024-01-24 Tamar Christina <tamar.christina@arm.com>
1085 PR tree-optimization/113364
1086 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
1087 early exits then we must reduce from the first offset for all of them.
1089 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1092 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
1094 (get_bb_index): Ditto.
1095 (pre_vsetvl::compute_avl_def_data): Ditto.
1096 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
1097 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
1099 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
1100 Richard Sandiford <richard.sandiford@arm.com>
1103 * ccmp.cc (ccmp_candidate_p): Add outer argument.
1104 Allow if the outer is true and the lhs is used more
1106 (expand_ccmp_expr): Update call to ccmp_candidate_p.
1107 * expr.h (expand_expr_real_gassign): Declare.
1108 * expr.cc (expand_expr_real_gassign): New function, split out from...
1109 (expand_expr_real_1): ...here.
1110 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
1112 2024-01-23 Alex Coplan <alex.coplan@arm.com>
1115 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
1116 (fixup_debug_use): New.
1117 (fixup_debug_uses_trailing_add): New.
1118 (fixup_debug_uses): New. Use it ...
1119 (ldp_bb_info::fuse_pair): ... here.
1120 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
1121 fix up debug uses of the base register that are affected by
1122 folding in the trailing add insn.
1124 2024-01-23 Alex Coplan <alex.coplan@arm.com>
1127 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
1128 Update trailing nondebug uses of the base register in the case
1129 of cancelling writeback.
1131 2024-01-23 Alex Coplan <alex.coplan@arm.com>
1134 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
1135 (debug_insn_use_iterator): New.
1136 (set_info::first_debug_insn_use): New.
1137 (set_info::debug_insn_uses): New.
1138 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
1139 (set_info::first_debug_insn_use): New.
1140 (set_info::debug_insn_uses): New.
1142 2024-01-23 Alex Coplan <alex.coplan@arm.com>
1145 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
1146 Don't record hazards against the opposite insn in the pair.
1148 2024-01-23 Alex Coplan <alex.coplan@arm.com>
1151 * config/aarch64/aarch64-ldp-fusion.cc
1152 (struct stp_change_builder): New.
1153 (decide_stp_strategy): Reanme to ...
1154 (try_repurpose_store): ... this.
1155 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
1156 construct stp changes. Fix up uses when inserting new stp insns.
1158 2024-01-23 Alex Coplan <alex.coplan@arm.com>
1161 * rtl-ssa.h: Include hash-set.h.
1162 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
1163 new_sets parameter and use it to keep track of new user-created sets.
1164 (function_info::apply_changes_to_insn): Also call add_def on new sets.
1165 (function_info::change_insns): Add hash_set to keep track of new
1166 user-created defs. Plumb it through.
1167 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
1168 apply_changes_to_insn.
1170 2024-01-23 Alex Coplan <alex.coplan@arm.com>
1173 * rtl-ssa/accesses.cc (function_info::create_use): New.
1174 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
1175 Ensure new uses end up referring to permanent defs.
1176 * rtl-ssa/functions.h (function_info::create_use): Declare.
1178 2024-01-23 Alex Coplan <alex.coplan@arm.com>
1181 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
1182 to finalize_new_accesses from the backwards placement loop, run it
1183 forwards in a separate loop.
1185 2024-01-23 Richard Biener <rguenther@suse.de>
1187 PR tree-optimization/113552
1188 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
1189 floor_log2 instead of exact_log2 on the number of calls.
1191 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
1192 Jakub Jelinek <jakub@redhat.com>
1194 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
1197 2024-01-23 Richard Biener <rguenther@suse.de>
1199 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1200 Separate single and multi-exit case when creating PHIs between
1201 the main and epilogue.
1203 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
1206 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
1207 MODE_single variants of functions that don't take tuple arguments.
1209 2024-01-23 Alex Coplan <alex.coplan@arm.com>
1212 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
1213 Don't assert recog success, just punt if the writeback pair
1216 2024-01-23 Jakub Jelinek <jakub@redhat.com>
1218 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
1219 ATTRIBUTE_UNUSED to decl.
1221 2024-01-23 Richard Biener <rguenther@suse.de>
1224 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
1225 handle unexpected but bogus DIE contexts when not checking
1228 2024-01-23 Jakub Jelinek <jakub@redhat.com>
1230 PR tree-optimization/113462
1231 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
1232 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
1233 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
1234 sizes between 129 and 8192 bytes.
1236 2024-01-23 Xi Ruoyao <xry111@xry111.site>
1238 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
1239 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
1240 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
1241 (loongarch_call_tls_get_addr): Do not split symbols of
1242 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
1243 EXPLICIT_RELOCS_AUTO.
1245 2024-01-23 Richard Biener <rguenther@suse.de>
1247 * alias.cc (known_base_value_p): Remove.
1248 (find_base_value): Remove PLUS/MINUS handling
1249 when both operands are not CONST_INT_P.
1251 2024-01-23 Richard Biener <rguenther@suse.de>
1253 PR rtl-optimization/113255
1254 * alias.cc (find_base_term): Remove PLUS/MINUS handling
1255 when both operands are not CONST_INT_P.
1257 2024-01-23 Richard Biener <rguenther@suse.de>
1260 * dwarf2out.cc (dwarf2out_finish): Reset all type units
1261 for the fat part of an LTO compile.
1263 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
1265 * doc/sourcebuild.texi: Add attributes for keywords.
1267 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
1270 * doc/invoke.texi (Warning Options): Correct lists of options
1271 enabled by -Wall and -Wextra by checking against common.opt
1274 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
1277 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
1278 instead of cpu_optaliases.
1279 (check_arch): Use arch_opt_alias instead of arch_optaliases.
1281 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1283 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
1284 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
1285 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
1287 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1290 * config/riscv/riscv.md: Use reg instead of subreg.
1292 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
1295 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
1296 to match the compiler default.
1297 (simple_object_copy_lto_debug_sections): Never unlink the outfile
1298 on error as the caller does so.
1299 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
1300 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
1302 2024-01-22 Richard Biener <rguenther@suse.de>
1304 PR tree-optimization/113373
1305 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1306 Create LC PHIs in the exit blocks where necessary.
1307 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
1308 to handle missing LC PHIs.
1309 (find_connected_edge): Remove.
1310 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
1312 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1314 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
1316 2024-01-22 xuli <xuli1@eswincomputing.com>
1319 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
1320 (registered_function::overloaded_hash):refactor.
1321 (resolve_overloaded_builtin):avoid internal ICE.
1323 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
1327 * calls.cc (emit_library_call_value_1): Pass valid TYPE
1329 * expr.cc (emit_push_insn): Likewise.
1331 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
1333 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
1334 correcction version of last change.
1336 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
1338 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
1339 fix bugs in signature.
1341 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
1342 Richard Biener <rguenther@suse.de>
1344 PR rtl-optimization/111267
1345 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
1346 profitable_p method to likely_profitable_p.
1347 (try_fwprop_subst_node): Update call to likely_profitable_p.
1348 Only bail-out early when !prop.likely_profitable_p for instructions
1349 that are not single sets. When comparing costs, bail-out if the
1350 cost is unchanged and !prop.likely_profitable_p.
1352 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
1355 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
1356 isn't enabled by -Wunused unless -Wextra is provided, and that
1357 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
1358 -Wunused doesn't enable -Wunused-* options documented as behaving
1359 otherwise, and list them explicitly.
1361 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
1364 * doc/invoke.texi (Warning Options): Fix broken example and
1365 clean up/reorganize the others. Also describe what the short-form
1368 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
1371 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
1372 (Warning Options): Correct/edit discussion of -Warray-parameter
1373 to make the first example less confusing, and fill in missing info.
1375 2024-01-20 Jakub Jelinek <jakub@redhat.com>
1377 PR tree-optimization/113462
1378 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
1379 Handle rhs1 INTEGER_CST like SSA_NAME.
1381 2024-01-20 Jakub Jelinek <jakub@redhat.com>
1383 PR tree-optimization/113491
1384 * tree-switch-conversion.cc (switch_conversion::build_constructors):
1385 If elt.index has precision higher than sizetype, fold_convert it to
1387 (switch_conversion::array_value_type): Return type if type is
1388 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
1389 (switch_conversion::build_arrays): Use unsigned_type_for rather than
1390 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
1391 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
1392 higher than sizetype, use sizetype as tidx type and fold_convert the
1393 subtraction to sizetype.
1395 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1397 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
1398 (riscv_vector_mode_supported_any_target_p): Ditto.
1400 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
1403 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
1404 (TARGET_ZERO_CALL_USED_REGS): Define.
1406 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
1409 * config/m68k/m68k.cc (output_andsi3): Use QImode for
1410 address adjusted for 1-byte RMW access.
1411 (output_iorsi3): Likewise.
1412 (output_xorsi3): Likewise.
1414 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1416 * doc/invoke.texi (RISC-V Options): Add list of supported
1419 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1422 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
1423 (RVV_VUNDEF): Ditto.
1424 * config/riscv/riscv-vsetvl.cc: Add timevar.
1426 2024-01-19 Richard Biener <rguenther@suse.de>
1429 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
1430 an early DIE but there should be, do not pretend there is.
1432 2024-01-19 Richard Biener <rguenther@suse.de>
1434 PR tree-optimization/113494
1435 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1436 Handle endless loop on exit. Handle re-allocated PHI.
1438 2024-01-19 Jakub Jelinek <jakub@redhat.com>
1440 PR tree-optimization/113464
1441 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
1442 optimize loads into GIMPLE_ASM stmts.
1444 2024-01-19 Jakub Jelinek <jakub@redhat.com>
1446 PR tree-optimization/113463
1447 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
1448 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
1451 2024-01-19 Jakub Jelinek <jakub@redhat.com>
1453 PR tree-optimization/113459
1454 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
1455 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
1456 of SCALAR_INT_TYPE_MODE if type has BLKmode.
1457 (vn_reference_lookup_3): Likewise. Formatting fix.
1459 2024-01-19 Jakub Jelinek <jakub@redhat.com>
1460 Richard Biener <rguenther@suse.de>
1462 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
1463 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
1464 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
1465 but adjust_address also for BLKmode mode and MEM op0.
1467 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
1469 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
1472 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1474 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
1476 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1478 * common/config/riscv/riscv-common.cc
1479 (riscv_subset_list::parse_std_ext): Remove.
1480 (riscv_subset_list::parse_multiletter_ext): Remove.
1481 * config/riscv/riscv-subset.h
1482 (riscv_subset_list::parse_std_ext): Remove.
1483 (riscv_subset_list::parse_multiletter_ext): Remove.
1485 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1487 * common/config/riscv/riscv-common.cc
1488 (riscv_subset_list::parse_single_std_ext): New parameter.
1489 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
1490 (riscv_subset_list::parse_single_ext): Ditto.
1491 (riscv_subset_list::parse): Relax the order for the input of ISA
1493 * config/riscv/riscv-subset.h
1494 (riscv_subset_list::parse_single_std_ext): New parameter.
1495 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
1496 (riscv_subset_list::parse_single_ext): Ditto.
1498 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1500 * common/config/riscv/riscv-common.cc
1501 (riscv_subset_list::parse_base_ext): New.
1502 (riscv_subset_list::parse): Extract part of logic into
1503 riscv_subset_list::parse_base_ext.
1504 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
1507 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
1509 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
1512 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
1514 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
1517 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
1520 * doc/extend.texi (Common Variable Attributes): Explain what
1521 happens when multiple variables with cleanups are in the same scope.
1523 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
1526 * doc/extend.texi (Common Function Attributes): Document that
1527 noinline also disables some interprocedural optimizations and
1528 improve flow to the part about using inline asm instead to
1529 disable calls from being optimized away completely. Remove the
1530 sentence that says noipa is mainly for internal compiler testing.
1532 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
1534 PR tree-optimization/69807
1535 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
1537 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
1540 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
1541 from x86 Windows Options.
1543 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
1546 * doc/extend.texi (C Extensions): Add new section to menu.
1547 (Function Attributes): Move dangling index entries to....
1548 (Const and Volatile Functions): New section.
1550 2024-01-18 David Malcolm <dmalcolm@redhat.com>
1552 PR middle-end/112684
1553 * toplev.cc (toplev::main): Don't ICE in
1554 -fdiagnostics-generate-patch when exiting after options,
1555 since no edit context will have been created.
1557 2024-01-18 Richard Biener <rguenther@suse.de>
1559 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
1562 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1564 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
1565 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
1567 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1568 Jin Ma <jinma@linux.alibaba.com>
1569 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1570 Christoph Müllner <christoph.muellner@vrull.eu>
1572 * config/riscv/thead.cc
1573 (th_asm_output_opcode): Rewrite some instructions.
1575 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1576 Jin Ma <jinma@linux.alibaba.com>
1577 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1578 Christoph Müllner <christoph.muellner@vrull.eu>
1580 * config/riscv/riscv.md (none,thv,rvv): New attribute.
1581 (no,yes): Add an attribute to disable alternative
1582 for xtheadvector or RVV1.0.
1583 * config/riscv/vector.md:
1584 Disable alternatives that destination register overlaps
1585 source register group for xtheadvector.
1587 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1588 Jin Ma <jinma@linux.alibaba.com>
1589 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1590 Christoph Müllner <christoph.muellner@vrull.eu>
1592 * config/riscv/riscv-vector-builtins-bases.cc
1593 (class th_loadstore_width): Define new builtin bases.
1594 (class th_extract): Define new builtin bases.
1595 (BASE): Define new builtin bases.
1596 * config/riscv/riscv-vector-builtins-bases.h:
1597 Define new builtin class.
1598 * config/riscv/riscv-vector-builtins-shapes.cc
1599 (struct th_loadstore_width_def): Define new builtin shapes.
1600 (struct th_indexed_loadstore_width_def):
1601 Define new builtin shapes.
1602 (struct th_extract_def): Define new builtin shapes.
1603 (SHAPE): Define new builtin shapes.
1604 * config/riscv/riscv-vector-builtins-shapes.h:
1605 Define new builtin shapes.
1606 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
1607 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
1608 * config/riscv/riscv-vector-builtins.h
1609 (enum required_ext): Add new XTheadVector member.
1610 (struct function_group_info): Likewise.
1611 * config/riscv/t-riscv:
1612 Add thead-vector-builtins-functions.def
1613 * config/riscv/thead-vector.md
1614 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
1615 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
1616 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
1617 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
1618 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
1619 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
1620 (@pred_th_extract<mode>): Likewise.
1621 (*pred_th_extract<mode>): Likewise.
1622 * config/riscv/thead-vector-builtins-functions.def: New file.
1624 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1625 Jin Ma <jinma@linux.alibaba.com>
1626 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1627 Christoph Müllner <christoph.muellner@vrull.eu>
1629 * config.gcc: Add files for XTheadVector intrinsics.
1630 * config/riscv/autovec.md: Guard XTheadVector.
1631 * config/riscv/predicates.md: Disable immediate vl
1633 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
1634 Add pragma for XTheadVector.
1635 * config/riscv/riscv-string.cc (riscv_expand_block_move):
1637 * config/riscv/riscv-v.cc (vls_mode_valid_p):
1639 * config/riscv/riscv-vector-builtins-bases.cc:
1640 Do not normalize vsetvl instructions for XTheadVector.
1641 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
1642 New check type function.
1643 (build_one): Adjust for XTheadVector.
1644 * config/riscv/riscv-vector-switch.def (ENTRY):
1645 Disable fractional mode for the XTheadVector extension.
1646 (TUPLE_ENTRY): Likewise.
1647 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
1649 (riscv_preferred_simd_mode): Likewsie.
1650 (riscv_autovectorize_vector_modes): Likewise.
1651 (riscv_vector_mode_supported_any_target_p): Likewise.
1652 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
1653 * config/riscv/thead.cc (th_asm_output_opcode):
1654 Rewrite vsetvl instructions.
1655 * config/riscv/vector.md:
1656 Include thead-vector.md and change fractional LMUL
1658 * config/riscv/riscv_th_vector.h: New file.
1659 * config/riscv/thead-vector.md: New file.
1661 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1662 Jin Ma <jinma@linux.alibaba.com>
1663 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1664 Christoph Müllner <christoph.muellner@vrull.eu>
1666 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
1667 Add new function to add assembler insn code prefix/suffix.
1668 (th_asm_output_opcode):
1669 Add Thead function to add assembler insn code prefix/suffix.
1670 * config/riscv/riscv.cc (riscv_asm_output_opcode):
1671 Implement function to add assembler insn code prefix/suffix.
1672 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
1673 Add new function to add assembler insn code prefix/suffix.
1674 * config/riscv/thead.cc (th_asm_output_opcode):
1675 Implement Thead function to add assembler insn code
1678 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
1679 Jin Ma <jinma@linux.alibaba.com>
1680 Xianmiao Qu <cooper.qu@linux.alibaba.com>
1681 Christoph Müllner <christoph.muellner@vrull.eu>
1683 * common/config/riscv/riscv-common.cc
1684 (riscv_subset_list::parse): Add new vendor extension.
1685 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
1687 * config/riscv/riscv.opt: Add new mask.
1689 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1691 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
1692 to be conditional on macosx-version-min.
1694 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1696 * config/darwin.cc (darwin_objc1_section): Use the correct
1697 meta-data version for constant strings.
1698 (machopic_select_section): Assert if we fail to handle CFString
1699 sections as Obejctive-C meta-data or drectly.
1701 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1703 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
1704 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
1705 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
1706 versions when the object format is Mach-O.
1708 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
1711 * config/darwin.cc (machopic_select_section): Handle C and C++
1713 (darwin_rename_builtins): Move this out of the CFString code.
1714 (darwin_libc_has_function): Likewise.
1715 (darwin_build_constant_cfstring): Create an anonymous var to
1717 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
1720 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
1723 * haifa-sched.cc (dep_list_size): Make global.
1724 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
1725 * sched-int.h (dep_list_size): Declare.
1727 2024-01-18 Martin Jambor <mjambor@suse.cz>
1729 PR tree-optimization/110422
1730 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
1733 2024-01-18 Richard Biener <rguenther@suse.de>
1735 PR tree-optimization/113475
1736 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
1737 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
1738 (phi_analyzer::~phi_analyzer): Deallocate and free collected
1740 (phi_analyzer::process_phi): Record allocated phi_groups.
1742 2024-01-18 Richard Biener <rguenther@suse.de>
1744 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
1745 storage for gvec_oprnds elements.
1747 2024-01-18 Richard Biener <rguenther@suse.de>
1749 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
1750 prefer all later exits we can handle.
1751 (vect_analyze_loop_form): Free the allocated loop body.
1754 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1756 * config/avr/avr-log.cc: Tabify.
1758 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1760 * config/riscv/autovec.md: Support vi variant.
1762 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1764 * config/avr/avr-devices.cc: Tabify.
1766 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1768 * config/avr/avr-c.cc: Tabify.
1770 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1772 * config/avr/driver-avr.cc: Tabify.
1774 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1776 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
1778 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1780 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
1782 2024-01-18 Jakub Jelinek <jakub@redhat.com>
1784 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
1785 minline-strcmp, minline-strncmp, minline-strlen,
1786 -param=riscv-vector-abi): Remove Bool keywords.
1788 2024-01-18 Jakub Jelinek <jakub@redhat.com>
1791 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
1792 support. Add missing space after , in emitted assembly in some
1793 cases. Formatting fixes.
1795 2024-01-18 Xi Ruoyao <xry111@xry111.site>
1797 * config/loongarch/loongarch.md (movsi_internal): Remove
1800 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
1802 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
1803 in the diagnostic, and capitalize the device name.
1804 (print_mcu): Generate specs such that:
1805 <*check_rodata_in_ram>: New.
1806 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
1807 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
1808 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
1810 2024-01-18 Jakub Jelinek <jakub@redhat.com>
1813 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
1814 Common and Optimization.
1816 2024-01-18 Richard Biener <rguenther@suse.de>
1818 PR tree-optimization/113431
1819 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
1820 When there is an invariant load we might not preserve
1823 2024-01-18 Richard Biener <rguenther@suse.de>
1825 PR tree-optimization/113374
1826 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
1827 * tree-vect-loop.cc (move_early_exit_stmts): Update
1829 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1830 Refactor. Preserve virtual LC PHIs on all exits.
1832 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
1834 * config/loongarch/loongarch.cc (loongarch_split_symbol):
1835 Assign the '/u' attribute to the mem.
1837 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
1839 PR middle-end/110847
1840 * doc/invoke.texi (Option Summary): Document negative forms of
1841 -Wtsan and -Wxor-used-as-pow.
1842 (Warning Options): Likewise.
1844 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1847 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
1849 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
1851 * doc/extend.texi (Common Function Attributes): Re-alphabetize
1853 (Common Variable Attributes): Likewise.
1854 (Common Type Attributes): Likewise.
1856 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
1858 PR middle-end/111659
1859 * doc/extend.texi (Common Variable Attributes): Fix long lines
1860 in documentation of strict_flex_array + other minor copy-editing.
1861 Add a cross-reference to -Wstrict-flex-arrays.
1862 * doc/invoke.texi (Option Summary): Fix whitespace in tables
1863 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
1864 (C Dialect Options): Combine the docs for the two
1865 -fstrict-flex-arrays forms into a single entry. Note this option
1866 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
1867 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
1868 Minor copy-editing. Add cross references to the strict_flex_array
1869 attribute and -fstrict-flex-arrays option. Add note that this
1870 option depends on -ftree-vrp.
1872 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
1875 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
1876 only allow REG operands instead of allowing all.
1878 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
1880 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
1881 Remove redundant checks in else condition for readablity.
1882 (earliest_fuse_vsetvl_info) Print iteration count in debug
1884 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
1885 dump details in certain cases.
1887 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
1889 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
1890 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
1891 * config/riscv/riscv-vsetvl.cc
1892 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
1893 (pass_vsetvl::execute): Use vsetvl_strategy.
1895 2024-01-17 Jan Hubicka <jh@suse.cz>
1897 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
1898 accidental hack reseting offset.
1900 2024-01-17 Jan Hubicka <jh@suse.cz>
1902 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
1903 handling of X86_TUNE_AVOID_512FMA_CHAINS.
1905 2024-01-17 Jan Hubicka <jh@suse.cz>
1906 Jakub Jelinek <jakub@redhat.com>
1908 PR tree-optimization/110852
1909 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
1911 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
1912 PRED_COMBINED_VALUE_PREDICTIONS_PHI
1913 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
1914 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
1916 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1918 PR tree-optimization/113421
1919 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
1921 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
1922 formatting. Start at vop rather than cvop even if stmt is a store
1923 and needs_operand_addr.
1925 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1927 PR middle-end/113410
1928 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
1929 If access_nelts is integral with larger precision than sizetype,
1930 fold_convert it to sizetype.
1932 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1934 PR tree-optimization/113408
1935 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
1936 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
1939 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1941 PR middle-end/113406
1942 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
1943 regardless of whether is_gimple_reg_type (restype) or not.
1945 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1947 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
1948 funcions -> functions, and use were instead of was.
1949 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
1950 and guaranteee -> guarantee.
1951 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
1953 2024-01-17 Jakub Jelinek <jakub@redhat.com>
1955 PR middle-end/113409
1956 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
1958 (omp_extract_for_data): Use build_bitint_type rather than
1959 build_nonstandard_integer_type if either iter_type or loop->v type
1961 * omp-expand.cc (expand_omp_for_generic,
1962 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
1963 BITINT_TYPE like INTEGER_TYPE.
1965 2024-01-17 Richard Biener <rguenther@suse.de>
1967 PR tree-optimization/113371
1968 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
1969 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
1970 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
1971 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
1973 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
1975 PR rtl-optimization/96388
1976 PR rtl-optimization/111554
1977 * sched-deps.cc (find_inc): Avoid exponential behavior.
1979 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
1982 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
1983 from C++ Language Options to Warning Options. Add entry for
1985 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
1987 (Warning Options): ...to here. Minor copy-editing to fix typo
1990 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
1992 * config/mips/mips.cc (mips_compute_frame_info): If another
1993 register is used as global_pointer, mark $GP live false.
1995 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
1998 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
1999 give the section a light copy-editing pass.
2001 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
2003 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
2004 * config/aarch64/aarch64-tune.md: Regenerated.
2005 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
2007 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
2010 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
2011 badly formed CONST expressions.
2013 2024-01-16 Daniel Cederman <cederman@gaisler.com>
2015 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
2017 2024-01-16 Daniel Cederman <cederman@gaisler.com>
2019 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
2020 * config/sparc/sync.md (membar_storeload): Turn into named insn
2021 and add GR712RC errata workaround.
2022 (membar_v8): Add GR712RC errata workaround.
2024 2024-01-16 Andreas Larsson <andreas@gaisler.com>
2026 * config/sparc/sync.md (*membar_storeload_leon3): Remove
2027 (*membar_storeload): Enable for LEON
2029 2024-01-16 Jakub Jelinek <jakub@redhat.com>
2031 PR tree-optimization/113372
2033 PR middle-end/110115
2034 PR middle-end/111422
2035 * cfgexpand.cc (add_scope_conflicts_2): New function.
2036 (add_scope_conflicts_1): Use it.
2038 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
2040 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
2041 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
2042 * doc/avr-mmcu.texi: Regenerate.
2044 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
2046 PR tree-optimization/113091
2047 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
2048 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
2049 scalar use with new function.
2050 (vect_bb_slp_mark_live_stmts): New function as entry to existing
2051 overriden functions with same name.
2052 (vect_slp_analyze_operations): Call new entry function to mark
2055 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2058 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
2059 for RVV in big-endian mode.
2061 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
2063 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
2064 (riscv_pass_in_vector_p): Delete.
2065 (riscv_init_cumulative_args): Delete the checking.
2066 (riscv_get_arg_info): Delete the checking.
2067 (riscv_function_value): Delete the checking.
2068 * config/riscv/riscv.h: Delete the member for checking.
2070 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
2072 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
2074 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
2076 * config.gcc: Include riscv_bitmanip.h.
2077 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
2078 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
2079 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
2080 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
2081 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
2082 * config/riscv/riscv-ftypes.def (2): New ftypes.
2083 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
2084 (RISCV_BUILTIN_NO_PREFIX): Likewise.
2085 * config/riscv/riscv_bitmanip.h: New file.
2087 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
2089 * config.gcc: Include riscv_crypto.h.
2090 * config/riscv/riscv_crypto.h: New file.
2092 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
2094 PR middle-end/113354
2095 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
2096 in the insn if the corresponding operand does not require hard
2099 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
2102 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
2103 * config/avr/driver-avr.cc (avr_no_devlib): New function.
2104 (avr_devicespecs_file): Use it to remove -nodevicelib from the
2105 options for cores only.
2106 * config/avr/avr-arch.h (avr_get_parch): New prototype.
2107 * config/avr/avr-devices.cc (avr_get_parch): New function.
2109 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2112 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
2113 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
2114 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
2116 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2119 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
2120 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
2121 * config/riscv/riscv-vector-costs.h: New function.
2123 2024-01-15 Richard Biener <rguenther@suse.de>
2125 PR tree-optimization/113385
2126 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2127 First redirect, then split the exit edge.
2129 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2131 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
2132 Remove m_num_vector_iterations.
2133 * config/riscv/riscv-vector-costs.h: Ditto.
2135 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
2138 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
2139 (-mbranch-cost): Set "Optimization" flag.
2141 2024-01-15 Jakub Jelinek <jakub@redhat.com>
2143 PR tree-optimization/113370
2144 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
2145 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
2146 set it to just prec % limb_prec.
2148 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2151 * config/riscv/vector.md: Fix ternary attributes.
2153 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
2156 * configure.ac [target=avr]: Check availability of emulations
2157 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
2158 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
2159 * configure: Regenerate.
2160 * config.in: Regenerate.
2161 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
2162 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
2163 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
2164 * config/avr/avr-arch.h (enum avr_device_specific_features):
2166 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
2168 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
2169 (avr_set_core_architecture): Set avr_arch_index.
2170 (have_avrxmega2_flmap, have_avrxmega4_flmap)
2171 (have_avrxmega3_rodata_in_flash): Set new static const bool according
2172 to configure results.
2173 (avr_rodata_in_flash_p): New function using them.
2174 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
2175 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
2176 (avr_asm_named_section): Track avr_has_rodata_p.
2177 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
2178 and not avr_rodata_in_flash_p ().
2179 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
2180 (LINK_SPEC): Add %(link_rodata_in_ram).
2181 (LINK_ARCH_SPEC): Remove.
2182 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
2183 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
2184 const bool according to configure results.
2185 (diagnose_mrodata_in_ram): New function.
2186 (print_mcu): Generate specs with the following changes:
2187 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
2188 need to extend avr/specs.h each time we add a new bell or whistle.
2189 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
2190 -m[no-]rodata-in-ram.
2191 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
2192 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
2193 <*cpp>: Add %(cpp_rodata_in_ram).
2194 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
2196 <*self_spec>: Add -mflmap or %<mflmap as needed.
2198 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
2200 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
2201 not the GPR iterator. Adjust pattern name and mode attribute
2204 2024-01-13 Jakub Jelinek <jakub@redhat.com>
2206 PR tree-optimization/113361
2207 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
2208 Fix up determination of the type for > limb_prec constants.
2210 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
2212 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
2213 Add web-link to the avr-gcc wiki.
2215 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
2217 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
2218 documentation for a version without argument, which is not supported.
2220 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2222 * config/arm/arm_neon.h
2223 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
2224 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
2225 (vld1_f16_x4, vld1_f32_x4): New.
2226 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
2227 (vld1_bf16_x4): New.
2228 (vld1q_types_x4): Updated to use vld1q_x4
2229 from arm_neon_builtins.def
2230 * config/arm/arm_neon_builtins.def
2231 (vld1_x4): Updated entries.
2232 (vld1q_x4): New entries, but comes from the old vld1_x4
2233 * config/arm/neon.md
2234 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
2236 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2238 * config/arm/arm_neon.h
2239 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
2240 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
2241 (vld1_f16_x3, vld1_f32_x3): New.
2242 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
2243 (vld1_bf16_x3): New.
2244 (vld1q_types_x3): Updated to use vld1q_x3 from
2245 arm_neon_builtins.def
2246 * config/arm/arm_neon_builtins.def
2247 (vld1_x3): Updated entries.
2248 (vld1q_x3): New entries, but comes from the old vld1_x2
2249 * config/arm/neon.md
2250 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
2252 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2254 * config/arm/arm_neon.h
2255 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
2256 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
2257 (vld1_f16_x2, vld1_f32_x2): New.
2258 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
2259 (vld1_bf16_x2): New.
2260 (vld1q_types_x2): Updated to use vld1q_x2 from
2261 arm_neon_builtins.def
2262 * config/arm/arm_neon_builtins.def
2263 (vld1_x2): Updated entries.
2264 (vld1q_x2): New entries, but comes from the old vld1_x2
2265 * config/arm/neon.md
2266 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
2269 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2271 * config/arm/arm_neon.h
2272 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
2273 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
2274 (vst1q_f16_x4, vst1q_f32_x4): New.
2275 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
2276 (vst1q_bf16_x4): New.
2277 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
2278 * config/arm/neon.md
2279 (neon_vst1q_x4<mode>): New.
2280 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
2281 * config/arm/unspecs.md
2282 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
2284 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2286 * config/arm/arm_neon.h
2287 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
2288 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
2289 (vst1q_f16_x3, vst1q_f32_x3): New.
2290 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
2291 (vst1q_bf16_x3): New.
2292 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
2293 * config/arm/neon.md
2294 (neon_vst1q_x3<mode>): New.
2295 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
2296 * config/arm/unspecs.md
2297 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
2299 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2301 * config/arm/arm_neon.h
2302 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
2303 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
2304 (vst1q_f16_x2, vst1q_f32_x2): New.
2305 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
2306 (vst1q_bf16_x2): New.
2307 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
2308 * config/arm/neon.md
2309 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
2311 * config/arm/iterators.md
2312 (VMEMX2): New mode iterator.
2313 (VMEMX2_q): New mode attribute.
2315 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2317 * config/arm/arm_neon.h
2318 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
2319 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
2320 (vst1_f16_x4, vst1_f32_x4): New.
2321 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
2322 (vst1_bf16_x4): New.
2323 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
2324 * config/arm/neon.md (vst1_x4<mode>): New.
2326 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2328 * config/arm/arm_neon.h
2329 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
2330 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
2331 (vst1_f16_x3, vst1_f32_x3): New.
2332 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
2333 (vst1_bf16_x3): New.
2334 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
2335 * config/arm/neon.md (vst1_x3<mode>): New.
2337 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2339 * config/arm/arm_neon.h
2340 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
2341 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
2342 (vst1_f16_x2, vst1_f32_x2): New.
2343 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
2344 (vst1_bf16_x2): New.
2345 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
2346 * config/arm/neon.md (vst1_x2<mode>): New.
2348 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2350 * config/arm/arm_neon.h
2351 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
2352 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
2353 (vld1q_f16_x4, vld1q_f32_x4): New.
2354 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
2355 (vld1q_bf16_x4): New.
2356 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
2357 * config/arm/neon.md
2358 (neon_vld1_x4<mode>): New.
2359 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
2360 * config/arm/unspecs.md
2361 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
2363 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2365 * config/arm/arm_neon.h
2366 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
2367 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
2368 (vld1q_f16_x3, vld1q_f32_x3): New.
2369 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
2370 (vld1q_bf16_x3): New.
2371 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
2372 * config/arm/neon.md
2373 (neon_vld1_x3<mode>): New.
2374 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
2375 * config/arm/unspecs.md
2376 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
2378 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
2380 * config/arm/arm_neon.h
2381 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
2382 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
2383 (vld1q_f16_x2, vld1q_f32_x2): New.
2384 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
2385 (vld1q_bf16_x2): New.
2386 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
2387 * config/arm/neon.md (vld1_x2<mode>): New.
2389 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2391 PR tree-optimization/113287
2392 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
2394 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2396 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
2397 * tree-vect-loop.cc (vect_transform_loop): Likewise.
2399 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2401 PR tree-optimization/113178
2402 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
2405 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2407 PR tree-optimization/113237
2408 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
2409 existing LCSSA variable for exit when all exits are early break.
2411 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2413 PR tree-optimization/113137
2414 PR tree-optimization/113136
2415 PR tree-optimization/113172
2416 PR tree-optimization/113178
2417 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2418 Maintain PHIs on inverted loops.
2419 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
2420 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
2422 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
2424 2024-01-12 Tamar Christina <tamar.christina@arm.com>
2426 PR tree-optimization/113135
2427 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
2428 dependency analysis.
2430 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
2432 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
2433 diagnostics class member name for abort of error.
2435 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
2437 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
2438 format string to %s argument.
2440 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
2441 Jakub Jelinek <jakub@redhat.com>
2443 PR middle-end/113182
2444 * varasm.cc (process_pending_assemble_externals,
2445 assemble_external_libcall): Use targetm.strip_name_encoding
2446 before calling get_identifier.
2448 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
2451 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
2452 New member variable.
2453 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
2455 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
2456 * config/aarch64/aarch64-simd.md
2457 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
2458 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
2459 zip2 for zero-extends to...
2460 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
2461 instruction. Fix big-endian handling.
2462 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
2463 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
2464 zip1 for zero-extends to...
2465 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
2466 Fix big-endian handling.
2467 (*aarch64_zip1_uxtl): New pattern.
2468 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
2469 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
2470 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
2471 (aarch64_gen_shareable_zero): Use it.
2472 (aarch64_split_simd_shift_p): New function.
2474 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
2476 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
2477 (function_beg_insn): New macro.
2478 * function.cc (expand_function_start): Initialize function_beg_insn.
2480 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
2483 * config/aarch64/aarch64-sve-builtins.h
2484 (function_builder::m_overload_names): Replace with...
2485 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
2487 (add_overloaded_function): Update accordingly, using get_identifier
2488 to get a GGC-friendly record of the name.
2490 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
2493 * config/aarch64/aarch64-sve-builtins.def: Don't include
2494 aarch64-sve-builtins-sme.def.
2495 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
2496 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
2497 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
2498 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
2499 requires AARCH64_FL_SME2.
2500 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
2501 AARCH64_FL_SME adjustment here.
2502 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
2503 include SME intrinsics.
2504 (sme_function_groups): New array.
2505 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
2506 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
2508 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2511 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
2512 (struct cpu_vector_cost): Add regmove struct.
2513 (get_vector_costs): Export as global.
2514 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
2515 (costs::add_stmt_cost): Ditto.
2516 * config/riscv/riscv.cc (get_common_costs): Export global function.
2518 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2520 PR tree-optimization/113334
2521 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
2522 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
2523 to determine if number should be extended by all ones rather than zero
2526 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2528 PR tree-optimization/113330
2529 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
2532 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2534 PR tree-optimization/113323
2535 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
2536 check for lhs being large/huge _BitInt not in m_names.
2538 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2540 PR tree-optimization/113316
2541 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
2542 uninitialized large/huge _BitInt arguments to calls.
2544 2024-01-12 Jakub Jelinek <jakub@redhat.com>
2546 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
2547 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
2548 CEIL (TYPE_PRECISION (t), limb_prec).
2549 (bitint_large_huge::handle_cast): Likewise.
2551 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
2554 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
2555 Use assemble_function_label_final () for Power ELF V1 ABI.
2556 * output.h (assemble_function_label_final): New function.
2557 * varasm.cc (assemble_function_label_raw): Use
2558 assemble_function_label_final ().
2559 (assemble_function_label_final): New function.
2561 2024-01-12 Richard Biener <rguenther@suse.de>
2563 PR middle-end/113344
2564 * match.pd ((double)float CMP (double)float -> float CMP float):
2565 Perform result type check only for vectors.
2566 * fold-const.cc (fold_binary_loc): Likewise.
2568 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
2570 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
2571 (usdot_prod<mode>): Ditto.
2572 (sdot_prod<mode>): Ditto.
2573 (udot_prod<mode>): Ditto.
2575 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
2578 * config/i386/i386-c.cc (ix86_target_macros_internal):
2579 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
2581 2024-01-12 Richard Biener <rguenther@suse.de>
2584 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
2585 Do not generate code when d.testing_p.
2587 2024-01-12 liuhongt <hongtao.liu@intel.com>
2590 * doc/invoke.texi (fcf-protection=): Update documents.
2592 2024-01-12 Pan Li <pan2.li@intel.com>
2594 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
2595 comments of predicate func riscv_v_ext_mode_p.
2597 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
2599 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
2600 Modify ABI-name length of vfloat16m8_t
2602 2024-01-12 Li Wei <liwei@loongson.cn>
2604 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
2607 2024-01-12 Li Wei <liwei@loongson.cn>
2609 * config/loongarch/loongarch.md (add<mode>3): Removed.
2613 (*addsi3_extended): Removed.
2614 (addsi3_extended): New.
2616 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
2618 * config/riscv/thead.md: Add limits for splits.
2620 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
2622 PR middle-end/113322
2623 * expr.cc (do_store_flag): Don't try single bit tests with
2624 comparison on vector types.
2626 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
2628 PR tree-optimization/113301
2629 * match.pd (`1/x`): Delay signed case until late.
2631 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
2633 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
2635 (AVR Internal Options): ...this new @subsubsection.
2637 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
2639 PR rtl-optimization/112918
2640 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
2641 (in_class_p): Restrict condition for narrowing class in case of
2642 allow_all_reload_class_changes_p.
2643 (process_alt_operands): Try to match operand without and with
2644 narrowing reg class. Discourage narrowing the class. Finish insn
2645 matching only if there is no class narrowing.
2646 (curr_insn_transform): Pass true to in_class_p for reg operand win.
2648 2024-01-11 Richard Biener <rguenther@suse.de>
2650 PR tree-optimization/112505
2651 * tree-vect-loop.cc (vectorizable_induction): Reject
2652 bit-precision induction.
2654 2024-01-11 Richard Biener <rguenther@suse.de>
2656 PR tree-optimization/113126
2657 * match.pd ((double)float CMP (double)float -> float CMP float):
2658 Make sure the boolean type is the same.
2659 * fold-const.cc (fold_binary_loc): Likewise.
2661 2024-01-11 Richard Biener <rguenther@suse.de>
2663 PR tree-optimization/112636
2664 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
2665 estimate_numbers_of_iterations before querying
2666 get_max_loop_iterations_int.
2667 (pass_ch::execute): Initialize SCEV and loops appropriately.
2669 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
2671 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
2673 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
2674 * doc/extend.texi (AVR Variable Attributes): Improve documentation
2675 of io, io_low and address attributes.
2676 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
2677 * doc/avr-mmcu.texi: Rebuild.
2679 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
2682 * config/loongarch/genopts/loongarch.opt.in: Mark options with
2683 the "Save" property.
2684 * config/loongarch/loongarch.opt: Same.
2685 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
2686 according to la_target.
2687 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
2688 RESTORE} for the la_target structure; Rename option conditions
2689 to have the same "la_" prefix.
2690 * config/loongarch/loongarch.h: Same.
2692 2024-01-11 Pan Li <pan2.li@intel.com>
2694 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
2695 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
2697 2024-01-11 Alex Coplan <alex.coplan@arm.com>
2700 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
2701 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
2702 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
2703 synthesize these if needed. Update caller ...
2704 (ldp_bb_info::fuse_pair): ... here.
2705 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
2706 and either insn is frame-related.
2707 (find_trailing_add): Punt on frame-related insns.
2708 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
2709 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
2711 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
2713 * config/mips/mips.cc (mips_start_function_definition):
2714 Add ATTRIBUTE_UNUSED.
2716 2024-01-11 Richard Biener <rguenther@suse.de>
2718 PR middle-end/112740
2719 * expr.cc (store_constructor): Check the integer vector
2720 mask has a single bit per element before using sign-extension
2721 to expand an uniform vector.
2723 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2725 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
2726 preempt VLS on unknown NITERS loop.
2728 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
2730 * doc/invoke.texi: Add -mevex512.
2732 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
2734 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
2735 (*nor<mode>3): Likewise.
2736 (nor<mode>3): Likewise.
2737 (*negsi2_extended): New template.
2738 (*<optab>si3_internal): Likewise.
2739 (*one_cmplsi2_internal): Likewise.
2740 (*norsi3_internal): Likewise.
2741 (*<optab>nsi_internal): Likewise.
2742 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
2743 modified bit operation to make the optimization work.
2745 2024-01-11 liuhongt <hongtao.liu@intel.com>
2748 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
2750 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2752 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
2753 (get_vector_costs): Ditto.
2754 (riscv_builtin_vectorization_cost): Ditto.
2756 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2758 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
2760 2024-01-10 Antoni Boucher <bouanto@zoho.com>
2763 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
2764 ipa_free_size_summary.
2765 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
2766 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
2767 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
2768 * ipa-prop.h (ipa_prop_cc_finalize): New function.
2769 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
2770 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
2771 ipa_sra_cc_finalize): New functions.
2772 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
2773 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
2775 Include ipa-utils.h.
2777 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
2779 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
2780 (th_int_get_save_adjustment): Likewise.
2781 (th_int_adjust_cfi_prologue): Likewise.
2782 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
2783 (TH_INT_INTERRUPT): New macro.
2784 (riscv_expand_prologue): Add the processing of XTheadInt.
2785 (riscv_expand_epilogue): Likewise.
2786 * config/riscv/riscv.h (BITSET_P): Moved to here.
2787 * config/riscv/riscv.md: New unspec.
2788 * config/riscv/thead.cc (th_int_get_mask): New function.
2789 (th_int_get_save_adjustment): Likewise.
2790 (th_int_adjust_cfi_prologue): Likewise.
2791 * config/riscv/thead.md (th_int_push): New pattern.
2792 (th_int_pop): new pattern.
2794 2024-01-10 Tamar Christina <tamar.christina@arm.com>
2796 PR tree-optimization/112468
2797 * doc/sourcebuild.texi: Document ifn_copysign.
2798 * match.pd: Only apply transformation if target supports the IFN.
2800 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
2802 PR tree-optimization/112581
2803 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
2804 mark_ssa_maybe_undefs.
2805 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
2806 variables can not be reassociated.
2807 (init_range_entry): Check for uninitialized variables too.
2808 (init_reassoc): Call mark_ssa_maybe_undefs.
2810 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
2812 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
2813 Also handle sign extension.
2815 2024-01-10 Alex Coplan <alex.coplan@arm.com>
2817 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
2819 (-mlate-ldp-fusion): Likewise.
2821 2024-01-10 Tamar Christina <tamar.christina@arm.com>
2823 PR tree-optimization/113287
2824 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
2825 instead of using BRANCH_EDGE to determine true edge.
2827 2024-01-10 Richard Biener <rguenther@suse.de>
2829 PR tree-optimization/113078
2830 * tree-vect-loop.cc (check_reduction_path): Canonicalize
2831 .COND_SUB to .COND_ADD.
2833 2024-01-10 David Malcolm <dmalcolm@redhat.com>
2835 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
2836 Handle prefix mappings before calling find_opt.
2837 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
2838 "-fno-"-prefixed command-line option.
2839 * opts-common.cc (get_option_prefix_remapping): New.
2840 * opts.h (get_option_prefix_remapping): New decl.
2842 2024-01-10 David Malcolm <dmalcolm@redhat.com>
2844 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
2845 m_urlifier to pp_output_formatted_text.
2846 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
2847 (obstack_append_string): New overload, taking a length.
2848 (urlify_quoted_string): Pass in an obstack ptr, rather than using
2849 that of the pp's buffer. Generalize to handle trailing text in
2850 the buffer beyond the run of quoted text.
2851 (class quoting_info): New.
2852 (on_begin_quote): New.
2853 (on_end_quote): New.
2854 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
2855 it to calls to on_begin_quote and on_end_quote.
2856 (struct auto_obstack): New.
2857 (quoting_info::handle_phase_3): New.
2858 (pp_output_formatted_text): Add urlifier param. Use it if there
2859 is deferred urlification. Delete m_quotes.
2860 (selftest::pp_printf_with_urlifier): Pass urlifier to
2861 pp_output_formatted_text.
2862 (selftest::test_urlification): Update results for the existing
2863 case of quoted text stradding chunks; add more such test cases.
2864 * pretty-print.h (class quoting_info): New forward decl.
2865 (chunk_info::m_quotes): New field.
2866 (pp_output_formatted_text): Add optional urlifier param.
2868 2024-01-10 David Malcolm <dmalcolm@redhat.com>
2870 * pretty-print.cc (selftest::test_pp_format): Add selftest
2871 coverage for numbered args.
2873 2024-01-10 Tamar Christina <tamar.christina@arm.com>
2875 PR tree-optimization/113144
2876 PR tree-optimization/113145
2877 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2878 Update all BB that the original exits dominated.
2880 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
2882 * dwarf2out.cc (modified_type_die): Extend the support of reverse
2883 storage order to enumeration types if -gstrict-dwarf is not passed.
2884 (gen_enumeration_type_die): Add REVERSE parameter and generate the
2885 DIE immediately after the existing one if it is true.
2886 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
2887 call to gen_enumeration_type_die.
2888 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
2889 first recursive call as well as the call to gen_tagged_type_die.
2890 (gen_type_die): Add REVERSE parameter and pass it in the call to
2891 gen_type_die_with_usage.
2893 2024-01-10 Jakub Jelinek <jakub@redhat.com>
2895 PR tree-optimization/113120
2896 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
2897 with root->size TYPE_PRECISION don't build anything new.
2898 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
2899 rather than build_nonstandard_integer_type.
2901 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
2903 * config/i386/i386.opt: Adjust document.
2904 * doc/invoke.texi: Add description for
2905 -mapx-inline-asm-use-gpr32.
2907 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2909 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
2910 (avg<v_double_trunc>3_floor): New pattern.
2911 (<u>avg<v_double_trunc>3_ceil): Remove.
2912 (avg<v_double_trunc>3_ceil): New pattern.
2913 (uavg<mode>3_floor): Ditto.
2914 (uavg<mode>3_ceil): Ditto.
2915 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
2916 (enum insn_type): Ditto.
2917 * config/riscv/riscv-v.cc: Ditto.
2918 * config/riscv/vector-iterators.md (ashiftrt): Remove.
2920 * config/riscv/vector.md: Add VLS modes.
2922 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
2925 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
2926 (vczlsbb_char): New int attribute.
2927 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
2928 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
2929 (*vctzlsbb_zext_<mode>): Rename to ...
2930 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
2933 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
2936 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
2937 of the last argument from altivec_register_operand to any_operand. If
2938 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
2939 otherwise if it doesn't satisfy altivec_register_operand, force it to
2940 REG using copy_to_mode_reg.
2942 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
2944 PR middle-end/113100
2945 * builtins.cc (expand_builtin_stack_address): Guard stack point
2946 adjustment with SPARC_STACK_BOUNDARY_HACK.
2948 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
2950 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
2951 argument string definitions.
2952 * config/loongarch/loongarch-str.h: Same.
2953 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
2954 as aliases to -mexplicit-relocs={always,none}
2955 * config/loongarch/loongarch.opt: Regenerate.
2956 * config/loongarch/loongarch.cc: Same.
2958 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
2960 * config/loongarch/loongarch-def.h: Define constants with
2961 enums instead of Macros.
2963 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
2965 * config/loongarch/genopts/loongarch-strings: Rename.
2966 * config/loongarch/genopts/loongarch.opt.in: Same.
2967 * config/loongarch/loongarch-cpu.cc: Same.
2968 * config/loongarch/loongarch-def.cc: Same.
2969 * config/loongarch/loongarch-def.h: Same.
2970 * config/loongarch/loongarch-opts.cc: Same.
2971 * config/loongarch/loongarch-opts.h: Same.
2972 * config/loongarch/loongarch-str.h: Same.
2973 * config/loongarch/loongarch.opt: Same.
2975 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
2977 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
2978 variable with the common la_ prefix.
2979 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
2980 flags as saved using TargetVariable.
2981 * config/loongarch/loongarch.opt: Same.
2982 * config/loongarch/loongarch-def.h: Define evolution_set to
2983 mark changes to the -march default.
2984 * config/loongarch/loongarch-driver.cc: Same.
2985 * config/loongarch/loongarch-opts.cc: Same.
2986 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
2987 conditions around the la_target structure.
2988 * config/loongarch/loongarch.cc: Same.
2989 * config/loongarch/loongarch.md: Same.
2990 * config/loongarch/loongarch-builtins.cc: Same.
2991 * config/loongarch/loongarch-c.cc: Same.
2992 * config/loongarch/lasx.md: Same.
2993 * config/loongarch/lsx.md: Same.
2994 * config/loongarch/sync.md: Same.
2996 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
2998 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
3001 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
3003 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
3005 2024-01-09 Tamar Christina <tamar.christina@arm.com>
3007 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
3009 (vectorizable_live_operation): Likewise.
3011 2024-01-09 Tamar Christina <tamar.christina@arm.com>
3013 PR tree-optimization/113199
3014 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
3017 2024-01-09 Jakub Jelinek <jakub@redhat.com>
3020 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
3021 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
3022 GTY(()) declaration before the definition, drop GTY(()) drom the
3025 2024-01-09 Richard Biener <rguenther@suse.de>
3027 PR tree-optimization/113026
3028 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
3029 redundant and wrong niter bound setting. Move niter
3030 bound adjustment down.
3032 2024-01-09 Tamar Christina <tamar.christina@arm.com>
3034 PR middle-end/113163
3035 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
3036 Reject non-linear inductions that aren't supported.
3038 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
3040 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
3041 left shift implementation strategies.
3042 (arc_shift_info): Type for each entry of the shift strategy table.
3043 (arc_shift_context_idx): Return a integer value for each code
3044 generation context, used as an index
3045 (arc_ashl_alg): Table indexed by context and shifted bit count.
3046 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
3047 left shift implementation.
3048 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
3049 provide accurate costs, when optimizing for speed or size.
3051 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3053 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
3055 2024-01-09 Julian Brown <julian@codesourcery.com>
3057 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
3058 processed out before gimplification.
3059 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
3060 * tree.def (OMP_ARRAY_SECTION): New tree code.
3062 2024-01-09 Jakub Jelinek <jakub@redhat.com>
3064 PR tree-optimization/113210
3065 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
3066 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
3067 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
3070 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
3072 PR rtl-optimization/113140
3073 * reorg.cc (fill_slots_from_thread): If we are to branch after the
3074 last instruction of the function, create an end label.
3076 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
3077 Hongtao Liu <hongtao.liu@intel.com>
3080 * config/i386/i386-expand.cc
3081 (ix86_convert_const_wide_int_to_broadcast): Allow call to
3082 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
3083 (ix86_broadcast_from_constant): Revert recent change; Return a
3084 suitable MEMREF independently of mode/target combinations.
3085 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
3086 to decide whether expansion is possible/preferrable. Only try
3087 forcing DImode constants to memory (and trying again) if calling
3088 ix86_expand_vector_init_duplicate fails with an DImode immediate
3090 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
3091 V4SImode for suitable immediate constants.
3092 <case E_V4DImode>: Try using V8SImode for suitable constants.
3093 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
3094 <case E_V2HImode>: Likewise.
3095 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
3096 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
3097 <label widen>: Handle CONT_INTs via simplify_binary_operation.
3098 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
3099 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
3100 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
3101 (ix86_expand_vector_init): Move try using a broadcast for all_same
3102 with ix86_expand_vector_init_duplicate before using constant pool.
3104 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
3106 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
3108 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
3110 * config/arm/arm-cpus.in (cortex-m52): New cpu.
3111 * config/arm/arm-tables.opt: Regenerate.
3112 * config/arm/arm-tune.md: Regenerate.
3114 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
3116 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
3117 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
3118 (@vec_concatz<mode>): New insn pattern.
3119 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
3120 Handle VALS containing two vectors.
3122 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3124 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
3125 (vundefined): Ditto.
3127 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
3129 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
3130 Add new function_base for crypto vector.
3131 (class bitmanip): Ditto.
3132 (class b_reverse):Ditto.
3133 (class vwsll): Ditto.
3134 (class clmul): Ditto.
3135 (class vg_nhab): Ditto.
3136 (class crypto_vv):Ditto.
3137 (class crypto_vi):Ditto.
3138 (class vaeskf2_vsm3c):Ditto.
3139 (class vsm3me): Ditto.
3140 (BASE): Add BASE declaration for crypto vector.
3141 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
3142 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
3143 Add crypto vector intrinsic definition.
3171 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
3172 Add new function_shape for crypto vector.
3173 (struct crypto_vi_def): Ditto.
3174 (struct crypto_vv_no_op_type_def): Ditto.
3175 (SHAPE): Add SHAPE declaration of crypto vector.
3176 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
3177 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
3178 Add new data type for crypto vector.
3179 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3180 (vuint32mf2_t): Ditto.
3181 (vuint32m1_t): Ditto.
3182 (vuint32m2_t): Ditto.
3183 (vuint32m4_t): Ditto.
3184 (vuint32m8_t): Ditto.
3185 (vuint64m1_t): Ditto.
3186 (vuint64m2_t): Ditto.
3187 (vuint64m4_t): Ditto.
3188 (vuint64m8_t): Ditto.
3189 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
3190 Add new data struct for crypto vector.
3191 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3192 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
3193 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
3195 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
3198 * varasm.cc (assemble_function_label_raw): Do not call
3199 asan_function_start () without the current function.
3201 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
3204 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
3205 extern and kernel_helper attributed function decls.
3207 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
3209 * btfout.cc (output_btf_strs): Changed.
3211 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
3213 * config/gcn/mkoffload.cc (main): Handle gfx1100
3214 when setting the default XNACK.
3216 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
3218 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
3219 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
3220 (ASM_SPEC): Handle gfx1100.
3221 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
3222 (enum gcn_isa): Add ISA_RDNA3.
3223 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
3224 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
3225 * config/gcn/gcn.cc (gcn_option_override,
3226 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
3227 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
3228 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
3229 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
3231 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
3232 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
3234 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
3235 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
3236 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
3237 (isa_has_combined_avgprs, main): Handle gfx1100.
3238 * config/gcn/t-omp-device (isa): Add gfx1100.
3240 2024-01-08 Richard Biener <rguenther@suse.de>
3242 * doc/invoke.texi (-mmovbe): Clarify.
3244 2024-01-08 Richard Biener <rguenther@suse.de>
3246 PR tree-optimization/113026
3247 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
3248 Avoid an epilog in more cases.
3249 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
3250 epilogues niter upper bounds and estimates.
3252 2024-01-08 Jakub Jelinek <jakub@redhat.com>
3254 PR tree-optimization/113228
3255 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
3257 2024-01-08 Jakub Jelinek <jakub@redhat.com>
3259 PR tree-optimization/113120
3260 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
3261 large _BitInt zero INTEGER_CST PHI argument.
3263 2024-01-08 Jakub Jelinek <jakub@redhat.com>
3265 PR tree-optimization/113119
3266 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
3267 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
3268 is before REALPART_EXPR.
3270 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
3273 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
3274 range when diagnosing attribute "io" and "io_low" are out of range.
3275 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
3276 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
3277 in contexts other than static storage.
3278 (avr_asm_output_aligned_decl_common): Move output of decls with
3279 attribute "address", "io", and "io_low" to...
3280 (avr_output_addr_attrib): ...this new function.
3281 (avr_asm_asm_output_aligned_bss): Remove output for decls with
3282 attribute "address", "io", and "io_low".
3283 (avr_encode_section_info): Rectify handling of decls with attribute
3284 "address", "io", and "io_low".
3286 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
3288 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
3289 (elf_flags): Remove XNACK from the default value.
3290 (main): Set a default XNACK according to the arch.
3292 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
3294 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
3295 (process_asm): Don't count avgprs.
3297 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
3299 * config/i386/i386.opt: Add supported sub-features.
3300 * doc/extend.texi: Add description for target attribute.
3302 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
3304 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
3306 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
3307 Uros Bizjak <ubizjak@gmail.com>
3310 * config/i386/i386-features.cc (compute_convert_gain): Include
3311 the overhead of explicit load and store (movd) instructions when
3312 converting non-store scalar operations with memory destinations.
3313 Various indentation whitespace fixes.
3315 2024-01-07 Tamar Christina <tamar.christina@arm.com>
3317 * config/arm/neon.md (cbranch<mode>4): New.
3319 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3321 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
3323 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
3325 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
3327 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3330 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
3333 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3335 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
3336 (variable_vectorized_p): Teach loop invariant.
3337 (has_unexpected_spills_p): Ditto.
3339 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3341 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
3342 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
3343 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
3345 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
3348 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
3349 (aarch64-vect-compare-costs): ...this.
3350 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
3352 (-param=aarch64-vect-compare-costs=): ...this new param.
3353 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
3354 Don't disable it when vectorizing for Advanced SIMD only.
3355 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
3356 whenever aarch64_vect_compare_costs is true.
3358 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
3360 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
3361 Modify the method of determining the memory offset of [x]vld/[x]vst.
3362 (lasx_mxst_<lasxfmt_f>): Likewise.
3363 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
3364 (loongarch_address_insns): Likewise.
3365 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
3366 (lsx_st_<lsxfmt_f>): Likewise.
3367 * config/loongarch/predicates.md (aq10b_operand): Likewise.
3368 (aq10h_operand): Likewise.
3369 (aq10w_operand): Likewise.
3370 (aq10d_operand): Likewise.
3372 2024-01-05 Alex Coplan <alex.coplan@arm.com>
3375 * config/aarch64/aarch64-ldp-fusion.cc
3376 (ldp_bb_info::try_fuse_pair): If the second access can throw,
3377 narrow the move range to exactly that insn.
3379 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
3381 * asan.cc (asan_function_start): Drop switch_to_section ().
3382 (asan_emit_stack_protection): Set .LASANPC alignment.
3383 * config/i386/i386.cc: Use assemble_function_label_raw ()
3384 instead of ASM_OUTPUT_LABEL ().
3385 * config/s390/s390.cc (s390_asm_output_function_label):
3387 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
3388 * final.cc (final_start_function_1): Drop
3389 asan_function_start ().
3390 * output.h (assemble_function_label_raw): New function.
3391 * varasm.cc (assemble_function_label_raw): Likewise.
3393 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
3395 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
3396 Use ASM_OUTPUT_FUNCTION_LABEL ().
3397 * config/alpha/alpha.cc (alpha_start_function): Likewise.
3398 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
3399 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
3400 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
3401 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
3402 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
3403 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
3404 * config/ia64/ia64.cc (ia64_start_function): Likewise.
3405 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
3407 * config/microblaze/microblaze.cc (microblaze_function_prologue):
3409 * config/mips/mips.cc (mips_start_unique_function): Return the
3411 (mips_start_function_definition): Use
3412 ASM_OUTPUT_FUNCTION_LABEL ().
3413 (mips_finish_stub): Pass the tree to
3414 mips_start_function_definition ().
3415 (mips16_build_function_stub): Likewise.
3416 (mips16_build_call_stub): Likewise.
3417 (mips_output_function_prologue): Likewise.
3418 * config/pa/pa.cc (pa_output_function_label): Use
3419 ASM_OUTPUT_FUNCTION_LABEL ().
3420 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
3421 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
3423 (rs6000_xcoff_declare_function_name): Likewise.
3425 2024-01-05 Jakub Jelinek <jakub@redhat.com>
3427 PR tree-optimization/113201
3428 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
3429 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
3431 2024-01-05 Jakub Jelinek <jakub@redhat.com>
3433 PR tree-optimization/90693
3434 * tree-ssa-math-opts.cc (match_single_bit_test): If
3435 tree_expr_nonzero_p (arg), remember it in the second argument to
3436 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
3437 arg ^ (arg - 1) > arg - 1.
3438 * internal-fn.cc (expand_POPCOUNT): If second argument to
3439 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
3440 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
3442 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
3444 * config/riscv/riscv-v.cc (expand_load_store):
3446 (expand_cond_len_op): Ditto.
3447 (expand_gather_scatter): Ditto.
3448 (expand_lanes_load_store): Ditto.
3449 (expand_fold_extract_last): Ditto.
3451 2024-01-05 Pan Li <pan2.li@intel.com>
3454 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
3456 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
3457 Add new function_base for crypto vector.
3458 (class bitmanip): Ditto.
3459 (class b_reverse):Ditto.
3460 (class vwsll): Ditto.
3461 (class clmul): Ditto.
3462 (class vg_nhab): Ditto.
3463 (class crypto_vv):Ditto.
3464 (class crypto_vi):Ditto.
3465 (class vaeskf2_vsm3c):Ditto.
3466 (class vsm3me): Ditto.
3467 (BASE): Add BASE declaration for crypto vector.
3468 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
3469 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
3470 Add crypto vector intrinsic definition.
3498 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
3499 Add new function_shape for crypto vector.
3500 (struct crypto_vi_def): Ditto.
3501 (struct crypto_vv_no_op_type_def): Ditto.
3502 (SHAPE): Add SHAPE declaration of crypto vector.
3503 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
3504 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
3505 Add new data type for crypto vector.
3506 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3507 (vuint32mf2_t): Ditto.
3508 (vuint32m1_t): Ditto.
3509 (vuint32m2_t): Ditto.
3510 (vuint32m4_t): Ditto.
3511 (vuint32m8_t): Ditto.
3512 (vuint64m1_t): Ditto.
3513 (vuint64m2_t): Ditto.
3514 (vuint64m4_t): Ditto.
3515 (vuint64m8_t): Ditto.
3516 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
3517 Add new data struct for crypto vector.
3518 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3519 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
3520 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
3522 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
3524 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
3525 Add new function_base for crypto vector.
3526 (class bitmanip): Ditto.
3527 (class b_reverse):Ditto.
3528 (class vwsll): Ditto.
3529 (class clmul): Ditto.
3530 (class vg_nhab): Ditto.
3531 (class crypto_vv):Ditto.
3532 (class crypto_vi):Ditto.
3533 (class vaeskf2_vsm3c):Ditto.
3534 (class vsm3me): Ditto.
3535 (BASE): Add BASE declaration for crypto vector.
3536 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
3537 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
3538 Add crypto vector intrinsic definition.
3566 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
3567 Add new function_shape for crypto vector.
3568 (struct crypto_vi_def): Ditto.
3569 (struct crypto_vv_no_op_type_def): Ditto.
3570 (SHAPE): Add SHAPE declaration of crypto vector.
3571 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
3572 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
3573 Add new data type for crypto vector.
3574 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3575 (vuint32mf2_t): Ditto.
3576 (vuint32m1_t): Ditto.
3577 (vuint32m2_t): Ditto.
3578 (vuint32m4_t): Ditto.
3579 (vuint32m8_t): Ditto.
3580 (vuint64m1_t): Ditto.
3581 (vuint64m2_t): Ditto.
3582 (vuint64m4_t): Ditto.
3583 (vuint64m8_t): Ditto.
3584 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
3585 Add new data struct for crypto vector.
3586 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3587 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
3588 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
3590 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3592 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
3594 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
3596 PR tree-optimization/113186
3597 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
3598 Match `^` with the `==` for 1bit integral types.
3599 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
3602 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3604 * toplev.cc (general_init): Pass lang_mask to urlifier.
3606 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3608 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
3610 (diagnostic_context::make_option_url): Update for lang_mask param.
3611 * gcc-urlifier.cc: Include "opts.h" and "options.h".
3612 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
3613 (gcc_urlifier::m_lang_mask): New field.
3614 (doc_urls): Make static.
3615 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
3616 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
3617 Look for an option by name before trying a binary search in
3619 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
3620 (gcc_urlifier::get_url_suffix_for_option): New.
3621 (make_gcc_urlifier): Add lang_mask param.
3622 (selftest::gcc_urlifier_cc_tests): Update for above changes.
3623 Verify that a URL is found for "-fpack-struct".
3624 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
3625 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
3626 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
3627 to make_gcc_urlifier.
3628 * opts-diagnostic.h (get_option_url): Add lang_mask param.
3629 * opts.cc (get_option_html_page): Remove special-casing for
3631 (get_option_url_suffix): New.
3632 (get_option_url): Reimplement.
3633 (selftest::test_get_option_html_page): Rename to...
3634 (selftest::test_get_option_url_suffix): ...this and update for
3636 (selftest::opts_cc_tests): Update for renaming.
3637 * opts.h: Include "rich-location.h".
3638 (get_option_url_suffix): New decl.
3640 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3642 * Makefile.in (ALL_OPT_URL_FILES): New.
3643 (GCC_OBJS): Add options-urls.o.
3645 (OBJS-libcommon): Likewise.
3646 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
3647 inputs to opt-gather.awk.
3648 (options-urls.cc): New Makefile target.
3649 * opt-functions.awk (url_suffix): New function.
3650 (lang_url_suffix): New function.
3651 * options-urls-cc-gen.awk: New file.
3652 * opts.h (get_opt_url_suffix): New decl.
3654 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3656 * params.opt.urls: New file, autogenerated by
3657 regenerate-opt-urls.py.
3659 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3661 * common.opt.urls: New file, autogenerated by
3662 regenerate-opt-urls.py.
3663 * config/aarch64/aarch64.opt.urls: Likewise.
3664 * config/alpha/alpha.opt.urls: Likewise.
3665 * config/alpha/elf.opt.urls: Likewise.
3666 * config/arc/arc-tables.opt.urls: Likewise.
3667 * config/arc/arc.opt.urls: Likewise.
3668 * config/arm/arm-tables.opt.urls: Likewise.
3669 * config/arm/arm.opt.urls: Likewise.
3670 * config/arm/vxworks.opt.urls: Likewise.
3671 * config/avr/avr.opt.urls: Likewise.
3672 * config/bpf/bpf.opt.urls: Likewise.
3673 * config/c6x/c6x-tables.opt.urls: Likewise.
3674 * config/c6x/c6x.opt.urls: Likewise.
3675 * config/cris/cris.opt.urls: Likewise.
3676 * config/cris/elf.opt.urls: Likewise.
3677 * config/csky/csky.opt.urls: Likewise.
3678 * config/csky/csky_tables.opt.urls: Likewise.
3679 * config/darwin.opt.urls: Likewise.
3680 * config/dragonfly.opt.urls: Likewise.
3681 * config/epiphany/epiphany.opt.urls: Likewise.
3682 * config/fr30/fr30.opt.urls: Likewise.
3683 * config/freebsd.opt.urls: Likewise.
3684 * config/frv/frv.opt.urls: Likewise.
3685 * config/ft32/ft32.opt.urls: Likewise.
3686 * config/fused-madd.opt.urls: Likewise.
3687 * config/g.opt.urls: Likewise.
3688 * config/gcn/gcn.opt.urls: Likewise.
3689 * config/gnu-user.opt.urls: Likewise.
3690 * config/h8300/h8300.opt.urls: Likewise.
3691 * config/hpux11.opt.urls: Likewise.
3692 * config/i386/cygming.opt.urls: Likewise.
3693 * config/i386/cygwin.opt.urls: Likewise.
3694 * config/i386/djgpp.opt.urls: Likewise.
3695 * config/i386/i386.opt.urls: Likewise.
3696 * config/i386/mingw-w64.opt.urls: Likewise.
3697 * config/i386/mingw.opt.urls: Likewise.
3698 * config/i386/nto.opt.urls: Likewise.
3699 * config/ia64/ia64.opt.urls: Likewise.
3700 * config/ia64/ilp32.opt.urls: Likewise.
3701 * config/ia64/vms.opt.urls: Likewise.
3702 * config/iq2000/iq2000.opt.urls: Likewise.
3703 * config/linux-android.opt.urls: Likewise.
3704 * config/linux.opt.urls: Likewise.
3705 * config/lm32/lm32.opt.urls: Likewise.
3706 * config/loongarch/loongarch.opt.urls: Likewise.
3707 * config/lynx.opt.urls: Likewise.
3708 * config/m32c/m32c.opt.urls: Likewise.
3709 * config/m32r/m32r.opt.urls: Likewise.
3710 * config/m68k/ieee.opt.urls: Likewise.
3711 * config/m68k/m68k-tables.opt.urls: Likewise.
3712 * config/m68k/m68k.opt.urls: Likewise.
3713 * config/m68k/uclinux.opt.urls: Likewise.
3714 * config/mcore/mcore.opt.urls: Likewise.
3715 * config/microblaze/microblaze.opt.urls: Likewise.
3716 * config/mips/mips-tables.opt.urls: Likewise.
3717 * config/mips/mips.opt.urls: Likewise.
3718 * config/mips/sde.opt.urls: Likewise.
3719 * config/mmix/mmix.opt.urls: Likewise.
3720 * config/mn10300/mn10300.opt.urls: Likewise.
3721 * config/moxie/moxie.opt.urls: Likewise.
3722 * config/msp430/msp430.opt.urls: Likewise.
3723 * config/nds32/nds32-elf.opt.urls: Likewise.
3724 * config/nds32/nds32-linux.opt.urls: Likewise.
3725 * config/nds32/nds32.opt.urls: Likewise.
3726 * config/netbsd-elf.opt.urls: Likewise.
3727 * config/netbsd.opt.urls: Likewise.
3728 * config/nios2/elf.opt.urls: Likewise.
3729 * config/nios2/nios2.opt.urls: Likewise.
3730 * config/nvptx/nvptx-gen.opt.urls: Likewise.
3731 * config/nvptx/nvptx.opt.urls: Likewise.
3732 * config/openbsd.opt.urls: Likewise.
3733 * config/or1k/elf.opt.urls: Likewise.
3734 * config/or1k/or1k.opt.urls: Likewise.
3735 * config/pa/pa-hpux.opt.urls: Likewise.
3736 * config/pa/pa-hpux1010.opt.urls: Likewise.
3737 * config/pa/pa-hpux1111.opt.urls: Likewise.
3738 * config/pa/pa-hpux1131.opt.urls: Likewise.
3739 * config/pa/pa.opt.urls: Likewise.
3740 * config/pa/pa64-hpux.opt.urls: Likewise.
3741 * config/pdp11/pdp11.opt.urls: Likewise.
3742 * config/pru/pru.opt.urls: Likewise.
3743 * config/riscv/riscv.opt.urls: Likewise.
3744 * config/rl78/rl78.opt.urls: Likewise.
3745 * config/rpath.opt.urls: Likewise.
3746 * config/rs6000/476.opt.urls: Likewise.
3747 * config/rs6000/aix64.opt.urls: Likewise.
3748 * config/rs6000/darwin.opt.urls: Likewise.
3749 * config/rs6000/linux64.opt.urls: Likewise.
3750 * config/rs6000/rs6000-tables.opt.urls: Likewise.
3751 * config/rs6000/rs6000.opt.urls: Likewise.
3752 * config/rs6000/sysv4.opt.urls: Likewise.
3753 * config/rtems.opt.urls: Likewise.
3754 * config/rx/elf.opt.urls: Likewise.
3755 * config/rx/rx.opt.urls: Likewise.
3756 * config/s390/s390.opt.urls: Likewise.
3757 * config/s390/tpf.opt.urls: Likewise.
3758 * config/sh/sh.opt.urls: Likewise.
3759 * config/sh/superh.opt.urls: Likewise.
3760 * config/sol2.opt.urls: Likewise.
3761 * config/sparc/long-double-switch.opt.urls: Likewise.
3762 * config/sparc/sparc.opt.urls: Likewise.
3763 * config/stormy16/stormy16.opt.urls: Likewise.
3764 * config/v850/v850.opt.urls: Likewise.
3765 * config/vax/elf.opt.urls: Likewise.
3766 * config/vax/vax.opt.urls: Likewise.
3767 * config/visium/visium.opt.urls: Likewise.
3768 * config/vms/vms.opt.urls: Likewise.
3769 * config/vxworks-smp.opt.urls: Likewise.
3770 * config/vxworks.opt.urls: Likewise.
3771 * config/xtensa/elf.opt.urls: Likewise.
3772 * config/xtensa/uclinux.opt.urls: Likewise.
3773 * config/xtensa/xtensa.opt.urls: Likewise.
3774 * config/bfin/bfin.opt.urls: New file.
3776 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3778 * Makefile.in (OPT_URLS_HTML_DEPS): New.
3779 (regenerate-opt-urls): New target.
3780 (regenerate-opt-urls-unit-test): New target.
3781 * doc/options.texi (Option properties): Add UrlSuffix and
3782 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
3783 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
3784 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
3785 and Makefile.in's OPT_URLS_HTML_DEPS.
3786 (Anatomy of a Target Back End): Add
3787 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
3788 * regenerate-opt-urls.py: New file.
3790 2024-01-04 David Malcolm <dmalcolm@redhat.com>
3792 * diagnostic-format-sarif.cc
3793 (sarif_builder::make_logical_location_object): Convert to...
3794 (make_sarif_logical_location_object): ...this.
3795 (sarif_builder::set_any_logical_locs_arr): Update for above
3797 (sarif_builder::make_thread_flow_location_object): Call
3798 maybe_add_sarif_properties on each diagnostic_event.
3799 * diagnostic-format-sarif.h (class logical_location): New forward
3801 (make_sarif_logical_location_object): New decl.
3802 * diagnostic-path.h (class sarif_object): New forward decl.
3803 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
3805 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
3806 Patrick Lin <patrick@andestech.com>
3807 Rufus Chen <rufus@andestech.com>
3808 Monk Chiang <monk.chiang@sifive.com>
3810 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
3811 with Nan-boxing value.
3812 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
3814 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
3815 Jeff Law <jlaw@ventanamicro.com>
3817 PR rtl-optimization/104914
3818 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
3819 a sign or zero extension is only required if the modified field
3820 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
3821 targets, don't refer to the temporarily incorrectly extended value
3822 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
3824 2024-01-04 Pan Li <pan2.li@intel.com>
3827 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3829 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
3831 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3833 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
3835 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
3837 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
3840 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3842 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
3843 (compute_nregs_for_mode): Refine LMUL.
3844 (max_number_of_live_regs): Ditto.
3845 (compute_estimated_lmul): Ditto.
3846 (has_unexpected_spills_p): Ditto.
3848 2024-01-04 Li Wei <liwei@loongson.cn>
3850 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
3851 Remove useless forward declaration.
3852 (loongarch_is_even_extraction): Remove useless forward declaration.
3853 (loongarch_try_expand_lsx_vshuf_const): Removed.
3854 (loongarch_expand_vec_perm_const_1): Merged.
3855 (loongarch_is_double_duplicate): Removed.
3856 (loongarch_is_center_extraction): Ditto.
3857 (loongarch_is_reversing_permutation): Ditto.
3858 (loongarch_is_di_misalign_extract): Ditto.
3859 (loongarch_is_si_misalign_extract): Ditto.
3860 (loongarch_is_lasx_lowpart_extract): Ditto.
3861 (loongarch_is_op_reverse_perm): Ditto.
3862 (loongarch_is_single_op_perm): Ditto.
3863 (loongarch_is_divisible_perm): Ditto.
3864 (loongarch_is_triple_stride_extract): Ditto.
3865 (loongarch_expand_vec_perm_const_2): Merged.
3866 (loongarch_expand_vec_perm_const): New.
3867 (loongarch_vectorize_vec_perm_const): Adjust.
3869 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
3871 * omp-general.cc: Fix comment typos and misplaced/confusing
3872 comments. Delete redundant include of omp-general.h.
3874 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
3876 PR rtl-optimization/104914
3877 * config/mips/mips.md (insqisi_extended): New patterns.
3878 (inshisi_extended): Ditto.
3880 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
3882 * config/mips/mips.cc (mips_insn_cost): New function.
3884 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
3886 * config/mips/mips.md (perf_ratio): New attribute.
3888 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3892 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
3893 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
3894 blocks belong to infinite loop.
3895 (pre_vsetvl::emit_vsetvl): Remove fake edges.
3896 * config/riscv/t-riscv: Add a new include file.
3898 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3900 * config/riscv/vector.md: Fix indent.
3902 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
3904 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
3905 OMP_CLAUSE__SIMDUID_.
3906 * tree.cc (omp_clause_num_ops): Update position of entry for
3907 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
3908 (omp_clause_code_name): Likewise.
3910 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
3912 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
3913 printing of FUNC_MAP/IND_FUNC_MAP labels.
3915 2024-01-03 Jakub Jelinek <jakub@redhat.com>
3917 * gcc.cc (process_command): Update copyright notice dates.
3918 * gcov-dump.cc (print_version): Ditto.
3919 * gcov.cc (print_version): Ditto.
3920 * gcov-tool.cc (print_version): Ditto.
3921 * gengtype.cc (create_file): Ditto.
3922 * doc/cpp.texi: Bump @copying's copyright year.
3923 * doc/cppinternals.texi: Ditto.
3924 * doc/gcc.texi: Ditto.
3925 * doc/gccint.texi: Ditto.
3926 * doc/gcov.texi: Ditto.
3927 * doc/install.texi: Ditto.
3928 * doc/invoke.texi: Ditto.
3930 2024-01-03 Xi Ruoyao <xry111@xry111.site>
3932 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
3933 (fmin<mode>3): Likewise.
3934 (reduc_fmax_scal_<mode>3): New define_expand.
3935 (reduc_fmin_scal_<mode>3): Likewise.
3937 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3940 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
3941 (max_number_of_live_regs): Ditto.
3942 (has_unexpected_spills_p): Ditto.
3944 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
3945 Jin Ma <jinma@linux.alibaba.com>
3946 Xianmiao Qu <cooper.qu@linux.alibaba.com>
3947 Christoph Müllner <christoph.muellner@vrull.eu>
3949 * config/riscv/vector.md:
3950 Use vector_length_operand for vsetvl patterns.
3952 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3954 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
3955 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
3957 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
3959 * config/aarch64/aarch64-tuning-flags.def
3960 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
3961 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
3962 * config/aarch64/aarch64.cc
3963 (aarch64_override_options_internal): Set
3964 param_fully_pipelined_fma according to tuning option.
3965 * config/aarch64/tuning_models/ampere1.h: Add
3966 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
3967 * config/aarch64/tuning_models/ampere1a.h: Likewise.
3968 * config/aarch64/tuning_models/ampere1b.h: Likewise.
3970 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
3972 * config/riscv/vector-crypto.md: Modify copyright year.
3974 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3976 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
3978 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
3980 * config.in: Regenerate.
3981 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
3982 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
3983 Added TLS Le Relax support.
3984 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
3985 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
3986 * configure: Regenerate.
3987 * configure.ac: Check if binutils supports TLS le relax.
3989 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
3991 * config/riscv/iterators.md: Add rotate insn name.
3992 * config/riscv/riscv.md: Add new insns name for crypto vector.
3993 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
3994 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
3995 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
3997 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4000 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
4001 pointer type liveness count.
4003 Copyright (C) 2024 Free Software Foundation, Inc.
4005 Copying and distribution of this file, with or without modification,
4006 are permitted in any medium without royalty provided the copyright
4007 notice and this notice are preserved.