1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx
*reg_last_death
;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx
*reg_last_set
;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set
;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid
;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn
;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn
;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid
;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs
;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn
;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block
;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks
;
202 static int need_refresh
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; unsigned int i
;} old_contents
;
318 union {rtx
*r
; unsigned int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST
PARAMS ((rtx
*, rtx
));
342 static void do_SUBST_INT
PARAMS ((unsigned int *,
344 static void init_reg_last_arrays
PARAMS ((void));
345 static void setup_incoming_promotions
PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
347 static int cant_combine_insn_p
PARAMS ((rtx
));
348 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
349 static int sets_function_arg_p
PARAMS ((rtx
));
350 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
351 static int contains_muldiv
PARAMS ((rtx
));
352 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
353 static void undo_all
PARAMS ((void));
354 static void undo_commit
PARAMS ((void));
355 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
356 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
357 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
358 static rtx simplify_if_then_else
PARAMS ((rtx
));
359 static rtx simplify_set
PARAMS ((rtx
));
360 static rtx simplify_logical
PARAMS ((rtx
, int));
361 static rtx expand_compound_operation
PARAMS ((rtx
));
362 static rtx expand_field_assignment
PARAMS ((rtx
));
363 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
364 rtx
, unsigned HOST_WIDE_INT
, int,
366 static rtx extract_left_shift
PARAMS ((rtx
, int));
367 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
368 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
369 unsigned HOST_WIDE_INT
*));
370 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
371 unsigned HOST_WIDE_INT
, rtx
, int));
372 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
373 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
374 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
375 static rtx make_field_assignment
PARAMS ((rtx
));
376 static rtx apply_distributive_law
PARAMS ((rtx
));
377 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
378 unsigned HOST_WIDE_INT
));
379 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
380 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
381 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
382 enum rtx_code
, HOST_WIDE_INT
,
383 enum machine_mode
, int *));
384 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
386 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
387 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
388 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
390 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
391 static void update_table_tick
PARAMS ((rtx
));
392 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
393 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
394 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
395 static void record_dead_and_set_regs
PARAMS ((rtx
));
396 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
397 static rtx get_last_value
PARAMS ((rtx
));
398 static int use_crosses_set_p
PARAMS ((rtx
, int));
399 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
400 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
401 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
402 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
403 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
404 static void distribute_links
PARAMS ((rtx
));
405 static void mark_used_regs_combine
PARAMS ((rtx
));
406 static int insn_cuid
PARAMS ((rtx
));
407 static void record_promoted_value
PARAMS ((rtx
, rtx
));
408 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
409 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into
, newval
)
424 if (oldval
== newval
)
428 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
430 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
434 buf
->old_contents
.r
= oldval
;
437 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
440 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
442 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
443 for the value of a HOST_WIDE_INT value (including CONST_INT) is
447 do_SUBST_INT (into
, newval
)
448 unsigned int *into
, newval
;
451 unsigned int oldval
= *into
;
453 if (oldval
== newval
)
457 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
459 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
463 buf
->old_contents
.i
= oldval
;
466 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
469 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
471 /* Main entry point for combiner. F is the first insn of the function.
472 NREGS is the first unused pseudo-reg number.
474 Return non-zero if the combiner has turned an indirect jump
475 instruction into a direct jump. */
477 combine_instructions (f
, nregs
)
481 register rtx insn
, next
;
486 register rtx links
, nextlinks
;
488 int new_direct_jump_p
= 0;
490 combine_attempts
= 0;
493 combine_successes
= 0;
495 combine_max_regno
= nregs
;
497 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
498 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
500 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
502 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
503 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
504 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
505 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
506 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
507 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
509 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
510 reg_last_set_nonzero_bits
511 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
512 reg_last_set_sign_bit_copies
513 = (char *) xmalloc (nregs
* sizeof (char));
515 init_reg_last_arrays ();
517 init_recog_no_volatile ();
519 /* Compute maximum uid value so uid_cuid can be allocated. */
521 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
522 if (INSN_UID (insn
) > i
)
525 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
528 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
530 /* Don't use reg_nonzero_bits when computing it. This can cause problems
531 when, for example, we have j <<= 1 in a loop. */
533 nonzero_sign_valid
= 0;
535 /* Compute the mapping from uids to cuids.
536 Cuids are numbers assigned to insns, like uids,
537 except that cuids increase monotonically through the code.
539 Scan all SETs and see if we can deduce anything about what
540 bits are known to be zero for some registers and how many copies
541 of the sign bit are known to exist for those registers.
543 Also set any known values so that we can use it while searching
544 for what bits are known to be set. */
548 /* We need to initialize it here, because record_dead_and_set_regs may call
550 subst_prev_insn
= NULL_RTX
;
552 setup_incoming_promotions ();
554 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
555 sbitmap_zero (refresh_blocks
);
558 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
560 uid_cuid
[INSN_UID (insn
)] = ++i
;
566 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
568 record_dead_and_set_regs (insn
);
571 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
572 if (REG_NOTE_KIND (links
) == REG_INC
)
573 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
578 if (GET_CODE (insn
) == CODE_LABEL
)
582 nonzero_sign_valid
= 1;
584 /* Now scan all the insns in forward order. */
586 this_basic_block
= -1;
590 init_reg_last_arrays ();
591 setup_incoming_promotions ();
593 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
597 /* If INSN starts a new basic block, update our basic block number. */
598 if (this_basic_block
+ 1 < n_basic_blocks
599 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
602 if (GET_CODE (insn
) == CODE_LABEL
)
605 else if (INSN_P (insn
))
607 /* See if we know about function return values before this
608 insn based upon SUBREG flags. */
609 check_promoted_subreg (insn
, PATTERN (insn
));
611 /* Try this insn with each insn it links back to. */
613 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
614 if ((next
= try_combine (insn
, XEXP (links
, 0),
615 NULL_RTX
, &new_direct_jump_p
)) != 0)
618 /* Try each sequence of three linked insns ending with this one. */
620 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
622 rtx link
= XEXP (links
, 0);
624 /* If the linked insn has been replaced by a note, then there
625 is no point in persuing this chain any further. */
626 if (GET_CODE (link
) == NOTE
)
629 for (nextlinks
= LOG_LINKS (link
);
631 nextlinks
= XEXP (nextlinks
, 1))
632 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 &new_direct_jump_p
)) != 0)
639 /* Try to combine a jump insn that uses CC0
640 with a preceding insn that sets CC0, and maybe with its
641 logical predecessor as well.
642 This is how we make decrement-and-branch insns.
643 We need this special code because data flow connections
644 via CC0 do not get entered in LOG_LINKS. */
646 if (GET_CODE (insn
) == JUMP_INSN
647 && (prev
= prev_nonnote_insn (insn
)) != 0
648 && GET_CODE (prev
) == INSN
649 && sets_cc0_p (PATTERN (prev
)))
651 if ((next
= try_combine (insn
, prev
,
652 NULL_RTX
, &new_direct_jump_p
)) != 0)
655 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
656 nextlinks
= XEXP (nextlinks
, 1))
657 if ((next
= try_combine (insn
, prev
,
659 &new_direct_jump_p
)) != 0)
663 /* Do the same for an insn that explicitly references CC0. */
664 if (GET_CODE (insn
) == INSN
665 && (prev
= prev_nonnote_insn (insn
)) != 0
666 && GET_CODE (prev
) == INSN
667 && sets_cc0_p (PATTERN (prev
))
668 && GET_CODE (PATTERN (insn
)) == SET
669 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
671 if ((next
= try_combine (insn
, prev
,
672 NULL_RTX
, &new_direct_jump_p
)) != 0)
675 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
676 nextlinks
= XEXP (nextlinks
, 1))
677 if ((next
= try_combine (insn
, prev
,
679 &new_direct_jump_p
)) != 0)
683 /* Finally, see if any of the insns that this insn links to
684 explicitly references CC0. If so, try this insn, that insn,
685 and its predecessor if it sets CC0. */
686 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
687 if (GET_CODE (XEXP (links
, 0)) == INSN
688 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
689 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
690 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
691 && GET_CODE (prev
) == INSN
692 && sets_cc0_p (PATTERN (prev
))
693 && (next
= try_combine (insn
, XEXP (links
, 0),
694 prev
, &new_direct_jump_p
)) != 0)
698 /* Try combining an insn with two different insns whose results it
700 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
701 for (nextlinks
= XEXP (links
, 1); nextlinks
;
702 nextlinks
= XEXP (nextlinks
, 1))
703 if ((next
= try_combine (insn
, XEXP (links
, 0),
705 &new_direct_jump_p
)) != 0)
708 if (GET_CODE (insn
) != NOTE
)
709 record_dead_and_set_regs (insn
);
716 delete_noop_moves (f
);
720 compute_bb_for_insn (get_max_uid ());
721 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
726 sbitmap_free (refresh_blocks
);
727 free (reg_nonzero_bits
);
728 free (reg_sign_bit_copies
);
729 free (reg_last_death
);
731 free (reg_last_set_value
);
732 free (reg_last_set_table_tick
);
733 free (reg_last_set_label
);
734 free (reg_last_set_invalid
);
735 free (reg_last_set_mode
);
736 free (reg_last_set_nonzero_bits
);
737 free (reg_last_set_sign_bit_copies
);
741 struct undo
*undo
, *next
;
742 for (undo
= undobuf
.frees
; undo
; undo
= next
)
750 total_attempts
+= combine_attempts
;
751 total_merges
+= combine_merges
;
752 total_extras
+= combine_extras
;
753 total_successes
+= combine_successes
;
755 nonzero_sign_valid
= 0;
757 /* Make recognizer allow volatile MEMs again. */
760 return new_direct_jump_p
;
763 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
766 init_reg_last_arrays ()
768 unsigned int nregs
= combine_max_regno
;
770 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
771 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
772 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
773 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
774 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
775 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
776 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
777 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
778 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
781 /* Set up any promoted values for incoming argument registers. */
784 setup_incoming_promotions ()
786 #ifdef PROMOTE_FUNCTION_ARGS
789 enum machine_mode mode
;
791 rtx first
= get_insns ();
793 #ifndef OUTGOING_REGNO
794 #define OUTGOING_REGNO(N) N
796 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
797 /* Check whether this register can hold an incoming pointer
798 argument. FUNCTION_ARG_REGNO_P tests outgoing register
799 numbers, so translate if necessary due to register windows. */
800 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
801 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
804 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
807 gen_rtx_CLOBBER (mode
, const0_rtx
)));
812 /* Called via note_stores. If X is a pseudo that is narrower than
813 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
815 If we are setting only a portion of X and we can't figure out what
816 portion, assume all bits will be used since we don't know what will
819 Similarly, set how many bits of X are known to be copies of the sign bit
820 at all locations in the function. This is the smallest number implied
824 set_nonzero_bits_and_sign_copies (x
, set
, data
)
827 void *data ATTRIBUTE_UNUSED
;
831 if (GET_CODE (x
) == REG
832 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
833 /* If this register is undefined at the start of the file, we can't
834 say what its contents were. */
835 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
836 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
838 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
840 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
841 reg_sign_bit_copies
[REGNO (x
)] = 1;
845 /* If this is a complex assignment, see if we can convert it into a
846 simple assignment. */
847 set
= expand_field_assignment (set
);
849 /* If this is a simple assignment, or we have a paradoxical SUBREG,
850 set what we know about X. */
852 if (SET_DEST (set
) == x
853 || (GET_CODE (SET_DEST (set
)) == SUBREG
854 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
855 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
856 && SUBREG_REG (SET_DEST (set
)) == x
))
858 rtx src
= SET_SRC (set
);
860 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
861 /* If X is narrower than a word and SRC is a non-negative
862 constant that would appear negative in the mode of X,
863 sign-extend it for use in reg_nonzero_bits because some
864 machines (maybe most) will actually do the sign-extension
865 and this is the conservative approach.
867 ??? For 2.5, try to tighten up the MD files in this regard
868 instead of this kludge. */
870 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
871 && GET_CODE (src
) == CONST_INT
873 && 0 != (INTVAL (src
)
875 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
876 src
= GEN_INT (INTVAL (src
)
877 | ((HOST_WIDE_INT
) (-1)
878 << GET_MODE_BITSIZE (GET_MODE (x
))));
881 reg_nonzero_bits
[REGNO (x
)]
882 |= nonzero_bits (src
, nonzero_bits_mode
);
883 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
884 if (reg_sign_bit_copies
[REGNO (x
)] == 0
885 || reg_sign_bit_copies
[REGNO (x
)] > num
)
886 reg_sign_bit_copies
[REGNO (x
)] = num
;
890 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
891 reg_sign_bit_copies
[REGNO (x
)] = 1;
896 /* See if INSN can be combined into I3. PRED and SUCC are optionally
897 insns that were previously combined into I3 or that will be combined
898 into the merger of INSN and I3.
900 Return 0 if the combination is not allowed for any reason.
902 If the combination is allowed, *PDEST will be set to the single
903 destination of INSN and *PSRC to the single source, and this function
907 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
910 rtx pred ATTRIBUTE_UNUSED
;
915 rtx set
= 0, src
, dest
;
920 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
921 && next_active_insn (succ
) == i3
)
922 : next_active_insn (insn
) == i3
);
924 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
925 or a PARALLEL consisting of such a SET and CLOBBERs.
927 If INSN has CLOBBER parallel parts, ignore them for our processing.
928 By definition, these happen during the execution of the insn. When it
929 is merged with another insn, all bets are off. If they are, in fact,
930 needed and aren't also supplied in I3, they may be added by
931 recog_for_combine. Otherwise, it won't match.
933 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
936 Get the source and destination of INSN. If more than one, can't
939 if (GET_CODE (PATTERN (insn
)) == SET
)
940 set
= PATTERN (insn
);
941 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
942 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
944 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
946 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
948 switch (GET_CODE (elt
))
950 /* This is important to combine floating point insns
953 /* Combining an isolated USE doesn't make sense.
954 We depend here on combinable_i3_pat to reject them. */
955 /* The code below this loop only verifies that the inputs of
956 the SET in INSN do not change. We call reg_set_between_p
957 to verify that the REG in the USE does not change betweeen
959 If the USE in INSN was for a pseudo register, the matching
960 insn pattern will likely match any register; combining this
961 with any other USE would only be safe if we knew that the
962 used registers have identical values, or if there was
963 something to tell them apart, e.g. different modes. For
964 now, we forgo such compilcated tests and simply disallow
965 combining of USES of pseudo registers with any other USE. */
966 if (GET_CODE (XEXP (elt
, 0)) == REG
967 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
969 rtx i3pat
= PATTERN (i3
);
970 int i
= XVECLEN (i3pat
, 0) - 1;
971 unsigned int regno
= REGNO (XEXP (elt
, 0));
975 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
977 if (GET_CODE (i3elt
) == USE
978 && GET_CODE (XEXP (i3elt
, 0)) == REG
979 && (REGNO (XEXP (i3elt
, 0)) == regno
980 ? reg_set_between_p (XEXP (elt
, 0),
981 PREV_INSN (insn
), i3
)
982 : regno
>= FIRST_PSEUDO_REGISTER
))
989 /* We can ignore CLOBBERs. */
994 /* Ignore SETs whose result isn't used but not those that
995 have side-effects. */
996 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
997 && ! side_effects_p (elt
))
1000 /* If we have already found a SET, this is a second one and
1001 so we cannot combine with this insn. */
1009 /* Anything else means we can't combine. */
1015 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1016 so don't do anything with it. */
1017 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1026 set
= expand_field_assignment (set
);
1027 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1029 /* Don't eliminate a store in the stack pointer. */
1030 if (dest
== stack_pointer_rtx
1031 /* If we couldn't eliminate a field assignment, we can't combine. */
1032 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1033 /* Don't combine with an insn that sets a register to itself if it has
1034 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1035 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1036 /* Can't merge an ASM_OPERANDS. */
1037 || GET_CODE (src
) == ASM_OPERANDS
1038 /* Can't merge a function call. */
1039 || GET_CODE (src
) == CALL
1040 /* Don't eliminate a function call argument. */
1041 || (GET_CODE (i3
) == CALL_INSN
1042 && (find_reg_fusage (i3
, USE
, dest
)
1043 || (GET_CODE (dest
) == REG
1044 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1045 && global_regs
[REGNO (dest
)])))
1046 /* Don't substitute into an incremented register. */
1047 || FIND_REG_INC_NOTE (i3
, dest
)
1048 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1050 /* Don't combine the end of a libcall into anything. */
1051 /* ??? This gives worse code, and appears to be unnecessary, since no
1052 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1053 use REG_RETVAL notes for noconflict blocks, but other code here
1054 makes sure that those insns don't disappear. */
1055 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1057 /* Make sure that DEST is not used after SUCC but before I3. */
1058 || (succ
&& ! all_adjacent
1059 && reg_used_between_p (dest
, succ
, i3
))
1060 /* Make sure that the value that is to be substituted for the register
1061 does not use any registers whose values alter in between. However,
1062 If the insns are adjacent, a use can't cross a set even though we
1063 think it might (this can happen for a sequence of insns each setting
1064 the same destination; reg_last_set of that register might point to
1065 a NOTE). If INSN has a REG_EQUIV note, the register is always
1066 equivalent to the memory so the substitution is valid even if there
1067 are intervening stores. Also, don't move a volatile asm or
1068 UNSPEC_VOLATILE across any other insns. */
1070 && (((GET_CODE (src
) != MEM
1071 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1072 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1073 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1074 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1075 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1076 better register allocation by not doing the combine. */
1077 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1078 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1079 /* Don't combine across a CALL_INSN, because that would possibly
1080 change whether the life span of some REGs crosses calls or not,
1081 and it is a pain to update that information.
1082 Exception: if source is a constant, moving it later can't hurt.
1083 Accept that special case, because it helps -fforce-addr a lot. */
1084 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1087 /* DEST must either be a REG or CC0. */
1088 if (GET_CODE (dest
) == REG
)
1090 /* If register alignment is being enforced for multi-word items in all
1091 cases except for parameters, it is possible to have a register copy
1092 insn referencing a hard register that is not allowed to contain the
1093 mode being copied and which would not be valid as an operand of most
1094 insns. Eliminate this problem by not combining with such an insn.
1096 Also, on some machines we don't want to extend the life of a hard
1099 if (GET_CODE (src
) == REG
1100 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1101 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1102 /* Don't extend the life of a hard register unless it is
1103 user variable (if we have few registers) or it can't
1104 fit into the desired register (meaning something special
1106 Also avoid substituting a return register into I3, because
1107 reload can't handle a conflict with constraints of other
1109 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1110 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1113 else if (GET_CODE (dest
) != CC0
)
1116 /* Don't substitute for a register intended as a clobberable operand.
1117 Similarly, don't substitute an expression containing a register that
1118 will be clobbered in I3. */
1119 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1120 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1121 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1122 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1124 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1127 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1128 or not), reject, unless nothing volatile comes between it and I3 */
1130 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1132 /* Make sure succ doesn't contain a volatile reference. */
1133 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1136 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1137 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1141 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1142 to be an explicit register variable, and was chosen for a reason. */
1144 if (GET_CODE (src
) == ASM_OPERANDS
1145 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1148 /* If there are any volatile insns between INSN and I3, reject, because
1149 they might affect machine state. */
1151 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1152 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1155 /* If INSN or I2 contains an autoincrement or autodecrement,
1156 make sure that register is not used between there and I3,
1157 and not already used in I3 either.
1158 Also insist that I3 not be a jump; if it were one
1159 and the incremented register were spilled, we would lose. */
1162 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1163 if (REG_NOTE_KIND (link
) == REG_INC
1164 && (GET_CODE (i3
) == JUMP_INSN
1165 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1166 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1171 /* Don't combine an insn that follows a CC0-setting insn.
1172 An insn that uses CC0 must not be separated from the one that sets it.
1173 We do, however, allow I2 to follow a CC0-setting insn if that insn
1174 is passed as I1; in that case it will be deleted also.
1175 We also allow combining in this case if all the insns are adjacent
1176 because that would leave the two CC0 insns adjacent as well.
1177 It would be more logical to test whether CC0 occurs inside I1 or I2,
1178 but that would be much slower, and this ought to be equivalent. */
1180 p
= prev_nonnote_insn (insn
);
1181 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1186 /* If we get here, we have passed all the tests and the combination is
1195 /* Check if PAT is an insn - or a part of it - used to set up an
1196 argument for a function in a hard register. */
1199 sets_function_arg_p (pat
)
1205 switch (GET_CODE (pat
))
1208 return sets_function_arg_p (PATTERN (pat
));
1211 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1212 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1218 inner_dest
= SET_DEST (pat
);
1219 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1220 || GET_CODE (inner_dest
) == SUBREG
1221 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1222 inner_dest
= XEXP (inner_dest
, 0);
1224 return (GET_CODE (inner_dest
) == REG
1225 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1226 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1235 /* LOC is the location within I3 that contains its pattern or the component
1236 of a PARALLEL of the pattern. We validate that it is valid for combining.
1238 One problem is if I3 modifies its output, as opposed to replacing it
1239 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1240 so would produce an insn that is not equivalent to the original insns.
1244 (set (reg:DI 101) (reg:DI 100))
1245 (set (subreg:SI (reg:DI 101) 0) <foo>)
1247 This is NOT equivalent to:
1249 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1250 (set (reg:DI 101) (reg:DI 100))])
1252 Not only does this modify 100 (in which case it might still be valid
1253 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1255 We can also run into a problem if I2 sets a register that I1
1256 uses and I1 gets directly substituted into I3 (not via I2). In that
1257 case, we would be getting the wrong value of I2DEST into I3, so we
1258 must reject the combination. This case occurs when I2 and I1 both
1259 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1260 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1261 of a SET must prevent combination from occurring.
1263 Before doing the above check, we first try to expand a field assignment
1264 into a set of logical operations.
1266 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1267 we place a register that is both set and used within I3. If more than one
1268 such register is detected, we fail.
1270 Return 1 if the combination is valid, zero otherwise. */
1273 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1279 rtx
*pi3dest_killed
;
1283 if (GET_CODE (x
) == SET
)
1285 rtx set
= expand_field_assignment (x
);
1286 rtx dest
= SET_DEST (set
);
1287 rtx src
= SET_SRC (set
);
1288 rtx inner_dest
= dest
;
1291 rtx inner_src
= src
;
1296 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1297 || GET_CODE (inner_dest
) == SUBREG
1298 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1299 inner_dest
= XEXP (inner_dest
, 0);
1301 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1304 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1305 || GET_CODE (inner_src
) == SUBREG
1306 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1307 inner_src
= XEXP (inner_src
, 0);
1309 /* If it is better that two different modes keep two different pseudos,
1310 avoid combining them. This avoids producing the following pattern
1312 (set (subreg:SI (reg/v:QI 21) 0)
1313 (lshiftrt:SI (reg/v:SI 20)
1315 If that were made, reload could not handle the pair of
1316 reg 20/21, since it would try to get any GENERAL_REGS
1317 but some of them don't handle QImode. */
1319 if (rtx_equal_p (inner_src
, i2dest
)
1320 && GET_CODE (inner_dest
) == REG
1321 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1325 /* Check for the case where I3 modifies its output, as
1327 if ((inner_dest
!= dest
1328 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1329 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1331 /* This is the same test done in can_combine_p except we can't test
1332 all_adjacent; we don't have to, since this instruction will stay
1333 in place, thus we are not considering increasing the lifetime of
1336 Also, if this insn sets a function argument, combining it with
1337 something that might need a spill could clobber a previous
1338 function argument; the all_adjacent test in can_combine_p also
1339 checks this; here, we do a more specific test for this case. */
1341 || (GET_CODE (inner_dest
) == REG
1342 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1343 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1344 GET_MODE (inner_dest
))))
1345 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1348 /* If DEST is used in I3, it is being killed in this insn,
1349 so record that for later.
1350 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1351 STACK_POINTER_REGNUM, since these are always considered to be
1352 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1353 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1354 && reg_referenced_p (dest
, PATTERN (i3
))
1355 && REGNO (dest
) != FRAME_POINTER_REGNUM
1356 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1357 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1359 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1360 && (REGNO (dest
) != ARG_POINTER_REGNUM
1361 || ! fixed_regs
[REGNO (dest
)])
1363 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1365 if (*pi3dest_killed
)
1368 *pi3dest_killed
= dest
;
1372 else if (GET_CODE (x
) == PARALLEL
)
1376 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1377 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1378 i1_not_in_src
, pi3dest_killed
))
1385 /* Return 1 if X is an arithmetic expression that contains a multiplication
1386 and division. We don't count multiplications by powers of two here. */
1392 switch (GET_CODE (x
))
1394 case MOD
: case DIV
: case UMOD
: case UDIV
:
1398 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1399 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1401 switch (GET_RTX_CLASS (GET_CODE (x
)))
1403 case 'c': case '<': case '2':
1404 return contains_muldiv (XEXP (x
, 0))
1405 || contains_muldiv (XEXP (x
, 1));
1408 return contains_muldiv (XEXP (x
, 0));
1416 /* Determine whether INSN can be used in a combination. Return nonzero if
1417 not. This is used in try_combine to detect early some cases where we
1418 can't perform combinations. */
1421 cant_combine_insn_p (insn
)
1427 /* If this isn't really an insn, we can't do anything.
1428 This can occur when flow deletes an insn that it has merged into an
1429 auto-increment address. */
1430 if (! INSN_P (insn
))
1433 /* Never combine loads and stores involving hard regs. The register
1434 allocator can usually handle such reg-reg moves by tying. If we allow
1435 the combiner to make substitutions of hard regs, we risk aborting in
1436 reload on machines that have SMALL_REGISTER_CLASSES.
1437 As an exception, we allow combinations involving fixed regs; these are
1438 not available to the register allocator so there's no risk involved. */
1440 set
= single_set (insn
);
1443 src
= SET_SRC (set
);
1444 dest
= SET_DEST (set
);
1445 if (GET_CODE (src
) == SUBREG
)
1446 src
= SUBREG_REG (src
);
1447 if (GET_CODE (dest
) == SUBREG
)
1448 dest
= SUBREG_REG (dest
);
1449 if (REG_P (src
) && REG_P (dest
)
1450 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1451 && ! fixed_regs
[REGNO (src
)])
1452 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1453 && ! fixed_regs
[REGNO (dest
)])))
1459 /* Try to combine the insns I1 and I2 into I3.
1460 Here I1 and I2 appear earlier than I3.
1461 I1 can be zero; then we combine just I2 into I3.
1463 If we are combining three insns and the resulting insn is not recognized,
1464 try splitting it into two insns. If that happens, I2 and I3 are retained
1465 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1468 Return 0 if the combination does not work. Then nothing is changed.
1469 If we did the combination, return the insn at which combine should
1472 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1473 new direct jump instruction. */
1476 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1477 register rtx i3
, i2
, i1
;
1478 register int *new_direct_jump_p
;
1480 /* New patterns for I3 and I2, respectively. */
1481 rtx newpat
, newi2pat
= 0;
1482 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1483 int added_sets_1
, added_sets_2
;
1484 /* Total number of SETs to put into I3. */
1486 /* Nonzero is I2's body now appears in I3. */
1488 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1489 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1490 /* Contains I3 if the destination of I3 is used in its source, which means
1491 that the old life of I3 is being killed. If that usage is placed into
1492 I2 and not in I3, a REG_DEAD note must be made. */
1493 rtx i3dest_killed
= 0;
1494 /* SET_DEST and SET_SRC of I2 and I1. */
1495 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1496 /* PATTERN (I2), or a copy of it in certain cases. */
1498 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1499 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1500 int i1_feeds_i3
= 0;
1501 /* Notes that must be added to REG_NOTES in I3 and I2. */
1502 rtx new_i3_notes
, new_i2_notes
;
1503 /* Notes that we substituted I3 into I2 instead of the normal case. */
1504 int i3_subst_into_i2
= 0;
1505 /* Notes that I1, I2 or I3 is a MULT operation. */
1513 /* Exit early if one of the insns involved can't be used for
1515 if (cant_combine_insn_p (i3
)
1516 || cant_combine_insn_p (i2
)
1517 || (i1
&& cant_combine_insn_p (i1
))
1518 /* We also can't do anything if I3 has a
1519 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1522 /* ??? This gives worse code, and appears to be unnecessary, since no
1523 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1524 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1530 undobuf
.other_insn
= 0;
1532 /* Reset the hard register usage information. */
1533 CLEAR_HARD_REG_SET (newpat_used_regs
);
1535 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1536 code below, set I1 to be the earlier of the two insns. */
1537 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1538 temp
= i1
, i1
= i2
, i2
= temp
;
1540 added_links_insn
= 0;
1542 /* First check for one important special-case that the code below will
1543 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1544 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1545 we may be able to replace that destination with the destination of I3.
1546 This occurs in the common code where we compute both a quotient and
1547 remainder into a structure, in which case we want to do the computation
1548 directly into the structure to avoid register-register copies.
1550 Note that this case handles both multiple sets in I2 and also
1551 cases where I2 has a number of CLOBBER or PARALLELs.
1553 We make very conservative checks below and only try to handle the
1554 most common cases of this. For example, we only handle the case
1555 where I2 and I3 are adjacent to avoid making difficult register
1558 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1559 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1560 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1561 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1562 && GET_CODE (PATTERN (i2
)) == PARALLEL
1563 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1564 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1565 below would need to check what is inside (and reg_overlap_mentioned_p
1566 doesn't support those codes anyway). Don't allow those destinations;
1567 the resulting insn isn't likely to be recognized anyway. */
1568 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1569 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1570 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1571 SET_DEST (PATTERN (i3
)))
1572 && next_real_insn (i2
) == i3
)
1574 rtx p2
= PATTERN (i2
);
1576 /* Make sure that the destination of I3,
1577 which we are going to substitute into one output of I2,
1578 is not used within another output of I2. We must avoid making this:
1579 (parallel [(set (mem (reg 69)) ...)
1580 (set (reg 69) ...)])
1581 which is not well-defined as to order of actions.
1582 (Besides, reload can't handle output reloads for this.)
1584 The problem can also happen if the dest of I3 is a memory ref,
1585 if another dest in I2 is an indirect memory ref. */
1586 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1587 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1588 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1589 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1590 SET_DEST (XVECEXP (p2
, 0, i
))))
1593 if (i
== XVECLEN (p2
, 0))
1594 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1595 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1596 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1597 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1602 subst_low_cuid
= INSN_CUID (i2
);
1604 added_sets_2
= added_sets_1
= 0;
1605 i2dest
= SET_SRC (PATTERN (i3
));
1607 /* Replace the dest in I2 with our dest and make the resulting
1608 insn the new pattern for I3. Then skip to where we
1609 validate the pattern. Everything was set up above. */
1610 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1611 SET_DEST (PATTERN (i3
)));
1614 i3_subst_into_i2
= 1;
1615 goto validate_replacement
;
1619 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1620 one of those words to another constant, merge them by making a new
1623 && (temp
= single_set (i2
)) != 0
1624 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1625 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1626 && GET_CODE (SET_DEST (temp
)) == REG
1627 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1628 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1629 && GET_CODE (PATTERN (i3
)) == SET
1630 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1631 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1632 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1633 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1634 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1636 HOST_WIDE_INT lo
, hi
;
1638 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1639 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1642 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1643 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1646 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1648 /* We don't handle the case of the target word being wider
1649 than a host wide int. */
1650 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1653 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1654 lo
|= INTVAL (SET_SRC (PATTERN (i3
)));
1656 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1657 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1658 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1660 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1661 >> (HOST_BITS_PER_WIDE_INT
- 1));
1663 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1664 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1665 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1666 (INTVAL (SET_SRC (PATTERN (i3
)))));
1668 hi
= lo
< 0 ? -1 : 0;
1671 /* We don't handle the case of the higher word not fitting
1672 entirely in either hi or lo. */
1677 subst_low_cuid
= INSN_CUID (i2
);
1678 added_sets_2
= added_sets_1
= 0;
1679 i2dest
= SET_DEST (temp
);
1681 SUBST (SET_SRC (temp
),
1682 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1684 newpat
= PATTERN (i2
);
1685 goto validate_replacement
;
1689 /* If we have no I1 and I2 looks like:
1690 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1692 make up a dummy I1 that is
1695 (set (reg:CC X) (compare:CC Y (const_int 0)))
1697 (We can ignore any trailing CLOBBERs.)
1699 This undoes a previous combination and allows us to match a branch-and-
1702 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1703 && XVECLEN (PATTERN (i2
), 0) >= 2
1704 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1705 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1707 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1708 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1709 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1710 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1711 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1712 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1714 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1715 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1720 /* We make I1 with the same INSN_UID as I2. This gives it
1721 the same INSN_CUID for value tracking. Our fake I1 will
1722 never appear in the insn stream so giving it the same INSN_UID
1723 as I2 will not cause a problem. */
1725 subst_prev_insn
= i1
1726 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1727 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1730 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1731 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1732 SET_DEST (PATTERN (i1
)));
1737 /* Verify that I2 and I1 are valid for combining. */
1738 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1739 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1745 /* Record whether I2DEST is used in I2SRC and similarly for the other
1746 cases. Knowing this will help in register status updating below. */
1747 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1748 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1749 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1751 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1753 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1755 /* Ensure that I3's pattern can be the destination of combines. */
1756 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1757 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1764 /* See if any of the insns is a MULT operation. Unless one is, we will
1765 reject a combination that is, since it must be slower. Be conservative
1767 if (GET_CODE (i2src
) == MULT
1768 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1769 || (GET_CODE (PATTERN (i3
)) == SET
1770 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1773 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1774 We used to do this EXCEPT in one case: I3 has a post-inc in an
1775 output operand. However, that exception can give rise to insns like
1777 which is a famous insn on the PDP-11 where the value of r3 used as the
1778 source was model-dependent. Avoid this sort of thing. */
1781 if (!(GET_CODE (PATTERN (i3
)) == SET
1782 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1783 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1784 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1785 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1786 /* It's not the exception. */
1789 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1790 if (REG_NOTE_KIND (link
) == REG_INC
1791 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1793 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1800 /* See if the SETs in I1 or I2 need to be kept around in the merged
1801 instruction: whenever the value set there is still needed past I3.
1802 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1804 For the SET in I1, we have two cases: If I1 and I2 independently
1805 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1806 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1807 in I1 needs to be kept around unless I1DEST dies or is set in either
1808 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1809 I1DEST. If so, we know I1 feeds into I2. */
1811 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1814 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1815 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1817 /* If the set in I2 needs to be kept around, we must make a copy of
1818 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1819 PATTERN (I2), we are only substituting for the original I1DEST, not into
1820 an already-substituted copy. This also prevents making self-referential
1821 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1824 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1825 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1829 i2pat
= copy_rtx (i2pat
);
1833 /* Substitute in the latest insn for the regs set by the earlier ones. */
1835 maxreg
= max_reg_num ();
1839 /* It is possible that the source of I2 or I1 may be performing an
1840 unneeded operation, such as a ZERO_EXTEND of something that is known
1841 to have the high part zero. Handle that case by letting subst look at
1842 the innermost one of them.
1844 Another way to do this would be to have a function that tries to
1845 simplify a single insn instead of merging two or more insns. We don't
1846 do this because of the potential of infinite loops and because
1847 of the potential extra memory required. However, doing it the way
1848 we are is a bit of a kludge and doesn't catch all cases.
1850 But only do this if -fexpensive-optimizations since it slows things down
1851 and doesn't usually win. */
1853 if (flag_expensive_optimizations
)
1855 /* Pass pc_rtx so no substitutions are done, just simplifications.
1856 The cases that we are interested in here do not involve the few
1857 cases were is_replaced is checked. */
1860 subst_low_cuid
= INSN_CUID (i1
);
1861 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1865 subst_low_cuid
= INSN_CUID (i2
);
1866 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1871 /* Many machines that don't use CC0 have insns that can both perform an
1872 arithmetic operation and set the condition code. These operations will
1873 be represented as a PARALLEL with the first element of the vector
1874 being a COMPARE of an arithmetic operation with the constant zero.
1875 The second element of the vector will set some pseudo to the result
1876 of the same arithmetic operation. If we simplify the COMPARE, we won't
1877 match such a pattern and so will generate an extra insn. Here we test
1878 for this case, where both the comparison and the operation result are
1879 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1880 I2SRC. Later we will make the PARALLEL that contains I2. */
1882 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1883 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1884 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1885 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1887 #ifdef EXTRA_CC_MODES
1889 enum machine_mode compare_mode
;
1892 newpat
= PATTERN (i3
);
1893 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1897 #ifdef EXTRA_CC_MODES
1898 /* See if a COMPARE with the operand we substituted in should be done
1899 with the mode that is currently being used. If not, do the same
1900 processing we do in `subst' for a SET; namely, if the destination
1901 is used only once, try to replace it with a register of the proper
1902 mode and also replace the COMPARE. */
1903 if (undobuf
.other_insn
== 0
1904 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1905 &undobuf
.other_insn
))
1906 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1908 != GET_MODE (SET_DEST (newpat
))))
1910 unsigned int regno
= REGNO (SET_DEST (newpat
));
1911 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1913 if (regno
< FIRST_PSEUDO_REGISTER
1914 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1915 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1917 if (regno
>= FIRST_PSEUDO_REGISTER
)
1918 SUBST (regno_reg_rtx
[regno
], new_dest
);
1920 SUBST (SET_DEST (newpat
), new_dest
);
1921 SUBST (XEXP (*cc_use
, 0), new_dest
);
1922 SUBST (SET_SRC (newpat
),
1923 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1926 undobuf
.other_insn
= 0;
1933 n_occurrences
= 0; /* `subst' counts here */
1935 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1936 need to make a unique copy of I2SRC each time we substitute it
1937 to avoid self-referential rtl. */
1939 subst_low_cuid
= INSN_CUID (i2
);
1940 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1941 ! i1_feeds_i3
&& i1dest_in_i1src
);
1943 /* Record whether i2's body now appears within i3's body. */
1944 i2_is_used
= n_occurrences
;
1947 /* If we already got a failure, don't try to do more. Otherwise,
1948 try to substitute in I1 if we have it. */
1950 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1952 /* Before we can do this substitution, we must redo the test done
1953 above (see detailed comments there) that ensures that I1DEST
1954 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1956 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1964 subst_low_cuid
= INSN_CUID (i1
);
1965 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1968 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1969 to count all the ways that I2SRC and I1SRC can be used. */
1970 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1971 && i2_is_used
+ added_sets_2
> 1)
1972 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1973 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1975 /* Fail if we tried to make a new register (we used to abort, but there's
1976 really no reason to). */
1977 || max_reg_num () != maxreg
1978 /* Fail if we couldn't do something and have a CLOBBER. */
1979 || GET_CODE (newpat
) == CLOBBER
1980 /* Fail if this new pattern is a MULT and we didn't have one before
1981 at the outer level. */
1982 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1989 /* If the actions of the earlier insns must be kept
1990 in addition to substituting them into the latest one,
1991 we must make a new PARALLEL for the latest insn
1992 to hold additional the SETs. */
1994 if (added_sets_1
|| added_sets_2
)
1998 if (GET_CODE (newpat
) == PARALLEL
)
2000 rtvec old
= XVEC (newpat
, 0);
2001 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2002 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2003 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2004 sizeof (old
->elem
[0]) * old
->num_elem
);
2009 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2010 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2011 XVECEXP (newpat
, 0, 0) = old
;
2015 XVECEXP (newpat
, 0, --total_sets
)
2016 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2017 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2021 /* If there is no I1, use I2's body as is. We used to also not do
2022 the subst call below if I2 was substituted into I3,
2023 but that could lose a simplification. */
2025 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2027 /* See comment where i2pat is assigned. */
2028 XVECEXP (newpat
, 0, --total_sets
)
2029 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2033 /* We come here when we are replacing a destination in I2 with the
2034 destination of I3. */
2035 validate_replacement
:
2037 /* Note which hard regs this insn has as inputs. */
2038 mark_used_regs_combine (newpat
);
2040 /* Is the result of combination a valid instruction? */
2041 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2043 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2044 the second SET's destination is a register that is unused. In that case,
2045 we just need the first SET. This can occur when simplifying a divmod
2046 insn. We *must* test for this case here because the code below that
2047 splits two independent SETs doesn't handle this case correctly when it
2048 updates the register status. Also check the case where the first
2049 SET's destination is unused. That would not cause incorrect code, but
2050 does cause an unneeded insn to remain. */
2052 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2053 && XVECLEN (newpat
, 0) == 2
2054 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2055 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2056 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2057 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2058 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2059 && asm_noperands (newpat
) < 0)
2061 newpat
= XVECEXP (newpat
, 0, 0);
2062 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2065 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2066 && XVECLEN (newpat
, 0) == 2
2067 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2068 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2069 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2070 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2071 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2072 && asm_noperands (newpat
) < 0)
2074 newpat
= XVECEXP (newpat
, 0, 1);
2075 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2078 /* If we were combining three insns and the result is a simple SET
2079 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2080 insns. There are two ways to do this. It can be split using a
2081 machine-specific method (like when you have an addition of a large
2082 constant) or by combine in the function find_split_point. */
2084 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2085 && asm_noperands (newpat
) < 0)
2087 rtx m_split
, *split
;
2088 rtx ni2dest
= i2dest
;
2090 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2091 use I2DEST as a scratch register will help. In the latter case,
2092 convert I2DEST to the mode of the source of NEWPAT if we can. */
2094 m_split
= split_insns (newpat
, i3
);
2096 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2097 inputs of NEWPAT. */
2099 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2100 possible to try that as a scratch reg. This would require adding
2101 more code to make it work though. */
2103 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2105 /* If I2DEST is a hard register or the only use of a pseudo,
2106 we can change its mode. */
2107 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2108 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2109 && GET_CODE (i2dest
) == REG
2110 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2111 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2112 && ! REG_USERVAR_P (i2dest
))))
2113 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2116 m_split
= split_insns (gen_rtx_PARALLEL
2118 gen_rtvec (2, newpat
,
2119 gen_rtx_CLOBBER (VOIDmode
,
2122 /* If the split with the mode-changed register didn't work, try
2123 the original register. */
2124 if (! m_split
&& ni2dest
!= i2dest
)
2127 m_split
= split_insns (gen_rtx_PARALLEL
2129 gen_rtvec (2, newpat
,
2130 gen_rtx_CLOBBER (VOIDmode
,
2136 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2138 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2139 if (insn_code_number
>= 0)
2142 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2143 && XVECLEN (m_split
, 0) == 2
2144 && (next_real_insn (i2
) == i3
2145 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2149 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2150 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2152 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2153 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2155 /* In case we changed the mode of I2DEST, replace it in the
2156 pseudo-register table here. We can't do it above in case this
2157 code doesn't get executed and we do a split the other way. */
2159 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2160 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2162 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2164 /* If I2 or I3 has multiple SETs, we won't know how to track
2165 register status, so don't use these insns. If I2's destination
2166 is used between I2 and I3, we also can't use these insns. */
2168 if (i2_code_number
>= 0 && i2set
&& i3set
2169 && (next_real_insn (i2
) == i3
2170 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2171 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2173 if (insn_code_number
>= 0)
2176 /* It is possible that both insns now set the destination of I3.
2177 If so, we must show an extra use of it. */
2179 if (insn_code_number
>= 0)
2181 rtx new_i3_dest
= SET_DEST (i3set
);
2182 rtx new_i2_dest
= SET_DEST (i2set
);
2184 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2185 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2186 || GET_CODE (new_i3_dest
) == SUBREG
)
2187 new_i3_dest
= XEXP (new_i3_dest
, 0);
2189 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2190 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2191 || GET_CODE (new_i2_dest
) == SUBREG
)
2192 new_i2_dest
= XEXP (new_i2_dest
, 0);
2194 if (GET_CODE (new_i3_dest
) == REG
2195 && GET_CODE (new_i2_dest
) == REG
2196 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2197 REG_N_SETS (REGNO (new_i2_dest
))++;
2201 /* If we can split it and use I2DEST, go ahead and see if that
2202 helps things be recognized. Verify that none of the registers
2203 are set between I2 and I3. */
2204 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2206 && GET_CODE (i2dest
) == REG
2208 /* We need I2DEST in the proper mode. If it is a hard register
2209 or the only use of a pseudo, we can change its mode. */
2210 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2211 || GET_MODE (*split
) == VOIDmode
2212 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2213 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2214 && ! REG_USERVAR_P (i2dest
)))
2215 && (next_real_insn (i2
) == i3
2216 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2217 /* We can't overwrite I2DEST if its value is still used by
2219 && ! reg_referenced_p (i2dest
, newpat
))
2221 rtx newdest
= i2dest
;
2222 enum rtx_code split_code
= GET_CODE (*split
);
2223 enum machine_mode split_mode
= GET_MODE (*split
);
2225 /* Get NEWDEST as a register in the proper mode. We have already
2226 validated that we can do this. */
2227 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2229 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2231 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2232 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2235 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2236 an ASHIFT. This can occur if it was inside a PLUS and hence
2237 appeared to be a memory address. This is a kludge. */
2238 if (split_code
== MULT
2239 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2240 && INTVAL (XEXP (*split
, 1)) > 0
2241 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2243 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2244 XEXP (*split
, 0), GEN_INT (i
)));
2245 /* Update split_code because we may not have a multiply
2247 split_code
= GET_CODE (*split
);
2250 #ifdef INSN_SCHEDULING
2251 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2252 be written as a ZERO_EXTEND. */
2253 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2254 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2255 SUBREG_REG (*split
)));
2258 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2259 SUBST (*split
, newdest
);
2260 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2262 /* If the split point was a MULT and we didn't have one before,
2263 don't use one now. */
2264 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2265 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2269 /* Check for a case where we loaded from memory in a narrow mode and
2270 then sign extended it, but we need both registers. In that case,
2271 we have a PARALLEL with both loads from the same memory location.
2272 We can split this into a load from memory followed by a register-register
2273 copy. This saves at least one insn, more if register allocation can
2276 We cannot do this if the destination of the second assignment is
2277 a register that we have already assumed is zero-extended. Similarly
2278 for a SUBREG of such a register. */
2280 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2281 && GET_CODE (newpat
) == PARALLEL
2282 && XVECLEN (newpat
, 0) == 2
2283 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2284 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2285 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2286 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2287 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2288 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2290 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2291 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2292 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2293 (GET_CODE (temp
) == REG
2294 && reg_nonzero_bits
[REGNO (temp
)] != 0
2295 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2296 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2297 && (reg_nonzero_bits
[REGNO (temp
)]
2298 != GET_MODE_MASK (word_mode
))))
2299 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2300 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2301 (GET_CODE (temp
) == REG
2302 && reg_nonzero_bits
[REGNO (temp
)] != 0
2303 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2304 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2305 && (reg_nonzero_bits
[REGNO (temp
)]
2306 != GET_MODE_MASK (word_mode
)))))
2307 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2308 SET_SRC (XVECEXP (newpat
, 0, 1)))
2309 && ! find_reg_note (i3
, REG_UNUSED
,
2310 SET_DEST (XVECEXP (newpat
, 0, 0))))
2314 newi2pat
= XVECEXP (newpat
, 0, 0);
2315 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2316 newpat
= XVECEXP (newpat
, 0, 1);
2317 SUBST (SET_SRC (newpat
),
2318 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2319 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2321 if (i2_code_number
>= 0)
2322 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2324 if (insn_code_number
>= 0)
2329 /* If we will be able to accept this, we have made a change to the
2330 destination of I3. This can invalidate a LOG_LINKS pointing
2331 to I3. No other part of combine.c makes such a transformation.
2333 The new I3 will have a destination that was previously the
2334 destination of I1 or I2 and which was used in i2 or I3. Call
2335 distribute_links to make a LOG_LINK from the next use of
2336 that destination. */
2338 PATTERN (i3
) = newpat
;
2339 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2341 /* I3 now uses what used to be its destination and which is
2342 now I2's destination. That means we need a LOG_LINK from
2343 I3 to I2. But we used to have one, so we still will.
2345 However, some later insn might be using I2's dest and have
2346 a LOG_LINK pointing at I3. We must remove this link.
2347 The simplest way to remove the link is to point it at I1,
2348 which we know will be a NOTE. */
2350 for (insn
= NEXT_INSN (i3
);
2351 insn
&& (this_basic_block
== n_basic_blocks
- 1
2352 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2353 insn
= NEXT_INSN (insn
))
2355 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2357 for (link
= LOG_LINKS (insn
); link
;
2358 link
= XEXP (link
, 1))
2359 if (XEXP (link
, 0) == i3
)
2360 XEXP (link
, 0) = i1
;
2368 /* Similarly, check for a case where we have a PARALLEL of two independent
2369 SETs but we started with three insns. In this case, we can do the sets
2370 as two separate insns. This case occurs when some SET allows two
2371 other insns to combine, but the destination of that SET is still live. */
2373 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2374 && GET_CODE (newpat
) == PARALLEL
2375 && XVECLEN (newpat
, 0) == 2
2376 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2379 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2380 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2381 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2382 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2384 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2385 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2387 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2388 XVECEXP (newpat
, 0, 0))
2389 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2390 XVECEXP (newpat
, 0, 1))
2391 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2392 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2394 /* Normally, it doesn't matter which of the two is done first,
2395 but it does if one references cc0. In that case, it has to
2398 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2400 newi2pat
= XVECEXP (newpat
, 0, 0);
2401 newpat
= XVECEXP (newpat
, 0, 1);
2406 newi2pat
= XVECEXP (newpat
, 0, 1);
2407 newpat
= XVECEXP (newpat
, 0, 0);
2410 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2412 if (i2_code_number
>= 0)
2413 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2416 /* If it still isn't recognized, fail and change things back the way they
2418 if ((insn_code_number
< 0
2419 /* Is the result a reasonable ASM_OPERANDS? */
2420 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2426 /* If we had to change another insn, make sure it is valid also. */
2427 if (undobuf
.other_insn
)
2429 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2430 rtx new_other_notes
;
2433 CLEAR_HARD_REG_SET (newpat_used_regs
);
2435 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2438 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2444 PATTERN (undobuf
.other_insn
) = other_pat
;
2446 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2447 are still valid. Then add any non-duplicate notes added by
2448 recog_for_combine. */
2449 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2451 next
= XEXP (note
, 1);
2453 if (REG_NOTE_KIND (note
) == REG_UNUSED
2454 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2456 if (GET_CODE (XEXP (note
, 0)) == REG
)
2457 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2459 remove_note (undobuf
.other_insn
, note
);
2463 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2464 if (GET_CODE (XEXP (note
, 0)) == REG
)
2465 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2467 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2468 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2471 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2472 they are adjacent to each other or not. */
2474 rtx p
= prev_nonnote_insn (i3
);
2475 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2476 && sets_cc0_p (newi2pat
))
2484 /* We now know that we can do this combination. Merge the insns and
2485 update the status of registers and LOG_LINKS. */
2488 rtx i3notes
, i2notes
, i1notes
= 0;
2489 rtx i3links
, i2links
, i1links
= 0;
2492 /* Compute which registers we expect to eliminate. newi2pat may be setting
2493 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2494 same as i3dest, in which case newi2pat may be setting i1dest. */
2495 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2496 || i2dest_in_i2src
|| i2dest_in_i1src
2498 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2499 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2502 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2504 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2505 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2507 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2509 /* Ensure that we do not have something that should not be shared but
2510 occurs multiple times in the new insns. Check this by first
2511 resetting all the `used' flags and then copying anything is shared. */
2513 reset_used_flags (i3notes
);
2514 reset_used_flags (i2notes
);
2515 reset_used_flags (i1notes
);
2516 reset_used_flags (newpat
);
2517 reset_used_flags (newi2pat
);
2518 if (undobuf
.other_insn
)
2519 reset_used_flags (PATTERN (undobuf
.other_insn
));
2521 i3notes
= copy_rtx_if_shared (i3notes
);
2522 i2notes
= copy_rtx_if_shared (i2notes
);
2523 i1notes
= copy_rtx_if_shared (i1notes
);
2524 newpat
= copy_rtx_if_shared (newpat
);
2525 newi2pat
= copy_rtx_if_shared (newi2pat
);
2526 if (undobuf
.other_insn
)
2527 reset_used_flags (PATTERN (undobuf
.other_insn
));
2529 INSN_CODE (i3
) = insn_code_number
;
2530 PATTERN (i3
) = newpat
;
2531 if (undobuf
.other_insn
)
2532 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2534 /* We had one special case above where I2 had more than one set and
2535 we replaced a destination of one of those sets with the destination
2536 of I3. In that case, we have to update LOG_LINKS of insns later
2537 in this basic block. Note that this (expensive) case is rare.
2539 Also, in this case, we must pretend that all REG_NOTEs for I2
2540 actually came from I3, so that REG_UNUSED notes from I2 will be
2541 properly handled. */
2543 if (i3_subst_into_i2
)
2545 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2546 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2547 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2548 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2549 && ! find_reg_note (i2
, REG_UNUSED
,
2550 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2551 for (temp
= NEXT_INSN (i2
);
2552 temp
&& (this_basic_block
== n_basic_blocks
- 1
2553 || BLOCK_HEAD (this_basic_block
) != temp
);
2554 temp
= NEXT_INSN (temp
))
2555 if (temp
!= i3
&& INSN_P (temp
))
2556 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2557 if (XEXP (link
, 0) == i2
)
2558 XEXP (link
, 0) = i3
;
2563 while (XEXP (link
, 1))
2564 link
= XEXP (link
, 1);
2565 XEXP (link
, 1) = i2notes
;
2579 INSN_CODE (i2
) = i2_code_number
;
2580 PATTERN (i2
) = newi2pat
;
2584 PUT_CODE (i2
, NOTE
);
2585 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2586 NOTE_SOURCE_FILE (i2
) = 0;
2593 PUT_CODE (i1
, NOTE
);
2594 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2595 NOTE_SOURCE_FILE (i1
) = 0;
2598 /* Get death notes for everything that is now used in either I3 or
2599 I2 and used to die in a previous insn. If we built two new
2600 patterns, move from I1 to I2 then I2 to I3 so that we get the
2601 proper movement on registers that I2 modifies. */
2605 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2606 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2609 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2612 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2614 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2617 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2620 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2623 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2626 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2627 know these are REG_UNUSED and want them to go to the desired insn,
2628 so we always pass it as i3. We have not counted the notes in
2629 reg_n_deaths yet, so we need to do so now. */
2631 if (newi2pat
&& new_i2_notes
)
2633 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2634 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2635 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2637 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2642 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2643 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2644 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2646 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2649 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2650 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2651 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2652 in that case, it might delete I2. Similarly for I2 and I1.
2653 Show an additional death due to the REG_DEAD note we make here. If
2654 we discard it in distribute_notes, we will decrement it again. */
2658 if (GET_CODE (i3dest_killed
) == REG
)
2659 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2661 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2662 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2664 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2668 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2672 if (i2dest_in_i2src
)
2674 if (GET_CODE (i2dest
) == REG
)
2675 REG_N_DEATHS (REGNO (i2dest
))++;
2677 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2679 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2682 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2683 NULL_RTX
, NULL_RTX
);
2686 if (i1dest_in_i1src
)
2688 if (GET_CODE (i1dest
) == REG
)
2689 REG_N_DEATHS (REGNO (i1dest
))++;
2691 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2692 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2693 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2695 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2696 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2697 NULL_RTX
, NULL_RTX
);
2700 distribute_links (i3links
);
2701 distribute_links (i2links
);
2702 distribute_links (i1links
);
2704 if (GET_CODE (i2dest
) == REG
)
2707 rtx i2_insn
= 0, i2_val
= 0, set
;
2709 /* The insn that used to set this register doesn't exist, and
2710 this life of the register may not exist either. See if one of
2711 I3's links points to an insn that sets I2DEST. If it does,
2712 that is now the last known value for I2DEST. If we don't update
2713 this and I2 set the register to a value that depended on its old
2714 contents, we will get confused. If this insn is used, thing
2715 will be set correctly in combine_instructions. */
2717 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2718 if ((set
= single_set (XEXP (link
, 0))) != 0
2719 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2720 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2722 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2724 /* If the reg formerly set in I2 died only once and that was in I3,
2725 zero its use count so it won't make `reload' do any work. */
2727 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2728 && ! i2dest_in_i2src
)
2730 regno
= REGNO (i2dest
);
2731 REG_N_SETS (regno
)--;
2735 if (i1
&& GET_CODE (i1dest
) == REG
)
2738 rtx i1_insn
= 0, i1_val
= 0, set
;
2740 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2741 if ((set
= single_set (XEXP (link
, 0))) != 0
2742 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2743 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2745 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2747 regno
= REGNO (i1dest
);
2748 if (! added_sets_1
&& ! i1dest_in_i1src
)
2749 REG_N_SETS (regno
)--;
2752 /* Update reg_nonzero_bits et al for any changes that may have been made
2753 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2754 important. Because newi2pat can affect nonzero_bits of newpat */
2756 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2757 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2759 /* Set new_direct_jump_p if a new return or simple jump instruction
2762 If I3 is now an unconditional jump, ensure that it has a
2763 BARRIER following it since it may have initially been a
2764 conditional jump. It may also be the last nonnote insn. */
2766 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
))
2768 *new_direct_jump_p
= 1;
2770 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2771 || GET_CODE (temp
) != BARRIER
)
2772 emit_barrier_after (i3
);
2774 /* An NOOP jump does not need barrier, but it does need cleaning up
2776 if (GET_CODE (newpat
) == SET
2777 && SET_SRC (newpat
) == pc_rtx
2778 && SET_DEST (newpat
) == pc_rtx
)
2779 *new_direct_jump_p
= 1;
2782 combine_successes
++;
2785 /* Clear this here, so that subsequent get_last_value calls are not
2787 subst_prev_insn
= NULL_RTX
;
2789 if (added_links_insn
2790 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2791 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2792 return added_links_insn
;
2794 return newi2pat
? i2
: i3
;
2797 /* Undo all the modifications recorded in undobuf. */
2802 struct undo
*undo
, *next
;
2804 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2808 *undo
->where
.i
= undo
->old_contents
.i
;
2810 *undo
->where
.r
= undo
->old_contents
.r
;
2812 undo
->next
= undobuf
.frees
;
2813 undobuf
.frees
= undo
;
2818 /* Clear this here, so that subsequent get_last_value calls are not
2820 subst_prev_insn
= NULL_RTX
;
2823 /* We've committed to accepting the changes we made. Move all
2824 of the undos to the free list. */
2829 struct undo
*undo
, *next
;
2831 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2834 undo
->next
= undobuf
.frees
;
2835 undobuf
.frees
= undo
;
2841 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2842 where we have an arithmetic expression and return that point. LOC will
2845 try_combine will call this function to see if an insn can be split into
2849 find_split_point (loc
, insn
)
2854 enum rtx_code code
= GET_CODE (x
);
2856 unsigned HOST_WIDE_INT len
= 0;
2857 HOST_WIDE_INT pos
= 0;
2859 rtx inner
= NULL_RTX
;
2861 /* First special-case some codes. */
2865 #ifdef INSN_SCHEDULING
2866 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2868 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2871 return find_split_point (&SUBREG_REG (x
), insn
);
2875 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2876 using LO_SUM and HIGH. */
2877 if (GET_CODE (XEXP (x
, 0)) == CONST
2878 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2881 gen_rtx_LO_SUM (Pmode
,
2882 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2884 return &XEXP (XEXP (x
, 0), 0);
2888 /* If we have a PLUS whose second operand is a constant and the
2889 address is not valid, perhaps will can split it up using
2890 the machine-specific way to split large constants. We use
2891 the first pseudo-reg (one of the virtual regs) as a placeholder;
2892 it will not remain in the result. */
2893 if (GET_CODE (XEXP (x
, 0)) == PLUS
2894 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2895 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2897 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2898 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2901 /* This should have produced two insns, each of which sets our
2902 placeholder. If the source of the second is a valid address,
2903 we can make put both sources together and make a split point
2906 if (seq
&& XVECLEN (seq
, 0) == 2
2907 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2908 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2909 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2910 && ! reg_mentioned_p (reg
,
2911 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2912 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2913 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2914 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2915 && memory_address_p (GET_MODE (x
),
2916 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2918 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2919 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2921 /* Replace the placeholder in SRC2 with SRC1. If we can
2922 find where in SRC2 it was placed, that can become our
2923 split point and we can replace this address with SRC2.
2924 Just try two obvious places. */
2926 src2
= replace_rtx (src2
, reg
, src1
);
2928 if (XEXP (src2
, 0) == src1
)
2929 split
= &XEXP (src2
, 0);
2930 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2931 && XEXP (XEXP (src2
, 0), 0) == src1
)
2932 split
= &XEXP (XEXP (src2
, 0), 0);
2936 SUBST (XEXP (x
, 0), src2
);
2941 /* If that didn't work, perhaps the first operand is complex and
2942 needs to be computed separately, so make a split point there.
2943 This will occur on machines that just support REG + CONST
2944 and have a constant moved through some previous computation. */
2946 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2947 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2948 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2950 return &XEXP (XEXP (x
, 0), 0);
2956 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2957 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2958 we need to put the operand into a register. So split at that
2961 if (SET_DEST (x
) == cc0_rtx
2962 && GET_CODE (SET_SRC (x
)) != COMPARE
2963 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2964 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2965 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2966 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2967 return &SET_SRC (x
);
2970 /* See if we can split SET_SRC as it stands. */
2971 split
= find_split_point (&SET_SRC (x
), insn
);
2972 if (split
&& split
!= &SET_SRC (x
))
2975 /* See if we can split SET_DEST as it stands. */
2976 split
= find_split_point (&SET_DEST (x
), insn
);
2977 if (split
&& split
!= &SET_DEST (x
))
2980 /* See if this is a bitfield assignment with everything constant. If
2981 so, this is an IOR of an AND, so split it into that. */
2982 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2983 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2984 <= HOST_BITS_PER_WIDE_INT
)
2985 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2986 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2987 && GET_CODE (SET_SRC (x
)) == CONST_INT
2988 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2989 + INTVAL (XEXP (SET_DEST (x
), 2)))
2990 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2991 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2993 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2994 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2995 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2996 rtx dest
= XEXP (SET_DEST (x
), 0);
2997 enum machine_mode mode
= GET_MODE (dest
);
2998 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3000 if (BITS_BIG_ENDIAN
)
3001 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3005 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3008 gen_binary (IOR
, mode
,
3009 gen_binary (AND
, mode
, dest
,
3010 GEN_INT (~(mask
<< pos
)
3011 & GET_MODE_MASK (mode
))),
3012 GEN_INT (src
<< pos
)));
3014 SUBST (SET_DEST (x
), dest
);
3016 split
= find_split_point (&SET_SRC (x
), insn
);
3017 if (split
&& split
!= &SET_SRC (x
))
3021 /* Otherwise, see if this is an operation that we can split into two.
3022 If so, try to split that. */
3023 code
= GET_CODE (SET_SRC (x
));
3028 /* If we are AND'ing with a large constant that is only a single
3029 bit and the result is only being used in a context where we
3030 need to know if it is zero or non-zero, replace it with a bit
3031 extraction. This will avoid the large constant, which might
3032 have taken more than one insn to make. If the constant were
3033 not a valid argument to the AND but took only one insn to make,
3034 this is no worse, but if it took more than one insn, it will
3037 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3038 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3039 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3040 && GET_CODE (SET_DEST (x
)) == REG
3041 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*)0)) != 0
3042 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3043 && XEXP (*split
, 0) == SET_DEST (x
)
3044 && XEXP (*split
, 1) == const0_rtx
)
3046 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3047 XEXP (SET_SRC (x
), 0),
3048 pos
, NULL_RTX
, 1, 1, 0, 0);
3049 if (extraction
!= 0)
3051 SUBST (SET_SRC (x
), extraction
);
3052 return find_split_point (loc
, insn
);
3058 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3059 is known to be on, this can be converted into a NEG of a shift. */
3060 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3061 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3062 && 1 <= (pos
= exact_log2
3063 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3064 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3066 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3070 gen_rtx_LSHIFTRT (mode
,
3071 XEXP (SET_SRC (x
), 0),
3074 split
= find_split_point (&SET_SRC (x
), insn
);
3075 if (split
&& split
!= &SET_SRC (x
))
3081 inner
= XEXP (SET_SRC (x
), 0);
3083 /* We can't optimize if either mode is a partial integer
3084 mode as we don't know how many bits are significant
3086 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3087 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3091 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3097 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3098 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3100 inner
= XEXP (SET_SRC (x
), 0);
3101 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3102 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3104 if (BITS_BIG_ENDIAN
)
3105 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3106 unsignedp
= (code
== ZERO_EXTRACT
);
3114 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3116 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3118 /* For unsigned, we have a choice of a shift followed by an
3119 AND or two shifts. Use two shifts for field sizes where the
3120 constant might be too large. We assume here that we can
3121 always at least get 8-bit constants in an AND insn, which is
3122 true for every current RISC. */
3124 if (unsignedp
&& len
<= 8)
3129 (mode
, gen_lowpart_for_combine (mode
, inner
),
3131 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3133 split
= find_split_point (&SET_SRC (x
), insn
);
3134 if (split
&& split
!= &SET_SRC (x
))
3141 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3142 gen_rtx_ASHIFT (mode
,
3143 gen_lowpart_for_combine (mode
, inner
),
3144 GEN_INT (GET_MODE_BITSIZE (mode
)
3146 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3148 split
= find_split_point (&SET_SRC (x
), insn
);
3149 if (split
&& split
!= &SET_SRC (x
))
3154 /* See if this is a simple operation with a constant as the second
3155 operand. It might be that this constant is out of range and hence
3156 could be used as a split point. */
3157 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3158 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3159 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3160 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3161 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3162 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3163 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3165 return &XEXP (SET_SRC (x
), 1);
3167 /* Finally, see if this is a simple operation with its first operand
3168 not in a register. The operation might require this operand in a
3169 register, so return it as a split point. We can always do this
3170 because if the first operand were another operation, we would have
3171 already found it as a split point. */
3172 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3173 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3174 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3175 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3176 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3177 return &XEXP (SET_SRC (x
), 0);
3183 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3184 it is better to write this as (not (ior A B)) so we can split it.
3185 Similarly for IOR. */
3186 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3189 gen_rtx_NOT (GET_MODE (x
),
3190 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3192 XEXP (XEXP (x
, 0), 0),
3193 XEXP (XEXP (x
, 1), 0))));
3194 return find_split_point (loc
, insn
);
3197 /* Many RISC machines have a large set of logical insns. If the
3198 second operand is a NOT, put it first so we will try to split the
3199 other operand first. */
3200 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3202 rtx tem
= XEXP (x
, 0);
3203 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3204 SUBST (XEXP (x
, 1), tem
);
3212 /* Otherwise, select our actions depending on our rtx class. */
3213 switch (GET_RTX_CLASS (code
))
3215 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3217 split
= find_split_point (&XEXP (x
, 2), insn
);
3220 /* ... fall through ... */
3224 split
= find_split_point (&XEXP (x
, 1), insn
);
3227 /* ... fall through ... */
3229 /* Some machines have (and (shift ...) ...) insns. If X is not
3230 an AND, but XEXP (X, 0) is, use it as our split point. */
3231 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3232 return &XEXP (x
, 0);
3234 split
= find_split_point (&XEXP (x
, 0), insn
);
3240 /* Otherwise, we don't have a split point. */
3244 /* Throughout X, replace FROM with TO, and return the result.
3245 The result is TO if X is FROM;
3246 otherwise the result is X, but its contents may have been modified.
3247 If they were modified, a record was made in undobuf so that
3248 undo_all will (among other things) return X to its original state.
3250 If the number of changes necessary is too much to record to undo,
3251 the excess changes are not made, so the result is invalid.
3252 The changes already made can still be undone.
3253 undobuf.num_undo is incremented for such changes, so by testing that
3254 the caller can tell whether the result is valid.
3256 `n_occurrences' is incremented each time FROM is replaced.
3258 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3260 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3261 by copying if `n_occurrences' is non-zero. */
3264 subst (x
, from
, to
, in_dest
, unique_copy
)
3265 register rtx x
, from
, to
;
3269 register enum rtx_code code
= GET_CODE (x
);
3270 enum machine_mode op0_mode
= VOIDmode
;
3271 register const char *fmt
;
3272 register int len
, i
;
3275 /* Two expressions are equal if they are identical copies of a shared
3276 RTX or if they are both registers with the same register number
3279 #define COMBINE_RTX_EQUAL_P(X,Y) \
3281 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3282 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3284 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3287 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3290 /* If X and FROM are the same register but different modes, they will
3291 not have been seen as equal above. However, flow.c will make a
3292 LOG_LINKS entry for that case. If we do nothing, we will try to
3293 rerecognize our original insn and, when it succeeds, we will
3294 delete the feeding insn, which is incorrect.
3296 So force this insn not to match in this (rare) case. */
3297 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3298 && REGNO (x
) == REGNO (from
))
3299 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3301 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3302 of which may contain things that can be combined. */
3303 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3306 /* It is possible to have a subexpression appear twice in the insn.
3307 Suppose that FROM is a register that appears within TO.
3308 Then, after that subexpression has been scanned once by `subst',
3309 the second time it is scanned, TO may be found. If we were
3310 to scan TO here, we would find FROM within it and create a
3311 self-referent rtl structure which is completely wrong. */
3312 if (COMBINE_RTX_EQUAL_P (x
, to
))
3315 /* Parallel asm_operands need special attention because all of the
3316 inputs are shared across the arms. Furthermore, unsharing the
3317 rtl results in recognition failures. Failure to handle this case
3318 specially can result in circular rtl.
3320 Solve this by doing a normal pass across the first entry of the
3321 parallel, and only processing the SET_DESTs of the subsequent
3324 if (code
== PARALLEL
3325 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3326 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3328 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3330 /* If this substitution failed, this whole thing fails. */
3331 if (GET_CODE (new) == CLOBBER
3332 && XEXP (new, 0) == const0_rtx
)
3335 SUBST (XVECEXP (x
, 0, 0), new);
3337 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3339 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3341 if (GET_CODE (dest
) != REG
3342 && GET_CODE (dest
) != CC0
3343 && GET_CODE (dest
) != PC
)
3345 new = subst (dest
, from
, to
, 0, unique_copy
);
3347 /* If this substitution failed, this whole thing fails. */
3348 if (GET_CODE (new) == CLOBBER
3349 && XEXP (new, 0) == const0_rtx
)
3352 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3358 len
= GET_RTX_LENGTH (code
);
3359 fmt
= GET_RTX_FORMAT (code
);
3361 /* We don't need to process a SET_DEST that is a register, CC0,
3362 or PC, so set up to skip this common case. All other cases
3363 where we want to suppress replacing something inside a
3364 SET_SRC are handled via the IN_DEST operand. */
3366 && (GET_CODE (SET_DEST (x
)) == REG
3367 || GET_CODE (SET_DEST (x
)) == CC0
3368 || GET_CODE (SET_DEST (x
)) == PC
))
3371 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3374 op0_mode
= GET_MODE (XEXP (x
, 0));
3376 for (i
= 0; i
< len
; i
++)
3381 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3383 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3385 new = (unique_copy
&& n_occurrences
3386 ? copy_rtx (to
) : to
);
3391 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3394 /* If this substitution failed, this whole thing
3396 if (GET_CODE (new) == CLOBBER
3397 && XEXP (new, 0) == const0_rtx
)
3401 SUBST (XVECEXP (x
, i
, j
), new);
3404 else if (fmt
[i
] == 'e')
3406 /* If this is a register being set, ignore it. */
3409 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3410 || code
== ZERO_EXTRACT
)
3412 && GET_CODE (new) == REG
)
3415 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3417 /* In general, don't install a subreg involving two
3418 modes not tieable. It can worsen register
3419 allocation, and can even make invalid reload
3420 insns, since the reg inside may need to be copied
3421 from in the outside mode, and that may be invalid
3422 if it is an fp reg copied in integer mode.
3424 We allow two exceptions to this: It is valid if
3425 it is inside another SUBREG and the mode of that
3426 SUBREG and the mode of the inside of TO is
3427 tieable and it is valid if X is a SET that copies
3430 if (GET_CODE (to
) == SUBREG
3431 && ! MODES_TIEABLE_P (GET_MODE (to
),
3432 GET_MODE (SUBREG_REG (to
)))
3433 && ! (code
== SUBREG
3434 && MODES_TIEABLE_P (GET_MODE (x
),
3435 GET_MODE (SUBREG_REG (to
))))
3437 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3440 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3442 #ifdef CLASS_CANNOT_CHANGE_MODE
3444 && GET_CODE (to
) == REG
3445 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3446 && (TEST_HARD_REG_BIT
3447 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3449 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3451 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3454 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3458 /* If we are in a SET_DEST, suppress most cases unless we
3459 have gone inside a MEM, in which case we want to
3460 simplify the address. We assume here that things that
3461 are actually part of the destination have their inner
3462 parts in the first expression. This is true for SUBREG,
3463 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3464 things aside from REG and MEM that should appear in a
3466 new = subst (XEXP (x
, i
), from
, to
,
3468 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3469 || code
== ZERO_EXTRACT
))
3471 && i
== 0), unique_copy
);
3473 /* If we found that we will have to reject this combination,
3474 indicate that by returning the CLOBBER ourselves, rather than
3475 an expression containing it. This will speed things up as
3476 well as prevent accidents where two CLOBBERs are considered
3477 to be equal, thus producing an incorrect simplification. */
3479 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3482 SUBST (XEXP (x
, i
), new);
3487 /* Try to simplify X. If the simplification changed the code, it is likely
3488 that further simplification will help, so loop, but limit the number
3489 of repetitions that will be performed. */
3491 for (i
= 0; i
< 4; i
++)
3493 /* If X is sufficiently simple, don't bother trying to do anything
3495 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3496 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3498 if (GET_CODE (x
) == code
)
3501 code
= GET_CODE (x
);
3503 /* We no longer know the original mode of operand 0 since we
3504 have changed the form of X) */
3505 op0_mode
= VOIDmode
;
3511 /* Simplify X, a piece of RTL. We just operate on the expression at the
3512 outer level; call `subst' to simplify recursively. Return the new
3515 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3516 will be the iteration even if an expression with a code different from
3517 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3520 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3522 enum machine_mode op0_mode
;
3526 enum rtx_code code
= GET_CODE (x
);
3527 enum machine_mode mode
= GET_MODE (x
);
3532 /* If this is a commutative operation, put a constant last and a complex
3533 expression first. We don't need to do this for comparisons here. */
3534 if (GET_RTX_CLASS (code
) == 'c'
3535 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3538 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3539 SUBST (XEXP (x
, 1), temp
);
3542 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3543 sign extension of a PLUS with a constant, reverse the order of the sign
3544 extension and the addition. Note that this not the same as the original
3545 code, but overflow is undefined for signed values. Also note that the
3546 PLUS will have been partially moved "inside" the sign-extension, so that
3547 the first operand of X will really look like:
3548 (ashiftrt (plus (ashift A C4) C5) C4).
3550 (plus (ashiftrt (ashift A C4) C2) C4)
3551 and replace the first operand of X with that expression. Later parts
3552 of this function may simplify the expression further.
3554 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3555 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3556 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3558 We do this to simplify address expressions. */
3560 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3561 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3562 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3563 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3564 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3565 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3566 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3567 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3568 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3569 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3570 XEXP (XEXP (x
, 0), 1))) != 0)
3573 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3574 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3575 INTVAL (XEXP (XEXP (x
, 0), 1)));
3577 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3578 INTVAL (XEXP (XEXP (x
, 0), 1)));
3580 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3583 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3584 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3585 things. Check for cases where both arms are testing the same
3588 Don't do anything if all operands are very simple. */
3590 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3591 || GET_RTX_CLASS (code
) == '<')
3592 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3593 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3594 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3596 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3597 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3598 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3600 || (GET_RTX_CLASS (code
) == '1'
3601 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3602 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3603 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3606 rtx cond
, true_rtx
, false_rtx
;
3608 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3610 /* If everything is a comparison, what we have is highly unlikely
3611 to be simpler, so don't use it. */
3612 && ! (GET_RTX_CLASS (code
) == '<'
3613 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3614 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3616 rtx cop1
= const0_rtx
;
3617 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3619 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3622 /* Simplify the alternative arms; this may collapse the true and
3623 false arms to store-flag values. */
3624 true_rtx
= subst (true_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3625 false_rtx
= subst (false_rtx
, pc_rtx
, pc_rtx
, 0, 0);
3627 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3628 is unlikely to be simpler. */
3629 if (general_operand (true_rtx
, VOIDmode
)
3630 && general_operand (false_rtx
, VOIDmode
))
3632 /* Restarting if we generate a store-flag expression will cause
3633 us to loop. Just drop through in this case. */
3635 /* If the result values are STORE_FLAG_VALUE and zero, we can
3636 just make the comparison operation. */
3637 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3638 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3639 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3640 && reverse_condition (cond_code
) != UNKNOWN
)
3641 x
= gen_binary (reverse_condition (cond_code
),
3644 /* Likewise, we can make the negate of a comparison operation
3645 if the result values are - STORE_FLAG_VALUE and zero. */
3646 else if (GET_CODE (true_rtx
) == CONST_INT
3647 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3648 && false_rtx
== const0_rtx
)
3649 x
= simplify_gen_unary (NEG
, mode
,
3650 gen_binary (cond_code
, mode
, cond
,
3653 else if (GET_CODE (false_rtx
) == CONST_INT
3654 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3655 && true_rtx
== const0_rtx
)
3656 x
= simplify_gen_unary (NEG
, mode
,
3657 gen_binary (reverse_condition
3662 return gen_rtx_IF_THEN_ELSE (mode
,
3663 gen_binary (cond_code
, VOIDmode
,
3665 true_rtx
, false_rtx
);
3667 code
= GET_CODE (x
);
3668 op0_mode
= VOIDmode
;
3673 /* Try to fold this expression in case we have constants that weren't
3676 switch (GET_RTX_CLASS (code
))
3679 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3683 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3684 if (cmp_mode
== VOIDmode
)
3686 cmp_mode
= GET_MODE (XEXP (x
, 1));
3687 if (cmp_mode
== VOIDmode
)
3688 cmp_mode
= op0_mode
;
3690 temp
= simplify_relational_operation (code
, cmp_mode
,
3691 XEXP (x
, 0), XEXP (x
, 1));
3693 #ifdef FLOAT_STORE_FLAG_VALUE
3694 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3696 if (temp
== const0_rtx
)
3697 temp
= CONST0_RTX (mode
);
3699 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3705 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3709 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3710 XEXP (x
, 1), XEXP (x
, 2));
3717 code
= GET_CODE (temp
);
3718 op0_mode
= VOIDmode
;
3719 mode
= GET_MODE (temp
);
3722 /* First see if we can apply the inverse distributive law. */
3723 if (code
== PLUS
|| code
== MINUS
3724 || code
== AND
|| code
== IOR
|| code
== XOR
)
3726 x
= apply_distributive_law (x
);
3727 code
= GET_CODE (x
);
3728 op0_mode
= VOIDmode
;
3731 /* If CODE is an associative operation not otherwise handled, see if we
3732 can associate some operands. This can win if they are constants or
3733 if they are logically related (i.e. (a & b) & a). */
3734 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3735 || code
== AND
|| code
== IOR
|| code
== XOR
3736 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3737 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3738 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3740 if (GET_CODE (XEXP (x
, 0)) == code
)
3742 rtx other
= XEXP (XEXP (x
, 0), 0);
3743 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3744 rtx inner_op1
= XEXP (x
, 1);
3747 /* Make sure we pass the constant operand if any as the second
3748 one if this is a commutative operation. */
3749 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3751 rtx tem
= inner_op0
;
3752 inner_op0
= inner_op1
;
3755 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3756 : code
== DIV
? MULT
3758 mode
, inner_op0
, inner_op1
);
3760 /* For commutative operations, try the other pair if that one
3762 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3764 other
= XEXP (XEXP (x
, 0), 1);
3765 inner
= simplify_binary_operation (code
, mode
,
3766 XEXP (XEXP (x
, 0), 0),
3771 return gen_binary (code
, mode
, other
, inner
);
3775 /* A little bit of algebraic simplification here. */
3779 /* Ensure that our address has any ASHIFTs converted to MULT in case
3780 address-recognizing predicates are called later. */
3781 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3782 SUBST (XEXP (x
, 0), temp
);
3786 if (op0_mode
== VOIDmode
)
3787 op0_mode
= GET_MODE (SUBREG_REG (x
));
3789 /* simplify_subreg can't use gen_lowpart_for_combine. */
3790 if (CONSTANT_P (SUBREG_REG (x
))
3791 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
))
3792 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3796 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3802 /* Note that we cannot do any narrowing for non-constants since
3803 we might have been counting on using the fact that some bits were
3804 zero. We now do this in the SET. */
3809 /* (not (plus X -1)) can become (neg X). */
3810 if (GET_CODE (XEXP (x
, 0)) == PLUS
3811 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3812 return gen_rtx_NEG (mode
, XEXP (XEXP (x
, 0), 0));
3814 /* Similarly, (not (neg X)) is (plus X -1). */
3815 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3816 return gen_rtx_PLUS (mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3818 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3819 if (GET_CODE (XEXP (x
, 0)) == XOR
3820 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3821 && (temp
= simplify_unary_operation (NOT
, mode
,
3822 XEXP (XEXP (x
, 0), 1),
3824 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3826 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3827 other than 1, but that is not valid. We could do a similar
3828 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3829 but this doesn't seem common enough to bother with. */
3830 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3831 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3832 return gen_rtx_ROTATE (mode
, simplify_gen_unary (NOT
, mode
,
3834 XEXP (XEXP (x
, 0), 1));
3836 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3837 && subreg_lowpart_p (XEXP (x
, 0))
3838 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3839 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3840 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3841 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3843 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3845 x
= gen_rtx_ROTATE (inner_mode
,
3846 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3848 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3849 return gen_lowpart_for_combine (mode
, x
);
3852 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3853 reversing the comparison code if valid. */
3854 if (STORE_FLAG_VALUE
== -1
3855 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3856 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3857 XEXP (XEXP (x
, 0), 1))))
3860 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3861 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3862 perform the above simplification. */
3864 if (STORE_FLAG_VALUE
== -1
3865 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3866 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3867 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3868 return gen_rtx_GE (mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3870 /* Apply De Morgan's laws to reduce number of patterns for machines
3871 with negating logical insns (and-not, nand, etc.). If result has
3872 only one NOT, put it first, since that is how the patterns are
3875 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3877 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3878 enum machine_mode op_mode
;
3880 op_mode
= GET_MODE (in1
);
3881 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3883 op_mode
= GET_MODE (in2
);
3884 if (op_mode
== VOIDmode
)
3886 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3888 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3891 in2
= in1
; in1
= tem
;
3894 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3900 /* (neg (plus X 1)) can become (not X). */
3901 if (GET_CODE (XEXP (x
, 0)) == PLUS
3902 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3903 return gen_rtx_NOT (mode
, XEXP (XEXP (x
, 0), 0));
3905 /* Similarly, (neg (not X)) is (plus X 1). */
3906 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3907 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3909 /* (neg (minus X Y)) can become (minus Y X). */
3910 if (GET_CODE (XEXP (x
, 0)) == MINUS
3911 && (! FLOAT_MODE_P (mode
)
3912 /* x-y != -(y-x) with IEEE floating point. */
3913 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3914 || flag_unsafe_math_optimizations
))
3915 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3916 XEXP (XEXP (x
, 0), 0));
3918 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3919 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3920 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3921 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3923 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3924 if we can then eliminate the NEG (e.g.,
3925 if the operand is a constant). */
3927 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3929 temp
= simplify_unary_operation (NEG
, mode
,
3930 XEXP (XEXP (x
, 0), 0), mode
);
3932 return gen_binary (ASHIFT
, mode
, temp
, XEXP (XEXP (x
, 0), 1));
3935 temp
= expand_compound_operation (XEXP (x
, 0));
3937 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3938 replaced by (lshiftrt X C). This will convert
3939 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3941 if (GET_CODE (temp
) == ASHIFTRT
3942 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3943 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3944 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3945 INTVAL (XEXP (temp
, 1)));
3947 /* If X has only a single bit that might be nonzero, say, bit I, convert
3948 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3949 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3950 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3951 or a SUBREG of one since we'd be making the expression more
3952 complex if it was just a register. */
3954 if (GET_CODE (temp
) != REG
3955 && ! (GET_CODE (temp
) == SUBREG
3956 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3957 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3959 rtx temp1
= simplify_shift_const
3960 (NULL_RTX
, ASHIFTRT
, mode
,
3961 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3962 GET_MODE_BITSIZE (mode
) - 1 - i
),
3963 GET_MODE_BITSIZE (mode
) - 1 - i
);
3965 /* If all we did was surround TEMP with the two shifts, we
3966 haven't improved anything, so don't use it. Otherwise,
3967 we are better off with TEMP1. */
3968 if (GET_CODE (temp1
) != ASHIFTRT
3969 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3970 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3976 /* We can't handle truncation to a partial integer mode here
3977 because we don't know the real bitsize of the partial
3979 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3982 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3983 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3984 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3986 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3987 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3989 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3990 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3991 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3992 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3993 return XEXP (XEXP (x
, 0), 0);
3995 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3996 (OP:SI foo:SI) if OP is NEG or ABS. */
3997 if ((GET_CODE (XEXP (x
, 0)) == ABS
3998 || GET_CODE (XEXP (x
, 0)) == NEG
)
3999 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4000 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4001 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4002 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4003 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4005 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4007 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4008 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4009 && subreg_lowpart_p (XEXP (x
, 0)))
4010 return SUBREG_REG (XEXP (x
, 0));
4012 /* If we know that the value is already truncated, we can
4013 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4014 is nonzero for the corresponding modes. But don't do this
4015 for an (LSHIFTRT (MULT ...)) since this will cause problems
4016 with the umulXi3_highpart patterns. */
4017 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4018 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4019 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4020 >= GET_MODE_BITSIZE (mode
) + 1
4021 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4022 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4023 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4025 /* A truncate of a comparison can be replaced with a subreg if
4026 STORE_FLAG_VALUE permits. This is like the previous test,
4027 but it works even if the comparison is done in a mode larger
4028 than HOST_BITS_PER_WIDE_INT. */
4029 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4030 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4031 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4032 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4034 /* Similarly, a truncate of a register whose value is a
4035 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4037 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4038 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4039 && (temp
= get_last_value (XEXP (x
, 0)))
4040 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4041 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4045 case FLOAT_TRUNCATE
:
4046 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4047 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4048 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4049 return XEXP (XEXP (x
, 0), 0);
4051 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4052 (OP:SF foo:SF) if OP is NEG or ABS. */
4053 if ((GET_CODE (XEXP (x
, 0)) == ABS
4054 || GET_CODE (XEXP (x
, 0)) == NEG
)
4055 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4056 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4057 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4058 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4060 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4061 is (float_truncate:SF x). */
4062 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4063 && subreg_lowpart_p (XEXP (x
, 0))
4064 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4065 return SUBREG_REG (XEXP (x
, 0));
4070 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4071 using cc0, in which case we want to leave it as a COMPARE
4072 so we can distinguish it from a register-register-copy. */
4073 if (XEXP (x
, 1) == const0_rtx
)
4076 /* In IEEE floating point, x-0 is not the same as x. */
4077 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4078 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4079 || flag_unsafe_math_optimizations
)
4080 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4086 /* (const (const X)) can become (const X). Do it this way rather than
4087 returning the inner CONST since CONST can be shared with a
4089 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4090 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4095 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4096 can add in an offset. find_split_point will split this address up
4097 again if it doesn't match. */
4098 if (GET_CODE (XEXP (x
, 0)) == HIGH
4099 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4105 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4106 outermost. That's because that's the way indexed addresses are
4107 supposed to appear. This code used to check many more cases, but
4108 they are now checked elsewhere. */
4109 if (GET_CODE (XEXP (x
, 0)) == PLUS
4110 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4111 return gen_binary (PLUS
, mode
,
4112 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4114 XEXP (XEXP (x
, 0), 1));
4116 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4117 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4118 bit-field and can be replaced by either a sign_extend or a
4119 sign_extract. The `and' may be a zero_extend and the two
4120 <c>, -<c> constants may be reversed. */
4121 if (GET_CODE (XEXP (x
, 0)) == XOR
4122 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4123 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4124 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4125 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4126 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4127 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4128 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4129 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4130 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4131 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4132 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4133 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4134 == (unsigned int) i
+ 1))))
4135 return simplify_shift_const
4136 (NULL_RTX
, ASHIFTRT
, mode
,
4137 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4138 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4139 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4140 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4142 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4143 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4144 is 1. This produces better code than the alternative immediately
4146 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4147 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4148 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4149 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4150 XEXP (XEXP (x
, 0), 0),
4151 XEXP (XEXP (x
, 0), 1))))
4153 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4155 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4156 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4157 the bitsize of the mode - 1. This allows simplification of
4158 "a = (b & 8) == 0;" */
4159 if (XEXP (x
, 1) == constm1_rtx
4160 && GET_CODE (XEXP (x
, 0)) != REG
4161 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4162 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4163 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4164 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4165 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4166 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4167 GET_MODE_BITSIZE (mode
) - 1),
4168 GET_MODE_BITSIZE (mode
) - 1);
4170 /* If we are adding two things that have no bits in common, convert
4171 the addition into an IOR. This will often be further simplified,
4172 for example in cases like ((a & 1) + (a & 2)), which can
4175 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4176 && (nonzero_bits (XEXP (x
, 0), mode
)
4177 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4179 /* Try to simplify the expression further. */
4180 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4181 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4183 /* If we could, great. If not, do not go ahead with the IOR
4184 replacement, since PLUS appears in many special purpose
4185 address arithmetic instructions. */
4186 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4192 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4193 by reversing the comparison code if valid. */
4194 if (STORE_FLAG_VALUE
== 1
4195 && XEXP (x
, 0) == const1_rtx
4196 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4197 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4198 XEXP (XEXP (x
, 1), 0),
4199 XEXP (XEXP (x
, 1), 1))))
4202 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4203 (and <foo> (const_int pow2-1)) */
4204 if (GET_CODE (XEXP (x
, 1)) == AND
4205 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4206 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4207 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4208 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4209 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4211 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4213 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4214 return gen_binary (MINUS
, mode
,
4215 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4216 XEXP (XEXP (x
, 1), 0)),
4217 XEXP (XEXP (x
, 1), 1));
4221 /* If we have (mult (plus A B) C), apply the distributive law and then
4222 the inverse distributive law to see if things simplify. This
4223 occurs mostly in addresses, often when unrolling loops. */
4225 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4227 x
= apply_distributive_law
4228 (gen_binary (PLUS
, mode
,
4229 gen_binary (MULT
, mode
,
4230 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4231 gen_binary (MULT
, mode
,
4232 XEXP (XEXP (x
, 0), 1),
4233 copy_rtx (XEXP (x
, 1)))));
4235 if (GET_CODE (x
) != MULT
)
4238 /* Try simplify a*(b/c) as (a*b)/c. */
4239 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4240 && GET_CODE (XEXP (x
, 0)) == DIV
)
4242 rtx tem
= simplify_binary_operation (MULT
, mode
,
4243 XEXP (XEXP (x
, 0), 0),
4246 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4251 /* If this is a divide by a power of two, treat it as a shift if
4252 its first operand is a shift. */
4253 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4254 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4255 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4256 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4257 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4258 || GET_CODE (XEXP (x
, 0)) == ROTATE
4259 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4260 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4264 case GT
: case GTU
: case GE
: case GEU
:
4265 case LT
: case LTU
: case LE
: case LEU
:
4266 case UNEQ
: case LTGT
:
4267 case UNGT
: case UNGE
:
4268 case UNLT
: case UNLE
:
4269 case UNORDERED
: case ORDERED
:
4270 /* If the first operand is a condition code, we can't do anything
4272 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4273 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4275 && XEXP (x
, 0) != cc0_rtx
4279 rtx op0
= XEXP (x
, 0);
4280 rtx op1
= XEXP (x
, 1);
4281 enum rtx_code new_code
;
4283 if (GET_CODE (op0
) == COMPARE
)
4284 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4286 /* Simplify our comparison, if possible. */
4287 new_code
= simplify_comparison (code
, &op0
, &op1
);
4289 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4290 if only the low-order bit is possibly nonzero in X (such as when
4291 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4292 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4293 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4296 Remove any ZERO_EXTRACT we made when thinking this was a
4297 comparison. It may now be simpler to use, e.g., an AND. If a
4298 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4299 the call to make_compound_operation in the SET case. */
4301 if (STORE_FLAG_VALUE
== 1
4302 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4303 && op1
== const0_rtx
4304 && mode
== GET_MODE (op0
)
4305 && nonzero_bits (op0
, mode
) == 1)
4306 return gen_lowpart_for_combine (mode
,
4307 expand_compound_operation (op0
));
4309 else if (STORE_FLAG_VALUE
== 1
4310 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4311 && op1
== const0_rtx
4312 && mode
== GET_MODE (op0
)
4313 && (num_sign_bit_copies (op0
, mode
)
4314 == GET_MODE_BITSIZE (mode
)))
4316 op0
= expand_compound_operation (op0
);
4317 return simplify_gen_unary (NEG
, mode
,
4318 gen_lowpart_for_combine (mode
, op0
),
4322 else if (STORE_FLAG_VALUE
== 1
4323 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4324 && op1
== const0_rtx
4325 && mode
== GET_MODE (op0
)
4326 && nonzero_bits (op0
, mode
) == 1)
4328 op0
= expand_compound_operation (op0
);
4329 return gen_binary (XOR
, mode
,
4330 gen_lowpart_for_combine (mode
, op0
),
4334 else if (STORE_FLAG_VALUE
== 1
4335 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4336 && op1
== const0_rtx
4337 && mode
== GET_MODE (op0
)
4338 && (num_sign_bit_copies (op0
, mode
)
4339 == GET_MODE_BITSIZE (mode
)))
4341 op0
= expand_compound_operation (op0
);
4342 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4345 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4347 if (STORE_FLAG_VALUE
== -1
4348 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4349 && op1
== const0_rtx
4350 && (num_sign_bit_copies (op0
, mode
)
4351 == GET_MODE_BITSIZE (mode
)))
4352 return gen_lowpart_for_combine (mode
,
4353 expand_compound_operation (op0
));
4355 else if (STORE_FLAG_VALUE
== -1
4356 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4357 && op1
== const0_rtx
4358 && mode
== GET_MODE (op0
)
4359 && nonzero_bits (op0
, mode
) == 1)
4361 op0
= expand_compound_operation (op0
);
4362 return simplify_gen_unary (NEG
, mode
,
4363 gen_lowpart_for_combine (mode
, op0
),
4367 else if (STORE_FLAG_VALUE
== -1
4368 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4369 && op1
== const0_rtx
4370 && mode
== GET_MODE (op0
)
4371 && (num_sign_bit_copies (op0
, mode
)
4372 == GET_MODE_BITSIZE (mode
)))
4374 op0
= expand_compound_operation (op0
);
4375 return simplify_gen_unary (NOT
, mode
,
4376 gen_lowpart_for_combine (mode
, op0
),
4380 /* If X is 0/1, (eq X 0) is X-1. */
4381 else if (STORE_FLAG_VALUE
== -1
4382 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4383 && op1
== const0_rtx
4384 && mode
== GET_MODE (op0
)
4385 && nonzero_bits (op0
, mode
) == 1)
4387 op0
= expand_compound_operation (op0
);
4388 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4391 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4392 one bit that might be nonzero, we can convert (ne x 0) to
4393 (ashift x c) where C puts the bit in the sign bit. Remove any
4394 AND with STORE_FLAG_VALUE when we are done, since we are only
4395 going to test the sign bit. */
4396 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4397 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4398 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4399 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4400 && op1
== const0_rtx
4401 && mode
== GET_MODE (op0
)
4402 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4404 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4405 expand_compound_operation (op0
),
4406 GET_MODE_BITSIZE (mode
) - 1 - i
);
4407 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4413 /* If the code changed, return a whole new comparison. */
4414 if (new_code
!= code
)
4415 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4417 /* Otherwise, keep this operation, but maybe change its operands.
4418 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4419 SUBST (XEXP (x
, 0), op0
);
4420 SUBST (XEXP (x
, 1), op1
);
4425 return simplify_if_then_else (x
);
4431 /* If we are processing SET_DEST, we are done. */
4435 return expand_compound_operation (x
);
4438 return simplify_set (x
);
4443 return simplify_logical (x
, last
);
4446 /* (abs (neg <foo>)) -> (abs <foo>) */
4447 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4448 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4450 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4452 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4455 /* If operand is something known to be positive, ignore the ABS. */
4456 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4457 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4458 <= HOST_BITS_PER_WIDE_INT
)
4459 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4460 & ((HOST_WIDE_INT
) 1
4461 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4465 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4466 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4467 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4472 /* (ffs (*_extend <X>)) = (ffs <X>) */
4473 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4474 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4475 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4479 /* (float (sign_extend <X>)) = (float <X>). */
4480 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4481 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4489 /* If this is a shift by a constant amount, simplify it. */
4490 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4491 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4492 INTVAL (XEXP (x
, 1)));
4494 #ifdef SHIFT_COUNT_TRUNCATED
4495 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4497 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4499 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4508 rtx op0
= XEXP (x
, 0);
4509 rtx op1
= XEXP (x
, 1);
4512 if (GET_CODE (op1
) != PARALLEL
)
4514 len
= XVECLEN (op1
, 0);
4516 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4517 && GET_CODE (op0
) == VEC_CONCAT
)
4519 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4521 /* Try to find the element in the VEC_CONCAT. */
4524 if (GET_MODE (op0
) == GET_MODE (x
))
4526 if (GET_CODE (op0
) == VEC_CONCAT
)
4528 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4529 if (op0_size
< offset
)
4530 op0
= XEXP (op0
, 0);
4534 op0
= XEXP (op0
, 1);
4552 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4555 simplify_if_then_else (x
)
4558 enum machine_mode mode
= GET_MODE (x
);
4559 rtx cond
= XEXP (x
, 0);
4560 rtx true_rtx
= XEXP (x
, 1);
4561 rtx false_rtx
= XEXP (x
, 2);
4562 enum rtx_code true_code
= GET_CODE (cond
);
4563 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4566 enum rtx_code false_code
;
4569 /* Simplify storing of the truth value. */
4570 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4571 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4573 /* Also when the truth value has to be reversed. */
4575 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4576 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4580 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4581 in it is being compared against certain values. Get the true and false
4582 comparisons and see if that says anything about the value of each arm. */
4585 && ((false_code
= combine_reversed_comparison_code (cond
))
4587 && GET_CODE (XEXP (cond
, 0)) == REG
)
4590 rtx from
= XEXP (cond
, 0);
4591 rtx true_val
= XEXP (cond
, 1);
4592 rtx false_val
= true_val
;
4595 /* If FALSE_CODE is EQ, swap the codes and arms. */
4597 if (false_code
== EQ
)
4599 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4600 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4603 /* If we are comparing against zero and the expression being tested has
4604 only a single bit that might be nonzero, that is its value when it is
4605 not equal to zero. Similarly if it is known to be -1 or 0. */
4607 if (true_code
== EQ
&& true_val
== const0_rtx
4608 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4609 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4610 else if (true_code
== EQ
&& true_val
== const0_rtx
4611 && (num_sign_bit_copies (from
, GET_MODE (from
))
4612 == GET_MODE_BITSIZE (GET_MODE (from
))))
4613 false_code
= EQ
, false_val
= constm1_rtx
;
4615 /* Now simplify an arm if we know the value of the register in the
4616 branch and it is used in the arm. Be careful due to the potential
4617 of locally-shared RTL. */
4619 if (reg_mentioned_p (from
, true_rtx
))
4620 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4622 pc_rtx
, pc_rtx
, 0, 0);
4623 if (reg_mentioned_p (from
, false_rtx
))
4624 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4626 pc_rtx
, pc_rtx
, 0, 0);
4628 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4629 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4631 true_rtx
= XEXP (x
, 1);
4632 false_rtx
= XEXP (x
, 2);
4633 true_code
= GET_CODE (cond
);
4636 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4637 reversed, do so to avoid needing two sets of patterns for
4638 subtract-and-branch insns. Similarly if we have a constant in the true
4639 arm, the false arm is the same as the first operand of the comparison, or
4640 the false arm is more complicated than the true arm. */
4643 && combine_reversed_comparison_code (cond
) != UNKNOWN
4644 && (true_rtx
== pc_rtx
4645 || (CONSTANT_P (true_rtx
)
4646 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4647 || true_rtx
== const0_rtx
4648 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4649 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4650 || (GET_CODE (true_rtx
) == SUBREG
4651 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4652 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4653 || reg_mentioned_p (true_rtx
, false_rtx
)
4654 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4656 true_code
= reversed_comparison_code (cond
, NULL
);
4658 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4661 SUBST (XEXP (x
, 1), false_rtx
);
4662 SUBST (XEXP (x
, 2), true_rtx
);
4664 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4667 /* It is possible that the conditional has been simplified out. */
4668 true_code
= GET_CODE (cond
);
4669 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4672 /* If the two arms are identical, we don't need the comparison. */
4674 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4677 /* Convert a == b ? b : a to "a". */
4678 if (true_code
== EQ
&& ! side_effects_p (cond
)
4679 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4680 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4681 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4683 else if (true_code
== NE
&& ! side_effects_p (cond
)
4684 && (! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4685 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4686 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4689 /* Look for cases where we have (abs x) or (neg (abs X)). */
4691 if (GET_MODE_CLASS (mode
) == MODE_INT
4692 && GET_CODE (false_rtx
) == NEG
4693 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4695 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4696 && ! side_effects_p (true_rtx
))
4701 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4705 simplify_gen_unary (NEG
, mode
,
4706 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4712 /* Look for MIN or MAX. */
4714 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4716 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4717 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4718 && ! side_effects_p (cond
))
4723 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4726 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4729 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4732 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4737 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4738 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4739 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4740 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4741 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4742 neither 1 or -1, but it isn't worth checking for. */
4744 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4745 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4747 rtx t
= make_compound_operation (true_rtx
, SET
);
4748 rtx f
= make_compound_operation (false_rtx
, SET
);
4749 rtx cond_op0
= XEXP (cond
, 0);
4750 rtx cond_op1
= XEXP (cond
, 1);
4751 enum rtx_code op
= NIL
, extend_op
= NIL
;
4752 enum machine_mode m
= mode
;
4753 rtx z
= 0, c1
= NULL_RTX
;
4755 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4756 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4757 || GET_CODE (t
) == ASHIFT
4758 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4759 && rtx_equal_p (XEXP (t
, 0), f
))
4760 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4762 /* If an identity-zero op is commutative, check whether there
4763 would be a match if we swapped the operands. */
4764 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4765 || GET_CODE (t
) == XOR
)
4766 && rtx_equal_p (XEXP (t
, 1), f
))
4767 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4768 else if (GET_CODE (t
) == SIGN_EXTEND
4769 && (GET_CODE (XEXP (t
, 0)) == PLUS
4770 || GET_CODE (XEXP (t
, 0)) == MINUS
4771 || GET_CODE (XEXP (t
, 0)) == IOR
4772 || GET_CODE (XEXP (t
, 0)) == XOR
4773 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4774 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4775 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4776 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4777 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4778 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4779 && (num_sign_bit_copies (f
, GET_MODE (f
))
4780 > (GET_MODE_BITSIZE (mode
)
4781 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4783 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4784 extend_op
= SIGN_EXTEND
;
4785 m
= GET_MODE (XEXP (t
, 0));
4787 else if (GET_CODE (t
) == SIGN_EXTEND
4788 && (GET_CODE (XEXP (t
, 0)) == PLUS
4789 || GET_CODE (XEXP (t
, 0)) == IOR
4790 || GET_CODE (XEXP (t
, 0)) == XOR
)
4791 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4792 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4793 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4794 && (num_sign_bit_copies (f
, GET_MODE (f
))
4795 > (GET_MODE_BITSIZE (mode
)
4796 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4798 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4799 extend_op
= SIGN_EXTEND
;
4800 m
= GET_MODE (XEXP (t
, 0));
4802 else if (GET_CODE (t
) == ZERO_EXTEND
4803 && (GET_CODE (XEXP (t
, 0)) == PLUS
4804 || GET_CODE (XEXP (t
, 0)) == MINUS
4805 || GET_CODE (XEXP (t
, 0)) == IOR
4806 || GET_CODE (XEXP (t
, 0)) == XOR
4807 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4808 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4809 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4810 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4811 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4812 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4813 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4814 && ((nonzero_bits (f
, GET_MODE (f
))
4815 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4818 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4819 extend_op
= ZERO_EXTEND
;
4820 m
= GET_MODE (XEXP (t
, 0));
4822 else if (GET_CODE (t
) == ZERO_EXTEND
4823 && (GET_CODE (XEXP (t
, 0)) == PLUS
4824 || GET_CODE (XEXP (t
, 0)) == IOR
4825 || GET_CODE (XEXP (t
, 0)) == XOR
)
4826 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4827 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4828 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4829 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4830 && ((nonzero_bits (f
, GET_MODE (f
))
4831 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4834 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4835 extend_op
= ZERO_EXTEND
;
4836 m
= GET_MODE (XEXP (t
, 0));
4841 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4842 pc_rtx
, pc_rtx
, 0, 0);
4843 temp
= gen_binary (MULT
, m
, temp
,
4844 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4845 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4846 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4848 if (extend_op
!= NIL
)
4849 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4855 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4856 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4857 negation of a single bit, we can convert this operation to a shift. We
4858 can actually do this more generally, but it doesn't seem worth it. */
4860 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4861 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4862 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4863 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4864 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4865 == GET_MODE_BITSIZE (mode
))
4866 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4868 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4869 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4874 /* Simplify X, a SET expression. Return the new expression. */
4880 rtx src
= SET_SRC (x
);
4881 rtx dest
= SET_DEST (x
);
4882 enum machine_mode mode
4883 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4887 /* (set (pc) (return)) gets written as (return). */
4888 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4891 /* Now that we know for sure which bits of SRC we are using, see if we can
4892 simplify the expression for the object knowing that we only need the
4895 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4897 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4898 SUBST (SET_SRC (x
), src
);
4901 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4902 the comparison result and try to simplify it unless we already have used
4903 undobuf.other_insn. */
4904 if ((GET_CODE (src
) == COMPARE
4909 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4910 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4911 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4912 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4914 enum rtx_code old_code
= GET_CODE (*cc_use
);
4915 enum rtx_code new_code
;
4917 int other_changed
= 0;
4918 enum machine_mode compare_mode
= GET_MODE (dest
);
4920 if (GET_CODE (src
) == COMPARE
)
4921 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4923 op0
= src
, op1
= const0_rtx
;
4925 /* Simplify our comparison, if possible. */
4926 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4928 #ifdef EXTRA_CC_MODES
4929 /* If this machine has CC modes other than CCmode, check to see if we
4930 need to use a different CC mode here. */
4931 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4932 #endif /* EXTRA_CC_MODES */
4934 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4935 /* If the mode changed, we have to change SET_DEST, the mode in the
4936 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4937 a hard register, just build new versions with the proper mode. If it
4938 is a pseudo, we lose unless it is only time we set the pseudo, in
4939 which case we can safely change its mode. */
4940 if (compare_mode
!= GET_MODE (dest
))
4942 unsigned int regno
= REGNO (dest
);
4943 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4945 if (regno
< FIRST_PSEUDO_REGISTER
4946 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4948 if (regno
>= FIRST_PSEUDO_REGISTER
)
4949 SUBST (regno_reg_rtx
[regno
], new_dest
);
4951 SUBST (SET_DEST (x
), new_dest
);
4952 SUBST (XEXP (*cc_use
, 0), new_dest
);
4960 /* If the code changed, we have to build a new comparison in
4961 undobuf.other_insn. */
4962 if (new_code
!= old_code
)
4964 unsigned HOST_WIDE_INT mask
;
4966 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
4969 /* If the only change we made was to change an EQ into an NE or
4970 vice versa, OP0 has only one bit that might be nonzero, and OP1
4971 is zero, check if changing the user of the condition code will
4972 produce a valid insn. If it won't, we can keep the original code
4973 in that insn by surrounding our operation with an XOR. */
4975 if (((old_code
== NE
&& new_code
== EQ
)
4976 || (old_code
== EQ
&& new_code
== NE
))
4977 && ! other_changed
&& op1
== const0_rtx
4978 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4979 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4981 rtx pat
= PATTERN (other_insn
), note
= 0;
4983 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4984 && ! check_asm_operands (pat
)))
4986 PUT_CODE (*cc_use
, old_code
);
4989 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4997 undobuf
.other_insn
= other_insn
;
5000 /* If we are now comparing against zero, change our source if
5001 needed. If we do not use cc0, we always have a COMPARE. */
5002 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5004 SUBST (SET_SRC (x
), op0
);
5010 /* Otherwise, if we didn't previously have a COMPARE in the
5011 correct mode, we need one. */
5012 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5014 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5019 /* Otherwise, update the COMPARE if needed. */
5020 SUBST (XEXP (src
, 0), op0
);
5021 SUBST (XEXP (src
, 1), op1
);
5026 /* Get SET_SRC in a form where we have placed back any
5027 compound expressions. Then do the checks below. */
5028 src
= make_compound_operation (src
, SET
);
5029 SUBST (SET_SRC (x
), src
);
5032 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5033 and X being a REG or (subreg (reg)), we may be able to convert this to
5034 (set (subreg:m2 x) (op)).
5036 We can always do this if M1 is narrower than M2 because that means that
5037 we only care about the low bits of the result.
5039 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5040 perform a narrower operation than requested since the high-order bits will
5041 be undefined. On machine where it is defined, this transformation is safe
5042 as long as M1 and M2 have the same number of words. */
5044 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5045 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5046 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5048 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5049 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5050 #ifndef WORD_REGISTER_OPERATIONS
5051 && (GET_MODE_SIZE (GET_MODE (src
))
5052 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5054 #ifdef CLASS_CANNOT_CHANGE_MODE
5055 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5056 && (TEST_HARD_REG_BIT
5057 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5059 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5060 GET_MODE (SUBREG_REG (src
))))
5062 && (GET_CODE (dest
) == REG
5063 || (GET_CODE (dest
) == SUBREG
5064 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5066 SUBST (SET_DEST (x
),
5067 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5069 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5071 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5074 #ifdef LOAD_EXTEND_OP
5075 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5076 would require a paradoxical subreg. Replace the subreg with a
5077 zero_extend to avoid the reload that would otherwise be required. */
5079 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5080 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5081 && SUBREG_BYTE (src
) == 0
5082 && (GET_MODE_SIZE (GET_MODE (src
))
5083 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5084 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5087 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5088 GET_MODE (src
), SUBREG_REG (src
)));
5094 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5095 are comparing an item known to be 0 or -1 against 0, use a logical
5096 operation instead. Check for one of the arms being an IOR of the other
5097 arm with some value. We compute three terms to be IOR'ed together. In
5098 practice, at most two will be nonzero. Then we do the IOR's. */
5100 if (GET_CODE (dest
) != PC
5101 && GET_CODE (src
) == IF_THEN_ELSE
5102 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5103 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5104 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5105 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5106 #ifdef HAVE_conditional_move
5107 && ! can_conditionally_move_p (GET_MODE (src
))
5109 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5110 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5111 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5112 && ! side_effects_p (src
))
5114 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5115 ? XEXP (src
, 1) : XEXP (src
, 2));
5116 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5117 ? XEXP (src
, 2) : XEXP (src
, 1));
5118 rtx term1
= const0_rtx
, term2
, term3
;
5120 if (GET_CODE (true_rtx
) == IOR
5121 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5122 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 1), false_rtx
= const0_rtx
;
5123 else if (GET_CODE (true_rtx
) == IOR
5124 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5125 term1
= false_rtx
, true_rtx
= XEXP(true_rtx
, 0), false_rtx
= const0_rtx
;
5126 else if (GET_CODE (false_rtx
) == IOR
5127 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5128 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 1), true_rtx
= const0_rtx
;
5129 else if (GET_CODE (false_rtx
) == IOR
5130 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5131 term1
= true_rtx
, false_rtx
= XEXP(false_rtx
, 0), true_rtx
= const0_rtx
;
5133 term2
= gen_binary (AND
, GET_MODE (src
),
5134 XEXP (XEXP (src
, 0), 0), true_rtx
);
5135 term3
= gen_binary (AND
, GET_MODE (src
),
5136 simplify_gen_unary (NOT
, GET_MODE (src
),
5137 XEXP (XEXP (src
, 0), 0),
5142 gen_binary (IOR
, GET_MODE (src
),
5143 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5149 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5150 whole thing fail. */
5151 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5153 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5156 /* Convert this into a field assignment operation, if possible. */
5157 return make_field_assignment (x
);
5160 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5161 result. LAST is nonzero if this is the last retry. */
5164 simplify_logical (x
, last
)
5168 enum machine_mode mode
= GET_MODE (x
);
5169 rtx op0
= XEXP (x
, 0);
5170 rtx op1
= XEXP (x
, 1);
5173 switch (GET_CODE (x
))
5176 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5177 insn (and may simplify more). */
5178 if (GET_CODE (op0
) == XOR
5179 && rtx_equal_p (XEXP (op0
, 0), op1
)
5180 && ! side_effects_p (op1
))
5181 x
= gen_binary (AND
, mode
,
5182 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5185 if (GET_CODE (op0
) == XOR
5186 && rtx_equal_p (XEXP (op0
, 1), op1
)
5187 && ! side_effects_p (op1
))
5188 x
= gen_binary (AND
, mode
,
5189 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5192 /* Similarly for (~(A ^ B)) & A. */
5193 if (GET_CODE (op0
) == NOT
5194 && GET_CODE (XEXP (op0
, 0)) == XOR
5195 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5196 && ! side_effects_p (op1
))
5197 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5199 if (GET_CODE (op0
) == NOT
5200 && GET_CODE (XEXP (op0
, 0)) == XOR
5201 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5202 && ! side_effects_p (op1
))
5203 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5205 /* We can call simplify_and_const_int only if we don't lose
5206 any (sign) bits when converting INTVAL (op1) to
5207 "unsigned HOST_WIDE_INT". */
5208 if (GET_CODE (op1
) == CONST_INT
5209 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5210 || INTVAL (op1
) > 0))
5212 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5214 /* If we have (ior (and (X C1) C2)) and the next restart would be
5215 the last, simplify this by making C1 as small as possible
5218 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5219 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5220 && GET_CODE (op1
) == CONST_INT
)
5221 return gen_binary (IOR
, mode
,
5222 gen_binary (AND
, mode
, XEXP (op0
, 0),
5223 GEN_INT (INTVAL (XEXP (op0
, 1))
5224 & ~INTVAL (op1
))), op1
);
5226 if (GET_CODE (x
) != AND
)
5229 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5230 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5231 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5234 /* Convert (A | B) & A to A. */
5235 if (GET_CODE (op0
) == IOR
5236 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5237 || rtx_equal_p (XEXP (op0
, 1), op1
))
5238 && ! side_effects_p (XEXP (op0
, 0))
5239 && ! side_effects_p (XEXP (op0
, 1)))
5242 /* In the following group of tests (and those in case IOR below),
5243 we start with some combination of logical operations and apply
5244 the distributive law followed by the inverse distributive law.
5245 Most of the time, this results in no change. However, if some of
5246 the operands are the same or inverses of each other, simplifications
5249 For example, (and (ior A B) (not B)) can occur as the result of
5250 expanding a bit field assignment. When we apply the distributive
5251 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5252 which then simplifies to (and (A (not B))).
5254 If we have (and (ior A B) C), apply the distributive law and then
5255 the inverse distributive law to see if things simplify. */
5257 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5259 x
= apply_distributive_law
5260 (gen_binary (GET_CODE (op0
), mode
,
5261 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5262 gen_binary (AND
, mode
, XEXP (op0
, 1),
5264 if (GET_CODE (x
) != AND
)
5268 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5269 return apply_distributive_law
5270 (gen_binary (GET_CODE (op1
), mode
,
5271 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5272 gen_binary (AND
, mode
, XEXP (op1
, 1),
5275 /* Similarly, taking advantage of the fact that
5276 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5278 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5279 return apply_distributive_law
5280 (gen_binary (XOR
, mode
,
5281 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5282 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5285 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5286 return apply_distributive_law
5287 (gen_binary (XOR
, mode
,
5288 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5289 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5293 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5294 if (GET_CODE (op1
) == CONST_INT
5295 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5296 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5299 /* Convert (A & B) | A to A. */
5300 if (GET_CODE (op0
) == AND
5301 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5302 || rtx_equal_p (XEXP (op0
, 1), op1
))
5303 && ! side_effects_p (XEXP (op0
, 0))
5304 && ! side_effects_p (XEXP (op0
, 1)))
5307 /* If we have (ior (and A B) C), apply the distributive law and then
5308 the inverse distributive law to see if things simplify. */
5310 if (GET_CODE (op0
) == AND
)
5312 x
= apply_distributive_law
5313 (gen_binary (AND
, mode
,
5314 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5315 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5318 if (GET_CODE (x
) != IOR
)
5322 if (GET_CODE (op1
) == AND
)
5324 x
= apply_distributive_law
5325 (gen_binary (AND
, mode
,
5326 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5327 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5330 if (GET_CODE (x
) != IOR
)
5334 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5335 mode size to (rotate A CX). */
5337 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5338 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5339 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5340 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5341 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5342 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5343 == GET_MODE_BITSIZE (mode
)))
5344 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5345 (GET_CODE (op0
) == ASHIFT
5346 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5348 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5349 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5350 does not affect any of the bits in OP1, it can really be done
5351 as a PLUS and we can associate. We do this by seeing if OP1
5352 can be safely shifted left C bits. */
5353 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5354 && GET_CODE (XEXP (op0
, 0)) == PLUS
5355 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5356 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5357 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5359 int count
= INTVAL (XEXP (op0
, 1));
5360 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5362 if (mask
>> count
== INTVAL (op1
)
5363 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5365 SUBST (XEXP (XEXP (op0
, 0), 1),
5366 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5373 /* If we are XORing two things that have no bits in common,
5374 convert them into an IOR. This helps to detect rotation encoded
5375 using those methods and possibly other simplifications. */
5377 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5378 && (nonzero_bits (op0
, mode
)
5379 & nonzero_bits (op1
, mode
)) == 0)
5380 return (gen_binary (IOR
, mode
, op0
, op1
));
5382 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5383 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5386 int num_negated
= 0;
5388 if (GET_CODE (op0
) == NOT
)
5389 num_negated
++, op0
= XEXP (op0
, 0);
5390 if (GET_CODE (op1
) == NOT
)
5391 num_negated
++, op1
= XEXP (op1
, 0);
5393 if (num_negated
== 2)
5395 SUBST (XEXP (x
, 0), op0
);
5396 SUBST (XEXP (x
, 1), op1
);
5398 else if (num_negated
== 1)
5400 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5404 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5405 correspond to a machine insn or result in further simplifications
5406 if B is a constant. */
5408 if (GET_CODE (op0
) == AND
5409 && rtx_equal_p (XEXP (op0
, 1), op1
)
5410 && ! side_effects_p (op1
))
5411 return gen_binary (AND
, mode
,
5412 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5415 else if (GET_CODE (op0
) == AND
5416 && rtx_equal_p (XEXP (op0
, 0), op1
)
5417 && ! side_effects_p (op1
))
5418 return gen_binary (AND
, mode
,
5419 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5422 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5423 comparison if STORE_FLAG_VALUE is 1. */
5424 if (STORE_FLAG_VALUE
== 1
5425 && op1
== const1_rtx
5426 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5427 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5431 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5432 is (lt foo (const_int 0)), so we can perform the above
5433 simplification if STORE_FLAG_VALUE is 1. */
5435 if (STORE_FLAG_VALUE
== 1
5436 && op1
== const1_rtx
5437 && GET_CODE (op0
) == LSHIFTRT
5438 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5439 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5440 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5442 /* (xor (comparison foo bar) (const_int sign-bit))
5443 when STORE_FLAG_VALUE is the sign bit. */
5444 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5445 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5446 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5447 && op1
== const_true_rtx
5448 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5449 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5462 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5463 operations" because they can be replaced with two more basic operations.
5464 ZERO_EXTEND is also considered "compound" because it can be replaced with
5465 an AND operation, which is simpler, though only one operation.
5467 The function expand_compound_operation is called with an rtx expression
5468 and will convert it to the appropriate shifts and AND operations,
5469 simplifying at each stage.
5471 The function make_compound_operation is called to convert an expression
5472 consisting of shifts and ANDs into the equivalent compound expression.
5473 It is the inverse of this function, loosely speaking. */
5476 expand_compound_operation (x
)
5479 unsigned HOST_WIDE_INT pos
= 0, len
;
5481 unsigned int modewidth
;
5484 switch (GET_CODE (x
))
5489 /* We can't necessarily use a const_int for a multiword mode;
5490 it depends on implicitly extending the value.
5491 Since we don't know the right way to extend it,
5492 we can't tell whether the implicit way is right.
5494 Even for a mode that is no wider than a const_int,
5495 we can't win, because we need to sign extend one of its bits through
5496 the rest of it, and we don't know which bit. */
5497 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5500 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5501 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5502 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5503 reloaded. If not for that, MEM's would very rarely be safe.
5505 Reject MODEs bigger than a word, because we might not be able
5506 to reference a two-register group starting with an arbitrary register
5507 (and currently gen_lowpart might crash for a SUBREG). */
5509 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5512 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5513 /* If the inner object has VOIDmode (the only way this can happen
5514 is if it is a ASM_OPERANDS), we can't do anything since we don't
5515 know how much masking to do. */
5524 /* If the operand is a CLOBBER, just return it. */
5525 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5528 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5529 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5530 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5533 len
= INTVAL (XEXP (x
, 1));
5534 pos
= INTVAL (XEXP (x
, 2));
5536 /* If this goes outside the object being extracted, replace the object
5537 with a (use (mem ...)) construct that only combine understands
5538 and is used only for this purpose. */
5539 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5540 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5542 if (BITS_BIG_ENDIAN
)
5543 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5550 /* Convert sign extension to zero extension, if we know that the high
5551 bit is not set, as this is easier to optimize. It will be converted
5552 back to cheaper alternative in make_extraction. */
5553 if (GET_CODE (x
) == SIGN_EXTEND
5554 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5555 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5556 & ~(((unsigned HOST_WIDE_INT
)
5557 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5561 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5562 return expand_compound_operation (temp
);
5565 /* We can optimize some special cases of ZERO_EXTEND. */
5566 if (GET_CODE (x
) == ZERO_EXTEND
)
5568 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5569 know that the last value didn't have any inappropriate bits
5571 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5572 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5573 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5574 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5575 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5576 return XEXP (XEXP (x
, 0), 0);
5578 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5579 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5580 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5581 && subreg_lowpart_p (XEXP (x
, 0))
5582 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5583 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5584 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5585 return SUBREG_REG (XEXP (x
, 0));
5587 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5588 is a comparison and STORE_FLAG_VALUE permits. This is like
5589 the first case, but it works even when GET_MODE (x) is larger
5590 than HOST_WIDE_INT. */
5591 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5592 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5593 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5594 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5595 <= HOST_BITS_PER_WIDE_INT
)
5596 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5597 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5598 return XEXP (XEXP (x
, 0), 0);
5600 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5601 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5602 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5603 && subreg_lowpart_p (XEXP (x
, 0))
5604 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5605 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5606 <= HOST_BITS_PER_WIDE_INT
)
5607 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5608 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5609 return SUBREG_REG (XEXP (x
, 0));
5613 /* If we reach here, we want to return a pair of shifts. The inner
5614 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5615 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5616 logical depending on the value of UNSIGNEDP.
5618 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5619 converted into an AND of a shift.
5621 We must check for the case where the left shift would have a negative
5622 count. This can happen in a case like (x >> 31) & 255 on machines
5623 that can't shift by a constant. On those machines, we would first
5624 combine the shift with the AND to produce a variable-position
5625 extraction. Then the constant of 31 would be substituted in to produce
5626 a such a position. */
5628 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5629 if (modewidth
+ len
>= pos
)
5630 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5632 simplify_shift_const (NULL_RTX
, ASHIFT
,
5635 modewidth
- pos
- len
),
5638 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5639 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5640 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5643 ((HOST_WIDE_INT
) 1 << len
) - 1);
5645 /* Any other cases we can't handle. */
5648 /* If we couldn't do this for some reason, return the original
5650 if (GET_CODE (tem
) == CLOBBER
)
5656 /* X is a SET which contains an assignment of one object into
5657 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5658 or certain SUBREGS). If possible, convert it into a series of
5661 We half-heartedly support variable positions, but do not at all
5662 support variable lengths. */
5665 expand_field_assignment (x
)
5669 rtx pos
; /* Always counts from low bit. */
5672 enum machine_mode compute_mode
;
5674 /* Loop until we find something we can't simplify. */
5677 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5678 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5680 int byte_offset
= SUBREG_BYTE (XEXP (SET_DEST (x
), 0));
5682 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5683 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5684 pos
= GEN_INT (BITS_PER_WORD
* (byte_offset
/ UNITS_PER_WORD
));
5686 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5687 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5689 inner
= XEXP (SET_DEST (x
), 0);
5690 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5691 pos
= XEXP (SET_DEST (x
), 2);
5693 /* If the position is constant and spans the width of INNER,
5694 surround INNER with a USE to indicate this. */
5695 if (GET_CODE (pos
) == CONST_INT
5696 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5697 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5699 if (BITS_BIG_ENDIAN
)
5701 if (GET_CODE (pos
) == CONST_INT
)
5702 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5704 else if (GET_CODE (pos
) == MINUS
5705 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5706 && (INTVAL (XEXP (pos
, 1))
5707 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5708 /* If position is ADJUST - X, new position is X. */
5709 pos
= XEXP (pos
, 0);
5711 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5712 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5718 /* A SUBREG between two modes that occupy the same numbers of words
5719 can be done by moving the SUBREG to the source. */
5720 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5721 /* We need SUBREGs to compute nonzero_bits properly. */
5722 && nonzero_sign_valid
5723 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5724 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5725 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5726 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5728 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5729 gen_lowpart_for_combine
5730 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5737 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5738 inner
= SUBREG_REG (inner
);
5740 compute_mode
= GET_MODE (inner
);
5742 /* Don't attempt bitwise arithmetic on non-integral modes. */
5743 if (! INTEGRAL_MODE_P (compute_mode
))
5745 enum machine_mode imode
;
5747 /* Something is probably seriously wrong if this matches. */
5748 if (! FLOAT_MODE_P (compute_mode
))
5751 /* Try to find an integral mode to pun with. */
5752 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5753 if (imode
== BLKmode
)
5756 compute_mode
= imode
;
5757 inner
= gen_lowpart_for_combine (imode
, inner
);
5760 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5761 if (len
< HOST_BITS_PER_WIDE_INT
)
5762 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5766 /* Now compute the equivalent expression. Make a copy of INNER
5767 for the SET_DEST in case it is a MEM into which we will substitute;
5768 we don't want shared RTL in that case. */
5770 (VOIDmode
, copy_rtx (inner
),
5771 gen_binary (IOR
, compute_mode
,
5772 gen_binary (AND
, compute_mode
,
5773 simplify_gen_unary (NOT
, compute_mode
,
5779 gen_binary (ASHIFT
, compute_mode
,
5780 gen_binary (AND
, compute_mode
,
5781 gen_lowpart_for_combine
5782 (compute_mode
, SET_SRC (x
)),
5790 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5791 it is an RTX that represents a variable starting position; otherwise,
5792 POS is the (constant) starting bit position (counted from the LSB).
5794 INNER may be a USE. This will occur when we started with a bitfield
5795 that went outside the boundary of the object in memory, which is
5796 allowed on most machines. To isolate this case, we produce a USE
5797 whose mode is wide enough and surround the MEM with it. The only
5798 code that understands the USE is this routine. If it is not removed,
5799 it will cause the resulting insn not to match.
5801 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5804 IN_DEST is non-zero if this is a reference in the destination of a
5805 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5806 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5809 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5810 ZERO_EXTRACT should be built even for bits starting at bit 0.
5812 MODE is the desired mode of the result (if IN_DEST == 0).
5814 The result is an RTX for the extraction or NULL_RTX if the target
5818 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5819 unsignedp
, in_dest
, in_compare
)
5820 enum machine_mode mode
;
5824 unsigned HOST_WIDE_INT len
;
5826 int in_dest
, in_compare
;
5828 /* This mode describes the size of the storage area
5829 to fetch the overall value from. Within that, we
5830 ignore the POS lowest bits, etc. */
5831 enum machine_mode is_mode
= GET_MODE (inner
);
5832 enum machine_mode inner_mode
;
5833 enum machine_mode wanted_inner_mode
= byte_mode
;
5834 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5835 enum machine_mode pos_mode
= word_mode
;
5836 enum machine_mode extraction_mode
= word_mode
;
5837 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5840 rtx orig_pos_rtx
= pos_rtx
;
5841 HOST_WIDE_INT orig_pos
;
5843 /* Get some information about INNER and get the innermost object. */
5844 if (GET_CODE (inner
) == USE
)
5845 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5846 /* We don't need to adjust the position because we set up the USE
5847 to pretend that it was a full-word object. */
5848 spans_byte
= 1, inner
= XEXP (inner
, 0);
5849 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5851 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5852 consider just the QI as the memory to extract from.
5853 The subreg adds or removes high bits; its mode is
5854 irrelevant to the meaning of this extraction,
5855 since POS and LEN count from the lsb. */
5856 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5857 is_mode
= GET_MODE (SUBREG_REG (inner
));
5858 inner
= SUBREG_REG (inner
);
5861 inner_mode
= GET_MODE (inner
);
5863 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5864 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5866 /* See if this can be done without an extraction. We never can if the
5867 width of the field is not the same as that of some integer mode. For
5868 registers, we can only avoid the extraction if the position is at the
5869 low-order bit and this is either not in the destination or we have the
5870 appropriate STRICT_LOW_PART operation available.
5872 For MEM, we can avoid an extract if the field starts on an appropriate
5873 boundary and we can change the mode of the memory reference. However,
5874 we cannot directly access the MEM if we have a USE and the underlying
5875 MEM is not TMODE. This combination means that MEM was being used in a
5876 context where bits outside its mode were being referenced; that is only
5877 valid in bit-field insns. */
5879 if (tmode
!= BLKmode
5880 && ! (spans_byte
&& inner_mode
!= tmode
)
5881 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5882 && GET_CODE (inner
) != MEM
5884 || (GET_CODE (inner
) == REG
5885 && have_insn_for (STRICT_LOW_PART
, tmode
))))
5886 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5888 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5889 : BITS_PER_UNIT
)) == 0
5890 /* We can't do this if we are widening INNER_MODE (it
5891 may not be aligned, for one thing). */
5892 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5893 && (inner_mode
== tmode
5894 || (! mode_dependent_address_p (XEXP (inner
, 0))
5895 && ! MEM_VOLATILE_P (inner
))))))
5897 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5898 field. If the original and current mode are the same, we need not
5899 adjust the offset. Otherwise, we do if bytes big endian.
5901 If INNER is not a MEM, get a piece consisting of just the field
5902 of interest (in this case POS % BITS_PER_WORD must be 0). */
5904 if (GET_CODE (inner
) == MEM
)
5906 HOST_WIDE_INT offset
;
5908 /* POS counts from lsb, but make OFFSET count in memory order. */
5909 if (BYTES_BIG_ENDIAN
)
5910 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5912 offset
= pos
/ BITS_PER_UNIT
;
5914 new = adjust_address_nv (inner
, tmode
, offset
);
5916 else if (GET_CODE (inner
) == REG
)
5918 /* We can't call gen_lowpart_for_combine here since we always want
5919 a SUBREG and it would sometimes return a new hard register. */
5920 if (tmode
!= inner_mode
)
5922 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
5924 if (WORDS_BIG_ENDIAN
5925 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
5926 final_word
= ((GET_MODE_SIZE (inner_mode
)
5927 - GET_MODE_SIZE (tmode
))
5928 / UNITS_PER_WORD
) - final_word
;
5930 final_word
*= UNITS_PER_WORD
;
5931 if (BYTES_BIG_ENDIAN
&&
5932 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
5933 final_word
+= (GET_MODE_SIZE (inner_mode
)
5934 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
5936 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
5942 new = force_to_mode (inner
, tmode
,
5943 len
>= HOST_BITS_PER_WIDE_INT
5944 ? ~(unsigned HOST_WIDE_INT
) 0
5945 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
5948 /* If this extraction is going into the destination of a SET,
5949 make a STRICT_LOW_PART unless we made a MEM. */
5952 return (GET_CODE (new) == MEM
? new
5953 : (GET_CODE (new) != SUBREG
5954 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
5955 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
5960 /* If we know that no extraneous bits are set, and that the high
5961 bit is not set, convert the extraction to the cheaper of
5962 sign and zero extension, that are equivalent in these cases. */
5963 if (flag_expensive_optimizations
5964 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
5965 && ((nonzero_bits (new, tmode
)
5966 & ~(((unsigned HOST_WIDE_INT
)
5967 GET_MODE_MASK (tmode
))
5971 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
5972 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
5974 /* Prefer ZERO_EXTENSION, since it gives more information to
5976 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
5981 /* Otherwise, sign- or zero-extend unless we already are in the
5984 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5988 /* Unless this is a COMPARE or we have a funny memory reference,
5989 don't do anything with zero-extending field extracts starting at
5990 the low-order bit since they are simple AND operations. */
5991 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5992 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5995 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5996 we would be spanning bytes or if the position is not a constant and the
5997 length is not 1. In all other cases, we would only be going outside
5998 our object in cases when an original shift would have been
6000 if (! spans_byte
&& GET_CODE (inner
) == MEM
6001 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6002 || (pos_rtx
!= 0 && len
!= 1)))
6005 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6006 and the mode for the result. */
6007 if (in_dest
&& mode_for_extraction(EP_insv
, -1) != MAX_MACHINE_MODE
)
6009 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6010 pos_mode
= mode_for_extraction (EP_insv
, 2);
6011 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6014 if (! in_dest
&& unsignedp
6015 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6017 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6018 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6019 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6022 if (! in_dest
&& ! unsignedp
6023 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6025 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6026 pos_mode
= mode_for_extraction (EP_extv
, 3);
6027 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6030 /* Never narrow an object, since that might not be safe. */
6032 if (mode
!= VOIDmode
6033 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6034 extraction_mode
= mode
;
6036 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6037 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6038 pos_mode
= GET_MODE (pos_rtx
);
6040 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6041 if we have to change the mode of memory and cannot, the desired mode is
6043 if (GET_CODE (inner
) != MEM
)
6044 wanted_inner_mode
= wanted_inner_reg_mode
;
6045 else if (inner_mode
!= wanted_inner_mode
6046 && (mode_dependent_address_p (XEXP (inner
, 0))
6047 || MEM_VOLATILE_P (inner
)))
6048 wanted_inner_mode
= extraction_mode
;
6052 if (BITS_BIG_ENDIAN
)
6054 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6055 BITS_BIG_ENDIAN style. If position is constant, compute new
6056 position. Otherwise, build subtraction.
6057 Note that POS is relative to the mode of the original argument.
6058 If it's a MEM we need to recompute POS relative to that.
6059 However, if we're extracting from (or inserting into) a register,
6060 we want to recompute POS relative to wanted_inner_mode. */
6061 int width
= (GET_CODE (inner
) == MEM
6062 ? GET_MODE_BITSIZE (is_mode
)
6063 : GET_MODE_BITSIZE (wanted_inner_mode
));
6066 pos
= width
- len
- pos
;
6069 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6070 /* POS may be less than 0 now, but we check for that below.
6071 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6074 /* If INNER has a wider mode, make it smaller. If this is a constant
6075 extract, try to adjust the byte to point to the byte containing
6077 if (wanted_inner_mode
!= VOIDmode
6078 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6079 && ((GET_CODE (inner
) == MEM
6080 && (inner_mode
== wanted_inner_mode
6081 || (! mode_dependent_address_p (XEXP (inner
, 0))
6082 && ! MEM_VOLATILE_P (inner
))))))
6086 /* The computations below will be correct if the machine is big
6087 endian in both bits and bytes or little endian in bits and bytes.
6088 If it is mixed, we must adjust. */
6090 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6091 adjust OFFSET to compensate. */
6092 if (BYTES_BIG_ENDIAN
6094 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6095 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6097 /* If this is a constant position, we can move to the desired byte. */
6100 offset
+= pos
/ BITS_PER_UNIT
;
6101 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6104 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6106 && is_mode
!= wanted_inner_mode
)
6107 offset
= (GET_MODE_SIZE (is_mode
)
6108 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6110 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6111 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6114 /* If INNER is not memory, we can always get it into the proper mode. If we
6115 are changing its mode, POS must be a constant and smaller than the size
6117 else if (GET_CODE (inner
) != MEM
)
6119 if (GET_MODE (inner
) != wanted_inner_mode
6121 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6124 inner
= force_to_mode (inner
, wanted_inner_mode
,
6126 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6127 ? ~(unsigned HOST_WIDE_INT
) 0
6128 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6133 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6134 have to zero extend. Otherwise, we can just use a SUBREG. */
6136 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6138 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6140 /* If we know that no extraneous bits are set, and that the high
6141 bit is not set, convert extraction to cheaper one - eighter
6142 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6144 if (flag_expensive_optimizations
6145 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6146 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6147 & ~(((unsigned HOST_WIDE_INT
)
6148 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6152 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6154 /* Prefer ZERO_EXTENSION, since it gives more information to
6156 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6161 else if (pos_rtx
!= 0
6162 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6163 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6165 /* Make POS_RTX unless we already have it and it is correct. If we don't
6166 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6168 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6169 pos_rtx
= orig_pos_rtx
;
6171 else if (pos_rtx
== 0)
6172 pos_rtx
= GEN_INT (pos
);
6174 /* Make the required operation. See if we can use existing rtx. */
6175 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6176 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6178 new = gen_lowpart_for_combine (mode
, new);
6183 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6184 with any other operations in X. Return X without that shift if so. */
6187 extract_left_shift (x
, count
)
6191 enum rtx_code code
= GET_CODE (x
);
6192 enum machine_mode mode
= GET_MODE (x
);
6198 /* This is the shift itself. If it is wide enough, we will return
6199 either the value being shifted if the shift count is equal to
6200 COUNT or a shift for the difference. */
6201 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6202 && INTVAL (XEXP (x
, 1)) >= count
)
6203 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6204 INTVAL (XEXP (x
, 1)) - count
);
6208 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6209 return simplify_gen_unary (code
, mode
, tem
, mode
);
6213 case PLUS
: case IOR
: case XOR
: case AND
:
6214 /* If we can safely shift this constant and we find the inner shift,
6215 make a new operation. */
6216 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6217 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6218 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6219 return gen_binary (code
, mode
, tem
,
6220 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6231 /* Look at the expression rooted at X. Look for expressions
6232 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6233 Form these expressions.
6235 Return the new rtx, usually just X.
6237 Also, for machines like the VAX that don't have logical shift insns,
6238 try to convert logical to arithmetic shift operations in cases where
6239 they are equivalent. This undoes the canonicalizations to logical
6240 shifts done elsewhere.
6242 We try, as much as possible, to re-use rtl expressions to save memory.
6244 IN_CODE says what kind of expression we are processing. Normally, it is
6245 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6246 being kludges), it is MEM. When processing the arguments of a comparison
6247 or a COMPARE against zero, it is COMPARE. */
6250 make_compound_operation (x
, in_code
)
6252 enum rtx_code in_code
;
6254 enum rtx_code code
= GET_CODE (x
);
6255 enum machine_mode mode
= GET_MODE (x
);
6256 int mode_width
= GET_MODE_BITSIZE (mode
);
6258 enum rtx_code next_code
;
6264 /* Select the code to be used in recursive calls. Once we are inside an
6265 address, we stay there. If we have a comparison, set to COMPARE,
6266 but once inside, go back to our default of SET. */
6268 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6269 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6270 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6271 : in_code
== COMPARE
? SET
: in_code
);
6273 /* Process depending on the code of this operation. If NEW is set
6274 non-zero, it will be returned. */
6279 /* Convert shifts by constants into multiplications if inside
6281 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6282 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6283 && INTVAL (XEXP (x
, 1)) >= 0)
6285 new = make_compound_operation (XEXP (x
, 0), next_code
);
6286 new = gen_rtx_MULT (mode
, new,
6287 GEN_INT ((HOST_WIDE_INT
) 1
6288 << INTVAL (XEXP (x
, 1))));
6293 /* If the second operand is not a constant, we can't do anything
6295 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6298 /* If the constant is a power of two minus one and the first operand
6299 is a logical right shift, make an extraction. */
6300 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6301 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6303 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6304 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6305 0, in_code
== COMPARE
);
6308 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6309 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6310 && subreg_lowpart_p (XEXP (x
, 0))
6311 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6312 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6314 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6316 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6317 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6318 0, in_code
== COMPARE
);
6320 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6321 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6322 || GET_CODE (XEXP (x
, 0)) == IOR
)
6323 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6324 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6325 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6327 /* Apply the distributive law, and then try to make extractions. */
6328 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6329 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6331 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6333 new = make_compound_operation (new, in_code
);
6336 /* If we are have (and (rotate X C) M) and C is larger than the number
6337 of bits in M, this is an extraction. */
6339 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6340 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6341 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6342 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6344 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6345 new = make_extraction (mode
, new,
6346 (GET_MODE_BITSIZE (mode
)
6347 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6348 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6351 /* On machines without logical shifts, if the operand of the AND is
6352 a logical shift and our mask turns off all the propagated sign
6353 bits, we can replace the logical shift with an arithmetic shift. */
6354 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6355 && !have_insn_for (LSHIFTRT
, mode
)
6356 && have_insn_for (ASHIFTRT
, mode
)
6357 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6358 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6359 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6360 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6362 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6364 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6365 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6367 gen_rtx_ASHIFTRT (mode
,
6368 make_compound_operation
6369 (XEXP (XEXP (x
, 0), 0), next_code
),
6370 XEXP (XEXP (x
, 0), 1)));
6373 /* If the constant is one less than a power of two, this might be
6374 representable by an extraction even if no shift is present.
6375 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6376 we are in a COMPARE. */
6377 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6378 new = make_extraction (mode
,
6379 make_compound_operation (XEXP (x
, 0),
6381 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6383 /* If we are in a comparison and this is an AND with a power of two,
6384 convert this into the appropriate bit extract. */
6385 else if (in_code
== COMPARE
6386 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6387 new = make_extraction (mode
,
6388 make_compound_operation (XEXP (x
, 0),
6390 i
, NULL_RTX
, 1, 1, 0, 1);
6395 /* If the sign bit is known to be zero, replace this with an
6396 arithmetic shift. */
6397 if (have_insn_for (ASHIFTRT
, mode
)
6398 && ! have_insn_for (LSHIFTRT
, mode
)
6399 && mode_width
<= HOST_BITS_PER_WIDE_INT
6400 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6402 new = gen_rtx_ASHIFTRT (mode
,
6403 make_compound_operation (XEXP (x
, 0),
6409 /* ... fall through ... */
6415 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6416 this is a SIGN_EXTRACT. */
6417 if (GET_CODE (rhs
) == CONST_INT
6418 && GET_CODE (lhs
) == ASHIFT
6419 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6420 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6422 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6423 new = make_extraction (mode
, new,
6424 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6425 NULL_RTX
, mode_width
- INTVAL (rhs
),
6426 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6430 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6431 If so, try to merge the shifts into a SIGN_EXTEND. We could
6432 also do this for some cases of SIGN_EXTRACT, but it doesn't
6433 seem worth the effort; the case checked for occurs on Alpha. */
6435 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6436 && ! (GET_CODE (lhs
) == SUBREG
6437 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6438 && GET_CODE (rhs
) == CONST_INT
6439 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6440 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6441 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6442 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6443 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6448 /* Call ourselves recursively on the inner expression. If we are
6449 narrowing the object and it has a different RTL code from
6450 what it originally did, do this SUBREG as a force_to_mode. */
6452 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6453 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6454 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6455 && subreg_lowpart_p (x
))
6457 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6460 /* If we have something other than a SUBREG, we might have
6461 done an expansion, so rerun outselves. */
6462 if (GET_CODE (newer
) != SUBREG
)
6463 newer
= make_compound_operation (newer
, in_code
);
6468 /* If this is a paradoxical subreg, and the new code is a sign or
6469 zero extension, omit the subreg and widen the extension. If it
6470 is a regular subreg, we can still get rid of the subreg by not
6471 widening so much, or in fact removing the extension entirely. */
6472 if ((GET_CODE (tem
) == SIGN_EXTEND
6473 || GET_CODE (tem
) == ZERO_EXTEND
)
6474 && subreg_lowpart_p (x
))
6476 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6477 || (GET_MODE_SIZE (mode
) >
6478 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6479 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6481 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6492 x
= gen_lowpart_for_combine (mode
, new);
6493 code
= GET_CODE (x
);
6496 /* Now recursively process each operand of this operation. */
6497 fmt
= GET_RTX_FORMAT (code
);
6498 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6501 new = make_compound_operation (XEXP (x
, i
), next_code
);
6502 SUBST (XEXP (x
, i
), new);
6508 /* Given M see if it is a value that would select a field of bits
6509 within an item, but not the entire word. Return -1 if not.
6510 Otherwise, return the starting position of the field, where 0 is the
6513 *PLEN is set to the length of the field. */
6516 get_pos_from_mask (m
, plen
)
6517 unsigned HOST_WIDE_INT m
;
6518 unsigned HOST_WIDE_INT
*plen
;
6520 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6521 int pos
= exact_log2 (m
& -m
);
6527 /* Now shift off the low-order zero bits and see if we have a power of
6529 len
= exact_log2 ((m
>> pos
) + 1);
6538 /* See if X can be simplified knowing that we will only refer to it in
6539 MODE and will only refer to those bits that are nonzero in MASK.
6540 If other bits are being computed or if masking operations are done
6541 that select a superset of the bits in MASK, they can sometimes be
6544 Return a possibly simplified expression, but always convert X to
6545 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6547 Also, if REG is non-zero and X is a register equal in value to REG,
6550 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6551 are all off in X. This is used when X will be complemented, by either
6552 NOT, NEG, or XOR. */
6555 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6557 enum machine_mode mode
;
6558 unsigned HOST_WIDE_INT mask
;
6562 enum rtx_code code
= GET_CODE (x
);
6563 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6564 enum machine_mode op_mode
;
6565 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6568 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6569 code below will do the wrong thing since the mode of such an
6570 expression is VOIDmode.
6572 Also do nothing if X is a CLOBBER; this can happen if X was
6573 the return value from a call to gen_lowpart_for_combine. */
6574 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6577 /* We want to perform the operation is its present mode unless we know
6578 that the operation is valid in MODE, in which case we do the operation
6580 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6581 && have_insn_for (code
, mode
))
6582 ? mode
: GET_MODE (x
));
6584 /* It is not valid to do a right-shift in a narrower mode
6585 than the one it came in with. */
6586 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6587 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6588 op_mode
= GET_MODE (x
);
6590 /* Truncate MASK to fit OP_MODE. */
6592 mask
&= GET_MODE_MASK (op_mode
);
6594 /* When we have an arithmetic operation, or a shift whose count we
6595 do not know, we need to assume that all bit the up to the highest-order
6596 bit in MASK will be needed. This is how we form such a mask. */
6598 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6599 ? GET_MODE_MASK (op_mode
)
6600 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6603 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6605 /* Determine what bits of X are guaranteed to be (non)zero. */
6606 nonzero
= nonzero_bits (x
, mode
);
6608 /* If none of the bits in X are needed, return a zero. */
6609 if (! just_select
&& (nonzero
& mask
) == 0)
6612 /* If X is a CONST_INT, return a new one. Do this here since the
6613 test below will fail. */
6614 if (GET_CODE (x
) == CONST_INT
)
6616 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6617 int width
= GET_MODE_BITSIZE (mode
);
6619 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6620 number, sign extend it. */
6621 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6622 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6623 cval
|= (HOST_WIDE_INT
) -1 << width
;
6625 return GEN_INT (cval
);
6628 /* If X is narrower than MODE and we want all the bits in X's mode, just
6629 get X in the proper mode. */
6630 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6631 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6632 return gen_lowpart_for_combine (mode
, x
);
6634 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6635 MASK are already known to be zero in X, we need not do anything. */
6636 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6642 /* If X is a (clobber (const_int)), return it since we know we are
6643 generating something that won't match. */
6647 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6648 spanned the boundary of the MEM. If we are now masking so it is
6649 within that boundary, we don't need the USE any more. */
6650 if (! BITS_BIG_ENDIAN
6651 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6652 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6659 x
= expand_compound_operation (x
);
6660 if (GET_CODE (x
) != code
)
6661 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6665 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6666 || rtx_equal_p (reg
, get_last_value (x
))))
6671 if (subreg_lowpart_p (x
)
6672 /* We can ignore the effect of this SUBREG if it narrows the mode or
6673 if the constant masks to zero all the bits the mode doesn't
6675 && ((GET_MODE_SIZE (GET_MODE (x
))
6676 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6678 & GET_MODE_MASK (GET_MODE (x
))
6679 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6680 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6684 /* If this is an AND with a constant, convert it into an AND
6685 whose constant is the AND of that constant with MASK. If it
6686 remains an AND of MASK, delete it since it is redundant. */
6688 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6690 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6691 mask
& INTVAL (XEXP (x
, 1)));
6693 /* If X is still an AND, see if it is an AND with a mask that
6694 is just some low-order bits. If so, and it is MASK, we don't
6697 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6698 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6701 /* If it remains an AND, try making another AND with the bits
6702 in the mode mask that aren't in MASK turned on. If the
6703 constant in the AND is wide enough, this might make a
6704 cheaper constant. */
6706 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6707 && GET_MODE_MASK (GET_MODE (x
)) != mask
6708 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6710 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6711 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6712 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6715 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6716 number, sign extend it. */
6717 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6718 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6719 cval
|= (HOST_WIDE_INT
) -1 << width
;
6721 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6722 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6732 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6733 low-order bits (as in an alignment operation) and FOO is already
6734 aligned to that boundary, mask C1 to that boundary as well.
6735 This may eliminate that PLUS and, later, the AND. */
6738 unsigned int width
= GET_MODE_BITSIZE (mode
);
6739 unsigned HOST_WIDE_INT smask
= mask
;
6741 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6742 number, sign extend it. */
6744 if (width
< HOST_BITS_PER_WIDE_INT
6745 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6746 smask
|= (HOST_WIDE_INT
) -1 << width
;
6748 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6749 && exact_log2 (- smask
) >= 0)
6753 && (XEXP (x
, 0) == stack_pointer_rtx
6754 || XEXP (x
, 0) == frame_pointer_rtx
))
6756 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6757 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6759 sp_mask
&= ~(sp_alignment
- 1);
6760 if ((sp_mask
& ~smask
) == 0
6761 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6762 return force_to_mode (plus_constant (XEXP (x
, 0),
6763 ((INTVAL (XEXP (x
, 1)) -
6764 STACK_BIAS
) & smask
)
6766 mode
, smask
, reg
, next_select
);
6769 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6770 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6771 return force_to_mode (plus_constant (XEXP (x
, 0),
6772 (INTVAL (XEXP (x
, 1))
6774 mode
, smask
, reg
, next_select
);
6778 /* ... fall through ... */
6781 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6782 most significant bit in MASK since carries from those bits will
6783 affect the bits we are interested in. */
6788 /* If X is (minus C Y) where C's least set bit is larger than any bit
6789 in the mask, then we may replace with (neg Y). */
6790 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6791 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6792 & -INTVAL (XEXP (x
, 0))))
6795 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6797 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6800 /* Similarly, if C contains every bit in the mask, then we may
6801 replace with (not Y). */
6802 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6803 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6804 == INTVAL (XEXP (x
, 0))))
6806 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6807 XEXP (x
, 1), GET_MODE (x
));
6808 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6816 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6817 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6818 operation which may be a bitfield extraction. Ensure that the
6819 constant we form is not wider than the mode of X. */
6821 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6822 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6823 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6824 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6825 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6826 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6827 + floor_log2 (INTVAL (XEXP (x
, 1))))
6828 < GET_MODE_BITSIZE (GET_MODE (x
)))
6829 && (INTVAL (XEXP (x
, 1))
6830 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6832 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6833 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6834 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6835 XEXP (XEXP (x
, 0), 0), temp
);
6836 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6837 XEXP (XEXP (x
, 0), 1));
6838 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6842 /* For most binary operations, just propagate into the operation and
6843 change the mode if we have an operation of that mode. */
6845 op0
= gen_lowpart_for_combine (op_mode
,
6846 force_to_mode (XEXP (x
, 0), mode
, mask
,
6848 op1
= gen_lowpart_for_combine (op_mode
,
6849 force_to_mode (XEXP (x
, 1), mode
, mask
,
6852 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6853 MASK since OP1 might have been sign-extended but we never want
6854 to turn on extra bits, since combine might have previously relied
6855 on them being off. */
6856 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6857 && (INTVAL (op1
) & mask
) != 0)
6858 op1
= GEN_INT (INTVAL (op1
) & mask
);
6860 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6861 x
= gen_binary (code
, op_mode
, op0
, op1
);
6865 /* For left shifts, do the same, but just for the first operand.
6866 However, we cannot do anything with shifts where we cannot
6867 guarantee that the counts are smaller than the size of the mode
6868 because such a count will have a different meaning in a
6871 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6872 && INTVAL (XEXP (x
, 1)) >= 0
6873 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6874 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6875 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6876 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6879 /* If the shift count is a constant and we can do arithmetic in
6880 the mode of the shift, refine which bits we need. Otherwise, use the
6881 conservative form of the mask. */
6882 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6883 && INTVAL (XEXP (x
, 1)) >= 0
6884 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6885 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6886 mask
>>= INTVAL (XEXP (x
, 1));
6890 op0
= gen_lowpart_for_combine (op_mode
,
6891 force_to_mode (XEXP (x
, 0), op_mode
,
6892 mask
, reg
, next_select
));
6894 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6895 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6899 /* Here we can only do something if the shift count is a constant,
6900 this shift constant is valid for the host, and we can do arithmetic
6903 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6904 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6905 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6907 rtx inner
= XEXP (x
, 0);
6908 unsigned HOST_WIDE_INT inner_mask
;
6910 /* Select the mask of the bits we need for the shift operand. */
6911 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
6913 /* We can only change the mode of the shift if we can do arithmetic
6914 in the mode of the shift and INNER_MASK is no wider than the
6915 width of OP_MODE. */
6916 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6917 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
6918 op_mode
= GET_MODE (x
);
6920 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
6922 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6923 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6926 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6927 shift and AND produces only copies of the sign bit (C2 is one less
6928 than a power of two), we can do this with just a shift. */
6930 if (GET_CODE (x
) == LSHIFTRT
6931 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6932 /* The shift puts one of the sign bit copies in the least significant
6934 && ((INTVAL (XEXP (x
, 1))
6935 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6936 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6937 && exact_log2 (mask
+ 1) >= 0
6938 /* Number of bits left after the shift must be more than the mask
6940 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
6941 <= GET_MODE_BITSIZE (GET_MODE (x
)))
6942 /* Must be more sign bit copies than the mask needs. */
6943 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6944 >= exact_log2 (mask
+ 1)))
6945 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6946 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6947 - exact_log2 (mask
+ 1)));
6952 /* If we are just looking for the sign bit, we don't need this shift at
6953 all, even if it has a variable count. */
6954 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6955 && (mask
== ((unsigned HOST_WIDE_INT
) 1
6956 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6957 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6959 /* If this is a shift by a constant, get a mask that contains those bits
6960 that are not copies of the sign bit. We then have two cases: If
6961 MASK only includes those bits, this can be a logical shift, which may
6962 allow simplifications. If MASK is a single-bit field not within
6963 those bits, we are requesting a copy of the sign bit and hence can
6964 shift the sign bit to the appropriate location. */
6966 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6967 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6971 /* If the considered data is wider then HOST_WIDE_INT, we can't
6972 represent a mask for all its bits in a single scalar.
6973 But we only care about the lower bits, so calculate these. */
6975 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
6977 nonzero
= ~(HOST_WIDE_INT
) 0;
6979 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6980 is the number of bits a full-width mask would have set.
6981 We need only shift if these are fewer than nonzero can
6982 hold. If not, we must keep all bits set in nonzero. */
6984 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
6985 < HOST_BITS_PER_WIDE_INT
)
6986 nonzero
>>= INTVAL (XEXP (x
, 1))
6987 + HOST_BITS_PER_WIDE_INT
6988 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
6992 nonzero
= GET_MODE_MASK (GET_MODE (x
));
6993 nonzero
>>= INTVAL (XEXP (x
, 1));
6996 if ((mask
& ~nonzero
) == 0
6997 || (i
= exact_log2 (mask
)) >= 0)
6999 x
= simplify_shift_const
7000 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7001 i
< 0 ? INTVAL (XEXP (x
, 1))
7002 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7004 if (GET_CODE (x
) != ASHIFTRT
)
7005 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7009 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7010 even if the shift count isn't a constant. */
7012 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7016 /* If this is a zero- or sign-extension operation that just affects bits
7017 we don't care about, remove it. Be sure the call above returned
7018 something that is still a shift. */
7020 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7021 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7022 && INTVAL (XEXP (x
, 1)) >= 0
7023 && (INTVAL (XEXP (x
, 1))
7024 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7025 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7026 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7027 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7028 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7035 /* If the shift count is constant and we can do computations
7036 in the mode of X, compute where the bits we care about are.
7037 Otherwise, we can't do anything. Don't change the mode of
7038 the shift or propagate MODE into the shift, though. */
7039 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7040 && INTVAL (XEXP (x
, 1)) >= 0)
7042 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7043 GET_MODE (x
), GEN_INT (mask
),
7045 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7047 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7048 INTVAL (temp
), reg
, next_select
));
7053 /* If we just want the low-order bit, the NEG isn't needed since it
7054 won't change the low-order bit. */
7056 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7058 /* We need any bits less significant than the most significant bit in
7059 MASK since carries from those bits will affect the bits we are
7065 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7066 same as the XOR case above. Ensure that the constant we form is not
7067 wider than the mode of X. */
7069 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7070 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7071 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7072 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7073 < GET_MODE_BITSIZE (GET_MODE (x
)))
7074 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7076 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7077 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7078 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7080 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7083 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7084 use the full mask inside the NOT. */
7088 op0
= gen_lowpart_for_combine (op_mode
,
7089 force_to_mode (XEXP (x
, 0), mode
, mask
,
7091 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7092 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7096 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7097 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7098 which is equal to STORE_FLAG_VALUE. */
7099 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7100 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7101 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7102 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7107 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7108 written in a narrower mode. We play it safe and do not do so. */
7111 gen_lowpart_for_combine (GET_MODE (x
),
7112 force_to_mode (XEXP (x
, 1), mode
,
7113 mask
, reg
, next_select
)));
7115 gen_lowpart_for_combine (GET_MODE (x
),
7116 force_to_mode (XEXP (x
, 2), mode
,
7117 mask
, reg
,next_select
)));
7124 /* Ensure we return a value of the proper mode. */
7125 return gen_lowpart_for_combine (mode
, x
);
7128 /* Return nonzero if X is an expression that has one of two values depending on
7129 whether some other value is zero or nonzero. In that case, we return the
7130 value that is being tested, *PTRUE is set to the value if the rtx being
7131 returned has a nonzero value, and *PFALSE is set to the other alternative.
7133 If we return zero, we set *PTRUE and *PFALSE to X. */
7136 if_then_else_cond (x
, ptrue
, pfalse
)
7138 rtx
*ptrue
, *pfalse
;
7140 enum machine_mode mode
= GET_MODE (x
);
7141 enum rtx_code code
= GET_CODE (x
);
7142 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7143 unsigned HOST_WIDE_INT nz
;
7145 /* If we are comparing a value against zero, we are done. */
7146 if ((code
== NE
|| code
== EQ
)
7147 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7149 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7150 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7154 /* If this is a unary operation whose operand has one of two values, apply
7155 our opcode to compute those values. */
7156 else if (GET_RTX_CLASS (code
) == '1'
7157 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7159 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7160 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7161 GET_MODE (XEXP (x
, 0)));
7165 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7166 make can't possibly match and would suppress other optimizations. */
7167 else if (code
== COMPARE
)
7170 /* If this is a binary operation, see if either side has only one of two
7171 values. If either one does or if both do and they are conditional on
7172 the same value, compute the new true and false values. */
7173 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7174 || GET_RTX_CLASS (code
) == '<')
7176 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7177 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7179 if ((cond0
!= 0 || cond1
!= 0)
7180 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7182 /* If if_then_else_cond returned zero, then true/false are the
7183 same rtl. We must copy one of them to prevent invalid rtl
7186 true0
= copy_rtx (true0
);
7187 else if (cond1
== 0)
7188 true1
= copy_rtx (true1
);
7190 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7191 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7192 return cond0
? cond0
: cond1
;
7195 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7196 operands is zero when the other is non-zero, and vice-versa,
7197 and STORE_FLAG_VALUE is 1 or -1. */
7199 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7200 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7202 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7204 rtx op0
= XEXP (XEXP (x
, 0), 1);
7205 rtx op1
= XEXP (XEXP (x
, 1), 1);
7207 cond0
= XEXP (XEXP (x
, 0), 0);
7208 cond1
= XEXP (XEXP (x
, 1), 0);
7210 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7211 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7212 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7213 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7214 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7215 || ((swap_condition (GET_CODE (cond0
))
7216 == combine_reversed_comparison_code (cond1
))
7217 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7218 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7219 && ! side_effects_p (x
))
7221 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7222 *pfalse
= gen_binary (MULT
, mode
,
7224 ? simplify_gen_unary (NEG
, mode
, op1
,
7232 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7234 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7235 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7236 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7238 cond0
= XEXP (XEXP (x
, 0), 0);
7239 cond1
= XEXP (XEXP (x
, 1), 0);
7241 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7242 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7243 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7244 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7245 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7246 || ((swap_condition (GET_CODE (cond0
))
7247 == combine_reversed_comparison_code (cond1
))
7248 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7249 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7250 && ! side_effects_p (x
))
7252 *ptrue
= *pfalse
= const0_rtx
;
7258 else if (code
== IF_THEN_ELSE
)
7260 /* If we have IF_THEN_ELSE already, extract the condition and
7261 canonicalize it if it is NE or EQ. */
7262 cond0
= XEXP (x
, 0);
7263 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7264 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7265 return XEXP (cond0
, 0);
7266 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7268 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7269 return XEXP (cond0
, 0);
7275 /* If X is a SUBREG, we can narrow both the true and false values
7276 if the inner expression, if there is a condition. */
7277 else if (code
== SUBREG
7278 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7281 *ptrue
= simplify_gen_subreg (mode
, true0
,
7282 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7283 *pfalse
= simplify_gen_subreg (mode
, false0
,
7284 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7289 /* If X is a constant, this isn't special and will cause confusions
7290 if we treat it as such. Likewise if it is equivalent to a constant. */
7291 else if (CONSTANT_P (x
)
7292 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7295 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7296 will be least confusing to the rest of the compiler. */
7297 else if (mode
== BImode
)
7299 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7303 /* If X is known to be either 0 or -1, those are the true and
7304 false values when testing X. */
7305 else if (x
== constm1_rtx
|| x
== const0_rtx
7306 || (mode
!= VOIDmode
7307 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7309 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7313 /* Likewise for 0 or a single bit. */
7314 else if (mode
!= VOIDmode
7315 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7316 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7318 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7322 /* Otherwise fail; show no condition with true and false values the same. */
7323 *ptrue
= *pfalse
= x
;
7327 /* Return the value of expression X given the fact that condition COND
7328 is known to be true when applied to REG as its first operand and VAL
7329 as its second. X is known to not be shared and so can be modified in
7332 We only handle the simplest cases, and specifically those cases that
7333 arise with IF_THEN_ELSE expressions. */
7336 known_cond (x
, cond
, reg
, val
)
7341 enum rtx_code code
= GET_CODE (x
);
7346 if (side_effects_p (x
))
7349 if (cond
== EQ
&& rtx_equal_p (x
, reg
) && !FLOAT_MODE_P (cond
))
7351 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7354 /* If X is (abs REG) and we know something about REG's relationship
7355 with zero, we may be able to simplify this. */
7357 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7360 case GE
: case GT
: case EQ
:
7363 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7365 GET_MODE (XEXP (x
, 0)));
7370 /* The only other cases we handle are MIN, MAX, and comparisons if the
7371 operands are the same as REG and VAL. */
7373 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7375 if (rtx_equal_p (XEXP (x
, 0), val
))
7376 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7378 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7380 if (GET_RTX_CLASS (code
) == '<')
7382 if (comparison_dominates_p (cond
, code
))
7383 return const_true_rtx
;
7385 code
= combine_reversed_comparison_code (x
);
7387 && comparison_dominates_p (cond
, code
))
7392 else if (code
== SMAX
|| code
== SMIN
7393 || code
== UMIN
|| code
== UMAX
)
7395 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7397 /* Do not reverse the condition when it is NE or EQ.
7398 This is because we cannot conclude anything about
7399 the value of 'SMAX (x, y)' when x is not equal to y,
7400 but we can when x equals y. */
7401 if ((code
== SMAX
|| code
== UMAX
)
7402 && ! (cond
== EQ
|| cond
== NE
))
7403 cond
= reverse_condition (cond
);
7408 return unsignedp
? x
: XEXP (x
, 1);
7410 return unsignedp
? x
: XEXP (x
, 0);
7412 return unsignedp
? XEXP (x
, 1) : x
;
7414 return unsignedp
? XEXP (x
, 0) : x
;
7422 fmt
= GET_RTX_FORMAT (code
);
7423 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7426 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7427 else if (fmt
[i
] == 'E')
7428 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7429 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7436 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7437 assignment as a field assignment. */
7440 rtx_equal_for_field_assignment_p (x
, y
)
7444 if (x
== y
|| rtx_equal_p (x
, y
))
7447 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7450 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7451 Note that all SUBREGs of MEM are paradoxical; otherwise they
7452 would have been rewritten. */
7453 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7454 && GET_CODE (SUBREG_REG (y
)) == MEM
7455 && rtx_equal_p (SUBREG_REG (y
),
7456 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7459 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7460 && GET_CODE (SUBREG_REG (x
)) == MEM
7461 && rtx_equal_p (SUBREG_REG (x
),
7462 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7465 /* We used to see if get_last_value of X and Y were the same but that's
7466 not correct. In one direction, we'll cause the assignment to have
7467 the wrong destination and in the case, we'll import a register into this
7468 insn that might have already have been dead. So fail if none of the
7469 above cases are true. */
7473 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7474 Return that assignment if so.
7476 We only handle the most common cases. */
7479 make_field_assignment (x
)
7482 rtx dest
= SET_DEST (x
);
7483 rtx src
= SET_SRC (x
);
7488 unsigned HOST_WIDE_INT len
;
7490 enum machine_mode mode
;
7492 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7493 a clear of a one-bit field. We will have changed it to
7494 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7497 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7498 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7499 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7500 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7502 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7505 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7509 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7510 && subreg_lowpart_p (XEXP (src
, 0))
7511 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7512 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7513 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7514 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7515 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7517 assign
= make_extraction (VOIDmode
, dest
, 0,
7518 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7521 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7525 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7527 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7528 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7529 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7531 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7534 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7538 /* The other case we handle is assignments into a constant-position
7539 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7540 a mask that has all one bits except for a group of zero bits and
7541 OTHER is known to have zeros where C1 has ones, this is such an
7542 assignment. Compute the position and length from C1. Shift OTHER
7543 to the appropriate position, force it to the required mode, and
7544 make the extraction. Check for the AND in both operands. */
7546 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7549 rhs
= expand_compound_operation (XEXP (src
, 0));
7550 lhs
= expand_compound_operation (XEXP (src
, 1));
7552 if (GET_CODE (rhs
) == AND
7553 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7554 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7555 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7556 else if (GET_CODE (lhs
) == AND
7557 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7558 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7559 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7563 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7564 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7565 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7566 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7569 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7573 /* The mode to use for the source is the mode of the assignment, or of
7574 what is inside a possible STRICT_LOW_PART. */
7575 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7576 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7578 /* Shift OTHER right POS places and make it the source, restricting it
7579 to the proper length and mode. */
7581 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7582 GET_MODE (src
), other
, pos
),
7584 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7585 ? ~(unsigned HOST_WIDE_INT
) 0
7586 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7589 return gen_rtx_SET (VOIDmode
, assign
, src
);
7592 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7596 apply_distributive_law (x
)
7599 enum rtx_code code
= GET_CODE (x
);
7600 rtx lhs
, rhs
, other
;
7602 enum rtx_code inner_code
;
7604 /* Distributivity is not true for floating point.
7605 It can change the value. So don't do it.
7606 -- rms and moshier@world.std.com. */
7607 if (FLOAT_MODE_P (GET_MODE (x
)))
7610 /* The outer operation can only be one of the following: */
7611 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7612 && code
!= PLUS
&& code
!= MINUS
)
7615 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7617 /* If either operand is a primitive we can't do anything, so get out
7619 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7620 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7623 lhs
= expand_compound_operation (lhs
);
7624 rhs
= expand_compound_operation (rhs
);
7625 inner_code
= GET_CODE (lhs
);
7626 if (inner_code
!= GET_CODE (rhs
))
7629 /* See if the inner and outer operations distribute. */
7636 /* These all distribute except over PLUS. */
7637 if (code
== PLUS
|| code
== MINUS
)
7642 if (code
!= PLUS
&& code
!= MINUS
)
7647 /* This is also a multiply, so it distributes over everything. */
7651 /* Non-paradoxical SUBREGs distributes over all operations, provided
7652 the inner modes and byte offsets are the same, this is an extraction
7653 of a low-order part, we don't convert an fp operation to int or
7654 vice versa, and we would not be converting a single-word
7655 operation into a multi-word operation. The latter test is not
7656 required, but it prevents generating unneeded multi-word operations.
7657 Some of the previous tests are redundant given the latter test, but
7658 are retained because they are required for correctness.
7660 We produce the result slightly differently in this case. */
7662 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7663 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7664 || ! subreg_lowpart_p (lhs
)
7665 || (GET_MODE_CLASS (GET_MODE (lhs
))
7666 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7667 || (GET_MODE_SIZE (GET_MODE (lhs
))
7668 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7669 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7672 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7673 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7674 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7680 /* Set LHS and RHS to the inner operands (A and B in the example
7681 above) and set OTHER to the common operand (C in the example).
7682 These is only one way to do this unless the inner operation is
7684 if (GET_RTX_CLASS (inner_code
) == 'c'
7685 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7686 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7687 else if (GET_RTX_CLASS (inner_code
) == 'c'
7688 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7689 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7690 else if (GET_RTX_CLASS (inner_code
) == 'c'
7691 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7692 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7693 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7694 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7698 /* Form the new inner operation, seeing if it simplifies first. */
7699 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7701 /* There is one exception to the general way of distributing:
7702 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7703 if (code
== XOR
&& inner_code
== IOR
)
7706 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7709 /* We may be able to continuing distributing the result, so call
7710 ourselves recursively on the inner operation before forming the
7711 outer operation, which we return. */
7712 return gen_binary (inner_code
, GET_MODE (x
),
7713 apply_distributive_law (tem
), other
);
7716 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7719 Return an equivalent form, if different from X. Otherwise, return X. If
7720 X is zero, we are to always construct the equivalent form. */
7723 simplify_and_const_int (x
, mode
, varop
, constop
)
7725 enum machine_mode mode
;
7727 unsigned HOST_WIDE_INT constop
;
7729 unsigned HOST_WIDE_INT nonzero
;
7732 /* Simplify VAROP knowing that we will be only looking at some of the
7734 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7736 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7737 CONST_INT, we are done. */
7738 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7741 /* See what bits may be nonzero in VAROP. Unlike the general case of
7742 a call to nonzero_bits, here we don't care about bits outside
7745 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7746 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7748 /* Turn off all bits in the constant that are known to already be zero.
7749 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7750 which is tested below. */
7754 /* If we don't have any bits left, return zero. */
7758 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7759 a power of two, we can replace this with a ASHIFT. */
7760 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7761 && (i
= exact_log2 (constop
)) >= 0)
7762 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7764 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7765 or XOR, then try to apply the distributive law. This may eliminate
7766 operations if either branch can be simplified because of the AND.
7767 It may also make some cases more complex, but those cases probably
7768 won't match a pattern either with or without this. */
7770 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7772 gen_lowpart_for_combine
7774 apply_distributive_law
7775 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7776 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7777 XEXP (varop
, 0), constop
),
7778 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7779 XEXP (varop
, 1), constop
))));
7781 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7782 if we already had one (just check for the simplest cases). */
7783 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7784 && GET_MODE (XEXP (x
, 0)) == mode
7785 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7786 varop
= XEXP (x
, 0);
7788 varop
= gen_lowpart_for_combine (mode
, varop
);
7790 /* If we can't make the SUBREG, try to return what we were given. */
7791 if (GET_CODE (varop
) == CLOBBER
)
7792 return x
? x
: varop
;
7794 /* If we are only masking insignificant bits, return VAROP. */
7795 if (constop
== nonzero
)
7798 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7799 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7800 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7804 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7805 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7806 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7808 SUBST (XEXP (x
, 0), varop
);
7814 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7815 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7816 is less useful. We can't allow both, because that results in exponential
7817 run time recursion. There is a nullstone testcase that triggered
7818 this. This macro avoids accidental uses of num_sign_bit_copies. */
7819 #define num_sign_bit_copies()
7821 /* Given an expression, X, compute which bits in X can be non-zero.
7822 We don't care about bits outside of those defined in MODE.
7824 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7825 a shift, AND, or zero_extract, we can do better. */
7827 static unsigned HOST_WIDE_INT
7828 nonzero_bits (x
, mode
)
7830 enum machine_mode mode
;
7832 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7833 unsigned HOST_WIDE_INT inner_nz
;
7835 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
7838 /* For floating-point values, assume all bits are needed. */
7839 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7842 /* If X is wider than MODE, use its mode instead. */
7843 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7845 mode
= GET_MODE (x
);
7846 nonzero
= GET_MODE_MASK (mode
);
7847 mode_width
= GET_MODE_BITSIZE (mode
);
7850 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7851 /* Our only callers in this case look for single bit values. So
7852 just return the mode mask. Those tests will then be false. */
7855 #ifndef WORD_REGISTER_OPERATIONS
7856 /* If MODE is wider than X, but both are a single word for both the host
7857 and target machines, we can compute this from which bits of the
7858 object might be nonzero in its own mode, taking into account the fact
7859 that on many CISC machines, accessing an object in a wider mode
7860 causes the high-order bits to become undefined. So they are
7861 not known to be zero. */
7863 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7864 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7865 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7866 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
7868 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
7869 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
7874 code
= GET_CODE (x
);
7878 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
7879 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7880 all the bits above ptr_mode are known to be zero. */
7881 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
7883 nonzero
&= GET_MODE_MASK (ptr_mode
);
7886 #ifdef STACK_BOUNDARY
7887 /* If this is the stack pointer, we may know something about its
7888 alignment. If PUSH_ROUNDING is defined, it is possible for the
7889 stack to be momentarily aligned only to that amount, so we pick
7890 the least alignment. */
7892 /* We can't check for arg_pointer_rtx here, because it is not
7893 guaranteed to have as much alignment as the stack pointer.
7894 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7895 alignment but the argument pointer has only 64 bit alignment. */
7897 if ((x
== frame_pointer_rtx
7898 || x
== stack_pointer_rtx
7899 || x
== hard_frame_pointer_rtx
7900 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
7901 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
7907 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7909 #ifdef PUSH_ROUNDING
7910 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
7911 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
7914 /* We must return here, otherwise we may get a worse result from
7915 one of the choices below. There is nothing useful below as
7916 far as the stack pointer is concerned. */
7917 return nonzero
&= ~(sp_alignment
- 1);
7921 /* If X is a register whose nonzero bits value is current, use it.
7922 Otherwise, if X is a register whose value we can find, use that
7923 value. Otherwise, use the previously-computed global nonzero bits
7924 for this register. */
7926 if (reg_last_set_value
[REGNO (x
)] != 0
7927 && reg_last_set_mode
[REGNO (x
)] == mode
7928 && (reg_last_set_label
[REGNO (x
)] == label_tick
7929 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
7930 && REG_N_SETS (REGNO (x
)) == 1
7931 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
7933 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7934 return reg_last_set_nonzero_bits
[REGNO (x
)];
7936 tem
= get_last_value (x
);
7940 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7941 /* If X is narrower than MODE and TEM is a non-negative
7942 constant that would appear negative in the mode of X,
7943 sign-extend it for use in reg_nonzero_bits because some
7944 machines (maybe most) will actually do the sign-extension
7945 and this is the conservative approach.
7947 ??? For 2.5, try to tighten up the MD files in this regard
7948 instead of this kludge. */
7950 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7951 && GET_CODE (tem
) == CONST_INT
7953 && 0 != (INTVAL (tem
)
7954 & ((HOST_WIDE_INT
) 1
7955 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7956 tem
= GEN_INT (INTVAL (tem
)
7957 | ((HOST_WIDE_INT
) (-1)
7958 << GET_MODE_BITSIZE (GET_MODE (x
))));
7960 return nonzero_bits (tem
, mode
);
7962 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7963 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
7968 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7969 /* If X is negative in MODE, sign-extend the value. */
7970 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
7971 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
7972 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
7978 #ifdef LOAD_EXTEND_OP
7979 /* In many, if not most, RISC machines, reading a byte from memory
7980 zeros the rest of the register. Noticing that fact saves a lot
7981 of extra zero-extends. */
7982 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
7983 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
7988 case UNEQ
: case LTGT
:
7989 case GT
: case GTU
: case UNGT
:
7990 case LT
: case LTU
: case UNLT
:
7991 case GE
: case GEU
: case UNGE
:
7992 case LE
: case LEU
: case UNLE
:
7993 case UNORDERED
: case ORDERED
:
7995 /* If this produces an integer result, we know which bits are set.
7996 Code here used to clear bits outside the mode of X, but that is
7999 if (GET_MODE_CLASS (mode
) == MODE_INT
8000 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8001 nonzero
= STORE_FLAG_VALUE
;
8006 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8007 and num_sign_bit_copies. */
8008 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8009 == GET_MODE_BITSIZE (GET_MODE (x
)))
8013 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8014 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8019 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8020 and num_sign_bit_copies. */
8021 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8022 == GET_MODE_BITSIZE (GET_MODE (x
)))
8028 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8032 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8033 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8034 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8038 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8039 Otherwise, show all the bits in the outer mode but not the inner
8041 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8042 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8044 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8046 & (((HOST_WIDE_INT
) 1
8047 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8048 inner_nz
|= (GET_MODE_MASK (mode
)
8049 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8052 nonzero
&= inner_nz
;
8056 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8057 & nonzero_bits (XEXP (x
, 1), mode
));
8061 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8062 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8063 | nonzero_bits (XEXP (x
, 1), mode
));
8066 case PLUS
: case MINUS
:
8068 case DIV
: case UDIV
:
8069 case MOD
: case UMOD
:
8070 /* We can apply the rules of arithmetic to compute the number of
8071 high- and low-order zero bits of these operations. We start by
8072 computing the width (position of the highest-order non-zero bit)
8073 and the number of low-order zero bits for each value. */
8075 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8076 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8077 int width0
= floor_log2 (nz0
) + 1;
8078 int width1
= floor_log2 (nz1
) + 1;
8079 int low0
= floor_log2 (nz0
& -nz0
);
8080 int low1
= floor_log2 (nz1
& -nz1
);
8081 HOST_WIDE_INT op0_maybe_minusp
8082 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8083 HOST_WIDE_INT op1_maybe_minusp
8084 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8085 unsigned int result_width
= mode_width
;
8093 && (XEXP (x
, 0) == stack_pointer_rtx
8094 || XEXP (x
, 0) == frame_pointer_rtx
)
8095 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8097 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8099 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8100 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8101 width0
= floor_log2 (nz0
) + 1;
8102 width1
= floor_log2 (nz1
) + 1;
8103 low0
= floor_log2 (nz0
& -nz0
);
8104 low1
= floor_log2 (nz1
& -nz1
);
8107 result_width
= MAX (width0
, width1
) + 1;
8108 result_low
= MIN (low0
, low1
);
8111 result_low
= MIN (low0
, low1
);
8114 result_width
= width0
+ width1
;
8115 result_low
= low0
+ low1
;
8120 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8121 result_width
= width0
;
8126 result_width
= width0
;
8131 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8132 result_width
= MIN (width0
, width1
);
8133 result_low
= MIN (low0
, low1
);
8138 result_width
= MIN (width0
, width1
);
8139 result_low
= MIN (low0
, low1
);
8145 if (result_width
< mode_width
)
8146 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8149 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8151 #ifdef POINTERS_EXTEND_UNSIGNED
8152 /* If pointers extend unsigned and this is an addition or subtraction
8153 to a pointer in Pmode, all the bits above ptr_mode are known to be
8155 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8156 && (code
== PLUS
|| code
== MINUS
)
8157 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8158 nonzero
&= GET_MODE_MASK (ptr_mode
);
8164 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8165 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8166 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8170 /* If this is a SUBREG formed for a promoted variable that has
8171 been zero-extended, we know that at least the high-order bits
8172 are zero, though others might be too. */
8174 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8175 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8176 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8178 /* If the inner mode is a single word for both the host and target
8179 machines, we can compute this from which bits of the inner
8180 object might be nonzero. */
8181 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8182 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8183 <= HOST_BITS_PER_WIDE_INT
))
8185 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8187 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8188 /* If this is a typical RISC machine, we only have to worry
8189 about the way loads are extended. */
8190 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8192 & (((unsigned HOST_WIDE_INT
) 1
8193 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8195 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8198 /* On many CISC machines, accessing an object in a wider mode
8199 causes the high-order bits to become undefined. So they are
8200 not known to be zero. */
8201 if (GET_MODE_SIZE (GET_MODE (x
))
8202 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8203 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8204 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8213 /* The nonzero bits are in two classes: any bits within MODE
8214 that aren't in GET_MODE (x) are always significant. The rest of the
8215 nonzero bits are those that are significant in the operand of
8216 the shift when shifted the appropriate number of bits. This
8217 shows that high-order bits are cleared by the right shift and
8218 low-order bits by left shifts. */
8219 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8220 && INTVAL (XEXP (x
, 1)) >= 0
8221 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8223 enum machine_mode inner_mode
= GET_MODE (x
);
8224 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8225 int count
= INTVAL (XEXP (x
, 1));
8226 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8227 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8228 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8229 unsigned HOST_WIDE_INT outer
= 0;
8231 if (mode_width
> width
)
8232 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8234 if (code
== LSHIFTRT
)
8236 else if (code
== ASHIFTRT
)
8240 /* If the sign bit may have been nonzero before the shift, we
8241 need to mark all the places it could have been copied to
8242 by the shift as possibly nonzero. */
8243 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8244 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8246 else if (code
== ASHIFT
)
8249 inner
= ((inner
<< (count
% width
)
8250 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8252 nonzero
&= (outer
| inner
);
8257 /* This is at most the number of bits in the mode. */
8258 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8262 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8263 | nonzero_bits (XEXP (x
, 2), mode
));
8273 /* See the macro definition above. */
8274 #undef num_sign_bit_copies
8276 /* Return the number of bits at the high-order end of X that are known to
8277 be equal to the sign bit. X will be used in mode MODE; if MODE is
8278 VOIDmode, X will be used in its own mode. The returned value will always
8279 be between 1 and the number of bits in MODE. */
8282 num_sign_bit_copies (x
, mode
)
8284 enum machine_mode mode
;
8286 enum rtx_code code
= GET_CODE (x
);
8287 unsigned int bitwidth
;
8288 int num0
, num1
, result
;
8289 unsigned HOST_WIDE_INT nonzero
;
8292 /* If we weren't given a mode, use the mode of X. If the mode is still
8293 VOIDmode, we don't know anything. Likewise if one of the modes is
8296 if (mode
== VOIDmode
)
8297 mode
= GET_MODE (x
);
8299 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8302 bitwidth
= GET_MODE_BITSIZE (mode
);
8304 /* For a smaller object, just ignore the high bits. */
8305 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8307 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8309 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8312 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8314 #ifndef WORD_REGISTER_OPERATIONS
8315 /* If this machine does not do all register operations on the entire
8316 register and MODE is wider than the mode of X, we can say nothing
8317 at all about the high-order bits. */
8320 /* Likewise on machines that do, if the mode of the object is smaller
8321 than a word and loads of that size don't sign extend, we can say
8322 nothing about the high order bits. */
8323 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8324 #ifdef LOAD_EXTEND_OP
8325 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8336 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8337 /* If pointers extend signed and this is a pointer in Pmode, say that
8338 all the bits above ptr_mode are known to be sign bit copies. */
8339 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8341 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8344 if (reg_last_set_value
[REGNO (x
)] != 0
8345 && reg_last_set_mode
[REGNO (x
)] == mode
8346 && (reg_last_set_label
[REGNO (x
)] == label_tick
8347 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8348 && REG_N_SETS (REGNO (x
)) == 1
8349 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8351 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8352 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8354 tem
= get_last_value (x
);
8356 return num_sign_bit_copies (tem
, mode
);
8358 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8359 return reg_sign_bit_copies
[REGNO (x
)];
8363 #ifdef LOAD_EXTEND_OP
8364 /* Some RISC machines sign-extend all loads of smaller than a word. */
8365 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8366 return MAX (1, ((int) bitwidth
8367 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8372 /* If the constant is negative, take its 1's complement and remask.
8373 Then see how many zero bits we have. */
8374 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8375 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8376 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8377 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8379 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8382 /* If this is a SUBREG for a promoted object that is sign-extended
8383 and we are looking at it in a wider mode, we know that at least the
8384 high-order bits are known to be sign bit copies. */
8386 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8388 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8389 return MAX ((int) bitwidth
8390 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8394 /* For a smaller object, just ignore the high bits. */
8395 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8397 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8398 return MAX (1, (num0
8399 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8403 #ifdef WORD_REGISTER_OPERATIONS
8404 #ifdef LOAD_EXTEND_OP
8405 /* For paradoxical SUBREGs on machines where all register operations
8406 affect the entire register, just look inside. Note that we are
8407 passing MODE to the recursive call, so the number of sign bit copies
8408 will remain relative to that mode, not the inner mode. */
8410 /* This works only if loads sign extend. Otherwise, if we get a
8411 reload for the inner part, it may be loaded from the stack, and
8412 then we lose all sign bit copies that existed before the store
8415 if ((GET_MODE_SIZE (GET_MODE (x
))
8416 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8417 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8418 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8424 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8425 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8429 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8430 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8433 /* For a smaller object, just ignore the high bits. */
8434 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8435 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8439 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8441 case ROTATE
: case ROTATERT
:
8442 /* If we are rotating left by a number of bits less than the number
8443 of sign bit copies, we can just subtract that amount from the
8445 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8446 && INTVAL (XEXP (x
, 1)) >= 0
8447 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8449 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8450 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8451 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8456 /* In general, this subtracts one sign bit copy. But if the value
8457 is known to be positive, the number of sign bit copies is the
8458 same as that of the input. Finally, if the input has just one bit
8459 that might be nonzero, all the bits are copies of the sign bit. */
8460 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8461 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8462 return num0
> 1 ? num0
- 1 : 1;
8464 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8469 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8474 case IOR
: case AND
: case XOR
:
8475 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8476 /* Logical operations will preserve the number of sign-bit copies.
8477 MIN and MAX operations always return one of the operands. */
8478 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8479 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8480 return MIN (num0
, num1
);
8482 case PLUS
: case MINUS
:
8483 /* For addition and subtraction, we can have a 1-bit carry. However,
8484 if we are subtracting 1 from a positive number, there will not
8485 be such a carry. Furthermore, if the positive number is known to
8486 be 0 or 1, we know the result is either -1 or 0. */
8488 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8489 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8491 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8492 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8493 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8494 : bitwidth
- floor_log2 (nonzero
) - 1);
8497 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8498 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8499 result
= MAX (1, MIN (num0
, num1
) - 1);
8501 #ifdef POINTERS_EXTEND_UNSIGNED
8502 /* If pointers extend signed and this is an addition or subtraction
8503 to a pointer in Pmode, all the bits above ptr_mode are known to be
8505 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8506 && (code
== PLUS
|| code
== MINUS
)
8507 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8508 result
= MAX ((GET_MODE_BITSIZE (Pmode
)
8509 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8515 /* The number of bits of the product is the sum of the number of
8516 bits of both terms. However, unless one of the terms if known
8517 to be positive, we must allow for an additional bit since negating
8518 a negative number can remove one sign bit copy. */
8520 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8521 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8523 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8525 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8526 || (((nonzero_bits (XEXP (x
, 0), mode
)
8527 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8528 && ((nonzero_bits (XEXP (x
, 1), mode
)
8529 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8532 return MAX (1, result
);
8535 /* The result must be <= the first operand. If the first operand
8536 has the high bit set, we know nothing about the number of sign
8538 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8540 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8541 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8544 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8547 /* The result must be <= the scond operand. */
8548 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8551 /* Similar to unsigned division, except that we have to worry about
8552 the case where the divisor is negative, in which case we have
8554 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8556 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8557 || (nonzero_bits (XEXP (x
, 1), mode
)
8558 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8564 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8566 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8567 || (nonzero_bits (XEXP (x
, 1), mode
)
8568 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8574 /* Shifts by a constant add to the number of bits equal to the
8576 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8577 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8578 && INTVAL (XEXP (x
, 1)) > 0)
8579 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8584 /* Left shifts destroy copies. */
8585 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8586 || INTVAL (XEXP (x
, 1)) < 0
8587 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8590 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8591 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8594 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8595 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8596 return MIN (num0
, num1
);
8598 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8599 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8600 case GEU
: case GTU
: case LEU
: case LTU
:
8601 case UNORDERED
: case ORDERED
:
8602 /* If the constant is negative, take its 1's complement and remask.
8603 Then see how many zero bits we have. */
8604 nonzero
= STORE_FLAG_VALUE
;
8605 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8606 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8607 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8609 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8616 /* If we haven't been able to figure it out by one of the above rules,
8617 see if some of the high-order bits are known to be zero. If so,
8618 count those bits and return one less than that amount. If we can't
8619 safely compute the mask for this mode, always return BITWIDTH. */
8621 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8624 nonzero
= nonzero_bits (x
, mode
);
8625 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8626 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8629 /* Return the number of "extended" bits there are in X, when interpreted
8630 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8631 unsigned quantities, this is the number of high-order zero bits.
8632 For signed quantities, this is the number of copies of the sign bit
8633 minus 1. In both case, this function returns the number of "spare"
8634 bits. For example, if two quantities for which this function returns
8635 at least 1 are added, the addition is known not to overflow.
8637 This function will always return 0 unless called during combine, which
8638 implies that it must be called from a define_split. */
8641 extended_count (x
, mode
, unsignedp
)
8643 enum machine_mode mode
;
8646 if (nonzero_sign_valid
== 0)
8650 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8651 ? (GET_MODE_BITSIZE (mode
) - 1
8652 - floor_log2 (nonzero_bits (x
, mode
)))
8654 : num_sign_bit_copies (x
, mode
) - 1);
8657 /* This function is called from `simplify_shift_const' to merge two
8658 outer operations. Specifically, we have already found that we need
8659 to perform operation *POP0 with constant *PCONST0 at the outermost
8660 position. We would now like to also perform OP1 with constant CONST1
8661 (with *POP0 being done last).
8663 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8664 the resulting operation. *PCOMP_P is set to 1 if we would need to
8665 complement the innermost operand, otherwise it is unchanged.
8667 MODE is the mode in which the operation will be done. No bits outside
8668 the width of this mode matter. It is assumed that the width of this mode
8669 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8671 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8672 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8673 result is simply *PCONST0.
8675 If the resulting operation cannot be expressed as one operation, we
8676 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8679 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8680 enum rtx_code
*pop0
;
8681 HOST_WIDE_INT
*pconst0
;
8683 HOST_WIDE_INT const1
;
8684 enum machine_mode mode
;
8687 enum rtx_code op0
= *pop0
;
8688 HOST_WIDE_INT const0
= *pconst0
;
8690 const0
&= GET_MODE_MASK (mode
);
8691 const1
&= GET_MODE_MASK (mode
);
8693 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8697 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8700 if (op1
== NIL
|| op0
== SET
)
8703 else if (op0
== NIL
)
8704 op0
= op1
, const0
= const1
;
8706 else if (op0
== op1
)
8730 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8731 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8734 /* If the two constants aren't the same, we can't do anything. The
8735 remaining six cases can all be done. */
8736 else if (const0
!= const1
)
8744 /* (a & b) | b == b */
8746 else /* op1 == XOR */
8747 /* (a ^ b) | b == a | b */
8753 /* (a & b) ^ b == (~a) & b */
8754 op0
= AND
, *pcomp_p
= 1;
8755 else /* op1 == IOR */
8756 /* (a | b) ^ b == a & ~b */
8757 op0
= AND
, *pconst0
= ~const0
;
8762 /* (a | b) & b == b */
8764 else /* op1 == XOR */
8765 /* (a ^ b) & b) == (~a) & b */
8772 /* Check for NO-OP cases. */
8773 const0
&= GET_MODE_MASK (mode
);
8775 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8777 else if (const0
== 0 && op0
== AND
)
8779 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8783 /* ??? Slightly redundant with the above mask, but not entirely.
8784 Moving this above means we'd have to sign-extend the mode mask
8785 for the final test. */
8786 const0
= trunc_int_for_mode (const0
, mode
);
8794 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8795 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8796 that we started with.
8798 The shift is normally computed in the widest mode we find in VAROP, as
8799 long as it isn't a different number of words than RESULT_MODE. Exceptions
8800 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8803 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8806 enum machine_mode result_mode
;
8810 enum rtx_code orig_code
= code
;
8811 int orig_count
= input_count
;
8814 enum machine_mode mode
= result_mode
;
8815 enum machine_mode shift_mode
, tmode
;
8816 unsigned int mode_words
8817 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8818 /* We form (outer_op (code varop count) (outer_const)). */
8819 enum rtx_code outer_op
= NIL
;
8820 HOST_WIDE_INT outer_const
= 0;
8822 int complement_p
= 0;
8825 /* If we were given an invalid count, don't do anything except exactly
8826 what was requested. */
8828 if (input_count
< 0 || input_count
> (int) GET_MODE_BITSIZE (mode
))
8833 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8836 count
= input_count
;
8838 /* Make sure and truncate the "natural" shift on the way in. We don't
8839 want to do this inside the loop as it makes it more difficult to
8841 #ifdef SHIFT_COUNT_TRUNCATED
8842 if (SHIFT_COUNT_TRUNCATED
)
8843 count
%= GET_MODE_BITSIZE (mode
);
8846 /* Unless one of the branches of the `if' in this loop does a `continue',
8847 we will `break' the loop after the `if'. */
8851 /* If we have an operand of (clobber (const_int 0)), just return that
8853 if (GET_CODE (varop
) == CLOBBER
)
8856 /* If we discovered we had to complement VAROP, leave. Making a NOT
8857 here would cause an infinite loop. */
8861 /* Convert ROTATERT to ROTATE. */
8862 if (code
== ROTATERT
)
8863 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8865 /* We need to determine what mode we will do the shift in. If the
8866 shift is a right shift or a ROTATE, we must always do it in the mode
8867 it was originally done in. Otherwise, we can do it in MODE, the
8868 widest mode encountered. */
8870 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8871 ? result_mode
: mode
);
8873 /* Handle cases where the count is greater than the size of the mode
8874 minus 1. For ASHIFT, use the size minus one as the count (this can
8875 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8876 take the count modulo the size. For other shifts, the result is
8879 Since these shifts are being produced by the compiler by combining
8880 multiple operations, each of which are defined, we know what the
8881 result is supposed to be. */
8883 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8885 if (code
== ASHIFTRT
)
8886 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8887 else if (code
== ROTATE
|| code
== ROTATERT
)
8888 count
%= GET_MODE_BITSIZE (shift_mode
);
8891 /* We can't simply return zero because there may be an
8899 /* An arithmetic right shift of a quantity known to be -1 or 0
8901 if (code
== ASHIFTRT
8902 && (num_sign_bit_copies (varop
, shift_mode
)
8903 == GET_MODE_BITSIZE (shift_mode
)))
8909 /* If we are doing an arithmetic right shift and discarding all but
8910 the sign bit copies, this is equivalent to doing a shift by the
8911 bitsize minus one. Convert it into that shift because it will often
8912 allow other simplifications. */
8914 if (code
== ASHIFTRT
8915 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8916 >= GET_MODE_BITSIZE (shift_mode
)))
8917 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8919 /* We simplify the tests below and elsewhere by converting
8920 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8921 `make_compound_operation' will convert it to a ASHIFTRT for
8922 those machines (such as VAX) that don't have a LSHIFTRT. */
8923 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8925 && ((nonzero_bits (varop
, shift_mode
)
8926 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8930 switch (GET_CODE (varop
))
8936 new = expand_compound_operation (varop
);
8945 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8946 minus the width of a smaller mode, we can do this with a
8947 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8948 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8949 && ! mode_dependent_address_p (XEXP (varop
, 0))
8950 && ! MEM_VOLATILE_P (varop
)
8951 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8952 MODE_INT
, 1)) != BLKmode
)
8954 new = adjust_address_nv (varop
, tmode
,
8955 BYTES_BIG_ENDIAN
? 0
8956 : count
/ BITS_PER_UNIT
);
8958 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8959 : ZERO_EXTEND
, mode
, new);
8966 /* Similar to the case above, except that we can only do this if
8967 the resulting mode is the same as that of the underlying
8968 MEM and adjust the address depending on the *bits* endianness
8969 because of the way that bit-field extract insns are defined. */
8970 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8971 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8972 MODE_INT
, 1)) != BLKmode
8973 && tmode
== GET_MODE (XEXP (varop
, 0)))
8975 if (BITS_BIG_ENDIAN
)
8976 new = XEXP (varop
, 0);
8979 new = copy_rtx (XEXP (varop
, 0));
8980 SUBST (XEXP (new, 0),
8981 plus_constant (XEXP (new, 0),
8982 count
/ BITS_PER_UNIT
));
8985 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8986 : ZERO_EXTEND
, mode
, new);
8993 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8994 the same number of words as what we've seen so far. Then store
8995 the widest mode in MODE. */
8996 if (subreg_lowpart_p (varop
)
8997 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8998 > GET_MODE_SIZE (GET_MODE (varop
)))
8999 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9000 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9003 varop
= SUBREG_REG (varop
);
9004 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9005 mode
= GET_MODE (varop
);
9011 /* Some machines use MULT instead of ASHIFT because MULT
9012 is cheaper. But it is still better on those machines to
9013 merge two shifts into one. */
9014 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9015 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9018 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9019 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9025 /* Similar, for when divides are cheaper. */
9026 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9027 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9030 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9031 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9037 /* If we are extracting just the sign bit of an arithmetic
9038 right shift, that shift is not needed. However, the sign
9039 bit of a wider mode may be different from what would be
9040 interpreted as the sign bit in a narrower mode, so, if
9041 the result is narrower, don't discard the shift. */
9042 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9043 && (GET_MODE_BITSIZE (result_mode
)
9044 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9046 varop
= XEXP (varop
, 0);
9050 /* ... fall through ... */
9055 /* Here we have two nested shifts. The result is usually the
9056 AND of a new shift with a mask. We compute the result below. */
9057 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9058 && INTVAL (XEXP (varop
, 1)) >= 0
9059 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9060 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9061 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9063 enum rtx_code first_code
= GET_CODE (varop
);
9064 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9065 unsigned HOST_WIDE_INT mask
;
9068 /* We have one common special case. We can't do any merging if
9069 the inner code is an ASHIFTRT of a smaller mode. However, if
9070 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9071 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9072 we can convert it to
9073 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9074 This simplifies certain SIGN_EXTEND operations. */
9075 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9076 && (GET_MODE_BITSIZE (result_mode
)
9077 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9079 /* C3 has the low-order C1 bits zero. */
9081 mask
= (GET_MODE_MASK (mode
)
9082 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9084 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9085 XEXP (varop
, 0), mask
);
9086 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9088 count
= first_count
;
9093 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9094 than C1 high-order bits equal to the sign bit, we can convert
9095 this to either an ASHIFT or a ASHIFTRT depending on the
9098 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9100 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9101 && GET_MODE (varop
) == shift_mode
9102 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9105 varop
= XEXP (varop
, 0);
9107 signed_count
= count
- first_count
;
9108 if (signed_count
< 0)
9109 count
= -signed_count
, code
= ASHIFT
;
9111 count
= signed_count
;
9116 /* There are some cases we can't do. If CODE is ASHIFTRT,
9117 we can only do this if FIRST_CODE is also ASHIFTRT.
9119 We can't do the case when CODE is ROTATE and FIRST_CODE is
9122 If the mode of this shift is not the mode of the outer shift,
9123 we can't do this if either shift is a right shift or ROTATE.
9125 Finally, we can't do any of these if the mode is too wide
9126 unless the codes are the same.
9128 Handle the case where the shift codes are the same
9131 if (code
== first_code
)
9133 if (GET_MODE (varop
) != result_mode
9134 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9138 count
+= first_count
;
9139 varop
= XEXP (varop
, 0);
9143 if (code
== ASHIFTRT
9144 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9145 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9146 || (GET_MODE (varop
) != result_mode
9147 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9148 || first_code
== ROTATE
9149 || code
== ROTATE
)))
9152 /* To compute the mask to apply after the shift, shift the
9153 nonzero bits of the inner shift the same way the
9154 outer shift will. */
9156 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9159 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9162 /* Give up if we can't compute an outer operation to use. */
9164 || GET_CODE (mask_rtx
) != CONST_INT
9165 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9167 result_mode
, &complement_p
))
9170 /* If the shifts are in the same direction, we add the
9171 counts. Otherwise, we subtract them. */
9172 signed_count
= count
;
9173 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9174 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9175 signed_count
+= first_count
;
9177 signed_count
-= first_count
;
9179 /* If COUNT is positive, the new shift is usually CODE,
9180 except for the two exceptions below, in which case it is
9181 FIRST_CODE. If the count is negative, FIRST_CODE should
9183 if (signed_count
> 0
9184 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9185 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9186 code
= first_code
, count
= signed_count
;
9187 else if (signed_count
< 0)
9188 code
= first_code
, count
= -signed_count
;
9190 count
= signed_count
;
9192 varop
= XEXP (varop
, 0);
9196 /* If we have (A << B << C) for any shift, we can convert this to
9197 (A << C << B). This wins if A is a constant. Only try this if
9198 B is not a constant. */
9200 else if (GET_CODE (varop
) == code
9201 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9203 = simplify_binary_operation (code
, mode
,
9207 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9214 /* Make this fit the case below. */
9215 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9216 GEN_INT (GET_MODE_MASK (mode
)));
9222 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9223 with C the size of VAROP - 1 and the shift is logical if
9224 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9225 we have an (le X 0) operation. If we have an arithmetic shift
9226 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9227 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9229 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9230 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9231 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9232 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9233 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9234 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9237 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9240 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9241 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9246 /* If we have (shift (logical)), move the logical to the outside
9247 to allow it to possibly combine with another logical and the
9248 shift to combine with another shift. This also canonicalizes to
9249 what a ZERO_EXTRACT looks like. Also, some machines have
9250 (and (shift)) insns. */
9252 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9253 && (new = simplify_binary_operation (code
, result_mode
,
9255 GEN_INT (count
))) != 0
9256 && GET_CODE (new) == CONST_INT
9257 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9258 INTVAL (new), result_mode
, &complement_p
))
9260 varop
= XEXP (varop
, 0);
9264 /* If we can't do that, try to simplify the shift in each arm of the
9265 logical expression, make a new logical expression, and apply
9266 the inverse distributive law. */
9268 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9269 XEXP (varop
, 0), count
);
9270 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9271 XEXP (varop
, 1), count
);
9273 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9274 varop
= apply_distributive_law (varop
);
9281 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9282 says that the sign bit can be tested, FOO has mode MODE, C is
9283 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9284 that may be nonzero. */
9285 if (code
== LSHIFTRT
9286 && XEXP (varop
, 1) == const0_rtx
9287 && GET_MODE (XEXP (varop
, 0)) == result_mode
9288 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9289 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9290 && ((STORE_FLAG_VALUE
9291 & ((HOST_WIDE_INT
) 1
9292 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9293 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9294 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9295 (HOST_WIDE_INT
) 1, result_mode
,
9298 varop
= XEXP (varop
, 0);
9305 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9306 than the number of bits in the mode is equivalent to A. */
9307 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9308 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9310 varop
= XEXP (varop
, 0);
9315 /* NEG commutes with ASHIFT since it is multiplication. Move the
9316 NEG outside to allow shifts to combine. */
9318 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9319 (HOST_WIDE_INT
) 0, result_mode
,
9322 varop
= XEXP (varop
, 0);
9328 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9329 is one less than the number of bits in the mode is
9330 equivalent to (xor A 1). */
9331 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9332 && XEXP (varop
, 1) == constm1_rtx
9333 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9334 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9335 (HOST_WIDE_INT
) 1, result_mode
,
9339 varop
= XEXP (varop
, 0);
9343 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9344 that might be nonzero in BAR are those being shifted out and those
9345 bits are known zero in FOO, we can replace the PLUS with FOO.
9346 Similarly in the other operand order. This code occurs when
9347 we are computing the size of a variable-size array. */
9349 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9350 && count
< HOST_BITS_PER_WIDE_INT
9351 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9352 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9353 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9355 varop
= XEXP (varop
, 0);
9358 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9359 && count
< HOST_BITS_PER_WIDE_INT
9360 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9361 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9363 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9364 & nonzero_bits (XEXP (varop
, 1),
9367 varop
= XEXP (varop
, 1);
9371 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9373 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9374 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9376 GEN_INT (count
))) != 0
9377 && GET_CODE (new) == CONST_INT
9378 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9379 INTVAL (new), result_mode
, &complement_p
))
9381 varop
= XEXP (varop
, 0);
9387 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9388 with C the size of VAROP - 1 and the shift is logical if
9389 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9390 we have a (gt X 0) operation. If the shift is arithmetic with
9391 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9392 we have a (neg (gt X 0)) operation. */
9394 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9395 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9396 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9397 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9398 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9399 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9400 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9403 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9406 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9407 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9414 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9415 if the truncate does not affect the value. */
9416 if (code
== LSHIFTRT
9417 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9418 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9419 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9420 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9421 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9423 rtx varop_inner
= XEXP (varop
, 0);
9426 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9427 XEXP (varop_inner
, 0),
9429 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9430 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9443 /* We need to determine what mode to do the shift in. If the shift is
9444 a right shift or ROTATE, we must always do it in the mode it was
9445 originally done in. Otherwise, we can do it in MODE, the widest mode
9446 encountered. The code we care about is that of the shift that will
9447 actually be done, not the shift that was originally requested. */
9449 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9450 ? result_mode
: mode
);
9452 /* We have now finished analyzing the shift. The result should be
9453 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9454 OUTER_OP is non-NIL, it is an operation that needs to be applied
9455 to the result of the shift. OUTER_CONST is the relevant constant,
9456 but we must turn off all bits turned off in the shift.
9458 If we were passed a value for X, see if we can use any pieces of
9459 it. If not, make new rtx. */
9461 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9462 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9463 && INTVAL (XEXP (x
, 1)) == count
)
9464 const_rtx
= XEXP (x
, 1);
9466 const_rtx
= GEN_INT (count
);
9468 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9469 && GET_MODE (XEXP (x
, 0)) == shift_mode
9470 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9471 varop
= XEXP (x
, 0);
9472 else if (GET_MODE (varop
) != shift_mode
)
9473 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9475 /* If we can't make the SUBREG, try to return what we were given. */
9476 if (GET_CODE (varop
) == CLOBBER
)
9477 return x
? x
: varop
;
9479 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9484 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9485 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9487 SUBST (XEXP (x
, 0), varop
);
9488 SUBST (XEXP (x
, 1), const_rtx
);
9491 /* If we have an outer operation and we just made a shift, it is
9492 possible that we could have simplified the shift were it not
9493 for the outer operation. So try to do the simplification
9496 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9497 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9498 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9499 INTVAL (XEXP (x
, 1)));
9501 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9502 turn off all the bits that the shift would have turned off. */
9503 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9504 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9505 GET_MODE_MASK (result_mode
) >> orig_count
);
9507 /* Do the remainder of the processing in RESULT_MODE. */
9508 x
= gen_lowpart_for_combine (result_mode
, x
);
9510 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9513 x
=simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9515 if (outer_op
!= NIL
)
9517 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9518 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9520 if (outer_op
== AND
)
9521 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9522 else if (outer_op
== SET
)
9523 /* This means that we have determined that the result is
9524 equivalent to a constant. This should be rare. */
9525 x
= GEN_INT (outer_const
);
9526 else if (GET_RTX_CLASS (outer_op
) == '1')
9527 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9529 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9535 /* Like recog, but we receive the address of a pointer to a new pattern.
9536 We try to match the rtx that the pointer points to.
9537 If that fails, we may try to modify or replace the pattern,
9538 storing the replacement into the same pointer object.
9540 Modifications include deletion or addition of CLOBBERs.
9542 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9543 the CLOBBERs are placed.
9545 The value is the final insn code from the pattern ultimately matched,
9549 recog_for_combine (pnewpat
, insn
, pnotes
)
9554 register rtx pat
= *pnewpat
;
9555 int insn_code_number
;
9556 int num_clobbers_to_add
= 0;
9561 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9562 we use to indicate that something didn't match. If we find such a
9563 thing, force rejection. */
9564 if (GET_CODE (pat
) == PARALLEL
)
9565 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9566 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9567 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9570 /* Remove the old notes prior to trying to recognize the new pattern. */
9571 old_notes
= REG_NOTES (insn
);
9572 REG_NOTES (insn
) = 0;
9574 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9576 /* If it isn't, there is the possibility that we previously had an insn
9577 that clobbered some register as a side effect, but the combined
9578 insn doesn't need to do that. So try once more without the clobbers
9579 unless this represents an ASM insn. */
9581 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9582 && GET_CODE (pat
) == PARALLEL
)
9586 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9587 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9590 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9594 SUBST_INT (XVECLEN (pat
, 0), pos
);
9597 pat
= XVECEXP (pat
, 0, 0);
9599 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9602 /* Recognize all noop sets, these will be killed by followup pass. */
9603 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9604 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9606 REG_NOTES (insn
) = old_notes
;
9608 /* If we had any clobbers to add, make a new pattern than contains
9609 them. Then check to make sure that all of them are dead. */
9610 if (num_clobbers_to_add
)
9612 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9613 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9615 + num_clobbers_to_add
)
9616 : num_clobbers_to_add
+ 1));
9618 if (GET_CODE (pat
) == PARALLEL
)
9619 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9620 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9622 XVECEXP (newpat
, 0, 0) = pat
;
9624 add_clobbers (newpat
, insn_code_number
);
9626 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9627 i
< XVECLEN (newpat
, 0); i
++)
9629 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9630 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9632 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9633 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9641 return insn_code_number
;
9644 /* Like gen_lowpart but for use by combine. In combine it is not possible
9645 to create any new pseudoregs. However, it is safe to create
9646 invalid memory addresses, because combine will try to recognize
9647 them and all they will do is make the combine attempt fail.
9649 If for some reason this cannot do its job, an rtx
9650 (clobber (const_int 0)) is returned.
9651 An insn containing that will not be recognized. */
9656 gen_lowpart_for_combine (mode
, x
)
9657 enum machine_mode mode
;
9662 if (GET_MODE (x
) == mode
)
9665 /* We can only support MODE being wider than a word if X is a
9666 constant integer or has a mode the same size. */
9668 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9669 && ! ((GET_MODE (x
) == VOIDmode
9670 && (GET_CODE (x
) == CONST_INT
9671 || GET_CODE (x
) == CONST_DOUBLE
))
9672 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9673 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9675 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9676 won't know what to do. So we will strip off the SUBREG here and
9677 process normally. */
9678 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9681 if (GET_MODE (x
) == mode
)
9685 result
= gen_lowpart_common (mode
, x
);
9686 #ifdef CLASS_CANNOT_CHANGE_MODE
9688 && GET_CODE (result
) == SUBREG
9689 && GET_CODE (SUBREG_REG (result
)) == REG
9690 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9691 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9692 GET_MODE (SUBREG_REG (result
))))
9693 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9699 if (GET_CODE (x
) == MEM
)
9701 register int offset
= 0;
9703 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9705 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9706 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9708 /* If we want to refer to something bigger than the original memref,
9709 generate a perverse subreg instead. That will force a reload
9710 of the original memref X. */
9711 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9712 return gen_rtx_SUBREG (mode
, x
, 0);
9714 if (WORDS_BIG_ENDIAN
)
9715 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9716 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9718 if (BYTES_BIG_ENDIAN
)
9720 /* Adjust the address so that the address-after-the-data is
9722 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9723 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9726 return adjust_address_nv (x
, mode
, offset
);
9729 /* If X is a comparison operator, rewrite it in a new mode. This
9730 probably won't match, but may allow further simplifications. */
9731 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9732 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9734 /* If we couldn't simplify X any other way, just enclose it in a
9735 SUBREG. Normally, this SUBREG won't match, but some patterns may
9736 include an explicit SUBREG or we may simplify it further in combine. */
9742 offset
= subreg_lowpart_offset (mode
, GET_MODE (x
));
9743 res
= simplify_gen_subreg (mode
, x
, GET_MODE (x
), offset
);
9746 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9750 /* These routines make binary and unary operations by first seeing if they
9751 fold; if not, a new expression is allocated. */
9754 gen_binary (code
, mode
, op0
, op1
)
9756 enum machine_mode mode
;
9762 if (GET_RTX_CLASS (code
) == 'c'
9763 && swap_commutative_operands_p (op0
, op1
))
9764 tem
= op0
, op0
= op1
, op1
= tem
;
9766 if (GET_RTX_CLASS (code
) == '<')
9768 enum machine_mode op_mode
= GET_MODE (op0
);
9770 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9771 just (REL_OP X Y). */
9772 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9774 op1
= XEXP (op0
, 1);
9775 op0
= XEXP (op0
, 0);
9776 op_mode
= GET_MODE (op0
);
9779 if (op_mode
== VOIDmode
)
9780 op_mode
= GET_MODE (op1
);
9781 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9784 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9789 /* Put complex operands first and constants second. */
9790 if (GET_RTX_CLASS (code
) == 'c'
9791 && swap_commutative_operands_p (op0
, op1
))
9792 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9794 /* If we are turning off bits already known off in OP0, we need not do
9796 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9797 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9798 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9801 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9804 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9805 comparison code that will be tested.
9807 The result is a possibly different comparison code to use. *POP0 and
9808 *POP1 may be updated.
9810 It is possible that we might detect that a comparison is either always
9811 true or always false. However, we do not perform general constant
9812 folding in combine, so this knowledge isn't useful. Such tautologies
9813 should have been detected earlier. Hence we ignore all such cases. */
9815 static enum rtx_code
9816 simplify_comparison (code
, pop0
, pop1
)
9825 enum machine_mode mode
, tmode
;
9827 /* Try a few ways of applying the same transformation to both operands. */
9830 #ifndef WORD_REGISTER_OPERATIONS
9831 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9832 so check specially. */
9833 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9834 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9835 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9836 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9837 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9838 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9839 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9840 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9841 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9842 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
9843 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9844 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
9845 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
9846 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
9847 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
9848 && (INTVAL (XEXP (op0
, 1))
9849 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9851 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9853 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9854 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9858 /* If both operands are the same constant shift, see if we can ignore the
9859 shift. We can if the shift is a rotate or if the bits shifted out of
9860 this shift are known to be zero for both inputs and if the type of
9861 comparison is compatible with the shift. */
9862 if (GET_CODE (op0
) == GET_CODE (op1
)
9863 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9864 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9865 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9866 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9867 || (GET_CODE (op0
) == ASHIFTRT
9868 && (code
!= GTU
&& code
!= LTU
9869 && code
!= GEU
&& code
!= LEU
)))
9870 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9871 && INTVAL (XEXP (op0
, 1)) >= 0
9872 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9873 && XEXP (op0
, 1) == XEXP (op1
, 1))
9875 enum machine_mode mode
= GET_MODE (op0
);
9876 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9877 int shift_count
= INTVAL (XEXP (op0
, 1));
9879 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9880 mask
&= (mask
>> shift_count
) << shift_count
;
9881 else if (GET_CODE (op0
) == ASHIFT
)
9882 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9884 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9885 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9886 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9891 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9892 SUBREGs are of the same mode, and, in both cases, the AND would
9893 be redundant if the comparison was done in the narrower mode,
9894 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9895 and the operand's possibly nonzero bits are 0xffffff01; in that case
9896 if we only care about QImode, we don't need the AND). This case
9897 occurs if the output mode of an scc insn is not SImode and
9898 STORE_FLAG_VALUE == 1 (e.g., the 386).
9900 Similarly, check for a case where the AND's are ZERO_EXTEND
9901 operations from some narrower mode even though a SUBREG is not
9904 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9905 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9906 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9908 rtx inner_op0
= XEXP (op0
, 0);
9909 rtx inner_op1
= XEXP (op1
, 0);
9910 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9911 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9914 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9915 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9916 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9917 && (GET_MODE (SUBREG_REG (inner_op0
))
9918 == GET_MODE (SUBREG_REG (inner_op1
)))
9919 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9920 <= HOST_BITS_PER_WIDE_INT
)
9921 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9922 GET_MODE (SUBREG_REG (inner_op0
)))))
9923 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9924 GET_MODE (SUBREG_REG (inner_op1
))))))
9926 op0
= SUBREG_REG (inner_op0
);
9927 op1
= SUBREG_REG (inner_op1
);
9929 /* The resulting comparison is always unsigned since we masked
9930 off the original sign bit. */
9931 code
= unsigned_condition (code
);
9937 for (tmode
= GET_CLASS_NARROWEST_MODE
9938 (GET_MODE_CLASS (GET_MODE (op0
)));
9939 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9940 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9942 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
9943 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
9944 code
= unsigned_condition (code
);
9953 /* If both operands are NOT, we can strip off the outer operation
9954 and adjust the comparison code for swapped operands; similarly for
9955 NEG, except that this must be an equality comparison. */
9956 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9957 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9958 && (code
== EQ
|| code
== NE
)))
9959 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9965 /* If the first operand is a constant, swap the operands and adjust the
9966 comparison code appropriately, but don't do this if the second operand
9967 is already a constant integer. */
9968 if (swap_commutative_operands_p (op0
, op1
))
9970 tem
= op0
, op0
= op1
, op1
= tem
;
9971 code
= swap_condition (code
);
9974 /* We now enter a loop during which we will try to simplify the comparison.
9975 For the most part, we only are concerned with comparisons with zero,
9976 but some things may really be comparisons with zero but not start
9977 out looking that way. */
9979 while (GET_CODE (op1
) == CONST_INT
)
9981 enum machine_mode mode
= GET_MODE (op0
);
9982 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9983 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9984 int equality_comparison_p
;
9985 int sign_bit_comparison_p
;
9986 int unsigned_comparison_p
;
9987 HOST_WIDE_INT const_op
;
9989 /* We only want to handle integral modes. This catches VOIDmode,
9990 CCmode, and the floating-point modes. An exception is that we
9991 can handle VOIDmode if OP0 is a COMPARE or a comparison
9994 if (GET_MODE_CLASS (mode
) != MODE_INT
9995 && ! (mode
== VOIDmode
9996 && (GET_CODE (op0
) == COMPARE
9997 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10000 /* Get the constant we are comparing against and turn off all bits
10001 not on in our mode. */
10002 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10003 op1
= GEN_INT (const_op
);
10005 /* If we are comparing against a constant power of two and the value
10006 being compared can only have that single bit nonzero (e.g., it was
10007 `and'ed with that bit), we can replace this with a comparison
10010 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10011 || code
== LT
|| code
== LTU
)
10012 && mode_width
<= HOST_BITS_PER_WIDE_INT
10013 && exact_log2 (const_op
) >= 0
10014 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10016 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10017 op1
= const0_rtx
, const_op
= 0;
10020 /* Similarly, if we are comparing a value known to be either -1 or
10021 0 with -1, change it to the opposite comparison against zero. */
10024 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10025 || code
== GEU
|| code
== LTU
)
10026 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10028 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10029 op1
= const0_rtx
, const_op
= 0;
10032 /* Do some canonicalizations based on the comparison code. We prefer
10033 comparisons against zero and then prefer equality comparisons.
10034 If we can reduce the size of a constant, we will do that too. */
10039 /* < C is equivalent to <= (C - 1) */
10043 op1
= GEN_INT (const_op
);
10045 /* ... fall through to LE case below. */
10051 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10055 op1
= GEN_INT (const_op
);
10059 /* If we are doing a <= 0 comparison on a value known to have
10060 a zero sign bit, we can replace this with == 0. */
10061 else if (const_op
== 0
10062 && mode_width
<= HOST_BITS_PER_WIDE_INT
10063 && (nonzero_bits (op0
, mode
)
10064 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10069 /* >= C is equivalent to > (C - 1). */
10073 op1
= GEN_INT (const_op
);
10075 /* ... fall through to GT below. */
10081 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10085 op1
= GEN_INT (const_op
);
10089 /* If we are doing a > 0 comparison on a value known to have
10090 a zero sign bit, we can replace this with != 0. */
10091 else if (const_op
== 0
10092 && mode_width
<= HOST_BITS_PER_WIDE_INT
10093 && (nonzero_bits (op0
, mode
)
10094 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10099 /* < C is equivalent to <= (C - 1). */
10103 op1
= GEN_INT (const_op
);
10105 /* ... fall through ... */
10108 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10109 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10110 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10112 const_op
= 0, op1
= const0_rtx
;
10120 /* unsigned <= 0 is equivalent to == 0 */
10124 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10125 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10126 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10128 const_op
= 0, op1
= const0_rtx
;
10134 /* >= C is equivalent to < (C - 1). */
10138 op1
= GEN_INT (const_op
);
10140 /* ... fall through ... */
10143 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10144 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10145 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10147 const_op
= 0, op1
= const0_rtx
;
10155 /* unsigned > 0 is equivalent to != 0 */
10159 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10160 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10161 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10163 const_op
= 0, op1
= const0_rtx
;
10172 /* Compute some predicates to simplify code below. */
10174 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10175 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10176 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10179 /* If this is a sign bit comparison and we can do arithmetic in
10180 MODE, say that we will only be needing the sign bit of OP0. */
10181 if (sign_bit_comparison_p
10182 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10183 op0
= force_to_mode (op0
, mode
,
10185 << (GET_MODE_BITSIZE (mode
) - 1)),
10188 /* Now try cases based on the opcode of OP0. If none of the cases
10189 does a "continue", we exit this loop immediately after the
10192 switch (GET_CODE (op0
))
10195 /* If we are extracting a single bit from a variable position in
10196 a constant that has only a single bit set and are comparing it
10197 with zero, we can convert this into an equality comparison
10198 between the position and the location of the single bit. */
10200 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10201 && XEXP (op0
, 1) == const1_rtx
10202 && equality_comparison_p
&& const_op
== 0
10203 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10205 if (BITS_BIG_ENDIAN
)
10207 enum machine_mode new_mode
10208 = mode_for_extraction (EP_extzv
, 1);
10209 if (new_mode
== MAX_MACHINE_MODE
)
10210 i
= BITS_PER_WORD
- 1 - i
;
10214 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10218 op0
= XEXP (op0
, 2);
10222 /* Result is nonzero iff shift count is equal to I. */
10223 code
= reverse_condition (code
);
10227 /* ... fall through ... */
10230 tem
= expand_compound_operation (op0
);
10239 /* If testing for equality, we can take the NOT of the constant. */
10240 if (equality_comparison_p
10241 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10243 op0
= XEXP (op0
, 0);
10248 /* If just looking at the sign bit, reverse the sense of the
10250 if (sign_bit_comparison_p
)
10252 op0
= XEXP (op0
, 0);
10253 code
= (code
== GE
? LT
: GE
);
10259 /* If testing for equality, we can take the NEG of the constant. */
10260 if (equality_comparison_p
10261 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10263 op0
= XEXP (op0
, 0);
10268 /* The remaining cases only apply to comparisons with zero. */
10272 /* When X is ABS or is known positive,
10273 (neg X) is < 0 if and only if X != 0. */
10275 if (sign_bit_comparison_p
10276 && (GET_CODE (XEXP (op0
, 0)) == ABS
10277 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10278 && (nonzero_bits (XEXP (op0
, 0), mode
)
10279 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10281 op0
= XEXP (op0
, 0);
10282 code
= (code
== LT
? NE
: EQ
);
10286 /* If we have NEG of something whose two high-order bits are the
10287 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10288 if (num_sign_bit_copies (op0
, mode
) >= 2)
10290 op0
= XEXP (op0
, 0);
10291 code
= swap_condition (code
);
10297 /* If we are testing equality and our count is a constant, we
10298 can perform the inverse operation on our RHS. */
10299 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10300 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10301 op1
, XEXP (op0
, 1))) != 0)
10303 op0
= XEXP (op0
, 0);
10308 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10309 a particular bit. Convert it to an AND of a constant of that
10310 bit. This will be converted into a ZERO_EXTRACT. */
10311 if (const_op
== 0 && sign_bit_comparison_p
10312 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10313 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10315 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10318 - INTVAL (XEXP (op0
, 1)))));
10319 code
= (code
== LT
? NE
: EQ
);
10323 /* Fall through. */
10326 /* ABS is ignorable inside an equality comparison with zero. */
10327 if (const_op
== 0 && equality_comparison_p
)
10329 op0
= XEXP (op0
, 0);
10335 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10336 to (compare FOO CONST) if CONST fits in FOO's mode and we
10337 are either testing inequality or have an unsigned comparison
10338 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10339 if (! unsigned_comparison_p
10340 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10341 <= HOST_BITS_PER_WIDE_INT
)
10342 && ((unsigned HOST_WIDE_INT
) const_op
10343 < (((unsigned HOST_WIDE_INT
) 1
10344 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10346 op0
= XEXP (op0
, 0);
10352 /* Check for the case where we are comparing A - C1 with C2,
10353 both constants are smaller than 1/2 the maximum positive
10354 value in MODE, and the comparison is equality or unsigned.
10355 In that case, if A is either zero-extended to MODE or has
10356 sufficient sign bits so that the high-order bit in MODE
10357 is a copy of the sign in the inner mode, we can prove that it is
10358 safe to do the operation in the wider mode. This simplifies
10359 many range checks. */
10361 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10362 && subreg_lowpart_p (op0
)
10363 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10364 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10365 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10366 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10367 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10368 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10369 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10370 GET_MODE (SUBREG_REG (op0
)))
10371 & ~GET_MODE_MASK (mode
))
10372 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10373 GET_MODE (SUBREG_REG (op0
)))
10374 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10375 - GET_MODE_BITSIZE (mode
)))))
10377 op0
= SUBREG_REG (op0
);
10381 /* If the inner mode is narrower and we are extracting the low part,
10382 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10383 if (subreg_lowpart_p (op0
)
10384 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10385 /* Fall through */ ;
10389 /* ... fall through ... */
10392 if ((unsigned_comparison_p
|| equality_comparison_p
)
10393 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10394 <= HOST_BITS_PER_WIDE_INT
)
10395 && ((unsigned HOST_WIDE_INT
) const_op
10396 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10398 op0
= XEXP (op0
, 0);
10404 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10405 this for equality comparisons due to pathological cases involving
10407 if (equality_comparison_p
10408 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10409 op1
, XEXP (op0
, 1))))
10411 op0
= XEXP (op0
, 0);
10416 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10417 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10418 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10420 op0
= XEXP (XEXP (op0
, 0), 0);
10421 code
= (code
== LT
? EQ
: NE
);
10427 /* We used to optimize signed comparisons against zero, but that
10428 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10429 arrive here as equality comparisons, or (GEU, LTU) are
10430 optimized away. No need to special-case them. */
10432 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10433 (eq B (minus A C)), whichever simplifies. We can only do
10434 this for equality comparisons due to pathological cases involving
10436 if (equality_comparison_p
10437 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10438 XEXP (op0
, 1), op1
)))
10440 op0
= XEXP (op0
, 0);
10445 if (equality_comparison_p
10446 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10447 XEXP (op0
, 0), op1
)))
10449 op0
= XEXP (op0
, 1);
10454 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10455 of bits in X minus 1, is one iff X > 0. */
10456 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10457 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10458 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10459 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10461 op0
= XEXP (op0
, 1);
10462 code
= (code
== GE
? LE
: GT
);
10468 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10469 if C is zero or B is a constant. */
10470 if (equality_comparison_p
10471 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10472 XEXP (op0
, 1), op1
)))
10474 op0
= XEXP (op0
, 0);
10481 case UNEQ
: case LTGT
:
10482 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10483 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10484 case UNORDERED
: case ORDERED
:
10485 /* We can't do anything if OP0 is a condition code value, rather
10486 than an actual data value. */
10489 || XEXP (op0
, 0) == cc0_rtx
10491 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10494 /* Get the two operands being compared. */
10495 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10496 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10498 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10500 /* Check for the cases where we simply want the result of the
10501 earlier test or the opposite of that result. */
10502 if (code
== NE
|| code
== EQ
10503 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10504 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10505 && (STORE_FLAG_VALUE
10506 & (((HOST_WIDE_INT
) 1
10507 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10508 && (code
== LT
|| code
== GE
)))
10510 enum rtx_code new_code
;
10511 if (code
== LT
|| code
== NE
)
10512 new_code
= GET_CODE (op0
);
10514 new_code
= combine_reversed_comparison_code (op0
);
10516 if (new_code
!= UNKNOWN
)
10527 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10529 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10530 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10531 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10533 op0
= XEXP (op0
, 1);
10534 code
= (code
== GE
? GT
: LE
);
10540 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10541 will be converted to a ZERO_EXTRACT later. */
10542 if (const_op
== 0 && equality_comparison_p
10543 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10544 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10546 op0
= simplify_and_const_int
10547 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10549 XEXP (XEXP (op0
, 0), 1)),
10550 (HOST_WIDE_INT
) 1);
10554 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10555 zero and X is a comparison and C1 and C2 describe only bits set
10556 in STORE_FLAG_VALUE, we can compare with X. */
10557 if (const_op
== 0 && equality_comparison_p
10558 && mode_width
<= HOST_BITS_PER_WIDE_INT
10559 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10560 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10561 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10562 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10563 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10565 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10566 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10567 if ((~STORE_FLAG_VALUE
& mask
) == 0
10568 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10569 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10570 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10572 op0
= XEXP (XEXP (op0
, 0), 0);
10577 /* If we are doing an equality comparison of an AND of a bit equal
10578 to the sign bit, replace this with a LT or GE comparison of
10579 the underlying value. */
10580 if (equality_comparison_p
10582 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10583 && mode_width
<= HOST_BITS_PER_WIDE_INT
10584 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10585 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10587 op0
= XEXP (op0
, 0);
10588 code
= (code
== EQ
? GE
: LT
);
10592 /* If this AND operation is really a ZERO_EXTEND from a narrower
10593 mode, the constant fits within that mode, and this is either an
10594 equality or unsigned comparison, try to do this comparison in
10595 the narrower mode. */
10596 if ((equality_comparison_p
|| unsigned_comparison_p
)
10597 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10598 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10599 & GET_MODE_MASK (mode
))
10601 && const_op
>> i
== 0
10602 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10604 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10608 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10609 in both M1 and M2 and the SUBREG is either paradoxical or
10610 represents the low part, permute the SUBREG and the AND and
10612 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10614 #ifdef WORD_REGISTER_OPERATIONS
10616 > (GET_MODE_BITSIZE
10617 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10618 && mode_width
<= BITS_PER_WORD
)
10621 <= (GET_MODE_BITSIZE
10622 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10623 && subreg_lowpart_p (XEXP (op0
, 0))))
10624 #ifndef WORD_REGISTER_OPERATIONS
10625 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10626 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10627 As originally written the upper bits have a defined value
10628 due to the AND operation. However, if we commute the AND
10629 inside the SUBREG then they no longer have defined values
10630 and the meaning of the code has been changed. */
10631 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10632 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10634 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10635 && mode_width
<= HOST_BITS_PER_WIDE_INT
10636 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10637 <= HOST_BITS_PER_WIDE_INT
)
10638 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10639 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10640 & INTVAL (XEXP (op0
, 1)))
10641 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10642 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10643 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10647 = gen_lowpart_for_combine
10649 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10650 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10654 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10655 (eq (and (lshiftrt X) 1) 0). */
10656 if (const_op
== 0 && equality_comparison_p
10657 && XEXP (op0
, 1) == const1_rtx
10658 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10659 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10661 op0
= simplify_and_const_int
10663 gen_rtx_LSHIFTRT (mode
, XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10664 XEXP (XEXP (op0
, 0), 1)),
10665 (HOST_WIDE_INT
) 1);
10666 code
= (code
== NE
? EQ
: NE
);
10672 /* If we have (compare (ashift FOO N) (const_int C)) and
10673 the high order N bits of FOO (N+1 if an inequality comparison)
10674 are known to be zero, we can do this by comparing FOO with C
10675 shifted right N bits so long as the low-order N bits of C are
10677 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10678 && INTVAL (XEXP (op0
, 1)) >= 0
10679 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10680 < HOST_BITS_PER_WIDE_INT
)
10682 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10683 && mode_width
<= HOST_BITS_PER_WIDE_INT
10684 && (nonzero_bits (XEXP (op0
, 0), mode
)
10685 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10686 + ! equality_comparison_p
))) == 0)
10688 /* We must perform a logical shift, not an arithmetic one,
10689 as we want the top N bits of C to be zero. */
10690 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10692 temp
>>= INTVAL (XEXP (op0
, 1));
10693 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10694 op0
= XEXP (op0
, 0);
10698 /* If we are doing a sign bit comparison, it means we are testing
10699 a particular bit. Convert it to the appropriate AND. */
10700 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10701 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10703 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10706 - INTVAL (XEXP (op0
, 1)))));
10707 code
= (code
== LT
? NE
: EQ
);
10711 /* If this an equality comparison with zero and we are shifting
10712 the low bit to the sign bit, we can convert this to an AND of the
10714 if (const_op
== 0 && equality_comparison_p
10715 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10716 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10718 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10719 (HOST_WIDE_INT
) 1);
10725 /* If this is an equality comparison with zero, we can do this
10726 as a logical shift, which might be much simpler. */
10727 if (equality_comparison_p
&& const_op
== 0
10728 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10730 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10732 INTVAL (XEXP (op0
, 1)));
10736 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10737 do the comparison in a narrower mode. */
10738 if (! unsigned_comparison_p
10739 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10740 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10741 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10742 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10743 MODE_INT
, 1)) != BLKmode
10744 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10745 || ((unsigned HOST_WIDE_INT
) -const_op
10746 <= GET_MODE_MASK (tmode
))))
10748 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10752 /* Likewise if OP0 is a PLUS of a sign extension with a
10753 constant, which is usually represented with the PLUS
10754 between the shifts. */
10755 if (! unsigned_comparison_p
10756 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10757 && GET_CODE (XEXP (op0
, 0)) == PLUS
10758 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10759 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10760 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10761 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10762 MODE_INT
, 1)) != BLKmode
10763 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10764 || ((unsigned HOST_WIDE_INT
) -const_op
10765 <= GET_MODE_MASK (tmode
))))
10767 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10768 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10769 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10772 op0
= gen_binary (PLUS
, tmode
,
10773 gen_lowpart_for_combine (tmode
, inner
),
10778 /* ... fall through ... */
10780 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10781 the low order N bits of FOO are known to be zero, we can do this
10782 by comparing FOO with C shifted left N bits so long as no
10783 overflow occurs. */
10784 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10785 && INTVAL (XEXP (op0
, 1)) >= 0
10786 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10787 && mode_width
<= HOST_BITS_PER_WIDE_INT
10788 && (nonzero_bits (XEXP (op0
, 0), mode
)
10789 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10791 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10794 const_op
<<= INTVAL (XEXP (op0
, 1));
10795 op1
= GEN_INT (const_op
);
10796 op0
= XEXP (op0
, 0);
10800 /* If we are using this shift to extract just the sign bit, we
10801 can replace this with an LT or GE comparison. */
10803 && (equality_comparison_p
|| sign_bit_comparison_p
)
10804 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10805 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10807 op0
= XEXP (op0
, 0);
10808 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10820 /* Now make any compound operations involved in this comparison. Then,
10821 check for an outmost SUBREG on OP0 that is not doing anything or is
10822 paradoxical. The latter case can only occur when it is known that the
10823 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10824 We can never remove a SUBREG for a non-equality comparison because the
10825 sign bit is in a different place in the underlying object. */
10827 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10828 op1
= make_compound_operation (op1
, SET
);
10830 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10831 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10832 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10833 && (code
== NE
|| code
== EQ
)
10834 && ((GET_MODE_SIZE (GET_MODE (op0
))
10835 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
10837 op0
= SUBREG_REG (op0
);
10838 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
10841 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10842 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10843 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10844 && (code
== NE
|| code
== EQ
)
10845 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10846 <= HOST_BITS_PER_WIDE_INT
)
10847 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
10848 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
10849 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
10851 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10852 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
10853 op0
= SUBREG_REG (op0
), op1
= tem
;
10855 /* We now do the opposite procedure: Some machines don't have compare
10856 insns in all modes. If OP0's mode is an integer mode smaller than a
10857 word and we can't do a compare in that mode, see if there is a larger
10858 mode for which we can do the compare. There are a number of cases in
10859 which we can use the wider mode. */
10861 mode
= GET_MODE (op0
);
10862 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10863 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10864 && ! have_insn_for (COMPARE
, mode
))
10865 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10867 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10868 tmode
= GET_MODE_WIDER_MODE (tmode
))
10869 if (have_insn_for (COMPARE
, tmode
))
10871 /* If the only nonzero bits in OP0 and OP1 are those in the
10872 narrower mode and this is an equality or unsigned comparison,
10873 we can use the wider mode. Similarly for sign-extended
10874 values, in which case it is true for all comparisons. */
10875 if (((code
== EQ
|| code
== NE
10876 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
10877 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
10878 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
10879 || ((num_sign_bit_copies (op0
, tmode
)
10880 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
10881 && (num_sign_bit_copies (op1
, tmode
)
10882 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
10884 /* If OP0 is an AND and we don't have an AND in MODE either,
10885 make a new AND in the proper mode. */
10886 if (GET_CODE (op0
) == AND
10887 && !have_insn_for (AND
, mode
))
10888 op0
= gen_binary (AND
, tmode
,
10889 gen_lowpart_for_combine (tmode
,
10891 gen_lowpart_for_combine (tmode
,
10894 op0
= gen_lowpart_for_combine (tmode
, op0
);
10895 op1
= gen_lowpart_for_combine (tmode
, op1
);
10899 /* If this is a test for negative, we can make an explicit
10900 test of the sign bit. */
10902 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10903 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10905 op0
= gen_binary (AND
, tmode
,
10906 gen_lowpart_for_combine (tmode
, op0
),
10907 GEN_INT ((HOST_WIDE_INT
) 1
10908 << (GET_MODE_BITSIZE (mode
) - 1)));
10909 code
= (code
== LT
) ? NE
: EQ
;
10914 #ifdef CANONICALIZE_COMPARISON
10915 /* If this machine only supports a subset of valid comparisons, see if we
10916 can convert an unsupported one into a supported one. */
10917 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10926 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10927 searching backward. */
10928 static enum rtx_code
10929 combine_reversed_comparison_code (exp
)
10932 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10935 if (code1
!= UNKNOWN
10936 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10938 /* Otherwise try and find where the condition codes were last set and
10940 x
= get_last_value (XEXP (exp
, 0));
10941 if (!x
|| GET_CODE (x
) != COMPARE
)
10943 return reversed_comparison_code_parts (GET_CODE (exp
),
10944 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10946 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10947 Return NULL_RTX in case we fail to do the reversal. */
10949 reversed_comparison (exp
, mode
, op0
, op1
)
10951 enum machine_mode mode
;
10953 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10954 if (reversed_code
== UNKNOWN
)
10957 return gen_binary (reversed_code
, mode
, op0
, op1
);
10960 /* Utility function for following routine. Called when X is part of a value
10961 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10962 for each register mentioned. Similar to mention_regs in cse.c */
10965 update_table_tick (x
)
10968 register enum rtx_code code
= GET_CODE (x
);
10969 register const char *fmt
= GET_RTX_FORMAT (code
);
10974 unsigned int regno
= REGNO (x
);
10975 unsigned int endregno
10976 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10977 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10980 for (r
= regno
; r
< endregno
; r
++)
10981 reg_last_set_table_tick
[r
] = label_tick
;
10986 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10987 /* Note that we can't have an "E" in values stored; see
10988 get_last_value_validate. */
10990 update_table_tick (XEXP (x
, i
));
10993 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10994 are saying that the register is clobbered and we no longer know its
10995 value. If INSN is zero, don't update reg_last_set; this is only permitted
10996 with VALUE also zero and is used to invalidate the register. */
10999 record_value_for_reg (reg
, insn
, value
)
11004 unsigned int regno
= REGNO (reg
);
11005 unsigned int endregno
11006 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11007 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11010 /* If VALUE contains REG and we have a previous value for REG, substitute
11011 the previous value. */
11012 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11016 /* Set things up so get_last_value is allowed to see anything set up to
11018 subst_low_cuid
= INSN_CUID (insn
);
11019 tem
= get_last_value (reg
);
11021 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11022 it isn't going to be useful and will take a lot of time to process,
11023 so just use the CLOBBER. */
11027 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11028 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11029 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11030 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11031 tem
= XEXP (tem
, 0);
11033 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11037 /* For each register modified, show we don't know its value, that
11038 we don't know about its bitwise content, that its value has been
11039 updated, and that we don't know the location of the death of the
11041 for (i
= regno
; i
< endregno
; i
++)
11044 reg_last_set
[i
] = insn
;
11046 reg_last_set_value
[i
] = 0;
11047 reg_last_set_mode
[i
] = 0;
11048 reg_last_set_nonzero_bits
[i
] = 0;
11049 reg_last_set_sign_bit_copies
[i
] = 0;
11050 reg_last_death
[i
] = 0;
11053 /* Mark registers that are being referenced in this value. */
11055 update_table_tick (value
);
11057 /* Now update the status of each register being set.
11058 If someone is using this register in this block, set this register
11059 to invalid since we will get confused between the two lives in this
11060 basic block. This makes using this register always invalid. In cse, we
11061 scan the table to invalidate all entries using this register, but this
11062 is too much work for us. */
11064 for (i
= regno
; i
< endregno
; i
++)
11066 reg_last_set_label
[i
] = label_tick
;
11067 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11068 reg_last_set_invalid
[i
] = 1;
11070 reg_last_set_invalid
[i
] = 0;
11073 /* The value being assigned might refer to X (like in "x++;"). In that
11074 case, we must replace it with (clobber (const_int 0)) to prevent
11076 if (value
&& ! get_last_value_validate (&value
, insn
,
11077 reg_last_set_label
[regno
], 0))
11079 value
= copy_rtx (value
);
11080 if (! get_last_value_validate (&value
, insn
,
11081 reg_last_set_label
[regno
], 1))
11085 /* For the main register being modified, update the value, the mode, the
11086 nonzero bits, and the number of sign bit copies. */
11088 reg_last_set_value
[regno
] = value
;
11092 subst_low_cuid
= INSN_CUID (insn
);
11093 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11094 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11095 reg_last_set_sign_bit_copies
[regno
]
11096 = num_sign_bit_copies (value
, GET_MODE (reg
));
11100 /* Called via note_stores from record_dead_and_set_regs to handle one
11101 SET or CLOBBER in an insn. DATA is the instruction in which the
11102 set is occurring. */
11105 record_dead_and_set_regs_1 (dest
, setter
, data
)
11109 rtx record_dead_insn
= (rtx
) data
;
11111 if (GET_CODE (dest
) == SUBREG
)
11112 dest
= SUBREG_REG (dest
);
11114 if (GET_CODE (dest
) == REG
)
11116 /* If we are setting the whole register, we know its value. Otherwise
11117 show that we don't know the value. We can handle SUBREG in
11119 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11120 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11121 else if (GET_CODE (setter
) == SET
11122 && GET_CODE (SET_DEST (setter
)) == SUBREG
11123 && SUBREG_REG (SET_DEST (setter
)) == dest
11124 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11125 && subreg_lowpart_p (SET_DEST (setter
)))
11126 record_value_for_reg (dest
, record_dead_insn
,
11127 gen_lowpart_for_combine (GET_MODE (dest
),
11128 SET_SRC (setter
)));
11130 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11132 else if (GET_CODE (dest
) == MEM
11133 /* Ignore pushes, they clobber nothing. */
11134 && ! push_operand (dest
, GET_MODE (dest
)))
11135 mem_last_set
= INSN_CUID (record_dead_insn
);
11138 /* Update the records of when each REG was most recently set or killed
11139 for the things done by INSN. This is the last thing done in processing
11140 INSN in the combiner loop.
11142 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11143 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11144 and also the similar information mem_last_set (which insn most recently
11145 modified memory) and last_call_cuid (which insn was the most recent
11146 subroutine call). */
11149 record_dead_and_set_regs (insn
)
11155 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11157 if (REG_NOTE_KIND (link
) == REG_DEAD
11158 && GET_CODE (XEXP (link
, 0)) == REG
)
11160 unsigned int regno
= REGNO (XEXP (link
, 0));
11161 unsigned int endregno
11162 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11163 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11166 for (i
= regno
; i
< endregno
; i
++)
11167 reg_last_death
[i
] = insn
;
11169 else if (REG_NOTE_KIND (link
) == REG_INC
)
11170 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11173 if (GET_CODE (insn
) == CALL_INSN
)
11175 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11176 if (call_used_regs
[i
])
11178 reg_last_set_value
[i
] = 0;
11179 reg_last_set_mode
[i
] = 0;
11180 reg_last_set_nonzero_bits
[i
] = 0;
11181 reg_last_set_sign_bit_copies
[i
] = 0;
11182 reg_last_death
[i
] = 0;
11185 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11188 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11191 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11192 register present in the SUBREG, so for each such SUBREG go back and
11193 adjust nonzero and sign bit information of the registers that are
11194 known to have some zero/sign bits set.
11196 This is needed because when combine blows the SUBREGs away, the
11197 information on zero/sign bits is lost and further combines can be
11198 missed because of that. */
11201 record_promoted_value (insn
, subreg
)
11206 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11207 enum machine_mode mode
= GET_MODE (subreg
);
11209 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11212 for (links
= LOG_LINKS (insn
); links
;)
11214 insn
= XEXP (links
, 0);
11215 set
= single_set (insn
);
11217 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11218 || REGNO (SET_DEST (set
)) != regno
11219 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11221 links
= XEXP (links
, 1);
11225 if (reg_last_set
[regno
] == insn
)
11227 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11228 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11231 if (GET_CODE (SET_SRC (set
)) == REG
)
11233 regno
= REGNO (SET_SRC (set
));
11234 links
= LOG_LINKS (insn
);
11241 /* Scan X for promoted SUBREGs. For each one found,
11242 note what it implies to the registers used in it. */
11245 check_promoted_subreg (insn
, x
)
11249 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11250 && GET_CODE (SUBREG_REG (x
)) == REG
)
11251 record_promoted_value (insn
, x
);
11254 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11257 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11261 check_promoted_subreg (insn
, XEXP (x
, i
));
11265 if (XVEC (x
, i
) != 0)
11266 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11267 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11273 /* Utility routine for the following function. Verify that all the registers
11274 mentioned in *LOC are valid when *LOC was part of a value set when
11275 label_tick == TICK. Return 0 if some are not.
11277 If REPLACE is non-zero, replace the invalid reference with
11278 (clobber (const_int 0)) and return 1. This replacement is useful because
11279 we often can get useful information about the form of a value (e.g., if
11280 it was produced by a shift that always produces -1 or 0) even though
11281 we don't know exactly what registers it was produced from. */
11284 get_last_value_validate (loc
, insn
, tick
, replace
)
11291 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11292 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11295 if (GET_CODE (x
) == REG
)
11297 unsigned int regno
= REGNO (x
);
11298 unsigned int endregno
11299 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11300 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11303 for (j
= regno
; j
< endregno
; j
++)
11304 if (reg_last_set_invalid
[j
]
11305 /* If this is a pseudo-register that was only set once and not
11306 live at the beginning of the function, it is always valid. */
11307 || (! (regno
>= FIRST_PSEUDO_REGISTER
11308 && REG_N_SETS (regno
) == 1
11309 && (! REGNO_REG_SET_P
11310 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11311 && reg_last_set_label
[j
] > tick
))
11314 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11320 /* If this is a memory reference, make sure that there were
11321 no stores after it that might have clobbered the value. We don't
11322 have alias info, so we assume any store invalidates it. */
11323 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11324 && INSN_CUID (insn
) <= mem_last_set
)
11327 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11331 for (i
= 0; i
< len
; i
++)
11333 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11334 /* Don't bother with these. They shouldn't occur anyway. */
11338 /* If we haven't found a reason for it to be invalid, it is valid. */
11342 /* Get the last value assigned to X, if known. Some registers
11343 in the value may be replaced with (clobber (const_int 0)) if their value
11344 is known longer known reliably. */
11350 unsigned int regno
;
11353 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11354 then convert it to the desired mode. If this is a paradoxical SUBREG,
11355 we cannot predict what values the "extra" bits might have. */
11356 if (GET_CODE (x
) == SUBREG
11357 && subreg_lowpart_p (x
)
11358 && (GET_MODE_SIZE (GET_MODE (x
))
11359 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11360 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11361 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11363 if (GET_CODE (x
) != REG
)
11367 value
= reg_last_set_value
[regno
];
11369 /* If we don't have a value, or if it isn't for this basic block and
11370 it's either a hard register, set more than once, or it's a live
11371 at the beginning of the function, return 0.
11373 Because if it's not live at the beginnning of the function then the reg
11374 is always set before being used (is never used without being set).
11375 And, if it's set only once, and it's always set before use, then all
11376 uses must have the same last value, even if it's not from this basic
11380 || (reg_last_set_label
[regno
] != label_tick
11381 && (regno
< FIRST_PSEUDO_REGISTER
11382 || REG_N_SETS (regno
) != 1
11383 || (REGNO_REG_SET_P
11384 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11387 /* If the value was set in a later insn than the ones we are processing,
11388 we can't use it even if the register was only set once. */
11389 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11392 /* If the value has all its registers valid, return it. */
11393 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11394 reg_last_set_label
[regno
], 0))
11397 /* Otherwise, make a copy and replace any invalid register with
11398 (clobber (const_int 0)). If that fails for some reason, return 0. */
11400 value
= copy_rtx (value
);
11401 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11402 reg_last_set_label
[regno
], 1))
11408 /* Return nonzero if expression X refers to a REG or to memory
11409 that is set in an instruction more recent than FROM_CUID. */
11412 use_crosses_set_p (x
, from_cuid
)
11416 register const char *fmt
;
11418 register enum rtx_code code
= GET_CODE (x
);
11422 unsigned int regno
= REGNO (x
);
11423 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11424 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11426 #ifdef PUSH_ROUNDING
11427 /* Don't allow uses of the stack pointer to be moved,
11428 because we don't know whether the move crosses a push insn. */
11429 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11432 for (; regno
< endreg
; regno
++)
11433 if (reg_last_set
[regno
]
11434 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11439 if (code
== MEM
&& mem_last_set
> from_cuid
)
11442 fmt
= GET_RTX_FORMAT (code
);
11444 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11449 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11450 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11453 else if (fmt
[i
] == 'e'
11454 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11460 /* Define three variables used for communication between the following
11463 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11464 static int reg_dead_flag
;
11466 /* Function called via note_stores from reg_dead_at_p.
11468 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11469 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11472 reg_dead_at_p_1 (dest
, x
, data
)
11475 void *data ATTRIBUTE_UNUSED
;
11477 unsigned int regno
, endregno
;
11479 if (GET_CODE (dest
) != REG
)
11482 regno
= REGNO (dest
);
11483 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11484 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11486 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11487 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11490 /* Return non-zero if REG is known to be dead at INSN.
11492 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11493 referencing REG, it is dead. If we hit a SET referencing REG, it is
11494 live. Otherwise, see if it is live or dead at the start of the basic
11495 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11496 must be assumed to be always live. */
11499 reg_dead_at_p (reg
, insn
)
11506 /* Set variables for reg_dead_at_p_1. */
11507 reg_dead_regno
= REGNO (reg
);
11508 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11509 ? HARD_REGNO_NREGS (reg_dead_regno
,
11515 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11516 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11518 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11519 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11523 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11524 beginning of function. */
11525 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11526 insn
= prev_nonnote_insn (insn
))
11528 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11530 return reg_dead_flag
== 1 ? 1 : 0;
11532 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11536 /* Get the basic block number that we were in. */
11541 for (block
= 0; block
< n_basic_blocks
; block
++)
11542 if (insn
== BLOCK_HEAD (block
))
11545 if (block
== n_basic_blocks
)
11549 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11550 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11556 /* Note hard registers in X that are used. This code is similar to
11557 that in flow.c, but much simpler since we don't care about pseudos. */
11560 mark_used_regs_combine (x
)
11563 RTX_CODE code
= GET_CODE (x
);
11564 unsigned int regno
;
11576 case ADDR_DIFF_VEC
:
11579 /* CC0 must die in the insn after it is set, so we don't need to take
11580 special note of it here. */
11586 /* If we are clobbering a MEM, mark any hard registers inside the
11587 address as used. */
11588 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11589 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11594 /* A hard reg in a wide mode may really be multiple registers.
11595 If so, mark all of them just like the first. */
11596 if (regno
< FIRST_PSEUDO_REGISTER
)
11598 unsigned int endregno
, r
;
11600 /* None of this applies to the stack, frame or arg pointers */
11601 if (regno
== STACK_POINTER_REGNUM
11602 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11603 || regno
== HARD_FRAME_POINTER_REGNUM
11605 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11606 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11608 || regno
== FRAME_POINTER_REGNUM
)
11611 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11612 for (r
= regno
; r
< endregno
; r
++)
11613 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11619 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11621 register rtx testreg
= SET_DEST (x
);
11623 while (GET_CODE (testreg
) == SUBREG
11624 || GET_CODE (testreg
) == ZERO_EXTRACT
11625 || GET_CODE (testreg
) == SIGN_EXTRACT
11626 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11627 testreg
= XEXP (testreg
, 0);
11629 if (GET_CODE (testreg
) == MEM
)
11630 mark_used_regs_combine (XEXP (testreg
, 0));
11632 mark_used_regs_combine (SET_SRC (x
));
11640 /* Recursively scan the operands of this expression. */
11643 register const char *fmt
= GET_RTX_FORMAT (code
);
11645 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11648 mark_used_regs_combine (XEXP (x
, i
));
11649 else if (fmt
[i
] == 'E')
11653 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11654 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11660 /* Remove register number REGNO from the dead registers list of INSN.
11662 Return the note used to record the death, if there was one. */
11665 remove_death (regno
, insn
)
11666 unsigned int regno
;
11669 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11673 REG_N_DEATHS (regno
)--;
11674 remove_note (insn
, note
);
11680 /* For each register (hardware or pseudo) used within expression X, if its
11681 death is in an instruction with cuid between FROM_CUID (inclusive) and
11682 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11683 list headed by PNOTES.
11685 That said, don't move registers killed by maybe_kill_insn.
11687 This is done when X is being merged by combination into TO_INSN. These
11688 notes will then be distributed as needed. */
11691 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11693 rtx maybe_kill_insn
;
11698 register const char *fmt
;
11699 register int len
, i
;
11700 register enum rtx_code code
= GET_CODE (x
);
11704 unsigned int regno
= REGNO (x
);
11705 register rtx where_dead
= reg_last_death
[regno
];
11706 register rtx before_dead
, after_dead
;
11708 /* Don't move the register if it gets killed in between from and to */
11709 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11710 && ! reg_referenced_p (x
, maybe_kill_insn
))
11713 /* WHERE_DEAD could be a USE insn made by combine, so first we
11714 make sure that we have insns with valid INSN_CUID values. */
11715 before_dead
= where_dead
;
11716 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11717 before_dead
= PREV_INSN (before_dead
);
11719 after_dead
= where_dead
;
11720 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11721 after_dead
= NEXT_INSN (after_dead
);
11723 if (before_dead
&& after_dead
11724 && INSN_CUID (before_dead
) >= from_cuid
11725 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11726 || (where_dead
!= after_dead
11727 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11729 rtx note
= remove_death (regno
, where_dead
);
11731 /* It is possible for the call above to return 0. This can occur
11732 when reg_last_death points to I2 or I1 that we combined with.
11733 In that case make a new note.
11735 We must also check for the case where X is a hard register
11736 and NOTE is a death note for a range of hard registers
11737 including X. In that case, we must put REG_DEAD notes for
11738 the remaining registers in place of NOTE. */
11740 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11741 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11742 > GET_MODE_SIZE (GET_MODE (x
))))
11744 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11745 unsigned int deadend
11746 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11747 GET_MODE (XEXP (note
, 0))));
11748 unsigned int ourend
11749 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11752 for (i
= deadregno
; i
< deadend
; i
++)
11753 if (i
< regno
|| i
>= ourend
)
11754 REG_NOTES (where_dead
)
11755 = gen_rtx_EXPR_LIST (REG_DEAD
,
11756 gen_rtx_REG (reg_raw_mode
[i
], i
),
11757 REG_NOTES (where_dead
));
11760 /* If we didn't find any note, or if we found a REG_DEAD note that
11761 covers only part of the given reg, and we have a multi-reg hard
11762 register, then to be safe we must check for REG_DEAD notes
11763 for each register other than the first. They could have
11764 their own REG_DEAD notes lying around. */
11765 else if ((note
== 0
11767 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11768 < GET_MODE_SIZE (GET_MODE (x
)))))
11769 && regno
< FIRST_PSEUDO_REGISTER
11770 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11772 unsigned int ourend
11773 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11774 unsigned int i
, offset
;
11778 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11782 for (i
= regno
+ offset
; i
< ourend
; i
++)
11783 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11784 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11787 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11789 XEXP (note
, 1) = *pnotes
;
11793 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11795 REG_N_DEATHS (regno
)++;
11801 else if (GET_CODE (x
) == SET
)
11803 rtx dest
= SET_DEST (x
);
11805 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11807 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11808 that accesses one word of a multi-word item, some
11809 piece of everything register in the expression is used by
11810 this insn, so remove any old death. */
11811 /* ??? So why do we test for equality of the sizes? */
11813 if (GET_CODE (dest
) == ZERO_EXTRACT
11814 || GET_CODE (dest
) == STRICT_LOW_PART
11815 || (GET_CODE (dest
) == SUBREG
11816 && (((GET_MODE_SIZE (GET_MODE (dest
))
11817 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11818 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11819 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11821 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11825 /* If this is some other SUBREG, we know it replaces the entire
11826 value, so use that as the destination. */
11827 if (GET_CODE (dest
) == SUBREG
)
11828 dest
= SUBREG_REG (dest
);
11830 /* If this is a MEM, adjust deaths of anything used in the address.
11831 For a REG (the only other possibility), the entire value is
11832 being replaced so the old value is not used in this insn. */
11834 if (GET_CODE (dest
) == MEM
)
11835 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11840 else if (GET_CODE (x
) == CLOBBER
)
11843 len
= GET_RTX_LENGTH (code
);
11844 fmt
= GET_RTX_FORMAT (code
);
11846 for (i
= 0; i
< len
; i
++)
11851 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11852 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11855 else if (fmt
[i
] == 'e')
11856 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11860 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11861 pattern of an insn. X must be a REG. */
11864 reg_bitfield_target_p (x
, body
)
11870 if (GET_CODE (body
) == SET
)
11872 rtx dest
= SET_DEST (body
);
11874 unsigned int regno
, tregno
, endregno
, endtregno
;
11876 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11877 target
= XEXP (dest
, 0);
11878 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11879 target
= SUBREG_REG (XEXP (dest
, 0));
11883 if (GET_CODE (target
) == SUBREG
)
11884 target
= SUBREG_REG (target
);
11886 if (GET_CODE (target
) != REG
)
11889 tregno
= REGNO (target
), regno
= REGNO (x
);
11890 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11891 return target
== x
;
11893 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
11894 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11896 return endregno
> tregno
&& regno
< endtregno
;
11899 else if (GET_CODE (body
) == PARALLEL
)
11900 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11901 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11907 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11908 as appropriate. I3 and I2 are the insns resulting from the combination
11909 insns including FROM (I2 may be zero).
11911 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11912 not need REG_DEAD notes because they are being substituted for. This
11913 saves searching in the most common cases.
11915 Each note in the list is either ignored or placed on some insns, depending
11916 on the type of note. */
11919 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
11923 rtx elim_i2
, elim_i1
;
11925 rtx note
, next_note
;
11928 for (note
= notes
; note
; note
= next_note
)
11930 rtx place
= 0, place2
= 0;
11932 /* If this NOTE references a pseudo register, ensure it references
11933 the latest copy of that register. */
11934 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11935 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11936 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11938 next_note
= XEXP (note
, 1);
11939 switch (REG_NOTE_KIND (note
))
11943 case REG_EXEC_COUNT
:
11944 /* Doesn't matter much where we put this, as long as it's somewhere.
11945 It is preferable to keep these notes on branches, which is most
11946 likely to be i3. */
11950 case REG_NON_LOCAL_GOTO
:
11951 if (GET_CODE (i3
) == JUMP_INSN
)
11953 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
11959 case REG_EH_REGION
:
11960 /* These notes must remain with the call or trapping instruction. */
11961 if (GET_CODE (i3
) == CALL_INSN
)
11963 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11965 else if (flag_non_call_exceptions
)
11967 if (may_trap_p (i3
))
11969 else if (i2
&& may_trap_p (i2
))
11971 /* ??? Otherwise assume we've combined things such that we
11972 can now prove that the instructions can't trap. Drop the
11973 note in this case. */
11981 /* These notes must remain with the call. It should not be
11982 possible for both I2 and I3 to be a call. */
11983 if (GET_CODE (i3
) == CALL_INSN
)
11985 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11992 /* Any clobbers for i3 may still exist, and so we must process
11993 REG_UNUSED notes from that insn.
11995 Any clobbers from i2 or i1 can only exist if they were added by
11996 recog_for_combine. In that case, recog_for_combine created the
11997 necessary REG_UNUSED notes. Trying to keep any original
11998 REG_UNUSED notes from these insns can cause incorrect output
11999 if it is for the same register as the original i3 dest.
12000 In that case, we will notice that the register is set in i3,
12001 and then add a REG_UNUSED note for the destination of i3, which
12002 is wrong. However, it is possible to have REG_UNUSED notes from
12003 i2 or i1 for register which were both used and clobbered, so
12004 we keep notes from i2 or i1 if they will turn into REG_DEAD
12007 /* If this register is set or clobbered in I3, put the note there
12008 unless there is one already. */
12009 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12011 if (from_insn
!= i3
)
12014 if (! (GET_CODE (XEXP (note
, 0)) == REG
12015 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12016 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12019 /* Otherwise, if this register is used by I3, then this register
12020 now dies here, so we must put a REG_DEAD note here unless there
12022 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12023 && ! (GET_CODE (XEXP (note
, 0)) == REG
12024 ? find_regno_note (i3
, REG_DEAD
,
12025 REGNO (XEXP (note
, 0)))
12026 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12028 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12036 /* These notes say something about results of an insn. We can
12037 only support them if they used to be on I3 in which case they
12038 remain on I3. Otherwise they are ignored.
12040 If the note refers to an expression that is not a constant, we
12041 must also ignore the note since we cannot tell whether the
12042 equivalence is still true. It might be possible to do
12043 slightly better than this (we only have a problem if I2DEST
12044 or I1DEST is present in the expression), but it doesn't
12045 seem worth the trouble. */
12047 if (from_insn
== i3
12048 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12053 case REG_NO_CONFLICT
:
12054 /* These notes say something about how a register is used. They must
12055 be present on any use of the register in I2 or I3. */
12056 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12059 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12069 /* This can show up in several ways -- either directly in the
12070 pattern, or hidden off in the constant pool with (or without?)
12071 a REG_EQUAL note. */
12072 /* ??? Ignore the without-reg_equal-note problem for now. */
12073 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12074 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12075 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12076 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12080 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12081 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12082 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12083 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12094 /* These notes say something about the value of a register prior
12095 to the execution of an insn. It is too much trouble to see
12096 if the note is still correct in all situations. It is better
12097 to simply delete it. */
12101 /* If the insn previously containing this note still exists,
12102 put it back where it was. Otherwise move it to the previous
12103 insn. Adjust the corresponding REG_LIBCALL note. */
12104 if (GET_CODE (from_insn
) != NOTE
)
12108 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12109 place
= prev_real_insn (from_insn
);
12111 XEXP (tem
, 0) = place
;
12112 /* If we're deleting the last remaining instruction of a
12113 libcall sequence, don't add the notes. */
12114 else if (XEXP (note
, 0) == from_insn
)
12120 /* This is handled similarly to REG_RETVAL. */
12121 if (GET_CODE (from_insn
) != NOTE
)
12125 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12126 place
= next_real_insn (from_insn
);
12128 XEXP (tem
, 0) = place
;
12129 /* If we're deleting the last remaining instruction of a
12130 libcall sequence, don't add the notes. */
12131 else if (XEXP (note
, 0) == from_insn
)
12137 /* If the register is used as an input in I3, it dies there.
12138 Similarly for I2, if it is non-zero and adjacent to I3.
12140 If the register is not used as an input in either I3 or I2
12141 and it is not one of the registers we were supposed to eliminate,
12142 there are two possibilities. We might have a non-adjacent I2
12143 or we might have somehow eliminated an additional register
12144 from a computation. For example, we might have had A & B where
12145 we discover that B will always be zero. In this case we will
12146 eliminate the reference to A.
12148 In both cases, we must search to see if we can find a previous
12149 use of A and put the death note there. */
12152 && GET_CODE (from_insn
) == CALL_INSN
12153 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12155 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12157 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12158 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12161 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12162 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12167 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12169 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12171 if (! INSN_P (tem
))
12173 if (tem
== bb
->head
)
12178 /* If the register is being set at TEM, see if that is all
12179 TEM is doing. If so, delete TEM. Otherwise, make this
12180 into a REG_UNUSED note instead. */
12181 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12183 rtx set
= single_set (tem
);
12184 rtx inner_dest
= 0;
12186 rtx cc0_setter
= NULL_RTX
;
12190 for (inner_dest
= SET_DEST (set
);
12191 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12192 || GET_CODE (inner_dest
) == SUBREG
12193 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12194 inner_dest
= XEXP (inner_dest
, 0))
12197 /* Verify that it was the set, and not a clobber that
12198 modified the register.
12200 CC0 targets must be careful to maintain setter/user
12201 pairs. If we cannot delete the setter due to side
12202 effects, mark the user with an UNUSED note instead
12205 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12206 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12208 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12209 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12210 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12214 /* Move the notes and links of TEM elsewhere.
12215 This might delete other dead insns recursively.
12216 First set the pattern to something that won't use
12219 PATTERN (tem
) = pc_rtx
;
12221 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12222 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12223 distribute_links (LOG_LINKS (tem
));
12225 PUT_CODE (tem
, NOTE
);
12226 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12227 NOTE_SOURCE_FILE (tem
) = 0;
12230 /* Delete the setter too. */
12233 PATTERN (cc0_setter
) = pc_rtx
;
12235 distribute_notes (REG_NOTES (cc0_setter
),
12236 cc0_setter
, cc0_setter
,
12237 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12238 distribute_links (LOG_LINKS (cc0_setter
));
12240 PUT_CODE (cc0_setter
, NOTE
);
12241 NOTE_LINE_NUMBER (cc0_setter
)
12242 = NOTE_INSN_DELETED
;
12243 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12247 /* If the register is both set and used here, put the
12248 REG_DEAD note here, but place a REG_UNUSED note
12249 here too unless there already is one. */
12250 else if (reg_referenced_p (XEXP (note
, 0),
12255 if (! find_regno_note (tem
, REG_UNUSED
,
12256 REGNO (XEXP (note
, 0))))
12258 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12263 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12265 /* If there isn't already a REG_UNUSED note, put one
12267 if (! find_regno_note (tem
, REG_UNUSED
,
12268 REGNO (XEXP (note
, 0))))
12273 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12274 || (GET_CODE (tem
) == CALL_INSN
12275 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12279 /* If we are doing a 3->2 combination, and we have a
12280 register which formerly died in i3 and was not used
12281 by i2, which now no longer dies in i3 and is used in
12282 i2 but does not die in i2, and place is between i2
12283 and i3, then we may need to move a link from place to
12285 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12286 && INSN_CUID (place
) > INSN_CUID (i2
)
12288 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12289 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12291 rtx links
= LOG_LINKS (place
);
12292 LOG_LINKS (place
) = 0;
12293 distribute_links (links
);
12298 if (tem
== bb
->head
)
12302 /* We haven't found an insn for the death note and it
12303 is still a REG_DEAD note, but we have hit the beginning
12304 of the block. If the existing life info says the reg
12305 was dead, there's nothing left to do. Otherwise, we'll
12306 need to do a global life update after combine. */
12307 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12308 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12309 REGNO (XEXP (note
, 0))))
12311 SET_BIT (refresh_blocks
, this_basic_block
);
12316 /* If the register is set or already dead at PLACE, we needn't do
12317 anything with this note if it is still a REG_DEAD note.
12318 We can here if it is set at all, not if is it totally replace,
12319 which is what `dead_or_set_p' checks, so also check for it being
12322 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12324 unsigned int regno
= REGNO (XEXP (note
, 0));
12326 /* Similarly, if the instruction on which we want to place
12327 the note is a noop, we'll need do a global live update
12328 after we remove them in delete_noop_moves. */
12329 if (noop_move_p (place
))
12331 SET_BIT (refresh_blocks
, this_basic_block
);
12335 if (dead_or_set_p (place
, XEXP (note
, 0))
12336 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12338 /* Unless the register previously died in PLACE, clear
12339 reg_last_death. [I no longer understand why this is
12341 if (reg_last_death
[regno
] != place
)
12342 reg_last_death
[regno
] = 0;
12346 reg_last_death
[regno
] = place
;
12348 /* If this is a death note for a hard reg that is occupying
12349 multiple registers, ensure that we are still using all
12350 parts of the object. If we find a piece of the object
12351 that is unused, we must arrange for an appropriate REG_DEAD
12352 note to be added for it. However, we can't just emit a USE
12353 and tag the note to it, since the register might actually
12354 be dead; so we recourse, and the recursive call then finds
12355 the previous insn that used this register. */
12357 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12358 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12360 unsigned int endregno
12361 = regno
+ HARD_REGNO_NREGS (regno
,
12362 GET_MODE (XEXP (note
, 0)));
12366 for (i
= regno
; i
< endregno
; i
++)
12367 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12368 && ! find_regno_fusage (place
, USE
, i
))
12369 || dead_or_set_regno_p (place
, i
))
12374 /* Put only REG_DEAD notes for pieces that are
12375 not already dead or set. */
12377 for (i
= regno
; i
< endregno
;
12378 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12380 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12381 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12383 if (! dead_or_set_p (place
, piece
)
12384 && ! reg_bitfield_target_p (piece
,
12388 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12390 distribute_notes (new_note
, place
, place
,
12391 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12393 else if (! refers_to_regno_p (i
, i
+ 1,
12394 PATTERN (place
), 0)
12395 && ! find_regno_fusage (place
, USE
, i
))
12396 for (tem
= PREV_INSN (place
); ;
12397 tem
= PREV_INSN (tem
))
12399 if (! INSN_P (tem
))
12401 if (tem
== bb
->head
)
12403 SET_BIT (refresh_blocks
,
12410 if (dead_or_set_p (tem
, piece
)
12411 || reg_bitfield_target_p (piece
,
12415 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12430 /* Any other notes should not be present at this point in the
12437 XEXP (note
, 1) = REG_NOTES (place
);
12438 REG_NOTES (place
) = note
;
12440 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12441 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12442 && GET_CODE (XEXP (note
, 0)) == REG
)
12443 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12447 if ((REG_NOTE_KIND (note
) == REG_DEAD
12448 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12449 && GET_CODE (XEXP (note
, 0)) == REG
)
12450 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12452 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12453 REG_NOTE_KIND (note
),
12455 REG_NOTES (place2
));
12460 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12461 I3, I2, and I1 to new locations. This is also called in one case to
12462 add a link pointing at I3 when I3's destination is changed. */
12465 distribute_links (links
)
12468 rtx link
, next_link
;
12470 for (link
= links
; link
; link
= next_link
)
12476 next_link
= XEXP (link
, 1);
12478 /* If the insn that this link points to is a NOTE or isn't a single
12479 set, ignore it. In the latter case, it isn't clear what we
12480 can do other than ignore the link, since we can't tell which
12481 register it was for. Such links wouldn't be used by combine
12484 It is not possible for the destination of the target of the link to
12485 have been changed by combine. The only potential of this is if we
12486 replace I3, I2, and I1 by I3 and I2. But in that case the
12487 destination of I2 also remains unchanged. */
12489 if (GET_CODE (XEXP (link
, 0)) == NOTE
12490 || (set
= single_set (XEXP (link
, 0))) == 0)
12493 reg
= SET_DEST (set
);
12494 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12495 || GET_CODE (reg
) == SIGN_EXTRACT
12496 || GET_CODE (reg
) == STRICT_LOW_PART
)
12497 reg
= XEXP (reg
, 0);
12499 /* A LOG_LINK is defined as being placed on the first insn that uses
12500 a register and points to the insn that sets the register. Start
12501 searching at the next insn after the target of the link and stop
12502 when we reach a set of the register or the end of the basic block.
12504 Note that this correctly handles the link that used to point from
12505 I3 to I2. Also note that not much searching is typically done here
12506 since most links don't point very far away. */
12508 for (insn
= NEXT_INSN (XEXP (link
, 0));
12509 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12510 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12511 insn
= NEXT_INSN (insn
))
12512 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12514 if (reg_referenced_p (reg
, PATTERN (insn
)))
12518 else if (GET_CODE (insn
) == CALL_INSN
12519 && find_reg_fusage (insn
, USE
, reg
))
12525 /* If we found a place to put the link, place it there unless there
12526 is already a link to the same insn as LINK at that point. */
12532 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12533 if (XEXP (link2
, 0) == XEXP (link
, 0))
12538 XEXP (link
, 1) = LOG_LINKS (place
);
12539 LOG_LINKS (place
) = link
;
12541 /* Set added_links_insn to the earliest insn we added a
12543 if (added_links_insn
== 0
12544 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12545 added_links_insn
= place
;
12551 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12557 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12558 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12559 insn
= NEXT_INSN (insn
);
12561 if (INSN_UID (insn
) > max_uid_cuid
)
12564 return INSN_CUID (insn
);
12568 dump_combine_stats (file
)
12573 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12574 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12578 dump_combine_total_stats (file
)
12583 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12584 total_attempts
, total_merges
, total_extras
, total_successes
);