1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
56 #include "tree-flow.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack
{
76 int first_gp_reg_save
; /* first callee saved GP register used */
77 int first_fp_reg_save
; /* first callee saved FP register used */
78 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
79 int lr_save_p
; /* true if the link reg needs to be saved */
80 int cr_save_p
; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask
; /* mask of vec registers to save */
82 int push_p
; /* true if we need to allocate stack space */
83 int calls_p
; /* true if the function makes any calls */
84 int world_save_p
; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi
; /* which ABI to use */
87 int gp_save_offset
; /* offset to save GP regs from initial SP */
88 int fp_save_offset
; /* offset to save FP regs from initial SP */
89 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset
; /* offset to save LR from initial SP */
91 int cr_save_offset
; /* offset to save CR from initial SP */
92 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset
; /* offset to save the varargs registers */
95 int ehrd_offset
; /* offset to EH return data */
96 int reg_size
; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size
; /* variable save area size */
98 int parm_size
; /* outgoing parameter size */
99 int save_size
; /* save area size */
100 int fixed_size
; /* fixed size of stack frame */
101 int gp_size
; /* size of saved GP registers */
102 int fp_size
; /* size of saved FP registers */
103 int altivec_size
; /* size of saved AltiVec registers */
104 int cr_size
; /* size to hold CR if not in save_size */
105 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size
; /* size of altivec alignment padding if
108 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size
;
110 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
111 int spe_64bit_regs_used
;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function
GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame
;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name
;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p
;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset
;
129 /* Temporary stack slot to use for SDmode copies. This slot is
130 64-bits wide and is allocated early enough so that the offset
131 does not overflow the 16-bit load/store offset field. */
132 rtx sdmode_stack_slot
;
135 /* Target cpu type */
137 enum processor_type rs6000_cpu
;
138 struct rs6000_cpu_select rs6000_select
[3] =
140 /* switch name, tune arch */
141 { (const char *)0, "--with-cpu=", 1, 1 },
142 { (const char *)0, "-mcpu=", 1, 1 },
143 { (const char *)0, "-mtune=", 1, 0 },
146 static GTY(()) bool rs6000_cell_dont_microcode
;
148 /* Always emit branch hint bits. */
149 static GTY(()) bool rs6000_always_hint
;
151 /* Schedule instructions for group formation. */
152 static GTY(()) bool rs6000_sched_groups
;
154 /* Align branch targets. */
155 static GTY(()) bool rs6000_align_branch_targets
;
157 /* Support for -msched-costly-dep option. */
158 const char *rs6000_sched_costly_dep_str
;
159 enum rs6000_dependence_cost rs6000_sched_costly_dep
;
161 /* Support for -minsert-sched-nops option. */
162 const char *rs6000_sched_insert_nops_str
;
163 enum rs6000_nop_insertion rs6000_sched_insert_nops
;
165 /* Support targetm.vectorize.builtin_mask_for_load. */
166 static GTY(()) tree altivec_builtin_mask_for_load
;
168 /* Size of long double. */
169 int rs6000_long_double_type_size
;
171 /* IEEE quad extended precision long double. */
174 /* Nonzero to use AltiVec ABI. */
175 int rs6000_altivec_abi
;
177 /* Nonzero if we want SPE ABI extensions. */
180 /* Nonzero if floating point operations are done in the GPRs. */
181 int rs6000_float_gprs
= 0;
183 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
184 int rs6000_darwin64_abi
;
186 /* Set to nonzero once AIX common-mode calls have been defined. */
187 static GTY(()) int common_mode_defined
;
189 /* Save information from a "cmpxx" operation until the branch or scc is
191 rtx rs6000_compare_op0
, rs6000_compare_op1
;
192 int rs6000_compare_fp_p
;
194 /* Label number of label created for -mrelocatable, to call to so we can
195 get the address of the GOT section */
196 int rs6000_pic_labelno
;
199 /* Which abi to adhere to */
200 const char *rs6000_abi_name
;
202 /* Semantics of the small data area */
203 enum rs6000_sdata_type rs6000_sdata
= SDATA_DATA
;
205 /* Which small data model to use */
206 const char *rs6000_sdata_name
= (char *)0;
208 /* Counter for labels which are to be placed in .fixup. */
209 int fixuplabelno
= 0;
212 /* Bit size of immediate TLS offsets and string from which it is decoded. */
213 int rs6000_tls_size
= 32;
214 const char *rs6000_tls_size_string
;
216 /* ABI enumeration available for subtarget to use. */
217 enum rs6000_abi rs6000_current_abi
;
219 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
223 const char *rs6000_debug_name
;
224 int rs6000_debug_stack
; /* debug stack applications */
225 int rs6000_debug_arg
; /* debug argument handling */
227 /* Value is TRUE if register/mode pair is acceptable. */
228 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
230 /* Built in types. */
232 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
233 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
235 const char *rs6000_traceback_name
;
237 traceback_default
= 0,
243 /* Flag to say the TOC is initialized */
245 char toc_label_name
[10];
247 /* Cached value of rs6000_variable_issue. This is cached in
248 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
249 static short cached_can_issue_more
;
251 static GTY(()) section
*read_only_data_section
;
252 static GTY(()) section
*private_data_section
;
253 static GTY(()) section
*read_only_private_data_section
;
254 static GTY(()) section
*sdata2_section
;
255 static GTY(()) section
*toc_section
;
257 /* Control alignment for fields within structures. */
258 /* String from -malign-XXXXX. */
259 int rs6000_alignment_flags
;
261 /* True for any options that were explicitly set. */
263 bool aix_struct_ret
; /* True if -maix-struct-ret was used. */
264 bool alignment
; /* True if -malign- was used. */
265 bool spe_abi
; /* True if -mabi=spe/no-spe was used. */
266 bool altivec_abi
; /* True if -mabi=altivec/no-altivec used. */
267 bool spe
; /* True if -mspe= was used. */
268 bool float_gprs
; /* True if -mfloat-gprs= was used. */
269 bool isel
; /* True if -misel was used. */
270 bool long_double
; /* True if -mlong-double- was used. */
271 bool ieee
; /* True if -mabi=ieee/ibmlongdouble used. */
272 bool vrsave
; /* True if -mvrsave was used. */
273 } rs6000_explicit_options
;
275 struct builtin_description
277 /* mask is not const because we're going to alter it below. This
278 nonsense will go away when we rewrite the -march infrastructure
279 to give us more target flag bits. */
281 const enum insn_code icode
;
282 const char *const name
;
283 const enum rs6000_builtins code
;
286 /* Target cpu costs. */
288 struct processor_costs
{
289 const int mulsi
; /* cost of SImode multiplication. */
290 const int mulsi_const
; /* cost of SImode multiplication by constant. */
291 const int mulsi_const9
; /* cost of SImode mult by short constant. */
292 const int muldi
; /* cost of DImode multiplication. */
293 const int divsi
; /* cost of SImode division. */
294 const int divdi
; /* cost of DImode division. */
295 const int fp
; /* cost of simple SFmode and DFmode insns. */
296 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
297 const int sdiv
; /* cost of SFmode division (fdivs). */
298 const int ddiv
; /* cost of DFmode division (fdiv). */
299 const int cache_line_size
; /* cache line size in bytes. */
300 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
301 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
302 const int simultaneous_prefetches
; /* number of parallel prefetch
306 const struct processor_costs
*rs6000_cost
;
308 /* Processor costs (relative to an add) */
310 /* Instruction size costs on 32bit processors. */
312 struct processor_costs size32_cost
= {
313 COSTS_N_INSNS (1), /* mulsi */
314 COSTS_N_INSNS (1), /* mulsi_const */
315 COSTS_N_INSNS (1), /* mulsi_const9 */
316 COSTS_N_INSNS (1), /* muldi */
317 COSTS_N_INSNS (1), /* divsi */
318 COSTS_N_INSNS (1), /* divdi */
319 COSTS_N_INSNS (1), /* fp */
320 COSTS_N_INSNS (1), /* dmul */
321 COSTS_N_INSNS (1), /* sdiv */
322 COSTS_N_INSNS (1), /* ddiv */
329 /* Instruction size costs on 64bit processors. */
331 struct processor_costs size64_cost
= {
332 COSTS_N_INSNS (1), /* mulsi */
333 COSTS_N_INSNS (1), /* mulsi_const */
334 COSTS_N_INSNS (1), /* mulsi_const9 */
335 COSTS_N_INSNS (1), /* muldi */
336 COSTS_N_INSNS (1), /* divsi */
337 COSTS_N_INSNS (1), /* divdi */
338 COSTS_N_INSNS (1), /* fp */
339 COSTS_N_INSNS (1), /* dmul */
340 COSTS_N_INSNS (1), /* sdiv */
341 COSTS_N_INSNS (1), /* ddiv */
348 /* Instruction costs on RIOS1 processors. */
350 struct processor_costs rios1_cost
= {
351 COSTS_N_INSNS (5), /* mulsi */
352 COSTS_N_INSNS (4), /* mulsi_const */
353 COSTS_N_INSNS (3), /* mulsi_const9 */
354 COSTS_N_INSNS (5), /* muldi */
355 COSTS_N_INSNS (19), /* divsi */
356 COSTS_N_INSNS (19), /* divdi */
357 COSTS_N_INSNS (2), /* fp */
358 COSTS_N_INSNS (2), /* dmul */
359 COSTS_N_INSNS (19), /* sdiv */
360 COSTS_N_INSNS (19), /* ddiv */
367 /* Instruction costs on RIOS2 processors. */
369 struct processor_costs rios2_cost
= {
370 COSTS_N_INSNS (2), /* mulsi */
371 COSTS_N_INSNS (2), /* mulsi_const */
372 COSTS_N_INSNS (2), /* mulsi_const9 */
373 COSTS_N_INSNS (2), /* muldi */
374 COSTS_N_INSNS (13), /* divsi */
375 COSTS_N_INSNS (13), /* divdi */
376 COSTS_N_INSNS (2), /* fp */
377 COSTS_N_INSNS (2), /* dmul */
378 COSTS_N_INSNS (17), /* sdiv */
379 COSTS_N_INSNS (17), /* ddiv */
386 /* Instruction costs on RS64A processors. */
388 struct processor_costs rs64a_cost
= {
389 COSTS_N_INSNS (20), /* mulsi */
390 COSTS_N_INSNS (12), /* mulsi_const */
391 COSTS_N_INSNS (8), /* mulsi_const9 */
392 COSTS_N_INSNS (34), /* muldi */
393 COSTS_N_INSNS (65), /* divsi */
394 COSTS_N_INSNS (67), /* divdi */
395 COSTS_N_INSNS (4), /* fp */
396 COSTS_N_INSNS (4), /* dmul */
397 COSTS_N_INSNS (31), /* sdiv */
398 COSTS_N_INSNS (31), /* ddiv */
405 /* Instruction costs on MPCCORE processors. */
407 struct processor_costs mpccore_cost
= {
408 COSTS_N_INSNS (2), /* mulsi */
409 COSTS_N_INSNS (2), /* mulsi_const */
410 COSTS_N_INSNS (2), /* mulsi_const9 */
411 COSTS_N_INSNS (2), /* muldi */
412 COSTS_N_INSNS (6), /* divsi */
413 COSTS_N_INSNS (6), /* divdi */
414 COSTS_N_INSNS (4), /* fp */
415 COSTS_N_INSNS (5), /* dmul */
416 COSTS_N_INSNS (10), /* sdiv */
417 COSTS_N_INSNS (17), /* ddiv */
424 /* Instruction costs on PPC403 processors. */
426 struct processor_costs ppc403_cost
= {
427 COSTS_N_INSNS (4), /* mulsi */
428 COSTS_N_INSNS (4), /* mulsi_const */
429 COSTS_N_INSNS (4), /* mulsi_const9 */
430 COSTS_N_INSNS (4), /* muldi */
431 COSTS_N_INSNS (33), /* divsi */
432 COSTS_N_INSNS (33), /* divdi */
433 COSTS_N_INSNS (11), /* fp */
434 COSTS_N_INSNS (11), /* dmul */
435 COSTS_N_INSNS (11), /* sdiv */
436 COSTS_N_INSNS (11), /* ddiv */
443 /* Instruction costs on PPC405 processors. */
445 struct processor_costs ppc405_cost
= {
446 COSTS_N_INSNS (5), /* mulsi */
447 COSTS_N_INSNS (4), /* mulsi_const */
448 COSTS_N_INSNS (3), /* mulsi_const9 */
449 COSTS_N_INSNS (5), /* muldi */
450 COSTS_N_INSNS (35), /* divsi */
451 COSTS_N_INSNS (35), /* divdi */
452 COSTS_N_INSNS (11), /* fp */
453 COSTS_N_INSNS (11), /* dmul */
454 COSTS_N_INSNS (11), /* sdiv */
455 COSTS_N_INSNS (11), /* ddiv */
462 /* Instruction costs on PPC440 processors. */
464 struct processor_costs ppc440_cost
= {
465 COSTS_N_INSNS (3), /* mulsi */
466 COSTS_N_INSNS (2), /* mulsi_const */
467 COSTS_N_INSNS (2), /* mulsi_const9 */
468 COSTS_N_INSNS (3), /* muldi */
469 COSTS_N_INSNS (34), /* divsi */
470 COSTS_N_INSNS (34), /* divdi */
471 COSTS_N_INSNS (5), /* fp */
472 COSTS_N_INSNS (5), /* dmul */
473 COSTS_N_INSNS (19), /* sdiv */
474 COSTS_N_INSNS (33), /* ddiv */
481 /* Instruction costs on PPC601 processors. */
483 struct processor_costs ppc601_cost
= {
484 COSTS_N_INSNS (5), /* mulsi */
485 COSTS_N_INSNS (5), /* mulsi_const */
486 COSTS_N_INSNS (5), /* mulsi_const9 */
487 COSTS_N_INSNS (5), /* muldi */
488 COSTS_N_INSNS (36), /* divsi */
489 COSTS_N_INSNS (36), /* divdi */
490 COSTS_N_INSNS (4), /* fp */
491 COSTS_N_INSNS (5), /* dmul */
492 COSTS_N_INSNS (17), /* sdiv */
493 COSTS_N_INSNS (31), /* ddiv */
500 /* Instruction costs on PPC603 processors. */
502 struct processor_costs ppc603_cost
= {
503 COSTS_N_INSNS (5), /* mulsi */
504 COSTS_N_INSNS (3), /* mulsi_const */
505 COSTS_N_INSNS (2), /* mulsi_const9 */
506 COSTS_N_INSNS (5), /* muldi */
507 COSTS_N_INSNS (37), /* divsi */
508 COSTS_N_INSNS (37), /* divdi */
509 COSTS_N_INSNS (3), /* fp */
510 COSTS_N_INSNS (4), /* dmul */
511 COSTS_N_INSNS (18), /* sdiv */
512 COSTS_N_INSNS (33), /* ddiv */
519 /* Instruction costs on PPC604 processors. */
521 struct processor_costs ppc604_cost
= {
522 COSTS_N_INSNS (4), /* mulsi */
523 COSTS_N_INSNS (4), /* mulsi_const */
524 COSTS_N_INSNS (4), /* mulsi_const9 */
525 COSTS_N_INSNS (4), /* muldi */
526 COSTS_N_INSNS (20), /* divsi */
527 COSTS_N_INSNS (20), /* divdi */
528 COSTS_N_INSNS (3), /* fp */
529 COSTS_N_INSNS (3), /* dmul */
530 COSTS_N_INSNS (18), /* sdiv */
531 COSTS_N_INSNS (32), /* ddiv */
538 /* Instruction costs on PPC604e processors. */
540 struct processor_costs ppc604e_cost
= {
541 COSTS_N_INSNS (2), /* mulsi */
542 COSTS_N_INSNS (2), /* mulsi_const */
543 COSTS_N_INSNS (2), /* mulsi_const9 */
544 COSTS_N_INSNS (2), /* muldi */
545 COSTS_N_INSNS (20), /* divsi */
546 COSTS_N_INSNS (20), /* divdi */
547 COSTS_N_INSNS (3), /* fp */
548 COSTS_N_INSNS (3), /* dmul */
549 COSTS_N_INSNS (18), /* sdiv */
550 COSTS_N_INSNS (32), /* ddiv */
557 /* Instruction costs on PPC620 processors. */
559 struct processor_costs ppc620_cost
= {
560 COSTS_N_INSNS (5), /* mulsi */
561 COSTS_N_INSNS (4), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (7), /* muldi */
564 COSTS_N_INSNS (21), /* divsi */
565 COSTS_N_INSNS (37), /* divdi */
566 COSTS_N_INSNS (3), /* fp */
567 COSTS_N_INSNS (3), /* dmul */
568 COSTS_N_INSNS (18), /* sdiv */
569 COSTS_N_INSNS (32), /* ddiv */
576 /* Instruction costs on PPC630 processors. */
578 struct processor_costs ppc630_cost
= {
579 COSTS_N_INSNS (5), /* mulsi */
580 COSTS_N_INSNS (4), /* mulsi_const */
581 COSTS_N_INSNS (3), /* mulsi_const9 */
582 COSTS_N_INSNS (7), /* muldi */
583 COSTS_N_INSNS (21), /* divsi */
584 COSTS_N_INSNS (37), /* divdi */
585 COSTS_N_INSNS (3), /* fp */
586 COSTS_N_INSNS (3), /* dmul */
587 COSTS_N_INSNS (17), /* sdiv */
588 COSTS_N_INSNS (21), /* ddiv */
595 /* Instruction costs on Cell processor. */
596 /* COSTS_N_INSNS (1) ~ one add. */
598 struct processor_costs ppccell_cost
= {
599 COSTS_N_INSNS (9/2)+2, /* mulsi */
600 COSTS_N_INSNS (6/2), /* mulsi_const */
601 COSTS_N_INSNS (6/2), /* mulsi_const9 */
602 COSTS_N_INSNS (15/2)+2, /* muldi */
603 COSTS_N_INSNS (38/2), /* divsi */
604 COSTS_N_INSNS (70/2), /* divdi */
605 COSTS_N_INSNS (10/2), /* fp */
606 COSTS_N_INSNS (10/2), /* dmul */
607 COSTS_N_INSNS (74/2), /* sdiv */
608 COSTS_N_INSNS (74/2), /* ddiv */
615 /* Instruction costs on PPC750 and PPC7400 processors. */
617 struct processor_costs ppc750_cost
= {
618 COSTS_N_INSNS (5), /* mulsi */
619 COSTS_N_INSNS (3), /* mulsi_const */
620 COSTS_N_INSNS (2), /* mulsi_const9 */
621 COSTS_N_INSNS (5), /* muldi */
622 COSTS_N_INSNS (17), /* divsi */
623 COSTS_N_INSNS (17), /* divdi */
624 COSTS_N_INSNS (3), /* fp */
625 COSTS_N_INSNS (3), /* dmul */
626 COSTS_N_INSNS (17), /* sdiv */
627 COSTS_N_INSNS (31), /* ddiv */
634 /* Instruction costs on PPC7450 processors. */
636 struct processor_costs ppc7450_cost
= {
637 COSTS_N_INSNS (4), /* mulsi */
638 COSTS_N_INSNS (3), /* mulsi_const */
639 COSTS_N_INSNS (3), /* mulsi_const9 */
640 COSTS_N_INSNS (4), /* muldi */
641 COSTS_N_INSNS (23), /* divsi */
642 COSTS_N_INSNS (23), /* divdi */
643 COSTS_N_INSNS (5), /* fp */
644 COSTS_N_INSNS (5), /* dmul */
645 COSTS_N_INSNS (21), /* sdiv */
646 COSTS_N_INSNS (35), /* ddiv */
653 /* Instruction costs on PPC8540 processors. */
655 struct processor_costs ppc8540_cost
= {
656 COSTS_N_INSNS (4), /* mulsi */
657 COSTS_N_INSNS (4), /* mulsi_const */
658 COSTS_N_INSNS (4), /* mulsi_const9 */
659 COSTS_N_INSNS (4), /* muldi */
660 COSTS_N_INSNS (19), /* divsi */
661 COSTS_N_INSNS (19), /* divdi */
662 COSTS_N_INSNS (4), /* fp */
663 COSTS_N_INSNS (4), /* dmul */
664 COSTS_N_INSNS (29), /* sdiv */
665 COSTS_N_INSNS (29), /* ddiv */
669 1, /* prefetch streams /*/
672 /* Instruction costs on POWER4 and POWER5 processors. */
674 struct processor_costs power4_cost
= {
675 COSTS_N_INSNS (3), /* mulsi */
676 COSTS_N_INSNS (2), /* mulsi_const */
677 COSTS_N_INSNS (2), /* mulsi_const9 */
678 COSTS_N_INSNS (4), /* muldi */
679 COSTS_N_INSNS (18), /* divsi */
680 COSTS_N_INSNS (34), /* divdi */
681 COSTS_N_INSNS (3), /* fp */
682 COSTS_N_INSNS (3), /* dmul */
683 COSTS_N_INSNS (17), /* sdiv */
684 COSTS_N_INSNS (17), /* ddiv */
688 8, /* prefetch streams /*/
691 /* Instruction costs on POWER6 processors. */
693 struct processor_costs power6_cost
= {
694 COSTS_N_INSNS (8), /* mulsi */
695 COSTS_N_INSNS (8), /* mulsi_const */
696 COSTS_N_INSNS (8), /* mulsi_const9 */
697 COSTS_N_INSNS (8), /* muldi */
698 COSTS_N_INSNS (22), /* divsi */
699 COSTS_N_INSNS (28), /* divdi */
700 COSTS_N_INSNS (3), /* fp */
701 COSTS_N_INSNS (3), /* dmul */
702 COSTS_N_INSNS (13), /* sdiv */
703 COSTS_N_INSNS (16), /* ddiv */
707 16, /* prefetch streams */
711 static bool rs6000_function_ok_for_sibcall (tree
, tree
);
712 static const char *rs6000_invalid_within_doloop (const_rtx
);
713 static rtx
rs6000_generate_compare (enum rtx_code
);
714 static void rs6000_emit_stack_tie (void);
715 static void rs6000_frame_related (rtx
, rtx
, HOST_WIDE_INT
, rtx
, rtx
);
716 static rtx
spe_synthesize_frame_save (rtx
);
717 static bool spe_func_has_64bit_regs_p (void);
718 static void emit_frame_save (rtx
, rtx
, enum machine_mode
, unsigned int,
720 static rtx
gen_frame_mem_offset (enum machine_mode
, rtx
, int);
721 static void rs6000_emit_allocate_stack (HOST_WIDE_INT
, int);
722 static unsigned rs6000_hash_constant (rtx
);
723 static unsigned toc_hash_function (const void *);
724 static int toc_hash_eq (const void *, const void *);
725 static int constant_pool_expr_1 (rtx
, int *, int *);
726 static bool constant_pool_expr_p (rtx
);
727 static bool legitimate_small_data_p (enum machine_mode
, rtx
);
728 static bool legitimate_lo_sum_address_p (enum machine_mode
, rtx
, int);
729 static struct machine_function
* rs6000_init_machine_status (void);
730 static bool rs6000_assemble_integer (rtx
, unsigned int, int);
731 static bool no_global_regs_above (int);
732 #ifdef HAVE_GAS_HIDDEN
733 static void rs6000_assemble_visibility (tree
, int);
735 static int rs6000_ra_ever_killed (void);
736 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
737 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
738 static bool rs6000_ms_bitfield_layout_p (const_tree
);
739 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
740 static void rs6000_eliminate_indexed_memrefs (rtx operands
[2]);
741 static const char *rs6000_mangle_type (const_tree
);
742 extern const struct attribute_spec rs6000_attribute_table
[];
743 static void rs6000_set_default_type_attributes (tree
);
744 static bool rs6000_reg_live_or_pic_offset_p (int);
745 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT
);
746 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT
);
747 static void rs6000_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
749 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
750 static bool rs6000_return_in_memory (const_tree
, const_tree
);
751 static void rs6000_file_start (void);
753 static int rs6000_elf_reloc_rw_mask (void);
754 static void rs6000_elf_asm_out_constructor (rtx
, int);
755 static void rs6000_elf_asm_out_destructor (rtx
, int);
756 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED
;
757 static void rs6000_elf_asm_init_sections (void);
758 static section
*rs6000_elf_select_rtx_section (enum machine_mode
, rtx
,
759 unsigned HOST_WIDE_INT
);
760 static void rs6000_elf_encode_section_info (tree
, rtx
, int)
763 static bool rs6000_use_blocks_for_constant_p (enum machine_mode
, const_rtx
);
764 static void rs6000_alloc_sdmode_stack_slot (void);
765 static void rs6000_instantiate_decls (void);
767 static void rs6000_xcoff_asm_output_anchor (rtx
);
768 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
769 static void rs6000_xcoff_asm_init_sections (void);
770 static int rs6000_xcoff_reloc_rw_mask (void);
771 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree
);
772 static section
*rs6000_xcoff_select_section (tree
, int,
773 unsigned HOST_WIDE_INT
);
774 static void rs6000_xcoff_unique_section (tree
, int);
775 static section
*rs6000_xcoff_select_rtx_section
776 (enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
);
777 static const char * rs6000_xcoff_strip_name_encoding (const char *);
778 static unsigned int rs6000_xcoff_section_type_flags (tree
, const char *, int);
779 static void rs6000_xcoff_file_start (void);
780 static void rs6000_xcoff_file_end (void);
782 static int rs6000_variable_issue (FILE *, int, rtx
, int);
783 static bool rs6000_rtx_costs (rtx
, int, int, int *);
784 static int rs6000_adjust_cost (rtx
, rtx
, rtx
, int);
785 static void rs6000_sched_init (FILE *, int, int);
786 static bool is_microcoded_insn (rtx
);
787 static bool is_nonpipeline_insn (rtx
);
788 static bool is_cracked_insn (rtx
);
789 static bool is_branch_slot_insn (rtx
);
790 static bool is_load_insn (rtx
);
791 static rtx
get_store_dest (rtx pat
);
792 static bool is_store_insn (rtx
);
793 static bool set_to_load_agen (rtx
,rtx
);
794 static bool adjacent_mem_locations (rtx
,rtx
);
795 static int rs6000_adjust_priority (rtx
, int);
796 static int rs6000_issue_rate (void);
797 static bool rs6000_is_costly_dependence (dep_t
, int, int);
798 static rtx
get_next_active_insn (rtx
, rtx
);
799 static bool insn_terminates_group_p (rtx
, enum group_termination
);
800 static bool insn_must_be_first_in_group (rtx
);
801 static bool insn_must_be_last_in_group (rtx
);
802 static bool is_costly_group (rtx
*, rtx
);
803 static int force_new_group (int, FILE *, rtx
*, rtx
, bool *, int, int *);
804 static int redefine_groups (FILE *, int, rtx
, rtx
);
805 static int pad_groups (FILE *, int, rtx
, rtx
);
806 static void rs6000_sched_finish (FILE *, int);
807 static int rs6000_sched_reorder (FILE *, int, rtx
*, int *, int);
808 static int rs6000_sched_reorder2 (FILE *, int, rtx
*, int *, int);
809 static int rs6000_use_sched_lookahead (void);
810 static int rs6000_use_sched_lookahead_guard (rtx
);
811 static tree
rs6000_builtin_reciprocal (unsigned int, bool, bool);
812 static tree
rs6000_builtin_mask_for_load (void);
813 static tree
rs6000_builtin_mul_widen_even (tree
);
814 static tree
rs6000_builtin_mul_widen_odd (tree
);
815 static tree
rs6000_builtin_conversion (enum tree_code
, tree
);
817 static void def_builtin (int, const char *, tree
, int);
818 static bool rs6000_vector_alignment_reachable (const_tree
, bool);
819 static void rs6000_init_builtins (void);
820 static rtx
rs6000_expand_unop_builtin (enum insn_code
, tree
, rtx
);
821 static rtx
rs6000_expand_binop_builtin (enum insn_code
, tree
, rtx
);
822 static rtx
rs6000_expand_ternop_builtin (enum insn_code
, tree
, rtx
);
823 static rtx
rs6000_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
824 static void altivec_init_builtins (void);
825 static void rs6000_common_init_builtins (void);
826 static void rs6000_init_libfuncs (void);
828 static void paired_init_builtins (void);
829 static rtx
paired_expand_builtin (tree
, rtx
, bool *);
830 static rtx
paired_expand_lv_builtin (enum insn_code
, tree
, rtx
);
831 static rtx
paired_expand_stv_builtin (enum insn_code
, tree
);
832 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
834 static void enable_mask_for_builtins (struct builtin_description
*, int,
835 enum rs6000_builtins
,
836 enum rs6000_builtins
);
837 static tree
build_opaque_vector_type (tree
, int);
838 static void spe_init_builtins (void);
839 static rtx
spe_expand_builtin (tree
, rtx
, bool *);
840 static rtx
spe_expand_stv_builtin (enum insn_code
, tree
);
841 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
842 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
843 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
844 static rs6000_stack_t
*rs6000_stack_info (void);
845 static void debug_stack_info (rs6000_stack_t
*);
847 static rtx
altivec_expand_builtin (tree
, rtx
, bool *);
848 static rtx
altivec_expand_ld_builtin (tree
, rtx
, bool *);
849 static rtx
altivec_expand_st_builtin (tree
, rtx
, bool *);
850 static rtx
altivec_expand_dst_builtin (tree
, rtx
, bool *);
851 static rtx
altivec_expand_abs_builtin (enum insn_code
, tree
, rtx
);
852 static rtx
altivec_expand_predicate_builtin (enum insn_code
,
853 const char *, tree
, rtx
);
854 static rtx
altivec_expand_lv_builtin (enum insn_code
, tree
, rtx
);
855 static rtx
altivec_expand_stv_builtin (enum insn_code
, tree
);
856 static rtx
altivec_expand_vec_init_builtin (tree
, tree
, rtx
);
857 static rtx
altivec_expand_vec_set_builtin (tree
);
858 static rtx
altivec_expand_vec_ext_builtin (tree
, rtx
);
859 static int get_element_number (tree
, tree
);
860 static bool rs6000_handle_option (size_t, const char *, int);
861 static void rs6000_parse_tls_size_option (void);
862 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
863 static int first_altivec_reg_to_save (void);
864 static unsigned int compute_vrsave_mask (void);
865 static void compute_save_world_info (rs6000_stack_t
*info_ptr
);
866 static void is_altivec_return_reg (rtx
, void *);
867 static rtx
generate_set_vrsave (rtx
, rs6000_stack_t
*, int);
868 int easy_vector_constant (rtx
, enum machine_mode
);
869 static bool rs6000_is_opaque_type (const_tree
);
870 static rtx
rs6000_dwarf_register_span (rtx
);
871 static void rs6000_init_dwarf_reg_sizes_extra (tree
);
872 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
873 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
874 static rtx
rs6000_tls_get_addr (void);
875 static rtx
rs6000_got_sym (void);
876 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
877 static const char *rs6000_get_some_local_dynamic_name (void);
878 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
879 static rtx
rs6000_complex_function_value (enum machine_mode
);
880 static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS
*,
881 enum machine_mode
, tree
);
882 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*,
884 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*,
885 tree
, HOST_WIDE_INT
);
886 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*,
889 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*,
890 const_tree
, HOST_WIDE_INT
,
892 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
, int, bool);
893 static rtx
rs6000_mixed_function_arg (enum machine_mode
, tree
, int);
894 static void rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
);
895 static void setup_incoming_varargs (CUMULATIVE_ARGS
*,
896 enum machine_mode
, tree
,
898 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
900 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
902 static const char *invalid_arg_for_unprototyped_fn (const_tree
, const_tree
, const_tree
);
904 static void macho_branch_islands (void);
905 static int no_previous_def (tree function_name
);
906 static tree
get_prev_label (tree function_name
);
907 static void rs6000_darwin_file_start (void);
910 static tree
rs6000_build_builtin_va_list (void);
911 static void rs6000_va_start (tree
, rtx
);
912 static tree
rs6000_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
913 static bool rs6000_must_pass_in_stack (enum machine_mode
, const_tree
);
914 static bool rs6000_scalar_mode_supported_p (enum machine_mode
);
915 static bool rs6000_vector_mode_supported_p (enum machine_mode
);
916 static int get_vec_cmp_insn (enum rtx_code
, enum machine_mode
,
918 static rtx
rs6000_emit_vector_compare (enum rtx_code
, rtx
, rtx
,
920 static int get_vsel_insn (enum machine_mode
);
921 static void rs6000_emit_vector_select (rtx
, rtx
, rtx
, rtx
);
922 static tree
rs6000_stack_protect_fail (void);
924 const int INSN_NOT_AVAILABLE
= -1;
925 static enum machine_mode
rs6000_eh_return_filter_mode (void);
927 /* Hash table stuff for keeping track of TOC entries. */
929 struct toc_hash_struct
GTY(())
931 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
932 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
934 enum machine_mode key_mode
;
938 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
940 /* Default register names. */
941 char rs6000_reg_names
[][8] =
943 "0", "1", "2", "3", "4", "5", "6", "7",
944 "8", "9", "10", "11", "12", "13", "14", "15",
945 "16", "17", "18", "19", "20", "21", "22", "23",
946 "24", "25", "26", "27", "28", "29", "30", "31",
947 "0", "1", "2", "3", "4", "5", "6", "7",
948 "8", "9", "10", "11", "12", "13", "14", "15",
949 "16", "17", "18", "19", "20", "21", "22", "23",
950 "24", "25", "26", "27", "28", "29", "30", "31",
951 "mq", "lr", "ctr","ap",
952 "0", "1", "2", "3", "4", "5", "6", "7",
954 /* AltiVec registers. */
955 "0", "1", "2", "3", "4", "5", "6", "7",
956 "8", "9", "10", "11", "12", "13", "14", "15",
957 "16", "17", "18", "19", "20", "21", "22", "23",
958 "24", "25", "26", "27", "28", "29", "30", "31",
961 "spe_acc", "spefscr",
962 /* Soft frame pointer. */
966 #ifdef TARGET_REGNAMES
967 static const char alt_reg_names
[][8] =
969 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
970 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
971 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
972 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
973 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
974 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
975 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
976 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
977 "mq", "lr", "ctr", "ap",
978 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
980 /* AltiVec registers. */
981 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
982 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
983 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
984 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
987 "spe_acc", "spefscr",
988 /* Soft frame pointer. */
993 #ifndef MASK_STRICT_ALIGN
994 #define MASK_STRICT_ALIGN 0
996 #ifndef TARGET_PROFILE_KERNEL
997 #define TARGET_PROFILE_KERNEL 0
1000 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1001 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1003 /* Initialize the GCC target structure. */
1004 #undef TARGET_ATTRIBUTE_TABLE
1005 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1006 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1007 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1009 #undef TARGET_ASM_ALIGNED_DI_OP
1010 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1012 /* Default unaligned ops are only provided for ELF. Find the ops needed
1013 for non-ELF systems. */
1014 #ifndef OBJECT_FORMAT_ELF
1016 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1018 #undef TARGET_ASM_UNALIGNED_HI_OP
1019 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1020 #undef TARGET_ASM_UNALIGNED_SI_OP
1021 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1022 #undef TARGET_ASM_UNALIGNED_DI_OP
1023 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1026 #undef TARGET_ASM_UNALIGNED_HI_OP
1027 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1028 #undef TARGET_ASM_UNALIGNED_SI_OP
1029 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1030 #undef TARGET_ASM_UNALIGNED_DI_OP
1031 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1032 #undef TARGET_ASM_ALIGNED_DI_OP
1033 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1037 /* This hook deals with fixups for relocatable code and DI-mode objects
1039 #undef TARGET_ASM_INTEGER
1040 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1042 #ifdef HAVE_GAS_HIDDEN
1043 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1044 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1047 #undef TARGET_HAVE_TLS
1048 #define TARGET_HAVE_TLS HAVE_AS_TLS
1050 #undef TARGET_CANNOT_FORCE_CONST_MEM
1051 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1053 #undef TARGET_ASM_FUNCTION_PROLOGUE
1054 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1055 #undef TARGET_ASM_FUNCTION_EPILOGUE
1056 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1058 #undef TARGET_SCHED_VARIABLE_ISSUE
1059 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1061 #undef TARGET_SCHED_ISSUE_RATE
1062 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1063 #undef TARGET_SCHED_ADJUST_COST
1064 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1065 #undef TARGET_SCHED_ADJUST_PRIORITY
1066 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1067 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1068 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1069 #undef TARGET_SCHED_INIT
1070 #define TARGET_SCHED_INIT rs6000_sched_init
1071 #undef TARGET_SCHED_FINISH
1072 #define TARGET_SCHED_FINISH rs6000_sched_finish
1073 #undef TARGET_SCHED_REORDER
1074 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1075 #undef TARGET_SCHED_REORDER2
1076 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1078 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1079 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1081 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1082 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1084 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1085 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1086 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1087 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1088 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1089 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1090 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1091 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1093 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1094 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1096 #undef TARGET_INIT_BUILTINS
1097 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1099 #undef TARGET_EXPAND_BUILTIN
1100 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1102 #undef TARGET_MANGLE_TYPE
1103 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1105 #undef TARGET_INIT_LIBFUNCS
1106 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1109 #undef TARGET_BINDS_LOCAL_P
1110 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1113 #undef TARGET_MS_BITFIELD_LAYOUT_P
1114 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1116 #undef TARGET_ASM_OUTPUT_MI_THUNK
1117 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1119 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1120 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1122 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1123 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1125 #undef TARGET_INVALID_WITHIN_DOLOOP
1126 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1128 #undef TARGET_RTX_COSTS
1129 #define TARGET_RTX_COSTS rs6000_rtx_costs
1130 #undef TARGET_ADDRESS_COST
1131 #define TARGET_ADDRESS_COST hook_int_rtx_0
1133 #undef TARGET_VECTOR_OPAQUE_P
1134 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1136 #undef TARGET_DWARF_REGISTER_SPAN
1137 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1139 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1140 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1142 /* On rs6000, function arguments are promoted, as are function return
1144 #undef TARGET_PROMOTE_FUNCTION_ARGS
1145 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1146 #undef TARGET_PROMOTE_FUNCTION_RETURN
1147 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1149 #undef TARGET_RETURN_IN_MEMORY
1150 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1152 #undef TARGET_SETUP_INCOMING_VARARGS
1153 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1155 /* Always strict argument naming on rs6000. */
1156 #undef TARGET_STRICT_ARGUMENT_NAMING
1157 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1158 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1159 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1160 #undef TARGET_SPLIT_COMPLEX_ARG
1161 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1162 #undef TARGET_MUST_PASS_IN_STACK
1163 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1164 #undef TARGET_PASS_BY_REFERENCE
1165 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1166 #undef TARGET_ARG_PARTIAL_BYTES
1167 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1169 #undef TARGET_BUILD_BUILTIN_VA_LIST
1170 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1172 #undef TARGET_EXPAND_BUILTIN_VA_START
1173 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1175 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1176 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1178 #undef TARGET_EH_RETURN_FILTER_MODE
1179 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1181 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1182 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1184 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1185 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1187 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1188 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1190 #undef TARGET_HANDLE_OPTION
1191 #define TARGET_HANDLE_OPTION rs6000_handle_option
1193 #undef TARGET_DEFAULT_TARGET_FLAGS
1194 #define TARGET_DEFAULT_TARGET_FLAGS \
1197 #undef TARGET_STACK_PROTECT_FAIL
1198 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1200 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1201 The PowerPC architecture requires only weak consistency among
1202 processors--that is, memory accesses between processors need not be
1203 sequentially consistent and memory accesses among processors can occur
1204 in any order. The ability to order memory accesses weakly provides
1205 opportunities for more efficient use of the system bus. Unless a
1206 dependency exists, the 604e allows read operations to precede store
1208 #undef TARGET_RELAXED_ORDERING
1209 #define TARGET_RELAXED_ORDERING true
1212 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1213 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1216 /* Use a 32-bit anchor range. This leads to sequences like:
1218 addis tmp,anchor,high
1221 where tmp itself acts as an anchor, and can be shared between
1222 accesses to the same 64k page. */
1223 #undef TARGET_MIN_ANCHOR_OFFSET
1224 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1225 #undef TARGET_MAX_ANCHOR_OFFSET
1226 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1227 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1228 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1230 #undef TARGET_BUILTIN_RECIPROCAL
1231 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1233 #undef TARGET_EXPAND_TO_RTL_HOOK
1234 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1236 #undef TARGET_INSTANTIATE_DECLS
1237 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1239 struct gcc_target targetm
= TARGET_INITIALIZER
;
1242 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1245 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1247 /* The GPRs can hold any mode, but values bigger than one register
1248 cannot go past R31. */
1249 if (INT_REGNO_P (regno
))
1250 return INT_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1);
1252 /* The float registers can only hold floating modes and DImode.
1253 This excludes the 32-bit decimal float mode for now. */
1254 if (FP_REGNO_P (regno
))
1256 ((SCALAR_FLOAT_MODE_P (mode
)
1257 && (mode
!= TDmode
|| (regno
% 2) == 0)
1258 && FP_REGNO_P (regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1))
1259 || (GET_MODE_CLASS (mode
) == MODE_INT
1260 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1261 || (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1262 && PAIRED_VECTOR_MODE (mode
)));
1264 /* The CR register can only hold CC modes. */
1265 if (CR_REGNO_P (regno
))
1266 return GET_MODE_CLASS (mode
) == MODE_CC
;
1268 if (XER_REGNO_P (regno
))
1269 return mode
== PSImode
;
1271 /* AltiVec only in AldyVec registers. */
1272 if (ALTIVEC_REGNO_P (regno
))
1273 return ALTIVEC_VECTOR_MODE (mode
);
1275 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1276 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1279 /* We cannot put TImode anywhere except general register and it must be
1280 able to fit within the register set. */
1282 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1285 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1287 rs6000_init_hard_regno_mode_ok (void)
1291 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
1292 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1293 if (rs6000_hard_regno_mode_ok (r
, m
))
1294 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
1298 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1301 darwin_rs6000_override_options (void)
1303 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1305 rs6000_altivec_abi
= 1;
1306 TARGET_ALTIVEC_VRSAVE
= 1;
1307 if (DEFAULT_ABI
== ABI_DARWIN
)
1309 if (MACHO_DYNAMIC_NO_PIC_P
)
1312 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1315 else if (flag_pic
== 1)
1320 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
1322 target_flags
|= MASK_POWERPC64
;
1323 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1327 rs6000_default_long_calls
= 1;
1328 target_flags
|= MASK_SOFT_FLOAT
;
1331 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1333 if (!flag_mkernel
&& !flag_apple_kext
1335 && ! (target_flags_explicit
& MASK_ALTIVEC
))
1336 target_flags
|= MASK_ALTIVEC
;
1338 /* Unless the user (not the configurer) has explicitly overridden
1339 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1340 G4 unless targetting the kernel. */
1343 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
1344 && ! (target_flags_explicit
& MASK_ALTIVEC
)
1345 && ! rs6000_select
[1].string
)
1347 target_flags
|= MASK_ALTIVEC
;
1352 /* If not otherwise specified by a target, make 'long double' equivalent to
1355 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1356 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1359 /* Override command line options. Mostly we process the processor
1360 type and sometimes adjust other TARGET_ options. */
1363 rs6000_override_options (const char *default_cpu
)
1366 struct rs6000_cpu_select
*ptr
;
1369 /* Simplifications for entries below. */
1372 POWERPC_BASE_MASK
= MASK_POWERPC
| MASK_NEW_MNEMONICS
,
1373 POWERPC_7400_MASK
= POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_ALTIVEC
1376 /* This table occasionally claims that a processor does not support
1377 a particular feature even though it does, but the feature is slower
1378 than the alternative. Thus, it shouldn't be relied on as a
1379 complete description of the processor's support.
1381 Please keep this list in order, and don't forget to update the
1382 documentation in invoke.texi when adding a new processor or
1386 const char *const name
; /* Canonical processor name. */
1387 const enum processor_type processor
; /* Processor type enum value. */
1388 const int target_enable
; /* Target flags to enable. */
1389 } const processor_target_table
[]
1390 = {{"401", PROCESSOR_PPC403
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1391 {"403", PROCESSOR_PPC403
,
1392 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_STRICT_ALIGN
},
1393 {"405", PROCESSOR_PPC405
,
1394 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1395 {"405fp", PROCESSOR_PPC405
,
1396 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1397 {"440", PROCESSOR_PPC440
,
1398 POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
| MASK_MULHW
| MASK_DLMZB
},
1399 {"440fp", PROCESSOR_PPC440
,
1400 POWERPC_BASE_MASK
| MASK_MULHW
| MASK_DLMZB
},
1401 {"505", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
},
1402 {"601", PROCESSOR_PPC601
,
1403 MASK_POWER
| POWERPC_BASE_MASK
| MASK_MULTIPLE
| MASK_STRING
},
1404 {"602", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1405 {"603", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1406 {"603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1407 {"604", PROCESSOR_PPC604
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1408 {"604e", PROCESSOR_PPC604e
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1409 {"620", PROCESSOR_PPC620
,
1410 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1411 {"630", PROCESSOR_PPC630
,
1412 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1413 {"740", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1414 {"7400", PROCESSOR_PPC7400
, POWERPC_7400_MASK
},
1415 {"7450", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1416 {"750", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1417 {"801", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1418 {"821", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1419 {"823", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1420 {"8540", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1421 /* 8548 has a dummy entry for now. */
1422 {"8548", PROCESSOR_PPC8540
, POWERPC_BASE_MASK
| MASK_STRICT_ALIGN
},
1423 {"860", PROCESSOR_MPCCORE
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1424 {"970", PROCESSOR_POWER4
,
1425 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1426 {"cell", PROCESSOR_CELL
,
1427 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1428 {"common", PROCESSOR_COMMON
, MASK_NEW_MNEMONICS
},
1429 {"ec603e", PROCESSOR_PPC603
, POWERPC_BASE_MASK
| MASK_SOFT_FLOAT
},
1430 {"G3", PROCESSOR_PPC750
, POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
},
1431 {"G4", PROCESSOR_PPC7450
, POWERPC_7400_MASK
},
1432 {"G5", PROCESSOR_POWER4
,
1433 POWERPC_7400_MASK
| MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1434 {"power", PROCESSOR_POWER
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1435 {"power2", PROCESSOR_POWER
,
1436 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1437 {"power3", PROCESSOR_PPC630
,
1438 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1439 {"power4", PROCESSOR_POWER4
,
1440 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_MFCRF
| MASK_POWERPC64
},
1441 {"power5", PROCESSOR_POWER5
,
1442 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GFXOPT
1443 | MASK_MFCRF
| MASK_POPCNTB
},
1444 {"power5+", PROCESSOR_POWER5
,
1445 POWERPC_BASE_MASK
| MASK_POWERPC64
| MASK_PPC_GFXOPT
1446 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
},
1447 {"power6", PROCESSOR_POWER6
,
1448 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_MFCRF
| MASK_POPCNTB
1449 | MASK_FPRND
| MASK_CMPB
| MASK_DFP
},
1450 {"power6x", PROCESSOR_POWER6
,
1451 POWERPC_7400_MASK
| MASK_POWERPC64
| MASK_MFCRF
| MASK_POPCNTB
1452 | MASK_FPRND
| MASK_CMPB
| MASK_MFPGPR
| MASK_DFP
},
1453 {"powerpc", PROCESSOR_POWERPC
, POWERPC_BASE_MASK
},
1454 {"powerpc64", PROCESSOR_POWERPC64
,
1455 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
},
1456 {"rios", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1457 {"rios1", PROCESSOR_RIOS1
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1458 {"rios2", PROCESSOR_RIOS2
,
1459 MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
},
1460 {"rsc", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1461 {"rsc1", PROCESSOR_PPC601
, MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
},
1462 {"rs64", PROCESSOR_RS64A
,
1463 POWERPC_BASE_MASK
| MASK_PPC_GFXOPT
| MASK_POWERPC64
}
1466 const size_t ptt_size
= ARRAY_SIZE (processor_target_table
);
1468 /* Some OSs don't support saving the high part of 64-bit registers on
1469 context switch. Other OSs don't support saving Altivec registers.
1470 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1471 settings; if the user wants either, the user must explicitly specify
1472 them and we won't interfere with the user's specification. */
1475 POWER_MASKS
= MASK_POWER
| MASK_POWER2
| MASK_MULTIPLE
| MASK_STRING
,
1476 POWERPC_MASKS
= (POWERPC_BASE_MASK
| MASK_PPC_GPOPT
| MASK_STRICT_ALIGN
1477 | MASK_PPC_GFXOPT
| MASK_POWERPC64
| MASK_ALTIVEC
1478 | MASK_MFCRF
| MASK_POPCNTB
| MASK_FPRND
| MASK_MULHW
1479 | MASK_DLMZB
| MASK_CMPB
| MASK_MFPGPR
| MASK_DFP
)
1482 rs6000_init_hard_regno_mode_ok ();
1484 set_masks
= POWER_MASKS
| POWERPC_MASKS
| MASK_SOFT_FLOAT
;
1485 #ifdef OS_MISSING_POWERPC64
1486 if (OS_MISSING_POWERPC64
)
1487 set_masks
&= ~MASK_POWERPC64
;
1489 #ifdef OS_MISSING_ALTIVEC
1490 if (OS_MISSING_ALTIVEC
)
1491 set_masks
&= ~MASK_ALTIVEC
;
1494 /* Don't override by the processor default if given explicitly. */
1495 set_masks
&= ~target_flags_explicit
;
1497 /* Identify the processor type. */
1498 rs6000_select
[0].string
= default_cpu
;
1499 rs6000_cpu
= TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
;
1501 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
1503 ptr
= &rs6000_select
[i
];
1504 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
1506 for (j
= 0; j
< ptt_size
; j
++)
1507 if (! strcmp (ptr
->string
, processor_target_table
[j
].name
))
1509 if (ptr
->set_tune_p
)
1510 rs6000_cpu
= processor_target_table
[j
].processor
;
1512 if (ptr
->set_arch_p
)
1514 target_flags
&= ~set_masks
;
1515 target_flags
|= (processor_target_table
[j
].target_enable
1522 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1529 /* If we are optimizing big endian systems for space, use the load/store
1530 multiple and string instructions. */
1531 if (BYTES_BIG_ENDIAN
&& optimize_size
)
1532 target_flags
|= ~target_flags_explicit
& (MASK_MULTIPLE
| MASK_STRING
);
1534 /* Don't allow -mmultiple or -mstring on little endian systems
1535 unless the cpu is a 750, because the hardware doesn't support the
1536 instructions used in little endian mode, and causes an alignment
1537 trap. The 750 does not cause an alignment trap (except when the
1538 target is unaligned). */
1540 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
1542 if (TARGET_MULTIPLE
)
1544 target_flags
&= ~MASK_MULTIPLE
;
1545 if ((target_flags_explicit
& MASK_MULTIPLE
) != 0)
1546 warning (0, "-mmultiple is not supported on little endian systems");
1551 target_flags
&= ~MASK_STRING
;
1552 if ((target_flags_explicit
& MASK_STRING
) != 0)
1553 warning (0, "-mstring is not supported on little endian systems");
1557 /* Set debug flags */
1558 if (rs6000_debug_name
)
1560 if (! strcmp (rs6000_debug_name
, "all"))
1561 rs6000_debug_stack
= rs6000_debug_arg
= 1;
1562 else if (! strcmp (rs6000_debug_name
, "stack"))
1563 rs6000_debug_stack
= 1;
1564 else if (! strcmp (rs6000_debug_name
, "arg"))
1565 rs6000_debug_arg
= 1;
1567 error ("unknown -mdebug-%s switch", rs6000_debug_name
);
1570 if (rs6000_traceback_name
)
1572 if (! strncmp (rs6000_traceback_name
, "full", 4))
1573 rs6000_traceback
= traceback_full
;
1574 else if (! strncmp (rs6000_traceback_name
, "part", 4))
1575 rs6000_traceback
= traceback_part
;
1576 else if (! strncmp (rs6000_traceback_name
, "no", 2))
1577 rs6000_traceback
= traceback_none
;
1579 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1580 rs6000_traceback_name
);
1583 if (!rs6000_explicit_options
.long_double
)
1584 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
1586 #ifndef POWERPC_LINUX
1587 if (!rs6000_explicit_options
.ieee
)
1588 rs6000_ieeequad
= 1;
1591 /* Enable Altivec ABI for AIX -maltivec. */
1592 if (TARGET_XCOFF
&& TARGET_ALTIVEC
)
1593 rs6000_altivec_abi
= 1;
1595 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
1596 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
1597 be explicitly overridden in either case. */
1600 if (!rs6000_explicit_options
.altivec_abi
1601 && (TARGET_64BIT
|| TARGET_ALTIVEC
))
1602 rs6000_altivec_abi
= 1;
1604 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
1605 if (!rs6000_explicit_options
.vrsave
)
1606 TARGET_ALTIVEC_VRSAVE
= rs6000_altivec_abi
;
1609 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1610 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
1612 rs6000_darwin64_abi
= 1;
1614 darwin_one_byte_bool
= 1;
1616 /* Default to natural alignment, for better performance. */
1617 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
1620 /* Place FP constants in the constant pool instead of TOC
1621 if section anchors enabled. */
1622 if (flag_section_anchors
)
1623 TARGET_NO_FP_IN_TOC
= 1;
1625 /* Handle -mtls-size option. */
1626 rs6000_parse_tls_size_option ();
1628 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1629 SUBTARGET_OVERRIDE_OPTIONS
;
1631 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1632 SUBSUBTARGET_OVERRIDE_OPTIONS
;
1634 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1635 SUB3TARGET_OVERRIDE_OPTIONS
;
1640 /* The e500 does not have string instructions, and we set
1641 MASK_STRING above when optimizing for size. */
1642 if ((target_flags
& MASK_STRING
) != 0)
1643 target_flags
= target_flags
& ~MASK_STRING
;
1645 else if (rs6000_select
[1].string
!= NULL
)
1647 /* For the powerpc-eabispe configuration, we set all these by
1648 default, so let's unset them if we manually set another
1649 CPU that is not the E500. */
1650 if (!rs6000_explicit_options
.spe_abi
)
1652 if (!rs6000_explicit_options
.spe
)
1654 if (!rs6000_explicit_options
.float_gprs
)
1655 rs6000_float_gprs
= 0;
1656 if (!rs6000_explicit_options
.isel
)
1660 /* Detect invalid option combinations with E500. */
1663 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
1664 && rs6000_cpu
!= PROCESSOR_POWER5
1665 && rs6000_cpu
!= PROCESSOR_POWER6
1666 && rs6000_cpu
!= PROCESSOR_CELL
);
1667 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
1668 || rs6000_cpu
== PROCESSOR_POWER5
);
1669 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
1670 || rs6000_cpu
== PROCESSOR_POWER5
1671 || rs6000_cpu
== PROCESSOR_POWER6
);
1673 rs6000_sched_restricted_insns_priority
1674 = (rs6000_sched_groups
? 1 : 0);
1676 /* Handle -msched-costly-dep option. */
1677 rs6000_sched_costly_dep
1678 = (rs6000_sched_groups
? store_to_load_dep_costly
: no_dep_costly
);
1680 if (rs6000_sched_costly_dep_str
)
1682 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
1683 rs6000_sched_costly_dep
= no_dep_costly
;
1684 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
1685 rs6000_sched_costly_dep
= all_deps_costly
;
1686 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
1687 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
1688 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
1689 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
1691 rs6000_sched_costly_dep
= atoi (rs6000_sched_costly_dep_str
);
1694 /* Handle -minsert-sched-nops option. */
1695 rs6000_sched_insert_nops
1696 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
1698 if (rs6000_sched_insert_nops_str
)
1700 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
1701 rs6000_sched_insert_nops
= sched_finish_none
;
1702 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
1703 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
1704 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
1705 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
1707 rs6000_sched_insert_nops
= atoi (rs6000_sched_insert_nops_str
);
1710 #ifdef TARGET_REGNAMES
1711 /* If the user desires alternate register names, copy in the
1712 alternate names now. */
1713 if (TARGET_REGNAMES
)
1714 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
1717 /* Set aix_struct_return last, after the ABI is determined.
1718 If -maix-struct-return or -msvr4-struct-return was explicitly
1719 used, don't override with the ABI default. */
1720 if (!rs6000_explicit_options
.aix_struct_ret
)
1721 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
1723 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
1724 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
1727 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
1729 /* We can only guarantee the availability of DI pseudo-ops when
1730 assembling for 64-bit targets. */
1733 targetm
.asm_out
.aligned_op
.di
= NULL
;
1734 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1737 /* Set branch target alignment, if not optimizing for size. */
1740 /* Cell wants to be aligned 8byte for dual issue. */
1741 if (rs6000_cpu
== PROCESSOR_CELL
)
1743 if (align_functions
<= 0)
1744 align_functions
= 8;
1745 if (align_jumps
<= 0)
1747 if (align_loops
<= 0)
1750 if (rs6000_align_branch_targets
)
1752 if (align_functions
<= 0)
1753 align_functions
= 16;
1754 if (align_jumps
<= 0)
1756 if (align_loops
<= 0)
1759 if (align_jumps_max_skip
<= 0)
1760 align_jumps_max_skip
= 15;
1761 if (align_loops_max_skip
<= 0)
1762 align_loops_max_skip
= 15;
1765 /* Arrange to save and restore machine status around nested functions. */
1766 init_machine_status
= rs6000_init_machine_status
;
1768 /* We should always be splitting complex arguments, but we can't break
1769 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1770 if (DEFAULT_ABI
!= ABI_AIX
)
1771 targetm
.calls
.split_complex_arg
= NULL
;
1773 /* Initialize rs6000_cost with the appropriate target costs. */
1775 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
1779 case PROCESSOR_RIOS1
:
1780 rs6000_cost
= &rios1_cost
;
1783 case PROCESSOR_RIOS2
:
1784 rs6000_cost
= &rios2_cost
;
1787 case PROCESSOR_RS64A
:
1788 rs6000_cost
= &rs64a_cost
;
1791 case PROCESSOR_MPCCORE
:
1792 rs6000_cost
= &mpccore_cost
;
1795 case PROCESSOR_PPC403
:
1796 rs6000_cost
= &ppc403_cost
;
1799 case PROCESSOR_PPC405
:
1800 rs6000_cost
= &ppc405_cost
;
1803 case PROCESSOR_PPC440
:
1804 rs6000_cost
= &ppc440_cost
;
1807 case PROCESSOR_PPC601
:
1808 rs6000_cost
= &ppc601_cost
;
1811 case PROCESSOR_PPC603
:
1812 rs6000_cost
= &ppc603_cost
;
1815 case PROCESSOR_PPC604
:
1816 rs6000_cost
= &ppc604_cost
;
1819 case PROCESSOR_PPC604e
:
1820 rs6000_cost
= &ppc604e_cost
;
1823 case PROCESSOR_PPC620
:
1824 rs6000_cost
= &ppc620_cost
;
1827 case PROCESSOR_PPC630
:
1828 rs6000_cost
= &ppc630_cost
;
1831 case PROCESSOR_CELL
:
1832 rs6000_cost
= &ppccell_cost
;
1835 case PROCESSOR_PPC750
:
1836 case PROCESSOR_PPC7400
:
1837 rs6000_cost
= &ppc750_cost
;
1840 case PROCESSOR_PPC7450
:
1841 rs6000_cost
= &ppc7450_cost
;
1844 case PROCESSOR_PPC8540
:
1845 rs6000_cost
= &ppc8540_cost
;
1848 case PROCESSOR_POWER4
:
1849 case PROCESSOR_POWER5
:
1850 rs6000_cost
= &power4_cost
;
1853 case PROCESSOR_POWER6
:
1854 rs6000_cost
= &power6_cost
;
1861 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES
))
1862 set_param_value ("simultaneous-prefetches",
1863 rs6000_cost
->simultaneous_prefetches
);
1864 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE
))
1865 set_param_value ("l1-cache-size", rs6000_cost
->l1_cache_size
);
1866 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE
))
1867 set_param_value ("l1-cache-line-size", rs6000_cost
->cache_line_size
);
1868 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE
))
1869 set_param_value ("l2-cache-size", rs6000_cost
->l2_cache_size
);
1871 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
1872 can be optimized to ap = __builtin_next_arg (0). */
1873 if (DEFAULT_ABI
!= ABI_V4
)
1874 targetm
.expand_builtin_va_start
= NULL
;
1877 /* Implement targetm.vectorize.builtin_mask_for_load. */
1879 rs6000_builtin_mask_for_load (void)
1882 return altivec_builtin_mask_for_load
;
1887 /* Implement targetm.vectorize.builtin_conversion. */
1889 rs6000_builtin_conversion (enum tree_code code
, tree type
)
1891 if (!TARGET_ALTIVEC
)
1897 switch (TYPE_MODE (type
))
1900 return TYPE_UNSIGNED (type
) ?
1901 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFUX
] :
1902 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VCFSX
];
1911 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1913 rs6000_builtin_mul_widen_even (tree type
)
1915 if (!TARGET_ALTIVEC
)
1918 switch (TYPE_MODE (type
))
1921 return TYPE_UNSIGNED (type
) ?
1922 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUH
] :
1923 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESH
];
1926 return TYPE_UNSIGNED (type
) ?
1927 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULEUB
] :
1928 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULESB
];
1934 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1936 rs6000_builtin_mul_widen_odd (tree type
)
1938 if (!TARGET_ALTIVEC
)
1941 switch (TYPE_MODE (type
))
1944 return TYPE_UNSIGNED (type
) ?
1945 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUH
] :
1946 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSH
];
1949 return TYPE_UNSIGNED (type
) ?
1950 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOUB
] :
1951 rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMULOSB
];
1958 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1959 after applying N number of iterations. This routine does not determine
1960 how may iterations are required to reach desired alignment. */
1963 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
1970 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
1973 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
1983 /* Assuming that all other types are naturally aligned. CHECKME! */
1988 /* Handle generic options of the form -mfoo=yes/no.
1989 NAME is the option name.
1990 VALUE is the option value.
1991 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1992 whether the option value is 'yes' or 'no' respectively. */
1994 rs6000_parse_yes_no_option (const char *name
, const char *value
, int *flag
)
1998 else if (!strcmp (value
, "yes"))
2000 else if (!strcmp (value
, "no"))
2003 error ("unknown -m%s= option specified: '%s'", name
, value
);
2006 /* Validate and record the size specified with the -mtls-size option. */
2009 rs6000_parse_tls_size_option (void)
2011 if (rs6000_tls_size_string
== 0)
2013 else if (strcmp (rs6000_tls_size_string
, "16") == 0)
2014 rs6000_tls_size
= 16;
2015 else if (strcmp (rs6000_tls_size_string
, "32") == 0)
2016 rs6000_tls_size
= 32;
2017 else if (strcmp (rs6000_tls_size_string
, "64") == 0)
2018 rs6000_tls_size
= 64;
2020 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string
);
2024 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
2026 if (DEFAULT_ABI
== ABI_DARWIN
)
2027 /* The Darwin libraries never set errno, so we might as well
2028 avoid calling them when that's the only reason we would. */
2029 flag_errno_math
= 0;
2031 /* Double growth factor to counter reduced min jump length. */
2032 set_param_value ("max-grow-copy-bb-insns", 16);
2034 /* Enable section anchors by default.
2035 Skip section anchors for Objective C and Objective C++
2036 until front-ends fixed. */
2037 if (!TARGET_MACHO
&& lang_hooks
.name
[4] != 'O')
2038 flag_section_anchors
= 1;
2041 /* Implement TARGET_HANDLE_OPTION. */
2044 rs6000_handle_option (size_t code
, const char *arg
, int value
)
2049 target_flags
&= ~(MASK_POWER
| MASK_POWER2
2050 | MASK_MULTIPLE
| MASK_STRING
);
2051 target_flags_explicit
|= (MASK_POWER
| MASK_POWER2
2052 | MASK_MULTIPLE
| MASK_STRING
);
2054 case OPT_mno_powerpc
:
2055 target_flags
&= ~(MASK_POWERPC
| MASK_PPC_GPOPT
2056 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2057 target_flags_explicit
|= (MASK_POWERPC
| MASK_PPC_GPOPT
2058 | MASK_PPC_GFXOPT
| MASK_POWERPC64
);
2061 target_flags
&= ~MASK_MINIMAL_TOC
;
2062 TARGET_NO_FP_IN_TOC
= 0;
2063 TARGET_NO_SUM_IN_TOC
= 0;
2064 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2065 #ifdef TARGET_USES_SYSV4_OPT
2066 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2067 just the same as -mminimal-toc. */
2068 target_flags
|= MASK_MINIMAL_TOC
;
2069 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2073 #ifdef TARGET_USES_SYSV4_OPT
2075 /* Make -mtoc behave like -mminimal-toc. */
2076 target_flags
|= MASK_MINIMAL_TOC
;
2077 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2081 #ifdef TARGET_USES_AIX64_OPT
2086 target_flags
|= MASK_POWERPC64
| MASK_POWERPC
;
2087 target_flags
|= ~target_flags_explicit
& MASK_PPC_GFXOPT
;
2088 target_flags_explicit
|= MASK_POWERPC64
| MASK_POWERPC
;
2091 #ifdef TARGET_USES_AIX64_OPT
2096 target_flags
&= ~MASK_POWERPC64
;
2097 target_flags_explicit
|= MASK_POWERPC64
;
2100 case OPT_minsert_sched_nops_
:
2101 rs6000_sched_insert_nops_str
= arg
;
2104 case OPT_mminimal_toc
:
2107 TARGET_NO_FP_IN_TOC
= 0;
2108 TARGET_NO_SUM_IN_TOC
= 0;
2115 target_flags
|= (MASK_MULTIPLE
| MASK_STRING
);
2116 target_flags_explicit
|= (MASK_MULTIPLE
| MASK_STRING
);
2123 target_flags
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2124 target_flags_explicit
|= (MASK_POWER
| MASK_MULTIPLE
| MASK_STRING
);
2128 case OPT_mpowerpc_gpopt
:
2129 case OPT_mpowerpc_gfxopt
:
2132 target_flags
|= MASK_POWERPC
;
2133 target_flags_explicit
|= MASK_POWERPC
;
2137 case OPT_maix_struct_return
:
2138 case OPT_msvr4_struct_return
:
2139 rs6000_explicit_options
.aix_struct_ret
= true;
2143 rs6000_explicit_options
.vrsave
= true;
2144 rs6000_parse_yes_no_option ("vrsave", arg
, &(TARGET_ALTIVEC_VRSAVE
));
2148 rs6000_explicit_options
.isel
= true;
2149 rs6000_parse_yes_no_option ("isel", arg
, &(rs6000_isel
));
2153 rs6000_explicit_options
.spe
= true;
2154 rs6000_parse_yes_no_option ("spe", arg
, &(rs6000_spe
));
2158 rs6000_debug_name
= arg
;
2161 #ifdef TARGET_USES_SYSV4_OPT
2163 rs6000_abi_name
= arg
;
2167 rs6000_sdata_name
= arg
;
2170 case OPT_mtls_size_
:
2171 rs6000_tls_size_string
= arg
;
2174 case OPT_mrelocatable
:
2177 target_flags
|= MASK_MINIMAL_TOC
;
2178 target_flags_explicit
|= MASK_MINIMAL_TOC
;
2179 TARGET_NO_FP_IN_TOC
= 1;
2183 case OPT_mrelocatable_lib
:
2186 target_flags
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2187 target_flags_explicit
|= MASK_RELOCATABLE
| MASK_MINIMAL_TOC
;
2188 TARGET_NO_FP_IN_TOC
= 1;
2192 target_flags
&= ~MASK_RELOCATABLE
;
2193 target_flags_explicit
|= MASK_RELOCATABLE
;
2199 if (!strcmp (arg
, "altivec"))
2201 rs6000_explicit_options
.altivec_abi
= true;
2202 rs6000_altivec_abi
= 1;
2204 /* Enabling the AltiVec ABI turns off the SPE ABI. */
2207 else if (! strcmp (arg
, "no-altivec"))
2209 rs6000_explicit_options
.altivec_abi
= true;
2210 rs6000_altivec_abi
= 0;
2212 else if (! strcmp (arg
, "spe"))
2214 rs6000_explicit_options
.spe_abi
= true;
2216 rs6000_altivec_abi
= 0;
2217 if (!TARGET_SPE_ABI
)
2218 error ("not configured for ABI: '%s'", arg
);
2220 else if (! strcmp (arg
, "no-spe"))
2222 rs6000_explicit_options
.spe_abi
= true;
2226 /* These are here for testing during development only, do not
2227 document in the manual please. */
2228 else if (! strcmp (arg
, "d64"))
2230 rs6000_darwin64_abi
= 1;
2231 warning (0, "Using darwin64 ABI");
2233 else if (! strcmp (arg
, "d32"))
2235 rs6000_darwin64_abi
= 0;
2236 warning (0, "Using old darwin ABI");
2239 else if (! strcmp (arg
, "ibmlongdouble"))
2241 rs6000_explicit_options
.ieee
= true;
2242 rs6000_ieeequad
= 0;
2243 warning (0, "Using IBM extended precision long double");
2245 else if (! strcmp (arg
, "ieeelongdouble"))
2247 rs6000_explicit_options
.ieee
= true;
2248 rs6000_ieeequad
= 1;
2249 warning (0, "Using IEEE extended precision long double");
2254 error ("unknown ABI specified: '%s'", arg
);
2260 rs6000_select
[1].string
= arg
;
2264 rs6000_select
[2].string
= arg
;
2267 case OPT_mtraceback_
:
2268 rs6000_traceback_name
= arg
;
2271 case OPT_mfloat_gprs_
:
2272 rs6000_explicit_options
.float_gprs
= true;
2273 if (! strcmp (arg
, "yes") || ! strcmp (arg
, "single"))
2274 rs6000_float_gprs
= 1;
2275 else if (! strcmp (arg
, "double"))
2276 rs6000_float_gprs
= 2;
2277 else if (! strcmp (arg
, "no"))
2278 rs6000_float_gprs
= 0;
2281 error ("invalid option for -mfloat-gprs: '%s'", arg
);
2286 case OPT_mlong_double_
:
2287 rs6000_explicit_options
.long_double
= true;
2288 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2289 if (value
!= 64 && value
!= 128)
2291 error ("Unknown switch -mlong-double-%s", arg
);
2292 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
2296 rs6000_long_double_type_size
= value
;
2299 case OPT_msched_costly_dep_
:
2300 rs6000_sched_costly_dep_str
= arg
;
2304 rs6000_explicit_options
.alignment
= true;
2305 if (! strcmp (arg
, "power"))
2307 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2308 some C library functions, so warn about it. The flag may be
2309 useful for performance studies from time to time though, so
2310 don't disable it entirely. */
2311 if (DEFAULT_ABI
== ABI_DARWIN
&& TARGET_64BIT
)
2312 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2313 " it is incompatible with the installed C and C++ libraries");
2314 rs6000_alignment_flags
= MASK_ALIGN_POWER
;
2316 else if (! strcmp (arg
, "natural"))
2317 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
2320 error ("unknown -malign-XXXXX option specified: '%s'", arg
);
2328 /* Do anything needed at the start of the asm file. */
2331 rs6000_file_start (void)
2335 const char *start
= buffer
;
2336 struct rs6000_cpu_select
*ptr
;
2337 const char *default_cpu
= TARGET_CPU_DEFAULT
;
2338 FILE *file
= asm_out_file
;
2340 default_file_start ();
2342 #ifdef TARGET_BI_ARCH
2343 if ((TARGET_DEFAULT
^ target_flags
) & MASK_64BIT
)
2347 if (flag_verbose_asm
)
2349 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
2350 rs6000_select
[0].string
= default_cpu
;
2352 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
2354 ptr
= &rs6000_select
[i
];
2355 if (ptr
->string
!= (char *)0 && ptr
->string
[0] != '\0')
2357 fprintf (file
, "%s %s%s", start
, ptr
->name
, ptr
->string
);
2362 if (PPC405_ERRATUM77
)
2364 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
2368 #ifdef USING_ELFOS_H
2369 switch (rs6000_sdata
)
2371 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
2372 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
2373 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
2374 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
2377 if (rs6000_sdata
&& g_switch_value
)
2379 fprintf (file
, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED
, start
,
2389 #ifdef HAVE_AS_GNU_ATTRIBUTE
2390 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
2392 fprintf (file
, "\t.gnu_attribute 4, %d\n",
2393 (TARGET_HARD_FLOAT
&& TARGET_FPRS
) ? 1 : 2);
2394 fprintf (file
, "\t.gnu_attribute 8, %d\n",
2395 (TARGET_ALTIVEC_ABI
? 2
2396 : TARGET_SPE_ABI
? 3
2401 if (DEFAULT_ABI
== ABI_AIX
|| (TARGET_ELF
&& flag_pic
== 2))
2403 switch_to_section (toc_section
);
2404 switch_to_section (text_section
);
2409 /* Return nonzero if this function is known to have a null epilogue. */
2412 direct_return (void)
2414 if (reload_completed
)
2416 rs6000_stack_t
*info
= rs6000_stack_info ();
2418 if (info
->first_gp_reg_save
== 32
2419 && info
->first_fp_reg_save
== 64
2420 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
2421 && ! info
->lr_save_p
2422 && ! info
->cr_save_p
2423 && info
->vrsave_mask
== 0
2431 /* Return the number of instructions it takes to form a constant in an
2432 integer register. */
2435 num_insns_constant_wide (HOST_WIDE_INT value
)
2437 /* signed constant loadable with {cal|addi} */
2438 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
2441 /* constant loadable with {cau|addis} */
2442 else if ((value
& 0xffff) == 0
2443 && (value
>> 31 == -1 || value
>> 31 == 0))
2446 #if HOST_BITS_PER_WIDE_INT == 64
2447 else if (TARGET_POWERPC64
)
2449 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2450 HOST_WIDE_INT high
= value
>> 31;
2452 if (high
== 0 || high
== -1)
2458 return num_insns_constant_wide (high
) + 1;
2460 return (num_insns_constant_wide (high
)
2461 + num_insns_constant_wide (low
) + 1);
2470 num_insns_constant (rtx op
, enum machine_mode mode
)
2472 HOST_WIDE_INT low
, high
;
2474 switch (GET_CODE (op
))
2477 #if HOST_BITS_PER_WIDE_INT == 64
2478 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
2479 && mask64_operand (op
, mode
))
2483 return num_insns_constant_wide (INTVAL (op
));
2486 if (mode
== SFmode
|| mode
== SDmode
)
2491 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2492 if (DECIMAL_FLOAT_MODE_P (mode
))
2493 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
2495 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2496 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
2499 if (mode
== VOIDmode
|| mode
== DImode
)
2501 high
= CONST_DOUBLE_HIGH (op
);
2502 low
= CONST_DOUBLE_LOW (op
);
2509 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
2510 if (DECIMAL_FLOAT_MODE_P (mode
))
2511 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
2513 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
2514 high
= l
[WORDS_BIG_ENDIAN
== 0];
2515 low
= l
[WORDS_BIG_ENDIAN
!= 0];
2519 return (num_insns_constant_wide (low
)
2520 + num_insns_constant_wide (high
));
2523 if ((high
== 0 && low
>= 0)
2524 || (high
== -1 && low
< 0))
2525 return num_insns_constant_wide (low
);
2527 else if (mask64_operand (op
, mode
))
2531 return num_insns_constant_wide (high
) + 1;
2534 return (num_insns_constant_wide (high
)
2535 + num_insns_constant_wide (low
) + 1);
2543 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2544 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2545 corresponding element of the vector, but for V4SFmode and V2SFmode,
2546 the corresponding "float" is interpreted as an SImode integer. */
2548 static HOST_WIDE_INT
2549 const_vector_elt_as_int (rtx op
, unsigned int elt
)
2551 rtx tmp
= CONST_VECTOR_ELT (op
, elt
);
2552 if (GET_MODE (op
) == V4SFmode
2553 || GET_MODE (op
) == V2SFmode
)
2554 tmp
= gen_lowpart (SImode
, tmp
);
2555 return INTVAL (tmp
);
2558 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2559 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2560 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2561 all items are set to the same value and contain COPIES replicas of the
2562 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2563 operand and the others are set to the value of the operand's msb. */
2566 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
2568 enum machine_mode mode
= GET_MODE (op
);
2569 enum machine_mode inner
= GET_MODE_INNER (mode
);
2572 unsigned nunits
= GET_MODE_NUNITS (mode
);
2573 unsigned bitsize
= GET_MODE_BITSIZE (inner
);
2574 unsigned mask
= GET_MODE_MASK (inner
);
2576 HOST_WIDE_INT val
= const_vector_elt_as_int (op
, nunits
- 1);
2577 HOST_WIDE_INT splat_val
= val
;
2578 HOST_WIDE_INT msb_val
= val
> 0 ? 0 : -1;
2580 /* Construct the value to be splatted, if possible. If not, return 0. */
2581 for (i
= 2; i
<= copies
; i
*= 2)
2583 HOST_WIDE_INT small_val
;
2585 small_val
= splat_val
>> bitsize
;
2587 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
2589 splat_val
= small_val
;
2592 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2593 if (EASY_VECTOR_15 (splat_val
))
2596 /* Also check if we can splat, and then add the result to itself. Do so if
2597 the value is positive, of if the splat instruction is using OP's mode;
2598 for splat_val < 0, the splat and the add should use the same mode. */
2599 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
2600 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
2606 /* Check if VAL is present in every STEP-th element, and the
2607 other elements are filled with its most significant bit. */
2608 for (i
= 0; i
< nunits
- 1; ++i
)
2610 HOST_WIDE_INT desired_val
;
2611 if (((i
+ 1) & (step
- 1)) == 0)
2614 desired_val
= msb_val
;
2616 if (desired_val
!= const_vector_elt_as_int (op
, i
))
2624 /* Return true if OP is of the given MODE and can be synthesized
2625 with a vspltisb, vspltish or vspltisw. */
2628 easy_altivec_constant (rtx op
, enum machine_mode mode
)
2630 unsigned step
, copies
;
2632 if (mode
== VOIDmode
)
2633 mode
= GET_MODE (op
);
2634 else if (mode
!= GET_MODE (op
))
2637 /* Start with a vspltisw. */
2638 step
= GET_MODE_NUNITS (mode
) / 4;
2641 if (vspltis_constant (op
, step
, copies
))
2644 /* Then try with a vspltish. */
2650 if (vspltis_constant (op
, step
, copies
))
2653 /* And finally a vspltisb. */
2659 if (vspltis_constant (op
, step
, copies
))
2665 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2666 result is OP. Abort if it is not possible. */
2669 gen_easy_altivec_constant (rtx op
)
2671 enum machine_mode mode
= GET_MODE (op
);
2672 int nunits
= GET_MODE_NUNITS (mode
);
2673 rtx last
= CONST_VECTOR_ELT (op
, nunits
- 1);
2674 unsigned step
= nunits
/ 4;
2675 unsigned copies
= 1;
2677 /* Start with a vspltisw. */
2678 if (vspltis_constant (op
, step
, copies
))
2679 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, last
));
2681 /* Then try with a vspltish. */
2687 if (vspltis_constant (op
, step
, copies
))
2688 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, last
));
2690 /* And finally a vspltisb. */
2696 if (vspltis_constant (op
, step
, copies
))
2697 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, last
));
2703 output_vec_const_move (rtx
*operands
)
2706 enum machine_mode mode
;
2711 mode
= GET_MODE (dest
);
2716 if (zero_constant (vec
, mode
))
2717 return "vxor %0,%0,%0";
2719 splat_vec
= gen_easy_altivec_constant (vec
);
2720 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
2721 operands
[1] = XEXP (splat_vec
, 0);
2722 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
2725 switch (GET_MODE (splat_vec
))
2728 return "vspltisw %0,%1";
2731 return "vspltish %0,%1";
2734 return "vspltisb %0,%1";
2741 gcc_assert (TARGET_SPE
);
2743 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2744 pattern of V1DI, V4HI, and V2SF.
2746 FIXME: We should probably return # and add post reload
2747 splitters for these, but this way is so easy ;-). */
2748 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
2749 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
2750 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
2751 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
2753 return "li %0,%1\n\tevmergelo %0,%0,%0";
2755 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2758 /* Initialize TARGET of vector PAIRED to VALS. */
2761 paired_expand_vector_init (rtx target
, rtx vals
)
2763 enum machine_mode mode
= GET_MODE (target
);
2764 int n_elts
= GET_MODE_NUNITS (mode
);
2766 rtx x
, new, tmp
, constant_op
, op1
, op2
;
2769 for (i
= 0; i
< n_elts
; ++i
)
2771 x
= XVECEXP (vals
, 0, i
);
2772 if (!CONSTANT_P (x
))
2777 /* Load from constant pool. */
2778 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
2784 /* The vector is initialized only with non-constants. */
2785 new = gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
2786 XVECEXP (vals
, 0, 1));
2788 emit_move_insn (target
, new);
2792 /* One field is non-constant and the other one is a constant. Load the
2793 constant from the constant pool and use ps_merge instruction to
2794 construct the whole vector. */
2795 op1
= XVECEXP (vals
, 0, 0);
2796 op2
= XVECEXP (vals
, 0, 1);
2798 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
2800 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
2801 emit_move_insn (tmp
, constant_op
);
2803 if (CONSTANT_P (op1
))
2804 new = gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
2806 new = gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
2808 emit_move_insn (target
, new);
2812 paired_expand_vector_move (rtx operands
[])
2814 rtx op0
= operands
[0], op1
= operands
[1];
2816 emit_move_insn (op0
, op1
);
2819 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
2820 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
2821 operands for the relation operation COND. This is a recursive
2825 paired_emit_vector_compare (enum rtx_code rcode
,
2826 rtx dest
, rtx op0
, rtx op1
,
2827 rtx cc_op0
, rtx cc_op1
)
2829 rtx tmp
= gen_reg_rtx (V2SFmode
);
2830 rtx tmp1
, max
, min
, equal_zero
;
2832 gcc_assert (TARGET_PAIRED_FLOAT
);
2833 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
2839 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2843 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
2844 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
2848 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
2851 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2854 tmp1
= gen_reg_rtx (V2SFmode
);
2855 max
= gen_reg_rtx (V2SFmode
);
2856 min
= gen_reg_rtx (V2SFmode
);
2857 equal_zero
= gen_reg_rtx (V2SFmode
);
2859 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
2860 emit_insn (gen_selv2sf4
2861 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
2862 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
2863 emit_insn (gen_selv2sf4
2864 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
2865 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
2866 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
2869 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2872 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2875 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2878 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2881 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
2890 /* Emit vector conditional expression.
2891 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
2892 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
2895 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
2896 rtx cond
, rtx cc_op0
, rtx cc_op1
)
2898 enum rtx_code rcode
= GET_CODE (cond
);
2900 if (!TARGET_PAIRED_FLOAT
)
2903 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
2908 /* Initialize vector TARGET to VALS. */
2911 rs6000_expand_vector_init (rtx target
, rtx vals
)
2913 enum machine_mode mode
= GET_MODE (target
);
2914 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
2915 int n_elts
= GET_MODE_NUNITS (mode
);
2916 int n_var
= 0, one_var
= -1;
2917 bool all_same
= true, all_const_zero
= true;
2921 for (i
= 0; i
< n_elts
; ++i
)
2923 x
= XVECEXP (vals
, 0, i
);
2924 if (!CONSTANT_P (x
))
2925 ++n_var
, one_var
= i
;
2926 else if (x
!= CONST0_RTX (inner_mode
))
2927 all_const_zero
= false;
2929 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
2935 if (mode
!= V4SFmode
&& all_const_zero
)
2937 /* Zero register. */
2938 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2939 gen_rtx_XOR (mode
, target
, target
)));
2942 else if (mode
!= V4SFmode
&& easy_vector_constant (vals
, mode
))
2944 /* Splat immediate. */
2945 emit_insn (gen_rtx_SET (VOIDmode
, target
, vals
));
2949 ; /* Splat vector element. */
2952 /* Load from constant pool. */
2953 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
2958 /* Store value to stack temp. Load vector element. Splat. */
2961 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
2962 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
2963 XVECEXP (vals
, 0, 0));
2964 x
= gen_rtx_UNSPEC (VOIDmode
,
2965 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
2966 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
2968 gen_rtx_SET (VOIDmode
,
2971 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
2972 gen_rtx_PARALLEL (VOIDmode
,
2973 gen_rtvec (1, const0_rtx
)));
2974 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2975 gen_rtx_VEC_DUPLICATE (mode
, x
)));
2979 /* One field is non-constant. Load constant then overwrite
2983 rtx copy
= copy_rtx (vals
);
2985 /* Load constant part of vector, substitute neighboring value for
2987 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
2988 rs6000_expand_vector_init (target
, copy
);
2990 /* Insert variable. */
2991 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
2995 /* Construct the vector in memory one field at a time
2996 and load the whole vector. */
2997 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
2998 for (i
= 0; i
< n_elts
; i
++)
2999 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
3000 i
* GET_MODE_SIZE (inner_mode
)),
3001 XVECEXP (vals
, 0, i
));
3002 emit_move_insn (target
, mem
);
3005 /* Set field ELT of TARGET to VAL. */
3008 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
3010 enum machine_mode mode
= GET_MODE (target
);
3011 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3012 rtx reg
= gen_reg_rtx (mode
);
3014 int width
= GET_MODE_SIZE (inner_mode
);
3017 /* Load single variable value. */
3018 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
), 0);
3019 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
3020 x
= gen_rtx_UNSPEC (VOIDmode
,
3021 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
3022 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3024 gen_rtx_SET (VOIDmode
,
3028 /* Linear sequence. */
3029 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
3030 for (i
= 0; i
< 16; ++i
)
3031 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
3033 /* Set permute mask to insert element into target. */
3034 for (i
= 0; i
< width
; ++i
)
3035 XVECEXP (mask
, 0, elt
*width
+ i
)
3036 = GEN_INT (i
+ 0x10);
3037 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
3038 x
= gen_rtx_UNSPEC (mode
,
3039 gen_rtvec (3, target
, reg
,
3040 force_reg (V16QImode
, x
)),
3042 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
3045 /* Extract field ELT from VEC into TARGET. */
3048 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
3050 enum machine_mode mode
= GET_MODE (vec
);
3051 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
3054 /* Allocate mode-sized buffer. */
3055 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
3057 /* Add offset to field within buffer matching vector element. */
3058 mem
= adjust_address_nv (mem
, mode
, elt
* GET_MODE_SIZE (inner_mode
));
3060 /* Store single field into mode-sized buffer. */
3061 x
= gen_rtx_UNSPEC (VOIDmode
,
3062 gen_rtvec (1, const0_rtx
), UNSPEC_STVE
);
3063 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
3065 gen_rtx_SET (VOIDmode
,
3068 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
3071 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
3072 implement ANDing by the mask IN. */
3074 build_mask64_2_operands (rtx in
, rtx
*out
)
3076 #if HOST_BITS_PER_WIDE_INT >= 64
3077 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
3080 gcc_assert (GET_CODE (in
) == CONST_INT
);
3085 /* Assume c initially something like 0x00fff000000fffff. The idea
3086 is to rotate the word so that the middle ^^^^^^ group of zeros
3087 is at the MS end and can be cleared with an rldicl mask. We then
3088 rotate back and clear off the MS ^^ group of zeros with a
3090 c
= ~c
; /* c == 0xff000ffffff00000 */
3091 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
3092 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
3093 c
= ~c
; /* c == 0x00fff000000fffff */
3094 c
&= -lsb
; /* c == 0x00fff00000000000 */
3095 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
3096 c
= ~c
; /* c == 0xff000fffffffffff */
3097 c
&= -lsb
; /* c == 0xff00000000000000 */
3099 while ((lsb
>>= 1) != 0)
3100 shift
++; /* shift == 44 on exit from loop */
3101 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
3102 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
3103 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
3107 /* Assume c initially something like 0xff000f0000000000. The idea
3108 is to rotate the word so that the ^^^ middle group of zeros
3109 is at the LS end and can be cleared with an rldicr mask. We then
3110 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
3112 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
3113 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
3114 c
= ~c
; /* c == 0x00fff0ffffffffff */
3115 c
&= -lsb
; /* c == 0x00fff00000000000 */
3116 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
3117 c
= ~c
; /* c == 0xff000fffffffffff */
3118 c
&= -lsb
; /* c == 0xff00000000000000 */
3120 while ((lsb
>>= 1) != 0)
3121 shift
++; /* shift == 44 on exit from loop */
3122 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
3123 m1
>>= shift
; /* m1 == 0x0000000000000fff */
3124 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
3127 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
3128 masks will be all 1's. We are guaranteed more than one transition. */
3129 out
[0] = GEN_INT (64 - shift
);
3130 out
[1] = GEN_INT (m1
);
3131 out
[2] = GEN_INT (shift
);
3132 out
[3] = GEN_INT (m2
);
3140 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3143 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
3145 if (TARGET_E500_DOUBLE
)
3147 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
3148 subreg:TI and reg:TF. */
3149 if (GET_CODE (op
) == SUBREG
3150 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
)
3151 && REG_P (SUBREG_REG (op
))
3152 && (GET_MODE (SUBREG_REG (op
)) == DFmode
3153 || GET_MODE (SUBREG_REG (op
)) == TFmode
3154 || GET_MODE (SUBREG_REG (op
)) == DDmode
3155 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
3158 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
3160 if (GET_CODE (op
) == SUBREG
3161 && (mode
== DFmode
|| mode
== TFmode
3162 || mode
== DDmode
|| mode
== TDmode
)
3163 && REG_P (SUBREG_REG (op
))
3164 && (GET_MODE (SUBREG_REG (op
)) == DImode
3165 || GET_MODE (SUBREG_REG (op
)) == TImode
))
3170 && GET_CODE (op
) == SUBREG
3172 && REG_P (SUBREG_REG (op
))
3173 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
3179 /* AIX increases natural record alignment to doubleword if the first
3180 field is an FP double while the FP fields remain word aligned. */
3183 rs6000_special_round_type_align (tree type
, unsigned int computed
,
3184 unsigned int specified
)
3186 unsigned int align
= MAX (computed
, specified
);
3187 tree field
= TYPE_FIELDS (type
);
3189 /* Skip all non field decls */
3190 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3191 field
= TREE_CHAIN (field
);
3193 if (field
!= NULL
&& field
!= type
)
3195 type
= TREE_TYPE (field
);
3196 while (TREE_CODE (type
) == ARRAY_TYPE
)
3197 type
= TREE_TYPE (type
);
3199 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
3200 align
= MAX (align
, 64);
3206 /* Darwin increases record alignment to the natural alignment of
3210 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
3211 unsigned int specified
)
3213 unsigned int align
= MAX (computed
, specified
);
3215 if (TYPE_PACKED (type
))
3218 /* Find the first field, looking down into aggregates. */
3220 tree field
= TYPE_FIELDS (type
);
3221 /* Skip all non field decls */
3222 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
3223 field
= TREE_CHAIN (field
);
3226 type
= TREE_TYPE (field
);
3227 while (TREE_CODE (type
) == ARRAY_TYPE
)
3228 type
= TREE_TYPE (type
);
3229 } while (AGGREGATE_TYPE_P (type
));
3231 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
3232 align
= MAX (align
, TYPE_ALIGN (type
));
3237 /* Return 1 for an operand in small memory on V.4/eabi. */
3240 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
3241 enum machine_mode mode ATTRIBUTE_UNUSED
)
3246 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
3249 if (DEFAULT_ABI
!= ABI_V4
)
3252 /* Vector and float memory instructions have a limited offset on the
3253 SPE, so using a vector or float variable directly as an operand is
3256 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
3259 if (GET_CODE (op
) == SYMBOL_REF
)
3262 else if (GET_CODE (op
) != CONST
3263 || GET_CODE (XEXP (op
, 0)) != PLUS
3264 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
3265 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
3270 rtx sum
= XEXP (op
, 0);
3271 HOST_WIDE_INT summand
;
3273 /* We have to be careful here, because it is the referenced address
3274 that must be 32k from _SDA_BASE_, not just the symbol. */
3275 summand
= INTVAL (XEXP (sum
, 1));
3276 if (summand
< 0 || (unsigned HOST_WIDE_INT
) summand
> g_switch_value
)
3279 sym_ref
= XEXP (sum
, 0);
3282 return SYMBOL_REF_SMALL_P (sym_ref
);
3288 /* Return true if either operand is a general purpose register. */
3291 gpr_or_gpr_p (rtx op0
, rtx op1
)
3293 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
3294 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
3298 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3301 constant_pool_expr_1 (rtx op
, int *have_sym
, int *have_toc
)
3303 switch (GET_CODE (op
))
3306 if (RS6000_SYMBOL_REF_TLS_P (op
))
3308 else if (CONSTANT_POOL_ADDRESS_P (op
))
3310 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op
), Pmode
))
3318 else if (! strcmp (XSTR (op
, 0), toc_label_name
))
3327 return (constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
)
3328 && constant_pool_expr_1 (XEXP (op
, 1), have_sym
, have_toc
));
3330 return constant_pool_expr_1 (XEXP (op
, 0), have_sym
, have_toc
);
3339 constant_pool_expr_p (rtx op
)
3343 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_sym
;
3347 toc_relative_expr_p (rtx op
)
3351 return constant_pool_expr_1 (op
, &have_sym
, &have_toc
) && have_toc
;
3355 legitimate_constant_pool_address_p (rtx x
)
3358 && GET_CODE (x
) == PLUS
3359 && GET_CODE (XEXP (x
, 0)) == REG
3360 && (TARGET_MINIMAL_TOC
|| REGNO (XEXP (x
, 0)) == TOC_REGISTER
)
3361 && constant_pool_expr_p (XEXP (x
, 1)));
3365 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
3367 return (DEFAULT_ABI
== ABI_V4
3368 && !flag_pic
&& !TARGET_TOC
3369 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
3370 && small_data_operand (x
, mode
));
3373 /* SPE offset addressing is limited to 5-bits worth of double words. */
3374 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3377 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
, int strict
)
3379 unsigned HOST_WIDE_INT offset
, extra
;
3381 if (GET_CODE (x
) != PLUS
)
3383 if (GET_CODE (XEXP (x
, 0)) != REG
)
3385 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3387 if (legitimate_constant_pool_address_p (x
))
3389 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3392 offset
= INTVAL (XEXP (x
, 1));
3400 /* AltiVec vector modes. Only reg+reg addressing is valid and
3401 constant offset zero should not occur due to canonicalization. */
3408 /* Paired vector modes. Only reg+reg addressing is valid and
3409 constant offset zero should not occur due to canonicalization. */
3410 if (TARGET_PAIRED_FLOAT
)
3412 /* SPE vector modes. */
3413 return SPE_CONST_OFFSET_OK (offset
);
3417 if (TARGET_E500_DOUBLE
)
3418 return SPE_CONST_OFFSET_OK (offset
);
3421 /* On e500v2, we may have:
3423 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3425 Which gets addressed with evldd instructions. */
3426 if (TARGET_E500_DOUBLE
)
3427 return SPE_CONST_OFFSET_OK (offset
);
3429 if (mode
== DFmode
|| mode
== DDmode
|| !TARGET_POWERPC64
)
3431 else if (offset
& 3)
3437 if (TARGET_E500_DOUBLE
)
3438 return (SPE_CONST_OFFSET_OK (offset
)
3439 && SPE_CONST_OFFSET_OK (offset
+ 8));
3442 if (mode
== TFmode
|| mode
== TDmode
|| !TARGET_POWERPC64
)
3444 else if (offset
& 3)
3455 return (offset
< 0x10000) && (offset
+ extra
< 0x10000);
3459 legitimate_indexed_address_p (rtx x
, int strict
)
3463 if (GET_CODE (x
) != PLUS
)
3469 /* Recognize the rtl generated by reload which we know will later be
3470 replaced with proper base and index regs. */
3472 && reload_in_progress
3473 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
3477 return (REG_P (op0
) && REG_P (op1
)
3478 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
3479 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
3480 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
3481 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
3485 legitimate_indirect_address_p (rtx x
, int strict
)
3487 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
3491 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
3493 if (!TARGET_MACHO
|| !flag_pic
3494 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
3498 if (GET_CODE (x
) != LO_SUM
)
3500 if (GET_CODE (XEXP (x
, 0)) != REG
)
3502 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
3506 return CONSTANT_P (x
);
3510 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
3512 if (GET_CODE (x
) != LO_SUM
)
3514 if (GET_CODE (XEXP (x
, 0)) != REG
)
3516 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
3518 /* Restrict addressing for DI because of our SUBREG hackery. */
3519 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3520 || mode
== DDmode
|| mode
== TDmode
3525 if (TARGET_ELF
|| TARGET_MACHO
)
3527 if (DEFAULT_ABI
!= ABI_AIX
&& DEFAULT_ABI
!= ABI_DARWIN
&& flag_pic
)
3531 if (GET_MODE_NUNITS (mode
) != 1)
3533 if (GET_MODE_BITSIZE (mode
) > 64
3534 || (GET_MODE_BITSIZE (mode
) > 32 && !TARGET_POWERPC64
3535 && !(TARGET_HARD_FLOAT
&& TARGET_FPRS
3536 && (mode
== DFmode
|| mode
== DDmode
))))
3539 return CONSTANT_P (x
);
3546 /* Try machine-dependent ways of modifying an illegitimate address
3547 to be legitimate. If we find one, return the new, valid address.
3548 This is used from only one place: `memory_address' in explow.c.
3550 OLDX is the address as it was before break_out_memory_refs was
3551 called. In some cases it is useful to look at this to decide what
3554 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3556 It is always safe for this function to do nothing. It exists to
3557 recognize opportunities to optimize the output.
3559 On RS/6000, first check for the sum of a register with a constant
3560 integer that is out of range. If so, generate code to add the
3561 constant with the low-order 16 bits masked to the register and force
3562 this result into another register (this can be done with `cau').
3563 Then generate an address of REG+(CONST&0xffff), allowing for the
3564 possibility of bit 16 being a one.
3566 Then check for the sum of a register and something not constant, try to
3567 load the other things into a register and return the sum. */
3570 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3571 enum machine_mode mode
)
3573 if (GET_CODE (x
) == SYMBOL_REF
)
3575 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3577 return rs6000_legitimize_tls_address (x
, model
);
3580 if (GET_CODE (x
) == PLUS
3581 && GET_CODE (XEXP (x
, 0)) == REG
3582 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3583 && (unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000) >= 0x10000
3584 && !(SPE_VECTOR_MODE (mode
)
3585 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3586 || mode
== DImode
))))
3588 HOST_WIDE_INT high_int
, low_int
;
3590 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3591 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
3592 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3593 GEN_INT (high_int
)), 0);
3594 return gen_rtx_PLUS (Pmode
, sum
, GEN_INT (low_int
));
3596 else if (GET_CODE (x
) == PLUS
3597 && GET_CODE (XEXP (x
, 0)) == REG
3598 && GET_CODE (XEXP (x
, 1)) != CONST_INT
3599 && GET_MODE_NUNITS (mode
) == 1
3600 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3602 || (((mode
!= DImode
&& mode
!= DFmode
&& mode
!= DDmode
)
3603 || TARGET_E500_DOUBLE
)
3604 && mode
!= TFmode
&& mode
!= TDmode
))
3605 && (TARGET_POWERPC64
|| mode
!= DImode
)
3608 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3609 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
3611 else if (ALTIVEC_VECTOR_MODE (mode
))
3615 /* Make sure both operands are registers. */
3616 if (GET_CODE (x
) == PLUS
)
3617 return gen_rtx_PLUS (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
3618 force_reg (Pmode
, XEXP (x
, 1)));
3620 reg
= force_reg (Pmode
, x
);
3623 else if (SPE_VECTOR_MODE (mode
)
3624 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
3625 || mode
== DDmode
|| mode
== TDmode
3626 || mode
== DImode
)))
3630 /* We accept [reg + reg] and [reg + OFFSET]. */
3632 if (GET_CODE (x
) == PLUS
)
3634 rtx op1
= XEXP (x
, 0);
3635 rtx op2
= XEXP (x
, 1);
3637 op1
= force_reg (Pmode
, op1
);
3639 if (GET_CODE (op2
) != REG
3640 && (GET_CODE (op2
) != CONST_INT
3641 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))))
3642 op2
= force_reg (Pmode
, op2
);
3644 return gen_rtx_PLUS (Pmode
, op1
, op2
);
3647 return force_reg (Pmode
, x
);
3653 && GET_CODE (x
) != CONST_INT
3654 && GET_CODE (x
) != CONST_DOUBLE
3656 && GET_MODE_NUNITS (mode
) == 1
3657 && (GET_MODE_BITSIZE (mode
) <= 32
3658 || ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3659 && (mode
== DFmode
|| mode
== DDmode
))))
3661 rtx reg
= gen_reg_rtx (Pmode
);
3662 emit_insn (gen_elf_high (reg
, x
));
3663 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3665 else if (TARGET_MACHO
&& TARGET_32BIT
&& TARGET_NO_TOC
3668 && ! MACHO_DYNAMIC_NO_PIC_P
3670 && GET_CODE (x
) != CONST_INT
3671 && GET_CODE (x
) != CONST_DOUBLE
3673 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3674 || (mode
!= DFmode
&& mode
!= DDmode
))
3678 rtx reg
= gen_reg_rtx (Pmode
);
3679 emit_insn (gen_macho_high (reg
, x
));
3680 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
3683 && constant_pool_expr_p (x
)
3684 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
3686 return create_TOC_reference (x
);
3692 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3693 We need to emit DTP-relative relocations. */
3696 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3701 fputs ("\t.long\t", file
);
3704 fputs (DOUBLE_INT_ASM_OP
, file
);
3709 output_addr_const (file
, x
);
3710 fputs ("@dtprel+0x8000", file
);
3713 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3715 static GTY(()) rtx rs6000_tls_symbol
;
3717 rs6000_tls_get_addr (void)
3719 if (!rs6000_tls_symbol
)
3720 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3722 return rs6000_tls_symbol
;
3725 /* Construct the SYMBOL_REF for TLS GOT references. */
3727 static GTY(()) rtx rs6000_got_symbol
;
3729 rs6000_got_sym (void)
3731 if (!rs6000_got_symbol
)
3733 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3734 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
3735 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
3738 return rs6000_got_symbol
;
3741 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3742 this (thread-local) address. */
3745 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
3749 dest
= gen_reg_rtx (Pmode
);
3750 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
3756 tlsreg
= gen_rtx_REG (Pmode
, 13);
3757 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
3761 tlsreg
= gen_rtx_REG (Pmode
, 2);
3762 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
3766 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
3770 tmp
= gen_reg_rtx (Pmode
);
3773 tlsreg
= gen_rtx_REG (Pmode
, 13);
3774 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
3778 tlsreg
= gen_rtx_REG (Pmode
, 2);
3779 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
3783 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
3785 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
3790 rtx r3
, got
, tga
, tmp1
, tmp2
, eqv
;
3792 /* We currently use relocations like @got@tlsgd for tls, which
3793 means the linker will handle allocation of tls entries, placing
3794 them in the .got section. So use a pointer to the .got section,
3795 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3796 or to secondary GOT sections used by 32-bit -fPIC. */
3798 got
= gen_rtx_REG (Pmode
, 2);
3802 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
3805 rtx gsym
= rs6000_got_sym ();
3806 got
= gen_reg_rtx (Pmode
);
3808 rs6000_emit_move (got
, gsym
, Pmode
);
3814 tmp1
= gen_reg_rtx (Pmode
);
3815 tmp2
= gen_reg_rtx (Pmode
);
3816 tmp3
= gen_reg_rtx (Pmode
);
3817 mem
= gen_const_mem (Pmode
, tmp1
);
3819 first
= emit_insn (gen_load_toc_v4_PIC_1b (gsym
));
3820 emit_move_insn (tmp1
,
3821 gen_rtx_REG (Pmode
, LR_REGNO
));
3822 emit_move_insn (tmp2
, mem
);
3823 emit_insn (gen_addsi3 (tmp3
, tmp1
, tmp2
));
3824 last
= emit_move_insn (got
, tmp3
);
3825 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
3826 maybe_encapsulate_block (first
, last
, gsym
);
3831 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
3833 r3
= gen_rtx_REG (Pmode
, 3);
3835 insn
= gen_tls_gd_64 (r3
, got
, addr
);
3837 insn
= gen_tls_gd_32 (r3
, got
, addr
);
3840 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3841 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3842 insn
= emit_call_insn (insn
);
3843 CONST_OR_PURE_CALL_P (insn
) = 1;
3844 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3845 insn
= get_insns ();
3847 emit_libcall_block (insn
, dest
, r3
, addr
);
3849 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
3851 r3
= gen_rtx_REG (Pmode
, 3);
3853 insn
= gen_tls_ld_64 (r3
, got
);
3855 insn
= gen_tls_ld_32 (r3
, got
);
3858 tga
= gen_rtx_MEM (Pmode
, rs6000_tls_get_addr ());
3859 insn
= gen_call_value (r3
, tga
, const0_rtx
, const0_rtx
);
3860 insn
= emit_call_insn (insn
);
3861 CONST_OR_PURE_CALL_P (insn
) = 1;
3862 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r3
);
3863 insn
= get_insns ();
3865 tmp1
= gen_reg_rtx (Pmode
);
3866 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3868 emit_libcall_block (insn
, tmp1
, r3
, eqv
);
3869 if (rs6000_tls_size
== 16)
3872 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
3874 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
3876 else if (rs6000_tls_size
== 32)
3878 tmp2
= gen_reg_rtx (Pmode
);
3880 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
3882 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
3885 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
3887 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
3891 tmp2
= gen_reg_rtx (Pmode
);
3893 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
3895 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
3897 insn
= gen_rtx_SET (Pmode
, dest
,
3898 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
3904 /* IE, or 64-bit offset LE. */
3905 tmp2
= gen_reg_rtx (Pmode
);
3907 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
3909 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
3912 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
3914 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
3922 /* Return 1 if X contains a thread-local symbol. */
3925 rs6000_tls_referenced_p (rtx x
)
3927 if (! TARGET_HAVE_TLS
)
3930 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
3933 /* Return 1 if *X is a thread-local symbol. This is the same as
3934 rs6000_tls_symbol_ref except for the type of the unused argument. */
3937 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
3939 return RS6000_SYMBOL_REF_TLS_P (*x
);
3942 /* The convention appears to be to define this wherever it is used.
3943 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3944 is now used here. */
3945 #ifndef REG_MODE_OK_FOR_BASE_P
3946 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3949 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3950 replace the input X, or the original X if no replacement is called for.
3951 The output parameter *WIN is 1 if the calling macro should goto WIN,
3954 For RS/6000, we wish to handle large displacements off a base
3955 register by splitting the addend across an addiu/addis and the mem insn.
3956 This cuts number of extra insns needed from 3 to 1.
3958 On Darwin, we use this to generate code for floating point constants.
3959 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3960 The Darwin code is inside #if TARGET_MACHO because only then is
3961 machopic_function_base_name() defined. */
3963 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3964 int opnum
, int type
,
3965 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3967 /* We must recognize output that we have already generated ourselves. */
3968 if (GET_CODE (x
) == PLUS
3969 && GET_CODE (XEXP (x
, 0)) == PLUS
3970 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
3971 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3972 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3974 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3975 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3976 opnum
, (enum reload_type
)type
);
3982 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
3983 && GET_CODE (x
) == LO_SUM
3984 && GET_CODE (XEXP (x
, 0)) == PLUS
3985 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
3986 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
3987 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 0)) == CONST
3988 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
3989 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == MINUS
3990 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 0)) == SYMBOL_REF
3991 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == SYMBOL_REF
)
3993 /* Result of previous invocation of this function on Darwin
3994 floating point constant. */
3995 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3996 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3997 opnum
, (enum reload_type
)type
);
4003 /* Force ld/std non-word aligned offset into base register by wrapping
4005 if (GET_CODE (x
) == PLUS
4006 && GET_CODE (XEXP (x
, 0)) == REG
4007 && REGNO (XEXP (x
, 0)) < 32
4008 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
4009 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4010 && (INTVAL (XEXP (x
, 1)) & 3) != 0
4011 && !ALTIVEC_VECTOR_MODE (mode
)
4012 && GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
4013 && TARGET_POWERPC64
)
4015 x
= gen_rtx_PLUS (GET_MODE (x
), x
, GEN_INT (0));
4016 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4017 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4018 opnum
, (enum reload_type
) type
);
4023 if (GET_CODE (x
) == PLUS
4024 && GET_CODE (XEXP (x
, 0)) == REG
4025 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
4026 && REG_MODE_OK_FOR_BASE_P (XEXP (x
, 0), mode
)
4027 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4028 && !SPE_VECTOR_MODE (mode
)
4029 && !(TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
4030 || mode
== DDmode
|| mode
== TDmode
4032 && !ALTIVEC_VECTOR_MODE (mode
))
4034 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
4035 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
4037 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
4039 /* Check for 32-bit overflow. */
4040 if (high
+ low
!= val
)
4046 /* Reload the high part into a base reg; leave the low part
4047 in the mem directly. */
4049 x
= gen_rtx_PLUS (GET_MODE (x
),
4050 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
4054 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4055 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4056 opnum
, (enum reload_type
)type
);
4061 if (GET_CODE (x
) == SYMBOL_REF
4062 && !ALTIVEC_VECTOR_MODE (mode
)
4063 && !SPE_VECTOR_MODE (mode
)
4065 && DEFAULT_ABI
== ABI_DARWIN
4066 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
4068 && DEFAULT_ABI
== ABI_V4
4071 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
4072 The same goes for DImode without 64-bit gprs and DFmode and DDmode
4076 && (mode
!= DImode
|| TARGET_POWERPC64
)
4077 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
4078 || (TARGET_FPRS
&& TARGET_HARD_FLOAT
)))
4083 rtx offset
= gen_rtx_CONST (Pmode
,
4084 gen_rtx_MINUS (Pmode
, x
,
4085 machopic_function_base_sym ()));
4086 x
= gen_rtx_LO_SUM (GET_MODE (x
),
4087 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
4088 gen_rtx_HIGH (Pmode
, offset
)), offset
);
4092 x
= gen_rtx_LO_SUM (GET_MODE (x
),
4093 gen_rtx_HIGH (Pmode
, x
), x
);
4095 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4096 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4097 opnum
, (enum reload_type
)type
);
4102 /* Reload an offset address wrapped by an AND that represents the
4103 masking of the lower bits. Strip the outer AND and let reload
4104 convert the offset address into an indirect address. */
4106 && ALTIVEC_VECTOR_MODE (mode
)
4107 && GET_CODE (x
) == AND
4108 && GET_CODE (XEXP (x
, 0)) == PLUS
4109 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
4110 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4111 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4112 && INTVAL (XEXP (x
, 1)) == -16)
4120 && constant_pool_expr_p (x
)
4121 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), mode
))
4123 x
= create_TOC_reference (x
);
4131 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
4132 that is a valid memory address for an instruction.
4133 The MODE argument is the machine mode for the MEM expression
4134 that wants to use this address.
4136 On the RS/6000, there are four valid address: a SYMBOL_REF that
4137 refers to a constant pool entry of an address (or the sum of it
4138 plus a constant), a short (16-bit signed) constant plus a register,
4139 the sum of two registers, or a register indirect, possibly with an
4140 auto-increment. For DFmode, DDmode and DImode with a constant plus
4141 register, we must ensure that both words are addressable or PowerPC64
4142 with offset word aligned.
4144 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
4145 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
4146 because adjacent memory cells are accessed by adding word-sized offsets
4147 during assembly output. */
4149 rs6000_legitimate_address (enum machine_mode mode
, rtx x
, int reg_ok_strict
)
4151 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
4153 && ALTIVEC_VECTOR_MODE (mode
)
4154 && GET_CODE (x
) == AND
4155 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4156 && INTVAL (XEXP (x
, 1)) == -16)
4159 if (RS6000_SYMBOL_REF_TLS_P (x
))
4161 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
4163 if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
4164 && !ALTIVEC_VECTOR_MODE (mode
)
4165 && !SPE_VECTOR_MODE (mode
)
4168 /* Restrict addressing for DI because of our SUBREG hackery. */
4169 && !(TARGET_E500_DOUBLE
4170 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
4172 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
4174 if (legitimate_small_data_p (mode
, x
))
4176 if (legitimate_constant_pool_address_p (x
))
4178 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4180 && GET_CODE (x
) == PLUS
4181 && GET_CODE (XEXP (x
, 0)) == REG
4182 && (XEXP (x
, 0) == virtual_stack_vars_rtx
4183 || XEXP (x
, 0) == arg_pointer_rtx
)
4184 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4186 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
))
4191 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4193 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
4194 && (TARGET_POWERPC64
|| mode
!= DImode
)
4195 && legitimate_indexed_address_p (x
, reg_ok_strict
))
4197 if (GET_CODE (x
) == PRE_MODIFY
4201 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
)
4203 || ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_E500_DOUBLE
))
4204 && (TARGET_POWERPC64
|| mode
!= DImode
)
4205 && !ALTIVEC_VECTOR_MODE (mode
)
4206 && !SPE_VECTOR_MODE (mode
)
4207 /* Restrict addressing for DI because of our SUBREG hackery. */
4208 && !(TARGET_E500_DOUBLE
4209 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DImode
))
4211 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
4212 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1), reg_ok_strict
)
4213 || legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
))
4214 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4216 if (legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
4221 /* Go to LABEL if ADDR (a legitimate address expression)
4222 has an effect that depends on the machine mode it is used for.
4224 On the RS/6000 this is true of all integral offsets (since AltiVec
4225 modes don't allow them) or is a pre-increment or decrement.
4227 ??? Except that due to conceptual problems in offsettable_address_p
4228 we can't really report the problems of integral offsets. So leave
4229 this assuming that the adjustable offset must be valid for the
4230 sub-words of a TFmode operand, which is what we had before. */
4233 rs6000_mode_dependent_address (rtx addr
)
4235 switch (GET_CODE (addr
))
4238 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4240 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
4241 return val
+ 12 + 0x8000 >= 0x10000;
4251 return TARGET_UPDATE
;
4260 /* More elaborate version of recog's offsettable_memref_p predicate
4261 that works around the ??? note of rs6000_mode_dependent_address.
4262 In particular it accepts
4264 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4266 in 32-bit mode, that the recog predicate rejects. */
4269 rs6000_offsettable_memref_p (rtx op
)
4274 /* First mimic offsettable_memref_p. */
4275 if (offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)))
4278 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4279 the latter predicate knows nothing about the mode of the memory
4280 reference and, therefore, assumes that it is the largest supported
4281 mode (TFmode). As a consequence, legitimate offsettable memory
4282 references are rejected. rs6000_legitimate_offset_address_p contains
4283 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4284 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0), 1);
4287 /* Return number of consecutive hard regs needed starting at reg REGNO
4288 to hold something of mode MODE.
4289 This is ordinarily the length in words of a value of mode MODE
4290 but can be less for certain modes in special long registers.
4292 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4293 scalar instructions. The upper 32 bits are only available to the
4296 POWER and PowerPC GPRs hold 32 bits worth;
4297 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4300 rs6000_hard_regno_nregs (int regno
, enum machine_mode mode
)
4302 if (FP_REGNO_P (regno
))
4303 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4305 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
4306 return (GET_MODE_SIZE (mode
) + UNITS_PER_SPE_WORD
- 1) / UNITS_PER_SPE_WORD
;
4308 if (ALTIVEC_REGNO_P (regno
))
4310 (GET_MODE_SIZE (mode
) + UNITS_PER_ALTIVEC_WORD
- 1) / UNITS_PER_ALTIVEC_WORD
;
4312 /* The value returned for SCmode in the E500 double case is 2 for
4313 ABI compatibility; storing an SCmode value in a single register
4314 would require function_arg and rs6000_spe_function_arg to handle
4315 SCmode so as to pass the value correctly in a pair of
4317 if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
)
4318 return (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
4320 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4323 /* Change register usage conditional on target flags. */
4325 rs6000_conditional_register_usage (void)
4329 /* Set MQ register fixed (already call_used) if not POWER
4330 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4335 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4337 fixed_regs
[13] = call_used_regs
[13]
4338 = call_really_used_regs
[13] = 1;
4340 /* Conditionally disable FPRs. */
4341 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
4342 for (i
= 32; i
< 64; i
++)
4343 fixed_regs
[i
] = call_used_regs
[i
]
4344 = call_really_used_regs
[i
] = 1;
4346 /* The TOC register is not killed across calls in a way that is
4347 visible to the compiler. */
4348 if (DEFAULT_ABI
== ABI_AIX
)
4349 call_really_used_regs
[2] = 0;
4351 if (DEFAULT_ABI
== ABI_V4
4352 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4354 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4356 if (DEFAULT_ABI
== ABI_V4
4357 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
4359 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4360 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4361 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4363 if (DEFAULT_ABI
== ABI_DARWIN
4364 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
4365 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4366 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4367 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4369 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
4370 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
4371 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
4375 global_regs
[SPEFSCR_REGNO
] = 1;
4376 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4377 registers in prologues and epilogues. We no longer use r14
4378 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4379 pool for link-compatibility with older versions of GCC. Once
4380 "old" code has died out, we can return r14 to the allocation
4383 = call_used_regs
[14]
4384 = call_really_used_regs
[14] = 1;
4387 if (!TARGET_ALTIVEC
)
4389 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
4390 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4391 call_really_used_regs
[VRSAVE_REGNO
] = 1;
4395 global_regs
[VSCR_REGNO
] = 1;
4397 if (TARGET_ALTIVEC_ABI
)
4399 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
4400 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4402 /* AIX reserves VR20:31 in non-extended ABI mode. */
4404 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
4405 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
4409 /* Try to output insns to set TARGET equal to the constant C if it can
4410 be done in less than N insns. Do all computations in MODE.
4411 Returns the place where the output has been placed if it can be
4412 done and the insns have been emitted. If it would take more than N
4413 insns, zero is returned and no insns and emitted. */
4416 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
4417 rtx source
, int n ATTRIBUTE_UNUSED
)
4419 rtx result
, insn
, set
;
4420 HOST_WIDE_INT c0
, c1
;
4427 dest
= gen_reg_rtx (mode
);
4428 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
4432 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
4434 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
4435 GEN_INT (INTVAL (source
)
4436 & (~ (HOST_WIDE_INT
) 0xffff))));
4437 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
4438 gen_rtx_IOR (SImode
, copy_rtx (result
),
4439 GEN_INT (INTVAL (source
) & 0xffff))));
4444 switch (GET_CODE (source
))
4447 c0
= INTVAL (source
);
4452 #if HOST_BITS_PER_WIDE_INT >= 64
4453 c0
= CONST_DOUBLE_LOW (source
);
4456 c0
= CONST_DOUBLE_LOW (source
);
4457 c1
= CONST_DOUBLE_HIGH (source
);
4465 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
4472 insn
= get_last_insn ();
4473 set
= single_set (insn
);
4474 if (! CONSTANT_P (SET_SRC (set
)))
4475 set_unique_reg_note (insn
, REG_EQUAL
, source
);
4480 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4481 fall back to a straight forward decomposition. We do this to avoid
4482 exponential run times encountered when looking for longer sequences
4483 with rs6000_emit_set_const. */
4485 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
4487 if (!TARGET_POWERPC64
)
4489 rtx operand1
, operand2
;
4491 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
4493 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
4495 emit_move_insn (operand1
, GEN_INT (c1
));
4496 emit_move_insn (operand2
, GEN_INT (c2
));
4500 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
4503 ud2
= (c1
& 0xffff0000) >> 16;
4504 #if HOST_BITS_PER_WIDE_INT >= 64
4508 ud4
= (c2
& 0xffff0000) >> 16;
4510 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
4511 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
4514 emit_move_insn (dest
, GEN_INT (((ud1
^ 0x8000) - 0x8000)));
4516 emit_move_insn (dest
, GEN_INT (ud1
));
4519 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
4520 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
4523 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
4526 emit_move_insn (dest
, GEN_INT (ud2
<< 16));
4528 emit_move_insn (copy_rtx (dest
),
4529 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4532 else if ((ud4
== 0xffff && (ud3
& 0x8000))
4533 || (ud4
== 0 && ! (ud3
& 0x8000)))
4536 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
4539 emit_move_insn (dest
, GEN_INT (ud3
<< 16));
4542 emit_move_insn (copy_rtx (dest
),
4543 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4545 emit_move_insn (copy_rtx (dest
),
4546 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4549 emit_move_insn (copy_rtx (dest
),
4550 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4556 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
4559 emit_move_insn (dest
, GEN_INT (ud4
<< 16));
4562 emit_move_insn (copy_rtx (dest
),
4563 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4566 emit_move_insn (copy_rtx (dest
),
4567 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
4570 emit_move_insn (copy_rtx (dest
),
4571 gen_rtx_IOR (DImode
, copy_rtx (dest
),
4572 GEN_INT (ud2
<< 16)));
4574 emit_move_insn (copy_rtx (dest
),
4575 gen_rtx_IOR (DImode
, copy_rtx (dest
), GEN_INT (ud1
)));
4581 /* Helper for the following. Get rid of [r+r] memory refs
4582 in cases where it won't work (TImode, TFmode, TDmode). */
4585 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
4587 if (GET_CODE (operands
[0]) == MEM
4588 && GET_CODE (XEXP (operands
[0], 0)) != REG
4589 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0))
4590 && ! reload_in_progress
)
4592 = replace_equiv_address (operands
[0],
4593 copy_addr_to_reg (XEXP (operands
[0], 0)));
4595 if (GET_CODE (operands
[1]) == MEM
4596 && GET_CODE (XEXP (operands
[1], 0)) != REG
4597 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0))
4598 && ! reload_in_progress
)
4600 = replace_equiv_address (operands
[1],
4601 copy_addr_to_reg (XEXP (operands
[1], 0)));
4604 /* Emit a move from SOURCE to DEST in mode MODE. */
4606 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
4610 operands
[1] = source
;
4612 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4613 if (GET_CODE (operands
[1]) == CONST_DOUBLE
4614 && ! FLOAT_MODE_P (mode
)
4615 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4617 /* FIXME. This should never happen. */
4618 /* Since it seems that it does, do the safe thing and convert
4620 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
4622 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
4623 || FLOAT_MODE_P (mode
)
4624 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
4625 || CONST_DOUBLE_LOW (operands
[1]) < 0)
4626 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
4627 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
4629 /* Check if GCC is setting up a block move that will end up using FP
4630 registers as temporaries. We must make sure this is acceptable. */
4631 if (GET_CODE (operands
[0]) == MEM
4632 && GET_CODE (operands
[1]) == MEM
4634 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
4635 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
4636 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
4637 ? 32 : MEM_ALIGN (operands
[0])))
4638 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
4640 : MEM_ALIGN (operands
[1]))))
4641 && ! MEM_VOLATILE_P (operands
[0])
4642 && ! MEM_VOLATILE_P (operands
[1]))
4644 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
4645 adjust_address (operands
[1], SImode
, 0));
4646 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
4647 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
4651 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
4652 && !gpc_reg_operand (operands
[1], mode
))
4653 operands
[1] = force_reg (mode
, operands
[1]);
4655 if (mode
== SFmode
&& ! TARGET_POWERPC
4656 && TARGET_HARD_FLOAT
&& TARGET_FPRS
4657 && GET_CODE (operands
[0]) == MEM
)
4661 if (reload_in_progress
|| reload_completed
)
4662 regnum
= true_regnum (operands
[1]);
4663 else if (GET_CODE (operands
[1]) == REG
)
4664 regnum
= REGNO (operands
[1]);
4668 /* If operands[1] is a register, on POWER it may have
4669 double-precision data in it, so truncate it to single
4671 if (FP_REGNO_P (regnum
) || regnum
>= FIRST_PSEUDO_REGISTER
)
4674 newreg
= (!can_create_pseudo_p () ? copy_rtx (operands
[1])
4675 : gen_reg_rtx (mode
));
4676 emit_insn (gen_aux_truncdfsf2 (newreg
, operands
[1]));
4677 operands
[1] = newreg
;
4681 /* Recognize the case where operand[1] is a reference to thread-local
4682 data and load its address to a register. */
4683 if (rs6000_tls_referenced_p (operands
[1]))
4685 enum tls_model model
;
4686 rtx tmp
= operands
[1];
4689 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
4691 addend
= XEXP (XEXP (tmp
, 0), 1);
4692 tmp
= XEXP (XEXP (tmp
, 0), 0);
4695 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
4696 model
= SYMBOL_REF_TLS_MODEL (tmp
);
4697 gcc_assert (model
!= 0);
4699 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
4702 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
4703 tmp
= force_operand (tmp
, operands
[0]);
4708 /* Handle the case where reload calls us with an invalid address. */
4709 if (reload_in_progress
&& mode
== Pmode
4710 && (! general_operand (operands
[1], mode
)
4711 || ! nonimmediate_operand (operands
[0], mode
)))
4714 /* 128-bit constant floating-point values on Darwin should really be
4715 loaded as two parts. */
4716 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
4717 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
4719 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4720 know how to get a DFmode SUBREG of a TFmode. */
4721 enum machine_mode imode
= (TARGET_E500_DOUBLE
? DFmode
: DImode
);
4722 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
, 0),
4723 simplify_gen_subreg (imode
, operands
[1], mode
, 0),
4725 rs6000_emit_move (simplify_gen_subreg (imode
, operands
[0], mode
,
4726 GET_MODE_SIZE (imode
)),
4727 simplify_gen_subreg (imode
, operands
[1], mode
,
4728 GET_MODE_SIZE (imode
)),
4733 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
4734 cfun
->machine
->sdmode_stack_slot
=
4735 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
4737 if (reload_in_progress
4739 && MEM_P (operands
[0])
4740 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
4741 && REG_P (operands
[1]))
4743 if (FP_REGNO_P (REGNO (operands
[1])))
4745 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
4746 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4747 emit_insn (gen_movsd_store (mem
, operands
[1]));
4749 else if (INT_REGNO_P (REGNO (operands
[1])))
4751 rtx mem
= adjust_address_nv (operands
[0], mode
, 4);
4752 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4753 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
4759 if (reload_in_progress
4761 && REG_P (operands
[0])
4762 && MEM_P (operands
[1])
4763 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
4765 if (FP_REGNO_P (REGNO (operands
[0])))
4767 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
4768 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4769 emit_insn (gen_movsd_load (operands
[0], mem
));
4771 else if (INT_REGNO_P (REGNO (operands
[0])))
4773 rtx mem
= adjust_address_nv (operands
[1], mode
, 4);
4774 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
4775 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
4782 /* FIXME: In the long term, this switch statement should go away
4783 and be replaced by a sequence of tests based on things like
4789 if (CONSTANT_P (operands
[1])
4790 && GET_CODE (operands
[1]) != CONST_INT
)
4791 operands
[1] = force_const_mem (mode
, operands
[1]);
4796 rs6000_eliminate_indexed_memrefs (operands
);
4803 if (CONSTANT_P (operands
[1])
4804 && ! easy_fp_constant (operands
[1], mode
))
4805 operands
[1] = force_const_mem (mode
, operands
[1]);
4816 if (CONSTANT_P (operands
[1])
4817 && !easy_vector_constant (operands
[1], mode
))
4818 operands
[1] = force_const_mem (mode
, operands
[1]);
4823 /* Use default pattern for address of ELF small data */
4826 && DEFAULT_ABI
== ABI_V4
4827 && (GET_CODE (operands
[1]) == SYMBOL_REF
4828 || GET_CODE (operands
[1]) == CONST
)
4829 && small_data_operand (operands
[1], mode
))
4831 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4835 if (DEFAULT_ABI
== ABI_V4
4836 && mode
== Pmode
&& mode
== SImode
4837 && flag_pic
== 1 && got_operand (operands
[1], mode
))
4839 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
4843 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
4847 && CONSTANT_P (operands
[1])
4848 && GET_CODE (operands
[1]) != HIGH
4849 && GET_CODE (operands
[1]) != CONST_INT
)
4851 rtx target
= (!can_create_pseudo_p ()
4853 : gen_reg_rtx (mode
));
4855 /* If this is a function address on -mcall-aixdesc,
4856 convert it to the address of the descriptor. */
4857 if (DEFAULT_ABI
== ABI_AIX
4858 && GET_CODE (operands
[1]) == SYMBOL_REF
4859 && XSTR (operands
[1], 0)[0] == '.')
4861 const char *name
= XSTR (operands
[1], 0);
4863 while (*name
== '.')
4865 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
4866 CONSTANT_POOL_ADDRESS_P (new_ref
)
4867 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
4868 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
4869 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
4870 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
4871 operands
[1] = new_ref
;
4874 if (DEFAULT_ABI
== ABI_DARWIN
)
4877 if (MACHO_DYNAMIC_NO_PIC_P
)
4879 /* Take care of any required data indirection. */
4880 operands
[1] = rs6000_machopic_legitimize_pic_address (
4881 operands
[1], mode
, operands
[0]);
4882 if (operands
[0] != operands
[1])
4883 emit_insn (gen_rtx_SET (VOIDmode
,
4884 operands
[0], operands
[1]));
4888 emit_insn (gen_macho_high (target
, operands
[1]));
4889 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
4893 emit_insn (gen_elf_high (target
, operands
[1]));
4894 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
4898 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4899 and we have put it in the TOC, we just need to make a TOC-relative
4902 && GET_CODE (operands
[1]) == SYMBOL_REF
4903 && constant_pool_expr_p (operands
[1])
4904 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands
[1]),
4905 get_pool_mode (operands
[1])))
4907 operands
[1] = create_TOC_reference (operands
[1]);
4909 else if (mode
== Pmode
4910 && CONSTANT_P (operands
[1])
4911 && ((GET_CODE (operands
[1]) != CONST_INT
4912 && ! easy_fp_constant (operands
[1], mode
))
4913 || (GET_CODE (operands
[1]) == CONST_INT
4914 && num_insns_constant (operands
[1], mode
) > 2)
4915 || (GET_CODE (operands
[0]) == REG
4916 && FP_REGNO_P (REGNO (operands
[0]))))
4917 && GET_CODE (operands
[1]) != HIGH
4918 && ! legitimate_constant_pool_address_p (operands
[1])
4919 && ! toc_relative_expr_p (operands
[1]))
4921 /* Emit a USE operation so that the constant isn't deleted if
4922 expensive optimizations are turned on because nobody
4923 references it. This should only be done for operands that
4924 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4925 This should not be done for operands that contain LABEL_REFs.
4926 For now, we just handle the obvious case. */
4927 if (GET_CODE (operands
[1]) != LABEL_REF
)
4928 emit_insn (gen_rtx_USE (VOIDmode
, operands
[1]));
4931 /* Darwin uses a special PIC legitimizer. */
4932 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
4935 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
4937 if (operands
[0] != operands
[1])
4938 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
4943 /* If we are to limit the number of things we put in the TOC and
4944 this is a symbol plus a constant we can add in one insn,
4945 just put the symbol in the TOC and add the constant. Don't do
4946 this if reload is in progress. */
4947 if (GET_CODE (operands
[1]) == CONST
4948 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
4949 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
4950 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
4951 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
4952 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
4953 && ! side_effects_p (operands
[0]))
4956 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
4957 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
4959 sym
= force_reg (mode
, sym
);
4961 emit_insn (gen_addsi3 (operands
[0], sym
, other
));
4963 emit_insn (gen_adddi3 (operands
[0], sym
, other
));
4967 operands
[1] = force_const_mem (mode
, operands
[1]);
4970 && constant_pool_expr_p (XEXP (operands
[1], 0))
4971 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4972 get_pool_constant (XEXP (operands
[1], 0)),
4973 get_pool_mode (XEXP (operands
[1], 0))))
4976 = gen_const_mem (mode
,
4977 create_TOC_reference (XEXP (operands
[1], 0)));
4978 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
4984 rs6000_eliminate_indexed_memrefs (operands
);
4988 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
4990 gen_rtx_SET (VOIDmode
,
4991 operands
[0], operands
[1]),
4992 gen_rtx_CLOBBER (VOIDmode
,
4993 gen_rtx_SCRATCH (SImode
)))));
5002 /* Above, we may have called force_const_mem which may have returned
5003 an invalid address. If we can, fix this up; otherwise, reload will
5004 have to deal with it. */
5005 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
5006 operands
[1] = validize_mem (operands
[1]);
5009 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
5012 /* Nonzero if we can use a floating-point register to pass this arg. */
5013 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
5014 (SCALAR_FLOAT_MODE_P (MODE) \
5015 && (CUM)->fregno <= FP_ARG_MAX_REG \
5016 && TARGET_HARD_FLOAT && TARGET_FPRS)
5018 /* Nonzero if we can use an AltiVec register to pass this arg. */
5019 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
5020 (ALTIVEC_VECTOR_MODE (MODE) \
5021 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
5022 && TARGET_ALTIVEC_ABI \
5025 /* Return a nonzero value to say to return the function value in
5026 memory, just as large structures are always returned. TYPE will be
5027 the data type of the value, and FNTYPE will be the type of the
5028 function doing the returning, or @code{NULL} for libcalls.
5030 The AIX ABI for the RS/6000 specifies that all structures are
5031 returned in memory. The Darwin ABI does the same. The SVR4 ABI
5032 specifies that structures <= 8 bytes are returned in r3/r4, but a
5033 draft put them in memory, and GCC used to implement the draft
5034 instead of the final standard. Therefore, aix_struct_return
5035 controls this instead of DEFAULT_ABI; V.4 targets needing backward
5036 compatibility can change DRAFT_V4_STRUCT_RET to override the
5037 default, and -m switches get the final word. See
5038 rs6000_override_options for more details.
5040 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
5041 long double support is enabled. These values are returned in memory.
5043 int_size_in_bytes returns -1 for variable size objects, which go in
5044 memory always. The cast to unsigned makes -1 > 8. */
5047 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5049 /* In the darwin64 abi, try to use registers for larger structs
5051 if (rs6000_darwin64_abi
5052 && TREE_CODE (type
) == RECORD_TYPE
5053 && int_size_in_bytes (type
) > 0)
5055 CUMULATIVE_ARGS valcum
;
5059 valcum
.fregno
= FP_ARG_MIN_REG
;
5060 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
5061 /* Do a trial code generation as if this were going to be passed
5062 as an argument; if any part goes in memory, we return NULL. */
5063 valret
= rs6000_darwin64_record_arg (&valcum
, type
, 1, true);
5066 /* Otherwise fall through to more conventional ABI rules. */
5069 if (AGGREGATE_TYPE_P (type
)
5070 && (aix_struct_return
5071 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
5074 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5075 modes only exist for GCC vector types if -maltivec. */
5076 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
5077 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
5080 /* Return synthetic vectors in memory. */
5081 if (TREE_CODE (type
) == VECTOR_TYPE
5082 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
5084 static bool warned_for_return_big_vectors
= false;
5085 if (!warned_for_return_big_vectors
)
5087 warning (0, "GCC vector returned by reference: "
5088 "non-standard ABI extension with no compatibility guarantee");
5089 warned_for_return_big_vectors
= true;
5094 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
5100 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5101 for a call to a function whose data type is FNTYPE.
5102 For a library call, FNTYPE is 0.
5104 For incoming args we set the number of arguments in the prototype large
5105 so we never return a PARALLEL. */
5108 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
5109 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
5110 int libcall
, int n_named_args
)
5112 static CUMULATIVE_ARGS zero_cumulative
;
5114 *cum
= zero_cumulative
;
5116 cum
->fregno
= FP_ARG_MIN_REG
;
5117 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
5118 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
5119 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
5120 ? CALL_LIBCALL
: CALL_NORMAL
);
5121 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
5122 cum
->stdarg
= fntype
5123 && (TYPE_ARG_TYPES (fntype
) != 0
5124 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
5125 != void_type_node
));
5127 cum
->nargs_prototype
= 0;
5128 if (incoming
|| cum
->prototype
)
5129 cum
->nargs_prototype
= n_named_args
;
5131 /* Check for a longcall attribute. */
5132 if ((!fntype
&& rs6000_default_long_calls
)
5134 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
5135 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
5136 cum
->call_cookie
|= CALL_LONG
;
5138 if (TARGET_DEBUG_ARG
)
5140 fprintf (stderr
, "\ninit_cumulative_args:");
5143 tree ret_type
= TREE_TYPE (fntype
);
5144 fprintf (stderr
, " ret code = %s,",
5145 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
5148 if (cum
->call_cookie
& CALL_LONG
)
5149 fprintf (stderr
, " longcall,");
5151 fprintf (stderr
, " proto = %d, nargs = %d\n",
5152 cum
->prototype
, cum
->nargs_prototype
);
5157 && TARGET_ALTIVEC_ABI
5158 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
5160 error ("cannot return value in vector register because"
5161 " altivec instructions are disabled, use -maltivec"
5166 /* Return true if TYPE must be passed on the stack and not in registers. */
5169 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
5171 if (DEFAULT_ABI
== ABI_AIX
|| TARGET_64BIT
)
5172 return must_pass_in_stack_var_size (mode
, type
);
5174 return must_pass_in_stack_var_size_or_pad (mode
, type
);
5177 /* If defined, a C expression which determines whether, and in which
5178 direction, to pad out an argument with extra space. The value
5179 should be of type `enum direction': either `upward' to pad above
5180 the argument, `downward' to pad below, or `none' to inhibit
5183 For the AIX ABI structs are always stored left shifted in their
5187 function_arg_padding (enum machine_mode mode
, const_tree type
)
5189 #ifndef AGGREGATE_PADDING_FIXED
5190 #define AGGREGATE_PADDING_FIXED 0
5192 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
5193 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
5196 if (!AGGREGATE_PADDING_FIXED
)
5198 /* GCC used to pass structures of the same size as integer types as
5199 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
5200 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
5201 passed padded downward, except that -mstrict-align further
5202 muddied the water in that multi-component structures of 2 and 4
5203 bytes in size were passed padded upward.
5205 The following arranges for best compatibility with previous
5206 versions of gcc, but removes the -mstrict-align dependency. */
5207 if (BYTES_BIG_ENDIAN
)
5209 HOST_WIDE_INT size
= 0;
5211 if (mode
== BLKmode
)
5213 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
5214 size
= int_size_in_bytes (type
);
5217 size
= GET_MODE_SIZE (mode
);
5219 if (size
== 1 || size
== 2 || size
== 4)
5225 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
5227 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
5231 /* Fall back to the default. */
5232 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
5235 /* If defined, a C expression that gives the alignment boundary, in bits,
5236 of an argument with the specified mode and type. If it is not defined,
5237 PARM_BOUNDARY is used for all arguments.
5239 V.4 wants long longs and doubles to be double word aligned. Just
5240 testing the mode size is a boneheaded way to do this as it means
5241 that other types such as complex int are also double word aligned.
5242 However, we're stuck with this because changing the ABI might break
5243 existing library interfaces.
5245 Doubleword align SPE vectors.
5246 Quadword align Altivec vectors.
5247 Quadword align large synthetic vector types. */
5250 function_arg_boundary (enum machine_mode mode
, tree type
)
5252 if (DEFAULT_ABI
== ABI_V4
5253 && (GET_MODE_SIZE (mode
) == 8
5254 || (TARGET_HARD_FLOAT
5256 && (mode
== TFmode
|| mode
== TDmode
))))
5258 else if (SPE_VECTOR_MODE (mode
)
5259 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5260 && int_size_in_bytes (type
) >= 8
5261 && int_size_in_bytes (type
) < 16))
5263 else if (ALTIVEC_VECTOR_MODE (mode
)
5264 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5265 && int_size_in_bytes (type
) >= 16))
5267 else if (rs6000_darwin64_abi
&& mode
== BLKmode
5268 && type
&& TYPE_ALIGN (type
) > 64)
5271 return PARM_BOUNDARY
;
5274 /* For a function parm of MODE and TYPE, return the starting word in
5275 the parameter area. NWORDS of the parameter area are already used. */
5278 rs6000_parm_start (enum machine_mode mode
, tree type
, unsigned int nwords
)
5281 unsigned int parm_offset
;
5283 align
= function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
5284 parm_offset
= DEFAULT_ABI
== ABI_V4
? 2 : 6;
5285 return nwords
+ (-(parm_offset
+ nwords
) & align
);
5288 /* Compute the size (in words) of a function argument. */
5290 static unsigned long
5291 rs6000_arg_size (enum machine_mode mode
, tree type
)
5295 if (mode
!= BLKmode
)
5296 size
= GET_MODE_SIZE (mode
);
5298 size
= int_size_in_bytes (type
);
5301 return (size
+ 3) >> 2;
5303 return (size
+ 7) >> 3;
5306 /* Use this to flush pending int fields. */
5309 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
5310 HOST_WIDE_INT bitpos
)
5312 unsigned int startbit
, endbit
;
5313 int intregs
, intoffset
;
5314 enum machine_mode mode
;
5316 if (cum
->intoffset
== -1)
5319 intoffset
= cum
->intoffset
;
5320 cum
->intoffset
= -1;
5322 if (intoffset
% BITS_PER_WORD
!= 0)
5324 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5326 if (mode
== BLKmode
)
5328 /* We couldn't find an appropriate mode, which happens,
5329 e.g., in packed structs when there are 3 bytes to load.
5330 Back intoffset back to the beginning of the word in this
5332 intoffset
= intoffset
& -BITS_PER_WORD
;
5336 startbit
= intoffset
& -BITS_PER_WORD
;
5337 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5338 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
5339 cum
->words
+= intregs
;
5342 /* The darwin64 ABI calls for us to recurse down through structs,
5343 looking for elements passed in registers. Unfortunately, we have
5344 to track int register count here also because of misalignments
5345 in powerpc alignment mode. */
5348 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
5350 HOST_WIDE_INT startbitpos
)
5354 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5355 if (TREE_CODE (f
) == FIELD_DECL
)
5357 HOST_WIDE_INT bitpos
= startbitpos
;
5358 tree ftype
= TREE_TYPE (f
);
5359 enum machine_mode mode
;
5360 if (ftype
== error_mark_node
)
5362 mode
= TYPE_MODE (ftype
);
5364 if (DECL_SIZE (f
) != 0
5365 && host_integerp (bit_position (f
), 1))
5366 bitpos
+= int_bit_position (f
);
5368 /* ??? FIXME: else assume zero offset. */
5370 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5371 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
5372 else if (USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
5374 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5375 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5376 cum
->words
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5378 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, 1))
5380 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
);
5384 else if (cum
->intoffset
== -1)
5385 cum
->intoffset
= bitpos
;
5389 /* Update the data in CUM to advance over an argument
5390 of mode MODE and data type TYPE.
5391 (TYPE is null for libcalls where that information may not be available.)
5393 Note that for args passed by reference, function_arg will be called
5394 with MODE and TYPE set to that of the pointer to the arg, not the arg
5398 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5399 tree type
, int named
, int depth
)
5403 /* Only tick off an argument if we're not recursing. */
5405 cum
->nargs_prototype
--;
5407 if (TARGET_ALTIVEC_ABI
5408 && (ALTIVEC_VECTOR_MODE (mode
)
5409 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
5410 && int_size_in_bytes (type
) == 16)))
5414 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5417 if (!TARGET_ALTIVEC
)
5418 error ("cannot pass argument in vector register because"
5419 " altivec instructions are disabled, use -maltivec"
5422 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5423 even if it is going to be passed in a vector register.
5424 Darwin does the same for variable-argument functions. */
5425 if ((DEFAULT_ABI
== ABI_AIX
&& TARGET_64BIT
)
5426 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
5436 /* Vector parameters must be 16-byte aligned. This places
5437 them at 2 mod 4 in terms of words in 32-bit mode, since
5438 the parameter save area starts at offset 24 from the
5439 stack. In 64-bit mode, they just have to start on an
5440 even word, since the parameter save area is 16-byte
5441 aligned. Space for GPRs is reserved even if the argument
5442 will be passed in memory. */
5444 align
= (2 - cum
->words
) & 3;
5446 align
= cum
->words
& 1;
5447 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
5449 if (TARGET_DEBUG_ARG
)
5451 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
5453 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
5454 cum
->nargs_prototype
, cum
->prototype
,
5455 GET_MODE_NAME (mode
));
5459 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
5461 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
5464 else if (rs6000_darwin64_abi
5466 && TREE_CODE (type
) == RECORD_TYPE
5467 && (size
= int_size_in_bytes (type
)) > 0)
5469 /* Variable sized types have size == -1 and are
5470 treated as if consisting entirely of ints.
5471 Pad to 16 byte boundary if needed. */
5472 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5473 && (cum
->words
% 2) != 0)
5475 /* For varargs, we can just go up by the size of the struct. */
5477 cum
->words
+= (size
+ 7) / 8;
5480 /* It is tempting to say int register count just goes up by
5481 sizeof(type)/8, but this is wrong in a case such as
5482 { int; double; int; } [powerpc alignment]. We have to
5483 grovel through the fields for these too. */
5485 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
5486 rs6000_darwin64_record_arg_advance_flush (cum
,
5487 size
* BITS_PER_UNIT
);
5490 else if (DEFAULT_ABI
== ABI_V4
)
5492 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5493 && (mode
== SFmode
|| mode
== DFmode
5494 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
5495 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)))
5497 /* _Decimal128 must use an even/odd register pair. This assumes
5498 that the register number is odd when fregno is odd. */
5499 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5502 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
5503 <= FP_ARG_V4_MAX_REG
)
5504 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5507 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
5508 if (mode
== DFmode
|| mode
== TFmode
5509 || mode
== DDmode
|| mode
== TDmode
)
5510 cum
->words
+= cum
->words
& 1;
5511 cum
->words
+= rs6000_arg_size (mode
, type
);
5516 int n_words
= rs6000_arg_size (mode
, type
);
5517 int gregno
= cum
->sysv_gregno
;
5519 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5520 (r7,r8) or (r9,r10). As does any other 2 word item such
5521 as complex int due to a historical mistake. */
5523 gregno
+= (1 - gregno
) & 1;
5525 /* Multi-reg args are not split between registers and stack. */
5526 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5528 /* Long long and SPE vectors are aligned on the stack.
5529 So are other 2 word items such as complex int due to
5530 a historical mistake. */
5532 cum
->words
+= cum
->words
& 1;
5533 cum
->words
+= n_words
;
5536 /* Note: continuing to accumulate gregno past when we've started
5537 spilling to the stack indicates the fact that we've started
5538 spilling to the stack to expand_builtin_saveregs. */
5539 cum
->sysv_gregno
= gregno
+ n_words
;
5542 if (TARGET_DEBUG_ARG
)
5544 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5545 cum
->words
, cum
->fregno
);
5546 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
5547 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
5548 fprintf (stderr
, "mode = %4s, named = %d\n",
5549 GET_MODE_NAME (mode
), named
);
5554 int n_words
= rs6000_arg_size (mode
, type
);
5555 int start_words
= cum
->words
;
5556 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
5558 cum
->words
= align_words
+ n_words
;
5560 if (SCALAR_FLOAT_MODE_P (mode
)
5561 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5563 /* _Decimal128 must be passed in an even/odd float register pair.
5564 This assumes that the register number is odd when fregno is
5566 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
5568 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
5571 if (TARGET_DEBUG_ARG
)
5573 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
5574 cum
->words
, cum
->fregno
);
5575 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
5576 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
5577 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
5578 named
, align_words
- start_words
, depth
);
5584 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
5592 r1
= gen_rtx_REG (DImode
, gregno
);
5593 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5594 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
5599 r1
= gen_rtx_REG (DImode
, gregno
);
5600 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5601 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5602 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5603 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
5606 r1
= gen_rtx_REG (DImode
, gregno
);
5607 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
5608 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
5609 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
5610 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
5611 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
5612 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
5613 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
5614 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
5621 /* Determine where to put a SIMD argument on the SPE. */
5623 rs6000_spe_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5626 int gregno
= cum
->sysv_gregno
;
5628 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5629 are passed and returned in a pair of GPRs for ABI compatibility. */
5630 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
5631 || mode
== DDmode
|| mode
== TDmode
5632 || mode
== DCmode
|| mode
== TCmode
))
5634 int n_words
= rs6000_arg_size (mode
, type
);
5636 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5637 if (mode
== DFmode
|| mode
== DDmode
)
5638 gregno
+= (1 - gregno
) & 1;
5640 /* Multi-reg args are not split between registers and stack. */
5641 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
5644 return spe_build_register_parallel (mode
, gregno
);
5648 int n_words
= rs6000_arg_size (mode
, type
);
5650 /* SPE vectors are put in odd registers. */
5651 if (n_words
== 2 && (gregno
& 1) == 0)
5654 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
5657 enum machine_mode m
= SImode
;
5659 r1
= gen_rtx_REG (m
, gregno
);
5660 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
5661 r2
= gen_rtx_REG (m
, gregno
+ 1);
5662 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
5663 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
5670 if (gregno
<= GP_ARG_MAX_REG
)
5671 return gen_rtx_REG (mode
, gregno
);
5677 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5678 structure between cum->intoffset and bitpos to integer registers. */
5681 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
5682 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
5684 enum machine_mode mode
;
5686 unsigned int startbit
, endbit
;
5687 int this_regno
, intregs
, intoffset
;
5690 if (cum
->intoffset
== -1)
5693 intoffset
= cum
->intoffset
;
5694 cum
->intoffset
= -1;
5696 /* If this is the trailing part of a word, try to only load that
5697 much into the register. Otherwise load the whole register. Note
5698 that in the latter case we may pick up unwanted bits. It's not a
5699 problem at the moment but may wish to revisit. */
5701 if (intoffset
% BITS_PER_WORD
!= 0)
5703 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5705 if (mode
== BLKmode
)
5707 /* We couldn't find an appropriate mode, which happens,
5708 e.g., in packed structs when there are 3 bytes to load.
5709 Back intoffset back to the beginning of the word in this
5711 intoffset
= intoffset
& -BITS_PER_WORD
;
5718 startbit
= intoffset
& -BITS_PER_WORD
;
5719 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5720 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
5721 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
5723 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
5726 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
5730 intoffset
/= BITS_PER_UNIT
;
5733 regno
= GP_ARG_MIN_REG
+ this_regno
;
5734 reg
= gen_rtx_REG (mode
, regno
);
5736 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5739 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5743 while (intregs
> 0);
5746 /* Recursive workhorse for the following. */
5749 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
5750 HOST_WIDE_INT startbitpos
, rtx rvec
[],
5755 for (f
= TYPE_FIELDS (type
); f
; f
= TREE_CHAIN (f
))
5756 if (TREE_CODE (f
) == FIELD_DECL
)
5758 HOST_WIDE_INT bitpos
= startbitpos
;
5759 tree ftype
= TREE_TYPE (f
);
5760 enum machine_mode mode
;
5761 if (ftype
== error_mark_node
)
5763 mode
= TYPE_MODE (ftype
);
5765 if (DECL_SIZE (f
) != 0
5766 && host_integerp (bit_position (f
), 1))
5767 bitpos
+= int_bit_position (f
);
5769 /* ??? FIXME: else assume zero offset. */
5771 if (TREE_CODE (ftype
) == RECORD_TYPE
)
5772 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
5773 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
, ftype
))
5778 case SCmode
: mode
= SFmode
; break;
5779 case DCmode
: mode
= DFmode
; break;
5780 case TCmode
: mode
= TFmode
; break;
5784 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
5786 = gen_rtx_EXPR_LIST (VOIDmode
,
5787 gen_rtx_REG (mode
, cum
->fregno
++),
5788 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5789 if (mode
== TFmode
|| mode
== TDmode
)
5792 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, ftype
, 1))
5794 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
5796 = gen_rtx_EXPR_LIST (VOIDmode
,
5797 gen_rtx_REG (mode
, cum
->vregno
++),
5798 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5800 else if (cum
->intoffset
== -1)
5801 cum
->intoffset
= bitpos
;
5805 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5806 the register(s) to be used for each field and subfield of a struct
5807 being passed by value, along with the offset of where the
5808 register's value may be found in the block. FP fields go in FP
5809 register, vector fields go in vector registers, and everything
5810 else goes in int registers, packed as in memory.
5812 This code is also used for function return values. RETVAL indicates
5813 whether this is the case.
5815 Much of this is taken from the SPARC V9 port, which has a similar
5816 calling convention. */
5819 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
5820 int named
, bool retval
)
5822 rtx rvec
[FIRST_PSEUDO_REGISTER
];
5823 int k
= 1, kbase
= 1;
5824 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5825 /* This is a copy; modifications are not visible to our caller. */
5826 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
5827 CUMULATIVE_ARGS
*cum
= ©_cum
;
5829 /* Pad to 16 byte boundary if needed. */
5830 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
5831 && (cum
->words
% 2) != 0)
5838 /* Put entries into rvec[] for individual FP and vector fields, and
5839 for the chunks of memory that go in int regs. Note we start at
5840 element 1; 0 is reserved for an indication of using memory, and
5841 may or may not be filled in below. */
5842 rs6000_darwin64_record_arg_recurse (cum
, type
, 0, rvec
, &k
);
5843 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
5845 /* If any part of the struct went on the stack put all of it there.
5846 This hack is because the generic code for
5847 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5848 parts of the struct are not at the beginning. */
5852 return NULL_RTX
; /* doesn't go in registers at all */
5854 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5856 if (k
> 1 || cum
->use_stack
)
5857 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
5862 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5865 rs6000_mixed_function_arg (enum machine_mode mode
, tree type
, int align_words
)
5869 rtx rvec
[GP_ARG_NUM_REG
+ 1];
5871 if (align_words
>= GP_ARG_NUM_REG
)
5874 n_units
= rs6000_arg_size (mode
, type
);
5876 /* Optimize the simple case where the arg fits in one gpr, except in
5877 the case of BLKmode due to assign_parms assuming that registers are
5878 BITS_PER_WORD wide. */
5880 || (n_units
== 1 && mode
!= BLKmode
))
5881 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5884 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
5885 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5886 using a magic NULL_RTX component.
5887 This is not strictly correct. Only some of the arg belongs in
5888 memory, not all of it. However, the normal scheme using
5889 function_arg_partial_nregs can result in unusual subregs, eg.
5890 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5891 store the whole arg to memory is often more efficient than code
5892 to store pieces, and we know that space is available in the right
5893 place for the whole arg. */
5894 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5899 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
5900 rtx off
= GEN_INT (i
++ * 4);
5901 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
5903 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
5905 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
5908 /* Determine where to put an argument to a function.
5909 Value is zero to push the argument on the stack,
5910 or a hard register in which to store the argument.
5912 MODE is the argument's machine mode.
5913 TYPE is the data type of the argument (as a tree).
5914 This is null for libcalls where that information may
5916 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5917 the preceding args and about the function being called. It is
5918 not modified in this routine.
5919 NAMED is nonzero if this argument is a named parameter
5920 (otherwise it is an extra parameter matching an ellipsis).
5922 On RS/6000 the first eight words of non-FP are normally in registers
5923 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5924 Under V.4, the first 8 FP args are in registers.
5926 If this is floating-point and no prototype is specified, we use
5927 both an FP and integer register (or possibly FP reg and stack). Library
5928 functions (when CALL_LIBCALL is set) always have the proper types for args,
5929 so we can pass the FP value just in one register. emit_library_function
5930 doesn't support PARALLEL anyway.
5932 Note that for args passed by reference, function_arg will be called
5933 with MODE and TYPE set to that of the pointer to the arg, not the arg
5937 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5938 tree type
, int named
)
5940 enum rs6000_abi abi
= DEFAULT_ABI
;
5942 /* Return a marker to indicate whether CR1 needs to set or clear the
5943 bit that V.4 uses to say fp args were passed in registers.
5944 Assume that we don't need the marker for software floating point,
5945 or compiler generated library calls. */
5946 if (mode
== VOIDmode
)
5949 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
5951 || (cum
->nargs_prototype
< 0
5952 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
5954 /* For the SPE, we need to crxor CR6 always. */
5956 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
5957 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
5958 return GEN_INT (cum
->call_cookie
5959 | ((cum
->fregno
== FP_ARG_MIN_REG
)
5960 ? CALL_V4_SET_FP_ARGS
5961 : CALL_V4_CLEAR_FP_ARGS
));
5964 return GEN_INT (cum
->call_cookie
);
5967 if (rs6000_darwin64_abi
&& mode
== BLKmode
5968 && TREE_CODE (type
) == RECORD_TYPE
)
5970 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, false);
5971 if (rslt
!= NULL_RTX
)
5973 /* Else fall through to usual handling. */
5976 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
))
5977 if (TARGET_64BIT
&& ! cum
->prototype
)
5979 /* Vector parameters get passed in vector register
5980 and also in GPRs or memory, in absence of prototype. */
5983 align_words
= (cum
->words
+ 1) & ~1;
5985 if (align_words
>= GP_ARG_NUM_REG
)
5991 slot
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
5993 return gen_rtx_PARALLEL (mode
,
5995 gen_rtx_EXPR_LIST (VOIDmode
,
5997 gen_rtx_EXPR_LIST (VOIDmode
,
5998 gen_rtx_REG (mode
, cum
->vregno
),
6002 return gen_rtx_REG (mode
, cum
->vregno
);
6003 else if (TARGET_ALTIVEC_ABI
6004 && (ALTIVEC_VECTOR_MODE (mode
)
6005 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
6006 && int_size_in_bytes (type
) == 16)))
6008 if (named
|| abi
== ABI_V4
)
6012 /* Vector parameters to varargs functions under AIX or Darwin
6013 get passed in memory and possibly also in GPRs. */
6014 int align
, align_words
, n_words
;
6015 enum machine_mode part_mode
;
6017 /* Vector parameters must be 16-byte aligned. This places them at
6018 2 mod 4 in terms of words in 32-bit mode, since the parameter
6019 save area starts at offset 24 from the stack. In 64-bit mode,
6020 they just have to start on an even word, since the parameter
6021 save area is 16-byte aligned. */
6023 align
= (2 - cum
->words
) & 3;
6025 align
= cum
->words
& 1;
6026 align_words
= cum
->words
+ align
;
6028 /* Out of registers? Memory, then. */
6029 if (align_words
>= GP_ARG_NUM_REG
)
6032 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6033 return rs6000_mixed_function_arg (mode
, type
, align_words
);
6035 /* The vector value goes in GPRs. Only the part of the
6036 value in GPRs is reported here. */
6038 n_words
= rs6000_arg_size (mode
, type
);
6039 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
6040 /* Fortunately, there are only two possibilities, the value
6041 is either wholly in GPRs or half in GPRs and half not. */
6044 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
6047 else if (TARGET_SPE_ABI
&& TARGET_SPE
6048 && (SPE_VECTOR_MODE (mode
)
6049 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
6054 || mode
== TCmode
))))
6055 return rs6000_spe_function_arg (cum
, mode
, type
);
6057 else if (abi
== ABI_V4
)
6059 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6060 && (mode
== SFmode
|| mode
== DFmode
6061 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
6062 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
6064 /* _Decimal128 must use an even/odd register pair. This assumes
6065 that the register number is odd when fregno is odd. */
6066 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
6069 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
6070 <= FP_ARG_V4_MAX_REG
)
6071 return gen_rtx_REG (mode
, cum
->fregno
);
6077 int n_words
= rs6000_arg_size (mode
, type
);
6078 int gregno
= cum
->sysv_gregno
;
6080 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
6081 (r7,r8) or (r9,r10). As does any other 2 word item such
6082 as complex int due to a historical mistake. */
6084 gregno
+= (1 - gregno
) & 1;
6086 /* Multi-reg args are not split between registers and stack. */
6087 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
6090 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6091 return rs6000_mixed_function_arg (mode
, type
,
6092 gregno
- GP_ARG_MIN_REG
);
6093 return gen_rtx_REG (mode
, gregno
);
6098 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
6100 /* _Decimal128 must be passed in an even/odd float register pair.
6101 This assumes that the register number is odd when fregno is odd. */
6102 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
6105 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
6107 rtx rvec
[GP_ARG_NUM_REG
+ 1];
6111 enum machine_mode fmode
= mode
;
6112 unsigned long n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
6114 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
6116 /* Currently, we only ever need one reg here because complex
6117 doubles are split. */
6118 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
6119 && (fmode
== TFmode
|| fmode
== TDmode
));
6121 /* Long double or _Decimal128 split over regs and memory. */
6122 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
6125 /* Do we also need to pass this arg in the parameter save
6128 && (cum
->nargs_prototype
<= 0
6129 || (DEFAULT_ABI
== ABI_AIX
6131 && align_words
>= GP_ARG_NUM_REG
)));
6133 if (!needs_psave
&& mode
== fmode
)
6134 return gen_rtx_REG (fmode
, cum
->fregno
);
6139 /* Describe the part that goes in gprs or the stack.
6140 This piece must come first, before the fprs. */
6141 if (align_words
< GP_ARG_NUM_REG
)
6143 unsigned long n_words
= rs6000_arg_size (mode
, type
);
6145 if (align_words
+ n_words
> GP_ARG_NUM_REG
6146 || (TARGET_32BIT
&& TARGET_POWERPC64
))
6148 /* If this is partially on the stack, then we only
6149 include the portion actually in registers here. */
6150 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
6153 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
6154 /* Not all of the arg fits in gprs. Say that it
6155 goes in memory too, using a magic NULL_RTX
6156 component. Also see comment in
6157 rs6000_mixed_function_arg for why the normal
6158 function_arg_partial_nregs scheme doesn't work
6160 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
,
6164 r
= gen_rtx_REG (rmode
,
6165 GP_ARG_MIN_REG
+ align_words
);
6166 off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
6167 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
6169 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
6173 /* The whole arg fits in gprs. */
6174 r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6175 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
6179 /* It's entirely in memory. */
6180 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6183 /* Describe where this piece goes in the fprs. */
6184 r
= gen_rtx_REG (fmode
, cum
->fregno
);
6185 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
6187 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
6189 else if (align_words
< GP_ARG_NUM_REG
)
6191 if (TARGET_32BIT
&& TARGET_POWERPC64
)
6192 return rs6000_mixed_function_arg (mode
, type
, align_words
);
6194 if (mode
== BLKmode
)
6197 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
6204 /* For an arg passed partly in registers and partly in memory, this is
6205 the number of bytes passed in registers. For args passed entirely in
6206 registers or entirely in memory, zero. When an arg is described by a
6207 PARALLEL, perhaps using more than one register type, this function
6208 returns the number of bytes used by the first element of the PARALLEL. */
6211 rs6000_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6212 tree type
, bool named
)
6217 if (DEFAULT_ABI
== ABI_V4
)
6220 if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, type
, named
)
6221 && cum
->nargs_prototype
>= 0)
6224 /* In this complicated case we just disable the partial_nregs code. */
6225 if (rs6000_darwin64_abi
&& mode
== BLKmode
6226 && TREE_CODE (type
) == RECORD_TYPE
6227 && int_size_in_bytes (type
) > 0)
6230 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
6232 if (USE_FP_FOR_ARG_P (cum
, mode
, type
))
6234 /* If we are passing this arg in the fixed parameter save area
6235 (gprs or memory) as well as fprs, then this function should
6236 return the number of partial bytes passed in the parameter
6237 save area rather than partial bytes passed in fprs. */
6239 && (cum
->nargs_prototype
<= 0
6240 || (DEFAULT_ABI
== ABI_AIX
6242 && align_words
>= GP_ARG_NUM_REG
)))
6244 else if (cum
->fregno
+ ((GET_MODE_SIZE (mode
) + 7) >> 3)
6245 > FP_ARG_MAX_REG
+ 1)
6246 ret
= (FP_ARG_MAX_REG
+ 1 - cum
->fregno
) * 8;
6247 else if (cum
->nargs_prototype
>= 0)
6251 if (align_words
< GP_ARG_NUM_REG
6252 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
6253 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
6255 if (ret
!= 0 && TARGET_DEBUG_ARG
)
6256 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
6261 /* A C expression that indicates when an argument must be passed by
6262 reference. If nonzero for an argument, a copy of that argument is
6263 made in memory and a pointer to the argument is passed instead of
6264 the argument itself. The pointer is passed in whatever way is
6265 appropriate for passing a pointer to that type.
6267 Under V.4, aggregates and long double are passed by reference.
6269 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6270 reference unless the AltiVec vector extension ABI is in force.
6272 As an extension to all ABIs, variable sized types are passed by
6276 rs6000_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
6277 enum machine_mode mode
, const_tree type
,
6278 bool named ATTRIBUTE_UNUSED
)
6280 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
6282 if (TARGET_DEBUG_ARG
)
6283 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
6290 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
6292 if (TARGET_DEBUG_ARG
)
6293 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
6297 if (int_size_in_bytes (type
) < 0)
6299 if (TARGET_DEBUG_ARG
)
6300 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
6304 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6305 modes only exist for GCC vector types if -maltivec. */
6306 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
6308 if (TARGET_DEBUG_ARG
)
6309 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
6313 /* Pass synthetic vectors in memory. */
6314 if (TREE_CODE (type
) == VECTOR_TYPE
6315 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
6317 static bool warned_for_pass_big_vectors
= false;
6318 if (TARGET_DEBUG_ARG
)
6319 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
6320 if (!warned_for_pass_big_vectors
)
6322 warning (0, "GCC vector passed by reference: "
6323 "non-standard ABI extension with no compatibility guarantee");
6324 warned_for_pass_big_vectors
= true;
6333 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
6336 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
6341 for (i
= 0; i
< nregs
; i
++)
6343 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
6344 if (reload_completed
)
6346 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
6349 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
6350 i
* GET_MODE_SIZE (reg_mode
));
6353 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
6357 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
6361 /* Perform any needed actions needed for a function that is receiving a
6362 variable number of arguments.
6366 MODE and TYPE are the mode and type of the current parameter.
6368 PRETEND_SIZE is a variable that should be set to the amount of stack
6369 that must be pushed by the prolog to pretend that our caller pushed
6372 Normally, this macro will push all remaining incoming registers on the
6373 stack and set PRETEND_SIZE to the length of the registers pushed. */
6376 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
6377 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
6380 CUMULATIVE_ARGS next_cum
;
6381 int reg_size
= TARGET_32BIT
? 4 : 8;
6382 rtx save_area
= NULL_RTX
, mem
;
6383 int first_reg_offset
;
6386 /* Skip the last named argument. */
6388 function_arg_advance (&next_cum
, mode
, type
, 1, 0);
6390 if (DEFAULT_ABI
== ABI_V4
)
6392 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
6396 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
6397 HOST_WIDE_INT offset
= 0;
6399 /* Try to optimize the size of the varargs save area.
6400 The ABI requires that ap.reg_save_area is doubleword
6401 aligned, but we don't need to allocate space for all
6402 the bytes, only those to which we actually will save
6404 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
6405 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
6406 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6407 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6408 && cfun
->va_list_fpr_size
)
6411 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
6412 * UNITS_PER_FP_WORD
;
6413 if (cfun
->va_list_fpr_size
6414 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6415 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
6417 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
6418 * UNITS_PER_FP_WORD
;
6422 offset
= -((first_reg_offset
* reg_size
) & ~7);
6423 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
6425 gpr_reg_num
= cfun
->va_list_gpr_size
;
6426 if (reg_size
== 4 && (first_reg_offset
& 1))
6429 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
6432 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
6434 - (int) (GP_ARG_NUM_REG
* reg_size
);
6436 if (gpr_size
+ fpr_size
)
6439 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
6440 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
6441 reg_save_area
= XEXP (reg_save_area
, 0);
6442 if (GET_CODE (reg_save_area
) == PLUS
)
6444 gcc_assert (XEXP (reg_save_area
, 0)
6445 == virtual_stack_vars_rtx
);
6446 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
6447 offset
+= INTVAL (XEXP (reg_save_area
, 1));
6450 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
6453 cfun
->machine
->varargs_save_offset
= offset
;
6454 save_area
= plus_constant (virtual_stack_vars_rtx
, offset
);
6459 first_reg_offset
= next_cum
.words
;
6460 save_area
= virtual_incoming_args_rtx
;
6462 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
6463 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
6466 set
= get_varargs_alias_set ();
6467 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
6468 && cfun
->va_list_gpr_size
)
6470 int nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
6472 if (va_list_gpr_counter_field
)
6474 /* V4 va_list_gpr_size counts number of registers needed. */
6475 if (nregs
> cfun
->va_list_gpr_size
)
6476 nregs
= cfun
->va_list_gpr_size
;
6480 /* char * va_list instead counts number of bytes needed. */
6481 if (nregs
> cfun
->va_list_gpr_size
/ reg_size
)
6482 nregs
= cfun
->va_list_gpr_size
/ reg_size
;
6485 mem
= gen_rtx_MEM (BLKmode
,
6486 plus_constant (save_area
,
6487 first_reg_offset
* reg_size
));
6488 MEM_NOTRAP_P (mem
) = 1;
6489 set_mem_alias_set (mem
, set
);
6490 set_mem_align (mem
, BITS_PER_WORD
);
6492 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
6496 /* Save FP registers if needed. */
6497 if (DEFAULT_ABI
== ABI_V4
6498 && TARGET_HARD_FLOAT
&& TARGET_FPRS
6500 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
6501 && cfun
->va_list_fpr_size
)
6503 int fregno
= next_cum
.fregno
, nregs
;
6504 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
6505 rtx lab
= gen_label_rtx ();
6506 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
6507 * UNITS_PER_FP_WORD
);
6510 (gen_rtx_SET (VOIDmode
,
6512 gen_rtx_IF_THEN_ELSE (VOIDmode
,
6513 gen_rtx_NE (VOIDmode
, cr1
,
6515 gen_rtx_LABEL_REF (VOIDmode
, lab
),
6519 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
6520 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
6522 mem
= gen_rtx_MEM (DFmode
, plus_constant (save_area
, off
));
6523 MEM_NOTRAP_P (mem
) = 1;
6524 set_mem_alias_set (mem
, set
);
6525 set_mem_align (mem
, GET_MODE_ALIGNMENT (DFmode
));
6526 emit_move_insn (mem
, gen_rtx_REG (DFmode
, fregno
));
6533 /* Create the va_list data type. */
6536 rs6000_build_builtin_va_list (void)
6538 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
6540 /* For AIX, prefer 'char *' because that's what the system
6541 header files like. */
6542 if (DEFAULT_ABI
!= ABI_V4
)
6543 return build_pointer_type (char_type_node
);
6545 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6546 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6548 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gpr"),
6549 unsigned_char_type_node
);
6550 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fpr"),
6551 unsigned_char_type_node
);
6552 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6554 f_res
= build_decl (FIELD_DECL
, get_identifier ("reserved"),
6555 short_unsigned_type_node
);
6556 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
6558 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
6561 va_list_gpr_counter_field
= f_gpr
;
6562 va_list_fpr_counter_field
= f_fpr
;
6564 DECL_FIELD_CONTEXT (f_gpr
) = record
;
6565 DECL_FIELD_CONTEXT (f_fpr
) = record
;
6566 DECL_FIELD_CONTEXT (f_res
) = record
;
6567 DECL_FIELD_CONTEXT (f_ovf
) = record
;
6568 DECL_FIELD_CONTEXT (f_sav
) = record
;
6570 TREE_CHAIN (record
) = type_decl
;
6571 TYPE_NAME (record
) = type_decl
;
6572 TYPE_FIELDS (record
) = f_gpr
;
6573 TREE_CHAIN (f_gpr
) = f_fpr
;
6574 TREE_CHAIN (f_fpr
) = f_res
;
6575 TREE_CHAIN (f_res
) = f_ovf
;
6576 TREE_CHAIN (f_ovf
) = f_sav
;
6578 layout_type (record
);
6580 /* The correct type is an array type of one element. */
6581 return build_array_type (record
, build_index_type (size_zero_node
));
6584 /* Implement va_start. */
6587 rs6000_va_start (tree valist
, rtx nextarg
)
6589 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
6590 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6591 tree gpr
, fpr
, ovf
, sav
, t
;
6593 /* Only SVR4 needs something special. */
6594 if (DEFAULT_ABI
!= ABI_V4
)
6596 std_expand_builtin_va_start (valist
, nextarg
);
6600 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6601 f_fpr
= TREE_CHAIN (f_gpr
);
6602 f_res
= TREE_CHAIN (f_fpr
);
6603 f_ovf
= TREE_CHAIN (f_res
);
6604 f_sav
= TREE_CHAIN (f_ovf
);
6606 valist
= build_va_arg_indirect_ref (valist
);
6607 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6608 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
6609 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
6610 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
6612 /* Count number of gp and fp argument registers used. */
6613 words
= current_function_args_info
.words
;
6614 n_gpr
= MIN (current_function_args_info
.sysv_gregno
- GP_ARG_MIN_REG
,
6616 n_fpr
= MIN (current_function_args_info
.fregno
- FP_ARG_MIN_REG
,
6619 if (TARGET_DEBUG_ARG
)
6620 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
6621 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
6622 words
, n_gpr
, n_fpr
);
6624 if (cfun
->va_list_gpr_size
)
6626 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (gpr
), gpr
,
6627 build_int_cst (NULL_TREE
, n_gpr
));
6628 TREE_SIDE_EFFECTS (t
) = 1;
6629 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6632 if (cfun
->va_list_fpr_size
)
6634 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (fpr
), fpr
,
6635 build_int_cst (NULL_TREE
, n_fpr
));
6636 TREE_SIDE_EFFECTS (t
) = 1;
6637 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6640 /* Find the overflow area. */
6641 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
6643 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
,
6644 size_int (words
* UNITS_PER_WORD
));
6645 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovf
), ovf
, t
);
6646 TREE_SIDE_EFFECTS (t
) = 1;
6647 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6649 /* If there were no va_arg invocations, don't set up the register
6651 if (!cfun
->va_list_gpr_size
6652 && !cfun
->va_list_fpr_size
6653 && n_gpr
< GP_ARG_NUM_REG
6654 && n_fpr
< FP_ARG_V4_MAX_REG
)
6657 /* Find the register save area. */
6658 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
6659 if (cfun
->machine
->varargs_save_offset
)
6660 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
6661 size_int (cfun
->machine
->varargs_save_offset
));
6662 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (sav
), sav
, t
);
6663 TREE_SIDE_EFFECTS (t
) = 1;
6664 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6667 /* Implement va_arg. */
6670 rs6000_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
6672 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
6673 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
6674 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
6675 tree lab_false
, lab_over
, addr
;
6677 tree ptrtype
= build_pointer_type (type
);
6680 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6682 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
6683 return build_va_arg_indirect_ref (t
);
6686 if (DEFAULT_ABI
!= ABI_V4
)
6688 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
6690 tree elem_type
= TREE_TYPE (type
);
6691 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
6692 int elem_size
= GET_MODE_SIZE (elem_mode
);
6694 if (elem_size
< UNITS_PER_WORD
)
6696 tree real_part
, imag_part
;
6697 tree post
= NULL_TREE
;
6699 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6701 /* Copy the value into a temporary, lest the formal temporary
6702 be reused out from under us. */
6703 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
6704 append_to_statement_list (post
, pre_p
);
6706 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
6709 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
6713 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6716 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
6717 f_fpr
= TREE_CHAIN (f_gpr
);
6718 f_res
= TREE_CHAIN (f_fpr
);
6719 f_ovf
= TREE_CHAIN (f_res
);
6720 f_sav
= TREE_CHAIN (f_ovf
);
6722 valist
= build_va_arg_indirect_ref (valist
);
6723 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
6724 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
6725 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
6726 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
6728 size
= int_size_in_bytes (type
);
6729 rsize
= (size
+ 3) / 4;
6732 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
6733 && (TYPE_MODE (type
) == SFmode
6734 || TYPE_MODE (type
) == DFmode
6735 || TYPE_MODE (type
) == TFmode
6736 || TYPE_MODE (type
) == SDmode
6737 || TYPE_MODE (type
) == DDmode
6738 || TYPE_MODE (type
) == TDmode
))
6740 /* FP args go in FP registers, if present. */
6742 n_reg
= (size
+ 7) / 8;
6745 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
6750 /* Otherwise into GP registers. */
6759 /* Pull the value out of the saved registers.... */
6762 addr
= create_tmp_var (ptr_type_node
, "addr");
6763 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
6765 /* AltiVec vectors never go in registers when -mabi=altivec. */
6766 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
6770 lab_false
= create_artificial_label ();
6771 lab_over
= create_artificial_label ();
6773 /* Long long and SPE vectors are aligned in the registers.
6774 As are any other 2 gpr item such as complex int due to a
6775 historical mistake. */
6777 if (n_reg
== 2 && reg
== gpr
)
6780 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), reg
,
6781 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
6782 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
, u
);
6784 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6785 reg number is 0 for f1, so we want to make it odd. */
6786 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
6789 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), reg
, size_int (1));
6790 u
= build2 (MODIFY_EXPR
, void_type_node
, reg
, t
);
6793 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
6794 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
6795 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
6796 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
6797 gimplify_and_add (t
, pre_p
);
6801 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
, size_int (sav_ofs
));
6803 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
6804 build_int_cst (TREE_TYPE (reg
), n_reg
));
6805 u
= fold_convert (sizetype
, u
);
6806 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
6807 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, u
);
6809 /* _Decimal32 varargs are located in the second word of the 64-bit
6810 FP register for 32-bit binaries. */
6811 if (!TARGET_POWERPC64
&& TYPE_MODE (type
) == SDmode
)
6812 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
6814 t
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, addr
, t
);
6815 gimplify_and_add (t
, pre_p
);
6817 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
6818 gimplify_and_add (t
, pre_p
);
6820 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
6821 append_to_statement_list (t
, pre_p
);
6823 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
6825 /* Ensure that we don't find any more args in regs.
6826 Alignment has taken care of for special cases. */
6827 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (reg
), reg
, size_int (8));
6828 gimplify_and_add (t
, pre_p
);
6832 /* ... otherwise out of the overflow area. */
6834 /* Care for on-stack alignment if needed. */
6838 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (align
- 1));
6839 t
= fold_convert (sizetype
, t
);
6840 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
6842 t
= fold_convert (TREE_TYPE (ovf
), t
);
6844 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
6846 u
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, addr
, t
);
6847 gimplify_and_add (u
, pre_p
);
6849 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, size_int (size
));
6850 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovf
), ovf
, t
);
6851 gimplify_and_add (t
, pre_p
);
6855 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
6856 append_to_statement_list (t
, pre_p
);
6859 if (STRICT_ALIGNMENT
6860 && (TYPE_ALIGN (type
)
6861 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
6863 /* The value (of type complex double, for example) may not be
6864 aligned in memory in the saved registers, so copy via a
6865 temporary. (This is the same code as used for SPARC.) */
6866 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6867 tree dest_addr
= build_fold_addr_expr (tmp
);
6869 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
6870 3, dest_addr
, addr
, size_int (rsize
* 4));
6872 gimplify_and_add (copy
, pre_p
);
6876 addr
= fold_convert (ptrtype
, addr
);
6877 return build_va_arg_indirect_ref (addr
);
6883 def_builtin (int mask
, const char *name
, tree type
, int code
)
6885 if ((mask
& target_flags
) || TARGET_PAIRED_FLOAT
)
6887 if (rs6000_builtin_decls
[code
])
6890 rs6000_builtin_decls
[code
] =
6891 add_builtin_function (name
, type
, code
, BUILT_IN_MD
,
6896 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6898 static const struct builtin_description bdesc_3arg
[] =
6900 { MASK_ALTIVEC
, CODE_FOR_altivec_vmaddfp
, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP
},
6901 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhaddshs
, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS
},
6902 { MASK_ALTIVEC
, CODE_FOR_altivec_vmhraddshs
, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS
},
6903 { MASK_ALTIVEC
, CODE_FOR_altivec_vmladduhm
, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM
},
6904 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumubm
, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM
},
6905 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsummbm
, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM
},
6906 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhm
, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM
},
6907 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshm
, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM
},
6908 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumuhs
, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS
},
6909 { MASK_ALTIVEC
, CODE_FOR_altivec_vmsumshs
, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS
},
6910 { MASK_ALTIVEC
, CODE_FOR_altivec_vnmsubfp
, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP
},
6911 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4sf
, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF
},
6912 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v4si
, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI
},
6913 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v8hi
, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI
},
6914 { MASK_ALTIVEC
, CODE_FOR_altivec_vperm_v16qi
, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI
},
6915 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4sf
, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF
},
6916 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v4si
, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI
},
6917 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v8hi
, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI
},
6918 { MASK_ALTIVEC
, CODE_FOR_altivec_vsel_v16qi
, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI
},
6919 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v16qi
, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI
},
6920 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v8hi
, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI
},
6921 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4si
, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI
},
6922 { MASK_ALTIVEC
, CODE_FOR_altivec_vsldoi_v4sf
, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF
},
6924 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD
},
6925 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS
},
6926 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD
},
6927 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS
},
6928 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM
},
6929 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM
},
6930 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM
},
6931 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM
},
6932 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM
},
6933 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS
},
6934 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS
},
6935 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS
},
6936 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB
},
6937 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM
},
6938 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL
},
6940 { 0, CODE_FOR_paired_msub
, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB
},
6941 { 0, CODE_FOR_paired_madd
, "__builtin_paired_madd", PAIRED_BUILTIN_MADD
},
6942 { 0, CODE_FOR_paired_madds0
, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0
},
6943 { 0, CODE_FOR_paired_madds1
, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1
},
6944 { 0, CODE_FOR_paired_nmsub
, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB
},
6945 { 0, CODE_FOR_paired_nmadd
, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD
},
6946 { 0, CODE_FOR_paired_sum0
, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0
},
6947 { 0, CODE_FOR_paired_sum1
, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1
},
6948 { 0, CODE_FOR_selv2sf4
, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4
},
6951 /* DST operations: void foo (void *, const int, const char). */
6953 static const struct builtin_description bdesc_dst
[] =
6955 { MASK_ALTIVEC
, CODE_FOR_altivec_dst
, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST
},
6956 { MASK_ALTIVEC
, CODE_FOR_altivec_dstt
, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT
},
6957 { MASK_ALTIVEC
, CODE_FOR_altivec_dstst
, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST
},
6958 { MASK_ALTIVEC
, CODE_FOR_altivec_dststt
, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT
},
6960 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST
},
6961 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT
},
6962 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST
},
6963 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT
}
6966 /* Simple binary operations: VECc = foo (VECa, VECb). */
6968 static struct builtin_description bdesc_2arg
[] =
6970 { MASK_ALTIVEC
, CODE_FOR_addv16qi3
, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM
},
6971 { MASK_ALTIVEC
, CODE_FOR_addv8hi3
, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM
},
6972 { MASK_ALTIVEC
, CODE_FOR_addv4si3
, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM
},
6973 { MASK_ALTIVEC
, CODE_FOR_addv4sf3
, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP
},
6974 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddcuw
, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW
},
6975 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddubs
, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS
},
6976 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsbs
, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS
},
6977 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduhs
, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS
},
6978 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddshs
, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS
},
6979 { MASK_ALTIVEC
, CODE_FOR_altivec_vadduws
, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS
},
6980 { MASK_ALTIVEC
, CODE_FOR_altivec_vaddsws
, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS
},
6981 { MASK_ALTIVEC
, CODE_FOR_andv4si3
, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND
},
6982 { MASK_ALTIVEC
, CODE_FOR_andcv4si3
, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC
},
6983 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgub
, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB
},
6984 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsb
, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB
},
6985 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguh
, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH
},
6986 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsh
, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH
},
6987 { MASK_ALTIVEC
, CODE_FOR_altivec_vavguw
, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW
},
6988 { MASK_ALTIVEC
, CODE_FOR_altivec_vavgsw
, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW
},
6989 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfux
, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX
},
6990 { MASK_ALTIVEC
, CODE_FOR_altivec_vcfsx
, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX
},
6991 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpbfp
, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP
},
6992 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequb
, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB
},
6993 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequh
, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH
},
6994 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpequw
, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW
},
6995 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpeqfp
, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP
},
6996 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgefp
, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP
},
6997 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtub
, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB
},
6998 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsb
, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB
},
6999 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuh
, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH
},
7000 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsh
, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH
},
7001 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtuw
, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW
},
7002 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtsw
, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW
},
7003 { MASK_ALTIVEC
, CODE_FOR_altivec_vcmpgtfp
, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP
},
7004 { MASK_ALTIVEC
, CODE_FOR_altivec_vctsxs
, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS
},
7005 { MASK_ALTIVEC
, CODE_FOR_altivec_vctuxs
, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS
},
7006 { MASK_ALTIVEC
, CODE_FOR_umaxv16qi3
, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB
},
7007 { MASK_ALTIVEC
, CODE_FOR_smaxv16qi3
, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB
},
7008 { MASK_ALTIVEC
, CODE_FOR_umaxv8hi3
, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH
},
7009 { MASK_ALTIVEC
, CODE_FOR_smaxv8hi3
, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH
},
7010 { MASK_ALTIVEC
, CODE_FOR_umaxv4si3
, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW
},
7011 { MASK_ALTIVEC
, CODE_FOR_smaxv4si3
, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW
},
7012 { MASK_ALTIVEC
, CODE_FOR_smaxv4sf3
, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP
},
7013 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghb
, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB
},
7014 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghh
, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH
},
7015 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrghw
, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW
},
7016 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglb
, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB
},
7017 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglh
, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH
},
7018 { MASK_ALTIVEC
, CODE_FOR_altivec_vmrglw
, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW
},
7019 { MASK_ALTIVEC
, CODE_FOR_uminv16qi3
, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB
},
7020 { MASK_ALTIVEC
, CODE_FOR_sminv16qi3
, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB
},
7021 { MASK_ALTIVEC
, CODE_FOR_uminv8hi3
, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH
},
7022 { MASK_ALTIVEC
, CODE_FOR_sminv8hi3
, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH
},
7023 { MASK_ALTIVEC
, CODE_FOR_uminv4si3
, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW
},
7024 { MASK_ALTIVEC
, CODE_FOR_sminv4si3
, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW
},
7025 { MASK_ALTIVEC
, CODE_FOR_sminv4sf3
, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP
},
7026 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleub
, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB
},
7027 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesb
, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB
},
7028 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuleuh
, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH
},
7029 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulesh
, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH
},
7030 { MASK_ALTIVEC
, CODE_FOR_altivec_vmuloub
, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB
},
7031 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosb
, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB
},
7032 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulouh
, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH
},
7033 { MASK_ALTIVEC
, CODE_FOR_altivec_vmulosh
, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH
},
7034 { MASK_ALTIVEC
, CODE_FOR_altivec_norv4si3
, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR
},
7035 { MASK_ALTIVEC
, CODE_FOR_iorv4si3
, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR
},
7036 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM
},
7037 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM
},
7038 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkpx
, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX
},
7039 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshss
, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS
},
7040 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswss
, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS
},
7041 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhus
, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS
},
7042 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkshus
, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS
},
7043 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwus
, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS
},
7044 { MASK_ALTIVEC
, CODE_FOR_altivec_vpkswus
, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS
},
7045 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlb
, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB
},
7046 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlh
, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH
},
7047 { MASK_ALTIVEC
, CODE_FOR_altivec_vrlw
, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW
},
7048 { MASK_ALTIVEC
, CODE_FOR_altivec_vslb
, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB
},
7049 { MASK_ALTIVEC
, CODE_FOR_altivec_vslh
, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH
},
7050 { MASK_ALTIVEC
, CODE_FOR_altivec_vslw
, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW
},
7051 { MASK_ALTIVEC
, CODE_FOR_altivec_vsl
, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL
},
7052 { MASK_ALTIVEC
, CODE_FOR_altivec_vslo
, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO
},
7053 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltb
, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB
},
7054 { MASK_ALTIVEC
, CODE_FOR_altivec_vsplth
, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH
},
7055 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltw
, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW
},
7056 { MASK_ALTIVEC
, CODE_FOR_lshrv16qi3
, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB
},
7057 { MASK_ALTIVEC
, CODE_FOR_lshrv8hi3
, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH
},
7058 { MASK_ALTIVEC
, CODE_FOR_lshrv4si3
, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW
},
7059 { MASK_ALTIVEC
, CODE_FOR_ashrv16qi3
, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB
},
7060 { MASK_ALTIVEC
, CODE_FOR_ashrv8hi3
, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH
},
7061 { MASK_ALTIVEC
, CODE_FOR_ashrv4si3
, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW
},
7062 { MASK_ALTIVEC
, CODE_FOR_altivec_vsr
, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR
},
7063 { MASK_ALTIVEC
, CODE_FOR_altivec_vsro
, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO
},
7064 { MASK_ALTIVEC
, CODE_FOR_subv16qi3
, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM
},
7065 { MASK_ALTIVEC
, CODE_FOR_subv8hi3
, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM
},
7066 { MASK_ALTIVEC
, CODE_FOR_subv4si3
, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM
},
7067 { MASK_ALTIVEC
, CODE_FOR_subv4sf3
, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP
},
7068 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubcuw
, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW
},
7069 { MASK_ALTIVEC
, CODE_FOR_altivec_vsububs
, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS
},
7070 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsbs
, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS
},
7071 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuhs
, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS
},
7072 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubshs
, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS
},
7073 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubuws
, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS
},
7074 { MASK_ALTIVEC
, CODE_FOR_altivec_vsubsws
, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS
},
7075 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4ubs
, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS
},
7076 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4sbs
, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS
},
7077 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum4shs
, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS
},
7078 { MASK_ALTIVEC
, CODE_FOR_altivec_vsum2sws
, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS
},
7079 { MASK_ALTIVEC
, CODE_FOR_altivec_vsumsws
, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS
},
7080 { MASK_ALTIVEC
, CODE_FOR_xorv4si3
, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR
},
7082 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD
},
7083 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP
},
7084 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM
},
7085 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM
},
7086 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM
},
7087 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC
},
7088 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS
},
7089 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS
},
7090 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS
},
7091 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS
},
7092 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS
},
7093 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS
},
7094 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS
},
7095 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND
},
7096 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC
},
7097 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG
},
7098 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW
},
7099 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW
},
7100 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH
},
7101 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH
},
7102 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB
},
7103 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB
},
7104 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB
},
7105 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ
},
7106 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP
},
7107 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW
},
7108 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH
},
7109 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB
},
7110 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE
},
7111 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT
},
7112 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP
},
7113 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW
},
7114 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW
},
7115 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH
},
7116 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH
},
7117 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB
},
7118 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB
},
7119 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE
},
7120 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT
},
7121 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX
},
7122 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP
},
7123 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW
},
7124 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW
},
7125 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH
},
7126 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH
},
7127 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB
},
7128 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB
},
7129 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH
},
7130 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW
},
7131 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH
},
7132 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB
},
7133 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL
},
7134 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW
},
7135 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH
},
7136 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB
},
7137 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN
},
7138 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP
},
7139 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW
},
7140 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW
},
7141 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH
},
7142 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH
},
7143 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB
},
7144 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB
},
7145 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE
},
7146 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB
},
7147 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB
},
7148 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH
},
7149 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH
},
7150 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO
},
7151 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH
},
7152 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH
},
7153 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB
},
7154 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB
},
7155 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR
},
7156 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR
},
7157 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK
},
7158 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM
},
7159 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM
},
7160 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX
},
7161 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS
},
7162 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS
},
7163 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS
},
7164 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS
},
7165 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS
},
7166 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU
},
7167 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS
},
7168 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS
},
7169 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL
},
7170 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW
},
7171 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH
},
7172 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB
},
7173 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL
},
7174 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW
},
7175 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH
},
7176 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB
},
7177 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL
},
7178 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO
},
7179 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR
},
7180 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW
},
7181 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH
},
7182 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB
},
7183 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA
},
7184 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW
},
7185 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH
},
7186 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB
},
7187 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL
},
7188 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO
},
7189 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB
},
7190 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP
},
7191 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM
},
7192 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM
},
7193 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM
},
7194 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC
},
7195 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS
},
7196 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS
},
7197 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS
},
7198 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS
},
7199 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS
},
7200 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS
},
7201 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS
},
7202 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S
},
7203 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS
},
7204 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS
},
7205 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS
},
7206 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S
},
7207 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS
},
7208 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR
},
7210 { 0, CODE_FOR_divv2sf3
, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3
},
7211 { 0, CODE_FOR_addv2sf3
, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3
},
7212 { 0, CODE_FOR_subv2sf3
, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3
},
7213 { 0, CODE_FOR_mulv2sf3
, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3
},
7214 { 0, CODE_FOR_paired_muls0
, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0
},
7215 { 0, CODE_FOR_paired_muls1
, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1
},
7216 { 0, CODE_FOR_paired_merge00
, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00
},
7217 { 0, CODE_FOR_paired_merge01
, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01
},
7218 { 0, CODE_FOR_paired_merge10
, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10
},
7219 { 0, CODE_FOR_paired_merge11
, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11
},
7221 /* Place holder, leave as first spe builtin. */
7222 { 0, CODE_FOR_spe_evaddw
, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW
},
7223 { 0, CODE_FOR_spe_evand
, "__builtin_spe_evand", SPE_BUILTIN_EVAND
},
7224 { 0, CODE_FOR_spe_evandc
, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC
},
7225 { 0, CODE_FOR_spe_evdivws
, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS
},
7226 { 0, CODE_FOR_spe_evdivwu
, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU
},
7227 { 0, CODE_FOR_spe_eveqv
, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV
},
7228 { 0, CODE_FOR_spe_evfsadd
, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD
},
7229 { 0, CODE_FOR_spe_evfsdiv
, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV
},
7230 { 0, CODE_FOR_spe_evfsmul
, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL
},
7231 { 0, CODE_FOR_spe_evfssub
, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB
},
7232 { 0, CODE_FOR_spe_evmergehi
, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI
},
7233 { 0, CODE_FOR_spe_evmergehilo
, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO
},
7234 { 0, CODE_FOR_spe_evmergelo
, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO
},
7235 { 0, CODE_FOR_spe_evmergelohi
, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI
},
7236 { 0, CODE_FOR_spe_evmhegsmfaa
, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA
},
7237 { 0, CODE_FOR_spe_evmhegsmfan
, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN
},
7238 { 0, CODE_FOR_spe_evmhegsmiaa
, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA
},
7239 { 0, CODE_FOR_spe_evmhegsmian
, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN
},
7240 { 0, CODE_FOR_spe_evmhegumiaa
, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA
},
7241 { 0, CODE_FOR_spe_evmhegumian
, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN
},
7242 { 0, CODE_FOR_spe_evmhesmf
, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF
},
7243 { 0, CODE_FOR_spe_evmhesmfa
, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA
},
7244 { 0, CODE_FOR_spe_evmhesmfaaw
, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW
},
7245 { 0, CODE_FOR_spe_evmhesmfanw
, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW
},
7246 { 0, CODE_FOR_spe_evmhesmi
, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI
},
7247 { 0, CODE_FOR_spe_evmhesmia
, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA
},
7248 { 0, CODE_FOR_spe_evmhesmiaaw
, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW
},
7249 { 0, CODE_FOR_spe_evmhesmianw
, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW
},
7250 { 0, CODE_FOR_spe_evmhessf
, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF
},
7251 { 0, CODE_FOR_spe_evmhessfa
, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA
},
7252 { 0, CODE_FOR_spe_evmhessfaaw
, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW
},
7253 { 0, CODE_FOR_spe_evmhessfanw
, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW
},
7254 { 0, CODE_FOR_spe_evmhessiaaw
, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW
},
7255 { 0, CODE_FOR_spe_evmhessianw
, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW
},
7256 { 0, CODE_FOR_spe_evmheumi
, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI
},
7257 { 0, CODE_FOR_spe_evmheumia
, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA
},
7258 { 0, CODE_FOR_spe_evmheumiaaw
, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW
},
7259 { 0, CODE_FOR_spe_evmheumianw
, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW
},
7260 { 0, CODE_FOR_spe_evmheusiaaw
, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW
},
7261 { 0, CODE_FOR_spe_evmheusianw
, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW
},
7262 { 0, CODE_FOR_spe_evmhogsmfaa
, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA
},
7263 { 0, CODE_FOR_spe_evmhogsmfan
, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN
},
7264 { 0, CODE_FOR_spe_evmhogsmiaa
, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA
},
7265 { 0, CODE_FOR_spe_evmhogsmian
, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN
},
7266 { 0, CODE_FOR_spe_evmhogumiaa
, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA
},
7267 { 0, CODE_FOR_spe_evmhogumian
, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN
},
7268 { 0, CODE_FOR_spe_evmhosmf
, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF
},
7269 { 0, CODE_FOR_spe_evmhosmfa
, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA
},
7270 { 0, CODE_FOR_spe_evmhosmfaaw
, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW
},
7271 { 0, CODE_FOR_spe_evmhosmfanw
, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW
},
7272 { 0, CODE_FOR_spe_evmhosmi
, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI
},
7273 { 0, CODE_FOR_spe_evmhosmia
, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA
},
7274 { 0, CODE_FOR_spe_evmhosmiaaw
, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW
},
7275 { 0, CODE_FOR_spe_evmhosmianw
, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW
},
7276 { 0, CODE_FOR_spe_evmhossf
, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF
},
7277 { 0, CODE_FOR_spe_evmhossfa
, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA
},
7278 { 0, CODE_FOR_spe_evmhossfaaw
, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW
},
7279 { 0, CODE_FOR_spe_evmhossfanw
, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW
},
7280 { 0, CODE_FOR_spe_evmhossiaaw
, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW
},
7281 { 0, CODE_FOR_spe_evmhossianw
, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW
},
7282 { 0, CODE_FOR_spe_evmhoumi
, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI
},
7283 { 0, CODE_FOR_spe_evmhoumia
, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA
},
7284 { 0, CODE_FOR_spe_evmhoumiaaw
, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW
},
7285 { 0, CODE_FOR_spe_evmhoumianw
, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW
},
7286 { 0, CODE_FOR_spe_evmhousiaaw
, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW
},
7287 { 0, CODE_FOR_spe_evmhousianw
, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW
},
7288 { 0, CODE_FOR_spe_evmwhsmf
, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF
},
7289 { 0, CODE_FOR_spe_evmwhsmfa
, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA
},
7290 { 0, CODE_FOR_spe_evmwhsmi
, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI
},
7291 { 0, CODE_FOR_spe_evmwhsmia
, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA
},
7292 { 0, CODE_FOR_spe_evmwhssf
, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF
},
7293 { 0, CODE_FOR_spe_evmwhssfa
, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA
},
7294 { 0, CODE_FOR_spe_evmwhumi
, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI
},
7295 { 0, CODE_FOR_spe_evmwhumia
, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA
},
7296 { 0, CODE_FOR_spe_evmwlsmiaaw
, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW
},
7297 { 0, CODE_FOR_spe_evmwlsmianw
, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW
},
7298 { 0, CODE_FOR_spe_evmwlssiaaw
, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW
},
7299 { 0, CODE_FOR_spe_evmwlssianw
, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW
},
7300 { 0, CODE_FOR_spe_evmwlumi
, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI
},
7301 { 0, CODE_FOR_spe_evmwlumia
, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA
},
7302 { 0, CODE_FOR_spe_evmwlumiaaw
, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW
},
7303 { 0, CODE_FOR_spe_evmwlumianw
, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW
},
7304 { 0, CODE_FOR_spe_evmwlusiaaw
, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW
},
7305 { 0, CODE_FOR_spe_evmwlusianw
, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW
},
7306 { 0, CODE_FOR_spe_evmwsmf
, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF
},
7307 { 0, CODE_FOR_spe_evmwsmfa
, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA
},
7308 { 0, CODE_FOR_spe_evmwsmfaa
, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA
},
7309 { 0, CODE_FOR_spe_evmwsmfan
, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN
},
7310 { 0, CODE_FOR_spe_evmwsmi
, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI
},
7311 { 0, CODE_FOR_spe_evmwsmia
, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA
},
7312 { 0, CODE_FOR_spe_evmwsmiaa
, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA
},
7313 { 0, CODE_FOR_spe_evmwsmian
, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN
},
7314 { 0, CODE_FOR_spe_evmwssf
, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF
},
7315 { 0, CODE_FOR_spe_evmwssfa
, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA
},
7316 { 0, CODE_FOR_spe_evmwssfaa
, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA
},
7317 { 0, CODE_FOR_spe_evmwssfan
, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN
},
7318 { 0, CODE_FOR_spe_evmwumi
, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI
},
7319 { 0, CODE_FOR_spe_evmwumia
, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA
},
7320 { 0, CODE_FOR_spe_evmwumiaa
, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA
},
7321 { 0, CODE_FOR_spe_evmwumian
, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN
},
7322 { 0, CODE_FOR_spe_evnand
, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND
},
7323 { 0, CODE_FOR_spe_evnor
, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR
},
7324 { 0, CODE_FOR_spe_evor
, "__builtin_spe_evor", SPE_BUILTIN_EVOR
},
7325 { 0, CODE_FOR_spe_evorc
, "__builtin_spe_evorc", SPE_BUILTIN_EVORC
},
7326 { 0, CODE_FOR_spe_evrlw
, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW
},
7327 { 0, CODE_FOR_spe_evslw
, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW
},
7328 { 0, CODE_FOR_spe_evsrws
, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS
},
7329 { 0, CODE_FOR_spe_evsrwu
, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU
},
7330 { 0, CODE_FOR_spe_evsubfw
, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW
},
7332 /* SPE binary operations expecting a 5-bit unsigned literal. */
7333 { 0, CODE_FOR_spe_evaddiw
, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW
},
7335 { 0, CODE_FOR_spe_evrlwi
, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI
},
7336 { 0, CODE_FOR_spe_evslwi
, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI
},
7337 { 0, CODE_FOR_spe_evsrwis
, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS
},
7338 { 0, CODE_FOR_spe_evsrwiu
, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU
},
7339 { 0, CODE_FOR_spe_evsubifw
, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW
},
7340 { 0, CODE_FOR_spe_evmwhssfaa
, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA
},
7341 { 0, CODE_FOR_spe_evmwhssmaa
, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA
},
7342 { 0, CODE_FOR_spe_evmwhsmfaa
, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA
},
7343 { 0, CODE_FOR_spe_evmwhsmiaa
, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA
},
7344 { 0, CODE_FOR_spe_evmwhusiaa
, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA
},
7345 { 0, CODE_FOR_spe_evmwhumiaa
, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA
},
7346 { 0, CODE_FOR_spe_evmwhssfan
, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN
},
7347 { 0, CODE_FOR_spe_evmwhssian
, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN
},
7348 { 0, CODE_FOR_spe_evmwhsmfan
, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN
},
7349 { 0, CODE_FOR_spe_evmwhsmian
, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN
},
7350 { 0, CODE_FOR_spe_evmwhusian
, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN
},
7351 { 0, CODE_FOR_spe_evmwhumian
, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN
},
7352 { 0, CODE_FOR_spe_evmwhgssfaa
, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA
},
7353 { 0, CODE_FOR_spe_evmwhgsmfaa
, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA
},
7354 { 0, CODE_FOR_spe_evmwhgsmiaa
, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA
},
7355 { 0, CODE_FOR_spe_evmwhgumiaa
, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA
},
7356 { 0, CODE_FOR_spe_evmwhgssfan
, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN
},
7357 { 0, CODE_FOR_spe_evmwhgsmfan
, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN
},
7358 { 0, CODE_FOR_spe_evmwhgsmian
, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN
},
7359 { 0, CODE_FOR_spe_evmwhgumian
, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN
},
7360 { 0, CODE_FOR_spe_brinc
, "__builtin_spe_brinc", SPE_BUILTIN_BRINC
},
7362 /* Place-holder. Leave as last binary SPE builtin. */
7363 { 0, CODE_FOR_xorv2si3
, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR
}
7366 /* AltiVec predicates. */
7368 struct builtin_description_predicates
7370 const unsigned int mask
;
7371 const enum insn_code icode
;
7373 const char *const name
;
7374 const enum rs6000_builtins code
;
7377 static const struct builtin_description_predicates bdesc_altivec_preds
[] =
7379 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P
},
7380 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P
},
7381 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P
},
7382 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4sf
, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P
},
7383 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P
},
7384 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P
},
7385 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v4si
, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P
},
7386 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P
},
7387 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P
},
7388 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v8hi
, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P
},
7389 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P
},
7390 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P
},
7391 { MASK_ALTIVEC
, CODE_FOR_altivec_predicate_v16qi
, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P
},
7393 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P
},
7394 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P
},
7395 { MASK_ALTIVEC
, 0, NULL
, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P
}
7398 /* SPE predicates. */
7399 static struct builtin_description bdesc_spe_predicates
[] =
7401 /* Place-holder. Leave as first. */
7402 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ
},
7403 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS
},
7404 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU
},
7405 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS
},
7406 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU
},
7407 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ
},
7408 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT
},
7409 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT
},
7410 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ
},
7411 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT
},
7412 /* Place-holder. Leave as last. */
7413 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT
},
7416 /* SPE evsel predicates. */
7417 static struct builtin_description bdesc_spe_evsel
[] =
7419 /* Place-holder. Leave as first. */
7420 { 0, CODE_FOR_spe_evcmpgts
, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS
},
7421 { 0, CODE_FOR_spe_evcmpgtu
, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU
},
7422 { 0, CODE_FOR_spe_evcmplts
, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS
},
7423 { 0, CODE_FOR_spe_evcmpltu
, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU
},
7424 { 0, CODE_FOR_spe_evcmpeq
, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ
},
7425 { 0, CODE_FOR_spe_evfscmpgt
, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT
},
7426 { 0, CODE_FOR_spe_evfscmplt
, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT
},
7427 { 0, CODE_FOR_spe_evfscmpeq
, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ
},
7428 { 0, CODE_FOR_spe_evfststgt
, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT
},
7429 { 0, CODE_FOR_spe_evfststlt
, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT
},
7430 /* Place-holder. Leave as last. */
7431 { 0, CODE_FOR_spe_evfststeq
, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ
},
7434 /* PAIRED predicates. */
7435 static const struct builtin_description bdesc_paired_preds
[] =
7437 /* Place-holder. Leave as first. */
7438 { 0, CODE_FOR_paired_cmpu0
, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0
},
7439 /* Place-holder. Leave as last. */
7440 { 0, CODE_FOR_paired_cmpu1
, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1
},
7443 /* ABS* operations. */
7445 static const struct builtin_description bdesc_abs
[] =
7447 { MASK_ALTIVEC
, CODE_FOR_absv4si2
, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI
},
7448 { MASK_ALTIVEC
, CODE_FOR_absv8hi2
, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI
},
7449 { MASK_ALTIVEC
, CODE_FOR_absv4sf2
, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF
},
7450 { MASK_ALTIVEC
, CODE_FOR_absv16qi2
, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI
},
7451 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v4si
, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI
},
7452 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v8hi
, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI
},
7453 { MASK_ALTIVEC
, CODE_FOR_altivec_abss_v16qi
, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI
}
7456 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7459 static struct builtin_description bdesc_1arg
[] =
7461 { MASK_ALTIVEC
, CODE_FOR_altivec_vexptefp
, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP
},
7462 { MASK_ALTIVEC
, CODE_FOR_altivec_vlogefp
, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP
},
7463 { MASK_ALTIVEC
, CODE_FOR_altivec_vrefp
, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP
},
7464 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfim
, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM
},
7465 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfin
, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN
},
7466 { MASK_ALTIVEC
, CODE_FOR_altivec_vrfip
, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP
},
7467 { MASK_ALTIVEC
, CODE_FOR_ftruncv4sf2
, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ
},
7468 { MASK_ALTIVEC
, CODE_FOR_altivec_vrsqrtefp
, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP
},
7469 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisb
, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB
},
7470 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltish
, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH
},
7471 { MASK_ALTIVEC
, CODE_FOR_altivec_vspltisw
, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW
},
7472 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsb
, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB
},
7473 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhpx
, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX
},
7474 { MASK_ALTIVEC
, CODE_FOR_altivec_vupkhsh
, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH
},
7475 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsb
, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB
},
7476 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklpx
, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX
},
7477 { MASK_ALTIVEC
, CODE_FOR_altivec_vupklsh
, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH
},
7479 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS
},
7480 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS
},
7481 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL
},
7482 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE
},
7483 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR
},
7484 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE
},
7485 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR
},
7486 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE
},
7487 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND
},
7488 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE
},
7489 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC
},
7490 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH
},
7491 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH
},
7492 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX
},
7493 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB
},
7494 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL
},
7495 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX
},
7496 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH
},
7497 { MASK_ALTIVEC
, CODE_FOR_nothing
, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB
},
7499 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7500 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7501 { 0, CODE_FOR_spe_evabs
, "__builtin_spe_evabs", SPE_BUILTIN_EVABS
},
7502 { 0, CODE_FOR_spe_evaddsmiaaw
, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW
},
7503 { 0, CODE_FOR_spe_evaddssiaaw
, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW
},
7504 { 0, CODE_FOR_spe_evaddumiaaw
, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW
},
7505 { 0, CODE_FOR_spe_evaddusiaaw
, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW
},
7506 { 0, CODE_FOR_spe_evcntlsw
, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW
},
7507 { 0, CODE_FOR_spe_evcntlzw
, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW
},
7508 { 0, CODE_FOR_spe_evextsb
, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB
},
7509 { 0, CODE_FOR_spe_evextsh
, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH
},
7510 { 0, CODE_FOR_spe_evfsabs
, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS
},
7511 { 0, CODE_FOR_spe_evfscfsf
, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF
},
7512 { 0, CODE_FOR_spe_evfscfsi
, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI
},
7513 { 0, CODE_FOR_spe_evfscfuf
, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF
},
7514 { 0, CODE_FOR_spe_evfscfui
, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI
},
7515 { 0, CODE_FOR_spe_evfsctsf
, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF
},
7516 { 0, CODE_FOR_spe_evfsctsi
, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI
},
7517 { 0, CODE_FOR_spe_evfsctsiz
, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ
},
7518 { 0, CODE_FOR_spe_evfsctuf
, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF
},
7519 { 0, CODE_FOR_spe_evfsctui
, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI
},
7520 { 0, CODE_FOR_spe_evfsctuiz
, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ
},
7521 { 0, CODE_FOR_spe_evfsnabs
, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS
},
7522 { 0, CODE_FOR_spe_evfsneg
, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG
},
7523 { 0, CODE_FOR_spe_evmra
, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA
},
7524 { 0, CODE_FOR_negv2si2
, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG
},
7525 { 0, CODE_FOR_spe_evrndw
, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW
},
7526 { 0, CODE_FOR_spe_evsubfsmiaaw
, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW
},
7527 { 0, CODE_FOR_spe_evsubfssiaaw
, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW
},
7528 { 0, CODE_FOR_spe_evsubfumiaaw
, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW
},
7530 /* Place-holder. Leave as last unary SPE builtin. */
7531 { 0, CODE_FOR_spe_evsubfusiaaw
, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW
},
7533 { 0, CODE_FOR_absv2sf2
, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2
},
7534 { 0, CODE_FOR_nabsv2sf2
, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2
},
7535 { 0, CODE_FOR_negv2sf2
, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2
},
7536 { 0, CODE_FOR_sqrtv2sf2
, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2
},
7537 { 0, CODE_FOR_resv2sf2
, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2
}
7541 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7544 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7545 rtx op0
= expand_normal (arg0
);
7546 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7547 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7549 if (icode
== CODE_FOR_nothing
)
7550 /* Builtin not supported on this processor. */
7553 /* If we got invalid arguments bail out before generating bad rtl. */
7554 if (arg0
== error_mark_node
)
7557 if (icode
== CODE_FOR_altivec_vspltisb
7558 || icode
== CODE_FOR_altivec_vspltish
7559 || icode
== CODE_FOR_altivec_vspltisw
7560 || icode
== CODE_FOR_spe_evsplatfi
7561 || icode
== CODE_FOR_spe_evsplati
)
7563 /* Only allow 5-bit *signed* literals. */
7564 if (GET_CODE (op0
) != CONST_INT
7565 || INTVAL (op0
) > 15
7566 || INTVAL (op0
) < -16)
7568 error ("argument 1 must be a 5-bit signed literal");
7574 || GET_MODE (target
) != tmode
7575 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7576 target
= gen_reg_rtx (tmode
);
7578 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7579 op0
= copy_to_mode_reg (mode0
, op0
);
7581 pat
= GEN_FCN (icode
) (target
, op0
);
7590 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
7592 rtx pat
, scratch1
, scratch2
;
7593 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7594 rtx op0
= expand_normal (arg0
);
7595 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7596 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7598 /* If we have invalid arguments, bail out before generating bad rtl. */
7599 if (arg0
== error_mark_node
)
7603 || GET_MODE (target
) != tmode
7604 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7605 target
= gen_reg_rtx (tmode
);
7607 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7608 op0
= copy_to_mode_reg (mode0
, op0
);
7610 scratch1
= gen_reg_rtx (mode0
);
7611 scratch2
= gen_reg_rtx (mode0
);
7613 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
7622 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7625 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7626 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7627 rtx op0
= expand_normal (arg0
);
7628 rtx op1
= expand_normal (arg1
);
7629 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7630 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7631 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7633 if (icode
== CODE_FOR_nothing
)
7634 /* Builtin not supported on this processor. */
7637 /* If we got invalid arguments bail out before generating bad rtl. */
7638 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7641 if (icode
== CODE_FOR_altivec_vcfux
7642 || icode
== CODE_FOR_altivec_vcfsx
7643 || icode
== CODE_FOR_altivec_vctsxs
7644 || icode
== CODE_FOR_altivec_vctuxs
7645 || icode
== CODE_FOR_altivec_vspltb
7646 || icode
== CODE_FOR_altivec_vsplth
7647 || icode
== CODE_FOR_altivec_vspltw
7648 || icode
== CODE_FOR_spe_evaddiw
7649 || icode
== CODE_FOR_spe_evldd
7650 || icode
== CODE_FOR_spe_evldh
7651 || icode
== CODE_FOR_spe_evldw
7652 || icode
== CODE_FOR_spe_evlhhesplat
7653 || icode
== CODE_FOR_spe_evlhhossplat
7654 || icode
== CODE_FOR_spe_evlhhousplat
7655 || icode
== CODE_FOR_spe_evlwhe
7656 || icode
== CODE_FOR_spe_evlwhos
7657 || icode
== CODE_FOR_spe_evlwhou
7658 || icode
== CODE_FOR_spe_evlwhsplat
7659 || icode
== CODE_FOR_spe_evlwwsplat
7660 || icode
== CODE_FOR_spe_evrlwi
7661 || icode
== CODE_FOR_spe_evslwi
7662 || icode
== CODE_FOR_spe_evsrwis
7663 || icode
== CODE_FOR_spe_evsubifw
7664 || icode
== CODE_FOR_spe_evsrwiu
)
7666 /* Only allow 5-bit unsigned literals. */
7668 if (TREE_CODE (arg1
) != INTEGER_CST
7669 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
7671 error ("argument 2 must be a 5-bit unsigned literal");
7677 || GET_MODE (target
) != tmode
7678 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7679 target
= gen_reg_rtx (tmode
);
7681 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7682 op0
= copy_to_mode_reg (mode0
, op0
);
7683 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7684 op1
= copy_to_mode_reg (mode1
, op1
);
7686 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
7695 altivec_expand_predicate_builtin (enum insn_code icode
, const char *opcode
,
7696 tree exp
, rtx target
)
7699 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
7700 tree arg0
= CALL_EXPR_ARG (exp
, 1);
7701 tree arg1
= CALL_EXPR_ARG (exp
, 2);
7702 rtx op0
= expand_normal (arg0
);
7703 rtx op1
= expand_normal (arg1
);
7704 enum machine_mode tmode
= SImode
;
7705 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7706 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7709 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
7711 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7715 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
7717 gcc_assert (mode0
== mode1
);
7719 /* If we have invalid arguments, bail out before generating bad rtl. */
7720 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7724 || GET_MODE (target
) != tmode
7725 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7726 target
= gen_reg_rtx (tmode
);
7728 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
7729 op0
= copy_to_mode_reg (mode0
, op0
);
7730 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
7731 op1
= copy_to_mode_reg (mode1
, op1
);
7733 scratch
= gen_reg_rtx (mode0
);
7735 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
,
7736 gen_rtx_SYMBOL_REF (Pmode
, opcode
));
7741 /* The vec_any* and vec_all* predicates use the same opcodes for two
7742 different operations, but the bits in CR6 will be different
7743 depending on what information we want. So we have to play tricks
7744 with CR6 to get the right bits out.
7746 If you think this is disgusting, look at the specs for the
7747 AltiVec predicates. */
7749 switch (cr6_form_int
)
7752 emit_insn (gen_cr6_test_for_zero (target
));
7755 emit_insn (gen_cr6_test_for_zero_reverse (target
));
7758 emit_insn (gen_cr6_test_for_lt (target
));
7761 emit_insn (gen_cr6_test_for_lt_reverse (target
));
7764 error ("argument 1 of __builtin_altivec_predicate is out of range");
7772 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
7775 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7776 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7777 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7778 enum machine_mode mode0
= Pmode
;
7779 enum machine_mode mode1
= Pmode
;
7780 rtx op0
= expand_normal (arg0
);
7781 rtx op1
= expand_normal (arg1
);
7783 if (icode
== CODE_FOR_nothing
)
7784 /* Builtin not supported on this processor. */
7787 /* If we got invalid arguments bail out before generating bad rtl. */
7788 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7792 || GET_MODE (target
) != tmode
7793 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7794 target
= gen_reg_rtx (tmode
);
7796 op1
= copy_to_mode_reg (mode1
, op1
);
7798 if (op0
== const0_rtx
)
7800 addr
= gen_rtx_MEM (tmode
, op1
);
7804 op0
= copy_to_mode_reg (mode0
, op0
);
7805 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
7808 pat
= GEN_FCN (icode
) (target
, addr
);
7818 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
7821 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7822 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7823 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7824 enum machine_mode mode0
= Pmode
;
7825 enum machine_mode mode1
= Pmode
;
7826 rtx op0
= expand_normal (arg0
);
7827 rtx op1
= expand_normal (arg1
);
7829 if (icode
== CODE_FOR_nothing
)
7830 /* Builtin not supported on this processor. */
7833 /* If we got invalid arguments bail out before generating bad rtl. */
7834 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
7838 || GET_MODE (target
) != tmode
7839 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7840 target
= gen_reg_rtx (tmode
);
7842 op1
= copy_to_mode_reg (mode1
, op1
);
7844 if (op0
== const0_rtx
)
7846 addr
= gen_rtx_MEM (tmode
, op1
);
7850 op0
= copy_to_mode_reg (mode0
, op0
);
7851 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
7854 pat
= GEN_FCN (icode
) (target
, addr
);
7864 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
7866 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7867 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7868 tree arg2
= CALL_EXPR_ARG (exp
, 2);
7869 rtx op0
= expand_normal (arg0
);
7870 rtx op1
= expand_normal (arg1
);
7871 rtx op2
= expand_normal (arg2
);
7873 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
7874 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
7875 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
7877 /* Invalid arguments. Bail before doing anything stoopid! */
7878 if (arg0
== error_mark_node
7879 || arg1
== error_mark_node
7880 || arg2
== error_mark_node
)
7883 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
7884 op0
= copy_to_mode_reg (mode2
, op0
);
7885 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
7886 op1
= copy_to_mode_reg (mode0
, op1
);
7887 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
7888 op2
= copy_to_mode_reg (mode1
, op2
);
7890 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
7897 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
7899 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7900 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7901 tree arg2
= CALL_EXPR_ARG (exp
, 2);
7902 rtx op0
= expand_normal (arg0
);
7903 rtx op1
= expand_normal (arg1
);
7904 rtx op2
= expand_normal (arg2
);
7906 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7907 enum machine_mode mode1
= Pmode
;
7908 enum machine_mode mode2
= Pmode
;
7910 /* Invalid arguments. Bail before doing anything stoopid! */
7911 if (arg0
== error_mark_node
7912 || arg1
== error_mark_node
7913 || arg2
== error_mark_node
)
7916 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
7917 op0
= copy_to_mode_reg (tmode
, op0
);
7919 op2
= copy_to_mode_reg (mode2
, op2
);
7921 if (op1
== const0_rtx
)
7923 addr
= gen_rtx_MEM (tmode
, op2
);
7927 op1
= copy_to_mode_reg (mode1
, op1
);
7928 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
7931 pat
= GEN_FCN (icode
) (addr
, op0
);
7938 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
7940 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7941 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7942 tree arg2
= CALL_EXPR_ARG (exp
, 2);
7943 rtx op0
= expand_normal (arg0
);
7944 rtx op1
= expand_normal (arg1
);
7945 rtx op2
= expand_normal (arg2
);
7947 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7948 enum machine_mode mode1
= Pmode
;
7949 enum machine_mode mode2
= Pmode
;
7951 /* Invalid arguments. Bail before doing anything stoopid! */
7952 if (arg0
== error_mark_node
7953 || arg1
== error_mark_node
7954 || arg2
== error_mark_node
)
7957 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
7958 op0
= copy_to_mode_reg (tmode
, op0
);
7960 op2
= copy_to_mode_reg (mode2
, op2
);
7962 if (op1
== const0_rtx
)
7964 addr
= gen_rtx_MEM (tmode
, op2
);
7968 op1
= copy_to_mode_reg (mode1
, op1
);
7969 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
7972 pat
= GEN_FCN (icode
) (addr
, op0
);
7979 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
7982 tree arg0
= CALL_EXPR_ARG (exp
, 0);
7983 tree arg1
= CALL_EXPR_ARG (exp
, 1);
7984 tree arg2
= CALL_EXPR_ARG (exp
, 2);
7985 rtx op0
= expand_normal (arg0
);
7986 rtx op1
= expand_normal (arg1
);
7987 rtx op2
= expand_normal (arg2
);
7988 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
7989 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
7990 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
7991 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
7993 if (icode
== CODE_FOR_nothing
)
7994 /* Builtin not supported on this processor. */
7997 /* If we got invalid arguments bail out before generating bad rtl. */
7998 if (arg0
== error_mark_node
7999 || arg1
== error_mark_node
8000 || arg2
== error_mark_node
)
8003 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
8004 || icode
== CODE_FOR_altivec_vsldoi_v4si
8005 || icode
== CODE_FOR_altivec_vsldoi_v8hi
8006 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
8008 /* Only allow 4-bit unsigned literals. */
8010 if (TREE_CODE (arg2
) != INTEGER_CST
8011 || TREE_INT_CST_LOW (arg2
) & ~0xf)
8013 error ("argument 3 must be a 4-bit unsigned literal");
8019 || GET_MODE (target
) != tmode
8020 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8021 target
= gen_reg_rtx (tmode
);
8023 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8024 op0
= copy_to_mode_reg (mode0
, op0
);
8025 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8026 op1
= copy_to_mode_reg (mode1
, op1
);
8027 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
8028 op2
= copy_to_mode_reg (mode2
, op2
);
8030 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
8031 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
8033 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8041 /* Expand the lvx builtins. */
8043 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
8045 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8046 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8048 enum machine_mode tmode
, mode0
;
8050 enum insn_code icode
;
8054 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
8055 icode
= CODE_FOR_altivec_lvx_v16qi
;
8057 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
8058 icode
= CODE_FOR_altivec_lvx_v8hi
;
8060 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
8061 icode
= CODE_FOR_altivec_lvx_v4si
;
8063 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
8064 icode
= CODE_FOR_altivec_lvx_v4sf
;
8073 arg0
= CALL_EXPR_ARG (exp
, 0);
8074 op0
= expand_normal (arg0
);
8075 tmode
= insn_data
[icode
].operand
[0].mode
;
8076 mode0
= insn_data
[icode
].operand
[1].mode
;
8079 || GET_MODE (target
) != tmode
8080 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8081 target
= gen_reg_rtx (tmode
);
8083 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8084 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8086 pat
= GEN_FCN (icode
) (target
, op0
);
8093 /* Expand the stvx builtins. */
8095 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
8098 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8099 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8101 enum machine_mode mode0
, mode1
;
8103 enum insn_code icode
;
8107 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
8108 icode
= CODE_FOR_altivec_stvx_v16qi
;
8110 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
8111 icode
= CODE_FOR_altivec_stvx_v8hi
;
8113 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
8114 icode
= CODE_FOR_altivec_stvx_v4si
;
8116 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
8117 icode
= CODE_FOR_altivec_stvx_v4sf
;
8124 arg0
= CALL_EXPR_ARG (exp
, 0);
8125 arg1
= CALL_EXPR_ARG (exp
, 1);
8126 op0
= expand_normal (arg0
);
8127 op1
= expand_normal (arg1
);
8128 mode0
= insn_data
[icode
].operand
[0].mode
;
8129 mode1
= insn_data
[icode
].operand
[1].mode
;
8131 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8132 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8133 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
8134 op1
= copy_to_mode_reg (mode1
, op1
);
8136 pat
= GEN_FCN (icode
) (op0
, op1
);
8144 /* Expand the dst builtins. */
8146 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
8149 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8150 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8151 tree arg0
, arg1
, arg2
;
8152 enum machine_mode mode0
, mode1
, mode2
;
8153 rtx pat
, op0
, op1
, op2
;
8154 const struct builtin_description
*d
;
8159 /* Handle DST variants. */
8161 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
8162 if (d
->code
== fcode
)
8164 arg0
= CALL_EXPR_ARG (exp
, 0);
8165 arg1
= CALL_EXPR_ARG (exp
, 1);
8166 arg2
= CALL_EXPR_ARG (exp
, 2);
8167 op0
= expand_normal (arg0
);
8168 op1
= expand_normal (arg1
);
8169 op2
= expand_normal (arg2
);
8170 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8171 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8172 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
8174 /* Invalid arguments, bail out before generating bad rtl. */
8175 if (arg0
== error_mark_node
8176 || arg1
== error_mark_node
8177 || arg2
== error_mark_node
)
8182 if (TREE_CODE (arg2
) != INTEGER_CST
8183 || TREE_INT_CST_LOW (arg2
) & ~0x3)
8185 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
8189 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
8190 op0
= copy_to_mode_reg (Pmode
, op0
);
8191 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
8192 op1
= copy_to_mode_reg (mode1
, op1
);
8194 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
8204 /* Expand vec_init builtin. */
8206 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
8208 enum machine_mode tmode
= TYPE_MODE (type
);
8209 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
8210 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
8211 rtvec v
= rtvec_alloc (n_elt
);
8213 gcc_assert (VECTOR_MODE_P (tmode
));
8214 gcc_assert (n_elt
== call_expr_nargs (exp
));
8216 for (i
= 0; i
< n_elt
; ++i
)
8218 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
8219 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
8222 if (!target
|| !register_operand (target
, tmode
))
8223 target
= gen_reg_rtx (tmode
);
8225 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
8229 /* Return the integer constant in ARG. Constrain it to be in the range
8230 of the subparts of VEC_TYPE; issue an error if not. */
8233 get_element_number (tree vec_type
, tree arg
)
8235 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
8237 if (!host_integerp (arg
, 1)
8238 || (elt
= tree_low_cst (arg
, 1), elt
> max
))
8240 error ("selector must be an integer constant in the range 0..%wi", max
);
8247 /* Expand vec_set builtin. */
8249 altivec_expand_vec_set_builtin (tree exp
)
8251 enum machine_mode tmode
, mode1
;
8252 tree arg0
, arg1
, arg2
;
8256 arg0
= CALL_EXPR_ARG (exp
, 0);
8257 arg1
= CALL_EXPR_ARG (exp
, 1);
8258 arg2
= CALL_EXPR_ARG (exp
, 2);
8260 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
8261 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
8262 gcc_assert (VECTOR_MODE_P (tmode
));
8264 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, 0);
8265 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, 0);
8266 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
8268 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
8269 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
8271 op0
= force_reg (tmode
, op0
);
8272 op1
= force_reg (mode1
, op1
);
8274 rs6000_expand_vector_set (op0
, op1
, elt
);
8279 /* Expand vec_ext builtin. */
8281 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
8283 enum machine_mode tmode
, mode0
;
8288 arg0
= CALL_EXPR_ARG (exp
, 0);
8289 arg1
= CALL_EXPR_ARG (exp
, 1);
8291 op0
= expand_normal (arg0
);
8292 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
8294 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
8295 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
8296 gcc_assert (VECTOR_MODE_P (mode0
));
8298 op0
= force_reg (mode0
, op0
);
8300 if (optimize
|| !target
|| !register_operand (target
, tmode
))
8301 target
= gen_reg_rtx (tmode
);
8303 rs6000_expand_vector_extract (target
, op0
, elt
);
8308 /* Expand the builtin in EXP and store the result in TARGET. Store
8309 true in *EXPANDEDP if we found a builtin to expand. */
8311 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8313 const struct builtin_description
*d
;
8314 const struct builtin_description_predicates
*dp
;
8316 enum insn_code icode
;
8317 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8320 enum machine_mode tmode
, mode0
;
8321 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8323 if (fcode
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8324 && fcode
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
)
8327 error ("unresolved overload for Altivec builtin %qF", fndecl
);
8331 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
8335 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
8339 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
8347 case ALTIVEC_BUILTIN_STVX
:
8348 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx
, exp
);
8349 case ALTIVEC_BUILTIN_STVEBX
:
8350 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
8351 case ALTIVEC_BUILTIN_STVEHX
:
8352 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
8353 case ALTIVEC_BUILTIN_STVEWX
:
8354 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
8355 case ALTIVEC_BUILTIN_STVXL
:
8356 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
8358 case ALTIVEC_BUILTIN_MFVSCR
:
8359 icode
= CODE_FOR_altivec_mfvscr
;
8360 tmode
= insn_data
[icode
].operand
[0].mode
;
8363 || GET_MODE (target
) != tmode
8364 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8365 target
= gen_reg_rtx (tmode
);
8367 pat
= GEN_FCN (icode
) (target
);
8373 case ALTIVEC_BUILTIN_MTVSCR
:
8374 icode
= CODE_FOR_altivec_mtvscr
;
8375 arg0
= CALL_EXPR_ARG (exp
, 0);
8376 op0
= expand_normal (arg0
);
8377 mode0
= insn_data
[icode
].operand
[0].mode
;
8379 /* If we got invalid arguments bail out before generating bad rtl. */
8380 if (arg0
== error_mark_node
)
8383 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8384 op0
= copy_to_mode_reg (mode0
, op0
);
8386 pat
= GEN_FCN (icode
) (op0
);
8391 case ALTIVEC_BUILTIN_DSSALL
:
8392 emit_insn (gen_altivec_dssall ());
8395 case ALTIVEC_BUILTIN_DSS
:
8396 icode
= CODE_FOR_altivec_dss
;
8397 arg0
= CALL_EXPR_ARG (exp
, 0);
8399 op0
= expand_normal (arg0
);
8400 mode0
= insn_data
[icode
].operand
[0].mode
;
8402 /* If we got invalid arguments bail out before generating bad rtl. */
8403 if (arg0
== error_mark_node
)
8406 if (TREE_CODE (arg0
) != INTEGER_CST
8407 || TREE_INT_CST_LOW (arg0
) & ~0x3)
8409 error ("argument to dss must be a 2-bit unsigned literal");
8413 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8414 op0
= copy_to_mode_reg (mode0
, op0
);
8416 emit_insn (gen_altivec_dss (op0
));
8419 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
8420 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
8421 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
8422 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
8423 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
8425 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
8426 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
8427 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
8428 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
8429 return altivec_expand_vec_set_builtin (exp
);
8431 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
8432 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
8433 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
8434 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
8435 return altivec_expand_vec_ext_builtin (exp
, target
);
8442 /* Expand abs* operations. */
8444 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
8445 if (d
->code
== fcode
)
8446 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
8448 /* Expand the AltiVec predicates. */
8449 dp
= bdesc_altivec_preds
;
8450 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
8451 if (dp
->code
== fcode
)
8452 return altivec_expand_predicate_builtin (dp
->icode
, dp
->opcode
,
8455 /* LV* are funky. We initialized them differently. */
8458 case ALTIVEC_BUILTIN_LVSL
:
8459 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
8461 case ALTIVEC_BUILTIN_LVSR
:
8462 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
8464 case ALTIVEC_BUILTIN_LVEBX
:
8465 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
8467 case ALTIVEC_BUILTIN_LVEHX
:
8468 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
8470 case ALTIVEC_BUILTIN_LVEWX
:
8471 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
8473 case ALTIVEC_BUILTIN_LVXL
:
8474 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
8476 case ALTIVEC_BUILTIN_LVX
:
8477 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx
,
8488 /* Expand the builtin in EXP and store the result in TARGET. Store
8489 true in *EXPANDEDP if we found a builtin to expand. */
8491 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
8493 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8494 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8495 const struct builtin_description
*d
;
8502 case PAIRED_BUILTIN_STX
:
8503 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
8504 case PAIRED_BUILTIN_LX
:
8505 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
8511 /* Expand the paired predicates. */
8512 d
= bdesc_paired_preds
;
8513 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
8514 if (d
->code
== fcode
)
8515 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
8521 /* Binops that need to be initialized manually, but can be expanded
8522 automagically by rs6000_expand_binop_builtin. */
8523 static struct builtin_description bdesc_2arg_spe
[] =
8525 { 0, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
8526 { 0, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
8527 { 0, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
8528 { 0, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
8529 { 0, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
8530 { 0, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
8531 { 0, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
8532 { 0, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
8533 { 0, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
8534 { 0, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
8535 { 0, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
8536 { 0, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
8537 { 0, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
8538 { 0, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
8539 { 0, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
8540 { 0, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
8541 { 0, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
8542 { 0, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
8543 { 0, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
8544 { 0, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
8545 { 0, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
8546 { 0, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
8549 /* Expand the builtin in EXP and store the result in TARGET. Store
8550 true in *EXPANDEDP if we found a builtin to expand.
8552 This expands the SPE builtins that are not simple unary and binary
8555 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
8557 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8559 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8560 enum insn_code icode
;
8561 enum machine_mode tmode
, mode0
;
8563 struct builtin_description
*d
;
8568 /* Syntax check for a 5-bit unsigned immediate. */
8571 case SPE_BUILTIN_EVSTDD
:
8572 case SPE_BUILTIN_EVSTDH
:
8573 case SPE_BUILTIN_EVSTDW
:
8574 case SPE_BUILTIN_EVSTWHE
:
8575 case SPE_BUILTIN_EVSTWHO
:
8576 case SPE_BUILTIN_EVSTWWE
:
8577 case SPE_BUILTIN_EVSTWWO
:
8578 arg1
= CALL_EXPR_ARG (exp
, 2);
8579 if (TREE_CODE (arg1
) != INTEGER_CST
8580 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
8582 error ("argument 2 must be a 5-bit unsigned literal");
8590 /* The evsplat*i instructions are not quite generic. */
8593 case SPE_BUILTIN_EVSPLATFI
:
8594 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
8596 case SPE_BUILTIN_EVSPLATI
:
8597 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
8603 d
= (struct builtin_description
*) bdesc_2arg_spe
;
8604 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
8605 if (d
->code
== fcode
)
8606 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
8608 d
= (struct builtin_description
*) bdesc_spe_predicates
;
8609 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
8610 if (d
->code
== fcode
)
8611 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
8613 d
= (struct builtin_description
*) bdesc_spe_evsel
;
8614 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
8615 if (d
->code
== fcode
)
8616 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
8620 case SPE_BUILTIN_EVSTDDX
:
8621 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
8622 case SPE_BUILTIN_EVSTDHX
:
8623 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
8624 case SPE_BUILTIN_EVSTDWX
:
8625 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
8626 case SPE_BUILTIN_EVSTWHEX
:
8627 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
8628 case SPE_BUILTIN_EVSTWHOX
:
8629 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
8630 case SPE_BUILTIN_EVSTWWEX
:
8631 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
8632 case SPE_BUILTIN_EVSTWWOX
:
8633 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
8634 case SPE_BUILTIN_EVSTDD
:
8635 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
8636 case SPE_BUILTIN_EVSTDH
:
8637 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
8638 case SPE_BUILTIN_EVSTDW
:
8639 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
8640 case SPE_BUILTIN_EVSTWHE
:
8641 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
8642 case SPE_BUILTIN_EVSTWHO
:
8643 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
8644 case SPE_BUILTIN_EVSTWWE
:
8645 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
8646 case SPE_BUILTIN_EVSTWWO
:
8647 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
8648 case SPE_BUILTIN_MFSPEFSCR
:
8649 icode
= CODE_FOR_spe_mfspefscr
;
8650 tmode
= insn_data
[icode
].operand
[0].mode
;
8653 || GET_MODE (target
) != tmode
8654 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8655 target
= gen_reg_rtx (tmode
);
8657 pat
= GEN_FCN (icode
) (target
);
8662 case SPE_BUILTIN_MTSPEFSCR
:
8663 icode
= CODE_FOR_spe_mtspefscr
;
8664 arg0
= CALL_EXPR_ARG (exp
, 0);
8665 op0
= expand_normal (arg0
);
8666 mode0
= insn_data
[icode
].operand
[0].mode
;
8668 if (arg0
== error_mark_node
)
8671 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
8672 op0
= copy_to_mode_reg (mode0
, op0
);
8674 pat
= GEN_FCN (icode
) (op0
);
8687 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
8689 rtx pat
, scratch
, tmp
;
8690 tree form
= CALL_EXPR_ARG (exp
, 0);
8691 tree arg0
= CALL_EXPR_ARG (exp
, 1);
8692 tree arg1
= CALL_EXPR_ARG (exp
, 2);
8693 rtx op0
= expand_normal (arg0
);
8694 rtx op1
= expand_normal (arg1
);
8695 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8696 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8700 if (TREE_CODE (form
) != INTEGER_CST
)
8702 error ("argument 1 of __builtin_paired_predicate must be a constant");
8706 form_int
= TREE_INT_CST_LOW (form
);
8708 gcc_assert (mode0
== mode1
);
8710 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8714 || GET_MODE (target
) != SImode
8715 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
8716 target
= gen_reg_rtx (SImode
);
8717 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8718 op0
= copy_to_mode_reg (mode0
, op0
);
8719 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8720 op1
= copy_to_mode_reg (mode1
, op1
);
8722 scratch
= gen_reg_rtx (CCFPmode
);
8724 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8746 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
8749 error ("argument 1 of __builtin_paired_predicate is out of range");
8753 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
8754 emit_move_insn (target
, tmp
);
8759 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
8761 rtx pat
, scratch
, tmp
;
8762 tree form
= CALL_EXPR_ARG (exp
, 0);
8763 tree arg0
= CALL_EXPR_ARG (exp
, 1);
8764 tree arg1
= CALL_EXPR_ARG (exp
, 2);
8765 rtx op0
= expand_normal (arg0
);
8766 rtx op1
= expand_normal (arg1
);
8767 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8768 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8772 if (TREE_CODE (form
) != INTEGER_CST
)
8774 error ("argument 1 of __builtin_spe_predicate must be a constant");
8778 form_int
= TREE_INT_CST_LOW (form
);
8780 gcc_assert (mode0
== mode1
);
8782 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
8786 || GET_MODE (target
) != SImode
8787 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
8788 target
= gen_reg_rtx (SImode
);
8790 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8791 op0
= copy_to_mode_reg (mode0
, op0
);
8792 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8793 op1
= copy_to_mode_reg (mode1
, op1
);
8795 scratch
= gen_reg_rtx (CCmode
);
8797 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8802 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8803 _lower_. We use one compare, but look in different bits of the
8804 CR for each variant.
8806 There are 2 elements in each SPE simd type (upper/lower). The CR
8807 bits are set as follows:
8809 BIT0 | BIT 1 | BIT 2 | BIT 3
8810 U | L | (U | L) | (U & L)
8812 So, for an "all" relationship, BIT 3 would be set.
8813 For an "any" relationship, BIT 2 would be set. Etc.
8815 Following traditional nomenclature, these bits map to:
8817 BIT0 | BIT 1 | BIT 2 | BIT 3
8820 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8825 /* All variant. OV bit. */
8827 /* We need to get to the OV bit, which is the ORDERED bit. We
8828 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8829 that's ugly and will make validate_condition_mode die.
8830 So let's just use another pattern. */
8831 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
8833 /* Any variant. EQ bit. */
8837 /* Upper variant. LT bit. */
8841 /* Lower variant. GT bit. */
8846 error ("argument 1 of __builtin_spe_predicate is out of range");
8850 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
8851 emit_move_insn (target
, tmp
);
8856 /* The evsel builtins look like this:
8858 e = __builtin_spe_evsel_OP (a, b, c, d);
8862 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8863 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8867 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
8870 tree arg0
= CALL_EXPR_ARG (exp
, 0);
8871 tree arg1
= CALL_EXPR_ARG (exp
, 1);
8872 tree arg2
= CALL_EXPR_ARG (exp
, 2);
8873 tree arg3
= CALL_EXPR_ARG (exp
, 3);
8874 rtx op0
= expand_normal (arg0
);
8875 rtx op1
= expand_normal (arg1
);
8876 rtx op2
= expand_normal (arg2
);
8877 rtx op3
= expand_normal (arg3
);
8878 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8879 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8881 gcc_assert (mode0
== mode1
);
8883 if (arg0
== error_mark_node
|| arg1
== error_mark_node
8884 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
8888 || GET_MODE (target
) != mode0
8889 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
8890 target
= gen_reg_rtx (mode0
);
8892 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8893 op0
= copy_to_mode_reg (mode0
, op0
);
8894 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
8895 op1
= copy_to_mode_reg (mode0
, op1
);
8896 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
8897 op2
= copy_to_mode_reg (mode0
, op2
);
8898 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
8899 op3
= copy_to_mode_reg (mode0
, op3
);
8901 /* Generate the compare. */
8902 scratch
= gen_reg_rtx (CCmode
);
8903 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
8908 if (mode0
== V2SImode
)
8909 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
8911 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
8916 /* Expand an expression EXP that calls a built-in function,
8917 with result going to TARGET if that's convenient
8918 (and in mode MODE if that's convenient).
8919 SUBTARGET may be used as the target for computing one of EXP's operands.
8920 IGNORE is nonzero if the value is to be ignored. */
8923 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8924 enum machine_mode mode ATTRIBUTE_UNUSED
,
8925 int ignore ATTRIBUTE_UNUSED
)
8927 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8928 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8929 const struct builtin_description
*d
;
8934 if (fcode
== RS6000_BUILTIN_RECIP
)
8935 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
8937 if (fcode
== RS6000_BUILTIN_RECIPF
)
8938 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
8940 if (fcode
== RS6000_BUILTIN_RSQRTF
)
8941 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
8943 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_LOAD
8944 || fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
8946 int icode
= (int) CODE_FOR_altivec_lvsr
;
8947 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8948 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
8952 gcc_assert (TARGET_ALTIVEC
);
8954 arg
= CALL_EXPR_ARG (exp
, 0);
8955 gcc_assert (TREE_CODE (TREE_TYPE (arg
)) == POINTER_TYPE
);
8956 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
8957 addr
= memory_address (mode
, op
);
8958 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
8962 /* For the load case need to negate the address. */
8963 op
= gen_reg_rtx (GET_MODE (addr
));
8964 emit_insn (gen_rtx_SET (VOIDmode
, op
,
8965 gen_rtx_NEG (GET_MODE (addr
), addr
)));
8967 op
= gen_rtx_MEM (mode
, op
);
8970 || GET_MODE (target
) != tmode
8971 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8972 target
= gen_reg_rtx (tmode
);
8974 /*pat = gen_altivec_lvsr (target, op);*/
8975 pat
= GEN_FCN (icode
) (target
, op
);
8983 /* FIXME: There's got to be a nicer way to handle this case than
8984 constructing a new CALL_EXPR. */
8985 if (fcode
== ALTIVEC_BUILTIN_VCFUX
8986 || fcode
== ALTIVEC_BUILTIN_VCFSX
)
8988 if (call_expr_nargs (exp
) == 1)
8989 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
8990 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
8995 ret
= altivec_expand_builtin (exp
, target
, &success
);
9002 ret
= spe_expand_builtin (exp
, target
, &success
);
9007 if (TARGET_PAIRED_FLOAT
)
9009 ret
= paired_expand_builtin (exp
, target
, &success
);
9015 gcc_assert (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
9017 /* Handle simple unary operations. */
9018 d
= (struct builtin_description
*) bdesc_1arg
;
9019 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9020 if (d
->code
== fcode
)
9021 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
9023 /* Handle simple binary operations. */
9024 d
= (struct builtin_description
*) bdesc_2arg
;
9025 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9026 if (d
->code
== fcode
)
9027 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
9029 /* Handle simple ternary operations. */
9031 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
9032 if (d
->code
== fcode
)
9033 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
9039 build_opaque_vector_type (tree node
, int nunits
)
9041 node
= copy_node (node
);
9042 TYPE_MAIN_VARIANT (node
) = node
;
9043 return build_vector_type (node
, nunits
);
9047 rs6000_init_builtins (void)
9049 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
9050 V2SF_type_node
= build_vector_type (float_type_node
, 2);
9051 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
9052 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
9053 V4SF_type_node
= build_vector_type (float_type_node
, 4);
9054 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
9055 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
9057 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
9058 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
9059 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
9061 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
9062 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
9063 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
9064 opaque_V4SI_type_node
= copy_node (V4SI_type_node
);
9066 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
9067 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
9068 'vector unsigned short'. */
9070 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
9071 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
9072 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
9073 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
9075 long_integer_type_internal_node
= long_integer_type_node
;
9076 long_unsigned_type_internal_node
= long_unsigned_type_node
;
9077 intQI_type_internal_node
= intQI_type_node
;
9078 uintQI_type_internal_node
= unsigned_intQI_type_node
;
9079 intHI_type_internal_node
= intHI_type_node
;
9080 uintHI_type_internal_node
= unsigned_intHI_type_node
;
9081 intSI_type_internal_node
= intSI_type_node
;
9082 uintSI_type_internal_node
= unsigned_intSI_type_node
;
9083 float_type_internal_node
= float_type_node
;
9084 void_type_internal_node
= void_type_node
;
9086 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9087 get_identifier ("__bool char"),
9088 bool_char_type_node
));
9089 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9090 get_identifier ("__bool short"),
9091 bool_short_type_node
));
9092 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9093 get_identifier ("__bool int"),
9094 bool_int_type_node
));
9095 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9096 get_identifier ("__pixel"),
9099 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
9100 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
9101 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
9102 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
9104 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9105 get_identifier ("__vector unsigned char"),
9106 unsigned_V16QI_type_node
));
9107 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9108 get_identifier ("__vector signed char"),
9110 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9111 get_identifier ("__vector __bool char"),
9112 bool_V16QI_type_node
));
9114 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9115 get_identifier ("__vector unsigned short"),
9116 unsigned_V8HI_type_node
));
9117 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9118 get_identifier ("__vector signed short"),
9120 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9121 get_identifier ("__vector __bool short"),
9122 bool_V8HI_type_node
));
9124 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9125 get_identifier ("__vector unsigned int"),
9126 unsigned_V4SI_type_node
));
9127 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9128 get_identifier ("__vector signed int"),
9130 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9131 get_identifier ("__vector __bool int"),
9132 bool_V4SI_type_node
));
9134 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9135 get_identifier ("__vector float"),
9137 (*lang_hooks
.decls
.pushdecl
) (build_decl (TYPE_DECL
,
9138 get_identifier ("__vector __pixel"),
9139 pixel_V8HI_type_node
));
9141 if (TARGET_PAIRED_FLOAT
)
9142 paired_init_builtins ();
9144 spe_init_builtins ();
9146 altivec_init_builtins ();
9147 if (TARGET_ALTIVEC
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
9148 rs6000_common_init_builtins ();
9149 if (TARGET_PPC_GFXOPT
)
9151 tree ftype
= build_function_type_list (float_type_node
,
9155 def_builtin (MASK_PPC_GFXOPT
, "__builtin_recipdivf", ftype
,
9156 RS6000_BUILTIN_RECIPF
);
9158 ftype
= build_function_type_list (float_type_node
,
9161 def_builtin (MASK_PPC_GFXOPT
, "__builtin_rsqrtf", ftype
,
9162 RS6000_BUILTIN_RSQRTF
);
9166 tree ftype
= build_function_type_list (double_type_node
,
9170 def_builtin (MASK_POPCNTB
, "__builtin_recipdiv", ftype
,
9171 RS6000_BUILTIN_RECIP
);
9176 /* AIX libm provides clog as __clog. */
9177 if (built_in_decls
[BUILT_IN_CLOG
])
9178 set_user_assembler_name (built_in_decls
[BUILT_IN_CLOG
], "__clog");
9182 /* Search through a set of builtins and enable the mask bits.
9183 DESC is an array of builtins.
9184 SIZE is the total number of builtins.
9185 START is the builtin enum at which to start.
9186 END is the builtin enum at which to end. */
9188 enable_mask_for_builtins (struct builtin_description
*desc
, int size
,
9189 enum rs6000_builtins start
,
9190 enum rs6000_builtins end
)
9194 for (i
= 0; i
< size
; ++i
)
9195 if (desc
[i
].code
== start
)
9201 for (; i
< size
; ++i
)
9203 /* Flip all the bits on. */
9204 desc
[i
].mask
= target_flags
;
9205 if (desc
[i
].code
== end
)
9211 spe_init_builtins (void)
9213 tree endlink
= void_list_node
;
9214 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
9215 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
9216 struct builtin_description
*d
;
9219 tree v2si_ftype_4_v2si
9220 = build_function_type
9221 (opaque_V2SI_type_node
,
9222 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9223 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9224 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9225 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9228 tree v2sf_ftype_4_v2sf
9229 = build_function_type
9230 (opaque_V2SF_type_node
,
9231 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9232 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9233 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9234 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9237 tree int_ftype_int_v2si_v2si
9238 = build_function_type
9240 tree_cons (NULL_TREE
, integer_type_node
,
9241 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9242 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9245 tree int_ftype_int_v2sf_v2sf
9246 = build_function_type
9248 tree_cons (NULL_TREE
, integer_type_node
,
9249 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9250 tree_cons (NULL_TREE
, opaque_V2SF_type_node
,
9253 tree void_ftype_v2si_puint_int
9254 = build_function_type (void_type_node
,
9255 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9256 tree_cons (NULL_TREE
, puint_type_node
,
9257 tree_cons (NULL_TREE
,
9261 tree void_ftype_v2si_puint_char
9262 = build_function_type (void_type_node
,
9263 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9264 tree_cons (NULL_TREE
, puint_type_node
,
9265 tree_cons (NULL_TREE
,
9269 tree void_ftype_v2si_pv2si_int
9270 = build_function_type (void_type_node
,
9271 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9272 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9273 tree_cons (NULL_TREE
,
9277 tree void_ftype_v2si_pv2si_char
9278 = build_function_type (void_type_node
,
9279 tree_cons (NULL_TREE
, opaque_V2SI_type_node
,
9280 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9281 tree_cons (NULL_TREE
,
9286 = build_function_type (void_type_node
,
9287 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
9290 = build_function_type (integer_type_node
, endlink
);
9292 tree v2si_ftype_pv2si_int
9293 = build_function_type (opaque_V2SI_type_node
,
9294 tree_cons (NULL_TREE
, opaque_p_V2SI_type_node
,
9295 tree_cons (NULL_TREE
, integer_type_node
,
9298 tree v2si_ftype_puint_int
9299 = build_function_type (opaque_V2SI_type_node
,
9300 tree_cons (NULL_TREE
, puint_type_node
,
9301 tree_cons (NULL_TREE
, integer_type_node
,
9304 tree v2si_ftype_pushort_int
9305 = build_function_type (opaque_V2SI_type_node
,
9306 tree_cons (NULL_TREE
, pushort_type_node
,
9307 tree_cons (NULL_TREE
, integer_type_node
,
9310 tree v2si_ftype_signed_char
9311 = build_function_type (opaque_V2SI_type_node
,
9312 tree_cons (NULL_TREE
, signed_char_type_node
,
9315 /* The initialization of the simple binary and unary builtins is
9316 done in rs6000_common_init_builtins, but we have to enable the
9317 mask bits here manually because we have run out of `target_flags'
9318 bits. We really need to redesign this mask business. */
9320 enable_mask_for_builtins ((struct builtin_description
*) bdesc_2arg
,
9321 ARRAY_SIZE (bdesc_2arg
),
9324 enable_mask_for_builtins ((struct builtin_description
*) bdesc_1arg
,
9325 ARRAY_SIZE (bdesc_1arg
),
9327 SPE_BUILTIN_EVSUBFUSIAAW
);
9328 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_predicates
,
9329 ARRAY_SIZE (bdesc_spe_predicates
),
9330 SPE_BUILTIN_EVCMPEQ
,
9331 SPE_BUILTIN_EVFSTSTLT
);
9332 enable_mask_for_builtins ((struct builtin_description
*) bdesc_spe_evsel
,
9333 ARRAY_SIZE (bdesc_spe_evsel
),
9334 SPE_BUILTIN_EVSEL_CMPGTS
,
9335 SPE_BUILTIN_EVSEL_FSTSTEQ
);
9337 (*lang_hooks
.decls
.pushdecl
)
9338 (build_decl (TYPE_DECL
, get_identifier ("__ev64_opaque__"),
9339 opaque_V2SI_type_node
));
9341 /* Initialize irregular SPE builtins. */
9343 def_builtin (target_flags
, "__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
9344 def_builtin (target_flags
, "__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
9345 def_builtin (target_flags
, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
9346 def_builtin (target_flags
, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
9347 def_builtin (target_flags
, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
9348 def_builtin (target_flags
, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
9349 def_builtin (target_flags
, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
9350 def_builtin (target_flags
, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
9351 def_builtin (target_flags
, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
9352 def_builtin (target_flags
, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
9353 def_builtin (target_flags
, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
9354 def_builtin (target_flags
, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
9355 def_builtin (target_flags
, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
9356 def_builtin (target_flags
, "__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
9357 def_builtin (target_flags
, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
9358 def_builtin (target_flags
, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
9359 def_builtin (target_flags
, "__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
9360 def_builtin (target_flags
, "__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
9363 def_builtin (target_flags
, "__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
9364 def_builtin (target_flags
, "__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
9365 def_builtin (target_flags
, "__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
9366 def_builtin (target_flags
, "__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
9367 def_builtin (target_flags
, "__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
9368 def_builtin (target_flags
, "__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
9369 def_builtin (target_flags
, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
9370 def_builtin (target_flags
, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
9371 def_builtin (target_flags
, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
9372 def_builtin (target_flags
, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
9373 def_builtin (target_flags
, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
9374 def_builtin (target_flags
, "__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
9375 def_builtin (target_flags
, "__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
9376 def_builtin (target_flags
, "__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
9377 def_builtin (target_flags
, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
9378 def_builtin (target_flags
, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
9379 def_builtin (target_flags
, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
9380 def_builtin (target_flags
, "__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
9381 def_builtin (target_flags
, "__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
9382 def_builtin (target_flags
, "__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
9383 def_builtin (target_flags
, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
9384 def_builtin (target_flags
, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
9387 d
= (struct builtin_description
*) bdesc_spe_predicates
;
9388 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
9392 switch (insn_data
[d
->icode
].operand
[1].mode
)
9395 type
= int_ftype_int_v2si_v2si
;
9398 type
= int_ftype_int_v2sf_v2sf
;
9404 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9407 /* Evsel predicates. */
9408 d
= (struct builtin_description
*) bdesc_spe_evsel
;
9409 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
9413 switch (insn_data
[d
->icode
].operand
[1].mode
)
9416 type
= v2si_ftype_4_v2si
;
9419 type
= v2sf_ftype_4_v2sf
;
9425 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9430 paired_init_builtins (void)
9432 const struct builtin_description
*d
;
9434 tree endlink
= void_list_node
;
9436 tree int_ftype_int_v2sf_v2sf
9437 = build_function_type
9439 tree_cons (NULL_TREE
, integer_type_node
,
9440 tree_cons (NULL_TREE
, V2SF_type_node
,
9441 tree_cons (NULL_TREE
, V2SF_type_node
,
9443 tree pcfloat_type_node
=
9444 build_pointer_type (build_qualified_type
9445 (float_type_node
, TYPE_QUAL_CONST
));
9447 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
9448 long_integer_type_node
,
9451 tree void_ftype_v2sf_long_pcfloat
=
9452 build_function_type_list (void_type_node
,
9454 long_integer_type_node
,
9459 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
9463 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
9464 PAIRED_BUILTIN_STX
);
9467 d
= bdesc_paired_preds
;
9468 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
9472 switch (insn_data
[d
->icode
].operand
[1].mode
)
9475 type
= int_ftype_int_v2sf_v2sf
;
9481 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9486 altivec_init_builtins (void)
9488 const struct builtin_description
*d
;
9489 const struct builtin_description_predicates
*dp
;
9493 tree pfloat_type_node
= build_pointer_type (float_type_node
);
9494 tree pint_type_node
= build_pointer_type (integer_type_node
);
9495 tree pshort_type_node
= build_pointer_type (short_integer_type_node
);
9496 tree pchar_type_node
= build_pointer_type (char_type_node
);
9498 tree pvoid_type_node
= build_pointer_type (void_type_node
);
9500 tree pcfloat_type_node
= build_pointer_type (build_qualified_type (float_type_node
, TYPE_QUAL_CONST
));
9501 tree pcint_type_node
= build_pointer_type (build_qualified_type (integer_type_node
, TYPE_QUAL_CONST
));
9502 tree pcshort_type_node
= build_pointer_type (build_qualified_type (short_integer_type_node
, TYPE_QUAL_CONST
));
9503 tree pcchar_type_node
= build_pointer_type (build_qualified_type (char_type_node
, TYPE_QUAL_CONST
));
9505 tree pcvoid_type_node
= build_pointer_type (build_qualified_type (void_type_node
, TYPE_QUAL_CONST
));
9507 tree int_ftype_opaque
9508 = build_function_type_list (integer_type_node
,
9509 opaque_V4SI_type_node
, NULL_TREE
);
9511 tree opaque_ftype_opaque_int
9512 = build_function_type_list (opaque_V4SI_type_node
,
9513 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
9514 tree opaque_ftype_opaque_opaque_int
9515 = build_function_type_list (opaque_V4SI_type_node
,
9516 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
9517 integer_type_node
, NULL_TREE
);
9518 tree int_ftype_int_opaque_opaque
9519 = build_function_type_list (integer_type_node
,
9520 integer_type_node
, opaque_V4SI_type_node
,
9521 opaque_V4SI_type_node
, NULL_TREE
);
9522 tree int_ftype_int_v4si_v4si
9523 = build_function_type_list (integer_type_node
,
9524 integer_type_node
, V4SI_type_node
,
9525 V4SI_type_node
, NULL_TREE
);
9526 tree v4sf_ftype_pcfloat
9527 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
9528 tree void_ftype_pfloat_v4sf
9529 = build_function_type_list (void_type_node
,
9530 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
9531 tree v4si_ftype_pcint
9532 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
9533 tree void_ftype_pint_v4si
9534 = build_function_type_list (void_type_node
,
9535 pint_type_node
, V4SI_type_node
, NULL_TREE
);
9536 tree v8hi_ftype_pcshort
9537 = build_function_type_list (V8HI_type_node
, pcshort_type_node
, NULL_TREE
);
9538 tree void_ftype_pshort_v8hi
9539 = build_function_type_list (void_type_node
,
9540 pshort_type_node
, V8HI_type_node
, NULL_TREE
);
9541 tree v16qi_ftype_pcchar
9542 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
9543 tree void_ftype_pchar_v16qi
9544 = build_function_type_list (void_type_node
,
9545 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
9546 tree void_ftype_v4si
9547 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
9548 tree v8hi_ftype_void
9549 = build_function_type (V8HI_type_node
, void_list_node
);
9550 tree void_ftype_void
9551 = build_function_type (void_type_node
, void_list_node
);
9553 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
9555 tree opaque_ftype_long_pcvoid
9556 = build_function_type_list (opaque_V4SI_type_node
,
9557 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9558 tree v16qi_ftype_long_pcvoid
9559 = build_function_type_list (V16QI_type_node
,
9560 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9561 tree v8hi_ftype_long_pcvoid
9562 = build_function_type_list (V8HI_type_node
,
9563 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9564 tree v4si_ftype_long_pcvoid
9565 = build_function_type_list (V4SI_type_node
,
9566 long_integer_type_node
, pcvoid_type_node
, NULL_TREE
);
9568 tree void_ftype_opaque_long_pvoid
9569 = build_function_type_list (void_type_node
,
9570 opaque_V4SI_type_node
, long_integer_type_node
,
9571 pvoid_type_node
, NULL_TREE
);
9572 tree void_ftype_v4si_long_pvoid
9573 = build_function_type_list (void_type_node
,
9574 V4SI_type_node
, long_integer_type_node
,
9575 pvoid_type_node
, NULL_TREE
);
9576 tree void_ftype_v16qi_long_pvoid
9577 = build_function_type_list (void_type_node
,
9578 V16QI_type_node
, long_integer_type_node
,
9579 pvoid_type_node
, NULL_TREE
);
9580 tree void_ftype_v8hi_long_pvoid
9581 = build_function_type_list (void_type_node
,
9582 V8HI_type_node
, long_integer_type_node
,
9583 pvoid_type_node
, NULL_TREE
);
9584 tree int_ftype_int_v8hi_v8hi
9585 = build_function_type_list (integer_type_node
,
9586 integer_type_node
, V8HI_type_node
,
9587 V8HI_type_node
, NULL_TREE
);
9588 tree int_ftype_int_v16qi_v16qi
9589 = build_function_type_list (integer_type_node
,
9590 integer_type_node
, V16QI_type_node
,
9591 V16QI_type_node
, NULL_TREE
);
9592 tree int_ftype_int_v4sf_v4sf
9593 = build_function_type_list (integer_type_node
,
9594 integer_type_node
, V4SF_type_node
,
9595 V4SF_type_node
, NULL_TREE
);
9596 tree v4si_ftype_v4si
9597 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
9598 tree v8hi_ftype_v8hi
9599 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
9600 tree v16qi_ftype_v16qi
9601 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
9602 tree v4sf_ftype_v4sf
9603 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9604 tree void_ftype_pcvoid_int_int
9605 = build_function_type_list (void_type_node
,
9606 pcvoid_type_node
, integer_type_node
,
9607 integer_type_node
, NULL_TREE
);
9609 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat
,
9610 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
);
9611 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf
,
9612 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
);
9613 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint
,
9614 ALTIVEC_BUILTIN_LD_INTERNAL_4si
);
9615 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si
,
9616 ALTIVEC_BUILTIN_ST_INTERNAL_4si
);
9617 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort
,
9618 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
);
9619 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi
,
9620 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
);
9621 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar
,
9622 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
);
9623 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi
,
9624 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
);
9625 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
9626 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
9627 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
9628 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
9629 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
9630 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
9631 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
9632 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
9633 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
9634 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
9635 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
9636 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
9637 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
9638 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
9639 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
9640 def_builtin (MASK_ALTIVEC
, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
9641 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
9642 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
9643 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
9644 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
9645 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
9646 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
9647 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
9648 def_builtin (MASK_ALTIVEC
, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
9649 def_builtin (MASK_ALTIVEC
, "__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
9650 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
9651 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
9652 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
9653 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
9654 def_builtin (MASK_ALTIVEC
, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
9656 def_builtin (MASK_ALTIVEC
, "__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
9658 def_builtin (MASK_ALTIVEC
, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
9659 def_builtin (MASK_ALTIVEC
, "__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
9660 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
9661 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
9662 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
9663 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
9664 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
9665 def_builtin (MASK_ALTIVEC
, "__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
9666 def_builtin (MASK_ALTIVEC
, "__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
9667 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
9669 /* Add the DST variants. */
9671 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
9672 def_builtin (d
->mask
, d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
9674 /* Initialize the predicates. */
9675 dp
= bdesc_altivec_preds
;
9676 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, dp
++)
9678 enum machine_mode mode1
;
9680 bool is_overloaded
= dp
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9681 && dp
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
9686 mode1
= insn_data
[dp
->icode
].operand
[1].mode
;
9691 type
= int_ftype_int_opaque_opaque
;
9694 type
= int_ftype_int_v4si_v4si
;
9697 type
= int_ftype_int_v8hi_v8hi
;
9700 type
= int_ftype_int_v16qi_v16qi
;
9703 type
= int_ftype_int_v4sf_v4sf
;
9709 def_builtin (dp
->mask
, dp
->name
, type
, dp
->code
);
9712 /* Initialize the abs* operators. */
9714 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
9716 enum machine_mode mode0
;
9719 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
9724 type
= v4si_ftype_v4si
;
9727 type
= v8hi_ftype_v8hi
;
9730 type
= v16qi_ftype_v16qi
;
9733 type
= v4sf_ftype_v4sf
;
9739 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
9746 /* Initialize target builtin that implements
9747 targetm.vectorize.builtin_mask_for_load. */
9749 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
9750 v16qi_ftype_long_pcvoid
,
9751 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
9752 BUILT_IN_MD
, NULL
, NULL_TREE
);
9753 TREE_READONLY (decl
) = 1;
9754 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9755 altivec_builtin_mask_for_load
= decl
;
9758 /* Access to the vec_init patterns. */
9759 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
9760 integer_type_node
, integer_type_node
,
9761 integer_type_node
, NULL_TREE
);
9762 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4si", ftype
,
9763 ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
9765 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
9766 short_integer_type_node
,
9767 short_integer_type_node
,
9768 short_integer_type_node
,
9769 short_integer_type_node
,
9770 short_integer_type_node
,
9771 short_integer_type_node
,
9772 short_integer_type_node
, NULL_TREE
);
9773 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v8hi", ftype
,
9774 ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
9776 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
9777 char_type_node
, char_type_node
,
9778 char_type_node
, char_type_node
,
9779 char_type_node
, char_type_node
,
9780 char_type_node
, char_type_node
,
9781 char_type_node
, char_type_node
,
9782 char_type_node
, char_type_node
,
9783 char_type_node
, char_type_node
,
9784 char_type_node
, NULL_TREE
);
9785 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v16qi", ftype
,
9786 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
9788 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
9789 float_type_node
, float_type_node
,
9790 float_type_node
, NULL_TREE
);
9791 def_builtin (MASK_ALTIVEC
, "__builtin_vec_init_v4sf", ftype
,
9792 ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
9794 /* Access to the vec_set patterns. */
9795 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
9797 integer_type_node
, NULL_TREE
);
9798 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4si", ftype
,
9799 ALTIVEC_BUILTIN_VEC_SET_V4SI
);
9801 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
9803 integer_type_node
, NULL_TREE
);
9804 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v8hi", ftype
,
9805 ALTIVEC_BUILTIN_VEC_SET_V8HI
);
9807 ftype
= build_function_type_list (V8HI_type_node
, V16QI_type_node
,
9809 integer_type_node
, NULL_TREE
);
9810 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v16qi", ftype
,
9811 ALTIVEC_BUILTIN_VEC_SET_V16QI
);
9813 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
9815 integer_type_node
, NULL_TREE
);
9816 def_builtin (MASK_ALTIVEC
, "__builtin_vec_set_v4sf", ftype
,
9817 ALTIVEC_BUILTIN_VEC_SET_V4SF
);
9819 /* Access to the vec_extract patterns. */
9820 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
9821 integer_type_node
, NULL_TREE
);
9822 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4si", ftype
,
9823 ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
9825 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
9826 integer_type_node
, NULL_TREE
);
9827 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v8hi", ftype
,
9828 ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
9830 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
9831 integer_type_node
, NULL_TREE
);
9832 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v16qi", ftype
,
9833 ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
9835 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
9836 integer_type_node
, NULL_TREE
);
9837 def_builtin (MASK_ALTIVEC
, "__builtin_vec_ext_v4sf", ftype
,
9838 ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
9842 rs6000_common_init_builtins (void)
9844 const struct builtin_description
*d
;
9847 tree v2sf_ftype_v2sf_v2sf_v2sf
9848 = build_function_type_list (V2SF_type_node
,
9849 V2SF_type_node
, V2SF_type_node
,
9850 V2SF_type_node
, NULL_TREE
);
9852 tree v4sf_ftype_v4sf_v4sf_v16qi
9853 = build_function_type_list (V4SF_type_node
,
9854 V4SF_type_node
, V4SF_type_node
,
9855 V16QI_type_node
, NULL_TREE
);
9856 tree v4si_ftype_v4si_v4si_v16qi
9857 = build_function_type_list (V4SI_type_node
,
9858 V4SI_type_node
, V4SI_type_node
,
9859 V16QI_type_node
, NULL_TREE
);
9860 tree v8hi_ftype_v8hi_v8hi_v16qi
9861 = build_function_type_list (V8HI_type_node
,
9862 V8HI_type_node
, V8HI_type_node
,
9863 V16QI_type_node
, NULL_TREE
);
9864 tree v16qi_ftype_v16qi_v16qi_v16qi
9865 = build_function_type_list (V16QI_type_node
,
9866 V16QI_type_node
, V16QI_type_node
,
9867 V16QI_type_node
, NULL_TREE
);
9869 = build_function_type_list (V4SI_type_node
, integer_type_node
, NULL_TREE
);
9871 = build_function_type_list (V8HI_type_node
, integer_type_node
, NULL_TREE
);
9872 tree v16qi_ftype_int
9873 = build_function_type_list (V16QI_type_node
, integer_type_node
, NULL_TREE
);
9874 tree v8hi_ftype_v16qi
9875 = build_function_type_list (V8HI_type_node
, V16QI_type_node
, NULL_TREE
);
9876 tree v4sf_ftype_v4sf
9877 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9879 tree v2si_ftype_v2si_v2si
9880 = build_function_type_list (opaque_V2SI_type_node
,
9881 opaque_V2SI_type_node
,
9882 opaque_V2SI_type_node
, NULL_TREE
);
9884 tree v2sf_ftype_v2sf_v2sf_spe
9885 = build_function_type_list (opaque_V2SF_type_node
,
9886 opaque_V2SF_type_node
,
9887 opaque_V2SF_type_node
, NULL_TREE
);
9889 tree v2sf_ftype_v2sf_v2sf
9890 = build_function_type_list (V2SF_type_node
,
9892 V2SF_type_node
, NULL_TREE
);
9895 tree v2si_ftype_int_int
9896 = build_function_type_list (opaque_V2SI_type_node
,
9897 integer_type_node
, integer_type_node
,
9900 tree opaque_ftype_opaque
9901 = build_function_type_list (opaque_V4SI_type_node
,
9902 opaque_V4SI_type_node
, NULL_TREE
);
9904 tree v2si_ftype_v2si
9905 = build_function_type_list (opaque_V2SI_type_node
,
9906 opaque_V2SI_type_node
, NULL_TREE
);
9908 tree v2sf_ftype_v2sf_spe
9909 = build_function_type_list (opaque_V2SF_type_node
,
9910 opaque_V2SF_type_node
, NULL_TREE
);
9912 tree v2sf_ftype_v2sf
9913 = build_function_type_list (V2SF_type_node
,
9914 V2SF_type_node
, NULL_TREE
);
9916 tree v2sf_ftype_v2si
9917 = build_function_type_list (opaque_V2SF_type_node
,
9918 opaque_V2SI_type_node
, NULL_TREE
);
9920 tree v2si_ftype_v2sf
9921 = build_function_type_list (opaque_V2SI_type_node
,
9922 opaque_V2SF_type_node
, NULL_TREE
);
9924 tree v2si_ftype_v2si_char
9925 = build_function_type_list (opaque_V2SI_type_node
,
9926 opaque_V2SI_type_node
,
9927 char_type_node
, NULL_TREE
);
9929 tree v2si_ftype_int_char
9930 = build_function_type_list (opaque_V2SI_type_node
,
9931 integer_type_node
, char_type_node
, NULL_TREE
);
9933 tree v2si_ftype_char
9934 = build_function_type_list (opaque_V2SI_type_node
,
9935 char_type_node
, NULL_TREE
);
9937 tree int_ftype_int_int
9938 = build_function_type_list (integer_type_node
,
9939 integer_type_node
, integer_type_node
,
9942 tree opaque_ftype_opaque_opaque
9943 = build_function_type_list (opaque_V4SI_type_node
,
9944 opaque_V4SI_type_node
, opaque_V4SI_type_node
, NULL_TREE
);
9945 tree v4si_ftype_v4si_v4si
9946 = build_function_type_list (V4SI_type_node
,
9947 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
9948 tree v4sf_ftype_v4si_int
9949 = build_function_type_list (V4SF_type_node
,
9950 V4SI_type_node
, integer_type_node
, NULL_TREE
);
9951 tree v4si_ftype_v4sf_int
9952 = build_function_type_list (V4SI_type_node
,
9953 V4SF_type_node
, integer_type_node
, NULL_TREE
);
9954 tree v4si_ftype_v4si_int
9955 = build_function_type_list (V4SI_type_node
,
9956 V4SI_type_node
, integer_type_node
, NULL_TREE
);
9957 tree v8hi_ftype_v8hi_int
9958 = build_function_type_list (V8HI_type_node
,
9959 V8HI_type_node
, integer_type_node
, NULL_TREE
);
9960 tree v16qi_ftype_v16qi_int
9961 = build_function_type_list (V16QI_type_node
,
9962 V16QI_type_node
, integer_type_node
, NULL_TREE
);
9963 tree v16qi_ftype_v16qi_v16qi_int
9964 = build_function_type_list (V16QI_type_node
,
9965 V16QI_type_node
, V16QI_type_node
,
9966 integer_type_node
, NULL_TREE
);
9967 tree v8hi_ftype_v8hi_v8hi_int
9968 = build_function_type_list (V8HI_type_node
,
9969 V8HI_type_node
, V8HI_type_node
,
9970 integer_type_node
, NULL_TREE
);
9971 tree v4si_ftype_v4si_v4si_int
9972 = build_function_type_list (V4SI_type_node
,
9973 V4SI_type_node
, V4SI_type_node
,
9974 integer_type_node
, NULL_TREE
);
9975 tree v4sf_ftype_v4sf_v4sf_int
9976 = build_function_type_list (V4SF_type_node
,
9977 V4SF_type_node
, V4SF_type_node
,
9978 integer_type_node
, NULL_TREE
);
9979 tree v4sf_ftype_v4sf_v4sf
9980 = build_function_type_list (V4SF_type_node
,
9981 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
9982 tree opaque_ftype_opaque_opaque_opaque
9983 = build_function_type_list (opaque_V4SI_type_node
,
9984 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
9985 opaque_V4SI_type_node
, NULL_TREE
);
9986 tree v4sf_ftype_v4sf_v4sf_v4si
9987 = build_function_type_list (V4SF_type_node
,
9988 V4SF_type_node
, V4SF_type_node
,
9989 V4SI_type_node
, NULL_TREE
);
9990 tree v4sf_ftype_v4sf_v4sf_v4sf
9991 = build_function_type_list (V4SF_type_node
,
9992 V4SF_type_node
, V4SF_type_node
,
9993 V4SF_type_node
, NULL_TREE
);
9994 tree v4si_ftype_v4si_v4si_v4si
9995 = build_function_type_list (V4SI_type_node
,
9996 V4SI_type_node
, V4SI_type_node
,
9997 V4SI_type_node
, NULL_TREE
);
9998 tree v8hi_ftype_v8hi_v8hi
9999 = build_function_type_list (V8HI_type_node
,
10000 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10001 tree v8hi_ftype_v8hi_v8hi_v8hi
10002 = build_function_type_list (V8HI_type_node
,
10003 V8HI_type_node
, V8HI_type_node
,
10004 V8HI_type_node
, NULL_TREE
);
10005 tree v4si_ftype_v8hi_v8hi_v4si
10006 = build_function_type_list (V4SI_type_node
,
10007 V8HI_type_node
, V8HI_type_node
,
10008 V4SI_type_node
, NULL_TREE
);
10009 tree v4si_ftype_v16qi_v16qi_v4si
10010 = build_function_type_list (V4SI_type_node
,
10011 V16QI_type_node
, V16QI_type_node
,
10012 V4SI_type_node
, NULL_TREE
);
10013 tree v16qi_ftype_v16qi_v16qi
10014 = build_function_type_list (V16QI_type_node
,
10015 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10016 tree v4si_ftype_v4sf_v4sf
10017 = build_function_type_list (V4SI_type_node
,
10018 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10019 tree v8hi_ftype_v16qi_v16qi
10020 = build_function_type_list (V8HI_type_node
,
10021 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10022 tree v4si_ftype_v8hi_v8hi
10023 = build_function_type_list (V4SI_type_node
,
10024 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10025 tree v8hi_ftype_v4si_v4si
10026 = build_function_type_list (V8HI_type_node
,
10027 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10028 tree v16qi_ftype_v8hi_v8hi
10029 = build_function_type_list (V16QI_type_node
,
10030 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10031 tree v4si_ftype_v16qi_v4si
10032 = build_function_type_list (V4SI_type_node
,
10033 V16QI_type_node
, V4SI_type_node
, NULL_TREE
);
10034 tree v4si_ftype_v16qi_v16qi
10035 = build_function_type_list (V4SI_type_node
,
10036 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10037 tree v4si_ftype_v8hi_v4si
10038 = build_function_type_list (V4SI_type_node
,
10039 V8HI_type_node
, V4SI_type_node
, NULL_TREE
);
10040 tree v4si_ftype_v8hi
10041 = build_function_type_list (V4SI_type_node
, V8HI_type_node
, NULL_TREE
);
10042 tree int_ftype_v4si_v4si
10043 = build_function_type_list (integer_type_node
,
10044 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
10045 tree int_ftype_v4sf_v4sf
10046 = build_function_type_list (integer_type_node
,
10047 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
10048 tree int_ftype_v16qi_v16qi
10049 = build_function_type_list (integer_type_node
,
10050 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
10051 tree int_ftype_v8hi_v8hi
10052 = build_function_type_list (integer_type_node
,
10053 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
10055 /* Add the simple ternary operators. */
10057 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
10059 enum machine_mode mode0
, mode1
, mode2
, mode3
;
10061 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10062 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10073 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10076 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10077 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10078 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
10079 mode3
= insn_data
[d
->icode
].operand
[3].mode
;
10082 /* When all four are of the same mode. */
10083 if (mode0
== mode1
&& mode1
== mode2
&& mode2
== mode3
)
10088 type
= opaque_ftype_opaque_opaque_opaque
;
10091 type
= v4si_ftype_v4si_v4si_v4si
;
10094 type
= v4sf_ftype_v4sf_v4sf_v4sf
;
10097 type
= v8hi_ftype_v8hi_v8hi_v8hi
;
10100 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
10103 type
= v2sf_ftype_v2sf_v2sf_v2sf
;
10106 gcc_unreachable ();
10109 else if (mode0
== mode1
&& mode1
== mode2
&& mode3
== V16QImode
)
10114 type
= v4si_ftype_v4si_v4si_v16qi
;
10117 type
= v4sf_ftype_v4sf_v4sf_v16qi
;
10120 type
= v8hi_ftype_v8hi_v8hi_v16qi
;
10123 type
= v16qi_ftype_v16qi_v16qi_v16qi
;
10126 gcc_unreachable ();
10129 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
10130 && mode3
== V4SImode
)
10131 type
= v4si_ftype_v16qi_v16qi_v4si
;
10132 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
10133 && mode3
== V4SImode
)
10134 type
= v4si_ftype_v8hi_v8hi_v4si
;
10135 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
10136 && mode3
== V4SImode
)
10137 type
= v4sf_ftype_v4sf_v4sf_v4si
;
10139 /* vchar, vchar, vchar, 4-bit literal. */
10140 else if (mode0
== V16QImode
&& mode1
== mode0
&& mode2
== mode0
10141 && mode3
== QImode
)
10142 type
= v16qi_ftype_v16qi_v16qi_int
;
10144 /* vshort, vshort, vshort, 4-bit literal. */
10145 else if (mode0
== V8HImode
&& mode1
== mode0
&& mode2
== mode0
10146 && mode3
== QImode
)
10147 type
= v8hi_ftype_v8hi_v8hi_int
;
10149 /* vint, vint, vint, 4-bit literal. */
10150 else if (mode0
== V4SImode
&& mode1
== mode0
&& mode2
== mode0
10151 && mode3
== QImode
)
10152 type
= v4si_ftype_v4si_v4si_int
;
10154 /* vfloat, vfloat, vfloat, 4-bit literal. */
10155 else if (mode0
== V4SFmode
&& mode1
== mode0
&& mode2
== mode0
10156 && mode3
== QImode
)
10157 type
= v4sf_ftype_v4sf_v4sf_int
;
10160 gcc_unreachable ();
10162 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10165 /* Add the simple binary operators. */
10166 d
= (struct builtin_description
*) bdesc_2arg
;
10167 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
10169 enum machine_mode mode0
, mode1
, mode2
;
10171 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10172 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10182 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10185 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10186 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10187 mode2
= insn_data
[d
->icode
].operand
[2].mode
;
10190 /* When all three operands are of the same mode. */
10191 if (mode0
== mode1
&& mode1
== mode2
)
10196 type
= opaque_ftype_opaque_opaque
;
10199 type
= v4sf_ftype_v4sf_v4sf
;
10202 type
= v4si_ftype_v4si_v4si
;
10205 type
= v16qi_ftype_v16qi_v16qi
;
10208 type
= v8hi_ftype_v8hi_v8hi
;
10211 type
= v2si_ftype_v2si_v2si
;
10214 if (TARGET_PAIRED_FLOAT
)
10215 type
= v2sf_ftype_v2sf_v2sf
;
10217 type
= v2sf_ftype_v2sf_v2sf_spe
;
10220 type
= int_ftype_int_int
;
10223 gcc_unreachable ();
10227 /* A few other combos we really don't want to do manually. */
10229 /* vint, vfloat, vfloat. */
10230 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== V4SFmode
)
10231 type
= v4si_ftype_v4sf_v4sf
;
10233 /* vshort, vchar, vchar. */
10234 else if (mode0
== V8HImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
10235 type
= v8hi_ftype_v16qi_v16qi
;
10237 /* vint, vshort, vshort. */
10238 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
10239 type
= v4si_ftype_v8hi_v8hi
;
10241 /* vshort, vint, vint. */
10242 else if (mode0
== V8HImode
&& mode1
== V4SImode
&& mode2
== V4SImode
)
10243 type
= v8hi_ftype_v4si_v4si
;
10245 /* vchar, vshort, vshort. */
10246 else if (mode0
== V16QImode
&& mode1
== V8HImode
&& mode2
== V8HImode
)
10247 type
= v16qi_ftype_v8hi_v8hi
;
10249 /* vint, vchar, vint. */
10250 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V4SImode
)
10251 type
= v4si_ftype_v16qi_v4si
;
10253 /* vint, vchar, vchar. */
10254 else if (mode0
== V4SImode
&& mode1
== V16QImode
&& mode2
== V16QImode
)
10255 type
= v4si_ftype_v16qi_v16qi
;
10257 /* vint, vshort, vint. */
10258 else if (mode0
== V4SImode
&& mode1
== V8HImode
&& mode2
== V4SImode
)
10259 type
= v4si_ftype_v8hi_v4si
;
10261 /* vint, vint, 5-bit literal. */
10262 else if (mode0
== V4SImode
&& mode1
== V4SImode
&& mode2
== QImode
)
10263 type
= v4si_ftype_v4si_int
;
10265 /* vshort, vshort, 5-bit literal. */
10266 else if (mode0
== V8HImode
&& mode1
== V8HImode
&& mode2
== QImode
)
10267 type
= v8hi_ftype_v8hi_int
;
10269 /* vchar, vchar, 5-bit literal. */
10270 else if (mode0
== V16QImode
&& mode1
== V16QImode
&& mode2
== QImode
)
10271 type
= v16qi_ftype_v16qi_int
;
10273 /* vfloat, vint, 5-bit literal. */
10274 else if (mode0
== V4SFmode
&& mode1
== V4SImode
&& mode2
== QImode
)
10275 type
= v4sf_ftype_v4si_int
;
10277 /* vint, vfloat, 5-bit literal. */
10278 else if (mode0
== V4SImode
&& mode1
== V4SFmode
&& mode2
== QImode
)
10279 type
= v4si_ftype_v4sf_int
;
10281 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== SImode
)
10282 type
= v2si_ftype_int_int
;
10284 else if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
10285 type
= v2si_ftype_v2si_char
;
10287 else if (mode0
== V2SImode
&& mode1
== SImode
&& mode2
== QImode
)
10288 type
= v2si_ftype_int_char
;
10293 gcc_assert (mode0
== SImode
);
10297 type
= int_ftype_v4si_v4si
;
10300 type
= int_ftype_v4sf_v4sf
;
10303 type
= int_ftype_v16qi_v16qi
;
10306 type
= int_ftype_v8hi_v8hi
;
10309 gcc_unreachable ();
10313 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10316 /* Add the simple unary operators. */
10317 d
= (struct builtin_description
*) bdesc_1arg
;
10318 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
10320 enum machine_mode mode0
, mode1
;
10322 bool is_overloaded
= d
->code
>= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10323 && d
->code
<= ALTIVEC_BUILTIN_OVERLOADED_LAST
;
10332 if (d
->name
== 0 || d
->icode
== CODE_FOR_nothing
)
10335 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
10336 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
10339 if (mode0
== V4SImode
&& mode1
== QImode
)
10340 type
= v4si_ftype_int
;
10341 else if (mode0
== V8HImode
&& mode1
== QImode
)
10342 type
= v8hi_ftype_int
;
10343 else if (mode0
== V16QImode
&& mode1
== QImode
)
10344 type
= v16qi_ftype_int
;
10345 else if (mode0
== VOIDmode
&& mode1
== VOIDmode
)
10346 type
= opaque_ftype_opaque
;
10347 else if (mode0
== V4SFmode
&& mode1
== V4SFmode
)
10348 type
= v4sf_ftype_v4sf
;
10349 else if (mode0
== V8HImode
&& mode1
== V16QImode
)
10350 type
= v8hi_ftype_v16qi
;
10351 else if (mode0
== V4SImode
&& mode1
== V8HImode
)
10352 type
= v4si_ftype_v8hi
;
10353 else if (mode0
== V2SImode
&& mode1
== V2SImode
)
10354 type
= v2si_ftype_v2si
;
10355 else if (mode0
== V2SFmode
&& mode1
== V2SFmode
)
10357 if (TARGET_PAIRED_FLOAT
)
10358 type
= v2sf_ftype_v2sf
;
10360 type
= v2sf_ftype_v2sf_spe
;
10362 else if (mode0
== V2SFmode
&& mode1
== V2SImode
)
10363 type
= v2sf_ftype_v2si
;
10364 else if (mode0
== V2SImode
&& mode1
== V2SFmode
)
10365 type
= v2si_ftype_v2sf
;
10366 else if (mode0
== V2SImode
&& mode1
== QImode
)
10367 type
= v2si_ftype_char
;
10369 gcc_unreachable ();
10371 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
10376 rs6000_init_libfuncs (void)
10378 if (DEFAULT_ABI
!= ABI_V4
&& TARGET_XCOFF
10379 && !TARGET_POWER2
&& !TARGET_POWERPC
)
10381 /* AIX library routines for float->int conversion. */
10382 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__itrunc");
10383 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__uitrunc");
10384 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_qitrunc");
10385 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_quitrunc");
10388 if (!TARGET_IEEEQUAD
)
10389 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10390 if (!TARGET_XL_COMPAT
)
10392 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
10393 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
10394 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
10395 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
10397 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
10399 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
10400 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
10401 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
10402 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
10403 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
10404 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
10405 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
10407 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
10408 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
10409 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
10410 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
10411 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
10412 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
10413 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
10414 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
10417 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
10418 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
10422 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
10423 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
10424 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
10425 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
10429 /* 32-bit SVR4 quad floating point routines. */
10431 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
10432 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
10433 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
10434 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
10435 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
10436 if (TARGET_PPC_GPOPT
|| TARGET_POWER2
)
10437 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
10439 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
10440 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
10441 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
10442 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
10443 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
10444 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
10446 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
10447 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
10448 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
10449 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
10450 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
10451 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
10452 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
10453 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
10458 /* Expand a block clear operation, and return 1 if successful. Return 0
10459 if we should let the compiler generate normal code.
10461 operands[0] is the destination
10462 operands[1] is the length
10463 operands[3] is the alignment */
10466 expand_block_clear (rtx operands
[])
10468 rtx orig_dest
= operands
[0];
10469 rtx bytes_rtx
= operands
[1];
10470 rtx align_rtx
= operands
[3];
10471 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10472 HOST_WIDE_INT align
;
10473 HOST_WIDE_INT bytes
;
10478 /* If this is not a fixed size move, just call memcpy */
10482 /* This must be a fixed size alignment */
10483 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10484 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10486 /* Anything to clear? */
10487 bytes
= INTVAL (bytes_rtx
);
10491 /* Use the builtin memset after a point, to avoid huge code bloat.
10492 When optimize_size, avoid any significant code bloat; calling
10493 memset is about 4 instructions, so allow for one instruction to
10494 load zero and three to do clearing. */
10495 if (TARGET_ALTIVEC
&& align
>= 128)
10497 else if (TARGET_POWERPC64
&& align
>= 32)
10499 else if (TARGET_SPE
&& align
>= 64)
10504 if (optimize_size
&& bytes
> 3 * clear_step
)
10506 if (! optimize_size
&& bytes
> 8 * clear_step
)
10509 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
10511 enum machine_mode mode
= BLKmode
;
10514 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
10519 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
10524 else if (bytes
>= 8 && TARGET_POWERPC64
10525 /* 64-bit loads and stores require word-aligned
10527 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
10532 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
10533 { /* move 4 bytes */
10537 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
10538 { /* move 2 bytes */
10542 else /* move 1 byte at a time */
10548 dest
= adjust_address (orig_dest
, mode
, offset
);
10550 emit_move_insn (dest
, CONST0_RTX (mode
));
10557 /* Expand a block move operation, and return 1 if successful. Return 0
10558 if we should let the compiler generate normal code.
10560 operands[0] is the destination
10561 operands[1] is the source
10562 operands[2] is the length
10563 operands[3] is the alignment */
10565 #define MAX_MOVE_REG 4
10568 expand_block_move (rtx operands
[])
10570 rtx orig_dest
= operands
[0];
10571 rtx orig_src
= operands
[1];
10572 rtx bytes_rtx
= operands
[2];
10573 rtx align_rtx
= operands
[3];
10574 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
10579 rtx stores
[MAX_MOVE_REG
];
10582 /* If this is not a fixed size move, just call memcpy */
10586 /* This must be a fixed size alignment */
10587 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
10588 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
10590 /* Anything to move? */
10591 bytes
= INTVAL (bytes_rtx
);
10595 /* store_one_arg depends on expand_block_move to handle at least the size of
10596 reg_parm_stack_space. */
10597 if (bytes
> (TARGET_POWERPC64
? 64 : 32))
10600 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
10603 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
10604 rtx (*mov
) (rtx
, rtx
);
10606 enum machine_mode mode
= BLKmode
;
10609 /* Altivec first, since it will be faster than a string move
10610 when it applies, and usually not significantly larger. */
10611 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
10615 gen_func
.mov
= gen_movv4si
;
10617 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
10621 gen_func
.mov
= gen_movv2si
;
10623 else if (TARGET_STRING
10624 && bytes
> 24 /* move up to 32 bytes at a time */
10630 && ! fixed_regs
[10]
10631 && ! fixed_regs
[11]
10632 && ! fixed_regs
[12])
10634 move_bytes
= (bytes
> 32) ? 32 : bytes
;
10635 gen_func
.movmemsi
= gen_movmemsi_8reg
;
10637 else if (TARGET_STRING
10638 && bytes
> 16 /* move up to 24 bytes at a time */
10644 && ! fixed_regs
[10])
10646 move_bytes
= (bytes
> 24) ? 24 : bytes
;
10647 gen_func
.movmemsi
= gen_movmemsi_6reg
;
10649 else if (TARGET_STRING
10650 && bytes
> 8 /* move up to 16 bytes at a time */
10654 && ! fixed_regs
[8])
10656 move_bytes
= (bytes
> 16) ? 16 : bytes
;
10657 gen_func
.movmemsi
= gen_movmemsi_4reg
;
10659 else if (bytes
>= 8 && TARGET_POWERPC64
10660 /* 64-bit loads and stores require word-aligned
10662 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
10666 gen_func
.mov
= gen_movdi
;
10668 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
10669 { /* move up to 8 bytes at a time */
10670 move_bytes
= (bytes
> 8) ? 8 : bytes
;
10671 gen_func
.movmemsi
= gen_movmemsi_2reg
;
10673 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
10674 { /* move 4 bytes */
10677 gen_func
.mov
= gen_movsi
;
10679 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
10680 { /* move 2 bytes */
10683 gen_func
.mov
= gen_movhi
;
10685 else if (TARGET_STRING
&& bytes
> 1)
10686 { /* move up to 4 bytes at a time */
10687 move_bytes
= (bytes
> 4) ? 4 : bytes
;
10688 gen_func
.movmemsi
= gen_movmemsi_1reg
;
10690 else /* move 1 byte at a time */
10694 gen_func
.mov
= gen_movqi
;
10697 src
= adjust_address (orig_src
, mode
, offset
);
10698 dest
= adjust_address (orig_dest
, mode
, offset
);
10700 if (mode
!= BLKmode
)
10702 rtx tmp_reg
= gen_reg_rtx (mode
);
10704 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
10705 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
10708 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
10711 for (i
= 0; i
< num_reg
; i
++)
10712 emit_insn (stores
[i
]);
10716 if (mode
== BLKmode
)
10718 /* Move the address into scratch registers. The movmemsi
10719 patterns require zero offset. */
10720 if (!REG_P (XEXP (src
, 0)))
10722 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
10723 src
= replace_equiv_address (src
, src_reg
);
10725 set_mem_size (src
, GEN_INT (move_bytes
));
10727 if (!REG_P (XEXP (dest
, 0)))
10729 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
10730 dest
= replace_equiv_address (dest
, dest_reg
);
10732 set_mem_size (dest
, GEN_INT (move_bytes
));
10734 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
10735 GEN_INT (move_bytes
& 31),
10744 /* Return a string to perform a load_multiple operation.
10745 operands[0] is the vector.
10746 operands[1] is the source address.
10747 operands[2] is the first destination register. */
10750 rs6000_output_load_multiple (rtx operands
[3])
10752 /* We have to handle the case where the pseudo used to contain the address
10753 is assigned to one of the output registers. */
10755 int words
= XVECLEN (operands
[0], 0);
10758 if (XVECLEN (operands
[0], 0) == 1)
10759 return "{l|lwz} %2,0(%1)";
10761 for (i
= 0; i
< words
; i
++)
10762 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
10763 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
10767 xop
[0] = GEN_INT (4 * (words
-1));
10768 xop
[1] = operands
[1];
10769 xop
[2] = operands
[2];
10770 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop
);
10775 xop
[0] = GEN_INT (4 * (words
-1));
10776 xop
[1] = operands
[1];
10777 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10778 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop
);
10783 for (j
= 0; j
< words
; j
++)
10786 xop
[0] = GEN_INT (j
* 4);
10787 xop
[1] = operands
[1];
10788 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
10789 output_asm_insn ("{l|lwz} %2,%0(%1)", xop
);
10791 xop
[0] = GEN_INT (i
* 4);
10792 xop
[1] = operands
[1];
10793 output_asm_insn ("{l|lwz} %1,%0(%1)", xop
);
10798 return "{lsi|lswi} %2,%1,%N0";
10802 /* A validation routine: say whether CODE, a condition code, and MODE
10803 match. The other alternatives either don't make sense or should
10804 never be generated. */
10807 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
10809 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
10810 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
10811 && GET_MODE_CLASS (mode
) == MODE_CC
);
10813 /* These don't make sense. */
10814 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
10815 || mode
!= CCUNSmode
);
10817 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
10818 || mode
== CCUNSmode
);
10820 gcc_assert (mode
== CCFPmode
10821 || (code
!= ORDERED
&& code
!= UNORDERED
10822 && code
!= UNEQ
&& code
!= LTGT
10823 && code
!= UNGT
&& code
!= UNLT
10824 && code
!= UNGE
&& code
!= UNLE
));
10826 /* These should never be generated except for
10827 flag_finite_math_only. */
10828 gcc_assert (mode
!= CCFPmode
10829 || flag_finite_math_only
10830 || (code
!= LE
&& code
!= GE
10831 && code
!= UNEQ
&& code
!= LTGT
10832 && code
!= UNGT
&& code
!= UNLT
));
10834 /* These are invalid; the information is not there. */
10835 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
10839 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10840 mask required to convert the result of a rotate insn into a shift
10841 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10844 includes_lshift_p (rtx shiftop
, rtx andop
)
10846 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
10848 shift_mask
<<= INTVAL (shiftop
);
10850 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
10853 /* Similar, but for right shift. */
10856 includes_rshift_p (rtx shiftop
, rtx andop
)
10858 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
10860 shift_mask
>>= INTVAL (shiftop
);
10862 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
10865 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10866 to perform a left shift. It must have exactly SHIFTOP least
10867 significant 0's, then one or more 1's, then zero or more 0's. */
10870 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
10872 if (GET_CODE (andop
) == CONST_INT
)
10874 HOST_WIDE_INT c
, lsb
, shift_mask
;
10876 c
= INTVAL (andop
);
10877 if (c
== 0 || c
== ~0)
10881 shift_mask
<<= INTVAL (shiftop
);
10883 /* Find the least significant one bit. */
10886 /* It must coincide with the LSB of the shift mask. */
10887 if (-lsb
!= shift_mask
)
10890 /* Invert to look for the next transition (if any). */
10893 /* Remove the low group of ones (originally low group of zeros). */
10896 /* Again find the lsb, and check we have all 1's above. */
10900 else if (GET_CODE (andop
) == CONST_DOUBLE
10901 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
10903 HOST_WIDE_INT low
, high
, lsb
;
10904 HOST_WIDE_INT shift_mask_low
, shift_mask_high
;
10906 low
= CONST_DOUBLE_LOW (andop
);
10907 if (HOST_BITS_PER_WIDE_INT
< 64)
10908 high
= CONST_DOUBLE_HIGH (andop
);
10910 if ((low
== 0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== 0))
10911 || (low
== ~0 && (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0)))
10914 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
10916 shift_mask_high
= ~0;
10917 if (INTVAL (shiftop
) > 32)
10918 shift_mask_high
<<= INTVAL (shiftop
) - 32;
10920 lsb
= high
& -high
;
10922 if (-lsb
!= shift_mask_high
|| INTVAL (shiftop
) < 32)
10928 lsb
= high
& -high
;
10929 return high
== -lsb
;
10932 shift_mask_low
= ~0;
10933 shift_mask_low
<<= INTVAL (shiftop
);
10937 if (-lsb
!= shift_mask_low
)
10940 if (HOST_BITS_PER_WIDE_INT
< 64)
10945 if (HOST_BITS_PER_WIDE_INT
< 64 && low
== 0)
10947 lsb
= high
& -high
;
10948 return high
== -lsb
;
10952 return low
== -lsb
&& (HOST_BITS_PER_WIDE_INT
>= 64 || high
== ~0);
10958 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10959 to perform a left shift. It must have SHIFTOP or more least
10960 significant 0's, with the remainder of the word 1's. */
10963 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
10965 if (GET_CODE (andop
) == CONST_INT
)
10967 HOST_WIDE_INT c
, lsb
, shift_mask
;
10970 shift_mask
<<= INTVAL (shiftop
);
10971 c
= INTVAL (andop
);
10973 /* Find the least significant one bit. */
10976 /* It must be covered by the shift mask.
10977 This test also rejects c == 0. */
10978 if ((lsb
& shift_mask
) == 0)
10981 /* Check we have all 1's above the transition, and reject all 1's. */
10982 return c
== -lsb
&& lsb
!= 1;
10984 else if (GET_CODE (andop
) == CONST_DOUBLE
10985 && (GET_MODE (andop
) == VOIDmode
|| GET_MODE (andop
) == DImode
))
10987 HOST_WIDE_INT low
, lsb
, shift_mask_low
;
10989 low
= CONST_DOUBLE_LOW (andop
);
10991 if (HOST_BITS_PER_WIDE_INT
< 64)
10993 HOST_WIDE_INT high
, shift_mask_high
;
10995 high
= CONST_DOUBLE_HIGH (andop
);
10999 shift_mask_high
= ~0;
11000 if (INTVAL (shiftop
) > 32)
11001 shift_mask_high
<<= INTVAL (shiftop
) - 32;
11003 lsb
= high
& -high
;
11005 if ((lsb
& shift_mask_high
) == 0)
11008 return high
== -lsb
;
11014 shift_mask_low
= ~0;
11015 shift_mask_low
<<= INTVAL (shiftop
);
11019 if ((lsb
& shift_mask_low
) == 0)
11022 return low
== -lsb
&& lsb
!= 1;
11028 /* Return 1 if operands will generate a valid arguments to rlwimi
11029 instruction for insert with right shift in 64-bit mode. The mask may
11030 not start on the first bit or stop on the last bit because wrap-around
11031 effects of instruction do not correspond to semantics of RTL insn. */
11034 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
11036 if (INTVAL (startop
) > 32
11037 && INTVAL (startop
) < 64
11038 && INTVAL (sizeop
) > 1
11039 && INTVAL (sizeop
) + INTVAL (startop
) < 64
11040 && INTVAL (shiftop
) > 0
11041 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
11042 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
11048 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
11049 for lfq and stfq insns iff the registers are hard registers. */
11052 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
11054 /* We might have been passed a SUBREG. */
11055 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
11058 /* We might have been passed non floating point registers. */
11059 if (!FP_REGNO_P (REGNO (reg1
))
11060 || !FP_REGNO_P (REGNO (reg2
)))
11063 return (REGNO (reg1
) == REGNO (reg2
) - 1);
11066 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
11067 addr1 and addr2 must be in consecutive memory locations
11068 (addr2 == addr1 + 8). */
11071 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
11074 unsigned int reg1
, reg2
;
11075 int offset1
, offset2
;
11077 /* The mems cannot be volatile. */
11078 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
11081 addr1
= XEXP (mem1
, 0);
11082 addr2
= XEXP (mem2
, 0);
11084 /* Extract an offset (if used) from the first addr. */
11085 if (GET_CODE (addr1
) == PLUS
)
11087 /* If not a REG, return zero. */
11088 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
11092 reg1
= REGNO (XEXP (addr1
, 0));
11093 /* The offset must be constant! */
11094 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
11096 offset1
= INTVAL (XEXP (addr1
, 1));
11099 else if (GET_CODE (addr1
) != REG
)
11103 reg1
= REGNO (addr1
);
11104 /* This was a simple (mem (reg)) expression. Offset is 0. */
11108 /* And now for the second addr. */
11109 if (GET_CODE (addr2
) == PLUS
)
11111 /* If not a REG, return zero. */
11112 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
11116 reg2
= REGNO (XEXP (addr2
, 0));
11117 /* The offset must be constant. */
11118 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
11120 offset2
= INTVAL (XEXP (addr2
, 1));
11123 else if (GET_CODE (addr2
) != REG
)
11127 reg2
= REGNO (addr2
);
11128 /* This was a simple (mem (reg)) expression. Offset is 0. */
11132 /* Both of these must have the same base register. */
11136 /* The offset for the second addr must be 8 more than the first addr. */
11137 if (offset2
!= offset1
+ 8)
11140 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
11147 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
11149 static bool eliminated
= false;
11150 if (mode
!= SDmode
)
11151 return assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
11154 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
11155 gcc_assert (mem
!= NULL_RTX
);
11159 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
11160 cfun
->machine
->sdmode_stack_slot
= mem
;
11168 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
11170 /* Don't walk into types. */
11171 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
11173 *walk_subtrees
= 0;
11177 switch (TREE_CODE (*tp
))
11184 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
11195 /* Allocate a 64-bit stack slot to be used for copying SDmode
11196 values through if this function has any SDmode references. */
11199 rs6000_alloc_sdmode_stack_slot (void)
11203 block_stmt_iterator bsi
;
11205 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
11208 for (bsi
= bsi_start (bb
); !bsi_end_p (bsi
); bsi_next (&bsi
))
11210 tree ret
= walk_tree_without_duplicates (bsi_stmt_ptr (bsi
),
11211 rs6000_check_sdmode
, NULL
);
11214 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
11215 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
11221 /* Check for any SDmode parameters of the function. */
11222 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= TREE_CHAIN (t
))
11224 if (TREE_TYPE (t
) == error_mark_node
)
11227 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
11228 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
11230 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
11231 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
11239 rs6000_instantiate_decls (void)
11241 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
11242 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
11245 /* Return the register class of a scratch register needed to copy IN into
11246 or out of a register in CLASS in MODE. If it can be done directly,
11247 NO_REGS is returned. */
11250 rs6000_secondary_reload_class (enum reg_class
class,
11251 enum machine_mode mode ATTRIBUTE_UNUSED
,
11256 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
11258 && MACHOPIC_INDIRECT
11262 /* We cannot copy a symbolic operand directly into anything
11263 other than BASE_REGS for TARGET_ELF. So indicate that a
11264 register from BASE_REGS is needed as an intermediate
11267 On Darwin, pic addresses require a load from memory, which
11268 needs a base register. */
11269 if (class != BASE_REGS
11270 && (GET_CODE (in
) == SYMBOL_REF
11271 || GET_CODE (in
) == HIGH
11272 || GET_CODE (in
) == LABEL_REF
11273 || GET_CODE (in
) == CONST
))
11277 if (GET_CODE (in
) == REG
)
11279 regno
= REGNO (in
);
11280 if (regno
>= FIRST_PSEUDO_REGISTER
)
11282 regno
= true_regnum (in
);
11283 if (regno
>= FIRST_PSEUDO_REGISTER
)
11287 else if (GET_CODE (in
) == SUBREG
)
11289 regno
= true_regnum (in
);
11290 if (regno
>= FIRST_PSEUDO_REGISTER
)
11296 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
11298 if (class == GENERAL_REGS
|| class == BASE_REGS
11299 || (regno
>= 0 && INT_REGNO_P (regno
)))
11302 /* Constants, memory, and FP registers can go into FP registers. */
11303 if ((regno
== -1 || FP_REGNO_P (regno
))
11304 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
11305 return (mode
!= SDmode
) ? NO_REGS
: GENERAL_REGS
;
11307 /* Memory, and AltiVec registers can go into AltiVec registers. */
11308 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
11309 && class == ALTIVEC_REGS
)
11312 /* We can copy among the CR registers. */
11313 if ((class == CR_REGS
|| class == CR0_REGS
)
11314 && regno
>= 0 && CR_REGNO_P (regno
))
11317 /* Otherwise, we need GENERAL_REGS. */
11318 return GENERAL_REGS
;
11321 /* Given a comparison operation, return the bit number in CCR to test. We
11322 know this is a valid comparison.
11324 SCC_P is 1 if this is for an scc. That means that %D will have been
11325 used instead of %C, so the bits will be in different places.
11327 Return -1 if OP isn't a valid comparison for some reason. */
11330 ccr_bit (rtx op
, int scc_p
)
11332 enum rtx_code code
= GET_CODE (op
);
11333 enum machine_mode cc_mode
;
11338 if (!COMPARISON_P (op
))
11341 reg
= XEXP (op
, 0);
11343 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
11345 cc_mode
= GET_MODE (reg
);
11346 cc_regnum
= REGNO (reg
);
11347 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
11349 validate_condition_mode (code
, cc_mode
);
11351 /* When generating a sCOND operation, only positive conditions are
11354 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
11355 || code
== GTU
|| code
== LTU
);
11360 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
11362 return base_bit
+ 2;
11363 case GT
: case GTU
: case UNLE
:
11364 return base_bit
+ 1;
11365 case LT
: case LTU
: case UNGE
:
11367 case ORDERED
: case UNORDERED
:
11368 return base_bit
+ 3;
11371 /* If scc, we will have done a cror to put the bit in the
11372 unordered position. So test that bit. For integer, this is ! LT
11373 unless this is an scc insn. */
11374 return scc_p
? base_bit
+ 3 : base_bit
;
11377 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
11380 gcc_unreachable ();
11384 /* Return the GOT register. */
11387 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
11389 /* The second flow pass currently (June 1999) can't update
11390 regs_ever_live without disturbing other parts of the compiler, so
11391 update it here to make the prolog/epilogue code happy. */
11392 if (!can_create_pseudo_p ()
11393 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
11394 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
11396 current_function_uses_pic_offset_table
= 1;
11398 return pic_offset_table_rtx
;
11401 /* Function to init struct machine_function.
11402 This will be called, via a pointer variable,
11403 from push_function_context. */
11405 static struct machine_function
*
11406 rs6000_init_machine_status (void)
11408 return ggc_alloc_cleared (sizeof (machine_function
));
11411 /* These macros test for integers and extract the low-order bits. */
11413 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11414 && GET_MODE (X) == VOIDmode)
11416 #define INT_LOWPART(X) \
11417 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11420 extract_MB (rtx op
)
11423 unsigned long val
= INT_LOWPART (op
);
11425 /* If the high bit is zero, the value is the first 1 bit we find
11427 if ((val
& 0x80000000) == 0)
11429 gcc_assert (val
& 0xffffffff);
11432 while (((val
<<= 1) & 0x80000000) == 0)
11437 /* If the high bit is set and the low bit is not, or the mask is all
11438 1's, the value is zero. */
11439 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
11442 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11445 while (((val
>>= 1) & 1) != 0)
11452 extract_ME (rtx op
)
11455 unsigned long val
= INT_LOWPART (op
);
11457 /* If the low bit is zero, the value is the first 1 bit we find from
11459 if ((val
& 1) == 0)
11461 gcc_assert (val
& 0xffffffff);
11464 while (((val
>>= 1) & 1) == 0)
11470 /* If the low bit is set and the high bit is not, or the mask is all
11471 1's, the value is 31. */
11472 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
11475 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11478 while (((val
<<= 1) & 0x80000000) != 0)
11484 /* Locate some local-dynamic symbol still in use by this function
11485 so that we can print its name in some tls_ld pattern. */
11487 static const char *
11488 rs6000_get_some_local_dynamic_name (void)
11492 if (cfun
->machine
->some_ld_name
)
11493 return cfun
->machine
->some_ld_name
;
11495 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11497 && for_each_rtx (&PATTERN (insn
),
11498 rs6000_get_some_local_dynamic_name_1
, 0))
11499 return cfun
->machine
->some_ld_name
;
11501 gcc_unreachable ();
11504 /* Helper function for rs6000_get_some_local_dynamic_name. */
11507 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
11511 if (GET_CODE (x
) == SYMBOL_REF
)
11513 const char *str
= XSTR (x
, 0);
11514 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
11516 cfun
->machine
->some_ld_name
= str
;
11524 /* Write out a function code label. */
11527 rs6000_output_function_entry (FILE *file
, const char *fname
)
11529 if (fname
[0] != '.')
11531 switch (DEFAULT_ABI
)
11534 gcc_unreachable ();
11540 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
11549 RS6000_OUTPUT_BASENAME (file
, fname
);
11551 assemble_name (file
, fname
);
11554 /* Print an operand. Recognize special options, documented below. */
11557 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11558 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11560 #define SMALL_DATA_RELOC "sda21"
11561 #define SMALL_DATA_REG 0
11565 print_operand (FILE *file
, rtx x
, int code
)
11569 unsigned HOST_WIDE_INT uval
;
11574 /* Write out an instruction after the call which may be replaced
11575 with glue code by the loader. This depends on the AIX version. */
11576 asm_fprintf (file
, RS6000_CALL_GLUE
);
11579 /* %a is output_address. */
11582 /* If X is a constant integer whose low-order 5 bits are zero,
11583 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11584 in the AIX assembler where "sri" with a zero shift count
11585 writes a trash instruction. */
11586 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
11593 /* If constant, low-order 16 bits of constant, unsigned.
11594 Otherwise, write normally. */
11596 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 0xffff);
11598 print_operand (file
, x
, 0);
11602 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11603 for 64-bit mask direction. */
11604 putc (((INT_LOWPART (x
) & 1) == 0 ? 'r' : 'l'), file
);
11607 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11611 /* X is a CR register. Print the number of the GT bit of the CR. */
11612 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11613 output_operand_lossage ("invalid %%E value");
11615 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 1);
11619 /* Like 'J' but get to the GT bit only. */
11620 gcc_assert (GET_CODE (x
) == REG
);
11622 /* Bit 1 is GT bit. */
11623 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
11625 /* Add one for shift count in rlinm for scc. */
11626 fprintf (file
, "%d", i
+ 1);
11630 /* X is a CR register. Print the number of the EQ bit of the CR */
11631 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11632 output_operand_lossage ("invalid %%E value");
11634 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
11638 /* X is a CR register. Print the shift count needed to move it
11639 to the high-order four bits. */
11640 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11641 output_operand_lossage ("invalid %%f value");
11643 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
11647 /* Similar, but print the count for the rotate in the opposite
11649 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11650 output_operand_lossage ("invalid %%F value");
11652 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
11656 /* X is a constant integer. If it is negative, print "m",
11657 otherwise print "z". This is to make an aze or ame insn. */
11658 if (GET_CODE (x
) != CONST_INT
)
11659 output_operand_lossage ("invalid %%G value");
11660 else if (INTVAL (x
) >= 0)
11667 /* If constant, output low-order five bits. Otherwise, write
11670 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 31);
11672 print_operand (file
, x
, 0);
11676 /* If constant, output low-order six bits. Otherwise, write
11679 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INT_LOWPART (x
) & 63);
11681 print_operand (file
, x
, 0);
11685 /* Print `i' if this is a constant, else nothing. */
11691 /* Write the bit number in CCR for jump. */
11692 i
= ccr_bit (x
, 0);
11694 output_operand_lossage ("invalid %%j code");
11696 fprintf (file
, "%d", i
);
11700 /* Similar, but add one for shift count in rlinm for scc and pass
11701 scc flag to `ccr_bit'. */
11702 i
= ccr_bit (x
, 1);
11704 output_operand_lossage ("invalid %%J code");
11706 /* If we want bit 31, write a shift count of zero, not 32. */
11707 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
11711 /* X must be a constant. Write the 1's complement of the
11714 output_operand_lossage ("invalid %%k value");
11716 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INT_LOWPART (x
));
11720 /* X must be a symbolic constant on ELF. Write an
11721 expression suitable for an 'addi' that adds in the low 16
11722 bits of the MEM. */
11723 if (GET_CODE (x
) != CONST
)
11725 print_operand_address (file
, x
);
11726 fputs ("@l", file
);
11730 if (GET_CODE (XEXP (x
, 0)) != PLUS
11731 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
11732 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
11733 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
11734 output_operand_lossage ("invalid %%K value");
11735 print_operand_address (file
, XEXP (XEXP (x
, 0), 0));
11736 fputs ("@l", file
);
11737 /* For GNU as, there must be a non-alphanumeric character
11738 between 'l' and the number. The '-' is added by
11739 print_operand() already. */
11740 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
11742 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
11746 /* %l is output_asm_label. */
11749 /* Write second word of DImode or DFmode reference. Works on register
11750 or non-indexed memory only. */
11751 if (GET_CODE (x
) == REG
)
11752 fputs (reg_names
[REGNO (x
) + 1], file
);
11753 else if (GET_CODE (x
) == MEM
)
11755 /* Handle possible auto-increment. Since it is pre-increment and
11756 we have already done it, we can just use an offset of word. */
11757 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
11758 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
11759 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
11761 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
11762 output_address (plus_constant (XEXP (XEXP (x
, 0), 0),
11765 output_address (XEXP (adjust_address_nv (x
, SImode
,
11769 if (small_data_operand (x
, GET_MODE (x
)))
11770 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
11771 reg_names
[SMALL_DATA_REG
]);
11776 /* MB value for a mask operand. */
11777 if (! mask_operand (x
, SImode
))
11778 output_operand_lossage ("invalid %%m value");
11780 fprintf (file
, "%d", extract_MB (x
));
11784 /* ME value for a mask operand. */
11785 if (! mask_operand (x
, SImode
))
11786 output_operand_lossage ("invalid %%M value");
11788 fprintf (file
, "%d", extract_ME (x
));
11791 /* %n outputs the negative of its operand. */
11794 /* Write the number of elements in the vector times 4. */
11795 if (GET_CODE (x
) != PARALLEL
)
11796 output_operand_lossage ("invalid %%N value");
11798 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
11802 /* Similar, but subtract 1 first. */
11803 if (GET_CODE (x
) != PARALLEL
)
11804 output_operand_lossage ("invalid %%O value");
11806 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
11810 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11812 || INT_LOWPART (x
) < 0
11813 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
11814 output_operand_lossage ("invalid %%p value");
11816 fprintf (file
, "%d", i
);
11820 /* The operand must be an indirect memory reference. The result
11821 is the register name. */
11822 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
11823 || REGNO (XEXP (x
, 0)) >= 32)
11824 output_operand_lossage ("invalid %%P value");
11826 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
11830 /* This outputs the logical code corresponding to a boolean
11831 expression. The expression may have one or both operands
11832 negated (if one, only the first one). For condition register
11833 logical operations, it will also treat the negated
11834 CR codes as NOTs, but not handle NOTs of them. */
11836 const char *const *t
= 0;
11838 enum rtx_code code
= GET_CODE (x
);
11839 static const char * const tbl
[3][3] = {
11840 { "and", "andc", "nor" },
11841 { "or", "orc", "nand" },
11842 { "xor", "eqv", "xor" } };
11846 else if (code
== IOR
)
11848 else if (code
== XOR
)
11851 output_operand_lossage ("invalid %%q value");
11853 if (GET_CODE (XEXP (x
, 0)) != NOT
)
11857 if (GET_CODE (XEXP (x
, 1)) == NOT
)
11875 /* X is a CR register. Print the mask for `mtcrf'. */
11876 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
11877 output_operand_lossage ("invalid %%R value");
11879 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
11883 /* Low 5 bits of 32 - value */
11885 output_operand_lossage ("invalid %%s value");
11887 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INT_LOWPART (x
)) & 31);
11891 /* PowerPC64 mask position. All 0's is excluded.
11892 CONST_INT 32-bit mask is considered sign-extended so any
11893 transition must occur within the CONST_INT, not on the boundary. */
11894 if (! mask64_operand (x
, DImode
))
11895 output_operand_lossage ("invalid %%S value");
11897 uval
= INT_LOWPART (x
);
11899 if (uval
& 1) /* Clear Left */
11901 #if HOST_BITS_PER_WIDE_INT > 64
11902 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
11906 else /* Clear Right */
11909 #if HOST_BITS_PER_WIDE_INT > 64
11910 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
11916 gcc_assert (i
>= 0);
11917 fprintf (file
, "%d", i
);
11921 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11922 gcc_assert (GET_CODE (x
) == REG
&& GET_MODE (x
) == CCmode
);
11924 /* Bit 3 is OV bit. */
11925 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
11927 /* If we want bit 31, write a shift count of zero, not 32. */
11928 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
11932 /* Print the symbolic name of a branch target register. */
11933 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
11934 && REGNO (x
) != CTR_REGNO
))
11935 output_operand_lossage ("invalid %%T value");
11936 else if (REGNO (x
) == LR_REGNO
)
11937 fputs (TARGET_NEW_MNEMONICS
? "lr" : "r", file
);
11939 fputs ("ctr", file
);
11943 /* High-order 16 bits of constant for use in unsigned operand. */
11945 output_operand_lossage ("invalid %%u value");
11947 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
11948 (INT_LOWPART (x
) >> 16) & 0xffff);
11952 /* High-order 16 bits of constant for use in signed operand. */
11954 output_operand_lossage ("invalid %%v value");
11956 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
11957 (INT_LOWPART (x
) >> 16) & 0xffff);
11961 /* Print `u' if this has an auto-increment or auto-decrement. */
11962 if (GET_CODE (x
) == MEM
11963 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
11964 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
11965 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
11970 /* Print the trap code for this operand. */
11971 switch (GET_CODE (x
))
11974 fputs ("eq", file
); /* 4 */
11977 fputs ("ne", file
); /* 24 */
11980 fputs ("lt", file
); /* 16 */
11983 fputs ("le", file
); /* 20 */
11986 fputs ("gt", file
); /* 8 */
11989 fputs ("ge", file
); /* 12 */
11992 fputs ("llt", file
); /* 2 */
11995 fputs ("lle", file
); /* 6 */
11998 fputs ("lgt", file
); /* 1 */
12001 fputs ("lge", file
); /* 5 */
12004 gcc_unreachable ();
12009 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
12012 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
12013 ((INT_LOWPART (x
) & 0xffff) ^ 0x8000) - 0x8000);
12015 print_operand (file
, x
, 0);
12019 /* MB value for a PowerPC64 rldic operand. */
12020 val
= (GET_CODE (x
) == CONST_INT
12021 ? INTVAL (x
) : CONST_DOUBLE_HIGH (x
));
12026 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
++)
12027 if ((val
<<= 1) < 0)
12030 #if HOST_BITS_PER_WIDE_INT == 32
12031 if (GET_CODE (x
) == CONST_INT
&& i
>= 0)
12032 i
+= 32; /* zero-extend high-part was all 0's */
12033 else if (GET_CODE (x
) == CONST_DOUBLE
&& i
== 32)
12035 val
= CONST_DOUBLE_LOW (x
);
12041 for ( ; i
< 64; i
++)
12042 if ((val
<<= 1) < 0)
12047 fprintf (file
, "%d", i
+ 1);
12051 if (GET_CODE (x
) == MEM
12052 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
12053 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
12054 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
12059 /* Like 'L', for third word of TImode */
12060 if (GET_CODE (x
) == REG
)
12061 fputs (reg_names
[REGNO (x
) + 2], file
);
12062 else if (GET_CODE (x
) == MEM
)
12064 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
12065 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12066 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
12067 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12068 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
12070 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
12071 if (small_data_operand (x
, GET_MODE (x
)))
12072 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12073 reg_names
[SMALL_DATA_REG
]);
12078 /* X is a SYMBOL_REF. Write out the name preceded by a
12079 period and without any trailing data in brackets. Used for function
12080 names. If we are configured for System V (or the embedded ABI) on
12081 the PowerPC, do not emit the period, since those systems do not use
12082 TOCs and the like. */
12083 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
12085 /* Mark the decl as referenced so that cgraph will output the
12087 if (SYMBOL_REF_DECL (x
))
12088 mark_decl_referenced (SYMBOL_REF_DECL (x
));
12090 /* For macho, check to see if we need a stub. */
12093 const char *name
= XSTR (x
, 0);
12095 if (MACHOPIC_INDIRECT
12096 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
12097 name
= machopic_indirection_name (x
, /*stub_p=*/true);
12099 assemble_name (file
, name
);
12101 else if (!DOT_SYMBOLS
)
12102 assemble_name (file
, XSTR (x
, 0));
12104 rs6000_output_function_entry (file
, XSTR (x
, 0));
12108 /* Like 'L', for last word of TImode. */
12109 if (GET_CODE (x
) == REG
)
12110 fputs (reg_names
[REGNO (x
) + 3], file
);
12111 else if (GET_CODE (x
) == MEM
)
12113 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
12114 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12115 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
12116 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12117 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
12119 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
12120 if (small_data_operand (x
, GET_MODE (x
)))
12121 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12122 reg_names
[SMALL_DATA_REG
]);
12126 /* Print AltiVec or SPE memory operand. */
12131 gcc_assert (GET_CODE (x
) == MEM
);
12135 /* Ugly hack because %y is overloaded. */
12136 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
12137 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
12138 || GET_MODE (x
) == TFmode
12139 || GET_MODE (x
) == TImode
))
12141 /* Handle [reg]. */
12142 if (GET_CODE (tmp
) == REG
)
12144 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
12147 /* Handle [reg+UIMM]. */
12148 else if (GET_CODE (tmp
) == PLUS
&&
12149 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
12153 gcc_assert (GET_CODE (XEXP (tmp
, 0)) == REG
);
12155 x
= INTVAL (XEXP (tmp
, 1));
12156 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
12160 /* Fall through. Must be [reg+reg]. */
12163 && GET_CODE (tmp
) == AND
12164 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
12165 && INTVAL (XEXP (tmp
, 1)) == -16)
12166 tmp
= XEXP (tmp
, 0);
12167 if (GET_CODE (tmp
) == REG
)
12168 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
12171 gcc_assert (GET_CODE (tmp
) == PLUS
12172 && REG_P (XEXP (tmp
, 0))
12173 && REG_P (XEXP (tmp
, 1)));
12175 if (REGNO (XEXP (tmp
, 0)) == 0)
12176 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
12177 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
12179 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
12180 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
12186 if (GET_CODE (x
) == REG
)
12187 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
12188 else if (GET_CODE (x
) == MEM
)
12190 /* We need to handle PRE_INC and PRE_DEC here, since we need to
12191 know the width from the mode. */
12192 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
12193 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
12194 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
12195 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
12196 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
12197 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
12198 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
12199 output_address (XEXP (XEXP (x
, 0), 1));
12201 output_address (XEXP (x
, 0));
12204 output_addr_const (file
, x
);
12208 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
12212 output_operand_lossage ("invalid %%xn code");
12216 /* Print the address of an operand. */
12219 print_operand_address (FILE *file
, rtx x
)
12221 if (GET_CODE (x
) == REG
)
12222 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
12223 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
12224 || GET_CODE (x
) == LABEL_REF
)
12226 output_addr_const (file
, x
);
12227 if (small_data_operand (x
, GET_MODE (x
)))
12228 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
12229 reg_names
[SMALL_DATA_REG
]);
12231 gcc_assert (!TARGET_TOC
);
12233 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
12235 gcc_assert (REG_P (XEXP (x
, 0)));
12236 if (REGNO (XEXP (x
, 0)) == 0)
12237 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
12238 reg_names
[ REGNO (XEXP (x
, 0)) ]);
12240 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
12241 reg_names
[ REGNO (XEXP (x
, 1)) ]);
12243 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
12244 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
12245 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
12247 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
12248 && CONSTANT_P (XEXP (x
, 1)))
12250 output_addr_const (file
, XEXP (x
, 1));
12251 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
12255 else if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == REG
12256 && CONSTANT_P (XEXP (x
, 1)))
12258 fprintf (file
, "lo16(");
12259 output_addr_const (file
, XEXP (x
, 1));
12260 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
12263 else if (legitimate_constant_pool_address_p (x
))
12265 if (TARGET_AIX
&& (!TARGET_ELF
|| !TARGET_MINIMAL_TOC
))
12267 rtx contains_minus
= XEXP (x
, 1);
12271 /* Find the (minus (sym) (toc)) buried in X, and temporarily
12272 turn it into (sym) for output_addr_const. */
12273 while (GET_CODE (XEXP (contains_minus
, 0)) != MINUS
)
12274 contains_minus
= XEXP (contains_minus
, 0);
12276 minus
= XEXP (contains_minus
, 0);
12277 symref
= XEXP (minus
, 0);
12278 XEXP (contains_minus
, 0) = symref
;
12283 name
= XSTR (symref
, 0);
12284 newname
= alloca (strlen (name
) + sizeof ("@toc"));
12285 strcpy (newname
, name
);
12286 strcat (newname
, "@toc");
12287 XSTR (symref
, 0) = newname
;
12289 output_addr_const (file
, XEXP (x
, 1));
12291 XSTR (symref
, 0) = name
;
12292 XEXP (contains_minus
, 0) = minus
;
12295 output_addr_const (file
, XEXP (x
, 1));
12297 fprintf (file
, "(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
12300 gcc_unreachable ();
12303 /* Target hook for assembling integer objects. The PowerPC version has
12304 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
12305 is defined. It also needs to handle DI-mode objects on 64-bit
12309 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
12311 #ifdef RELOCATABLE_NEEDS_FIXUP
12312 /* Special handling for SI values. */
12313 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
12315 static int recurse
= 0;
12317 /* For -mrelocatable, we mark all addresses that need to be fixed up
12318 in the .fixup section. */
12319 if (TARGET_RELOCATABLE
12320 && in_section
!= toc_section
12321 && in_section
!= text_section
12322 && !unlikely_text_section_p (in_section
)
12324 && GET_CODE (x
) != CONST_INT
12325 && GET_CODE (x
) != CONST_DOUBLE
12331 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
12333 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
12334 fprintf (asm_out_file
, "\t.long\t(");
12335 output_addr_const (asm_out_file
, x
);
12336 fprintf (asm_out_file
, ")@fixup\n");
12337 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
12338 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
12339 fprintf (asm_out_file
, "\t.long\t");
12340 assemble_name (asm_out_file
, buf
);
12341 fprintf (asm_out_file
, "\n\t.previous\n");
12345 /* Remove initial .'s to turn a -mcall-aixdesc function
12346 address into the address of the descriptor, not the function
12348 else if (GET_CODE (x
) == SYMBOL_REF
12349 && XSTR (x
, 0)[0] == '.'
12350 && DEFAULT_ABI
== ABI_AIX
)
12352 const char *name
= XSTR (x
, 0);
12353 while (*name
== '.')
12356 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
12360 #endif /* RELOCATABLE_NEEDS_FIXUP */
12361 return default_assemble_integer (x
, size
, aligned_p
);
12364 #ifdef HAVE_GAS_HIDDEN
12365 /* Emit an assembler directive to set symbol visibility for DECL to
12366 VISIBILITY_TYPE. */
12369 rs6000_assemble_visibility (tree decl
, int vis
)
12371 /* Functions need to have their entry point symbol visibility set as
12372 well as their descriptor symbol visibility. */
12373 if (DEFAULT_ABI
== ABI_AIX
12375 && TREE_CODE (decl
) == FUNCTION_DECL
)
12377 static const char * const visibility_types
[] = {
12378 NULL
, "internal", "hidden", "protected"
12381 const char *name
, *type
;
12383 name
= ((* targetm
.strip_name_encoding
)
12384 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
12385 type
= visibility_types
[vis
];
12387 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
12388 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
12391 default_assemble_visibility (decl
, vis
);
12396 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
12398 /* Reversal of FP compares takes care -- an ordered compare
12399 becomes an unordered compare and vice versa. */
12400 if (mode
== CCFPmode
12401 && (!flag_finite_math_only
12402 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
12403 || code
== UNEQ
|| code
== LTGT
))
12404 return reverse_condition_maybe_unordered (code
);
12406 return reverse_condition (code
);
12409 /* Generate a compare for CODE. Return a brand-new rtx that
12410 represents the result of the compare. */
12413 rs6000_generate_compare (enum rtx_code code
)
12415 enum machine_mode comp_mode
;
12416 rtx compare_result
;
12418 if (rs6000_compare_fp_p
)
12419 comp_mode
= CCFPmode
;
12420 else if (code
== GTU
|| code
== LTU
12421 || code
== GEU
|| code
== LEU
)
12422 comp_mode
= CCUNSmode
;
12423 else if ((code
== EQ
|| code
== NE
)
12424 && GET_CODE (rs6000_compare_op0
) == SUBREG
12425 && GET_CODE (rs6000_compare_op1
) == SUBREG
12426 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0
)
12427 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1
))
12428 /* These are unsigned values, perhaps there will be a later
12429 ordering compare that can be shared with this one.
12430 Unfortunately we cannot detect the signedness of the operands
12431 for non-subregs. */
12432 comp_mode
= CCUNSmode
;
12434 comp_mode
= CCmode
;
12436 /* First, the compare. */
12437 compare_result
= gen_reg_rtx (comp_mode
);
12439 /* E500 FP compare instructions on the GPRs. Yuck! */
12440 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
12441 && rs6000_compare_fp_p
)
12443 rtx cmp
, or_result
, compare_result2
;
12444 enum machine_mode op_mode
= GET_MODE (rs6000_compare_op0
);
12446 if (op_mode
== VOIDmode
)
12447 op_mode
= GET_MODE (rs6000_compare_op1
);
12449 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12450 This explains the following mess. */
12454 case EQ
: case UNEQ
: case NE
: case LTGT
:
12458 cmp
= flag_unsafe_math_optimizations
12459 ? gen_tstsfeq_gpr (compare_result
, rs6000_compare_op0
,
12460 rs6000_compare_op1
)
12461 : gen_cmpsfeq_gpr (compare_result
, rs6000_compare_op0
,
12462 rs6000_compare_op1
);
12466 cmp
= flag_unsafe_math_optimizations
12467 ? gen_tstdfeq_gpr (compare_result
, rs6000_compare_op0
,
12468 rs6000_compare_op1
)
12469 : gen_cmpdfeq_gpr (compare_result
, rs6000_compare_op0
,
12470 rs6000_compare_op1
);
12474 cmp
= flag_unsafe_math_optimizations
12475 ? gen_tsttfeq_gpr (compare_result
, rs6000_compare_op0
,
12476 rs6000_compare_op1
)
12477 : gen_cmptfeq_gpr (compare_result
, rs6000_compare_op0
,
12478 rs6000_compare_op1
);
12482 gcc_unreachable ();
12486 case GT
: case GTU
: case UNGT
: case UNGE
: case GE
: case GEU
:
12490 cmp
= flag_unsafe_math_optimizations
12491 ? gen_tstsfgt_gpr (compare_result
, rs6000_compare_op0
,
12492 rs6000_compare_op1
)
12493 : gen_cmpsfgt_gpr (compare_result
, rs6000_compare_op0
,
12494 rs6000_compare_op1
);
12498 cmp
= flag_unsafe_math_optimizations
12499 ? gen_tstdfgt_gpr (compare_result
, rs6000_compare_op0
,
12500 rs6000_compare_op1
)
12501 : gen_cmpdfgt_gpr (compare_result
, rs6000_compare_op0
,
12502 rs6000_compare_op1
);
12506 cmp
= flag_unsafe_math_optimizations
12507 ? gen_tsttfgt_gpr (compare_result
, rs6000_compare_op0
,
12508 rs6000_compare_op1
)
12509 : gen_cmptfgt_gpr (compare_result
, rs6000_compare_op0
,
12510 rs6000_compare_op1
);
12514 gcc_unreachable ();
12518 case LT
: case LTU
: case UNLT
: case UNLE
: case LE
: case LEU
:
12522 cmp
= flag_unsafe_math_optimizations
12523 ? gen_tstsflt_gpr (compare_result
, rs6000_compare_op0
,
12524 rs6000_compare_op1
)
12525 : gen_cmpsflt_gpr (compare_result
, rs6000_compare_op0
,
12526 rs6000_compare_op1
);
12530 cmp
= flag_unsafe_math_optimizations
12531 ? gen_tstdflt_gpr (compare_result
, rs6000_compare_op0
,
12532 rs6000_compare_op1
)
12533 : gen_cmpdflt_gpr (compare_result
, rs6000_compare_op0
,
12534 rs6000_compare_op1
);
12538 cmp
= flag_unsafe_math_optimizations
12539 ? gen_tsttflt_gpr (compare_result
, rs6000_compare_op0
,
12540 rs6000_compare_op1
)
12541 : gen_cmptflt_gpr (compare_result
, rs6000_compare_op0
,
12542 rs6000_compare_op1
);
12546 gcc_unreachable ();
12550 gcc_unreachable ();
12553 /* Synthesize LE and GE from LT/GT || EQ. */
12554 if (code
== LE
|| code
== GE
|| code
== LEU
|| code
== GEU
)
12560 case LE
: code
= LT
; break;
12561 case GE
: code
= GT
; break;
12562 case LEU
: code
= LT
; break;
12563 case GEU
: code
= GT
; break;
12564 default: gcc_unreachable ();
12567 compare_result2
= gen_reg_rtx (CCFPmode
);
12573 cmp
= flag_unsafe_math_optimizations
12574 ? gen_tstsfeq_gpr (compare_result2
, rs6000_compare_op0
,
12575 rs6000_compare_op1
)
12576 : gen_cmpsfeq_gpr (compare_result2
, rs6000_compare_op0
,
12577 rs6000_compare_op1
);
12581 cmp
= flag_unsafe_math_optimizations
12582 ? gen_tstdfeq_gpr (compare_result2
, rs6000_compare_op0
,
12583 rs6000_compare_op1
)
12584 : gen_cmpdfeq_gpr (compare_result2
, rs6000_compare_op0
,
12585 rs6000_compare_op1
);
12589 cmp
= flag_unsafe_math_optimizations
12590 ? gen_tsttfeq_gpr (compare_result2
, rs6000_compare_op0
,
12591 rs6000_compare_op1
)
12592 : gen_cmptfeq_gpr (compare_result2
, rs6000_compare_op0
,
12593 rs6000_compare_op1
);
12597 gcc_unreachable ();
12601 /* OR them together. */
12602 or_result
= gen_reg_rtx (CCFPmode
);
12603 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
12605 compare_result
= or_result
;
12610 if (code
== NE
|| code
== LTGT
)
12620 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12621 CLOBBERs to match cmptf_internal2 pattern. */
12622 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
12623 && GET_MODE (rs6000_compare_op0
) == TFmode
12624 && !TARGET_IEEEQUAD
12625 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
12626 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
12628 gen_rtx_SET (VOIDmode
,
12630 gen_rtx_COMPARE (comp_mode
,
12631 rs6000_compare_op0
,
12632 rs6000_compare_op1
)),
12633 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12634 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12635 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12636 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12637 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12638 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12639 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
12640 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)))));
12641 else if (GET_CODE (rs6000_compare_op1
) == UNSPEC
12642 && XINT (rs6000_compare_op1
, 1) == UNSPEC_SP_TEST
)
12644 rtx op1
= XVECEXP (rs6000_compare_op1
, 0, 0);
12645 comp_mode
= CCEQmode
;
12646 compare_result
= gen_reg_rtx (CCEQmode
);
12648 emit_insn (gen_stack_protect_testdi (compare_result
,
12649 rs6000_compare_op0
, op1
));
12651 emit_insn (gen_stack_protect_testsi (compare_result
,
12652 rs6000_compare_op0
, op1
));
12655 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
12656 gen_rtx_COMPARE (comp_mode
,
12657 rs6000_compare_op0
,
12658 rs6000_compare_op1
)));
12661 /* Some kinds of FP comparisons need an OR operation;
12662 under flag_finite_math_only we don't bother. */
12663 if (rs6000_compare_fp_p
12664 && !flag_finite_math_only
12665 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
12666 && (code
== LE
|| code
== GE
12667 || code
== UNEQ
|| code
== LTGT
12668 || code
== UNGT
|| code
== UNLT
))
12670 enum rtx_code or1
, or2
;
12671 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
12672 rtx or_result
= gen_reg_rtx (CCEQmode
);
12676 case LE
: or1
= LT
; or2
= EQ
; break;
12677 case GE
: or1
= GT
; or2
= EQ
; break;
12678 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
12679 case LTGT
: or1
= LT
; or2
= GT
; break;
12680 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
12681 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
12682 default: gcc_unreachable ();
12684 validate_condition_mode (or1
, comp_mode
);
12685 validate_condition_mode (or2
, comp_mode
);
12686 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
12687 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
12688 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
12689 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
12691 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
12693 compare_result
= or_result
;
12697 validate_condition_mode (code
, GET_MODE (compare_result
));
12699 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
12703 /* Emit the RTL for an sCOND pattern. */
12706 rs6000_emit_sCOND (enum rtx_code code
, rtx result
)
12709 enum machine_mode op_mode
;
12710 enum rtx_code cond_code
;
12712 condition_rtx
= rs6000_generate_compare (code
);
12713 cond_code
= GET_CODE (condition_rtx
);
12715 if (rs6000_compare_fp_p
12716 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
12720 PUT_MODE (condition_rtx
, SImode
);
12721 t
= XEXP (condition_rtx
, 0);
12723 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
12725 if (cond_code
== NE
)
12726 emit_insn (gen_e500_flip_gt_bit (t
, t
));
12728 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
12732 if (cond_code
== NE
12733 || cond_code
== GE
|| cond_code
== LE
12734 || cond_code
== GEU
|| cond_code
== LEU
12735 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
12737 rtx not_result
= gen_reg_rtx (CCEQmode
);
12738 rtx not_op
, rev_cond_rtx
;
12739 enum machine_mode cc_mode
;
12741 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
12743 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
12744 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
12745 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
12746 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
12747 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
12750 op_mode
= GET_MODE (rs6000_compare_op0
);
12751 if (op_mode
== VOIDmode
)
12752 op_mode
= GET_MODE (rs6000_compare_op1
);
12754 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| rs6000_compare_fp_p
))
12756 PUT_MODE (condition_rtx
, DImode
);
12757 convert_move (result
, condition_rtx
, 0);
12761 PUT_MODE (condition_rtx
, SImode
);
12762 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
12766 /* Emit a branch of kind CODE to location LOC. */
12769 rs6000_emit_cbranch (enum rtx_code code
, rtx loc
)
12771 rtx condition_rtx
, loc_ref
;
12773 condition_rtx
= rs6000_generate_compare (code
);
12774 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, loc
);
12775 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
12776 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
12777 loc_ref
, pc_rtx
)));
12780 /* Return the string to output a conditional branch to LABEL, which is
12781 the operand number of the label, or -1 if the branch is really a
12782 conditional return.
12784 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12785 condition code register and its mode specifies what kind of
12786 comparison we made.
12788 REVERSED is nonzero if we should reverse the sense of the comparison.
12790 INSN is the insn. */
12793 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
12795 static char string
[64];
12796 enum rtx_code code
= GET_CODE (op
);
12797 rtx cc_reg
= XEXP (op
, 0);
12798 enum machine_mode mode
= GET_MODE (cc_reg
);
12799 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
12800 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
12801 int really_reversed
= reversed
^ need_longbranch
;
12807 validate_condition_mode (code
, mode
);
12809 /* Work out which way this really branches. We could use
12810 reverse_condition_maybe_unordered here always but this
12811 makes the resulting assembler clearer. */
12812 if (really_reversed
)
12814 /* Reversal of FP compares takes care -- an ordered compare
12815 becomes an unordered compare and vice versa. */
12816 if (mode
== CCFPmode
)
12817 code
= reverse_condition_maybe_unordered (code
);
12819 code
= reverse_condition (code
);
12822 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
12824 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12829 /* Opposite of GT. */
12838 gcc_unreachable ();
12844 /* Not all of these are actually distinct opcodes, but
12845 we distinguish them for clarity of the resulting assembler. */
12846 case NE
: case LTGT
:
12847 ccode
= "ne"; break;
12848 case EQ
: case UNEQ
:
12849 ccode
= "eq"; break;
12851 ccode
= "ge"; break;
12852 case GT
: case GTU
: case UNGT
:
12853 ccode
= "gt"; break;
12855 ccode
= "le"; break;
12856 case LT
: case LTU
: case UNLT
:
12857 ccode
= "lt"; break;
12858 case UNORDERED
: ccode
= "un"; break;
12859 case ORDERED
: ccode
= "nu"; break;
12860 case UNGE
: ccode
= "nl"; break;
12861 case UNLE
: ccode
= "ng"; break;
12863 gcc_unreachable ();
12866 /* Maybe we have a guess as to how likely the branch is.
12867 The old mnemonics don't have a way to specify this information. */
12869 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
12870 if (note
!= NULL_RTX
)
12872 /* PROB is the difference from 50%. */
12873 int prob
= INTVAL (XEXP (note
, 0)) - REG_BR_PROB_BASE
/ 2;
12875 /* Only hint for highly probable/improbable branches on newer
12876 cpus as static prediction overrides processor dynamic
12877 prediction. For older cpus we may as well always hint, but
12878 assume not taken for branches that are very close to 50% as a
12879 mispredicted taken branch is more expensive than a
12880 mispredicted not-taken branch. */
12881 if (rs6000_always_hint
12882 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
12883 && br_prob_note_reliable_p (note
)))
12885 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
12886 && ((prob
> 0) ^ need_longbranch
))
12894 s
+= sprintf (s
, "{b%sr|b%slr%s} ", ccode
, ccode
, pred
);
12896 s
+= sprintf (s
, "{b%s|b%s%s} ", ccode
, ccode
, pred
);
12898 /* We need to escape any '%' characters in the reg_names string.
12899 Assume they'd only be the first character.... */
12900 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
12902 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
12906 /* If the branch distance was too far, we may have to use an
12907 unconditional branch to go the distance. */
12908 if (need_longbranch
)
12909 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
12911 s
+= sprintf (s
, ",%s", label
);
12917 /* Return the string to flip the GT bit on a CR. */
12919 output_e500_flip_gt_bit (rtx dst
, rtx src
)
12921 static char string
[64];
12924 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
12925 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
12928 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
12929 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
12931 sprintf (string
, "crnot %d,%d", a
, b
);
12935 /* Return insn index for the vector compare instruction for given CODE,
12936 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12940 get_vec_cmp_insn (enum rtx_code code
,
12941 enum machine_mode dest_mode
,
12942 enum machine_mode op_mode
)
12944 if (!TARGET_ALTIVEC
)
12945 return INSN_NOT_AVAILABLE
;
12950 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
12951 return UNSPEC_VCMPEQUB
;
12952 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
12953 return UNSPEC_VCMPEQUH
;
12954 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
12955 return UNSPEC_VCMPEQUW
;
12956 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
12957 return UNSPEC_VCMPEQFP
;
12960 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
12961 return UNSPEC_VCMPGEFP
;
12963 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
12964 return UNSPEC_VCMPGTSB
;
12965 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
12966 return UNSPEC_VCMPGTSH
;
12967 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
12968 return UNSPEC_VCMPGTSW
;
12969 if (dest_mode
== V4SImode
&& op_mode
== V4SFmode
)
12970 return UNSPEC_VCMPGTFP
;
12973 if (dest_mode
== V16QImode
&& op_mode
== V16QImode
)
12974 return UNSPEC_VCMPGTUB
;
12975 if (dest_mode
== V8HImode
&& op_mode
== V8HImode
)
12976 return UNSPEC_VCMPGTUH
;
12977 if (dest_mode
== V4SImode
&& op_mode
== V4SImode
)
12978 return UNSPEC_VCMPGTUW
;
12983 return INSN_NOT_AVAILABLE
;
12986 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12987 DMODE is expected destination mode. This is a recursive function. */
12990 rs6000_emit_vector_compare (enum rtx_code rcode
,
12992 enum machine_mode dmode
)
12996 enum machine_mode dest_mode
;
12997 enum machine_mode op_mode
= GET_MODE (op1
);
12999 gcc_assert (TARGET_ALTIVEC
);
13000 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
13002 /* Floating point vector compare instructions uses destination V4SImode.
13003 Move destination to appropriate mode later. */
13004 if (dmode
== V4SFmode
)
13005 dest_mode
= V4SImode
;
13009 mask
= gen_reg_rtx (dest_mode
);
13010 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
13012 if (vec_cmp_insn
== INSN_NOT_AVAILABLE
)
13014 bool swap_operands
= false;
13015 bool try_again
= false;
13020 swap_operands
= true;
13025 swap_operands
= true;
13033 /* Invert condition and try again.
13034 e.g., A != B becomes ~(A==B). */
13036 enum rtx_code rev_code
;
13037 enum insn_code nor_code
;
13040 rev_code
= reverse_condition_maybe_unordered (rcode
);
13041 eq_rtx
= rs6000_emit_vector_compare (rev_code
, op0
, op1
,
13044 nor_code
= optab_handler (one_cmpl_optab
, (int)dest_mode
)->insn_code
;
13045 gcc_assert (nor_code
!= CODE_FOR_nothing
);
13046 emit_insn (GEN_FCN (nor_code
) (mask
, eq_rtx
));
13048 if (dmode
!= dest_mode
)
13050 rtx temp
= gen_reg_rtx (dest_mode
);
13051 convert_move (temp
, mask
, 0);
13061 /* Try GT/GTU/LT/LTU OR EQ */
13064 enum insn_code ior_code
;
13065 enum rtx_code new_code
;
13086 gcc_unreachable ();
13089 c_rtx
= rs6000_emit_vector_compare (new_code
,
13090 op0
, op1
, dest_mode
);
13091 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
,
13094 ior_code
= optab_handler (ior_optab
, (int)dest_mode
)->insn_code
;
13095 gcc_assert (ior_code
!= CODE_FOR_nothing
);
13096 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
13097 if (dmode
!= dest_mode
)
13099 rtx temp
= gen_reg_rtx (dest_mode
);
13100 convert_move (temp
, mask
, 0);
13107 gcc_unreachable ();
13112 vec_cmp_insn
= get_vec_cmp_insn (rcode
, dest_mode
, op_mode
);
13113 /* You only get two chances. */
13114 gcc_assert (vec_cmp_insn
!= INSN_NOT_AVAILABLE
);
13126 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
13127 gen_rtx_UNSPEC (dest_mode
,
13128 gen_rtvec (2, op0
, op1
),
13130 if (dmode
!= dest_mode
)
13132 rtx temp
= gen_reg_rtx (dest_mode
);
13133 convert_move (temp
, mask
, 0);
13139 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
13140 valid insn doesn exist for given mode. */
13143 get_vsel_insn (enum machine_mode mode
)
13148 return UNSPEC_VSEL4SI
;
13151 return UNSPEC_VSEL4SF
;
13154 return UNSPEC_VSEL8HI
;
13157 return UNSPEC_VSEL16QI
;
13160 return INSN_NOT_AVAILABLE
;
13163 return INSN_NOT_AVAILABLE
;
13166 /* Emit vector select insn where DEST is destination using
13167 operands OP1, OP2 and MASK. */
13170 rs6000_emit_vector_select (rtx dest
, rtx op1
, rtx op2
, rtx mask
)
13173 enum machine_mode dest_mode
= GET_MODE (dest
);
13174 int vsel_insn_index
= get_vsel_insn (GET_MODE (dest
));
13176 temp
= gen_reg_rtx (dest_mode
);
13178 /* For each vector element, select op1 when mask is 1 otherwise
13180 t
= gen_rtx_SET (VOIDmode
, temp
,
13181 gen_rtx_UNSPEC (dest_mode
,
13182 gen_rtvec (3, op2
, op1
, mask
),
13185 emit_move_insn (dest
, temp
);
13189 /* Emit vector conditional expression.
13190 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
13191 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
13194 rs6000_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
13195 rtx cond
, rtx cc_op0
, rtx cc_op1
)
13197 enum machine_mode dest_mode
= GET_MODE (dest
);
13198 enum rtx_code rcode
= GET_CODE (cond
);
13201 if (!TARGET_ALTIVEC
)
13204 /* Get the vector mask for the given relational operations. */
13205 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, dest_mode
);
13207 rs6000_emit_vector_select (dest
, op1
, op2
, mask
);
13212 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
13213 operands of the last comparison is nonzero/true, FALSE_COND if it
13214 is zero/false. Return 0 if the hardware has no such operation. */
13217 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
13219 enum rtx_code code
= GET_CODE (op
);
13220 rtx op0
= rs6000_compare_op0
;
13221 rtx op1
= rs6000_compare_op1
;
13222 REAL_VALUE_TYPE c1
;
13223 enum machine_mode compare_mode
= GET_MODE (op0
);
13224 enum machine_mode result_mode
= GET_MODE (dest
);
13226 bool is_against_zero
;
13228 /* These modes should always match. */
13229 if (GET_MODE (op1
) != compare_mode
13230 /* In the isel case however, we can use a compare immediate, so
13231 op1 may be a small constant. */
13232 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
13234 if (GET_MODE (true_cond
) != result_mode
)
13236 if (GET_MODE (false_cond
) != result_mode
)
13239 /* First, work out if the hardware can do this at all, or
13240 if it's too slow.... */
13241 if (! rs6000_compare_fp_p
)
13244 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
13247 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
13248 && SCALAR_FLOAT_MODE_P (compare_mode
))
13251 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
13253 /* A floating-point subtract might overflow, underflow, or produce
13254 an inexact result, thus changing the floating-point flags, so it
13255 can't be generated if we care about that. It's safe if one side
13256 of the construct is zero, since then no subtract will be
13258 if (SCALAR_FLOAT_MODE_P (compare_mode
)
13259 && flag_trapping_math
&& ! is_against_zero
)
13262 /* Eliminate half of the comparisons by switching operands, this
13263 makes the remaining code simpler. */
13264 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
13265 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
13267 code
= reverse_condition_maybe_unordered (code
);
13269 true_cond
= false_cond
;
13273 /* UNEQ and LTGT take four instructions for a comparison with zero,
13274 it'll probably be faster to use a branch here too. */
13275 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
13278 if (GET_CODE (op1
) == CONST_DOUBLE
)
13279 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
13281 /* We're going to try to implement comparisons by performing
13282 a subtract, then comparing against zero. Unfortunately,
13283 Inf - Inf is NaN which is not zero, and so if we don't
13284 know that the operand is finite and the comparison
13285 would treat EQ different to UNORDERED, we can't do it. */
13286 if (HONOR_INFINITIES (compare_mode
)
13287 && code
!= GT
&& code
!= UNGE
13288 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
13289 /* Constructs of the form (a OP b ? a : b) are safe. */
13290 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
13291 || (! rtx_equal_p (op0
, true_cond
)
13292 && ! rtx_equal_p (op1
, true_cond
))))
13295 /* At this point we know we can use fsel. */
13297 /* Reduce the comparison to a comparison against zero. */
13298 if (! is_against_zero
)
13300 temp
= gen_reg_rtx (compare_mode
);
13301 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13302 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
13304 op1
= CONST0_RTX (compare_mode
);
13307 /* If we don't care about NaNs we can reduce some of the comparisons
13308 down to faster ones. */
13309 if (! HONOR_NANS (compare_mode
))
13315 true_cond
= false_cond
;
13328 /* Now, reduce everything down to a GE. */
13335 temp
= gen_reg_rtx (compare_mode
);
13336 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13341 temp
= gen_reg_rtx (compare_mode
);
13342 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
13347 temp
= gen_reg_rtx (compare_mode
);
13348 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13349 gen_rtx_NEG (compare_mode
,
13350 gen_rtx_ABS (compare_mode
, op0
))));
13355 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
13356 temp
= gen_reg_rtx (result_mode
);
13357 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13358 gen_rtx_IF_THEN_ELSE (result_mode
,
13359 gen_rtx_GE (VOIDmode
,
13361 true_cond
, false_cond
)));
13362 false_cond
= true_cond
;
13365 temp
= gen_reg_rtx (compare_mode
);
13366 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13371 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13372 temp
= gen_reg_rtx (result_mode
);
13373 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
13374 gen_rtx_IF_THEN_ELSE (result_mode
,
13375 gen_rtx_GE (VOIDmode
,
13377 true_cond
, false_cond
)));
13378 true_cond
= false_cond
;
13381 temp
= gen_reg_rtx (compare_mode
);
13382 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
13387 gcc_unreachable ();
13390 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
13391 gen_rtx_IF_THEN_ELSE (result_mode
,
13392 gen_rtx_GE (VOIDmode
,
13394 true_cond
, false_cond
)));
13398 /* Same as above, but for ints (isel). */
13401 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
13403 rtx condition_rtx
, cr
;
13405 /* All isel implementations thus far are 32-bits. */
13406 if (GET_MODE (rs6000_compare_op0
) != SImode
)
13409 /* We still have to do the compare, because isel doesn't do a
13410 compare, it just looks at the CRx bits set by a previous compare
13412 condition_rtx
= rs6000_generate_compare (GET_CODE (op
));
13413 cr
= XEXP (condition_rtx
, 0);
13415 if (GET_MODE (cr
) == CCmode
)
13416 emit_insn (gen_isel_signed (dest
, condition_rtx
,
13417 true_cond
, false_cond
, cr
));
13419 emit_insn (gen_isel_unsigned (dest
, condition_rtx
,
13420 true_cond
, false_cond
, cr
));
13426 output_isel (rtx
*operands
)
13428 enum rtx_code code
;
13430 code
= GET_CODE (operands
[1]);
13431 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
13433 PUT_CODE (operands
[1], reverse_condition (code
));
13434 return "isel %0,%3,%2,%j1";
13437 return "isel %0,%2,%3,%j1";
13441 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
13443 enum machine_mode mode
= GET_MODE (op0
);
13447 if (code
== SMAX
|| code
== SMIN
)
13452 if (code
== SMAX
|| code
== UMAX
)
13453 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13454 op0
, op1
, mode
, 0);
13456 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
13457 op1
, op0
, mode
, 0);
13458 gcc_assert (target
);
13459 if (target
!= dest
)
13460 emit_move_insn (dest
, target
);
13463 /* Emit instructions to perform a load-reserved/store-conditional operation.
13464 The operation performed is an atomic
13465 (set M (CODE:MODE M OP))
13466 If not NULL, BEFORE is atomically set to M before the operation, and
13467 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13468 If SYNC_P then a memory barrier is emitted before the operation.
13469 Either OP or M may be wrapped in a NOT operation. */
13472 rs6000_emit_sync (enum rtx_code code
, enum machine_mode mode
,
13473 rtx m
, rtx op
, rtx before_param
, rtx after_param
,
13476 enum machine_mode used_mode
;
13477 rtx the_op
, set_before
, set_after
, set_atomic
, cc_scratch
, before
, after
;
13480 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
13481 rtx shift
= NULL_RTX
;
13484 emit_insn (gen_memory_barrier ());
13486 if (GET_CODE (m
) == NOT
)
13487 used_m
= XEXP (m
, 0);
13491 /* If this is smaller than SImode, we'll have to use SImode with
13493 if (mode
== QImode
|| mode
== HImode
)
13497 if (MEM_ALIGN (used_m
) >= 32)
13500 if (BYTES_BIG_ENDIAN
)
13501 ishift
= GET_MODE_BITSIZE (SImode
) - GET_MODE_BITSIZE (mode
);
13503 shift
= GEN_INT (ishift
);
13504 used_m
= change_address (used_m
, SImode
, 0);
13508 rtx addrSI
, aligned_addr
;
13509 int shift_mask
= mode
== QImode
? 0x18 : 0x10;
13511 addrSI
= gen_lowpart_common (SImode
,
13512 force_reg (Pmode
, XEXP (used_m
, 0)));
13513 addrSI
= force_reg (SImode
, addrSI
);
13514 shift
= gen_reg_rtx (SImode
);
13516 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
13517 GEN_INT (shift_mask
)));
13518 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
13520 aligned_addr
= expand_binop (Pmode
, and_optab
,
13522 GEN_INT (-4), NULL_RTX
,
13523 1, OPTAB_LIB_WIDEN
);
13524 used_m
= change_address (used_m
, SImode
, aligned_addr
);
13525 set_mem_align (used_m
, 32);
13527 /* It's safe to keep the old alias set of USED_M, because
13528 the operation is atomic and only affects the original
13530 if (GET_CODE (m
) == NOT
)
13531 m
= gen_rtx_NOT (SImode
, used_m
);
13535 if (GET_CODE (op
) == NOT
)
13537 oldop
= lowpart_subreg (SImode
, XEXP (op
, 0), mode
);
13538 oldop
= gen_rtx_NOT (SImode
, oldop
);
13541 oldop
= lowpart_subreg (SImode
, op
, mode
);
13547 newop
= expand_binop (SImode
, and_optab
,
13548 oldop
, GEN_INT (imask
), NULL_RTX
,
13549 1, OPTAB_LIB_WIDEN
);
13550 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13554 newop
= expand_binop (SImode
, ior_optab
,
13555 oldop
, GEN_INT (~imask
), NULL_RTX
,
13556 1, OPTAB_LIB_WIDEN
);
13557 emit_insn (gen_rotlsi3 (newop
, newop
, shift
));
13565 newop
= expand_binop (SImode
, and_optab
,
13566 oldop
, GEN_INT (imask
), NULL_RTX
,
13567 1, OPTAB_LIB_WIDEN
);
13568 emit_insn (gen_ashlsi3 (newop
, newop
, shift
));
13570 mask
= gen_reg_rtx (SImode
);
13571 emit_move_insn (mask
, GEN_INT (imask
));
13572 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13575 newop
= gen_rtx_PLUS (SImode
, m
, newop
);
13577 newop
= gen_rtx_MINUS (SImode
, m
, newop
);
13578 newop
= gen_rtx_AND (SImode
, newop
, mask
);
13579 newop
= gen_rtx_IOR (SImode
, newop
,
13580 gen_rtx_AND (SImode
,
13581 gen_rtx_NOT (SImode
, mask
),
13587 gcc_unreachable ();
13590 if (GET_CODE (m
) == NOT
)
13594 mask
= gen_reg_rtx (SImode
);
13595 emit_move_insn (mask
, GEN_INT (imask
));
13596 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13598 xorm
= gen_rtx_XOR (SImode
, used_m
, mask
);
13599 /* Depending on the value of 'op', the XOR or the operation might
13600 be able to be simplified away. */
13601 newop
= simplify_gen_binary (code
, SImode
, xorm
, newop
);
13604 used_mode
= SImode
;
13605 before
= gen_reg_rtx (used_mode
);
13606 after
= gen_reg_rtx (used_mode
);
13611 before
= before_param
;
13612 after
= after_param
;
13614 if (before
== NULL_RTX
)
13615 before
= gen_reg_rtx (used_mode
);
13616 if (after
== NULL_RTX
)
13617 after
= gen_reg_rtx (used_mode
);
13620 if ((code
== PLUS
|| code
== MINUS
|| GET_CODE (m
) == NOT
)
13621 && used_mode
!= mode
)
13622 the_op
= op
; /* Computed above. */
13623 else if (GET_CODE (op
) == NOT
&& GET_CODE (m
) != NOT
)
13624 the_op
= gen_rtx_fmt_ee (code
, used_mode
, op
, m
);
13626 the_op
= gen_rtx_fmt_ee (code
, used_mode
, m
, op
);
13628 set_after
= gen_rtx_SET (VOIDmode
, after
, the_op
);
13629 set_before
= gen_rtx_SET (VOIDmode
, before
, used_m
);
13630 set_atomic
= gen_rtx_SET (VOIDmode
, used_m
,
13631 gen_rtx_UNSPEC (used_mode
,
13632 gen_rtvec (1, the_op
),
13634 cc_scratch
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
13636 if ((code
== PLUS
|| code
== MINUS
) && used_mode
!= mode
)
13637 vec
= gen_rtvec (5, set_after
, set_before
, set_atomic
, cc_scratch
,
13638 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (SImode
)));
13640 vec
= gen_rtvec (4, set_after
, set_before
, set_atomic
, cc_scratch
);
13641 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
13643 /* Shift and mask the return values properly. */
13644 if (used_mode
!= mode
&& before_param
)
13646 emit_insn (gen_lshrsi3 (before
, before
, shift
));
13647 convert_move (before_param
, before
, 1);
13650 if (used_mode
!= mode
&& after_param
)
13652 emit_insn (gen_lshrsi3 (after
, after
, shift
));
13653 convert_move (after_param
, after
, 1);
13656 /* The previous sequence will end with a branch that's dependent on
13657 the conditional store, so placing an isync will ensure that no
13658 other instructions (especially, no load or store instructions)
13659 can start before the atomic operation completes. */
13661 emit_insn (gen_isync ());
13664 /* A subroutine of the atomic operation splitters. Jump to LABEL if
13665 COND is true. Mark the jump as unlikely to be taken. */
13668 emit_unlikely_jump (rtx cond
, rtx label
)
13670 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
13673 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
13674 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
13675 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_BR_PROB
, very_unlikely
, NULL_RTX
);
13678 /* A subroutine of the atomic operation splitters. Emit a load-locked
13679 instruction in MODE. */
13682 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
13684 rtx (*fn
) (rtx
, rtx
) = NULL
;
13685 if (mode
== SImode
)
13686 fn
= gen_load_locked_si
;
13687 else if (mode
== DImode
)
13688 fn
= gen_load_locked_di
;
13689 emit_insn (fn (reg
, mem
));
13692 /* A subroutine of the atomic operation splitters. Emit a store-conditional
13693 instruction in MODE. */
13696 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
13698 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
13699 if (mode
== SImode
)
13700 fn
= gen_store_conditional_si
;
13701 else if (mode
== DImode
)
13702 fn
= gen_store_conditional_di
;
13704 /* Emit sync before stwcx. to address PPC405 Erratum. */
13705 if (PPC405_ERRATUM77
)
13706 emit_insn (gen_memory_barrier ());
13708 emit_insn (fn (res
, mem
, val
));
13711 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
13712 to perform. MEM is the memory on which to operate. VAL is the second
13713 operand of the binary operator. BEFORE and AFTER are optional locations to
13714 return the value of MEM either before of after the operation. SCRATCH is
13715 a scratch register. */
13718 rs6000_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
13719 rtx before
, rtx after
, rtx scratch
)
13721 enum machine_mode mode
= GET_MODE (mem
);
13722 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13724 emit_insn (gen_memory_barrier ());
13726 label
= gen_label_rtx ();
13727 emit_label (label
);
13728 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
13730 if (before
== NULL_RTX
)
13732 emit_load_locked (mode
, before
, mem
);
13735 x
= gen_rtx_AND (mode
, gen_rtx_NOT (mode
, before
), val
);
13736 else if (code
== AND
)
13737 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (2, before
, val
), UNSPEC_AND
);
13739 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
13741 if (after
!= NULL_RTX
)
13742 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
13743 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
13745 emit_store_conditional (mode
, cond
, mem
, scratch
);
13747 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13748 emit_unlikely_jump (x
, label
);
13750 emit_insn (gen_isync ());
13753 /* Expand an atomic compare and swap operation. MEM is the memory on which
13754 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13755 value to be stored. SCRATCH is a scratch GPR. */
13758 rs6000_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
13761 enum machine_mode mode
= GET_MODE (mem
);
13762 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13764 emit_insn (gen_memory_barrier ());
13766 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13767 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13768 emit_label (XEXP (label1
, 0));
13770 emit_load_locked (mode
, retval
, mem
);
13772 x
= gen_rtx_COMPARE (CCmode
, retval
, oldval
);
13773 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
13775 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13776 emit_unlikely_jump (x
, label2
);
13778 emit_move_insn (scratch
, newval
);
13779 emit_store_conditional (mode
, cond
, mem
, scratch
);
13781 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13782 emit_unlikely_jump (x
, label1
);
13784 emit_insn (gen_isync ());
13785 emit_label (XEXP (label2
, 0));
13788 /* Expand an atomic test and set operation. MEM is the memory on which
13789 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13792 rs6000_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
13794 enum machine_mode mode
= GET_MODE (mem
);
13795 rtx label
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13797 emit_insn (gen_memory_barrier ());
13799 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13800 emit_label (XEXP (label
, 0));
13802 emit_load_locked (mode
, retval
, mem
);
13803 emit_move_insn (scratch
, val
);
13804 emit_store_conditional (mode
, cond
, mem
, scratch
);
13806 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13807 emit_unlikely_jump (x
, label
);
13809 emit_insn (gen_isync ());
13813 rs6000_expand_compare_and_swapqhi (rtx dst
, rtx mem
, rtx oldval
, rtx newval
)
13815 enum machine_mode mode
= GET_MODE (mem
);
13816 rtx addrSI
, align
, wdst
, shift
, mask
;
13817 HOST_WIDE_INT shift_mask
= mode
== QImode
? 0x18 : 0x10;
13818 HOST_WIDE_INT imask
= GET_MODE_MASK (mode
);
13820 /* Shift amount for subword relative to aligned word. */
13821 addrSI
= force_reg (SImode
, gen_lowpart_common (SImode
, XEXP (mem
, 0)));
13822 shift
= gen_reg_rtx (SImode
);
13823 emit_insn (gen_rlwinm (shift
, addrSI
, GEN_INT (3),
13824 GEN_INT (shift_mask
)));
13825 emit_insn (gen_xorsi3 (shift
, shift
, GEN_INT (shift_mask
)));
13827 /* Shift and mask old value into position within word. */
13828 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
13829 oldval
= expand_binop (SImode
, and_optab
,
13830 oldval
, GEN_INT (imask
), NULL_RTX
,
13831 1, OPTAB_LIB_WIDEN
);
13832 emit_insn (gen_ashlsi3 (oldval
, oldval
, shift
));
13834 /* Shift and mask new value into position within word. */
13835 newval
= convert_modes (SImode
, mode
, newval
, 1);
13836 newval
= expand_binop (SImode
, and_optab
,
13837 newval
, GEN_INT (imask
), NULL_RTX
,
13838 1, OPTAB_LIB_WIDEN
);
13839 emit_insn (gen_ashlsi3 (newval
, newval
, shift
));
13841 /* Mask for insertion. */
13842 mask
= gen_reg_rtx (SImode
);
13843 emit_move_insn (mask
, GEN_INT (imask
));
13844 emit_insn (gen_ashlsi3 (mask
, mask
, shift
));
13846 /* Address of aligned word containing subword. */
13847 align
= expand_binop (Pmode
, and_optab
, XEXP (mem
, 0), GEN_INT (-4),
13848 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
13849 mem
= change_address (mem
, SImode
, align
);
13850 set_mem_align (mem
, 32);
13851 MEM_VOLATILE_P (mem
) = 1;
13853 wdst
= gen_reg_rtx (SImode
);
13854 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst
, mask
,
13855 oldval
, newval
, mem
));
13857 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
13861 rs6000_split_compare_and_swapqhi (rtx dest
, rtx mask
,
13862 rtx oldval
, rtx newval
, rtx mem
,
13865 rtx label1
, label2
, x
, cond
= gen_rtx_REG (CCmode
, CR0_REGNO
);
13867 emit_insn (gen_memory_barrier ());
13868 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13869 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
13870 emit_label (XEXP (label1
, 0));
13872 emit_load_locked (SImode
, scratch
, mem
);
13874 /* Mask subword within loaded value for comparison with oldval.
13875 Use UNSPEC_AND to avoid clobber.*/
13876 emit_insn (gen_rtx_SET (SImode
, dest
,
13877 gen_rtx_UNSPEC (SImode
,
13878 gen_rtvec (2, scratch
, mask
),
13881 x
= gen_rtx_COMPARE (CCmode
, dest
, oldval
);
13882 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
13884 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13885 emit_unlikely_jump (x
, label2
);
13887 /* Clear subword within loaded value for insertion of new value. */
13888 emit_insn (gen_rtx_SET (SImode
, scratch
,
13889 gen_rtx_AND (SImode
,
13890 gen_rtx_NOT (SImode
, mask
), scratch
)));
13891 emit_insn (gen_iorsi3 (scratch
, scratch
, newval
));
13892 emit_store_conditional (SImode
, cond
, mem
, scratch
);
13894 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
13895 emit_unlikely_jump (x
, label1
);
13897 emit_insn (gen_isync ());
13898 emit_label (XEXP (label2
, 0));
13902 /* Emit instructions to move SRC to DST. Called by splitters for
13903 multi-register moves. It will emit at most one instruction for
13904 each register that is accessed; that is, it won't emit li/lis pairs
13905 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13909 rs6000_split_multireg_move (rtx dst
, rtx src
)
13911 /* The register number of the first register being moved. */
13913 /* The mode that is to be moved. */
13914 enum machine_mode mode
;
13915 /* The mode that the move is being done in, and its size. */
13916 enum machine_mode reg_mode
;
13918 /* The number of registers that will be moved. */
13921 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
13922 mode
= GET_MODE (dst
);
13923 nregs
= hard_regno_nregs
[reg
][mode
];
13924 if (FP_REGNO_P (reg
))
13925 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
13926 else if (ALTIVEC_REGNO_P (reg
))
13927 reg_mode
= V16QImode
;
13928 else if (TARGET_E500_DOUBLE
&& (mode
== TFmode
|| mode
== TDmode
))
13929 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
13931 reg_mode
= word_mode
;
13932 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
13934 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
13936 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
13938 /* Move register range backwards, if we might have destructive
13941 for (i
= nregs
- 1; i
>= 0; i
--)
13942 emit_insn (gen_rtx_SET (VOIDmode
,
13943 simplify_gen_subreg (reg_mode
, dst
, mode
,
13944 i
* reg_mode_size
),
13945 simplify_gen_subreg (reg_mode
, src
, mode
,
13946 i
* reg_mode_size
)));
13952 bool used_update
= false;
13954 if (MEM_P (src
) && INT_REGNO_P (reg
))
13958 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
13959 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
13962 breg
= XEXP (XEXP (src
, 0), 0);
13963 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
13964 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
13965 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
13966 emit_insn (TARGET_32BIT
13967 ? gen_addsi3 (breg
, breg
, delta_rtx
)
13968 : gen_adddi3 (breg
, breg
, delta_rtx
));
13969 src
= replace_equiv_address (src
, breg
);
13971 else if (! rs6000_offsettable_memref_p (src
))
13974 basereg
= gen_rtx_REG (Pmode
, reg
);
13975 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
13976 src
= replace_equiv_address (src
, basereg
);
13979 breg
= XEXP (src
, 0);
13980 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
13981 breg
= XEXP (breg
, 0);
13983 /* If the base register we are using to address memory is
13984 also a destination reg, then change that register last. */
13986 && REGNO (breg
) >= REGNO (dst
)
13987 && REGNO (breg
) < REGNO (dst
) + nregs
)
13988 j
= REGNO (breg
) - REGNO (dst
);
13991 if (GET_CODE (dst
) == MEM
&& INT_REGNO_P (reg
))
13995 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
13996 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
13999 breg
= XEXP (XEXP (dst
, 0), 0);
14000 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
14001 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
14002 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
14004 /* We have to update the breg before doing the store.
14005 Use store with update, if available. */
14009 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
14010 emit_insn (TARGET_32BIT
14011 ? (TARGET_POWERPC64
14012 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
14013 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
14014 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
14015 used_update
= true;
14018 emit_insn (TARGET_32BIT
14019 ? gen_addsi3 (breg
, breg
, delta_rtx
)
14020 : gen_adddi3 (breg
, breg
, delta_rtx
));
14021 dst
= replace_equiv_address (dst
, breg
);
14024 gcc_assert (rs6000_offsettable_memref_p (dst
));
14027 for (i
= 0; i
< nregs
; i
++)
14029 /* Calculate index to next subword. */
14034 /* If compiler already emitted move of first word by
14035 store with update, no need to do anything. */
14036 if (j
== 0 && used_update
)
14039 emit_insn (gen_rtx_SET (VOIDmode
,
14040 simplify_gen_subreg (reg_mode
, dst
, mode
,
14041 j
* reg_mode_size
),
14042 simplify_gen_subreg (reg_mode
, src
, mode
,
14043 j
* reg_mode_size
)));
14049 /* This page contains routines that are used to determine what the
14050 function prologue and epilogue code will do and write them out. */
14052 /* Return the first fixed-point register that is required to be
14053 saved. 32 if none. */
14056 first_reg_to_save (void)
14060 /* Find lowest numbered live register. */
14061 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
14062 if (df_regs_ever_live_p (first_reg
)
14063 && (! call_used_regs
[first_reg
]
14064 || (first_reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
14065 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
14066 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
14067 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))))
14072 && current_function_uses_pic_offset_table
14073 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
14074 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
14080 /* Similar, for FP regs. */
14083 first_fp_reg_to_save (void)
14087 /* Find lowest numbered live register. */
14088 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
14089 if (df_regs_ever_live_p (first_reg
))
14095 /* Similar, for AltiVec regs. */
14098 first_altivec_reg_to_save (void)
14102 /* Stack frame remains as is unless we are in AltiVec ABI. */
14103 if (! TARGET_ALTIVEC_ABI
)
14104 return LAST_ALTIVEC_REGNO
+ 1;
14106 /* On Darwin, the unwind routines are compiled without
14107 TARGET_ALTIVEC, and use save_world to save/restore the
14108 altivec registers when necessary. */
14109 if (DEFAULT_ABI
== ABI_DARWIN
&& current_function_calls_eh_return
14110 && ! TARGET_ALTIVEC
)
14111 return FIRST_ALTIVEC_REGNO
+ 20;
14113 /* Find lowest numbered live register. */
14114 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14115 if (df_regs_ever_live_p (i
))
14121 /* Return a 32-bit mask of the AltiVec registers we need to set in
14122 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
14123 the 32-bit word is 0. */
14125 static unsigned int
14126 compute_vrsave_mask (void)
14128 unsigned int i
, mask
= 0;
14130 /* On Darwin, the unwind routines are compiled without
14131 TARGET_ALTIVEC, and use save_world to save/restore the
14132 call-saved altivec registers when necessary. */
14133 if (DEFAULT_ABI
== ABI_DARWIN
&& current_function_calls_eh_return
14134 && ! TARGET_ALTIVEC
)
14137 /* First, find out if we use _any_ altivec registers. */
14138 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
14139 if (df_regs_ever_live_p (i
))
14140 mask
|= ALTIVEC_REG_BIT (i
);
14145 /* Next, remove the argument registers from the set. These must
14146 be in the VRSAVE mask set by the caller, so we don't need to add
14147 them in again. More importantly, the mask we compute here is
14148 used to generate CLOBBERs in the set_vrsave insn, and we do not
14149 wish the argument registers to die. */
14150 for (i
= cfun
->args_info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
14151 mask
&= ~ALTIVEC_REG_BIT (i
);
14153 /* Similarly, remove the return value from the set. */
14156 diddle_return_value (is_altivec_return_reg
, &yes
);
14158 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
14164 /* For a very restricted set of circumstances, we can cut down the
14165 size of prologues/epilogues by calling our own save/restore-the-world
14169 compute_save_world_info (rs6000_stack_t
*info_ptr
)
14171 info_ptr
->world_save_p
= 1;
14172 info_ptr
->world_save_p
14173 = (WORLD_SAVE_P (info_ptr
)
14174 && DEFAULT_ABI
== ABI_DARWIN
14175 && ! (current_function_calls_setjmp
&& flag_exceptions
)
14176 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
14177 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
14178 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
14179 && info_ptr
->cr_save_p
);
14181 /* This will not work in conjunction with sibcalls. Make sure there
14182 are none. (This check is expensive, but seldom executed.) */
14183 if (WORLD_SAVE_P (info_ptr
))
14186 for ( insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
14187 if ( GET_CODE (insn
) == CALL_INSN
14188 && SIBLING_CALL_P (insn
))
14190 info_ptr
->world_save_p
= 0;
14195 if (WORLD_SAVE_P (info_ptr
))
14197 /* Even if we're not touching VRsave, make sure there's room on the
14198 stack for it, if it looks like we're calling SAVE_WORLD, which
14199 will attempt to save it. */
14200 info_ptr
->vrsave_size
= 4;
14202 /* "Save" the VRsave register too if we're saving the world. */
14203 if (info_ptr
->vrsave_mask
== 0)
14204 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
14206 /* Because the Darwin register save/restore routines only handle
14207 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
14209 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
14210 && (info_ptr
->first_altivec_reg_save
14211 >= FIRST_SAVED_ALTIVEC_REGNO
));
14218 is_altivec_return_reg (rtx reg
, void *xyes
)
14220 bool *yes
= (bool *) xyes
;
14221 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
14226 /* Calculate the stack information for the current function. This is
14227 complicated by having two separate calling sequences, the AIX calling
14228 sequence and the V.4 calling sequence.
14230 AIX (and Darwin/Mac OS X) stack frames look like:
14232 SP----> +---------------------------------------+
14233 | back chain to caller | 0 0
14234 +---------------------------------------+
14235 | saved CR | 4 8 (8-11)
14236 +---------------------------------------+
14238 +---------------------------------------+
14239 | reserved for compilers | 12 24
14240 +---------------------------------------+
14241 | reserved for binders | 16 32
14242 +---------------------------------------+
14243 | saved TOC pointer | 20 40
14244 +---------------------------------------+
14245 | Parameter save area (P) | 24 48
14246 +---------------------------------------+
14247 | Alloca space (A) | 24+P etc.
14248 +---------------------------------------+
14249 | Local variable space (L) | 24+P+A
14250 +---------------------------------------+
14251 | Float/int conversion temporary (X) | 24+P+A+L
14252 +---------------------------------------+
14253 | Save area for AltiVec registers (W) | 24+P+A+L+X
14254 +---------------------------------------+
14255 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
14256 +---------------------------------------+
14257 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
14258 +---------------------------------------+
14259 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
14260 +---------------------------------------+
14261 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
14262 +---------------------------------------+
14263 old SP->| back chain to caller's caller |
14264 +---------------------------------------+
14266 The required alignment for AIX configurations is two words (i.e., 8
14270 V.4 stack frames look like:
14272 SP----> +---------------------------------------+
14273 | back chain to caller | 0
14274 +---------------------------------------+
14275 | caller's saved LR | 4
14276 +---------------------------------------+
14277 | Parameter save area (P) | 8
14278 +---------------------------------------+
14279 | Alloca space (A) | 8+P
14280 +---------------------------------------+
14281 | Varargs save area (V) | 8+P+A
14282 +---------------------------------------+
14283 | Local variable space (L) | 8+P+A+V
14284 +---------------------------------------+
14285 | Float/int conversion temporary (X) | 8+P+A+V+L
14286 +---------------------------------------+
14287 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
14288 +---------------------------------------+
14289 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
14290 +---------------------------------------+
14291 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
14292 +---------------------------------------+
14293 | SPE: area for 64-bit GP registers |
14294 +---------------------------------------+
14295 | SPE alignment padding |
14296 +---------------------------------------+
14297 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
14298 +---------------------------------------+
14299 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
14300 +---------------------------------------+
14301 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
14302 +---------------------------------------+
14303 old SP->| back chain to caller's caller |
14304 +---------------------------------------+
14306 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
14307 given. (But note below and in sysv4.h that we require only 8 and
14308 may round up the size of our stack frame anyways. The historical
14309 reason is early versions of powerpc-linux which didn't properly
14310 align the stack at program startup. A happy side-effect is that
14311 -mno-eabi libraries can be used with -meabi programs.)
14313 The EABI configuration defaults to the V.4 layout. However,
14314 the stack alignment requirements may differ. If -mno-eabi is not
14315 given, the required stack alignment is 8 bytes; if -mno-eabi is
14316 given, the required alignment is 16 bytes. (But see V.4 comment
14319 #ifndef ABI_STACK_BOUNDARY
14320 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
14323 static rs6000_stack_t
*
14324 rs6000_stack_info (void)
14326 static rs6000_stack_t info
;
14327 rs6000_stack_t
*info_ptr
= &info
;
14328 int reg_size
= TARGET_32BIT
? 4 : 8;
14332 HOST_WIDE_INT non_fixed_size
;
14334 memset (&info
, 0, sizeof (info
));
14338 /* Cache value so we don't rescan instruction chain over and over. */
14339 if (cfun
->machine
->insn_chain_scanned_p
== 0)
14340 cfun
->machine
->insn_chain_scanned_p
14341 = spe_func_has_64bit_regs_p () + 1;
14342 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
14345 /* Select which calling sequence. */
14346 info_ptr
->abi
= DEFAULT_ABI
;
14348 /* Calculate which registers need to be saved & save area size. */
14349 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
14350 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
14351 even if it currently looks like we won't. Reload may need it to
14352 get at a constant; if so, it will have already created a constant
14353 pool entry for it. */
14354 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
14355 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
14356 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
14357 && current_function_uses_const_pool
14358 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
14359 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
14361 first_gp
= info_ptr
->first_gp_reg_save
;
14363 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
14365 /* For the SPE, we have an additional upper 32-bits on each GPR.
14366 Ideally we should save the entire 64-bits only when the upper
14367 half is used in SIMD instructions. Since we only record
14368 registers live (not the size they are used in), this proves
14369 difficult because we'd have to traverse the instruction chain at
14370 the right time, taking reload into account. This is a real pain,
14371 so we opt to save the GPRs in 64-bits always if but one register
14372 gets used in 64-bits. Otherwise, all the registers in the frame
14373 get saved in 32-bits.
14375 So... since when we save all GPRs (except the SP) in 64-bits, the
14376 traditional GP save area will be empty. */
14377 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14378 info_ptr
->gp_size
= 0;
14380 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
14381 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
14383 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
14384 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
14385 - info_ptr
->first_altivec_reg_save
);
14387 /* Does this function call anything? */
14388 info_ptr
->calls_p
= (! current_function_is_leaf
14389 || cfun
->machine
->ra_needs_full_frame
);
14391 /* Determine if we need to save the link register. */
14392 if ((DEFAULT_ABI
== ABI_AIX
14393 && current_function_profile
14394 && !TARGET_PROFILE_KERNEL
)
14395 #ifdef TARGET_RELOCATABLE
14396 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
14398 || (info_ptr
->first_fp_reg_save
!= 64
14399 && !FP_SAVE_INLINE (info_ptr
->first_fp_reg_save
))
14400 || info_ptr
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
14401 || (DEFAULT_ABI
== ABI_V4
&& current_function_calls_alloca
)
14402 || info_ptr
->calls_p
14403 || rs6000_ra_ever_killed ())
14405 info_ptr
->lr_save_p
= 1;
14406 df_set_regs_ever_live (LR_REGNO
, true);
14409 /* Determine if we need to save the condition code registers. */
14410 if (df_regs_ever_live_p (CR2_REGNO
)
14411 || df_regs_ever_live_p (CR3_REGNO
)
14412 || df_regs_ever_live_p (CR4_REGNO
))
14414 info_ptr
->cr_save_p
= 1;
14415 if (DEFAULT_ABI
== ABI_V4
)
14416 info_ptr
->cr_size
= reg_size
;
14419 /* If the current function calls __builtin_eh_return, then we need
14420 to allocate stack space for registers that will hold data for
14421 the exception handler. */
14422 if (current_function_calls_eh_return
)
14425 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
14428 /* SPE saves EH registers in 64-bits. */
14429 ehrd_size
= i
* (TARGET_SPE_ABI
14430 && info_ptr
->spe_64bit_regs_used
!= 0
14431 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
14436 /* Determine various sizes. */
14437 info_ptr
->reg_size
= reg_size
;
14438 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
14439 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
14440 info_ptr
->parm_size
= RS6000_ALIGN (current_function_outgoing_args_size
,
14441 TARGET_ALTIVEC
? 16 : 8);
14442 if (FRAME_GROWS_DOWNWARD
)
14443 info_ptr
->vars_size
14444 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
14445 + info_ptr
->parm_size
,
14446 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
14447 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
14448 + info_ptr
->parm_size
);
14450 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14451 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
14453 info_ptr
->spe_gp_size
= 0;
14455 if (TARGET_ALTIVEC_ABI
)
14456 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
14458 info_ptr
->vrsave_mask
= 0;
14460 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
14461 info_ptr
->vrsave_size
= 4;
14463 info_ptr
->vrsave_size
= 0;
14465 compute_save_world_info (info_ptr
);
14467 /* Calculate the offsets. */
14468 switch (DEFAULT_ABI
)
14472 gcc_unreachable ();
14476 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14477 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14479 if (TARGET_ALTIVEC_ABI
)
14481 info_ptr
->vrsave_save_offset
14482 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
14484 /* Align stack so vector save area is on a quadword boundary.
14485 The padding goes above the vectors. */
14486 if (info_ptr
->altivec_size
!= 0)
14487 info_ptr
->altivec_padding_size
14488 = info_ptr
->vrsave_save_offset
& 0xF;
14490 info_ptr
->altivec_padding_size
= 0;
14492 info_ptr
->altivec_save_offset
14493 = info_ptr
->vrsave_save_offset
14494 - info_ptr
->altivec_padding_size
14495 - info_ptr
->altivec_size
;
14496 gcc_assert (info_ptr
->altivec_size
== 0
14497 || info_ptr
->altivec_save_offset
% 16 == 0);
14499 /* Adjust for AltiVec case. */
14500 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
14503 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
14504 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
14505 info_ptr
->lr_save_offset
= 2*reg_size
;
14509 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
14510 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
14511 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
14513 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
14515 /* Align stack so SPE GPR save area is aligned on a
14516 double-word boundary. */
14517 if (info_ptr
->spe_gp_size
!= 0)
14518 info_ptr
->spe_padding_size
14519 = 8 - (-info_ptr
->cr_save_offset
% 8);
14521 info_ptr
->spe_padding_size
= 0;
14523 info_ptr
->spe_gp_save_offset
14524 = info_ptr
->cr_save_offset
14525 - info_ptr
->spe_padding_size
14526 - info_ptr
->spe_gp_size
;
14528 /* Adjust for SPE case. */
14529 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
14531 else if (TARGET_ALTIVEC_ABI
)
14533 info_ptr
->vrsave_save_offset
14534 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
14536 /* Align stack so vector save area is on a quadword boundary. */
14537 if (info_ptr
->altivec_size
!= 0)
14538 info_ptr
->altivec_padding_size
14539 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
14541 info_ptr
->altivec_padding_size
= 0;
14543 info_ptr
->altivec_save_offset
14544 = info_ptr
->vrsave_save_offset
14545 - info_ptr
->altivec_padding_size
14546 - info_ptr
->altivec_size
;
14548 /* Adjust for AltiVec case. */
14549 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
14552 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
14553 info_ptr
->ehrd_offset
-= ehrd_size
;
14554 info_ptr
->lr_save_offset
= reg_size
;
14558 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
14559 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
14560 + info_ptr
->gp_size
14561 + info_ptr
->altivec_size
14562 + info_ptr
->altivec_padding_size
14563 + info_ptr
->spe_gp_size
14564 + info_ptr
->spe_padding_size
14566 + info_ptr
->cr_size
14567 + info_ptr
->vrsave_size
,
14570 non_fixed_size
= (info_ptr
->vars_size
14571 + info_ptr
->parm_size
14572 + info_ptr
->save_size
);
14574 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
14575 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
14577 /* Determine if we need to allocate any stack frame:
14579 For AIX we need to push the stack if a frame pointer is needed
14580 (because the stack might be dynamically adjusted), if we are
14581 debugging, if we make calls, or if the sum of fp_save, gp_save,
14582 and local variables are more than the space needed to save all
14583 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14584 + 18*8 = 288 (GPR13 reserved).
14586 For V.4 we don't have the stack cushion that AIX uses, but assume
14587 that the debugger can handle stackless frames. */
14589 if (info_ptr
->calls_p
)
14590 info_ptr
->push_p
= 1;
14592 else if (DEFAULT_ABI
== ABI_V4
)
14593 info_ptr
->push_p
= non_fixed_size
!= 0;
14595 else if (frame_pointer_needed
)
14596 info_ptr
->push_p
= 1;
14598 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
14599 info_ptr
->push_p
= 1;
14602 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
14604 /* Zero offsets if we're not saving those registers. */
14605 if (info_ptr
->fp_size
== 0)
14606 info_ptr
->fp_save_offset
= 0;
14608 if (info_ptr
->gp_size
== 0)
14609 info_ptr
->gp_save_offset
= 0;
14611 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
14612 info_ptr
->altivec_save_offset
= 0;
14614 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->vrsave_mask
== 0)
14615 info_ptr
->vrsave_save_offset
= 0;
14617 if (! TARGET_SPE_ABI
14618 || info_ptr
->spe_64bit_regs_used
== 0
14619 || info_ptr
->spe_gp_size
== 0)
14620 info_ptr
->spe_gp_save_offset
= 0;
14622 if (! info_ptr
->lr_save_p
)
14623 info_ptr
->lr_save_offset
= 0;
14625 if (! info_ptr
->cr_save_p
)
14626 info_ptr
->cr_save_offset
= 0;
14631 /* Return true if the current function uses any GPRs in 64-bit SIMD
14635 spe_func_has_64bit_regs_p (void)
14639 /* Functions that save and restore all the call-saved registers will
14640 need to save/restore the registers in 64-bits. */
14641 if (current_function_calls_eh_return
14642 || current_function_calls_setjmp
14643 || current_function_has_nonlocal_goto
)
14646 insns
= get_insns ();
14648 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
14654 /* FIXME: This should be implemented with attributes...
14656 (set_attr "spe64" "true")....then,
14657 if (get_spe64(insn)) return true;
14659 It's the only reliable way to do the stuff below. */
14661 i
= PATTERN (insn
);
14662 if (GET_CODE (i
) == SET
)
14664 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
14666 if (SPE_VECTOR_MODE (mode
))
14668 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
14669 || mode
== DDmode
|| mode
== TDmode
))
14679 debug_stack_info (rs6000_stack_t
*info
)
14681 const char *abi_string
;
14684 info
= rs6000_stack_info ();
14686 fprintf (stderr
, "\nStack information for function %s:\n",
14687 ((current_function_decl
&& DECL_NAME (current_function_decl
))
14688 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
14693 default: abi_string
= "Unknown"; break;
14694 case ABI_NONE
: abi_string
= "NONE"; break;
14695 case ABI_AIX
: abi_string
= "AIX"; break;
14696 case ABI_DARWIN
: abi_string
= "Darwin"; break;
14697 case ABI_V4
: abi_string
= "V.4"; break;
14700 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
14702 if (TARGET_ALTIVEC_ABI
)
14703 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
14705 if (TARGET_SPE_ABI
)
14706 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
14708 if (info
->first_gp_reg_save
!= 32)
14709 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
14711 if (info
->first_fp_reg_save
!= 64)
14712 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
14714 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
14715 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
14716 info
->first_altivec_reg_save
);
14718 if (info
->lr_save_p
)
14719 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
14721 if (info
->cr_save_p
)
14722 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
14724 if (info
->vrsave_mask
)
14725 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
14728 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
14731 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
14733 if (info
->gp_save_offset
)
14734 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
14736 if (info
->fp_save_offset
)
14737 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
14739 if (info
->altivec_save_offset
)
14740 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
14741 info
->altivec_save_offset
);
14743 if (info
->spe_gp_save_offset
)
14744 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
14745 info
->spe_gp_save_offset
);
14747 if (info
->vrsave_save_offset
)
14748 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
14749 info
->vrsave_save_offset
);
14751 if (info
->lr_save_offset
)
14752 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
14754 if (info
->cr_save_offset
)
14755 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
14757 if (info
->varargs_save_offset
)
14758 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
14760 if (info
->total_size
)
14761 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
14764 if (info
->vars_size
)
14765 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
14768 if (info
->parm_size
)
14769 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
14771 if (info
->fixed_size
)
14772 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
14775 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
14777 if (info
->spe_gp_size
)
14778 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
14781 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
14783 if (info
->altivec_size
)
14784 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
14786 if (info
->vrsave_size
)
14787 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
14789 if (info
->altivec_padding_size
)
14790 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
14791 info
->altivec_padding_size
);
14793 if (info
->spe_padding_size
)
14794 fprintf (stderr
, "\tspe_padding_size = %5d\n",
14795 info
->spe_padding_size
);
14798 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
14800 if (info
->save_size
)
14801 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
14803 if (info
->reg_size
!= 4)
14804 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
14806 fprintf (stderr
, "\n");
14810 rs6000_return_addr (int count
, rtx frame
)
14812 /* Currently we don't optimize very well between prolog and body
14813 code and for PIC code the code can be actually quite bad, so
14814 don't try to be too clever here. */
14815 if (count
!= 0 || (DEFAULT_ABI
!= ABI_AIX
&& flag_pic
))
14817 cfun
->machine
->ra_needs_full_frame
= 1;
14824 plus_constant (copy_to_reg
14825 (gen_rtx_MEM (Pmode
,
14826 memory_address (Pmode
, frame
))),
14827 RETURN_ADDRESS_OFFSET
)));
14830 cfun
->machine
->ra_need_lr
= 1;
14831 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
14834 /* Say whether a function is a candidate for sibcall handling or not.
14835 We do not allow indirect calls to be optimized into sibling calls.
14836 Also, we can't do it if there are any vector parameters; there's
14837 nowhere to put the VRsave code so it works; note that functions with
14838 vector parameters are required to have a prototype, so the argument
14839 type info must be available here. (The tail recursion case can work
14840 with vector parameters, but there's no way to distinguish here.) */
14842 rs6000_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
14847 if (TARGET_ALTIVEC_VRSAVE
)
14849 for (type
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
14850 type
; type
= TREE_CHAIN (type
))
14852 if (TREE_CODE (TREE_VALUE (type
)) == VECTOR_TYPE
)
14856 if (DEFAULT_ABI
== ABI_DARWIN
14857 || ((*targetm
.binds_local_p
) (decl
)
14858 && (DEFAULT_ABI
!= ABI_AIX
|| !DECL_EXTERNAL (decl
))))
14860 tree attr_list
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
14862 if (!lookup_attribute ("longcall", attr_list
)
14863 || lookup_attribute ("shortcall", attr_list
))
14870 /* NULL if INSN insn is valid within a low-overhead loop.
14871 Otherwise return why doloop cannot be applied.
14872 PowerPC uses the COUNT register for branch on table instructions. */
14874 static const char *
14875 rs6000_invalid_within_doloop (const_rtx insn
)
14878 return "Function call in the loop.";
14881 && (GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
14882 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
))
14883 return "Computed branch in the loop.";
14889 rs6000_ra_ever_killed (void)
14895 if (current_function_is_thunk
)
14898 /* regs_ever_live has LR marked as used if any sibcalls are present,
14899 but this should not force saving and restoring in the
14900 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14901 clobbers LR, so that is inappropriate. */
14903 /* Also, the prologue can generate a store into LR that
14904 doesn't really count, like this:
14907 bcl to set PIC register
14911 When we're called from the epilogue, we need to avoid counting
14912 this as a store. */
14914 push_topmost_sequence ();
14915 top
= get_insns ();
14916 pop_topmost_sequence ();
14917 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
14919 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
14925 if (!SIBLING_CALL_P (insn
))
14928 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
14930 else if (set_of (reg
, insn
) != NULL_RTX
14931 && !prologue_epilogue_contains (insn
))
14938 /* Emit instructions needed to load the TOC register.
14939 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14940 a constant pool; or for SVR4 -fpic. */
14943 rs6000_emit_load_toc_table (int fromprolog
)
14946 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
14948 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
)
14951 rtx lab
, tmp1
, tmp2
, got
;
14953 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
14954 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
14956 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
14958 got
= rs6000_got_sym ();
14959 tmp1
= tmp2
= dest
;
14962 tmp1
= gen_reg_rtx (Pmode
);
14963 tmp2
= gen_reg_rtx (Pmode
);
14965 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
14966 emit_move_insn (tmp1
,
14967 gen_rtx_REG (Pmode
, LR_REGNO
));
14968 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
14969 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
14971 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
14973 emit_insn (gen_load_toc_v4_pic_si ());
14974 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
14976 else if (TARGET_ELF
&& DEFAULT_ABI
!= ABI_AIX
&& flag_pic
== 2)
14979 rtx temp0
= (fromprolog
14980 ? gen_rtx_REG (Pmode
, 0)
14981 : gen_reg_rtx (Pmode
));
14987 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
14988 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
14990 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
14991 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
14993 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
14994 emit_move_insn (dest
,
14995 gen_rtx_REG (Pmode
, LR_REGNO
));
14996 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
15002 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
15003 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
));
15004 emit_move_insn (dest
,
15005 gen_rtx_REG (Pmode
, LR_REGNO
));
15006 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
15008 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
15010 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
15012 /* This is for AIX code running in non-PIC ELF32. */
15015 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
15016 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
15018 emit_insn (gen_elf_high (dest
, realsym
));
15019 emit_insn (gen_elf_low (dest
, dest
, realsym
));
15023 gcc_assert (DEFAULT_ABI
== ABI_AIX
);
15026 emit_insn (gen_load_toc_aix_si (dest
));
15028 emit_insn (gen_load_toc_aix_di (dest
));
15032 /* Emit instructions to restore the link register after determining where
15033 its value has been stored. */
15036 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
15038 rs6000_stack_t
*info
= rs6000_stack_info ();
15041 operands
[0] = source
;
15042 operands
[1] = scratch
;
15044 if (info
->lr_save_p
)
15046 rtx frame_rtx
= stack_pointer_rtx
;
15047 HOST_WIDE_INT sp_offset
= 0;
15050 if (frame_pointer_needed
15051 || current_function_calls_alloca
15052 || info
->total_size
> 32767)
15054 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
15055 emit_move_insn (operands
[1], tmp
);
15056 frame_rtx
= operands
[1];
15058 else if (info
->push_p
)
15059 sp_offset
= info
->total_size
;
15061 tmp
= plus_constant (frame_rtx
, info
->lr_save_offset
+ sp_offset
);
15062 tmp
= gen_frame_mem (Pmode
, tmp
);
15063 emit_move_insn (tmp
, operands
[0]);
15066 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
15069 static GTY(()) alias_set_type set
= -1;
15072 get_TOC_alias_set (void)
15075 set
= new_alias_set ();
15079 /* This returns nonzero if the current function uses the TOC. This is
15080 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
15081 is generated by the ABI_V4 load_toc_* patterns. */
15088 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15091 rtx pat
= PATTERN (insn
);
15094 if (GET_CODE (pat
) == PARALLEL
)
15095 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
15097 rtx sub
= XVECEXP (pat
, 0, i
);
15098 if (GET_CODE (sub
) == USE
)
15100 sub
= XEXP (sub
, 0);
15101 if (GET_CODE (sub
) == UNSPEC
15102 && XINT (sub
, 1) == UNSPEC_TOC
)
15112 create_TOC_reference (rtx symbol
)
15114 if (!can_create_pseudo_p ())
15115 df_set_regs_ever_live (TOC_REGISTER
, true);
15116 return gen_rtx_PLUS (Pmode
,
15117 gen_rtx_REG (Pmode
, TOC_REGISTER
),
15118 gen_rtx_CONST (Pmode
,
15119 gen_rtx_MINUS (Pmode
, symbol
,
15120 gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
))));
15123 /* If _Unwind_* has been called from within the same module,
15124 toc register is not guaranteed to be saved to 40(1) on function
15125 entry. Save it there in that case. */
15128 rs6000_aix_emit_builtin_unwind_init (void)
15131 rtx stack_top
= gen_reg_rtx (Pmode
);
15132 rtx opcode_addr
= gen_reg_rtx (Pmode
);
15133 rtx opcode
= gen_reg_rtx (SImode
);
15134 rtx tocompare
= gen_reg_rtx (SImode
);
15135 rtx no_toc_save_needed
= gen_label_rtx ();
15137 mem
= gen_frame_mem (Pmode
, hard_frame_pointer_rtx
);
15138 emit_move_insn (stack_top
, mem
);
15140 mem
= gen_frame_mem (Pmode
,
15141 gen_rtx_PLUS (Pmode
, stack_top
,
15142 GEN_INT (2 * GET_MODE_SIZE (Pmode
))));
15143 emit_move_insn (opcode_addr
, mem
);
15144 emit_move_insn (opcode
, gen_rtx_MEM (SImode
, opcode_addr
));
15145 emit_move_insn (tocompare
, gen_int_mode (TARGET_32BIT
? 0x80410014
15146 : 0xE8410028, SImode
));
15148 do_compare_rtx_and_jump (opcode
, tocompare
, EQ
, 1,
15149 SImode
, NULL_RTX
, NULL_RTX
,
15150 no_toc_save_needed
);
15152 mem
= gen_frame_mem (Pmode
,
15153 gen_rtx_PLUS (Pmode
, stack_top
,
15154 GEN_INT (5 * GET_MODE_SIZE (Pmode
))));
15155 emit_move_insn (mem
, gen_rtx_REG (Pmode
, 2));
15156 emit_label (no_toc_save_needed
);
15159 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
15160 and the change to the stack pointer. */
15163 rs6000_emit_stack_tie (void)
15165 rtx mem
= gen_frame_mem (BLKmode
,
15166 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
15168 emit_insn (gen_stack_tie (mem
));
15171 /* Emit the correct code for allocating stack space, as insns.
15172 If COPY_R12, make sure a copy of the old frame is left in r12.
15173 The generated code may use hard register 0 as a temporary. */
15176 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, int copy_r12
)
15179 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
15180 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
15181 rtx todec
= gen_int_mode (-size
, Pmode
);
15183 if (INTVAL (todec
) != -size
)
15185 warning (0, "stack frame too large");
15186 emit_insn (gen_trap ());
15190 if (current_function_limit_stack
)
15192 if (REG_P (stack_limit_rtx
)
15193 && REGNO (stack_limit_rtx
) > 1
15194 && REGNO (stack_limit_rtx
) <= 31)
15196 emit_insn (TARGET_32BIT
15197 ? gen_addsi3 (tmp_reg
,
15200 : gen_adddi3 (tmp_reg
,
15204 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
15207 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
15209 && DEFAULT_ABI
== ABI_V4
)
15211 rtx toload
= gen_rtx_CONST (VOIDmode
,
15212 gen_rtx_PLUS (Pmode
,
15216 emit_insn (gen_elf_high (tmp_reg
, toload
));
15217 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
15218 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
15222 warning (0, "stack limit expression is not supported");
15225 if (copy_r12
|| ! TARGET_UPDATE
)
15226 emit_move_insn (gen_rtx_REG (Pmode
, 12), stack_reg
);
15232 /* Need a note here so that try_split doesn't get confused. */
15233 if (get_last_insn () == NULL_RTX
)
15234 emit_note (NOTE_INSN_DELETED
);
15235 insn
= emit_move_insn (tmp_reg
, todec
);
15236 try_split (PATTERN (insn
), insn
, 0);
15240 insn
= emit_insn (TARGET_32BIT
15241 ? gen_movsi_update (stack_reg
, stack_reg
,
15243 : gen_movdi_di_update (stack_reg
, stack_reg
,
15244 todec
, stack_reg
));
15248 insn
= emit_insn (TARGET_32BIT
15249 ? gen_addsi3 (stack_reg
, stack_reg
, todec
)
15250 : gen_adddi3 (stack_reg
, stack_reg
, todec
));
15251 emit_move_insn (gen_rtx_MEM (Pmode
, stack_reg
),
15252 gen_rtx_REG (Pmode
, 12));
15255 RTX_FRAME_RELATED_P (insn
) = 1;
15257 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
15258 gen_rtx_SET (VOIDmode
, stack_reg
,
15259 gen_rtx_PLUS (Pmode
, stack_reg
,
15264 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
15265 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
15266 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
15267 deduce these equivalences by itself so it wasn't necessary to hold
15268 its hand so much. */
15271 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
15272 rtx reg2
, rtx rreg
)
15276 /* copy_rtx will not make unique copies of registers, so we need to
15277 ensure we don't have unwanted sharing here. */
15279 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
15282 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
15284 real
= copy_rtx (PATTERN (insn
));
15286 if (reg2
!= NULL_RTX
)
15287 real
= replace_rtx (real
, reg2
, rreg
);
15289 real
= replace_rtx (real
, reg
,
15290 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
15291 STACK_POINTER_REGNUM
),
15294 /* We expect that 'real' is either a SET or a PARALLEL containing
15295 SETs (and possibly other stuff). In a PARALLEL, all the SETs
15296 are important so they all have to be marked RTX_FRAME_RELATED_P. */
15298 if (GET_CODE (real
) == SET
)
15302 temp
= simplify_rtx (SET_SRC (set
));
15304 SET_SRC (set
) = temp
;
15305 temp
= simplify_rtx (SET_DEST (set
));
15307 SET_DEST (set
) = temp
;
15308 if (GET_CODE (SET_DEST (set
)) == MEM
)
15310 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
15312 XEXP (SET_DEST (set
), 0) = temp
;
15319 gcc_assert (GET_CODE (real
) == PARALLEL
);
15320 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
15321 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
15323 rtx set
= XVECEXP (real
, 0, i
);
15325 temp
= simplify_rtx (SET_SRC (set
));
15327 SET_SRC (set
) = temp
;
15328 temp
= simplify_rtx (SET_DEST (set
));
15330 SET_DEST (set
) = temp
;
15331 if (GET_CODE (SET_DEST (set
)) == MEM
)
15333 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
15335 XEXP (SET_DEST (set
), 0) = temp
;
15337 RTX_FRAME_RELATED_P (set
) = 1;
15342 real
= spe_synthesize_frame_save (real
);
15344 RTX_FRAME_RELATED_P (insn
) = 1;
15345 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
15350 /* Given an SPE frame note, return a PARALLEL of SETs with the
15351 original note, plus a synthetic register save. */
15354 spe_synthesize_frame_save (rtx real
)
15356 rtx synth
, offset
, reg
, real2
;
15358 if (GET_CODE (real
) != SET
15359 || GET_MODE (SET_SRC (real
)) != V2SImode
)
15362 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
15363 frame related note. The parallel contains a set of the register
15364 being saved, and another set to a synthetic register (n+1200).
15365 This is so we can differentiate between 64-bit and 32-bit saves.
15366 Words cannot describe this nastiness. */
15368 gcc_assert (GET_CODE (SET_DEST (real
)) == MEM
15369 && GET_CODE (XEXP (SET_DEST (real
), 0)) == PLUS
15370 && GET_CODE (SET_SRC (real
)) == REG
);
15373 (set (mem (plus (reg x) (const y)))
15376 (set (mem (plus (reg x) (const y+4)))
15380 real2
= copy_rtx (real
);
15381 PUT_MODE (SET_DEST (real2
), SImode
);
15382 reg
= SET_SRC (real2
);
15383 real2
= replace_rtx (real2
, reg
, gen_rtx_REG (SImode
, REGNO (reg
)));
15384 synth
= copy_rtx (real2
);
15386 if (BYTES_BIG_ENDIAN
)
15388 offset
= XEXP (XEXP (SET_DEST (real2
), 0), 1);
15389 real2
= replace_rtx (real2
, offset
, GEN_INT (INTVAL (offset
) + 4));
15392 reg
= SET_SRC (synth
);
15394 synth
= replace_rtx (synth
, reg
,
15395 gen_rtx_REG (SImode
, REGNO (reg
) + 1200));
15397 offset
= XEXP (XEXP (SET_DEST (synth
), 0), 1);
15398 synth
= replace_rtx (synth
, offset
,
15399 GEN_INT (INTVAL (offset
)
15400 + (BYTES_BIG_ENDIAN
? 0 : 4)));
15402 RTX_FRAME_RELATED_P (synth
) = 1;
15403 RTX_FRAME_RELATED_P (real2
) = 1;
15404 if (BYTES_BIG_ENDIAN
)
15405 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, synth
, real2
));
15407 real
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, real2
, synth
));
15412 /* Returns an insn that has a vrsave set operation with the
15413 appropriate CLOBBERs. */
15416 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
15419 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
15420 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
15423 = gen_rtx_SET (VOIDmode
,
15425 gen_rtx_UNSPEC_VOLATILE (SImode
,
15426 gen_rtvec (2, reg
, vrsave
),
15427 UNSPECV_SET_VRSAVE
));
15431 /* We need to clobber the registers in the mask so the scheduler
15432 does not move sets to VRSAVE before sets of AltiVec registers.
15434 However, if the function receives nonlocal gotos, reload will set
15435 all call saved registers live. We will end up with:
15437 (set (reg 999) (mem))
15438 (parallel [ (set (reg vrsave) (unspec blah))
15439 (clobber (reg 999))])
15441 The clobber will cause the store into reg 999 to be dead, and
15442 flow will attempt to delete an epilogue insn. In this case, we
15443 need an unspec use/set of the register. */
15445 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
15446 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
15448 if (!epiloguep
|| call_used_regs
[i
])
15449 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
15450 gen_rtx_REG (V4SImode
, i
));
15453 rtx reg
= gen_rtx_REG (V4SImode
, i
);
15456 = gen_rtx_SET (VOIDmode
,
15458 gen_rtx_UNSPEC (V4SImode
,
15459 gen_rtvec (1, reg
), 27));
15463 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
15465 for (i
= 0; i
< nclobs
; ++i
)
15466 XVECEXP (insn
, 0, i
) = clobs
[i
];
15471 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15472 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15475 emit_frame_save (rtx frame_reg
, rtx frame_ptr
, enum machine_mode mode
,
15476 unsigned int regno
, int offset
, HOST_WIDE_INT total_size
)
15478 rtx reg
, offset_rtx
, insn
, mem
, addr
, int_rtx
;
15479 rtx replacea
, replaceb
;
15481 int_rtx
= GEN_INT (offset
);
15483 /* Some cases that need register indexed addressing. */
15484 if ((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
15485 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DDmode
))
15487 && SPE_VECTOR_MODE (mode
)
15488 && !SPE_CONST_OFFSET_OK (offset
)))
15490 /* Whomever calls us must make sure r11 is available in the
15491 flow path of instructions in the prologue. */
15492 offset_rtx
= gen_rtx_REG (Pmode
, 11);
15493 emit_move_insn (offset_rtx
, int_rtx
);
15495 replacea
= offset_rtx
;
15496 replaceb
= int_rtx
;
15500 offset_rtx
= int_rtx
;
15501 replacea
= NULL_RTX
;
15502 replaceb
= NULL_RTX
;
15505 reg
= gen_rtx_REG (mode
, regno
);
15506 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, offset_rtx
);
15507 mem
= gen_frame_mem (mode
, addr
);
15509 insn
= emit_move_insn (mem
, reg
);
15511 rs6000_frame_related (insn
, frame_ptr
, total_size
, replacea
, replaceb
);
15514 /* Emit an offset memory reference suitable for a frame store, while
15515 converting to a valid addressing mode. */
15518 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
15520 rtx int_rtx
, offset_rtx
;
15522 int_rtx
= GEN_INT (offset
);
15524 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
))
15525 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== DDmode
)))
15527 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
15528 emit_move_insn (offset_rtx
, int_rtx
);
15531 offset_rtx
= int_rtx
;
15533 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
15536 /* Look for user-defined global regs. We should not save and restore these,
15537 and cannot use stmw/lmw if there are any in its range. */
15540 no_global_regs_above (int first_greg
)
15543 for (i
= 0; i
< 32 - first_greg
; i
++)
15544 if (global_regs
[first_greg
+ i
])
15549 #ifndef TARGET_FIX_AND_CONTINUE
15550 #define TARGET_FIX_AND_CONTINUE 0
15553 /* Determine whether the gp REG is really used. */
15556 rs6000_reg_live_or_pic_offset_p (int reg
)
15558 return ((df_regs_ever_live_p (reg
)
15559 && (!call_used_regs
[reg
]
15560 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
15561 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
15562 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
15563 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
15564 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
15567 /* Emit function prologue as insns. */
15570 rs6000_emit_prologue (void)
15572 rs6000_stack_t
*info
= rs6000_stack_info ();
15573 enum machine_mode reg_mode
= Pmode
;
15574 int reg_size
= TARGET_32BIT
? 4 : 8;
15575 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
15576 rtx frame_ptr_rtx
= gen_rtx_REG (Pmode
, 12);
15577 rtx frame_reg_rtx
= sp_reg_rtx
;
15578 rtx cr_save_rtx
= NULL_RTX
;
15580 int saving_FPRs_inline
;
15581 int using_store_multiple
;
15582 HOST_WIDE_INT sp_offset
= 0;
15584 if (TARGET_FIX_AND_CONTINUE
)
15586 /* gdb on darwin arranges to forward a function from the old
15587 address by modifying the first 5 instructions of the function
15588 to branch to the overriding function. This is necessary to
15589 permit function pointers that point to the old function to
15590 actually forward to the new function. */
15591 emit_insn (gen_nop ());
15592 emit_insn (gen_nop ());
15593 emit_insn (gen_nop ());
15594 emit_insn (gen_nop ());
15595 emit_insn (gen_nop ());
15598 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
15600 reg_mode
= V2SImode
;
15604 using_store_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
15605 && (!TARGET_SPE_ABI
15606 || info
->spe_64bit_regs_used
== 0)
15607 && info
->first_gp_reg_save
< 31
15608 && no_global_regs_above (info
->first_gp_reg_save
));
15609 saving_FPRs_inline
= (info
->first_fp_reg_save
== 64
15610 || FP_SAVE_INLINE (info
->first_fp_reg_save
)
15611 || current_function_calls_eh_return
15612 || cfun
->machine
->ra_need_lr
);
15614 /* For V.4, update stack before we do any saving and set back pointer. */
15615 if (! WORLD_SAVE_P (info
)
15617 && (DEFAULT_ABI
== ABI_V4
15618 || current_function_calls_eh_return
))
15620 if (info
->total_size
< 32767)
15621 sp_offset
= info
->total_size
;
15623 frame_reg_rtx
= frame_ptr_rtx
;
15624 rs6000_emit_allocate_stack (info
->total_size
,
15625 (frame_reg_rtx
!= sp_reg_rtx
15626 && (info
->cr_save_p
15628 || info
->first_fp_reg_save
< 64
15629 || info
->first_gp_reg_save
< 32
15631 if (frame_reg_rtx
!= sp_reg_rtx
)
15632 rs6000_emit_stack_tie ();
15635 /* Handle world saves specially here. */
15636 if (WORLD_SAVE_P (info
))
15643 /* save_world expects lr in r0. */
15644 reg0
= gen_rtx_REG (Pmode
, 0);
15645 if (info
->lr_save_p
)
15647 insn
= emit_move_insn (reg0
,
15648 gen_rtx_REG (Pmode
, LR_REGNO
));
15649 RTX_FRAME_RELATED_P (insn
) = 1;
15652 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
15653 assumptions about the offsets of various bits of the stack
15655 gcc_assert (info
->gp_save_offset
== -220
15656 && info
->fp_save_offset
== -144
15657 && info
->lr_save_offset
== 8
15658 && info
->cr_save_offset
== 4
15661 && (!current_function_calls_eh_return
15662 || info
->ehrd_offset
== -432)
15663 && info
->vrsave_save_offset
== -224
15664 && info
->altivec_save_offset
== -416);
15666 treg
= gen_rtx_REG (SImode
, 11);
15667 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
15669 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
15670 in R11. It also clobbers R12, so beware! */
15672 /* Preserve CR2 for save_world prologues */
15674 sz
+= 32 - info
->first_gp_reg_save
;
15675 sz
+= 64 - info
->first_fp_reg_save
;
15676 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
15677 p
= rtvec_alloc (sz
);
15679 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
15680 gen_rtx_REG (SImode
,
15682 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
15683 gen_rtx_SYMBOL_REF (Pmode
,
15685 /* We do floats first so that the instruction pattern matches
15687 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
15689 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
15690 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15691 GEN_INT (info
->fp_save_offset
15692 + sp_offset
+ 8 * i
));
15693 rtx mem
= gen_frame_mem (DFmode
, addr
);
15695 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15697 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
15699 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
15700 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15701 GEN_INT (info
->altivec_save_offset
15702 + sp_offset
+ 16 * i
));
15703 rtx mem
= gen_frame_mem (V4SImode
, addr
);
15705 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15707 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
15709 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
15710 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15711 GEN_INT (info
->gp_save_offset
15712 + sp_offset
+ reg_size
* i
));
15713 rtx mem
= gen_frame_mem (reg_mode
, addr
);
15715 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15719 /* CR register traditionally saved as CR2. */
15720 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
15721 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15722 GEN_INT (info
->cr_save_offset
15724 rtx mem
= gen_frame_mem (reg_mode
, addr
);
15726 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15728 /* Explain about use of R0. */
15729 if (info
->lr_save_p
)
15731 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15732 GEN_INT (info
->lr_save_offset
15734 rtx mem
= gen_frame_mem (reg_mode
, addr
);
15736 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, mem
, reg0
);
15738 /* Explain what happens to the stack pointer. */
15740 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
15741 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
15744 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
15745 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15746 treg
, GEN_INT (-info
->total_size
));
15747 sp_offset
= info
->total_size
;
15750 /* If we use the link register, get it into r0. */
15751 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
15753 rtx addr
, reg
, mem
;
15755 insn
= emit_move_insn (gen_rtx_REG (Pmode
, 0),
15756 gen_rtx_REG (Pmode
, LR_REGNO
));
15757 RTX_FRAME_RELATED_P (insn
) = 1;
15759 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15760 GEN_INT (info
->lr_save_offset
+ sp_offset
));
15761 reg
= gen_rtx_REG (Pmode
, 0);
15762 mem
= gen_rtx_MEM (Pmode
, addr
);
15763 /* This should not be of rs6000_sr_alias_set, because of
15764 __builtin_return_address. */
15766 insn
= emit_move_insn (mem
, reg
);
15767 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15768 NULL_RTX
, NULL_RTX
);
15771 /* If we need to save CR, put it into r12. */
15772 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
&& frame_reg_rtx
!= frame_ptr_rtx
)
15776 cr_save_rtx
= gen_rtx_REG (SImode
, 12);
15777 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
15778 RTX_FRAME_RELATED_P (insn
) = 1;
15779 /* Now, there's no way that dwarf2out_frame_debug_expr is going
15780 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
15781 But that's OK. All we have to do is specify that _one_ condition
15782 code register is saved in this stack slot. The thrower's epilogue
15783 will then restore all the call-saved registers.
15784 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
15785 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
,
15786 gen_rtx_REG (SImode
, CR2_REGNO
));
15787 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
15792 /* Do any required saving of fpr's. If only one or two to save, do
15793 it ourselves. Otherwise, call function. */
15794 if (!WORLD_SAVE_P (info
) && saving_FPRs_inline
)
15797 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
15798 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
15799 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
15800 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, DFmode
,
15801 info
->first_fp_reg_save
+ i
,
15802 info
->fp_save_offset
+ sp_offset
+ 8 * i
,
15805 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
15809 const char *alloc_rname
;
15811 p
= rtvec_alloc (2 + 64 - info
->first_fp_reg_save
);
15813 RTVEC_ELT (p
, 0) = gen_rtx_CLOBBER (VOIDmode
,
15814 gen_rtx_REG (Pmode
,
15816 sprintf (rname
, "%s%d%s", SAVE_FP_PREFIX
,
15817 info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
);
15818 alloc_rname
= ggc_strdup (rname
);
15819 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
15820 gen_rtx_SYMBOL_REF (Pmode
,
15822 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
15824 rtx addr
, reg
, mem
;
15825 reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
15826 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15827 GEN_INT (info
->fp_save_offset
15828 + sp_offset
+ 8*i
));
15829 mem
= gen_frame_mem (DFmode
, addr
);
15831 RTVEC_ELT (p
, i
+ 2) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15833 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
15834 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15835 NULL_RTX
, NULL_RTX
);
15838 /* Save GPRs. This is done as a PARALLEL if we are using
15839 the store-multiple instructions. */
15840 if (!WORLD_SAVE_P (info
) && using_store_multiple
)
15844 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
15845 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
15847 rtx addr
, reg
, mem
;
15848 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
15849 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15850 GEN_INT (info
->gp_save_offset
15853 mem
= gen_frame_mem (reg_mode
, addr
);
15855 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, reg
);
15857 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
15858 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15859 NULL_RTX
, NULL_RTX
);
15861 else if (!WORLD_SAVE_P (info
)
15863 && info
->spe_64bit_regs_used
!= 0
15864 && info
->first_gp_reg_save
!= 32)
15867 rtx spe_save_area_ptr
;
15868 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
15869 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
15870 && !call_used_regs
[STATIC_CHAIN_REGNUM
]);
15872 /* Determine whether we can address all of the registers that need
15873 to be saved with an offset from the stack pointer that fits in
15874 the small const field for SPE memory instructions. */
15875 int spe_regs_addressable_via_sp
15876 = SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
15877 + (32 - info
->first_gp_reg_save
- 1) * reg_size
);
15880 if (spe_regs_addressable_via_sp
)
15882 spe_save_area_ptr
= frame_reg_rtx
;
15883 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
15887 /* Make r11 point to the start of the SPE save area. We need
15888 to be careful here if r11 is holding the static chain. If
15889 it is, then temporarily save it in r0. We would use r0 as
15890 our base register here, but using r0 as a base register in
15891 loads and stores means something different from what we
15893 if (using_static_chain_p
)
15895 rtx r0
= gen_rtx_REG (Pmode
, 0);
15897 gcc_assert (info
->first_gp_reg_save
> 11);
15899 emit_move_insn (r0
, gen_rtx_REG (Pmode
, 11));
15902 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
15903 emit_insn (gen_addsi3 (spe_save_area_ptr
, frame_reg_rtx
,
15904 GEN_INT (info
->spe_gp_save_offset
+ sp_offset
)));
15909 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
15910 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
15912 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
15913 rtx offset
, addr
, mem
;
15915 /* We're doing all this to ensure that the offset fits into
15916 the immediate offset of 'evstdd'. */
15917 gcc_assert (SPE_CONST_OFFSET_OK (reg_size
* i
+ spe_offset
));
15919 offset
= GEN_INT (reg_size
* i
+ spe_offset
);
15920 addr
= gen_rtx_PLUS (Pmode
, spe_save_area_ptr
, offset
);
15921 mem
= gen_rtx_MEM (V2SImode
, addr
);
15923 insn
= emit_move_insn (mem
, reg
);
15925 rs6000_frame_related (insn
, spe_save_area_ptr
,
15926 info
->spe_gp_save_offset
15927 + sp_offset
+ reg_size
* i
,
15928 offset
, const0_rtx
);
15931 /* Move the static chain pointer back. */
15932 if (using_static_chain_p
&& !spe_regs_addressable_via_sp
)
15933 emit_move_insn (gen_rtx_REG (Pmode
, 11), gen_rtx_REG (Pmode
, 0));
15935 else if (!WORLD_SAVE_P (info
))
15938 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
15939 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
15941 rtx addr
, reg
, mem
;
15942 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
15944 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15945 GEN_INT (info
->gp_save_offset
15948 mem
= gen_frame_mem (reg_mode
, addr
);
15950 insn
= emit_move_insn (mem
, reg
);
15951 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15952 NULL_RTX
, NULL_RTX
);
15956 /* ??? There's no need to emit actual instructions here, but it's the
15957 easiest way to get the frame unwind information emitted. */
15958 if (current_function_calls_eh_return
)
15960 unsigned int i
, regno
;
15962 /* In AIX ABI we need to pretend we save r2 here. */
15965 rtx addr
, reg
, mem
;
15967 reg
= gen_rtx_REG (reg_mode
, 2);
15968 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15969 GEN_INT (sp_offset
+ 5 * reg_size
));
15970 mem
= gen_frame_mem (reg_mode
, addr
);
15972 insn
= emit_move_insn (mem
, reg
);
15973 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
15974 NULL_RTX
, NULL_RTX
);
15975 PATTERN (insn
) = gen_blockage ();
15980 regno
= EH_RETURN_DATA_REGNO (i
);
15981 if (regno
== INVALID_REGNUM
)
15984 emit_frame_save (frame_reg_rtx
, frame_ptr_rtx
, reg_mode
, regno
,
15985 info
->ehrd_offset
+ sp_offset
15986 + reg_size
* (int) i
,
15991 /* Save CR if we use any that must be preserved. */
15992 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
15994 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
15995 GEN_INT (info
->cr_save_offset
+ sp_offset
));
15996 rtx mem
= gen_frame_mem (SImode
, addr
);
15997 /* See the large comment above about why CR2_REGNO is used. */
15998 rtx magic_eh_cr_reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
16000 /* If r12 was used to hold the original sp, copy cr into r0 now
16002 if (REGNO (frame_reg_rtx
) == 12)
16006 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
16007 insn
= emit_insn (gen_movesi_from_cr (cr_save_rtx
));
16008 RTX_FRAME_RELATED_P (insn
) = 1;
16009 set
= gen_rtx_SET (VOIDmode
, cr_save_rtx
, magic_eh_cr_reg
);
16010 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
16015 insn
= emit_move_insn (mem
, cr_save_rtx
);
16017 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16018 NULL_RTX
, NULL_RTX
);
16021 /* Update stack and set back pointer unless this is V.4,
16022 for which it was done previously. */
16023 if (!WORLD_SAVE_P (info
) && info
->push_p
16024 && !(DEFAULT_ABI
== ABI_V4
|| current_function_calls_eh_return
))
16026 if (info
->total_size
< 32767)
16027 sp_offset
= info
->total_size
;
16029 frame_reg_rtx
= frame_ptr_rtx
;
16030 rs6000_emit_allocate_stack (info
->total_size
,
16031 (frame_reg_rtx
!= sp_reg_rtx
16032 && ((info
->altivec_size
!= 0)
16033 || (info
->vrsave_mask
!= 0)
16035 if (frame_reg_rtx
!= sp_reg_rtx
)
16036 rs6000_emit_stack_tie ();
16039 /* Set frame pointer, if needed. */
16040 if (frame_pointer_needed
)
16042 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
16044 RTX_FRAME_RELATED_P (insn
) = 1;
16047 /* Save AltiVec registers if needed. Save here because the red zone does
16048 not include AltiVec registers. */
16049 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
16053 /* There should be a non inline version of this, for when we
16054 are saving lots of vector registers. */
16055 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16056 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16058 rtx areg
, savereg
, mem
;
16061 offset
= info
->altivec_save_offset
+ sp_offset
16062 + 16 * (i
- info
->first_altivec_reg_save
);
16064 savereg
= gen_rtx_REG (V4SImode
, i
);
16066 areg
= gen_rtx_REG (Pmode
, 0);
16067 emit_move_insn (areg
, GEN_INT (offset
));
16069 /* AltiVec addressing mode is [reg+reg]. */
16070 mem
= gen_frame_mem (V4SImode
,
16071 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
16073 insn
= emit_move_insn (mem
, savereg
);
16075 rs6000_frame_related (insn
, frame_ptr_rtx
, info
->total_size
,
16076 areg
, GEN_INT (offset
));
16080 /* VRSAVE is a bit vector representing which AltiVec registers
16081 are used. The OS uses this to determine which vector
16082 registers to save on a context switch. We need to save
16083 VRSAVE on the stack frame, add whatever AltiVec registers we
16084 used in this function, and do the corresponding magic in the
16087 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
16088 && info
->vrsave_mask
!= 0)
16090 rtx reg
, mem
, vrsave
;
16093 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
16094 as frame_reg_rtx and r11 as the static chain pointer for
16095 nested functions. */
16096 reg
= gen_rtx_REG (SImode
, 0);
16097 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
16099 emit_insn (gen_get_vrsave_internal (reg
));
16101 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
16103 if (!WORLD_SAVE_P (info
))
16106 offset
= info
->vrsave_save_offset
+ sp_offset
;
16107 mem
= gen_frame_mem (SImode
,
16108 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16109 GEN_INT (offset
)));
16110 insn
= emit_move_insn (mem
, reg
);
16113 /* Include the registers in the mask. */
16114 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
16116 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
16119 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
16120 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
16121 || (DEFAULT_ABI
== ABI_V4
16122 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
16123 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
)))
16125 /* If emit_load_toc_table will use the link register, we need to save
16126 it. We use R12 for this purpose because emit_load_toc_table
16127 can use register 0. This allows us to use a plain 'blr' to return
16128 from the procedure more often. */
16129 int save_LR_around_toc_setup
= (TARGET_ELF
16130 && DEFAULT_ABI
!= ABI_AIX
16132 && ! info
->lr_save_p
16133 && EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) > 0);
16134 if (save_LR_around_toc_setup
)
16136 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
16138 insn
= emit_move_insn (frame_ptr_rtx
, lr
);
16139 RTX_FRAME_RELATED_P (insn
) = 1;
16141 rs6000_emit_load_toc_table (TRUE
);
16143 insn
= emit_move_insn (lr
, frame_ptr_rtx
);
16144 RTX_FRAME_RELATED_P (insn
) = 1;
16147 rs6000_emit_load_toc_table (TRUE
);
16151 if (DEFAULT_ABI
== ABI_DARWIN
16152 && flag_pic
&& current_function_uses_pic_offset_table
)
16154 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
16155 rtx src
= machopic_function_base_sym ();
16157 /* Save and restore LR locally around this call (in R0). */
16158 if (!info
->lr_save_p
)
16159 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
16161 emit_insn (gen_load_macho_picbase (src
));
16163 emit_move_insn (gen_rtx_REG (Pmode
,
16164 RS6000_PIC_OFFSET_TABLE_REGNUM
),
16167 if (!info
->lr_save_p
)
16168 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
16173 /* Write function prologue. */
16176 rs6000_output_function_prologue (FILE *file
,
16177 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
16179 rs6000_stack_t
*info
= rs6000_stack_info ();
16181 if (TARGET_DEBUG_STACK
)
16182 debug_stack_info (info
);
16184 /* Write .extern for any function we will call to save and restore
16186 if (info
->first_fp_reg_save
< 64
16187 && !FP_SAVE_INLINE (info
->first_fp_reg_save
))
16188 fprintf (file
, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
16189 SAVE_FP_PREFIX
, info
->first_fp_reg_save
- 32, SAVE_FP_SUFFIX
,
16190 RESTORE_FP_PREFIX
, info
->first_fp_reg_save
- 32,
16191 RESTORE_FP_SUFFIX
);
16193 /* Write .extern for AIX common mode routines, if needed. */
16194 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
16196 fputs ("\t.extern __mulh\n", file
);
16197 fputs ("\t.extern __mull\n", file
);
16198 fputs ("\t.extern __divss\n", file
);
16199 fputs ("\t.extern __divus\n", file
);
16200 fputs ("\t.extern __quoss\n", file
);
16201 fputs ("\t.extern __quous\n", file
);
16202 common_mode_defined
= 1;
16205 if (! HAVE_prologue
)
16209 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
16210 the "toplevel" insn chain. */
16211 emit_note (NOTE_INSN_DELETED
);
16212 rs6000_emit_prologue ();
16213 emit_note (NOTE_INSN_DELETED
);
16215 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16219 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16221 INSN_ADDRESSES_NEW (insn
, addr
);
16226 if (TARGET_DEBUG_STACK
)
16227 debug_rtx_list (get_insns (), 100);
16228 final (get_insns (), file
, FALSE
);
16232 rs6000_pic_labelno
++;
16235 /* Emit function epilogue as insns.
16237 At present, dwarf2out_frame_debug_expr doesn't understand
16238 register restores, so we don't bother setting RTX_FRAME_RELATED_P
16239 anywhere in the epilogue. Most of the insns below would in any case
16240 need special notes to explain where r11 is in relation to the stack. */
16243 rs6000_emit_epilogue (int sibcall
)
16245 rs6000_stack_t
*info
;
16246 int restoring_FPRs_inline
;
16247 int using_load_multiple
;
16248 int using_mtcr_multiple
;
16249 int use_backchain_to_restore_sp
;
16251 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
16252 rtx frame_reg_rtx
= sp_reg_rtx
;
16253 enum machine_mode reg_mode
= Pmode
;
16254 int reg_size
= TARGET_32BIT
? 4 : 8;
16257 info
= rs6000_stack_info ();
16259 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
16261 reg_mode
= V2SImode
;
16265 using_load_multiple
= (TARGET_MULTIPLE
&& ! TARGET_POWERPC64
16266 && (!TARGET_SPE_ABI
16267 || info
->spe_64bit_regs_used
== 0)
16268 && info
->first_gp_reg_save
< 31
16269 && no_global_regs_above (info
->first_gp_reg_save
));
16270 restoring_FPRs_inline
= (sibcall
16271 || current_function_calls_eh_return
16272 || info
->first_fp_reg_save
== 64
16273 || FP_SAVE_INLINE (info
->first_fp_reg_save
));
16274 use_backchain_to_restore_sp
= (frame_pointer_needed
16275 || current_function_calls_alloca
16276 || info
->total_size
> 32767);
16277 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
16278 || rs6000_cpu
== PROCESSOR_PPC603
16279 || rs6000_cpu
== PROCESSOR_PPC750
16282 if (WORLD_SAVE_P (info
))
16286 const char *alloc_rname
;
16289 /* eh_rest_world_r10 will return to the location saved in the LR
16290 stack slot (which is not likely to be our caller.)
16291 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
16292 rest_world is similar, except any R10 parameter is ignored.
16293 The exception-handling stuff that was here in 2.95 is no
16294 longer necessary. */
16298 + 32 - info
->first_gp_reg_save
16299 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
16300 + 63 + 1 - info
->first_fp_reg_save
);
16302 strcpy (rname
, ((current_function_calls_eh_return
) ?
16303 "*eh_rest_world_r10" : "*rest_world"));
16304 alloc_rname
= ggc_strdup (rname
);
16307 RTVEC_ELT (p
, j
++) = gen_rtx_RETURN (VOIDmode
);
16308 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
16309 gen_rtx_REG (Pmode
,
16312 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
16313 /* The instruction pattern requires a clobber here;
16314 it is shared with the restVEC helper. */
16316 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
16319 /* CR register traditionally saved as CR2. */
16320 rtx reg
= gen_rtx_REG (reg_mode
, CR2_REGNO
);
16321 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16322 GEN_INT (info
->cr_save_offset
));
16323 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16325 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16328 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16330 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
16331 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16332 GEN_INT (info
->gp_save_offset
16334 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16336 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16338 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
16340 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
16341 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16342 GEN_INT (info
->altivec_save_offset
16344 rtx mem
= gen_frame_mem (V4SImode
, addr
);
16346 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16348 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
16350 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
16351 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16352 GEN_INT (info
->fp_save_offset
16354 rtx mem
= gen_frame_mem (DFmode
, addr
);
16356 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, reg
, mem
);
16359 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
16361 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
16363 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
16365 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
16367 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
16368 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16373 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
16375 sp_offset
= info
->total_size
;
16377 /* Restore AltiVec registers if needed. */
16378 if (TARGET_ALTIVEC_ABI
&& info
->altivec_size
!= 0)
16382 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
16383 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
16385 rtx addr
, areg
, mem
;
16387 areg
= gen_rtx_REG (Pmode
, 0);
16389 (areg
, GEN_INT (info
->altivec_save_offset
16391 + 16 * (i
- info
->first_altivec_reg_save
)));
16393 /* AltiVec addressing mode is [reg+reg]. */
16394 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
16395 mem
= gen_frame_mem (V4SImode
, addr
);
16397 emit_move_insn (gen_rtx_REG (V4SImode
, i
), mem
);
16401 /* If we have a frame pointer, a call to alloca, or a large stack
16402 frame, restore the old stack pointer using the backchain. Otherwise,
16403 we know what size to update it with. */
16404 if (use_backchain_to_restore_sp
)
16406 /* Under V.4, don't reset the stack pointer until after we're done
16407 loading the saved registers. */
16408 if (DEFAULT_ABI
== ABI_V4
)
16409 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16411 emit_move_insn (frame_reg_rtx
,
16412 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
16415 else if (info
->push_p
16416 && DEFAULT_ABI
!= ABI_V4
16417 && !current_function_calls_eh_return
)
16419 emit_insn (TARGET_32BIT
16420 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
16421 GEN_INT (info
->total_size
))
16422 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
16423 GEN_INT (info
->total_size
)));
16427 /* Restore VRSAVE if needed. */
16428 if (TARGET_ALTIVEC
&& TARGET_ALTIVEC_VRSAVE
16429 && info
->vrsave_mask
!= 0)
16431 rtx addr
, mem
, reg
;
16433 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16434 GEN_INT (info
->vrsave_save_offset
+ sp_offset
));
16435 mem
= gen_frame_mem (SImode
, addr
);
16436 reg
= gen_rtx_REG (SImode
, 12);
16437 emit_move_insn (reg
, mem
);
16439 emit_insn (generate_set_vrsave (reg
, info
, 1));
16442 /* Get the old lr if we saved it. */
16443 if (info
->lr_save_p
)
16445 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
,
16446 info
->lr_save_offset
+ sp_offset
);
16448 emit_move_insn (gen_rtx_REG (Pmode
, 0), mem
);
16451 /* Get the old cr if we saved it. */
16452 if (info
->cr_save_p
)
16454 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16455 GEN_INT (info
->cr_save_offset
+ sp_offset
));
16456 rtx mem
= gen_frame_mem (SImode
, addr
);
16458 emit_move_insn (gen_rtx_REG (SImode
, 12), mem
);
16461 /* Set LR here to try to overlap restores below. */
16462 if (info
->lr_save_p
)
16463 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
),
16464 gen_rtx_REG (Pmode
, 0));
16466 /* Load exception handler data registers, if needed. */
16467 if (current_function_calls_eh_return
)
16469 unsigned int i
, regno
;
16473 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16474 GEN_INT (sp_offset
+ 5 * reg_size
));
16475 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16477 emit_move_insn (gen_rtx_REG (reg_mode
, 2), mem
);
16484 regno
= EH_RETURN_DATA_REGNO (i
);
16485 if (regno
== INVALID_REGNUM
)
16488 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
16489 info
->ehrd_offset
+ sp_offset
16490 + reg_size
* (int) i
);
16492 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
16496 /* Restore GPRs. This is done as a PARALLEL if we are using
16497 the load-multiple instructions. */
16498 if (using_load_multiple
)
16501 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
16502 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16504 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16505 GEN_INT (info
->gp_save_offset
16508 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16511 gen_rtx_SET (VOIDmode
,
16512 gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
16515 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16517 else if (TARGET_SPE_ABI
16518 && info
->spe_64bit_regs_used
!= 0
16519 && info
->first_gp_reg_save
!= 32)
16521 /* Determine whether we can address all of the registers that need
16522 to be saved with an offset from the stack pointer that fits in
16523 the small const field for SPE memory instructions. */
16524 int spe_regs_addressable_via_sp
16525 = SPE_CONST_OFFSET_OK(info
->spe_gp_save_offset
+ sp_offset
16526 + (32 - info
->first_gp_reg_save
- 1) * reg_size
);
16529 if (spe_regs_addressable_via_sp
)
16530 spe_offset
= info
->spe_gp_save_offset
+ sp_offset
;
16533 rtx old_frame_reg_rtx
= frame_reg_rtx
;
16534 /* Make r11 point to the start of the SPE save area. We worried about
16535 not clobbering it when we were saving registers in the prologue.
16536 There's no need to worry here because the static chain is passed
16537 anew to every function. */
16538 if (frame_reg_rtx
== sp_reg_rtx
)
16539 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
16540 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
16541 GEN_INT (info
->spe_gp_save_offset
+ sp_offset
)));
16542 /* Keep the invariant that frame_reg_rtx + sp_offset points
16543 at the top of the stack frame. */
16544 sp_offset
= -info
->spe_gp_save_offset
;
16549 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16550 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16552 rtx offset
, addr
, mem
;
16554 /* We're doing all this to ensure that the immediate offset
16555 fits into the immediate field of 'evldd'. */
16556 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
16558 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
16559 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
16560 mem
= gen_rtx_MEM (V2SImode
, addr
);
16562 emit_move_insn (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
16567 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
16568 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
16570 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16571 GEN_INT (info
->gp_save_offset
16574 rtx mem
= gen_frame_mem (reg_mode
, addr
);
16576 emit_move_insn (gen_rtx_REG (reg_mode
,
16577 info
->first_gp_reg_save
+ i
), mem
);
16580 /* Restore fpr's if we need to do it without calling a function. */
16581 if (restoring_FPRs_inline
)
16582 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16583 if ((df_regs_ever_live_p (info
->first_fp_reg_save
+i
)
16584 && ! call_used_regs
[info
->first_fp_reg_save
+i
]))
16587 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
16588 GEN_INT (info
->fp_save_offset
16591 mem
= gen_frame_mem (DFmode
, addr
);
16593 emit_move_insn (gen_rtx_REG (DFmode
,
16594 info
->first_fp_reg_save
+ i
),
16598 /* If we saved cr, restore it here. Just those that were used. */
16599 if (info
->cr_save_p
)
16601 rtx r12_rtx
= gen_rtx_REG (SImode
, 12);
16604 if (using_mtcr_multiple
)
16606 for (i
= 0; i
< 8; i
++)
16607 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16609 gcc_assert (count
);
16612 if (using_mtcr_multiple
&& count
> 1)
16617 p
= rtvec_alloc (count
);
16620 for (i
= 0; i
< 8; i
++)
16621 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16623 rtvec r
= rtvec_alloc (2);
16624 RTVEC_ELT (r
, 0) = r12_rtx
;
16625 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
16626 RTVEC_ELT (p
, ndx
) =
16627 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+i
),
16628 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
16631 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16632 gcc_assert (ndx
== count
);
16635 for (i
= 0; i
< 8; i
++)
16636 if (df_regs_ever_live_p (CR0_REGNO
+i
) && ! call_used_regs
[CR0_REGNO
+i
])
16638 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode
,
16644 /* If this is V.4, unwind the stack pointer after all of the loads
16646 if (frame_reg_rtx
!= sp_reg_rtx
)
16648 /* This blockage is needed so that sched doesn't decide to move
16649 the sp change before the register restores. */
16650 rs6000_emit_stack_tie ();
16651 if (sp_offset
!= 0)
16652 emit_insn (gen_addsi3 (sp_reg_rtx
, frame_reg_rtx
,
16653 GEN_INT (sp_offset
)));
16655 emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
16657 else if (sp_offset
!= 0)
16658 emit_insn (TARGET_32BIT
16659 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
,
16660 GEN_INT (sp_offset
))
16661 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
,
16662 GEN_INT (sp_offset
)));
16664 if (current_function_calls_eh_return
)
16666 rtx sa
= EH_RETURN_STACKADJ_RTX
;
16667 emit_insn (TARGET_32BIT
16668 ? gen_addsi3 (sp_reg_rtx
, sp_reg_rtx
, sa
)
16669 : gen_adddi3 (sp_reg_rtx
, sp_reg_rtx
, sa
));
16675 if (! restoring_FPRs_inline
)
16676 p
= rtvec_alloc (3 + 64 - info
->first_fp_reg_save
);
16678 p
= rtvec_alloc (2);
16680 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
16681 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
16682 gen_rtx_REG (Pmode
,
16685 /* If we have to restore more than two FP registers, branch to the
16686 restore function. It will return to our caller. */
16687 if (! restoring_FPRs_inline
)
16691 const char *alloc_rname
;
16693 sprintf (rname
, "%s%d%s", RESTORE_FP_PREFIX
,
16694 info
->first_fp_reg_save
- 32, RESTORE_FP_SUFFIX
);
16695 alloc_rname
= ggc_strdup (rname
);
16696 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
,
16697 gen_rtx_SYMBOL_REF (Pmode
,
16700 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
16703 addr
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
,
16704 GEN_INT (info
->fp_save_offset
+ 8*i
));
16705 mem
= gen_frame_mem (DFmode
, addr
);
16707 RTVEC_ELT (p
, i
+3) =
16708 gen_rtx_SET (VOIDmode
,
16709 gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
),
16714 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
16718 /* Write function epilogue. */
16721 rs6000_output_function_epilogue (FILE *file
,
16722 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
16724 if (! HAVE_epilogue
)
16726 rtx insn
= get_last_insn ();
16727 /* If the last insn was a BARRIER, we don't have to write anything except
16728 the trace table. */
16729 if (GET_CODE (insn
) == NOTE
)
16730 insn
= prev_nonnote_insn (insn
);
16731 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
16733 /* This is slightly ugly, but at least we don't have two
16734 copies of the epilogue-emitting code. */
16737 /* A NOTE_INSN_DELETED is supposed to be at the start
16738 and end of the "toplevel" insn chain. */
16739 emit_note (NOTE_INSN_DELETED
);
16740 rs6000_emit_epilogue (FALSE
);
16741 emit_note (NOTE_INSN_DELETED
);
16743 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16747 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16749 INSN_ADDRESSES_NEW (insn
, addr
);
16754 if (TARGET_DEBUG_STACK
)
16755 debug_rtx_list (get_insns (), 100);
16756 final (get_insns (), file
, FALSE
);
16762 macho_branch_islands ();
16763 /* Mach-O doesn't support labels at the end of objects, so if
16764 it looks like we might want one, insert a NOP. */
16766 rtx insn
= get_last_insn ();
16769 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
16770 insn
= PREV_INSN (insn
);
16774 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
16775 fputs ("\tnop\n", file
);
16779 /* Output a traceback table here. See /usr/include/sys/debug.h for info
16782 We don't output a traceback table if -finhibit-size-directive was
16783 used. The documentation for -finhibit-size-directive reads
16784 ``don't output a @code{.size} assembler directive, or anything
16785 else that would cause trouble if the function is split in the
16786 middle, and the two halves are placed at locations far apart in
16787 memory.'' The traceback table has this property, since it
16788 includes the offset from the start of the function to the
16789 traceback table itself.
16791 System V.4 Powerpc's (and the embedded ABI derived from it) use a
16792 different traceback table. */
16793 if (DEFAULT_ABI
== ABI_AIX
&& ! flag_inhibit_size_directive
16794 && rs6000_traceback
!= traceback_none
&& !current_function_is_thunk
)
16796 const char *fname
= NULL
;
16797 const char *language_string
= lang_hooks
.name
;
16798 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
16800 int optional_tbtab
;
16801 rs6000_stack_t
*info
= rs6000_stack_info ();
16803 if (rs6000_traceback
== traceback_full
)
16804 optional_tbtab
= 1;
16805 else if (rs6000_traceback
== traceback_part
)
16806 optional_tbtab
= 0;
16808 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
16810 if (optional_tbtab
)
16812 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
16813 while (*fname
== '.') /* V.4 encodes . in the name */
16816 /* Need label immediately before tbtab, so we can compute
16817 its offset from the function start. */
16818 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
16819 ASM_OUTPUT_LABEL (file
, fname
);
16822 /* The .tbtab pseudo-op can only be used for the first eight
16823 expressions, since it can't handle the possibly variable
16824 length fields that follow. However, if you omit the optional
16825 fields, the assembler outputs zeros for all optional fields
16826 anyways, giving each variable length field is minimum length
16827 (as defined in sys/debug.h). Thus we can not use the .tbtab
16828 pseudo-op at all. */
16830 /* An all-zero word flags the start of the tbtab, for debuggers
16831 that have to find it by searching forward from the entry
16832 point or from the current pc. */
16833 fputs ("\t.long 0\n", file
);
16835 /* Tbtab format type. Use format type 0. */
16836 fputs ("\t.byte 0,", file
);
16838 /* Language type. Unfortunately, there does not seem to be any
16839 official way to discover the language being compiled, so we
16840 use language_string.
16841 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
16842 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
16843 a number, so for now use 9. */
16844 if (! strcmp (language_string
, "GNU C"))
16846 else if (! strcmp (language_string
, "GNU F77")
16847 || ! strcmp (language_string
, "GNU F95"))
16849 else if (! strcmp (language_string
, "GNU Pascal"))
16851 else if (! strcmp (language_string
, "GNU Ada"))
16853 else if (! strcmp (language_string
, "GNU C++")
16854 || ! strcmp (language_string
, "GNU Objective-C++"))
16856 else if (! strcmp (language_string
, "GNU Java"))
16858 else if (! strcmp (language_string
, "GNU Objective-C"))
16861 gcc_unreachable ();
16862 fprintf (file
, "%d,", i
);
16864 /* 8 single bit fields: global linkage (not set for C extern linkage,
16865 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16866 from start of procedure stored in tbtab, internal function, function
16867 has controlled storage, function has no toc, function uses fp,
16868 function logs/aborts fp operations. */
16869 /* Assume that fp operations are used if any fp reg must be saved. */
16870 fprintf (file
, "%d,",
16871 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
16873 /* 6 bitfields: function is interrupt handler, name present in
16874 proc table, function calls alloca, on condition directives
16875 (controls stack walks, 3 bits), saves condition reg, saves
16877 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16878 set up as a frame pointer, even when there is no alloca call. */
16879 fprintf (file
, "%d,",
16880 ((optional_tbtab
<< 6)
16881 | ((optional_tbtab
& frame_pointer_needed
) << 5)
16882 | (info
->cr_save_p
<< 1)
16883 | (info
->lr_save_p
)));
16885 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16887 fprintf (file
, "%d,",
16888 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
16890 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16891 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
16893 if (optional_tbtab
)
16895 /* Compute the parameter info from the function decl argument
16898 int next_parm_info_bit
= 31;
16900 for (decl
= DECL_ARGUMENTS (current_function_decl
);
16901 decl
; decl
= TREE_CHAIN (decl
))
16903 rtx parameter
= DECL_INCOMING_RTL (decl
);
16904 enum machine_mode mode
= GET_MODE (parameter
);
16906 if (GET_CODE (parameter
) == REG
)
16908 if (SCALAR_FLOAT_MODE_P (mode
))
16929 gcc_unreachable ();
16932 /* If only one bit will fit, don't or in this entry. */
16933 if (next_parm_info_bit
> 0)
16934 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
16935 next_parm_info_bit
-= 2;
16939 fixed_parms
+= ((GET_MODE_SIZE (mode
)
16940 + (UNITS_PER_WORD
- 1))
16942 next_parm_info_bit
-= 1;
16948 /* Number of fixed point parameters. */
16949 /* This is actually the number of words of fixed point parameters; thus
16950 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16951 fprintf (file
, "%d,", fixed_parms
);
16953 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16955 /* This is actually the number of fp registers that hold parameters;
16956 and thus the maximum value is 13. */
16957 /* Set parameters on stack bit if parameters are not in their original
16958 registers, regardless of whether they are on the stack? Xlc
16959 seems to set the bit when not optimizing. */
16960 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
16962 if (! optional_tbtab
)
16965 /* Optional fields follow. Some are variable length. */
16967 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16968 11 double float. */
16969 /* There is an entry for each parameter in a register, in the order that
16970 they occur in the parameter list. Any intervening arguments on the
16971 stack are ignored. If the list overflows a long (max possible length
16972 34 bits) then completely leave off all elements that don't fit. */
16973 /* Only emit this long if there was at least one parameter. */
16974 if (fixed_parms
|| float_parms
)
16975 fprintf (file
, "\t.long %d\n", parm_info
);
16977 /* Offset from start of code to tb table. */
16978 fputs ("\t.long ", file
);
16979 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
16981 RS6000_OUTPUT_BASENAME (file
, fname
);
16983 assemble_name (file
, fname
);
16985 rs6000_output_function_entry (file
, fname
);
16988 /* Interrupt handler mask. */
16989 /* Omit this long, since we never set the interrupt handler bit
16992 /* Number of CTL (controlled storage) anchors. */
16993 /* Omit this long, since the has_ctl bit is never set above. */
16995 /* Displacement into stack of each CTL anchor. */
16996 /* Omit this list of longs, because there are no CTL anchors. */
16998 /* Length of function name. */
17001 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
17003 /* Function name. */
17004 assemble_string (fname
, strlen (fname
));
17006 /* Register for alloca automatic storage; this is always reg 31.
17007 Only emit this if the alloca bit was set above. */
17008 if (frame_pointer_needed
)
17009 fputs ("\t.byte 31\n", file
);
17011 fputs ("\t.align 2\n", file
);
17015 /* A C compound statement that outputs the assembler code for a thunk
17016 function, used to implement C++ virtual function calls with
17017 multiple inheritance. The thunk acts as a wrapper around a virtual
17018 function, adjusting the implicit object parameter before handing
17019 control off to the real function.
17021 First, emit code to add the integer DELTA to the location that
17022 contains the incoming first argument. Assume that this argument
17023 contains a pointer, and is the one used to pass the `this' pointer
17024 in C++. This is the incoming argument *before* the function
17025 prologue, e.g. `%o0' on a sparc. The addition must preserve the
17026 values of all other incoming arguments.
17028 After the addition, emit code to jump to FUNCTION, which is a
17029 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
17030 not touch the return address. Hence returning from FUNCTION will
17031 return to whoever called the current `thunk'.
17033 The effect must be as if FUNCTION had been called directly with the
17034 adjusted first argument. This macro is responsible for emitting
17035 all of the code for a thunk function; output_function_prologue()
17036 and output_function_epilogue() are not invoked.
17038 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
17039 been extracted from it.) It might possibly be useful on some
17040 targets, but probably not.
17042 If you do not define this macro, the target-independent code in the
17043 C++ frontend will generate a less efficient heavyweight thunk that
17044 calls FUNCTION instead of jumping to it. The generic approach does
17045 not support varargs. */
17048 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
17049 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
17052 rtx
this, insn
, funexp
;
17054 reload_completed
= 1;
17055 epilogue_completed
= 1;
17057 /* Mark the end of the (empty) prologue. */
17058 emit_note (NOTE_INSN_PROLOGUE_END
);
17060 /* Find the "this" pointer. If the function returns a structure,
17061 the structure return pointer is in r3. */
17062 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
17063 this = gen_rtx_REG (Pmode
, 4);
17065 this = gen_rtx_REG (Pmode
, 3);
17067 /* Apply the constant offset, if required. */
17070 rtx delta_rtx
= GEN_INT (delta
);
17071 emit_insn (TARGET_32BIT
17072 ? gen_addsi3 (this, this, delta_rtx
)
17073 : gen_adddi3 (this, this, delta_rtx
));
17076 /* Apply the offset from the vtable, if required. */
17079 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
17080 rtx tmp
= gen_rtx_REG (Pmode
, 12);
17082 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
17083 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
17085 emit_insn (TARGET_32BIT
17086 ? gen_addsi3 (tmp
, tmp
, vcall_offset_rtx
)
17087 : gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
17088 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
17092 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
17094 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
17096 emit_insn (TARGET_32BIT
17097 ? gen_addsi3 (this, this, tmp
)
17098 : gen_adddi3 (this, this, tmp
));
17101 /* Generate a tail call to the target function. */
17102 if (!TREE_USED (function
))
17104 assemble_external (function
);
17105 TREE_USED (function
) = 1;
17107 funexp
= XEXP (DECL_RTL (function
), 0);
17108 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
17111 if (MACHOPIC_INDIRECT
)
17112 funexp
= machopic_indirect_call_target (funexp
);
17115 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
17116 generate sibcall RTL explicitly. */
17117 insn
= emit_call_insn (
17118 gen_rtx_PARALLEL (VOIDmode
,
17120 gen_rtx_CALL (VOIDmode
,
17121 funexp
, const0_rtx
),
17122 gen_rtx_USE (VOIDmode
, const0_rtx
),
17123 gen_rtx_USE (VOIDmode
,
17124 gen_rtx_REG (SImode
,
17126 gen_rtx_RETURN (VOIDmode
))));
17127 SIBLING_CALL_P (insn
) = 1;
17130 /* Run just enough of rest_of_compilation to get the insns emitted.
17131 There's not really enough bulk here to make other passes such as
17132 instruction scheduling worth while. Note that use_thunk calls
17133 assemble_start_function and assemble_end_function. */
17134 insn
= get_insns ();
17135 insn_locators_alloc ();
17136 shorten_branches (insn
);
17137 final_start_function (insn
, file
, 1);
17138 final (insn
, file
, 1);
17139 final_end_function ();
17141 reload_completed
= 0;
17142 epilogue_completed
= 0;
17145 /* A quick summary of the various types of 'constant-pool tables'
17148 Target Flags Name One table per
17149 AIX (none) AIX TOC object file
17150 AIX -mfull-toc AIX TOC object file
17151 AIX -mminimal-toc AIX minimal TOC translation unit
17152 SVR4/EABI (none) SVR4 SDATA object file
17153 SVR4/EABI -fpic SVR4 pic object file
17154 SVR4/EABI -fPIC SVR4 PIC translation unit
17155 SVR4/EABI -mrelocatable EABI TOC function
17156 SVR4/EABI -maix AIX TOC object file
17157 SVR4/EABI -maix -mminimal-toc
17158 AIX minimal TOC translation unit
17160 Name Reg. Set by entries contains:
17161 made by addrs? fp? sum?
17163 AIX TOC 2 crt0 as Y option option
17164 AIX minimal TOC 30 prolog gcc Y Y option
17165 SVR4 SDATA 13 crt0 gcc N Y N
17166 SVR4 pic 30 prolog ld Y not yet N
17167 SVR4 PIC 30 prolog gcc Y option option
17168 EABI TOC 30 prolog gcc Y option option
17172 /* Hash functions for the hash table. */
17175 rs6000_hash_constant (rtx k
)
17177 enum rtx_code code
= GET_CODE (k
);
17178 enum machine_mode mode
= GET_MODE (k
);
17179 unsigned result
= (code
<< 3) ^ mode
;
17180 const char *format
;
17183 format
= GET_RTX_FORMAT (code
);
17184 flen
= strlen (format
);
17190 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
17193 if (mode
!= VOIDmode
)
17194 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
17206 for (; fidx
< flen
; fidx
++)
17207 switch (format
[fidx
])
17212 const char *str
= XSTR (k
, fidx
);
17213 len
= strlen (str
);
17214 result
= result
* 613 + len
;
17215 for (i
= 0; i
< len
; i
++)
17216 result
= result
* 613 + (unsigned) str
[i
];
17221 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
17225 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
17228 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
17229 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
17233 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
17234 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
17241 gcc_unreachable ();
17248 toc_hash_function (const void *hash_entry
)
17250 const struct toc_hash_struct
*thc
=
17251 (const struct toc_hash_struct
*) hash_entry
;
17252 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
17255 /* Compare H1 and H2 for equivalence. */
17258 toc_hash_eq (const void *h1
, const void *h2
)
17260 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
17261 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
17263 if (((const struct toc_hash_struct
*) h1
)->key_mode
17264 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
17267 return rtx_equal_p (r1
, r2
);
17270 /* These are the names given by the C++ front-end to vtables, and
17271 vtable-like objects. Ideally, this logic should not be here;
17272 instead, there should be some programmatic way of inquiring as
17273 to whether or not an object is a vtable. */
17275 #define VTABLE_NAME_P(NAME) \
17276 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
17277 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
17278 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
17279 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
17280 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
17283 rs6000_output_symbol_ref (FILE *file
, rtx x
)
17285 /* Currently C++ toc references to vtables can be emitted before it
17286 is decided whether the vtable is public or private. If this is
17287 the case, then the linker will eventually complain that there is
17288 a reference to an unknown section. Thus, for vtables only,
17289 we emit the TOC reference to reference the symbol and not the
17291 const char *name
= XSTR (x
, 0);
17293 if (VTABLE_NAME_P (name
))
17295 RS6000_OUTPUT_BASENAME (file
, name
);
17298 assemble_name (file
, name
);
17301 /* Output a TOC entry. We derive the entry name from what is being
17305 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
17308 const char *name
= buf
;
17309 const char *real_name
;
17311 HOST_WIDE_INT offset
= 0;
17313 gcc_assert (!TARGET_NO_TOC
);
17315 /* When the linker won't eliminate them, don't output duplicate
17316 TOC entries (this happens on AIX if there is any kind of TOC,
17317 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
17319 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
17321 struct toc_hash_struct
*h
;
17324 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
17325 time because GGC is not initialized at that point. */
17326 if (toc_hash_table
== NULL
)
17327 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
17328 toc_hash_eq
, NULL
);
17330 h
= ggc_alloc (sizeof (*h
));
17332 h
->key_mode
= mode
;
17333 h
->labelno
= labelno
;
17335 found
= htab_find_slot (toc_hash_table
, h
, 1);
17336 if (*found
== NULL
)
17338 else /* This is indeed a duplicate.
17339 Set this label equal to that label. */
17341 fputs ("\t.set ", file
);
17342 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
17343 fprintf (file
, "%d,", labelno
);
17344 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
17345 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
17351 /* If we're going to put a double constant in the TOC, make sure it's
17352 aligned properly when strict alignment is on. */
17353 if (GET_CODE (x
) == CONST_DOUBLE
17354 && STRICT_ALIGNMENT
17355 && GET_MODE_BITSIZE (mode
) >= 64
17356 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
17357 ASM_OUTPUT_ALIGN (file
, 3);
17360 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
17362 /* Handle FP constants specially. Note that if we have a minimal
17363 TOC, things we put here aren't actually in the TOC, so we can allow
17365 if (GET_CODE (x
) == CONST_DOUBLE
&&
17366 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
17368 REAL_VALUE_TYPE rv
;
17371 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17372 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17373 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
17375 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
17379 if (TARGET_MINIMAL_TOC
)
17380 fputs (DOUBLE_INT_ASM_OP
, file
);
17382 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17383 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17384 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17385 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
17386 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17387 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17392 if (TARGET_MINIMAL_TOC
)
17393 fputs ("\t.long ", file
);
17395 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17396 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17397 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17398 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
17399 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
17400 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
17404 else if (GET_CODE (x
) == CONST_DOUBLE
&&
17405 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
17407 REAL_VALUE_TYPE rv
;
17410 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17412 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17413 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
17415 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
17419 if (TARGET_MINIMAL_TOC
)
17420 fputs (DOUBLE_INT_ASM_OP
, file
);
17422 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
17423 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17424 fprintf (file
, "0x%lx%08lx\n",
17425 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17430 if (TARGET_MINIMAL_TOC
)
17431 fputs ("\t.long ", file
);
17433 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
17434 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17435 fprintf (file
, "0x%lx,0x%lx\n",
17436 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
17440 else if (GET_CODE (x
) == CONST_DOUBLE
&&
17441 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
17443 REAL_VALUE_TYPE rv
;
17446 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
17447 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
17448 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
17450 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
17454 if (TARGET_MINIMAL_TOC
)
17455 fputs (DOUBLE_INT_ASM_OP
, file
);
17457 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
17458 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
17463 if (TARGET_MINIMAL_TOC
)
17464 fputs ("\t.long ", file
);
17466 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
17467 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
17471 else if (GET_MODE (x
) == VOIDmode
17472 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
17474 unsigned HOST_WIDE_INT low
;
17475 HOST_WIDE_INT high
;
17477 if (GET_CODE (x
) == CONST_DOUBLE
)
17479 low
= CONST_DOUBLE_LOW (x
);
17480 high
= CONST_DOUBLE_HIGH (x
);
17483 #if HOST_BITS_PER_WIDE_INT == 32
17486 high
= (low
& 0x80000000) ? ~0 : 0;
17490 low
= INTVAL (x
) & 0xffffffff;
17491 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
17495 /* TOC entries are always Pmode-sized, but since this
17496 is a bigendian machine then if we're putting smaller
17497 integer constants in the TOC we have to pad them.
17498 (This is still a win over putting the constants in
17499 a separate constant pool, because then we'd have
17500 to have both a TOC entry _and_ the actual constant.)
17502 For a 32-bit target, CONST_INT values are loaded and shifted
17503 entirely within `low' and can be stored in one TOC entry. */
17505 /* It would be easy to make this work, but it doesn't now. */
17506 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
17508 if (POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
17510 #if HOST_BITS_PER_WIDE_INT == 32
17511 lshift_double (low
, high
, POINTER_SIZE
- GET_MODE_BITSIZE (mode
),
17512 POINTER_SIZE
, &low
, &high
, 0);
17515 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
17516 high
= (HOST_WIDE_INT
) low
>> 32;
17523 if (TARGET_MINIMAL_TOC
)
17524 fputs (DOUBLE_INT_ASM_OP
, file
);
17526 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
17527 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
17528 fprintf (file
, "0x%lx%08lx\n",
17529 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
17534 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
17536 if (TARGET_MINIMAL_TOC
)
17537 fputs ("\t.long ", file
);
17539 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
17540 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
17541 fprintf (file
, "0x%lx,0x%lx\n",
17542 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
17546 if (TARGET_MINIMAL_TOC
)
17547 fputs ("\t.long ", file
);
17549 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
17550 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
17556 if (GET_CODE (x
) == CONST
)
17558 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
);
17560 base
= XEXP (XEXP (x
, 0), 0);
17561 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
17564 switch (GET_CODE (base
))
17567 name
= XSTR (base
, 0);
17571 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
17572 CODE_LABEL_NUMBER (XEXP (base
, 0)));
17576 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
17580 gcc_unreachable ();
17583 real_name
= (*targetm
.strip_name_encoding
) (name
);
17584 if (TARGET_MINIMAL_TOC
)
17585 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
17588 fprintf (file
, "\t.tc %s", real_name
);
17591 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
17593 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
17595 fputs ("[TC],", file
);
17598 /* Currently C++ toc references to vtables can be emitted before it
17599 is decided whether the vtable is public or private. If this is
17600 the case, then the linker will eventually complain that there is
17601 a TOC reference to an unknown section. Thus, for vtables only,
17602 we emit the TOC reference to reference the symbol and not the
17604 if (VTABLE_NAME_P (name
))
17606 RS6000_OUTPUT_BASENAME (file
, name
);
17608 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
17609 else if (offset
> 0)
17610 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
17613 output_addr_const (file
, x
);
17617 /* Output an assembler pseudo-op to write an ASCII string of N characters
17618 starting at P to FILE.
17620 On the RS/6000, we have to do this using the .byte operation and
17621 write out special characters outside the quoted string.
17622 Also, the assembler is broken; very long strings are truncated,
17623 so we must artificially break them up early. */
17626 output_ascii (FILE *file
, const char *p
, int n
)
17629 int i
, count_string
;
17630 const char *for_string
= "\t.byte \"";
17631 const char *for_decimal
= "\t.byte ";
17632 const char *to_close
= NULL
;
17635 for (i
= 0; i
< n
; i
++)
17638 if (c
>= ' ' && c
< 0177)
17641 fputs (for_string
, file
);
17644 /* Write two quotes to get one. */
17652 for_decimal
= "\"\n\t.byte ";
17656 if (count_string
>= 512)
17658 fputs (to_close
, file
);
17660 for_string
= "\t.byte \"";
17661 for_decimal
= "\t.byte ";
17669 fputs (for_decimal
, file
);
17670 fprintf (file
, "%d", c
);
17672 for_string
= "\n\t.byte \"";
17673 for_decimal
= ", ";
17679 /* Now close the string if we have written one. Then end the line. */
17681 fputs (to_close
, file
);
17684 /* Generate a unique section name for FILENAME for a section type
17685 represented by SECTION_DESC. Output goes into BUF.
17687 SECTION_DESC can be any string, as long as it is different for each
17688 possible section type.
17690 We name the section in the same manner as xlc. The name begins with an
17691 underscore followed by the filename (after stripping any leading directory
17692 names) with the last period replaced by the string SECTION_DESC. If
17693 FILENAME does not contain a period, SECTION_DESC is appended to the end of
17697 rs6000_gen_section_name (char **buf
, const char *filename
,
17698 const char *section_desc
)
17700 const char *q
, *after_last_slash
, *last_period
= 0;
17704 after_last_slash
= filename
;
17705 for (q
= filename
; *q
; q
++)
17708 after_last_slash
= q
+ 1;
17709 else if (*q
== '.')
17713 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
17714 *buf
= (char *) xmalloc (len
);
17719 for (q
= after_last_slash
; *q
; q
++)
17721 if (q
== last_period
)
17723 strcpy (p
, section_desc
);
17724 p
+= strlen (section_desc
);
17728 else if (ISALNUM (*q
))
17732 if (last_period
== 0)
17733 strcpy (p
, section_desc
);
17738 /* Emit profile function. */
17741 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
17743 /* Non-standard profiling for kernels, which just saves LR then calls
17744 _mcount without worrying about arg saves. The idea is to change
17745 the function prologue as little as possible as it isn't easy to
17746 account for arg save/restore code added just for _mcount. */
17747 if (TARGET_PROFILE_KERNEL
)
17750 if (DEFAULT_ABI
== ABI_AIX
)
17752 #ifndef NO_PROFILE_COUNTERS
17753 # define NO_PROFILE_COUNTERS 0
17755 if (NO_PROFILE_COUNTERS
)
17756 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 0);
17760 const char *label_name
;
17763 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
17764 label_name
= (*targetm
.strip_name_encoding
) (ggc_strdup (buf
));
17765 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
17767 emit_library_call (init_one_libfunc (RS6000_MCOUNT
), 0, VOIDmode
, 1,
17771 else if (DEFAULT_ABI
== ABI_DARWIN
)
17773 const char *mcount_name
= RS6000_MCOUNT
;
17774 int caller_addr_regno
= LR_REGNO
;
17776 /* Be conservative and always set this, at least for now. */
17777 current_function_uses_pic_offset_table
= 1;
17780 /* For PIC code, set up a stub and collect the caller's address
17781 from r0, which is where the prologue puts it. */
17782 if (MACHOPIC_INDIRECT
17783 && current_function_uses_pic_offset_table
)
17784 caller_addr_regno
= 0;
17786 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
17788 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
17792 /* Write function profiler code. */
17795 output_function_profiler (FILE *file
, int labelno
)
17799 switch (DEFAULT_ABI
)
17802 gcc_unreachable ();
17807 warning (0, "no profiling of 64-bit code for this ABI");
17810 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
17811 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
17812 if (NO_PROFILE_COUNTERS
)
17814 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
17815 reg_names
[0], reg_names
[1]);
17817 else if (TARGET_SECURE_PLT
&& flag_pic
)
17819 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
17820 reg_names
[0], reg_names
[1]);
17821 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
17822 asm_fprintf (file
, "\t{cau|addis} %s,%s,",
17823 reg_names
[12], reg_names
[12]);
17824 assemble_name (file
, buf
);
17825 asm_fprintf (file
, "-1b@ha\n\t{cal|la} %s,", reg_names
[0]);
17826 assemble_name (file
, buf
);
17827 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
17829 else if (flag_pic
== 1)
17831 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
17832 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
17833 reg_names
[0], reg_names
[1]);
17834 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
17835 asm_fprintf (file
, "\t{l|lwz} %s,", reg_names
[0]);
17836 assemble_name (file
, buf
);
17837 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
17839 else if (flag_pic
> 1)
17841 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
17842 reg_names
[0], reg_names
[1]);
17843 /* Now, we need to get the address of the label. */
17844 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
17845 assemble_name (file
, buf
);
17846 fputs ("-.\n1:", file
);
17847 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
17848 asm_fprintf (file
, "\t{l|lwz} %s,0(%s)\n",
17849 reg_names
[0], reg_names
[11]);
17850 asm_fprintf (file
, "\t{cax|add} %s,%s,%s\n",
17851 reg_names
[0], reg_names
[0], reg_names
[11]);
17855 asm_fprintf (file
, "\t{liu|lis} %s,", reg_names
[12]);
17856 assemble_name (file
, buf
);
17857 fputs ("@ha\n", file
);
17858 asm_fprintf (file
, "\t{st|stw} %s,4(%s)\n",
17859 reg_names
[0], reg_names
[1]);
17860 asm_fprintf (file
, "\t{cal|la} %s,", reg_names
[0]);
17861 assemble_name (file
, buf
);
17862 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
17865 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
17866 fprintf (file
, "\tbl %s%s\n",
17867 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
17872 if (!TARGET_PROFILE_KERNEL
)
17874 /* Don't do anything, done in output_profile_hook (). */
17878 gcc_assert (!TARGET_32BIT
);
17880 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
17881 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
17883 if (cfun
->static_chain_decl
!= NULL
)
17885 asm_fprintf (file
, "\tstd %s,24(%s)\n",
17886 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
17887 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
17888 asm_fprintf (file
, "\tld %s,24(%s)\n",
17889 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
17892 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
17900 /* The following variable value is the last issued insn. */
17902 static rtx last_scheduled_insn
;
17904 /* The following variable helps to balance issuing of load and
17905 store instructions */
17907 static int load_store_pendulum
;
17909 /* Power4 load update and store update instructions are cracked into a
17910 load or store and an integer insn which are executed in the same cycle.
17911 Branches have their own dispatch slot which does not count against the
17912 GCC issue rate, but it changes the program flow so there are no other
17913 instructions to issue in this cycle. */
17916 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED
,
17917 int verbose ATTRIBUTE_UNUSED
,
17918 rtx insn
, int more
)
17920 last_scheduled_insn
= insn
;
17921 if (GET_CODE (PATTERN (insn
)) == USE
17922 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
17924 cached_can_issue_more
= more
;
17925 return cached_can_issue_more
;
17928 if (insn_terminates_group_p (insn
, current_group
))
17930 cached_can_issue_more
= 0;
17931 return cached_can_issue_more
;
17934 /* If no reservation, but reach here */
17935 if (recog_memoized (insn
) < 0)
17938 if (rs6000_sched_groups
)
17940 if (is_microcoded_insn (insn
))
17941 cached_can_issue_more
= 0;
17942 else if (is_cracked_insn (insn
))
17943 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
17945 cached_can_issue_more
= more
- 1;
17947 return cached_can_issue_more
;
17950 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
17953 cached_can_issue_more
= more
- 1;
17954 return cached_can_issue_more
;
17957 /* Adjust the cost of a scheduling dependency. Return the new cost of
17958 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17961 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
17963 enum attr_type attr_type
;
17965 if (! recog_memoized (insn
))
17968 switch (REG_NOTE_KIND (link
))
17972 /* Data dependency; DEP_INSN writes a register that INSN reads
17973 some cycles later. */
17975 /* Separate a load from a narrower, dependent store. */
17976 if (rs6000_sched_groups
17977 && GET_CODE (PATTERN (insn
)) == SET
17978 && GET_CODE (PATTERN (dep_insn
)) == SET
17979 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
17980 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
17981 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
17982 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
17985 attr_type
= get_attr_type (insn
);
17990 /* Tell the first scheduling pass about the latency between
17991 a mtctr and bctr (and mtlr and br/blr). The first
17992 scheduling pass will not know about this latency since
17993 the mtctr instruction, which has the latency associated
17994 to it, will be generated by reload. */
17995 return TARGET_POWER
? 5 : 4;
17997 /* Leave some extra cycles between a compare and its
17998 dependent branch, to inhibit expensive mispredicts. */
17999 if ((rs6000_cpu_attr
== CPU_PPC603
18000 || rs6000_cpu_attr
== CPU_PPC604
18001 || rs6000_cpu_attr
== CPU_PPC604E
18002 || rs6000_cpu_attr
== CPU_PPC620
18003 || rs6000_cpu_attr
== CPU_PPC630
18004 || rs6000_cpu_attr
== CPU_PPC750
18005 || rs6000_cpu_attr
== CPU_PPC7400
18006 || rs6000_cpu_attr
== CPU_PPC7450
18007 || rs6000_cpu_attr
== CPU_POWER4
18008 || rs6000_cpu_attr
== CPU_POWER5
18009 || rs6000_cpu_attr
== CPU_CELL
)
18010 && recog_memoized (dep_insn
)
18011 && (INSN_CODE (dep_insn
) >= 0))
18013 switch (get_attr_type (dep_insn
))
18017 case TYPE_DELAYED_COMPARE
:
18018 case TYPE_IMUL_COMPARE
:
18019 case TYPE_LMUL_COMPARE
:
18020 case TYPE_FPCOMPARE
:
18021 case TYPE_CR_LOGICAL
:
18022 case TYPE_DELAYED_CR
:
18031 case TYPE_STORE_UX
:
18033 case TYPE_FPSTORE_U
:
18034 case TYPE_FPSTORE_UX
:
18035 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18036 && recog_memoized (dep_insn
)
18037 && (INSN_CODE (dep_insn
) >= 0))
18040 if (GET_CODE (PATTERN (insn
)) != SET
)
18041 /* If this happens, we have to extend this to schedule
18042 optimally. Return default for now. */
18045 /* Adjust the cost for the case where the value written
18046 by a fixed point operation is used as the address
18047 gen value on a store. */
18048 switch (get_attr_type (dep_insn
))
18055 if (! store_data_bypass_p (dep_insn
, insn
))
18059 case TYPE_LOAD_EXT
:
18060 case TYPE_LOAD_EXT_U
:
18061 case TYPE_LOAD_EXT_UX
:
18062 case TYPE_VAR_SHIFT_ROTATE
:
18063 case TYPE_VAR_DELAYED_COMPARE
:
18065 if (! store_data_bypass_p (dep_insn
, insn
))
18071 case TYPE_FAST_COMPARE
:
18074 case TYPE_INSERT_WORD
:
18075 case TYPE_INSERT_DWORD
:
18076 case TYPE_FPLOAD_U
:
18077 case TYPE_FPLOAD_UX
:
18079 case TYPE_STORE_UX
:
18080 case TYPE_FPSTORE_U
:
18081 case TYPE_FPSTORE_UX
:
18083 if (! store_data_bypass_p (dep_insn
, insn
))
18091 case TYPE_IMUL_COMPARE
:
18092 case TYPE_LMUL_COMPARE
:
18094 if (! store_data_bypass_p (dep_insn
, insn
))
18100 if (! store_data_bypass_p (dep_insn
, insn
))
18106 if (! store_data_bypass_p (dep_insn
, insn
))
18119 case TYPE_LOAD_EXT
:
18120 case TYPE_LOAD_EXT_U
:
18121 case TYPE_LOAD_EXT_UX
:
18122 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18123 && recog_memoized (dep_insn
)
18124 && (INSN_CODE (dep_insn
) >= 0))
18127 /* Adjust the cost for the case where the value written
18128 by a fixed point instruction is used within the address
18129 gen portion of a subsequent load(u)(x) */
18130 switch (get_attr_type (dep_insn
))
18137 if (set_to_load_agen (dep_insn
, insn
))
18141 case TYPE_LOAD_EXT
:
18142 case TYPE_LOAD_EXT_U
:
18143 case TYPE_LOAD_EXT_UX
:
18144 case TYPE_VAR_SHIFT_ROTATE
:
18145 case TYPE_VAR_DELAYED_COMPARE
:
18147 if (set_to_load_agen (dep_insn
, insn
))
18153 case TYPE_FAST_COMPARE
:
18156 case TYPE_INSERT_WORD
:
18157 case TYPE_INSERT_DWORD
:
18158 case TYPE_FPLOAD_U
:
18159 case TYPE_FPLOAD_UX
:
18161 case TYPE_STORE_UX
:
18162 case TYPE_FPSTORE_U
:
18163 case TYPE_FPSTORE_UX
:
18165 if (set_to_load_agen (dep_insn
, insn
))
18173 case TYPE_IMUL_COMPARE
:
18174 case TYPE_LMUL_COMPARE
:
18176 if (set_to_load_agen (dep_insn
, insn
))
18182 if (set_to_load_agen (dep_insn
, insn
))
18188 if (set_to_load_agen (dep_insn
, insn
))
18199 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18200 && recog_memoized (dep_insn
)
18201 && (INSN_CODE (dep_insn
) >= 0)
18202 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
18209 /* Fall out to return default cost. */
18213 case REG_DEP_OUTPUT
:
18214 /* Output dependency; DEP_INSN writes a register that INSN writes some
18216 if ((rs6000_cpu
== PROCESSOR_POWER6
)
18217 && recog_memoized (dep_insn
)
18218 && (INSN_CODE (dep_insn
) >= 0))
18220 attr_type
= get_attr_type (insn
);
18225 if (get_attr_type (dep_insn
) == TYPE_FP
)
18229 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
18237 /* Anti dependency; DEP_INSN reads a register that INSN writes some
18242 gcc_unreachable ();
18248 /* The function returns a true if INSN is microcoded.
18249 Return false otherwise. */
18252 is_microcoded_insn (rtx insn
)
18254 if (!insn
|| !INSN_P (insn
)
18255 || GET_CODE (PATTERN (insn
)) == USE
18256 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18259 if (rs6000_cpu_attr
== CPU_CELL
)
18260 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
18262 if (rs6000_sched_groups
)
18264 enum attr_type type
= get_attr_type (insn
);
18265 if (type
== TYPE_LOAD_EXT_U
18266 || type
== TYPE_LOAD_EXT_UX
18267 || type
== TYPE_LOAD_UX
18268 || type
== TYPE_STORE_UX
18269 || type
== TYPE_MFCR
)
18276 /* The function returns true if INSN is cracked into 2 instructions
18277 by the processor (and therefore occupies 2 issue slots). */
18280 is_cracked_insn (rtx insn
)
18282 if (!insn
|| !INSN_P (insn
)
18283 || GET_CODE (PATTERN (insn
)) == USE
18284 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18287 if (rs6000_sched_groups
)
18289 enum attr_type type
= get_attr_type (insn
);
18290 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
18291 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
18292 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
18293 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
18294 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
18295 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
18296 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
18297 || type
== TYPE_INSERT_WORD
)
18304 /* The function returns true if INSN can be issued only from
18305 the branch slot. */
18308 is_branch_slot_insn (rtx insn
)
18310 if (!insn
|| !INSN_P (insn
)
18311 || GET_CODE (PATTERN (insn
)) == USE
18312 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18315 if (rs6000_sched_groups
)
18317 enum attr_type type
= get_attr_type (insn
);
18318 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
18326 /* The function returns true if out_inst sets a value that is
18327 used in the address generation computation of in_insn */
18329 set_to_load_agen (rtx out_insn
, rtx in_insn
)
18331 rtx out_set
, in_set
;
18333 /* For performance reasons, only handle the simple case where
18334 both loads are a single_set. */
18335 out_set
= single_set (out_insn
);
18338 in_set
= single_set (in_insn
);
18340 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
18346 /* The function returns true if the target storage location of
18347 out_insn is adjacent to the target storage location of in_insn */
18348 /* Return 1 if memory locations are adjacent. */
18351 adjacent_mem_locations (rtx insn1
, rtx insn2
)
18354 rtx a
= get_store_dest (PATTERN (insn1
));
18355 rtx b
= get_store_dest (PATTERN (insn2
));
18357 if ((GET_CODE (XEXP (a
, 0)) == REG
18358 || (GET_CODE (XEXP (a
, 0)) == PLUS
18359 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
18360 && (GET_CODE (XEXP (b
, 0)) == REG
18361 || (GET_CODE (XEXP (b
, 0)) == PLUS
18362 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
18364 HOST_WIDE_INT val0
= 0, val1
= 0, val_diff
;
18367 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
18369 reg0
= XEXP (XEXP (a
, 0), 0);
18370 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
18373 reg0
= XEXP (a
, 0);
18375 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
18377 reg1
= XEXP (XEXP (b
, 0), 0);
18378 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
18381 reg1
= XEXP (b
, 0);
18383 val_diff
= val1
- val0
;
18385 return ((REGNO (reg0
) == REGNO (reg1
))
18386 && ((MEM_SIZE (a
) && val_diff
== INTVAL (MEM_SIZE (a
)))
18387 || (MEM_SIZE (b
) && val_diff
== -INTVAL (MEM_SIZE (b
)))));
18393 /* A C statement (sans semicolon) to update the integer scheduling
18394 priority INSN_PRIORITY (INSN). Increase the priority to execute the
18395 INSN earlier, reduce the priority to execute INSN later. Do not
18396 define this macro if you do not need to adjust the scheduling
18397 priorities of insns. */
18400 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
18402 /* On machines (like the 750) which have asymmetric integer units,
18403 where one integer unit can do multiply and divides and the other
18404 can't, reduce the priority of multiply/divide so it is scheduled
18405 before other integer operations. */
18408 if (! INSN_P (insn
))
18411 if (GET_CODE (PATTERN (insn
)) == USE
)
18414 switch (rs6000_cpu_attr
) {
18416 switch (get_attr_type (insn
))
18423 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
18424 priority
, priority
);
18425 if (priority
>= 0 && priority
< 0x01000000)
18432 if (insn_must_be_first_in_group (insn
)
18433 && reload_completed
18434 && current_sched_info
->sched_max_insns_priority
18435 && rs6000_sched_restricted_insns_priority
)
18438 /* Prioritize insns that can be dispatched only in the first
18440 if (rs6000_sched_restricted_insns_priority
== 1)
18441 /* Attach highest priority to insn. This means that in
18442 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
18443 precede 'priority' (critical path) considerations. */
18444 return current_sched_info
->sched_max_insns_priority
;
18445 else if (rs6000_sched_restricted_insns_priority
== 2)
18446 /* Increase priority of insn by a minimal amount. This means that in
18447 haifa-sched.c:ready_sort(), only 'priority' (critical path)
18448 considerations precede dispatch-slot restriction considerations. */
18449 return (priority
+ 1);
18452 if (rs6000_cpu
== PROCESSOR_POWER6
18453 && ((load_store_pendulum
== -2 && is_load_insn (insn
))
18454 || (load_store_pendulum
== 2 && is_store_insn (insn
))))
18455 /* Attach highest priority to insn if the scheduler has just issued two
18456 stores and this instruction is a load, or two loads and this instruction
18457 is a store. Power6 wants loads and stores scheduled alternately
18459 return current_sched_info
->sched_max_insns_priority
;
18464 /* Return true if the instruction is nonpipelined on the Cell. */
18466 is_nonpipeline_insn (rtx insn
)
18468 enum attr_type type
;
18469 if (!insn
|| !INSN_P (insn
)
18470 || GET_CODE (PATTERN (insn
)) == USE
18471 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
18474 type
= get_attr_type (insn
);
18475 if (type
== TYPE_IMUL
18476 || type
== TYPE_IMUL2
18477 || type
== TYPE_IMUL3
18478 || type
== TYPE_LMUL
18479 || type
== TYPE_IDIV
18480 || type
== TYPE_LDIV
18481 || type
== TYPE_SDIV
18482 || type
== TYPE_DDIV
18483 || type
== TYPE_SSQRT
18484 || type
== TYPE_DSQRT
18485 || type
== TYPE_MFCR
18486 || type
== TYPE_MFCRF
18487 || type
== TYPE_MFJMPR
)
18495 /* Return how many instructions the machine can issue per cycle. */
18498 rs6000_issue_rate (void)
18500 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
18501 if (!reload_completed
)
18504 switch (rs6000_cpu_attr
) {
18505 case CPU_RIOS1
: /* ? */
18507 case CPU_PPC601
: /* ? */
18532 /* Return how many instructions to look ahead for better insn
18536 rs6000_use_sched_lookahead (void)
18538 if (rs6000_cpu_attr
== CPU_PPC8540
)
18540 if (rs6000_cpu_attr
== CPU_CELL
)
18541 return (reload_completed
? 8 : 0);
18545 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
18547 rs6000_use_sched_lookahead_guard (rtx insn
)
18549 if (rs6000_cpu_attr
!= CPU_CELL
)
18552 if (insn
== NULL_RTX
|| !INSN_P (insn
))
18555 if (!reload_completed
18556 || is_nonpipeline_insn (insn
)
18557 || is_microcoded_insn (insn
))
18563 /* Determine is PAT refers to memory. */
18566 is_mem_ref (rtx pat
)
18572 /* stack_tie does not produce any real memory traffic. */
18573 if (GET_CODE (pat
) == UNSPEC
18574 && XINT (pat
, 1) == UNSPEC_TIE
)
18577 if (GET_CODE (pat
) == MEM
)
18580 /* Recursively process the pattern. */
18581 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
18583 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0 && !ret
; i
--)
18586 ret
|= is_mem_ref (XEXP (pat
, i
));
18587 else if (fmt
[i
] == 'E')
18588 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
18589 ret
|= is_mem_ref (XVECEXP (pat
, i
, j
));
18595 /* Determine if PAT is a PATTERN of a load insn. */
18598 is_load_insn1 (rtx pat
)
18600 if (!pat
|| pat
== NULL_RTX
)
18603 if (GET_CODE (pat
) == SET
)
18604 return is_mem_ref (SET_SRC (pat
));
18606 if (GET_CODE (pat
) == PARALLEL
)
18610 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
18611 if (is_load_insn1 (XVECEXP (pat
, 0, i
)))
18618 /* Determine if INSN loads from memory. */
18621 is_load_insn (rtx insn
)
18623 if (!insn
|| !INSN_P (insn
))
18626 if (GET_CODE (insn
) == CALL_INSN
)
18629 return is_load_insn1 (PATTERN (insn
));
18632 /* Determine if PAT is a PATTERN of a store insn. */
18635 is_store_insn1 (rtx pat
)
18637 if (!pat
|| pat
== NULL_RTX
)
18640 if (GET_CODE (pat
) == SET
)
18641 return is_mem_ref (SET_DEST (pat
));
18643 if (GET_CODE (pat
) == PARALLEL
)
18647 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
18648 if (is_store_insn1 (XVECEXP (pat
, 0, i
)))
18655 /* Determine if INSN stores to memory. */
18658 is_store_insn (rtx insn
)
18660 if (!insn
|| !INSN_P (insn
))
18663 return is_store_insn1 (PATTERN (insn
));
18666 /* Return the dest of a store insn. */
18669 get_store_dest (rtx pat
)
18671 gcc_assert (is_store_insn1 (pat
));
18673 if (GET_CODE (pat
) == SET
)
18674 return SET_DEST (pat
);
18675 else if (GET_CODE (pat
) == PARALLEL
)
18679 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
18681 rtx inner_pat
= XVECEXP (pat
, 0, i
);
18682 if (GET_CODE (inner_pat
) == SET
18683 && is_mem_ref (SET_DEST (inner_pat
)))
18687 /* We shouldn't get here, because we should have either a simple
18688 store insn or a store with update which are covered above. */
18692 /* Returns whether the dependence between INSN and NEXT is considered
18693 costly by the given target. */
18696 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
18701 /* If the flag is not enabled - no dependence is considered costly;
18702 allow all dependent insns in the same group.
18703 This is the most aggressive option. */
18704 if (rs6000_sched_costly_dep
== no_dep_costly
)
18707 /* If the flag is set to 1 - a dependence is always considered costly;
18708 do not allow dependent instructions in the same group.
18709 This is the most conservative option. */
18710 if (rs6000_sched_costly_dep
== all_deps_costly
)
18713 insn
= DEP_PRO (dep
);
18714 next
= DEP_CON (dep
);
18716 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
18717 && is_load_insn (next
)
18718 && is_store_insn (insn
))
18719 /* Prevent load after store in the same group. */
18722 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
18723 && is_load_insn (next
)
18724 && is_store_insn (insn
)
18725 && DEP_TYPE (dep
) == REG_DEP_TRUE
)
18726 /* Prevent load after store in the same group if it is a true
18730 /* The flag is set to X; dependences with latency >= X are considered costly,
18731 and will not be scheduled in the same group. */
18732 if (rs6000_sched_costly_dep
<= max_dep_latency
18733 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
18739 /* Return the next insn after INSN that is found before TAIL is reached,
18740 skipping any "non-active" insns - insns that will not actually occupy
18741 an issue slot. Return NULL_RTX if such an insn is not found. */
18744 get_next_active_insn (rtx insn
, rtx tail
)
18746 if (insn
== NULL_RTX
|| insn
== tail
)
18751 insn
= NEXT_INSN (insn
);
18752 if (insn
== NULL_RTX
|| insn
== tail
)
18757 || (NONJUMP_INSN_P (insn
)
18758 && GET_CODE (PATTERN (insn
)) != USE
18759 && GET_CODE (PATTERN (insn
)) != CLOBBER
18760 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
18766 /* We are about to begin issuing insns for this clock cycle. */
18769 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
18770 rtx
*ready ATTRIBUTE_UNUSED
,
18771 int *pn_ready ATTRIBUTE_UNUSED
,
18772 int clock_var ATTRIBUTE_UNUSED
)
18774 int n_ready
= *pn_ready
;
18777 fprintf (dump
, "// rs6000_sched_reorder :\n");
18779 /* Reorder the ready list, if the second to last ready insn
18780 is a nonepipeline insn. */
18781 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
18783 if (is_nonpipeline_insn (ready
[n_ready
- 1])
18784 && (recog_memoized (ready
[n_ready
- 2]) > 0))
18785 /* Simply swap first two insns. */
18787 rtx tmp
= ready
[n_ready
- 1];
18788 ready
[n_ready
- 1] = ready
[n_ready
- 2];
18789 ready
[n_ready
- 2] = tmp
;
18793 if (rs6000_cpu
== PROCESSOR_POWER6
)
18794 load_store_pendulum
= 0;
18796 return rs6000_issue_rate ();
18799 /* Like rs6000_sched_reorder, but called after issuing each insn. */
18802 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
18803 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
18806 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
18808 /* For Power6, we need to handle some special cases to try and keep the
18809 store queue from overflowing and triggering expensive flushes.
18811 This code monitors how load and store instructions are being issued
18812 and skews the ready list one way or the other to increase the likelihood
18813 that a desired instruction is issued at the proper time.
18815 A couple of things are done. First, we maintain a "load_store_pendulum"
18816 to track the current state of load/store issue.
18818 - If the pendulum is at zero, then no loads or stores have been
18819 issued in the current cycle so we do nothing.
18821 - If the pendulum is 1, then a single load has been issued in this
18822 cycle and we attempt to locate another load in the ready list to
18825 - If the pendulum is -2, then two stores have already been
18826 issued in this cycle, so we increase the priority of the first load
18827 in the ready list to increase it's likelihood of being chosen first
18830 - If the pendulum is -1, then a single store has been issued in this
18831 cycle and we attempt to locate another store in the ready list to
18832 issue with it, preferring a store to an adjacent memory location to
18833 facilitate store pairing in the store queue.
18835 - If the pendulum is 2, then two loads have already been
18836 issued in this cycle, so we increase the priority of the first store
18837 in the ready list to increase it's likelihood of being chosen first
18840 - If the pendulum < -2 or > 2, then do nothing.
18842 Note: This code covers the most common scenarios. There exist non
18843 load/store instructions which make use of the LSU and which
18844 would need to be accounted for to strictly model the behavior
18845 of the machine. Those instructions are currently unaccounted
18846 for to help minimize compile time overhead of this code.
18848 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
18854 if (is_store_insn (last_scheduled_insn
))
18855 /* Issuing a store, swing the load_store_pendulum to the left */
18856 load_store_pendulum
--;
18857 else if (is_load_insn (last_scheduled_insn
))
18858 /* Issuing a load, swing the load_store_pendulum to the right */
18859 load_store_pendulum
++;
18861 return cached_can_issue_more
;
18863 /* If the pendulum is balanced, or there is only one instruction on
18864 the ready list, then all is well, so return. */
18865 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
18866 return cached_can_issue_more
;
18868 if (load_store_pendulum
== 1)
18870 /* A load has been issued in this cycle. Scan the ready list
18871 for another load to issue with it */
18876 if (is_load_insn (ready
[pos
]))
18878 /* Found a load. Move it to the head of the ready list,
18879 and adjust it's priority so that it is more likely to
18882 for (i
=pos
; i
<*pn_ready
-1; i
++)
18883 ready
[i
] = ready
[i
+ 1];
18884 ready
[*pn_ready
-1] = tmp
;
18885 if INSN_PRIORITY_KNOWN (tmp
)
18886 INSN_PRIORITY (tmp
)++;
18892 else if (load_store_pendulum
== -2)
18894 /* Two stores have been issued in this cycle. Increase the
18895 priority of the first load in the ready list to favor it for
18896 issuing in the next cycle. */
18901 if (is_load_insn (ready
[pos
])
18902 && INSN_PRIORITY_KNOWN (ready
[pos
]))
18904 INSN_PRIORITY (ready
[pos
])++;
18906 /* Adjust the pendulum to account for the fact that a load
18907 was found and increased in priority. This is to prevent
18908 increasing the priority of multiple loads */
18909 load_store_pendulum
--;
18916 else if (load_store_pendulum
== -1)
18918 /* A store has been issued in this cycle. Scan the ready list for
18919 another store to issue with it, preferring a store to an adjacent
18921 int first_store_pos
= -1;
18927 if (is_store_insn (ready
[pos
]))
18929 /* Maintain the index of the first store found on the
18931 if (first_store_pos
== -1)
18932 first_store_pos
= pos
;
18934 if (is_store_insn (last_scheduled_insn
)
18935 && adjacent_mem_locations (last_scheduled_insn
,ready
[pos
]))
18937 /* Found an adjacent store. Move it to the head of the
18938 ready list, and adjust it's priority so that it is
18939 more likely to stay there */
18941 for (i
=pos
; i
<*pn_ready
-1; i
++)
18942 ready
[i
] = ready
[i
+ 1];
18943 ready
[*pn_ready
-1] = tmp
;
18944 if INSN_PRIORITY_KNOWN (tmp
)
18945 INSN_PRIORITY (tmp
)++;
18946 first_store_pos
= -1;
18954 if (first_store_pos
>= 0)
18956 /* An adjacent store wasn't found, but a non-adjacent store was,
18957 so move the non-adjacent store to the front of the ready
18958 list, and adjust its priority so that it is more likely to
18960 tmp
= ready
[first_store_pos
];
18961 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
18962 ready
[i
] = ready
[i
+ 1];
18963 ready
[*pn_ready
-1] = tmp
;
18964 if INSN_PRIORITY_KNOWN (tmp
)
18965 INSN_PRIORITY (tmp
)++;
18968 else if (load_store_pendulum
== 2)
18970 /* Two loads have been issued in this cycle. Increase the priority
18971 of the first store in the ready list to favor it for issuing in
18977 if (is_store_insn (ready
[pos
])
18978 && INSN_PRIORITY_KNOWN (ready
[pos
]))
18980 INSN_PRIORITY (ready
[pos
])++;
18982 /* Adjust the pendulum to account for the fact that a store
18983 was found and increased in priority. This is to prevent
18984 increasing the priority of multiple stores */
18985 load_store_pendulum
++;
18994 return cached_can_issue_more
;
18997 /* Return whether the presence of INSN causes a dispatch group termination
18998 of group WHICH_GROUP.
19000 If WHICH_GROUP == current_group, this function will return true if INSN
19001 causes the termination of the current group (i.e, the dispatch group to
19002 which INSN belongs). This means that INSN will be the last insn in the
19003 group it belongs to.
19005 If WHICH_GROUP == previous_group, this function will return true if INSN
19006 causes the termination of the previous group (i.e, the dispatch group that
19007 precedes the group to which INSN belongs). This means that INSN will be
19008 the first insn in the group it belongs to). */
19011 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
19018 first
= insn_must_be_first_in_group (insn
);
19019 last
= insn_must_be_last_in_group (insn
);
19024 if (which_group
== current_group
)
19026 else if (which_group
== previous_group
)
19034 insn_must_be_first_in_group (rtx insn
)
19036 enum attr_type type
;
19039 || insn
== NULL_RTX
19040 || GET_CODE (insn
) == NOTE
19041 || GET_CODE (PATTERN (insn
)) == USE
19042 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19045 switch (rs6000_cpu
)
19047 case PROCESSOR_POWER5
:
19048 if (is_cracked_insn (insn
))
19050 case PROCESSOR_POWER4
:
19051 if (is_microcoded_insn (insn
))
19054 if (!rs6000_sched_groups
)
19057 type
= get_attr_type (insn
);
19064 case TYPE_DELAYED_CR
:
19065 case TYPE_CR_LOGICAL
:
19079 case PROCESSOR_POWER6
:
19080 type
= get_attr_type (insn
);
19084 case TYPE_INSERT_DWORD
:
19088 case TYPE_VAR_SHIFT_ROTATE
:
19095 case TYPE_INSERT_WORD
:
19096 case TYPE_DELAYED_COMPARE
:
19097 case TYPE_IMUL_COMPARE
:
19098 case TYPE_LMUL_COMPARE
:
19099 case TYPE_FPCOMPARE
:
19110 case TYPE_LOAD_EXT_UX
:
19112 case TYPE_STORE_UX
:
19113 case TYPE_FPLOAD_U
:
19114 case TYPE_FPLOAD_UX
:
19115 case TYPE_FPSTORE_U
:
19116 case TYPE_FPSTORE_UX
:
19130 insn_must_be_last_in_group (rtx insn
)
19132 enum attr_type type
;
19135 || insn
== NULL_RTX
19136 || GET_CODE (insn
) == NOTE
19137 || GET_CODE (PATTERN (insn
)) == USE
19138 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
19141 switch (rs6000_cpu
) {
19142 case PROCESSOR_POWER4
:
19143 case PROCESSOR_POWER5
:
19144 if (is_microcoded_insn (insn
))
19147 if (is_branch_slot_insn (insn
))
19151 case PROCESSOR_POWER6
:
19152 type
= get_attr_type (insn
);
19159 case TYPE_VAR_SHIFT_ROTATE
:
19166 case TYPE_DELAYED_COMPARE
:
19167 case TYPE_IMUL_COMPARE
:
19168 case TYPE_LMUL_COMPARE
:
19169 case TYPE_FPCOMPARE
:
19190 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
19191 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
19194 is_costly_group (rtx
*group_insns
, rtx next_insn
)
19197 int issue_rate
= rs6000_issue_rate ();
19199 for (i
= 0; i
< issue_rate
; i
++)
19201 sd_iterator_def sd_it
;
19203 rtx insn
= group_insns
[i
];
19208 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
19210 rtx next
= DEP_CON (dep
);
19212 if (next
== next_insn
19213 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
19221 /* Utility of the function redefine_groups.
19222 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
19223 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
19224 to keep it "far" (in a separate group) from GROUP_INSNS, following
19225 one of the following schemes, depending on the value of the flag
19226 -minsert_sched_nops = X:
19227 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
19228 in order to force NEXT_INSN into a separate group.
19229 (2) X < sched_finish_regroup_exact: insert exactly X nops.
19230 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
19231 insertion (has a group just ended, how many vacant issue slots remain in the
19232 last group, and how many dispatch groups were encountered so far). */
19235 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
19236 rtx next_insn
, bool *group_end
, int can_issue_more
,
19241 int issue_rate
= rs6000_issue_rate ();
19242 bool end
= *group_end
;
19245 if (next_insn
== NULL_RTX
)
19246 return can_issue_more
;
19248 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
19249 return can_issue_more
;
19251 force
= is_costly_group (group_insns
, next_insn
);
19253 return can_issue_more
;
19255 if (sched_verbose
> 6)
19256 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
19257 *group_count
,can_issue_more
);
19259 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
19262 can_issue_more
= 0;
19264 /* Since only a branch can be issued in the last issue_slot, it is
19265 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
19266 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
19267 in this case the last nop will start a new group and the branch
19268 will be forced to the new group. */
19269 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
19272 while (can_issue_more
> 0)
19275 emit_insn_before (nop
, next_insn
);
19283 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
19285 int n_nops
= rs6000_sched_insert_nops
;
19287 /* Nops can't be issued from the branch slot, so the effective
19288 issue_rate for nops is 'issue_rate - 1'. */
19289 if (can_issue_more
== 0)
19290 can_issue_more
= issue_rate
;
19292 if (can_issue_more
== 0)
19294 can_issue_more
= issue_rate
- 1;
19297 for (i
= 0; i
< issue_rate
; i
++)
19299 group_insns
[i
] = 0;
19306 emit_insn_before (nop
, next_insn
);
19307 if (can_issue_more
== issue_rate
- 1) /* new group begins */
19310 if (can_issue_more
== 0)
19312 can_issue_more
= issue_rate
- 1;
19315 for (i
= 0; i
< issue_rate
; i
++)
19317 group_insns
[i
] = 0;
19323 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
19326 /* Is next_insn going to start a new group? */
19329 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
19330 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
19331 || (can_issue_more
< issue_rate
&&
19332 insn_terminates_group_p (next_insn
, previous_group
)));
19333 if (*group_end
&& end
)
19336 if (sched_verbose
> 6)
19337 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
19338 *group_count
, can_issue_more
);
19339 return can_issue_more
;
19342 return can_issue_more
;
19345 /* This function tries to synch the dispatch groups that the compiler "sees"
19346 with the dispatch groups that the processor dispatcher is expected to
19347 form in practice. It tries to achieve this synchronization by forcing the
19348 estimated processor grouping on the compiler (as opposed to the function
19349 'pad_goups' which tries to force the scheduler's grouping on the processor).
19351 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
19352 examines the (estimated) dispatch groups that will be formed by the processor
19353 dispatcher. It marks these group boundaries to reflect the estimated
19354 processor grouping, overriding the grouping that the scheduler had marked.
19355 Depending on the value of the flag '-minsert-sched-nops' this function can
19356 force certain insns into separate groups or force a certain distance between
19357 them by inserting nops, for example, if there exists a "costly dependence"
19360 The function estimates the group boundaries that the processor will form as
19361 follows: It keeps track of how many vacant issue slots are available after
19362 each insn. A subsequent insn will start a new group if one of the following
19364 - no more vacant issue slots remain in the current dispatch group.
19365 - only the last issue slot, which is the branch slot, is vacant, but the next
19366 insn is not a branch.
19367 - only the last 2 or less issue slots, including the branch slot, are vacant,
19368 which means that a cracked insn (which occupies two issue slots) can't be
19369 issued in this group.
19370 - less than 'issue_rate' slots are vacant, and the next insn always needs to
19371 start a new group. */
19374 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
19376 rtx insn
, next_insn
;
19378 int can_issue_more
;
19381 int group_count
= 0;
19385 issue_rate
= rs6000_issue_rate ();
19386 group_insns
= alloca (issue_rate
* sizeof (rtx
));
19387 for (i
= 0; i
< issue_rate
; i
++)
19389 group_insns
[i
] = 0;
19391 can_issue_more
= issue_rate
;
19393 insn
= get_next_active_insn (prev_head_insn
, tail
);
19396 while (insn
!= NULL_RTX
)
19398 slot
= (issue_rate
- can_issue_more
);
19399 group_insns
[slot
] = insn
;
19401 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
19402 if (insn_terminates_group_p (insn
, current_group
))
19403 can_issue_more
= 0;
19405 next_insn
= get_next_active_insn (insn
, tail
);
19406 if (next_insn
== NULL_RTX
)
19407 return group_count
+ 1;
19409 /* Is next_insn going to start a new group? */
19411 = (can_issue_more
== 0
19412 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
19413 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
19414 || (can_issue_more
< issue_rate
&&
19415 insn_terminates_group_p (next_insn
, previous_group
)));
19417 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
19418 next_insn
, &group_end
, can_issue_more
,
19424 can_issue_more
= 0;
19425 for (i
= 0; i
< issue_rate
; i
++)
19427 group_insns
[i
] = 0;
19431 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
19432 PUT_MODE (next_insn
, VOIDmode
);
19433 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
19434 PUT_MODE (next_insn
, TImode
);
19437 if (can_issue_more
== 0)
19438 can_issue_more
= issue_rate
;
19441 return group_count
;
19444 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
19445 dispatch group boundaries that the scheduler had marked. Pad with nops
19446 any dispatch groups which have vacant issue slots, in order to force the
19447 scheduler's grouping on the processor dispatcher. The function
19448 returns the number of dispatch groups found. */
19451 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
19453 rtx insn
, next_insn
;
19456 int can_issue_more
;
19458 int group_count
= 0;
19460 /* Initialize issue_rate. */
19461 issue_rate
= rs6000_issue_rate ();
19462 can_issue_more
= issue_rate
;
19464 insn
= get_next_active_insn (prev_head_insn
, tail
);
19465 next_insn
= get_next_active_insn (insn
, tail
);
19467 while (insn
!= NULL_RTX
)
19470 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
19472 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
19474 if (next_insn
== NULL_RTX
)
19479 /* If the scheduler had marked group termination at this location
19480 (between insn and next_indn), and neither insn nor next_insn will
19481 force group termination, pad the group with nops to force group
19484 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
19485 && !insn_terminates_group_p (insn
, current_group
)
19486 && !insn_terminates_group_p (next_insn
, previous_group
))
19488 if (!is_branch_slot_insn (next_insn
))
19491 while (can_issue_more
)
19494 emit_insn_before (nop
, next_insn
);
19499 can_issue_more
= issue_rate
;
19504 next_insn
= get_next_active_insn (insn
, tail
);
19507 return group_count
;
19510 /* We're beginning a new block. Initialize data structures as necessary. */
19513 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
19514 int sched_verbose ATTRIBUTE_UNUSED
,
19515 int max_ready ATTRIBUTE_UNUSED
)
19517 last_scheduled_insn
= NULL_RTX
;
19518 load_store_pendulum
= 0;
19521 /* The following function is called at the end of scheduling BB.
19522 After reload, it inserts nops at insn group bundling. */
19525 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
19530 fprintf (dump
, "=== Finishing schedule.\n");
19532 if (reload_completed
&& rs6000_sched_groups
)
19534 if (rs6000_sched_insert_nops
== sched_finish_none
)
19537 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
19538 n_groups
= pad_groups (dump
, sched_verbose
,
19539 current_sched_info
->prev_head
,
19540 current_sched_info
->next_tail
);
19542 n_groups
= redefine_groups (dump
, sched_verbose
,
19543 current_sched_info
->prev_head
,
19544 current_sched_info
->next_tail
);
19546 if (sched_verbose
>= 6)
19548 fprintf (dump
, "ngroups = %d\n", n_groups
);
19549 print_rtl (dump
, current_sched_info
->prev_head
);
19550 fprintf (dump
, "Done finish_sched\n");
19555 /* Length in units of the trampoline for entering a nested function. */
19558 rs6000_trampoline_size (void)
19562 switch (DEFAULT_ABI
)
19565 gcc_unreachable ();
19568 ret
= (TARGET_32BIT
) ? 12 : 24;
19573 ret
= (TARGET_32BIT
) ? 40 : 48;
19580 /* Emit RTL insns to initialize the variable parts of a trampoline.
19581 FNADDR is an RTX for the address of the function's pure code.
19582 CXT is an RTX for the static chain value for the function. */
19585 rs6000_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
19587 int regsize
= (TARGET_32BIT
) ? 4 : 8;
19588 rtx ctx_reg
= force_reg (Pmode
, cxt
);
19590 switch (DEFAULT_ABI
)
19593 gcc_unreachable ();
19595 /* Macros to shorten the code expansions below. */
19596 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
19597 #define MEM_PLUS(addr,offset) \
19598 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
19600 /* Under AIX, just build the 3 word function descriptor */
19603 rtx fn_reg
= gen_reg_rtx (Pmode
);
19604 rtx toc_reg
= gen_reg_rtx (Pmode
);
19605 emit_move_insn (fn_reg
, MEM_DEREF (fnaddr
));
19606 emit_move_insn (toc_reg
, MEM_PLUS (fnaddr
, regsize
));
19607 emit_move_insn (MEM_DEREF (addr
), fn_reg
);
19608 emit_move_insn (MEM_PLUS (addr
, regsize
), toc_reg
);
19609 emit_move_insn (MEM_PLUS (addr
, 2*regsize
), ctx_reg
);
19613 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
19616 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
19617 FALSE
, VOIDmode
, 4,
19619 GEN_INT (rs6000_trampoline_size ()), SImode
,
19629 /* Table of valid machine attributes. */
19631 const struct attribute_spec rs6000_attribute_table
[] =
19633 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
19634 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
},
19635 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
19636 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
},
19637 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
19638 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
},
19639 #ifdef SUBTARGET_ATTRIBUTE_TABLE
19640 SUBTARGET_ATTRIBUTE_TABLE
,
19642 { NULL
, 0, 0, false, false, false, NULL
}
19645 /* Handle the "altivec" attribute. The attribute may have
19646 arguments as follows:
19648 __attribute__((altivec(vector__)))
19649 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
19650 __attribute__((altivec(bool__))) (always followed by 'unsigned')
19652 and may appear more than once (e.g., 'vector bool char') in a
19653 given declaration. */
19656 rs6000_handle_altivec_attribute (tree
*node
,
19657 tree name ATTRIBUTE_UNUSED
,
19659 int flags ATTRIBUTE_UNUSED
,
19660 bool *no_add_attrs
)
19662 tree type
= *node
, result
= NULL_TREE
;
19663 enum machine_mode mode
;
19666 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
19667 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
19668 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
19671 while (POINTER_TYPE_P (type
)
19672 || TREE_CODE (type
) == FUNCTION_TYPE
19673 || TREE_CODE (type
) == METHOD_TYPE
19674 || TREE_CODE (type
) == ARRAY_TYPE
)
19675 type
= TREE_TYPE (type
);
19677 mode
= TYPE_MODE (type
);
19679 /* Check for invalid AltiVec type qualifiers. */
19680 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
19683 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
19684 else if (rs6000_warn_altivec_long
)
19685 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
19687 else if (type
== long_long_unsigned_type_node
19688 || type
== long_long_integer_type_node
)
19689 error ("use of %<long long%> in AltiVec types is invalid");
19690 else if (type
== double_type_node
)
19691 error ("use of %<double%> in AltiVec types is invalid");
19692 else if (type
== long_double_type_node
)
19693 error ("use of %<long double%> in AltiVec types is invalid");
19694 else if (type
== boolean_type_node
)
19695 error ("use of boolean types in AltiVec types is invalid");
19696 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
19697 error ("use of %<complex%> in AltiVec types is invalid");
19698 else if (DECIMAL_FLOAT_MODE_P (mode
))
19699 error ("use of decimal floating point types in AltiVec types is invalid");
19701 switch (altivec_type
)
19704 unsigned_p
= TYPE_UNSIGNED (type
);
19708 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
19711 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
19714 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
19716 case SFmode
: result
= V4SF_type_node
; break;
19717 /* If the user says 'vector int bool', we may be handed the 'bool'
19718 attribute _before_ the 'vector' attribute, and so select the
19719 proper type in the 'b' case below. */
19720 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
19728 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
19729 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
19730 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
19737 case V8HImode
: result
= pixel_V8HI_type_node
;
19743 if (result
&& result
!= type
&& TYPE_READONLY (type
))
19744 result
= build_qualified_type (result
, TYPE_QUAL_CONST
);
19746 *no_add_attrs
= true; /* No need to hang on to the attribute. */
19749 *node
= reconstruct_complex_type (*node
, result
);
19754 /* AltiVec defines four built-in scalar types that serve as vector
19755 elements; we must teach the compiler how to mangle them. */
19757 static const char *
19758 rs6000_mangle_type (const_tree type
)
19760 type
= TYPE_MAIN_VARIANT (type
);
19762 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
19763 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
19766 if (type
== bool_char_type_node
) return "U6__boolc";
19767 if (type
== bool_short_type_node
) return "U6__bools";
19768 if (type
== pixel_type_node
) return "u7__pixel";
19769 if (type
== bool_int_type_node
) return "U6__booli";
19771 /* Mangle IBM extended float long double as `g' (__float128) on
19772 powerpc*-linux where long-double-64 previously was the default. */
19773 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
19775 && TARGET_LONG_DOUBLE_128
19776 && !TARGET_IEEEQUAD
)
19779 /* For all other types, use normal C++ mangling. */
19783 /* Handle a "longcall" or "shortcall" attribute; arguments as in
19784 struct attribute_spec.handler. */
19787 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
19788 tree args ATTRIBUTE_UNUSED
,
19789 int flags ATTRIBUTE_UNUSED
,
19790 bool *no_add_attrs
)
19792 if (TREE_CODE (*node
) != FUNCTION_TYPE
19793 && TREE_CODE (*node
) != FIELD_DECL
19794 && TREE_CODE (*node
) != TYPE_DECL
)
19796 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
19797 IDENTIFIER_POINTER (name
));
19798 *no_add_attrs
= true;
19804 /* Set longcall attributes on all functions declared when
19805 rs6000_default_long_calls is true. */
19807 rs6000_set_default_type_attributes (tree type
)
19809 if (rs6000_default_long_calls
19810 && (TREE_CODE (type
) == FUNCTION_TYPE
19811 || TREE_CODE (type
) == METHOD_TYPE
))
19812 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
19814 TYPE_ATTRIBUTES (type
));
19817 darwin_set_default_type_attributes (type
);
19821 /* Return a reference suitable for calling a function with the
19822 longcall attribute. */
19825 rs6000_longcall_ref (rtx call_ref
)
19827 const char *call_name
;
19830 if (GET_CODE (call_ref
) != SYMBOL_REF
)
19833 /* System V adds '.' to the internal name, so skip them. */
19834 call_name
= XSTR (call_ref
, 0);
19835 if (*call_name
== '.')
19837 while (*call_name
== '.')
19840 node
= get_identifier (call_name
);
19841 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
19844 return force_reg (Pmode
, call_ref
);
19847 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
19848 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
19851 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19852 struct attribute_spec.handler. */
19854 rs6000_handle_struct_attribute (tree
*node
, tree name
,
19855 tree args ATTRIBUTE_UNUSED
,
19856 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
19859 if (DECL_P (*node
))
19861 if (TREE_CODE (*node
) == TYPE_DECL
)
19862 type
= &TREE_TYPE (*node
);
19867 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
19868 || TREE_CODE (*type
) == UNION_TYPE
)))
19870 warning (OPT_Wattributes
, "%qs attribute ignored", IDENTIFIER_POINTER (name
));
19871 *no_add_attrs
= true;
19874 else if ((is_attribute_p ("ms_struct", name
)
19875 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
19876 || ((is_attribute_p ("gcc_struct", name
)
19877 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
19879 warning (OPT_Wattributes
, "%qs incompatible attribute ignored",
19880 IDENTIFIER_POINTER (name
));
19881 *no_add_attrs
= true;
19888 rs6000_ms_bitfield_layout_p (const_tree record_type
)
19890 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
19891 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
19892 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
19895 #ifdef USING_ELFOS_H
19897 /* A get_unnamed_section callback, used for switching to toc_section. */
19900 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
19902 if (DEFAULT_ABI
== ABI_AIX
19903 && TARGET_MINIMAL_TOC
19904 && !TARGET_RELOCATABLE
)
19906 if (!toc_initialized
)
19908 toc_initialized
= 1;
19909 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
19910 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
19911 fprintf (asm_out_file
, "\t.tc ");
19912 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
19913 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
19914 fprintf (asm_out_file
, "\n");
19916 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
19917 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
19918 fprintf (asm_out_file
, " = .+32768\n");
19921 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
19923 else if (DEFAULT_ABI
== ABI_AIX
&& !TARGET_RELOCATABLE
)
19924 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
19927 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
19928 if (!toc_initialized
)
19930 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
19931 fprintf (asm_out_file
, " = .+32768\n");
19932 toc_initialized
= 1;
19937 /* Implement TARGET_ASM_INIT_SECTIONS. */
19940 rs6000_elf_asm_init_sections (void)
19943 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
19946 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
19947 SDATA2_SECTION_ASM_OP
);
19950 /* Implement TARGET_SELECT_RTX_SECTION. */
19953 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
19954 unsigned HOST_WIDE_INT align
)
19956 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
19957 return toc_section
;
19959 return default_elf_select_rtx_section (mode
, x
, align
);
19962 /* For a SYMBOL_REF, set generic flags and then perform some
19963 target-specific processing.
19965 When the AIX ABI is requested on a non-AIX system, replace the
19966 function name with the real name (with a leading .) rather than the
19967 function descriptor name. This saves a lot of overriding code to
19968 read the prefixes. */
19971 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
19973 default_encode_section_info (decl
, rtl
, first
);
19976 && TREE_CODE (decl
) == FUNCTION_DECL
19978 && DEFAULT_ABI
== ABI_AIX
)
19980 rtx sym_ref
= XEXP (rtl
, 0);
19981 size_t len
= strlen (XSTR (sym_ref
, 0));
19982 char *str
= alloca (len
+ 2);
19984 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
19985 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
19990 compare_section_name (const char *section
, const char *template)
19994 len
= strlen (template);
19995 return (strncmp (section
, template, len
) == 0
19996 && (section
[len
] == 0 || section
[len
] == '.'));
20000 rs6000_elf_in_small_data_p (const_tree decl
)
20002 if (rs6000_sdata
== SDATA_NONE
)
20005 /* We want to merge strings, so we never consider them small data. */
20006 if (TREE_CODE (decl
) == STRING_CST
)
20009 /* Functions are never in the small data area. */
20010 if (TREE_CODE (decl
) == FUNCTION_DECL
)
20013 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
20015 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
20016 if (compare_section_name (section
, ".sdata")
20017 || compare_section_name (section
, ".sdata2")
20018 || compare_section_name (section
, ".gnu.linkonce.s")
20019 || compare_section_name (section
, ".sbss")
20020 || compare_section_name (section
, ".sbss2")
20021 || compare_section_name (section
, ".gnu.linkonce.sb")
20022 || strcmp (section
, ".PPC.EMB.sdata0") == 0
20023 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
20028 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
20031 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
20032 /* If it's not public, and we're not going to reference it there,
20033 there's no need to put it in the small data section. */
20034 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
20041 #endif /* USING_ELFOS_H */
20043 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
20046 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
20048 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
20051 /* Return a REG that occurs in ADDR with coefficient 1.
20052 ADDR can be effectively incremented by incrementing REG.
20054 r0 is special and we must not select it as an address
20055 register by this routine since our caller will try to
20056 increment the returned register via an "la" instruction. */
20059 find_addr_reg (rtx addr
)
20061 while (GET_CODE (addr
) == PLUS
)
20063 if (GET_CODE (XEXP (addr
, 0)) == REG
20064 && REGNO (XEXP (addr
, 0)) != 0)
20065 addr
= XEXP (addr
, 0);
20066 else if (GET_CODE (XEXP (addr
, 1)) == REG
20067 && REGNO (XEXP (addr
, 1)) != 0)
20068 addr
= XEXP (addr
, 1);
20069 else if (CONSTANT_P (XEXP (addr
, 0)))
20070 addr
= XEXP (addr
, 1);
20071 else if (CONSTANT_P (XEXP (addr
, 1)))
20072 addr
= XEXP (addr
, 0);
20074 gcc_unreachable ();
20076 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
20081 rs6000_fatal_bad_address (rtx op
)
20083 fatal_insn ("bad address", op
);
20088 static tree branch_island_list
= 0;
20090 /* Remember to generate a branch island for far calls to the given
20094 add_compiler_branch_island (tree label_name
, tree function_name
,
20097 tree branch_island
= build_tree_list (function_name
, label_name
);
20098 TREE_TYPE (branch_island
) = build_int_cst (NULL_TREE
, line_number
);
20099 TREE_CHAIN (branch_island
) = branch_island_list
;
20100 branch_island_list
= branch_island
;
20103 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
20104 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
20105 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
20106 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
20108 /* Generate far-jump branch islands for everything on the
20109 branch_island_list. Invoked immediately after the last instruction
20110 of the epilogue has been emitted; the branch-islands must be
20111 appended to, and contiguous with, the function body. Mach-O stubs
20112 are generated in machopic_output_stub(). */
20115 macho_branch_islands (void)
20118 tree branch_island
;
20120 for (branch_island
= branch_island_list
;
20122 branch_island
= TREE_CHAIN (branch_island
))
20124 const char *label
=
20125 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island
));
20127 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island
));
20128 char name_buf
[512];
20129 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
20130 if (name
[0] == '*' || name
[0] == '&')
20131 strcpy (name_buf
, name
+1);
20135 strcpy (name_buf
+1, name
);
20137 strcpy (tmp_buf
, "\n");
20138 strcat (tmp_buf
, label
);
20139 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20140 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
20141 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
20142 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20145 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
20146 strcat (tmp_buf
, label
);
20147 strcat (tmp_buf
, "_pic\n");
20148 strcat (tmp_buf
, label
);
20149 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
20151 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
20152 strcat (tmp_buf
, name_buf
);
20153 strcat (tmp_buf
, " - ");
20154 strcat (tmp_buf
, label
);
20155 strcat (tmp_buf
, "_pic)\n");
20157 strcat (tmp_buf
, "\tmtlr r0\n");
20159 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
20160 strcat (tmp_buf
, name_buf
);
20161 strcat (tmp_buf
, " - ");
20162 strcat (tmp_buf
, label
);
20163 strcat (tmp_buf
, "_pic)\n");
20165 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
20169 strcat (tmp_buf
, ":\nlis r12,hi16(");
20170 strcat (tmp_buf
, name_buf
);
20171 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
20172 strcat (tmp_buf
, name_buf
);
20173 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
20175 output_asm_insn (tmp_buf
, 0);
20176 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
20177 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
20178 dbxout_stabd (N_SLINE
, BRANCH_ISLAND_LINE_NUMBER (branch_island
));
20179 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
20182 branch_island_list
= 0;
20185 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
20186 already there or not. */
20189 no_previous_def (tree function_name
)
20191 tree branch_island
;
20192 for (branch_island
= branch_island_list
;
20194 branch_island
= TREE_CHAIN (branch_island
))
20195 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
20200 /* GET_PREV_LABEL gets the label name from the previous definition of
20204 get_prev_label (tree function_name
)
20206 tree branch_island
;
20207 for (branch_island
= branch_island_list
;
20209 branch_island
= TREE_CHAIN (branch_island
))
20210 if (function_name
== BRANCH_ISLAND_FUNCTION_NAME (branch_island
))
20211 return BRANCH_ISLAND_LABEL_NAME (branch_island
);
20215 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
20216 #define DARWIN_LINKER_GENERATES_ISLANDS 0
20219 /* KEXTs still need branch islands. */
20220 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
20221 || flag_mkernel || flag_apple_kext)
20223 /* INSN is either a function call or a millicode call. It may have an
20224 unconditional jump in its delay slot.
20226 CALL_DEST is the routine we are calling. */
20229 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
20230 int cookie_operand_number
)
20232 static char buf
[256];
20233 if (DARWIN_GENERATE_ISLANDS
20234 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
20235 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
20238 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
20240 if (no_previous_def (funname
))
20242 rtx label_rtx
= gen_label_rtx ();
20243 char *label_buf
, temp_buf
[256];
20244 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
20245 CODE_LABEL_NUMBER (label_rtx
));
20246 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
20247 labelname
= get_identifier (label_buf
);
20248 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
20251 labelname
= get_prev_label (funname
);
20253 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
20254 instruction will reach 'foo', otherwise link as 'bl L42'".
20255 "L42" should be a 'branch island', that will do a far jump to
20256 'foo'. Branch islands are generated in
20257 macho_branch_islands(). */
20258 sprintf (buf
, "jbsr %%z%d,%.246s",
20259 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
20262 sprintf (buf
, "bl %%z%d", dest_operand_number
);
20266 /* Generate PIC and indirect symbol stubs. */
20269 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
20271 unsigned int length
;
20272 char *symbol_name
, *lazy_ptr_name
;
20273 char *local_label_0
;
20274 static int label
= 0;
20276 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
20277 symb
= (*targetm
.strip_name_encoding
) (symb
);
20280 length
= strlen (symb
);
20281 symbol_name
= alloca (length
+ 32);
20282 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
20284 lazy_ptr_name
= alloca (length
+ 32);
20285 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
20288 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
20290 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
20294 fprintf (file
, "\t.align 5\n");
20296 fprintf (file
, "%s:\n", stub
);
20297 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
20300 local_label_0
= alloca (sizeof ("\"L00000000000$spb\""));
20301 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
20303 fprintf (file
, "\tmflr r0\n");
20304 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
20305 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
20306 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
20307 lazy_ptr_name
, local_label_0
);
20308 fprintf (file
, "\tmtlr r0\n");
20309 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
20310 (TARGET_64BIT
? "ldu" : "lwzu"),
20311 lazy_ptr_name
, local_label_0
);
20312 fprintf (file
, "\tmtctr r12\n");
20313 fprintf (file
, "\tbctr\n");
20317 fprintf (file
, "\t.align 4\n");
20319 fprintf (file
, "%s:\n", stub
);
20320 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
20322 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
20323 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
20324 (TARGET_64BIT
? "ldu" : "lwzu"),
20326 fprintf (file
, "\tmtctr r12\n");
20327 fprintf (file
, "\tbctr\n");
20330 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
20331 fprintf (file
, "%s:\n", lazy_ptr_name
);
20332 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
20333 fprintf (file
, "%sdyld_stub_binding_helper\n",
20334 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
20337 /* Legitimize PIC addresses. If the address is already
20338 position-independent, we return ORIG. Newly generated
20339 position-independent addresses go into a reg. This is REG if non
20340 zero, otherwise we allocate register(s) as necessary. */
20342 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
20345 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
20350 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
20351 reg
= gen_reg_rtx (Pmode
);
20353 if (GET_CODE (orig
) == CONST
)
20357 if (GET_CODE (XEXP (orig
, 0)) == PLUS
20358 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
20361 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
20363 /* Use a different reg for the intermediate value, as
20364 it will be marked UNCHANGING. */
20365 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
20366 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
20369 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
20372 if (GET_CODE (offset
) == CONST_INT
)
20374 if (SMALL_INT (offset
))
20375 return plus_constant (base
, INTVAL (offset
));
20376 else if (! reload_in_progress
&& ! reload_completed
)
20377 offset
= force_reg (Pmode
, offset
);
20380 rtx mem
= force_const_mem (Pmode
, orig
);
20381 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
20384 return gen_rtx_PLUS (Pmode
, base
, offset
);
20387 /* Fall back on generic machopic code. */
20388 return machopic_legitimize_pic_address (orig
, mode
, reg
);
20391 /* Output a .machine directive for the Darwin assembler, and call
20392 the generic start_file routine. */
20395 rs6000_darwin_file_start (void)
20397 static const struct
20403 { "ppc64", "ppc64", MASK_64BIT
},
20404 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
20405 { "power4", "ppc970", 0 },
20406 { "G5", "ppc970", 0 },
20407 { "7450", "ppc7450", 0 },
20408 { "7400", "ppc7400", MASK_ALTIVEC
},
20409 { "G4", "ppc7400", 0 },
20410 { "750", "ppc750", 0 },
20411 { "740", "ppc750", 0 },
20412 { "G3", "ppc750", 0 },
20413 { "604e", "ppc604e", 0 },
20414 { "604", "ppc604", 0 },
20415 { "603e", "ppc603", 0 },
20416 { "603", "ppc603", 0 },
20417 { "601", "ppc601", 0 },
20418 { NULL
, "ppc", 0 } };
20419 const char *cpu_id
= "";
20422 rs6000_file_start ();
20423 darwin_file_start ();
20425 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
20426 for (i
= 0; i
< ARRAY_SIZE (rs6000_select
); i
++)
20427 if (rs6000_select
[i
].set_arch_p
&& rs6000_select
[i
].string
20428 && rs6000_select
[i
].string
[0] != '\0')
20429 cpu_id
= rs6000_select
[i
].string
;
20431 /* Look through the mapping array. Pick the first name that either
20432 matches the argument, has a bit set in IF_SET that is also set
20433 in the target flags, or has a NULL name. */
20436 while (mapping
[i
].arg
!= NULL
20437 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
20438 && (mapping
[i
].if_set
& target_flags
) == 0)
20441 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
20444 #endif /* TARGET_MACHO */
20448 rs6000_elf_reloc_rw_mask (void)
20452 else if (DEFAULT_ABI
== ABI_AIX
)
20458 /* Record an element in the table of global constructors. SYMBOL is
20459 a SYMBOL_REF of the function to be called; PRIORITY is a number
20460 between 0 and MAX_INIT_PRIORITY.
20462 This differs from default_named_section_asm_out_constructor in
20463 that we have special handling for -mrelocatable. */
20466 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
20468 const char *section
= ".ctors";
20471 if (priority
!= DEFAULT_INIT_PRIORITY
)
20473 sprintf (buf
, ".ctors.%.5u",
20474 /* Invert the numbering so the linker puts us in the proper
20475 order; constructors are run from right to left, and the
20476 linker sorts in increasing order. */
20477 MAX_INIT_PRIORITY
- priority
);
20481 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
20482 assemble_align (POINTER_SIZE
);
20484 if (TARGET_RELOCATABLE
)
20486 fputs ("\t.long (", asm_out_file
);
20487 output_addr_const (asm_out_file
, symbol
);
20488 fputs (")@fixup\n", asm_out_file
);
20491 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
20495 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
20497 const char *section
= ".dtors";
20500 if (priority
!= DEFAULT_INIT_PRIORITY
)
20502 sprintf (buf
, ".dtors.%.5u",
20503 /* Invert the numbering so the linker puts us in the proper
20504 order; constructors are run from right to left, and the
20505 linker sorts in increasing order. */
20506 MAX_INIT_PRIORITY
- priority
);
20510 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
20511 assemble_align (POINTER_SIZE
);
20513 if (TARGET_RELOCATABLE
)
20515 fputs ("\t.long (", asm_out_file
);
20516 output_addr_const (asm_out_file
, symbol
);
20517 fputs (")@fixup\n", asm_out_file
);
20520 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
20524 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
20528 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
20529 ASM_OUTPUT_LABEL (file
, name
);
20530 fputs (DOUBLE_INT_ASM_OP
, file
);
20531 rs6000_output_function_entry (file
, name
);
20532 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
20535 fputs ("\t.size\t", file
);
20536 assemble_name (file
, name
);
20537 fputs (",24\n\t.type\t.", file
);
20538 assemble_name (file
, name
);
20539 fputs (",@function\n", file
);
20540 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
20542 fputs ("\t.globl\t.", file
);
20543 assemble_name (file
, name
);
20548 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
20549 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
20550 rs6000_output_function_entry (file
, name
);
20551 fputs (":\n", file
);
20555 if (TARGET_RELOCATABLE
20556 && !TARGET_SECURE_PLT
20557 && (get_pool_size () != 0 || current_function_profile
)
20562 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
20564 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
20565 fprintf (file
, "\t.long ");
20566 assemble_name (file
, buf
);
20568 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
20569 assemble_name (file
, buf
);
20573 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
20574 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
20576 if (DEFAULT_ABI
== ABI_AIX
)
20578 const char *desc_name
, *orig_name
;
20580 orig_name
= (*targetm
.strip_name_encoding
) (name
);
20581 desc_name
= orig_name
;
20582 while (*desc_name
== '.')
20585 if (TREE_PUBLIC (decl
))
20586 fprintf (file
, "\t.globl %s\n", desc_name
);
20588 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
20589 fprintf (file
, "%s:\n", desc_name
);
20590 fprintf (file
, "\t.long %s\n", orig_name
);
20591 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
20592 if (DEFAULT_ABI
== ABI_AIX
)
20593 fputs ("\t.long 0\n", file
);
20594 fprintf (file
, "\t.previous\n");
20596 ASM_OUTPUT_LABEL (file
, name
);
20600 rs6000_elf_end_indicate_exec_stack (void)
20603 file_end_indicate_exec_stack ();
20609 rs6000_xcoff_asm_output_anchor (rtx symbol
)
20613 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
20614 SYMBOL_REF_BLOCK_OFFSET (symbol
));
20615 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
20619 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
20621 fputs (GLOBAL_ASM_OP
, stream
);
20622 RS6000_OUTPUT_BASENAME (stream
, name
);
20623 putc ('\n', stream
);
20626 /* A get_unnamed_decl callback, used for read-only sections. PTR
20627 points to the section string variable. */
20630 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
20632 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
20633 *(const char *const *) directive
,
20634 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
20637 /* Likewise for read-write sections. */
20640 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
20642 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
20643 *(const char *const *) directive
,
20644 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
20647 /* A get_unnamed_section callback, used for switching to toc_section. */
20650 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
20652 if (TARGET_MINIMAL_TOC
)
20654 /* toc_section is always selected at least once from
20655 rs6000_xcoff_file_start, so this is guaranteed to
20656 always be defined once and only once in each file. */
20657 if (!toc_initialized
)
20659 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
20660 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
20661 toc_initialized
= 1;
20663 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
20664 (TARGET_32BIT
? "" : ",3"));
20667 fputs ("\t.toc\n", asm_out_file
);
20670 /* Implement TARGET_ASM_INIT_SECTIONS. */
20673 rs6000_xcoff_asm_init_sections (void)
20675 read_only_data_section
20676 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
20677 &xcoff_read_only_section_name
);
20679 private_data_section
20680 = get_unnamed_section (SECTION_WRITE
,
20681 rs6000_xcoff_output_readwrite_section_asm_op
,
20682 &xcoff_private_data_section_name
);
20684 read_only_private_data_section
20685 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
20686 &xcoff_private_data_section_name
);
20689 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
20691 readonly_data_section
= read_only_data_section
;
20692 exception_section
= data_section
;
20696 rs6000_xcoff_reloc_rw_mask (void)
20702 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
20703 tree decl ATTRIBUTE_UNUSED
)
20706 static const char * const suffix
[3] = { "PR", "RO", "RW" };
20708 if (flags
& SECTION_CODE
)
20710 else if (flags
& SECTION_WRITE
)
20715 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
20716 (flags
& SECTION_CODE
) ? "." : "",
20717 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
20721 rs6000_xcoff_select_section (tree decl
, int reloc
,
20722 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
20724 if (decl_readonly_section (decl
, reloc
))
20726 if (TREE_PUBLIC (decl
))
20727 return read_only_data_section
;
20729 return read_only_private_data_section
;
20733 if (TREE_PUBLIC (decl
))
20734 return data_section
;
20736 return private_data_section
;
20741 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
20745 /* Use select_section for private and uninitialized data. */
20746 if (!TREE_PUBLIC (decl
)
20747 || DECL_COMMON (decl
)
20748 || DECL_INITIAL (decl
) == NULL_TREE
20749 || DECL_INITIAL (decl
) == error_mark_node
20750 || (flag_zero_initialized_in_bss
20751 && initializer_zerop (DECL_INITIAL (decl
))))
20754 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
20755 name
= (*targetm
.strip_name_encoding
) (name
);
20756 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
20759 /* Select section for constant in constant pool.
20761 On RS/6000, all constants are in the private read-only data area.
20762 However, if this is being placed in the TOC it must be output as a
20766 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
20767 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
20769 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
20770 return toc_section
;
20772 return read_only_private_data_section
;
20775 /* Remove any trailing [DS] or the like from the symbol name. */
20777 static const char *
20778 rs6000_xcoff_strip_name_encoding (const char *name
)
20783 len
= strlen (name
);
20784 if (name
[len
- 1] == ']')
20785 return ggc_alloc_string (name
, len
- 4);
20790 /* Section attributes. AIX is always PIC. */
20792 static unsigned int
20793 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
20795 unsigned int align
;
20796 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
20798 /* Align to at least UNIT size. */
20799 if (flags
& SECTION_CODE
)
20800 align
= MIN_UNITS_PER_WORD
;
20802 /* Increase alignment of large objects if not already stricter. */
20803 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
20804 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
20805 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
20807 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
20810 /* Output at beginning of assembler file.
20812 Initialize the section names for the RS/6000 at this point.
20814 Specify filename, including full path, to assembler.
20816 We want to go into the TOC section so at least one .toc will be emitted.
20817 Also, in order to output proper .bs/.es pairs, we need at least one static
20818 [RW] section emitted.
20820 Finally, declare mcount when profiling to make the assembler happy. */
20823 rs6000_xcoff_file_start (void)
20825 rs6000_gen_section_name (&xcoff_bss_section_name
,
20826 main_input_filename
, ".bss_");
20827 rs6000_gen_section_name (&xcoff_private_data_section_name
,
20828 main_input_filename
, ".rw_");
20829 rs6000_gen_section_name (&xcoff_read_only_section_name
,
20830 main_input_filename
, ".ro_");
20832 fputs ("\t.file\t", asm_out_file
);
20833 output_quoted_string (asm_out_file
, main_input_filename
);
20834 fputc ('\n', asm_out_file
);
20835 if (write_symbols
!= NO_DEBUG
)
20836 switch_to_section (private_data_section
);
20837 switch_to_section (text_section
);
20839 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
20840 rs6000_file_start ();
20843 /* Output at end of assembler file.
20844 On the RS/6000, referencing data should automatically pull in text. */
20847 rs6000_xcoff_file_end (void)
20849 switch_to_section (text_section
);
20850 fputs ("_section_.text:\n", asm_out_file
);
20851 switch_to_section (data_section
);
20852 fputs (TARGET_32BIT
20853 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
20856 #endif /* TARGET_XCOFF */
20858 /* Compute a (partial) cost for rtx X. Return true if the complete
20859 cost has been computed, and false if subexpressions should be
20860 scanned. In either case, *TOTAL contains the cost result. */
20863 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
20865 enum machine_mode mode
= GET_MODE (x
);
20869 /* On the RS/6000, if it is valid in the insn, it is free. */
20871 if (((outer_code
== SET
20872 || outer_code
== PLUS
20873 || outer_code
== MINUS
)
20874 && (satisfies_constraint_I (x
)
20875 || satisfies_constraint_L (x
)))
20876 || (outer_code
== AND
20877 && (satisfies_constraint_K (x
)
20879 ? satisfies_constraint_L (x
)
20880 : satisfies_constraint_J (x
))
20881 || mask_operand (x
, mode
)
20883 && mask64_operand (x
, DImode
))))
20884 || ((outer_code
== IOR
|| outer_code
== XOR
)
20885 && (satisfies_constraint_K (x
)
20887 ? satisfies_constraint_L (x
)
20888 : satisfies_constraint_J (x
))))
20889 || outer_code
== ASHIFT
20890 || outer_code
== ASHIFTRT
20891 || outer_code
== LSHIFTRT
20892 || outer_code
== ROTATE
20893 || outer_code
== ROTATERT
20894 || outer_code
== ZERO_EXTRACT
20895 || (outer_code
== MULT
20896 && satisfies_constraint_I (x
))
20897 || ((outer_code
== DIV
|| outer_code
== UDIV
20898 || outer_code
== MOD
|| outer_code
== UMOD
)
20899 && exact_log2 (INTVAL (x
)) >= 0)
20900 || (outer_code
== COMPARE
20901 && (satisfies_constraint_I (x
)
20902 || satisfies_constraint_K (x
)))
20903 || (outer_code
== EQ
20904 && (satisfies_constraint_I (x
)
20905 || satisfies_constraint_K (x
)
20907 ? satisfies_constraint_L (x
)
20908 : satisfies_constraint_J (x
))))
20909 || (outer_code
== GTU
20910 && satisfies_constraint_I (x
))
20911 || (outer_code
== LTU
20912 && satisfies_constraint_P (x
)))
20917 else if ((outer_code
== PLUS
20918 && reg_or_add_cint_operand (x
, VOIDmode
))
20919 || (outer_code
== MINUS
20920 && reg_or_sub_cint_operand (x
, VOIDmode
))
20921 || ((outer_code
== SET
20922 || outer_code
== IOR
20923 || outer_code
== XOR
)
20925 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
20927 *total
= COSTS_N_INSNS (1);
20933 if (mode
== DImode
&& code
== CONST_DOUBLE
)
20935 if ((outer_code
== IOR
|| outer_code
== XOR
)
20936 && CONST_DOUBLE_HIGH (x
) == 0
20937 && (CONST_DOUBLE_LOW (x
)
20938 & ~ (unsigned HOST_WIDE_INT
) 0xffff) == 0)
20943 else if ((outer_code
== AND
&& and64_2_operand (x
, DImode
))
20944 || ((outer_code
== SET
20945 || outer_code
== IOR
20946 || outer_code
== XOR
)
20947 && CONST_DOUBLE_HIGH (x
) == 0))
20949 *total
= COSTS_N_INSNS (1);
20959 /* When optimizing for size, MEM should be slightly more expensive
20960 than generating address, e.g., (plus (reg) (const)).
20961 L1 cache latency is about two instructions. */
20962 *total
= optimize_size
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20970 if (mode
== DFmode
)
20972 if (GET_CODE (XEXP (x
, 0)) == MULT
)
20974 /* FNMA accounted in outer NEG. */
20975 if (outer_code
== NEG
)
20976 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
20978 *total
= rs6000_cost
->dmul
;
20981 *total
= rs6000_cost
->fp
;
20983 else if (mode
== SFmode
)
20985 /* FNMA accounted in outer NEG. */
20986 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
20989 *total
= rs6000_cost
->fp
;
20992 *total
= COSTS_N_INSNS (1);
20996 if (mode
== DFmode
)
20998 if (GET_CODE (XEXP (x
, 0)) == MULT
20999 || GET_CODE (XEXP (x
, 1)) == MULT
)
21001 /* FNMA accounted in outer NEG. */
21002 if (outer_code
== NEG
)
21003 *total
= rs6000_cost
->dmul
- rs6000_cost
->fp
;
21005 *total
= rs6000_cost
->dmul
;
21008 *total
= rs6000_cost
->fp
;
21010 else if (mode
== SFmode
)
21012 /* FNMA accounted in outer NEG. */
21013 if (outer_code
== NEG
&& GET_CODE (XEXP (x
, 0)) == MULT
)
21016 *total
= rs6000_cost
->fp
;
21019 *total
= COSTS_N_INSNS (1);
21023 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
21024 && satisfies_constraint_I (XEXP (x
, 1)))
21026 if (INTVAL (XEXP (x
, 1)) >= -256
21027 && INTVAL (XEXP (x
, 1)) <= 255)
21028 *total
= rs6000_cost
->mulsi_const9
;
21030 *total
= rs6000_cost
->mulsi_const
;
21032 /* FMA accounted in outer PLUS/MINUS. */
21033 else if ((mode
== DFmode
|| mode
== SFmode
)
21034 && (outer_code
== PLUS
|| outer_code
== MINUS
))
21036 else if (mode
== DFmode
)
21037 *total
= rs6000_cost
->dmul
;
21038 else if (mode
== SFmode
)
21039 *total
= rs6000_cost
->fp
;
21040 else if (mode
== DImode
)
21041 *total
= rs6000_cost
->muldi
;
21043 *total
= rs6000_cost
->mulsi
;
21048 if (FLOAT_MODE_P (mode
))
21050 *total
= mode
== DFmode
? rs6000_cost
->ddiv
21051 : rs6000_cost
->sdiv
;
21058 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
21059 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
21061 if (code
== DIV
|| code
== MOD
)
21063 *total
= COSTS_N_INSNS (2);
21066 *total
= COSTS_N_INSNS (1);
21070 if (GET_MODE (XEXP (x
, 1)) == DImode
)
21071 *total
= rs6000_cost
->divdi
;
21073 *total
= rs6000_cost
->divsi
;
21075 /* Add in shift and subtract for MOD. */
21076 if (code
== MOD
|| code
== UMOD
)
21077 *total
+= COSTS_N_INSNS (2);
21082 *total
= COSTS_N_INSNS (4);
21086 *total
= COSTS_N_INSNS (6);
21090 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
21102 *total
= COSTS_N_INSNS (1);
21110 /* Handle mul_highpart. */
21111 if (outer_code
== TRUNCATE
21112 && GET_CODE (XEXP (x
, 0)) == MULT
)
21114 if (mode
== DImode
)
21115 *total
= rs6000_cost
->muldi
;
21117 *total
= rs6000_cost
->mulsi
;
21120 else if (outer_code
== AND
)
21123 *total
= COSTS_N_INSNS (1);
21128 if (GET_CODE (XEXP (x
, 0)) == MEM
)
21131 *total
= COSTS_N_INSNS (1);
21137 if (!FLOAT_MODE_P (mode
))
21139 *total
= COSTS_N_INSNS (1);
21145 case UNSIGNED_FLOAT
:
21148 case FLOAT_TRUNCATE
:
21149 *total
= rs6000_cost
->fp
;
21153 if (mode
== DFmode
)
21156 *total
= rs6000_cost
->fp
;
21160 switch (XINT (x
, 1))
21163 *total
= rs6000_cost
->fp
;
21175 *total
= COSTS_N_INSNS (1);
21178 else if (FLOAT_MODE_P (mode
)
21179 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21181 *total
= rs6000_cost
->fp
;
21189 /* Carry bit requires mode == Pmode.
21190 NEG or PLUS already counted so only add one. */
21192 && (outer_code
== NEG
|| outer_code
== PLUS
))
21194 *total
= COSTS_N_INSNS (1);
21197 if (outer_code
== SET
)
21199 if (XEXP (x
, 1) == const0_rtx
)
21201 *total
= COSTS_N_INSNS (2);
21204 else if (mode
== Pmode
)
21206 *total
= COSTS_N_INSNS (3);
21215 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
21217 *total
= COSTS_N_INSNS (2);
21221 if (outer_code
== COMPARE
)
21235 /* A C expression returning the cost of moving data from a register of class
21236 CLASS1 to one of CLASS2. */
21239 rs6000_register_move_cost (enum machine_mode mode
,
21240 enum reg_class from
, enum reg_class to
)
21242 /* Moves from/to GENERAL_REGS. */
21243 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
21244 || reg_classes_intersect_p (from
, GENERAL_REGS
))
21246 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
21249 if (from
== FLOAT_REGS
|| from
== ALTIVEC_REGS
)
21250 return (rs6000_memory_move_cost (mode
, from
, 0)
21251 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, 0));
21253 /* It's more expensive to move CR_REGS than CR0_REGS because of the
21255 else if (from
== CR_REGS
)
21259 /* A move will cost one instruction per GPR moved. */
21260 return 2 * hard_regno_nregs
[0][mode
];
21263 /* Moving between two similar registers is just one instruction. */
21264 else if (reg_classes_intersect_p (to
, from
))
21265 return (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
21267 /* Everything else has to go through GENERAL_REGS. */
21269 return (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
21270 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
21273 /* A C expressions returning the cost of moving data of MODE from a register to
21277 rs6000_memory_move_cost (enum machine_mode mode
, enum reg_class
class,
21278 int in ATTRIBUTE_UNUSED
)
21280 if (reg_classes_intersect_p (class, GENERAL_REGS
))
21281 return 4 * hard_regno_nregs
[0][mode
];
21282 else if (reg_classes_intersect_p (class, FLOAT_REGS
))
21283 return 4 * hard_regno_nregs
[32][mode
];
21284 else if (reg_classes_intersect_p (class, ALTIVEC_REGS
))
21285 return 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
21287 return 4 + rs6000_register_move_cost (mode
, class, GENERAL_REGS
);
21290 /* Returns a code for a target-specific builtin that implements
21291 reciprocal of the function, or NULL_TREE if not available. */
21294 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
21295 bool sqrt ATTRIBUTE_UNUSED
)
21297 if (! (TARGET_RECIP
&& TARGET_PPC_GFXOPT
&& !optimize_size
21298 && flag_finite_math_only
&& !flag_trapping_math
21299 && flag_unsafe_math_optimizations
))
21307 case BUILT_IN_SQRTF
:
21308 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
21315 /* Newton-Raphson approximation of single-precision floating point divide n/d.
21316 Assumes no trapping math and finite arguments. */
21319 rs6000_emit_swdivsf (rtx dst
, rtx n
, rtx d
)
21321 rtx x0
, e0
, e1
, y1
, u0
, v0
, one
;
21323 x0
= gen_reg_rtx (SFmode
);
21324 e0
= gen_reg_rtx (SFmode
);
21325 e1
= gen_reg_rtx (SFmode
);
21326 y1
= gen_reg_rtx (SFmode
);
21327 u0
= gen_reg_rtx (SFmode
);
21328 v0
= gen_reg_rtx (SFmode
);
21329 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
21331 /* x0 = 1./d estimate */
21332 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21333 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, d
),
21335 /* e0 = 1. - d * x0 */
21336 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
21337 gen_rtx_MINUS (SFmode
, one
,
21338 gen_rtx_MULT (SFmode
, d
, x0
))));
21339 /* e1 = e0 + e0 * e0 */
21340 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
21341 gen_rtx_PLUS (SFmode
,
21342 gen_rtx_MULT (SFmode
, e0
, e0
), e0
)));
21343 /* y1 = x0 + e1 * x0 */
21344 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
21345 gen_rtx_PLUS (SFmode
,
21346 gen_rtx_MULT (SFmode
, e1
, x0
), x0
)));
21348 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
21349 gen_rtx_MULT (SFmode
, n
, y1
)));
21350 /* v0 = n - d * u0 */
21351 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
21352 gen_rtx_MINUS (SFmode
, n
,
21353 gen_rtx_MULT (SFmode
, d
, u0
))));
21354 /* dst = u0 + v0 * y1 */
21355 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
21356 gen_rtx_PLUS (SFmode
,
21357 gen_rtx_MULT (SFmode
, v0
, y1
), u0
)));
21360 /* Newton-Raphson approximation of double-precision floating point divide n/d.
21361 Assumes no trapping math and finite arguments. */
21364 rs6000_emit_swdivdf (rtx dst
, rtx n
, rtx d
)
21366 rtx x0
, e0
, e1
, e2
, y1
, y2
, y3
, u0
, v0
, one
;
21368 x0
= gen_reg_rtx (DFmode
);
21369 e0
= gen_reg_rtx (DFmode
);
21370 e1
= gen_reg_rtx (DFmode
);
21371 e2
= gen_reg_rtx (DFmode
);
21372 y1
= gen_reg_rtx (DFmode
);
21373 y2
= gen_reg_rtx (DFmode
);
21374 y3
= gen_reg_rtx (DFmode
);
21375 u0
= gen_reg_rtx (DFmode
);
21376 v0
= gen_reg_rtx (DFmode
);
21377 one
= force_reg (DFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, DFmode
));
21379 /* x0 = 1./d estimate */
21380 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21381 gen_rtx_UNSPEC (DFmode
, gen_rtvec (1, d
),
21383 /* e0 = 1. - d * x0 */
21384 emit_insn (gen_rtx_SET (VOIDmode
, e0
,
21385 gen_rtx_MINUS (DFmode
, one
,
21386 gen_rtx_MULT (SFmode
, d
, x0
))));
21387 /* y1 = x0 + e0 * x0 */
21388 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
21389 gen_rtx_PLUS (DFmode
,
21390 gen_rtx_MULT (DFmode
, e0
, x0
), x0
)));
21392 emit_insn (gen_rtx_SET (VOIDmode
, e1
,
21393 gen_rtx_MULT (DFmode
, e0
, e0
)));
21394 /* y2 = y1 + e1 * y1 */
21395 emit_insn (gen_rtx_SET (VOIDmode
, y2
,
21396 gen_rtx_PLUS (DFmode
,
21397 gen_rtx_MULT (DFmode
, e1
, y1
), y1
)));
21399 emit_insn (gen_rtx_SET (VOIDmode
, e2
,
21400 gen_rtx_MULT (DFmode
, e1
, e1
)));
21401 /* y3 = y2 + e2 * y2 */
21402 emit_insn (gen_rtx_SET (VOIDmode
, y3
,
21403 gen_rtx_PLUS (DFmode
,
21404 gen_rtx_MULT (DFmode
, e2
, y2
), y2
)));
21406 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
21407 gen_rtx_MULT (DFmode
, n
, y3
)));
21408 /* v0 = n - d * u0 */
21409 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
21410 gen_rtx_MINUS (DFmode
, n
,
21411 gen_rtx_MULT (DFmode
, d
, u0
))));
21412 /* dst = u0 + v0 * y3 */
21413 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
21414 gen_rtx_PLUS (DFmode
,
21415 gen_rtx_MULT (DFmode
, v0
, y3
), u0
)));
21419 /* Newton-Raphson approximation of single-precision floating point rsqrt.
21420 Assumes no trapping math and finite arguments. */
21423 rs6000_emit_swrsqrtsf (rtx dst
, rtx src
)
21425 rtx x0
, x1
, x2
, y1
, u0
, u1
, u2
, v0
, v1
, v2
, t0
,
21426 half
, one
, halfthree
, c1
, cond
, label
;
21428 x0
= gen_reg_rtx (SFmode
);
21429 x1
= gen_reg_rtx (SFmode
);
21430 x2
= gen_reg_rtx (SFmode
);
21431 y1
= gen_reg_rtx (SFmode
);
21432 u0
= gen_reg_rtx (SFmode
);
21433 u1
= gen_reg_rtx (SFmode
);
21434 u2
= gen_reg_rtx (SFmode
);
21435 v0
= gen_reg_rtx (SFmode
);
21436 v1
= gen_reg_rtx (SFmode
);
21437 v2
= gen_reg_rtx (SFmode
);
21438 t0
= gen_reg_rtx (SFmode
);
21439 halfthree
= gen_reg_rtx (SFmode
);
21440 cond
= gen_rtx_REG (CCFPmode
, CR1_REGNO
);
21441 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
21443 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
21444 emit_insn (gen_rtx_SET (VOIDmode
, t0
,
21445 gen_rtx_MULT (SFmode
, src
, src
)));
21447 emit_insn (gen_rtx_SET (VOIDmode
, cond
,
21448 gen_rtx_COMPARE (CCFPmode
, t0
, src
)));
21449 c1
= gen_rtx_EQ (VOIDmode
, cond
, const0_rtx
);
21450 emit_unlikely_jump (c1
, label
);
21452 half
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf
, SFmode
));
21453 one
= force_reg (SFmode
, CONST_DOUBLE_FROM_REAL_VALUE (dconst1
, SFmode
));
21455 /* halfthree = 1.5 = 1.0 + 0.5 */
21456 emit_insn (gen_rtx_SET (VOIDmode
, halfthree
,
21457 gen_rtx_PLUS (SFmode
, one
, half
)));
21459 /* x0 = rsqrt estimate */
21460 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
21461 gen_rtx_UNSPEC (SFmode
, gen_rtvec (1, src
),
21464 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
21465 emit_insn (gen_rtx_SET (VOIDmode
, y1
,
21466 gen_rtx_MINUS (SFmode
,
21467 gen_rtx_MULT (SFmode
, src
, halfthree
),
21470 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
21471 emit_insn (gen_rtx_SET (VOIDmode
, u0
,
21472 gen_rtx_MULT (SFmode
, x0
, x0
)));
21473 emit_insn (gen_rtx_SET (VOIDmode
, v0
,
21474 gen_rtx_MINUS (SFmode
,
21476 gen_rtx_MULT (SFmode
, y1
, u0
))));
21477 emit_insn (gen_rtx_SET (VOIDmode
, x1
,
21478 gen_rtx_MULT (SFmode
, x0
, v0
)));
21480 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
21481 emit_insn (gen_rtx_SET (VOIDmode
, u1
,
21482 gen_rtx_MULT (SFmode
, x1
, x1
)));
21483 emit_insn (gen_rtx_SET (VOIDmode
, v1
,
21484 gen_rtx_MINUS (SFmode
,
21486 gen_rtx_MULT (SFmode
, y1
, u1
))));
21487 emit_insn (gen_rtx_SET (VOIDmode
, x2
,
21488 gen_rtx_MULT (SFmode
, x1
, v1
)));
21490 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
21491 emit_insn (gen_rtx_SET (VOIDmode
, u2
,
21492 gen_rtx_MULT (SFmode
, x2
, x2
)));
21493 emit_insn (gen_rtx_SET (VOIDmode
, v2
,
21494 gen_rtx_MINUS (SFmode
,
21496 gen_rtx_MULT (SFmode
, y1
, u2
))));
21497 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
21498 gen_rtx_MULT (SFmode
, x2
, v2
)));
21500 emit_label (XEXP (label
, 0));
21503 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
21504 target, and SRC is the argument operand. */
21507 rs6000_emit_popcount (rtx dst
, rtx src
)
21509 enum machine_mode mode
= GET_MODE (dst
);
21512 tmp1
= gen_reg_rtx (mode
);
21514 if (mode
== SImode
)
21516 emit_insn (gen_popcntbsi2 (tmp1
, src
));
21517 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
21519 tmp2
= force_reg (SImode
, tmp2
);
21520 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
21524 emit_insn (gen_popcntbdi2 (tmp1
, src
));
21525 tmp2
= expand_mult (DImode
, tmp1
,
21526 GEN_INT ((HOST_WIDE_INT
)
21527 0x01010101 << 32 | 0x01010101),
21529 tmp2
= force_reg (DImode
, tmp2
);
21530 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
21535 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
21536 target, and SRC is the argument operand. */
21539 rs6000_emit_parity (rtx dst
, rtx src
)
21541 enum machine_mode mode
= GET_MODE (dst
);
21544 tmp
= gen_reg_rtx (mode
);
21545 if (mode
== SImode
)
21547 /* Is mult+shift >= shift+xor+shift+xor? */
21548 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
21550 rtx tmp1
, tmp2
, tmp3
, tmp4
;
21552 tmp1
= gen_reg_rtx (SImode
);
21553 emit_insn (gen_popcntbsi2 (tmp1
, src
));
21555 tmp2
= gen_reg_rtx (SImode
);
21556 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
21557 tmp3
= gen_reg_rtx (SImode
);
21558 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
21560 tmp4
= gen_reg_rtx (SImode
);
21561 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
21562 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
21565 rs6000_emit_popcount (tmp
, src
);
21566 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
21570 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
21571 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
21573 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
21575 tmp1
= gen_reg_rtx (DImode
);
21576 emit_insn (gen_popcntbdi2 (tmp1
, src
));
21578 tmp2
= gen_reg_rtx (DImode
);
21579 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
21580 tmp3
= gen_reg_rtx (DImode
);
21581 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
21583 tmp4
= gen_reg_rtx (DImode
);
21584 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
21585 tmp5
= gen_reg_rtx (DImode
);
21586 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
21588 tmp6
= gen_reg_rtx (DImode
);
21589 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
21590 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
21593 rs6000_emit_popcount (tmp
, src
);
21594 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
21598 /* Return an RTX representing where to find the function value of a
21599 function returning MODE. */
21601 rs6000_complex_function_value (enum machine_mode mode
)
21603 unsigned int regno
;
21605 enum machine_mode inner
= GET_MODE_INNER (mode
);
21606 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
21608 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21609 regno
= FP_ARG_RETURN
;
21612 regno
= GP_ARG_RETURN
;
21614 /* 32-bit is OK since it'll go in r3/r4. */
21615 if (TARGET_32BIT
&& inner_bytes
>= 4)
21616 return gen_rtx_REG (mode
, regno
);
21619 if (inner_bytes
>= 8)
21620 return gen_rtx_REG (mode
, regno
);
21622 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
21624 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
21625 GEN_INT (inner_bytes
));
21626 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
21629 /* Define how to find the value returned by a function.
21630 VALTYPE is the data type of the value (as a tree).
21631 If the precise function being called is known, FUNC is its FUNCTION_DECL;
21632 otherwise, FUNC is 0.
21634 On the SPE, both FPs and vectors are returned in r3.
21636 On RS/6000 an integer value is in r3 and a floating-point value is in
21637 fp1, unless -msoft-float. */
21640 rs6000_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
21642 enum machine_mode mode
;
21643 unsigned int regno
;
21645 /* Special handling for structs in darwin64. */
21646 if (rs6000_darwin64_abi
21647 && TYPE_MODE (valtype
) == BLKmode
21648 && TREE_CODE (valtype
) == RECORD_TYPE
21649 && int_size_in_bytes (valtype
) > 0)
21651 CUMULATIVE_ARGS valcum
;
21655 valcum
.fregno
= FP_ARG_MIN_REG
;
21656 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
21657 /* Do a trial code generation as if this were going to be passed as
21658 an argument; if any part goes in memory, we return NULL. */
21659 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, 1, true);
21662 /* Otherwise fall through to standard ABI rules. */
21665 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
21667 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21668 return gen_rtx_PARALLEL (DImode
,
21670 gen_rtx_EXPR_LIST (VOIDmode
,
21671 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
21673 gen_rtx_EXPR_LIST (VOIDmode
,
21674 gen_rtx_REG (SImode
,
21675 GP_ARG_RETURN
+ 1),
21678 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
21680 return gen_rtx_PARALLEL (DCmode
,
21682 gen_rtx_EXPR_LIST (VOIDmode
,
21683 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
21685 gen_rtx_EXPR_LIST (VOIDmode
,
21686 gen_rtx_REG (SImode
,
21687 GP_ARG_RETURN
+ 1),
21689 gen_rtx_EXPR_LIST (VOIDmode
,
21690 gen_rtx_REG (SImode
,
21691 GP_ARG_RETURN
+ 2),
21693 gen_rtx_EXPR_LIST (VOIDmode
,
21694 gen_rtx_REG (SImode
,
21695 GP_ARG_RETURN
+ 3),
21699 mode
= TYPE_MODE (valtype
);
21700 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
21701 || POINTER_TYPE_P (valtype
))
21702 mode
= TARGET_32BIT
? SImode
: DImode
;
21704 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21705 /* _Decimal128 must use an even/odd register pair. */
21706 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
21707 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21708 regno
= FP_ARG_RETURN
;
21709 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
21710 && targetm
.calls
.split_complex_arg
)
21711 return rs6000_complex_function_value (mode
);
21712 else if (TREE_CODE (valtype
) == VECTOR_TYPE
21713 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
21714 && ALTIVEC_VECTOR_MODE (mode
))
21715 regno
= ALTIVEC_ARG_RETURN
;
21716 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
21717 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DCmode
21718 || mode
== TFmode
|| mode
== TDmode
|| mode
== TCmode
))
21719 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
21721 regno
= GP_ARG_RETURN
;
21723 return gen_rtx_REG (mode
, regno
);
21726 /* Define how to find the value returned by a library function
21727 assuming the value has mode MODE. */
21729 rs6000_libcall_value (enum machine_mode mode
)
21731 unsigned int regno
;
21733 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
21735 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21736 return gen_rtx_PARALLEL (DImode
,
21738 gen_rtx_EXPR_LIST (VOIDmode
,
21739 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
21741 gen_rtx_EXPR_LIST (VOIDmode
,
21742 gen_rtx_REG (SImode
,
21743 GP_ARG_RETURN
+ 1),
21747 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21748 /* _Decimal128 must use an even/odd register pair. */
21749 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
21750 else if (SCALAR_FLOAT_MODE_P (mode
)
21751 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
21752 regno
= FP_ARG_RETURN
;
21753 else if (ALTIVEC_VECTOR_MODE (mode
)
21754 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
21755 regno
= ALTIVEC_ARG_RETURN
;
21756 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
21757 return rs6000_complex_function_value (mode
);
21758 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
21759 && (mode
== DFmode
|| mode
== DDmode
|| mode
== DCmode
21760 || mode
== TFmode
|| mode
== TDmode
|| mode
== TCmode
))
21761 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
21763 regno
= GP_ARG_RETURN
;
21765 return gen_rtx_REG (mode
, regno
);
21768 /* Define the offset between two registers, FROM to be eliminated and its
21769 replacement TO, at the start of a routine. */
21771 rs6000_initial_elimination_offset (int from
, int to
)
21773 rs6000_stack_t
*info
= rs6000_stack_info ();
21774 HOST_WIDE_INT offset
;
21776 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
21777 offset
= info
->push_p
? 0 : -info
->total_size
;
21778 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
21780 offset
= info
->push_p
? 0 : -info
->total_size
;
21781 if (FRAME_GROWS_DOWNWARD
)
21782 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
21784 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
21785 offset
= FRAME_GROWS_DOWNWARD
21786 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
21788 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
21789 offset
= info
->total_size
;
21790 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
21791 offset
= info
->push_p
? info
->total_size
: 0;
21792 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
21795 gcc_unreachable ();
21800 /* Return true if TYPE is a SPE or AltiVec opaque type. */
21803 rs6000_is_opaque_type (const_tree type
)
21805 return (type
== opaque_V2SI_type_node
21806 || type
== opaque_V2SF_type_node
21807 || type
== opaque_p_V2SI_type_node
21808 || type
== opaque_V4SI_type_node
);
21812 rs6000_dwarf_register_span (rtx reg
)
21817 && (SPE_VECTOR_MODE (GET_MODE (reg
))
21818 || (TARGET_E500_DOUBLE
21819 && (GET_MODE (reg
) == DFmode
|| GET_MODE (reg
) == DDmode
))))
21824 regno
= REGNO (reg
);
21826 /* The duality of the SPE register size wreaks all kinds of havoc.
21827 This is a way of distinguishing r0 in 32-bits from r0 in
21830 gen_rtx_PARALLEL (VOIDmode
,
21833 gen_rtx_REG (SImode
, regno
+ 1200),
21834 gen_rtx_REG (SImode
, regno
))
21836 gen_rtx_REG (SImode
, regno
),
21837 gen_rtx_REG (SImode
, regno
+ 1200)));
21840 /* Fill in sizes for SPE register high parts in table used by unwinder. */
21843 rs6000_init_dwarf_reg_sizes_extra (tree address
)
21848 enum machine_mode mode
= TYPE_MODE (char_type_node
);
21849 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, 0);
21850 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
21851 rtx value
= gen_int_mode (4, mode
);
21853 for (i
= 1201; i
< 1232; i
++)
21855 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
21856 HOST_WIDE_INT offset
21857 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
21859 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
21864 /* Map internal gcc register numbers to DWARF2 register numbers. */
21867 rs6000_dbx_register_number (unsigned int regno
)
21869 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
21871 if (regno
== MQ_REGNO
)
21873 if (regno
== LR_REGNO
)
21875 if (regno
== CTR_REGNO
)
21877 if (CR_REGNO_P (regno
))
21878 return regno
- CR0_REGNO
+ 86;
21879 if (regno
== XER_REGNO
)
21881 if (ALTIVEC_REGNO_P (regno
))
21882 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
21883 if (regno
== VRSAVE_REGNO
)
21885 if (regno
== VSCR_REGNO
)
21887 if (regno
== SPE_ACC_REGNO
)
21889 if (regno
== SPEFSCR_REGNO
)
21891 /* SPE high reg number. We get these values of regno from
21892 rs6000_dwarf_register_span. */
21893 gcc_assert (regno
>= 1200 && regno
< 1232);
21897 /* target hook eh_return_filter_mode */
21898 static enum machine_mode
21899 rs6000_eh_return_filter_mode (void)
21901 return TARGET_32BIT
? SImode
: word_mode
;
21904 /* Target hook for scalar_mode_supported_p. */
21906 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
21908 if (DECIMAL_FLOAT_MODE_P (mode
))
21911 return default_scalar_mode_supported_p (mode
);
21914 /* Target hook for vector_mode_supported_p. */
21916 rs6000_vector_mode_supported_p (enum machine_mode mode
)
21919 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
21922 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
21925 else if (TARGET_ALTIVEC
&& ALTIVEC_VECTOR_MODE (mode
))
21932 /* Target hook for invalid_arg_for_unprototyped_fn. */
21933 static const char *
21934 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
21936 return (!rs6000_darwin64_abi
21938 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
21939 && (funcdecl
== NULL_TREE
21940 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
21941 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
21942 ? N_("AltiVec argument passed to unprototyped function")
21946 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
21947 setup by using __stack_chk_fail_local hidden function instead of
21948 calling __stack_chk_fail directly. Otherwise it is better to call
21949 __stack_chk_fail directly. */
21952 rs6000_stack_protect_fail (void)
21954 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
21955 ? default_hidden_stack_protect_fail ()
21956 : default_external_stack_protect_fail ();
21959 #include "gt-rs6000.h"