1 ;; GCC machine description for CRIS atomic memory sequences.
2 ;; Copyright (C) 2012-2023 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; The CRIS atomic support yields code in three flavors, depending on
21 ;; the CPU for which code is generated:
23 ;; - Plain old CRIS v0 (..v8)
24 ;; - CRIS v10 (as used in ETRAX 100 LX)
26 ;; The second alternative is of LL/SC type. It may
27 ;; fail for other reasons; an exception, a cache miss or a bus request
28 ;; from other parts of the system. See the chapter on integral read-write
29 ;; operations, chapter 1.13 in "ETRAX 100LX Programmers Manual",
30 ;; <http://www.axis.com/files/tech_notes/etrax_100lx_prog_man-050519.pdf>.
31 ;; Note that the datum being stored has to be contained fully within a
32 ;; cache-line to be integral. A failure to store the data integrally
33 ;; will be flagged, but the store may still have happened in part,
34 ;; which translates most usefully into the data having to be
35 ;; "naturally aligned" to work. Natural alignment is verified in the
36 ;; generated code and will by default cause for unaligned pointers a
37 ;; "break 8" to be executed or optionally a call to abort(). Beware
38 ;; that options -m16bit and -m8bit may cause data to be unaligned
39 ;; where it was otherwise aligned. Data has a better chance of being
40 ;; aligned if it is declared with e.g. __attribute__ ((__align__ (4))).
42 ;; The "plain old v0..v8 flavor" just assumes there's a single CPU in
43 ;; the system, that no other parts of the system have access to memory
44 ;; used for atomic accesses and since there's no user mode without
45 ;; access to interrupt flags (another assumption), it just turns off
46 ;; interrupts while doing the access. Here, alignment is neither
47 ;; required nor asserted.
52 CRIS_UNSPEC_ATOMIC_SWAP_MEM
53 CRIS_UNSPEC_ATOMIC_SWAP_BOOL
56 (define_constants [(CRIS_CCR_INTERRUPT_BIT 5)])
58 ;; We use "mult" as a placeholder for "nand" (which does not have a
59 ;; separate binary rtx operation) so we can use an iterator in the
60 ;; define_expand and define_insn and avoid having a separate
61 ;; mostly-identical copy. You will see the "mult" operator in rtl
62 ;; dumps, but it shouldn't matter as its use has one of its operands
63 ;; inside an unspec_volatile.
65 (define_code_iterator atomic_op [plus minus ior and xor mult])
67 (define_code_attr atomic_op_name
68 [(plus "add") (minus "sub") (and "and") (ior "or") (xor "xor") (mult "nand")])
70 ;; The operator nonatomic-operand can be memory, constant or register
71 ;; for all but xor. We can't use memory or addressing modes with
72 ;; side-effects though, so just use registers and literal constants.
73 (define_code_attr atomic_op_op_cnstr
74 [(plus "ri") (minus "ri") (and "ri") (ior "ri") (xor "r") (mult "ri")])
76 (define_code_attr atomic_op_op_pred
77 [(plus "nonmemory_operand") (minus "nonmemory_operand")
78 (and "nonmemory_operand") (ior "nonmemory_operand")
79 (xor "register_operand") (mult "nonmemory_operand")])
81 ;; Pairs of these are used to insert the "not" after the "and" for nand.
82 (define_code_attr atomic_op_mnem_pre_op2 ;; Upper-case only to simplify testing.
83 [(plus "%P2") (minus "Sub.d %2") (and "And%q2 %2") (ior "Or%q2 %2") (xor "Xor %2")
86 (define_code_attr atomic_op_mnem_post_op3
87 [(plus "") (minus "") (and "") (ior "") (xor "") (mult "not %3\;")])
89 ;; For SImode, emit "q" for operands -31..31.
90 (define_mode_attr qm3 [(SI "%q3") (HI ".w") (QI ".b")])
92 (define_expand "atomic_fetch_<atomic_op_name><mode>"
93 [(match_operand:BWD 0 "register_operand")
94 (match_operand:BWD 1 "memory_operand")
95 (match_operand:BWD 2 "<atomic_op_op_pred>")
97 (atomic_op:BWD (match_dup 0) (match_dup 1))]
98 "<MODE>mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS"
100 enum memmodel mmodel = (enum memmodel) INTVAL (operands[3]);
102 if (<MODE>mode != QImode && TARGET_TRAP_UNALIGNED_ATOMIC)
103 cris_emit_trap_for_misalignment (operands[1]);
105 if (need_atomic_barrier_p (mmodel, true))
106 expand_mem_thread_fence (mmodel);
108 emit_insn (gen_cris_atomic_fetch_<atomic_op_name><mode>_1 (operands[0],
111 if (need_atomic_barrier_p (mmodel, false))
112 expand_mem_thread_fence (mmodel);
117 (define_insn "cris_atomic_fetch_<atomic_op_name><mode>_1"
118 [(set (match_operand:BWD 1 "memory_operand" "+Q")
120 (unspec_volatile:BWD [(match_dup 1)] CRIS_UNSPEC_ATOMIC_OP)
121 ;; FIXME: improve constants more for plus, minus, and, ior.
122 ;; FIXME: handle memory operands without side-effects.
123 (match_operand:BWD 2 "<atomic_op_op_pred>" "<atomic_op_op_cnstr>")))
124 (set (match_operand:BWD 0 "register_operand" "=&r")
126 (clobber (match_scratch:SI 3 "=&r"))
127 (clobber (reg:CC CRIS_CC0_REGNUM))]
128 "<MODE>mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS"
130 /* Can't be too sure; better ICE if this happens. */
131 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])
132 && !reg_overlap_mentioned_p (operands[0], operands[2])
133 && !reg_overlap_mentioned_p (operands[0], operands[3])
134 && !reg_overlap_mentioned_p (operands[1], operands[3])
135 && !reg_overlap_mentioned_p (operands[2], operands[3]));
137 if (cris_cpu_version == 10)
143 "<atomic_op_mnem_pre_op2>,%3\;<atomic_op_mnem_post_op3>"
150 /* This one is for CRIS versions without load-locked-store-conditional
151 machinery; assume single-core-non-shared-memory without user
152 mode/supervisor mode distinction, and just disable interrupts
153 while performing the operation.
154 Rather than making this pattern more complex by freeing another
155 register or stack position to save condition codes (the value
156 of the interrupt-enabled bit), we check whether interrupts were
157 enabled before we disabled them and branch to a version
158 with/without afterwards re-enabling them. */
161 /* We have no available macro to stringify CRIS_CCR_INTERRUPT_BIT. */
162 memcpy (ops, operands, sizeof(ops));
163 ops[4] = GEN_INT (CRIS_CCR_INTERRUPT_BIT);
165 output_asm_insn ("move $ccr,%3\;"
171 "bmi .Lsync.irqon.%=\;"
174 "<atomic_op_mnem_pre_op2>,%3\;<atomic_op_mnem_post_op3>"
175 "ba .Lsync.irqoff.%=\;"
179 "<atomic_op_mnem_pre_op2>,%3\;<atomic_op_mnem_post_op3>"
186 ;; This pattern is more-or-less assumed to always exist if any of the
187 ;; other atomic patterns exist (see e.g. comment at the
188 ;; can_compare_and_swap_p call in omp-low.cc, 4.8 era). We'd slightly
189 ;; prefer atomic_exchange<mode> over this, but having both would be
191 ;; FIXME: handle memory without side-effects for operand[3].
192 (define_expand "atomic_compare_and_swap<mode>"
193 [(match_operand:SI 0 "register_operand")
194 (match_operand:BWD 1 "register_operand")
195 (match_operand:BWD 2 "memory_operand")
196 (match_operand:BWD 3 "nonmemory_operand")
197 (match_operand:BWD 4 "register_operand")
201 "<MODE>mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS"
203 enum memmodel mmodel = (enum memmodel) INTVAL (operands[6]);
205 if (<MODE>mode != QImode && TARGET_TRAP_UNALIGNED_ATOMIC)
206 cris_emit_trap_for_misalignment (operands[2]);
208 if (need_atomic_barrier_p (mmodel, true))
209 expand_mem_thread_fence (mmodel);
211 emit_insn (gen_cris_atomic_compare_and_swap<mode>_1 (operands[0],
216 if (need_atomic_barrier_p (mmodel, false))
217 expand_mem_thread_fence (mmodel);
222 (define_insn "cris_atomic_compare_and_swap<mode>_1"
223 [(set (match_operand:SI 0 "register_operand" "=&r")
225 [(match_operand:BWD 2 "memory_operand" "+Q")
226 (match_operand:BWD 3 "nonmemory_operand" "ri")]
227 CRIS_UNSPEC_ATOMIC_SWAP_BOOL))
228 (set (match_operand:BWD 1 "register_operand" "=&r") (match_dup 2))
233 (match_operand:BWD 4 "register_operand" "r")]
234 CRIS_UNSPEC_ATOMIC_SWAP_MEM))
235 (clobber (reg:CC CRIS_CC0_REGNUM))]
236 "<MODE>mode == QImode || !TARGET_ATOMICS_MAY_CALL_LIBFUNCS"
238 if (cris_cpu_version == 10)
240 "\n.Lsync.repeat.%=:\;"
244 "bne .Lsync.after.%=\;"
248 "bwf .Lsync.repeat.%=\n"
253 /* This one is for CRIS versions without load-locked-store-conditional
254 machinery; assume single-core-non-shared-memory without user
255 mode/supervisor mode distinction, and just disable interrupts
256 while performing the operation.
257 Rather than making this pattern more complex by freeing another
258 register or stack position to save condition codes (the value
259 of the interrupt-enabled bit), we check whether interrupts were
260 enabled before we disabled them and branch to a version
261 with/without afterwards re-enabling them. */
264 /* We have no available macro to stringify CRIS_CCR_INTERRUPT_BIT. */
265 memcpy (ops, operands, sizeof(ops));
266 ops[3] = GEN_INT (CRIS_CCR_INTERRUPT_BIT);
268 output_asm_insn ("move $ccr,%0\;"
274 "bmi .Lsync.irqon.%=\;"
278 "bne .Lsync.after.%=\;"
280 "ba .Lsync.after.%=\;"
285 "bne .Lsync.after.%=\;"