1 ;; MIPS Paired-Single Floating and MIPS-3D Instructions.
2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_c_enum "unspec" [
24 ;; MIPS64/MIPS32R2 alnv.ps
27 ;; MIPS-3D instructions
44 (define_insn "*movcc_v2sf_<mode>"
45 [(set (match_operand:V2SF 0 "register_operand" "=f,f")
47 (match_operator:GPR 4 "equality_operator"
48 [(match_operand:GPR 1 "register_operand" "d,d")
50 (match_operand:V2SF 2 "register_operand" "f,0")
51 (match_operand:V2SF 3 "register_operand" "0,f")))]
52 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
56 [(set_attr "type" "condmove")
57 (set_attr "mode" "SF")])
59 (define_insn "mips_cond_move_tf_ps"
60 [(set (match_operand:V2SF 0 "register_operand" "=f,f")
61 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f,0")
62 (match_operand:V2SF 2 "register_operand" "0,f")
63 (match_operand:CCV2 3 "register_operand" "z,z")]
65 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
69 [(set_attr "type" "condmove")
70 (set_attr "mode" "SF")])
72 (define_expand "movv2sfcc"
73 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
74 (set (match_operand:V2SF 0 "register_operand")
75 (if_then_else:V2SF (match_dup 5)
76 (match_operand:V2SF 2 "register_operand")
77 (match_operand:V2SF 3 "register_operand")))]
78 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
80 /* We can only support MOVN.PS and MOVZ.PS.
81 NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and
82 MOVZ.PS. MOVT.PS and MOVF.PS depend on two CC values and move
83 each item independently. */
85 if (GET_MODE_CLASS (GET_MODE (XEXP (operands[1], 0))) != MODE_INT)
88 mips_expand_conditional_move (operands);
92 (define_insn "vec_perm_const_ps"
93 [(set (match_operand:V2SF 0 "register_operand" "=f")
96 (match_operand:V2SF 1 "register_operand" "f")
97 (match_operand:V2SF 2 "register_operand" "f"))
98 (parallel [(match_operand:SI 3 "const_0_or_1_operand" "")
99 (match_operand:SI 4 "const_2_or_3_operand" "")])))]
100 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
102 /* Let <op>L be the lower part of operand <op> and <op>U be the upper part.
103 The P[UL][UL].PS instruction always specifies the upper part of the
104 result first, so the instruction is:
106 P<aUL><bUL>.PS %0,<aop>,<bop>
108 where 0U == <aop><aUL> and 0L == <bop><bUL>.
110 GCC's vector indices are specified in memory order, which means
111 that vector element 0 is the lower part (L) on little-endian targets
112 and the upper part (U) on big-endian targets. vec_concat likewise
113 concatenates in memory order, which means that operand 3 (being
114 0 or 1) selects part of operand 1 and operand 4 (being 2 or 3)
115 selects part of operand 2.
119 I3 = INTVAL (operands[3])
120 I4 = INTVAL (operands[4]) - 2
122 Taking the two endiannesses in turn:
126 The semantics of the RTL pattern are:
128 { 0L, 0U } = { X[I3], X[I4 + 2] }, where X = { 1L, 1U, 2L, 2U }
130 so: 0L = { 1L, 1U }[I3] (= <bop><bUL>)
131 0U = { 2L, 2U }[I4] (= <aop><aUL>)
133 <aop> = 2, <aUL> = I4 ? U : L
134 <bop> = 1, <bUL> = I3 ? U : L
136 [LL] !I4 && !I3 [UL] I4 && !I3
137 [LU] !I4 && I3 [UU] I4 && I3
141 The semantics of the RTL pattern are:
143 { 0U, 0L } = { X[I3], X[I4 + 2] }, where X = { 1U, 1L, 2U, 2L }
145 so: 0U = { 1U, 1L }[I3] (= <aop><aUL>)
146 0L = { 2U, 2L }[I4] (= <bop><bUL>)
148 <aop> = 1, <aUL> = I3 ? L : U
149 <bop> = 2, <bUL> = I4 ? L : U
151 [UU] !I3 && !I4 [UL] !I3 && I4
152 [LU] I3 && !I4 [LL] I3 && I4. */
154 static const char * const mnemonics[2][4] = {
155 /* LE */ { "pll.ps\t%0,%2,%1", "pul.ps\t%0,%2,%1",
156 "plu.ps\t%0,%2,%1", "puu.ps\t%0,%2,%1" },
157 /* BE */ { "puu.ps\t%0,%1,%2", "pul.ps\t%0,%1,%2",
158 "plu.ps\t%0,%1,%2", "pll.ps\t%0,%1,%2" },
161 unsigned mask = INTVAL (operands[3]) * 2 + (INTVAL (operands[4]) - 2);
162 return mnemonics[BYTES_BIG_ENDIAN][mask];
164 [(set_attr "type" "fmove")
165 (set_attr "mode" "SF")])
167 (define_expand "vec_perm_constv2sf"
168 [(match_operand:V2SF 0 "register_operand" "")
169 (match_operand:V2SF 1 "register_operand" "")
170 (match_operand:V2SF 2 "register_operand" "")
171 (match_operand:V2SI 3 "" "")]
172 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
174 if (mips_expand_vec_perm_const (operands))
180 ;; Expanders for builtins. The instruction:
182 ;; P[UL][UL].PS <result>, <a>, <b>
184 ;; says that the upper part of <result> is taken from half of <a> and
185 ;; the lower part of <result> is taken from half of <b>. This means
186 ;; that the P[UL][UL].PS operand order matches memory order on big-endian
187 ;; targets; <a> is element 0 of the V2SF result while <b> is element 1.
188 ;; However, the P[UL][UL].PS operand order is the reverse of memory order
189 ;; on little-endian targets; <a> is element 1 of the V2SF result while
190 ;; <b> is element 0. The arguments to vec_perm_const_ps are always in
193 ;; Similarly, "U" corresponds to element 0 on big-endian targets but
194 ;; to element 1 on little-endian targets.
196 (define_expand "mips_puu_ps"
197 [(match_operand:V2SF 0 "register_operand" "")
198 (match_operand:V2SF 1 "register_operand" "")
199 (match_operand:V2SF 2 "register_operand" "")]
200 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
202 if (BYTES_BIG_ENDIAN)
203 emit_insn (gen_vec_perm_const_ps (operands[0], operands[1], operands[2],
204 const0_rtx, const2_rtx));
206 emit_insn (gen_vec_perm_const_ps (operands[0], operands[2], operands[1],
207 const1_rtx, GEN_INT (3)));
211 (define_expand "mips_pul_ps"
212 [(match_operand:V2SF 0 "register_operand" "")
213 (match_operand:V2SF 1 "register_operand" "")
214 (match_operand:V2SF 2 "register_operand" "")]
215 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
217 if (BYTES_BIG_ENDIAN)
218 emit_insn (gen_vec_perm_const_ps (operands[0], operands[1], operands[2],
219 const0_rtx, GEN_INT (3)));
221 emit_insn (gen_vec_perm_const_ps (operands[0], operands[2], operands[1],
222 const0_rtx, GEN_INT (3)));
226 (define_expand "mips_plu_ps"
227 [(match_operand:V2SF 0 "register_operand" "")
228 (match_operand:V2SF 1 "register_operand" "")
229 (match_operand:V2SF 2 "register_operand" "")]
230 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
232 if (BYTES_BIG_ENDIAN)
233 emit_insn (gen_vec_perm_const_ps (operands[0], operands[1], operands[2],
234 const1_rtx, const2_rtx));
236 emit_insn (gen_vec_perm_const_ps (operands[0], operands[2], operands[1],
237 const1_rtx, const2_rtx));
241 (define_expand "mips_pll_ps"
242 [(match_operand:V2SF 0 "register_operand" "")
243 (match_operand:V2SF 1 "register_operand" "")
244 (match_operand:V2SF 2 "register_operand" "")]
245 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
247 if (BYTES_BIG_ENDIAN)
248 emit_insn (gen_vec_perm_const_ps (operands[0], operands[1], operands[2],
249 const1_rtx, GEN_INT (3)));
251 emit_insn (gen_vec_perm_const_ps (operands[0], operands[2], operands[1],
252 const0_rtx, const2_rtx));
257 (define_expand "vec_initv2sf"
258 [(match_operand:V2SF 0 "register_operand")
259 (match_operand:V2SF 1 "")]
260 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
262 mips_expand_vector_init (operands[0], operands[1]);
266 (define_insn "vec_concatv2sf"
267 [(set (match_operand:V2SF 0 "register_operand" "=f")
269 (match_operand:SF 1 "register_operand" "f")
270 (match_operand:SF 2 "register_operand" "f")))]
271 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
273 if (BYTES_BIG_ENDIAN)
274 return "cvt.ps.s\t%0,%1,%2";
276 return "cvt.ps.s\t%0,%2,%1";
278 [(set_attr "type" "fcvt")
279 (set_attr "mode" "SF")])
281 ;; ??? This is only generated if we perform a vector operation that has to be
282 ;; emulated. There is no other way to get a vector mode bitfield extract
285 (define_insn "vec_extractv2sf"
286 [(set (match_operand:SF 0 "register_operand" "=f")
287 (vec_select:SF (match_operand:V2SF 1 "register_operand" "f")
289 [(match_operand 2 "const_0_or_1_operand" "")])))]
290 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
292 if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
293 return "cvt.s.pu\t%0,%1";
295 return "cvt.s.pl\t%0,%1";
297 [(set_attr "type" "fcvt")
298 (set_attr "mode" "SF")])
300 ;; ??? This is only generated if we disable the vec_init pattern. There is
301 ;; no other way to get a vector mode bitfield store currently.
303 (define_expand "vec_setv2sf"
304 [(set (match_operand:V2SF 0 "register_operand" "")
307 (match_operand:SF 1 "register_operand" "")
309 (parallel [(match_operand 2 "const_0_or_1_operand" "")
311 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
313 /* We don't have an insert instruction, so we duplicate the float, and
314 then use a PUL instruction. */
315 rtx temp = gen_reg_rtx (V2SFmode);
316 emit_insn (gen_vec_concatv2sf (temp, operands[1], operands[1]));
318 operands[3] = GEN_INT (1 - INTVAL (operands[2]) + 2);
321 ; cvt.ps.s - Floating Point Convert Pair to Paired Single
322 (define_expand "mips_cvt_ps_s"
323 [(match_operand:V2SF 0 "register_operand")
324 (match_operand:SF 1 "register_operand")
325 (match_operand:SF 2 "register_operand")]
326 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
328 if (BYTES_BIG_ENDIAN)
329 emit_insn (gen_vec_concatv2sf (operands[0], operands[1], operands[2]));
331 emit_insn (gen_vec_concatv2sf (operands[0], operands[2], operands[1]));
335 ; cvt.s.pl - Floating Point Convert Pair Lower to Single Floating Point
336 (define_expand "mips_cvt_s_pl"
337 [(set (match_operand:SF 0 "register_operand")
338 (vec_select:SF (match_operand:V2SF 1 "register_operand")
339 (parallel [(match_dup 2)])))]
340 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
341 { operands[2] = GEN_INT (BYTES_BIG_ENDIAN); })
343 ; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point
344 (define_expand "mips_cvt_s_pu"
345 [(set (match_operand:SF 0 "register_operand")
346 (vec_select:SF (match_operand:V2SF 1 "register_operand")
347 (parallel [(match_dup 2)])))]
348 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
349 { operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); })
351 ; alnv.ps - Floating Point Align Variable
352 (define_insn "mips_alnv_ps"
353 [(set (match_operand:V2SF 0 "register_operand" "=f")
354 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
355 (match_operand:V2SF 2 "register_operand" "f")
356 (match_operand:SI 3 "register_operand" "d")]
358 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
359 "alnv.ps\t%0,%1,%2,%3"
360 [(set_attr "type" "fmove")
361 (set_attr "mode" "SF")])
363 ; addr.ps - Floating Point Reduction Add
364 (define_insn "mips_addr_ps"
365 [(set (match_operand:V2SF 0 "register_operand" "=f")
366 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
367 (match_operand:V2SF 2 "register_operand" "f")]
369 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
371 [(set_attr "type" "fadd")
372 (set_attr "mode" "SF")])
374 (define_expand "reduc_plus_scal_v2sf"
375 [(match_operand:SF 0 "register_operand" "=f")
376 (match_operand:V2SF 1 "register_operand" "f")]
377 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
379 rtx temp = gen_reg_rtx (V2SFmode);
380 emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1]));
381 rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx;
382 emit_insn (gen_vec_extractv2sf (operands[0], temp, lane));
386 ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word
387 (define_insn "mips_cvt_pw_ps"
388 [(set (match_operand:V2SF 0 "register_operand" "=f")
389 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
391 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
393 [(set_attr "type" "fcvt")
394 (set_attr "mode" "SF")])
396 ; cvt.ps.pw - Floating Point Convert Paired Word to Paired Single
397 (define_insn "mips_cvt_ps_pw"
398 [(set (match_operand:V2SF 0 "register_operand" "=f")
399 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
401 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
403 [(set_attr "type" "fcvt")
404 (set_attr "mode" "SF")])
406 ; mulr.ps - Floating Point Reduction Multiply
407 (define_insn "mips_mulr_ps"
408 [(set (match_operand:V2SF 0 "register_operand" "=f")
409 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
410 (match_operand:V2SF 2 "register_operand" "f")]
412 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
414 [(set_attr "type" "fmul")
415 (set_attr "mode" "SF")])
418 (define_expand "mips_abs_ps"
419 [(set (match_operand:V2SF 0 "register_operand")
420 (unspec:V2SF [(match_operand:V2SF 1 "register_operand")]
422 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
424 /* If we can ignore NaNs, this operation is equivalent to the
426 if (!HONOR_NANS (V2SFmode))
428 emit_insn (gen_absv2sf2 (operands[0], operands[1]));
433 (define_insn "*mips_abs_ps"
434 [(set (match_operand:V2SF 0 "register_operand" "=f")
435 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
437 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
439 [(set_attr "type" "fabs")
440 (set_attr "mode" "SF")])
442 ;----------------------------------------------------------------------------
443 ; Floating Point Comparisons for Scalars
444 ;----------------------------------------------------------------------------
446 (define_insn "mips_cabs_cond_<fmt>"
447 [(set (match_operand:CC 0 "register_operand" "=z")
448 (unspec:CC [(match_operand:SCALARF 1 "register_operand" "f")
449 (match_operand:SCALARF 2 "register_operand" "f")
450 (match_operand 3 "const_int_operand" "")]
452 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
453 "cabs.%Y3.<fmt>\t%0,%1,%2"
454 [(set_attr "type" "fcmp")
455 (set_attr "mode" "FPSW")])
458 ;----------------------------------------------------------------------------
459 ; Floating Point Comparisons for Four Singles
460 ;----------------------------------------------------------------------------
462 (define_insn_and_split "mips_c_cond_4s"
463 [(set (match_operand:CCV4 0 "register_operand" "=z")
464 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
465 (match_operand:V2SF 2 "register_operand" "f")
466 (match_operand:V2SF 3 "register_operand" "f")
467 (match_operand:V2SF 4 "register_operand" "f")
468 (match_operand 5 "const_int_operand" "")]
470 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
472 "&& reload_completed"
474 (unspec:CCV2 [(match_dup 1)
479 (unspec:CCV2 [(match_dup 3)
484 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
485 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
487 [(set_attr "type" "fcmp")
488 (set_attr "insn_count" "2")
489 (set_attr "mode" "FPSW")])
491 (define_insn_and_split "mips_cabs_cond_4s"
492 [(set (match_operand:CCV4 0 "register_operand" "=z")
493 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
494 (match_operand:V2SF 2 "register_operand" "f")
495 (match_operand:V2SF 3 "register_operand" "f")
496 (match_operand:V2SF 4 "register_operand" "f")
497 (match_operand 5 "const_int_operand" "")]
499 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
501 "&& reload_completed"
503 (unspec:CCV2 [(match_dup 1)
508 (unspec:CCV2 [(match_dup 3)
513 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
514 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
516 [(set_attr "type" "fcmp")
517 (set_attr "insn_count" "2")
518 (set_attr "mode" "FPSW")])
521 ;----------------------------------------------------------------------------
522 ; Floating Point Comparisons for Paired Singles
523 ;----------------------------------------------------------------------------
525 (define_insn "mips_c_cond_ps"
526 [(set (match_operand:CCV2 0 "register_operand" "=z")
527 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
528 (match_operand:V2SF 2 "register_operand" "f")
529 (match_operand 3 "const_int_operand" "")]
531 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
533 [(set_attr "type" "fcmp")
534 (set_attr "mode" "FPSW")])
536 (define_insn "mips_cabs_cond_ps"
537 [(set (match_operand:CCV2 0 "register_operand" "=z")
538 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
539 (match_operand:V2SF 2 "register_operand" "f")
540 (match_operand 3 "const_int_operand" "")]
542 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
543 "cabs.%Y3.ps\t%0,%1,%2"
544 [(set_attr "type" "fcmp")
545 (set_attr "mode" "FPSW")])
547 ;; An expander for generating an scc operation.
548 (define_expand "scc_ps"
549 [(set (match_operand:CCV2 0)
550 (unspec:CCV2 [(match_operand 1)] UNSPEC_SCC))])
552 (define_insn "s<code>_ps"
553 [(set (match_operand:CCV2 0 "register_operand" "=z")
555 [(fcond (match_operand:V2SF 1 "register_operand" "f")
556 (match_operand:V2SF 2 "register_operand" "f"))]
558 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
559 "c.<fcond>.ps\t%0,%1,%2"
560 [(set_attr "type" "fcmp")
561 (set_attr "mode" "FPSW")])
563 (define_insn "s<code>_ps"
564 [(set (match_operand:CCV2 0 "register_operand" "=z")
566 [(swapped_fcond (match_operand:V2SF 1 "register_operand" "f")
567 (match_operand:V2SF 2 "register_operand" "f"))]
569 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
570 "c.<swapped_fcond>.ps\t%0,%2,%1"
571 [(set_attr "type" "fcmp")
572 (set_attr "mode" "FPSW")])
574 ;----------------------------------------------------------------------------
575 ; Floating Point Branch Instructions.
576 ;----------------------------------------------------------------------------
578 ; Branch on Any of Four Floating Point Condition Codes True
579 (define_insn "bc1any4t"
581 (if_then_else (ne (match_operand:CCV4 1 "register_operand" "z")
583 (label_ref (match_operand 0 "" ""))
585 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
586 "%*bc1any4t\t%1,%0%/"
587 [(set_attr "type" "branch")])
589 ; Branch on Any of Four Floating Point Condition Codes False
590 (define_insn "bc1any4f"
592 (if_then_else (ne (match_operand:CCV4 1 "register_operand" "z")
594 (label_ref (match_operand 0 "" ""))
596 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
597 "%*bc1any4f\t%1,%0%/"
598 [(set_attr "type" "branch")])
600 ; Branch on Any of Two Floating Point Condition Codes True
601 (define_insn "bc1any2t"
603 (if_then_else (ne (match_operand:CCV2 1 "register_operand" "z")
605 (label_ref (match_operand 0 "" ""))
607 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
608 "%*bc1any2t\t%1,%0%/"
609 [(set_attr "type" "branch")])
611 ; Branch on Any of Two Floating Point Condition Codes False
612 (define_insn "bc1any2f"
614 (if_then_else (ne (match_operand:CCV2 1 "register_operand" "z")
616 (label_ref (match_operand 0 "" ""))
618 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
619 "%*bc1any2f\t%1,%0%/"
620 [(set_attr "type" "branch")])
622 ; Used to access one register in a CCV2 pair. Operand 0 is the register
623 ; pair and operand 1 is the index of the register we want (a CONST_INT).
624 (define_expand "single_cc"
625 [(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC)
628 ; This is a normal floating-point branch pattern, but rather than check
629 ; a single CCmode register, it checks one register in a CCV2 pair.
630 ; Operand 2 is the register pair and operand 3 is the index of the
632 (define_insn "*branch_upper_lower"
635 (match_operator 1 "equality_operator"
636 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
637 (match_operand 3 "const_int_operand")]
640 (label_ref (match_operand 0 "" ""))
645 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
646 return mips_output_conditional_branch (insn, operands,
647 MIPS_BRANCH ("b%F1", "%2,%0"),
648 MIPS_BRANCH ("b%W1", "%2,%0"));
650 [(set_attr "type" "branch")])
652 ; As above, but with the sense of the condition reversed.
653 (define_insn "*branch_upper_lower_inverted"
656 (match_operator 1 "equality_operator"
657 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
658 (match_operand 3 "const_int_operand")]
662 (label_ref (match_operand 0 "" ""))))]
666 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
667 return mips_output_conditional_branch (insn, operands,
668 MIPS_BRANCH ("b%W1", "%2,%0"),
669 MIPS_BRANCH ("b%F1", "%2,%0"));
671 [(set_attr "type" "branch")])
673 ;----------------------------------------------------------------------------
674 ; Floating Point Reduced Precision Reciprocal Square Root Instructions.
675 ;----------------------------------------------------------------------------
677 (define_insn "mips_rsqrt1_<fmt>"
678 [(set (match_operand:ANYF 0 "register_operand" "=f")
679 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
681 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
682 "rsqrt1.<fmt>\t%0,%1"
683 [(set_attr "type" "frsqrt1")
684 (set_attr "mode" "<UNITMODE>")])
686 (define_insn "mips_rsqrt2_<fmt>"
687 [(set (match_operand:ANYF 0 "register_operand" "=f")
688 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
689 (match_operand:ANYF 2 "register_operand" "f")]
691 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
692 "rsqrt2.<fmt>\t%0,%1,%2"
693 [(set_attr "type" "frsqrt2")
694 (set_attr "mode" "<UNITMODE>")])
696 (define_insn "mips_recip1_<fmt>"
697 [(set (match_operand:ANYF 0 "register_operand" "=f")
698 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
700 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
701 "recip1.<fmt>\t%0,%1"
702 [(set_attr "type" "frdiv1")
703 (set_attr "mode" "<UNITMODE>")])
705 (define_insn "mips_recip2_<fmt>"
706 [(set (match_operand:ANYF 0 "register_operand" "=f")
707 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
708 (match_operand:ANYF 2 "register_operand" "f")]
710 "TARGET_HARD_FLOAT && TARGET_MIPS3D"
711 "recip2.<fmt>\t%0,%1,%2"
712 [(set_attr "type" "frdiv2")
713 (set_attr "mode" "<UNITMODE>")])
715 (define_expand "vcondv2sfv2sf"
716 [(set (match_operand:V2SF 0 "register_operand")
719 [(match_operand:V2SF 4 "register_operand")
720 (match_operand:V2SF 5 "register_operand")])
721 (match_operand:V2SF 1 "register_operand")
722 (match_operand:V2SF 2 "register_operand")))]
723 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
725 mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
726 GET_CODE (operands[3]), operands[4], operands[5]);
730 (define_expand "sminv2sf3"
731 [(set (match_operand:V2SF 0 "register_operand")
732 (smin:V2SF (match_operand:V2SF 1 "register_operand")
733 (match_operand:V2SF 2 "register_operand")))]
734 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
736 mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
737 LE, operands[1], operands[2]);
741 (define_expand "smaxv2sf3"
742 [(set (match_operand:V2SF 0 "register_operand")
743 (smax:V2SF (match_operand:V2SF 1 "register_operand")
744 (match_operand:V2SF 2 "register_operand")))]
745 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
747 mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
748 LE, operands[2], operands[1]);
752 (define_expand "reduc_smin_scal_v2sf"
753 [(match_operand:SF 0 "register_operand")
754 (match_operand:V2SF 1 "register_operand")]
755 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
757 rtx temp = gen_reg_rtx (V2SFmode);
758 mips_expand_vec_reduc (temp, operands[1], gen_sminv2sf3);
759 rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx;
760 emit_insn (gen_vec_extractv2sf (operands[0], temp, lane));
764 (define_expand "reduc_smax_scal_v2sf"
765 [(match_operand:SF 0 "register_operand")
766 (match_operand:V2SF 1 "register_operand")]
767 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
769 rtx temp = gen_reg_rtx (V2SFmode);
770 mips_expand_vec_reduc (temp, operands[1], gen_smaxv2sf3);
771 rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx;
772 emit_insn (gen_vec_extractv2sf (operands[0], temp, lane));