1 ;; DFA-based pipeline descriptions for MIPS32 5K processor family
2 ;; Contributed by David Ung (davidu@mips.com)
3 ;; and Nigel Stephens (nigel@mips.com)
6 ;; "MIPS64 5K Processor Core Family Software User's Manual,
7 ;; Doc no: MD00012, Rev 2.09, Jan 28, 2005."
9 ;; 5Kc - Single issue with no floating point unit.
10 ;; 5kf - Separate floating point pipe which can dual-issue with the
13 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
15 ;; This file is part of GCC.
17 ;; GCC is free software; you can redistribute it and/or modify it
18 ;; under the terms of the GNU General Public License as published
19 ;; by the Free Software Foundation; either version 3, or (at your
20 ;; option) any later version.
22 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
23 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
25 ;; License for more details.
27 ;; You should have received a copy of the GNU General Public License
28 ;; along with GCC; see the file COPYING3. If not see
29 ;; <http://www.gnu.org/licenses/>.
31 (define_automaton "r5k_cpu, r5k_mdu, r5k_fpu")
33 ;; Integer execution unit.
34 (define_cpu_unit "r5k_ixu_arith" "r5k_cpu")
35 (define_cpu_unit "r5k_ixu_mpydiv" "r5k_mdu")
36 (define_cpu_unit "r5kf_fpu_arith" "r5k_fpu")
38 (define_insn_reservation "r5k_int_load" 2
39 (and (eq_attr "cpu" "5kc,5kf")
40 (eq_attr "type" "load"))
43 (define_insn_reservation "r5k_int_prefetch" 1
44 (and (eq_attr "cpu" "5kc,5kf")
45 (eq_attr "type" "prefetch,prefetchx"))
48 (define_insn_reservation "r5k_int_store" 1
49 (and (eq_attr "cpu" "5kc,5kf")
50 (eq_attr "type" "store"))
54 (define_insn_reservation "r5k_int_divsi" 34
55 (and (eq_attr "cpu" "5kc,5kf")
56 (and (eq_attr "type" "idiv")
57 (eq_attr "mode" "!DI")))
58 "r5k_ixu_arith+(r5k_ixu_mpydiv*34)")
60 (define_insn_reservation "r5k_int_divdi" 66
61 (and (eq_attr "cpu" "5kc,5kf")
62 (and (eq_attr "type" "idiv")
63 (eq_attr "mode" "DI")))
64 "r5k_ixu_arith+(r5k_ixu_mpydiv*66)")
67 ;; 32x16 is faster, but there's no way to detect this
68 (define_insn_reservation "r5k_int_mult" 2
69 (and (eq_attr "cpu" "5kc,5kf")
70 (and (eq_attr "type" "imul,imadd")
71 (eq_attr "mode" "SI")))
72 "r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
75 (define_insn_reservation "r5k_int_mult_64" 9
76 (and (eq_attr "cpu" "5kc,5kf")
77 (and (eq_attr "type" "imul,imadd")
78 (eq_attr "mode" "DI")))
79 "r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
81 ;; 3 operand MUL 32x32
82 (define_insn_reservation "r5k_int_mul" 4
83 (and (eq_attr "cpu" "5kc,5kf")
84 (and (eq_attr "type" "imul3")
85 (eq_attr "mode" "SI")))
86 "r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
88 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
89 (define_insn_reservation "r5k_int_mthilo" 1
90 (and (eq_attr "cpu" "5kc,5kf")
91 (eq_attr "type" "mthi,mtlo"))
92 "r5k_ixu_arith+r5k_ixu_mpydiv")
94 ;; Move from HI/LO -> integer operation has a 2 cycle latency.
95 (define_insn_reservation "r5k_int_mfhilo" 2
96 (and (eq_attr "cpu" "5kc,5kf")
97 (eq_attr "type" "mfhi,mflo"))
98 "r5k_ixu_arith+r5k_ixu_mpydiv")
100 ;; All other integer insns.
101 (define_insn_reservation "r5k_int_alu" 1
102 (and (eq_attr "cpu" "5kc,5kf")
103 (eq_attr "type" "arith,condmove,const,logical,move,nop,shift,signext,slt"))
106 (define_insn_reservation "r5k_int_branch" 1
107 (and (eq_attr "cpu" "5kc,5kf")
108 (eq_attr "type" "branch"))
111 ;; JR/JALR always cause one pipeline bubble because of interlock.
112 (define_insn_reservation "r5k_int_jump" 2
113 (and (eq_attr "cpu" "5kc,5kf")
114 (eq_attr "type" "jump,call"))
117 ;; Any -> JR/JALR (without dependency) : 1 clock issue delay
118 ;; Any -> JR/JALR (with dependency) : 2 clock issue delay
119 ;; load -> JR/JALR (with dependency) : 3 clock issue delay
120 ;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay
121 ;; mul -> JR/JALR (with dependency) : 3 clock issue delay
122 (define_bypass 2 "r5k_int_alu" "r5k_int_jump")
123 (define_bypass 3 "r5k_int_load" "r5k_int_jump")
124 (define_bypass 3 "r5k_int_mfhilo" "r5k_int_jump")
125 (define_bypass 3 "r5k_int_mul" "r5k_int_jump")
127 ;; Unknown or multi - single issue
128 (define_insn_reservation "r5k_int_unknown" 1
129 (and (eq_attr "cpu" "5kc,5kf")
130 (eq_attr "type" "unknown,multi,atomic,syncloop"))
131 "r5k_ixu_arith+r5k_ixu_mpydiv")
134 ;; Floating Point Instructions
135 ;; The 5Kf is a partial dual-issue cpu which can dual issue an integer
136 ;; and floating-point instruction in the same cycle.
139 (define_insn_reservation "r5kf_fadd" 4
140 (and (eq_attr "cpu" "5kf")
141 (eq_attr "type" "fadd,fabs,fneg"))
145 (define_insn_reservation "r5kf_fmove" 4
146 (and (eq_attr "cpu" "5kf")
147 (eq_attr "type" "fmove"))
151 (define_insn_reservation "r5kf_fload" 3
152 (and (eq_attr "cpu" "5kf")
153 (eq_attr "type" "fpload,fpidxload"))
157 (define_insn_reservation "r5kf_fstore" 1
158 (and (eq_attr "cpu" "5kf")
159 (eq_attr "type" "fpstore"))
163 (define_insn_reservation "r5kf_fmul_sf" 4
164 (and (eq_attr "cpu" "5kf")
165 (and (eq_attr "type" "fmul,fmadd")
166 (eq_attr "mode" "SF")))
169 (define_insn_reservation "r5kf_fmul_df" 5
170 (and (eq_attr "cpu" "5kf")
171 (and (eq_attr "type" "fmul,fmadd")
172 (eq_attr "mode" "DF")))
175 ;; fdiv, fsqrt, frsqrt
176 (define_insn_reservation "r5kf_fdiv_sf" 17
177 (and (eq_attr "cpu" "5kf")
178 (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
179 (eq_attr "mode" "SF")))
182 (define_insn_reservation "r5kf_fdiv_df" 32
183 (and (eq_attr "cpu" "5kf")
184 (and (eq_attr "type" "fdiv,fsqrt")
185 (eq_attr "mode" "DF")))
189 (define_insn_reservation "r5kf_frsqrt_df" 35
190 (and (eq_attr "cpu" "5kf")
191 (and (eq_attr "type" "frsqrt")
192 (eq_attr "mode" "DF")))
196 (define_insn_reservation "r5kf_fcmp" 2
197 (and (eq_attr "cpu" "5kf")
198 (eq_attr "type" "fcmp"))
201 ;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on condition)
202 (define_bypass 1 "r5kf_fcmp" "r5kf_fmove")
204 ;; fcvt (cvt.d.s, cvt.[sd].[wl]
205 (define_insn_reservation "r5kf_fcvt_d2s" 4
206 (and (eq_attr "cpu" "5kf")
207 (and (eq_attr "type" "fcvt")
208 (eq_attr "cnv_mode" "I2S,I2D,S2D")))
212 (define_insn_reservation "r5kf_fcvt_s2d" 6
213 (and (eq_attr "cpu" "5kc")
214 (and (eq_attr "type" "fcvt")
215 (eq_attr "cnv_mode" "D2S")))
218 ;; fcvt (cvt.[wl].[sd], etc)
219 (define_insn_reservation "r5kf_fcvt_f2i" 5
220 (and (eq_attr "cpu" "5kf")
221 (and (eq_attr "type" "fcvt")
222 (eq_attr "cnv_mode" "S2I,D2I")))
225 ;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue
226 (define_insn_reservation "r5kf_fxfer" 2
227 (and (eq_attr "cpu" "5kf")
228 (eq_attr "type" "mfc,mtc"))
229 "r5k_ixu_arith+r5kf_fpu_arith")