1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
51 (UNSPEC_TLS_GET_TP 30)
54 (UNSPEC_CLEAR_HAZARD 33)
58 (UNSPEC_COMPARE_AND_SWAP 37)
59 (UNSPEC_COMPARE_AND_SWAP_12 38)
60 (UNSPEC_SYNC_OLD_OP 39)
61 (UNSPEC_SYNC_NEW_OP 40)
62 (UNSPEC_SYNC_NEW_OP_12 41)
63 (UNSPEC_SYNC_OLD_OP_12 42)
64 (UNSPEC_SYNC_EXCHANGE 43)
65 (UNSPEC_SYNC_EXCHANGE_12 44)
66 (UNSPEC_MEMORY_BARRIER 45)
67 (UNSPEC_SET_GOT_VERSION 46)
68 (UNSPEC_UPDATE_GOT_VERSION 47)
77 (UNSPEC_ADDRESS_FIRST 100)
80 (GOT_VERSION_REGNUM 79)
82 ;; For MIPS Paired-Singled Floating Point Instructions.
84 (UNSPEC_MOVE_TF_PS 200)
87 ;; MIPS64/MIPS32R2 alnv.ps
90 ;; MIPS-3D instructions
94 (UNSPEC_CVT_PW_PS 205)
95 (UNSPEC_CVT_PS_PW 206)
103 (UNSPEC_SINGLE_CC 213)
106 ;; MIPS DSP ASE Revision 0.98 3/24/2005
114 (UNSPEC_RADDU_W_QB 307)
116 (UNSPEC_PRECRQ_QB_PH 309)
117 (UNSPEC_PRECRQ_PH_W 310)
118 (UNSPEC_PRECRQ_RS_PH_W 311)
119 (UNSPEC_PRECRQU_S_QB_PH 312)
120 (UNSPEC_PRECEQ_W_PHL 313)
121 (UNSPEC_PRECEQ_W_PHR 314)
122 (UNSPEC_PRECEQU_PH_QBL 315)
123 (UNSPEC_PRECEQU_PH_QBR 316)
124 (UNSPEC_PRECEQU_PH_QBLA 317)
125 (UNSPEC_PRECEQU_PH_QBRA 318)
126 (UNSPEC_PRECEU_PH_QBL 319)
127 (UNSPEC_PRECEU_PH_QBR 320)
128 (UNSPEC_PRECEU_PH_QBLA 321)
129 (UNSPEC_PRECEU_PH_QBRA 322)
135 (UNSPEC_MULEU_S_PH_QBL 328)
136 (UNSPEC_MULEU_S_PH_QBR 329)
137 (UNSPEC_MULQ_RS_PH 330)
138 (UNSPEC_MULEQ_S_W_PHL 331)
139 (UNSPEC_MULEQ_S_W_PHR 332)
140 (UNSPEC_DPAU_H_QBL 333)
141 (UNSPEC_DPAU_H_QBR 334)
142 (UNSPEC_DPSU_H_QBL 335)
143 (UNSPEC_DPSU_H_QBR 336)
144 (UNSPEC_DPAQ_S_W_PH 337)
145 (UNSPEC_DPSQ_S_W_PH 338)
146 (UNSPEC_MULSAQ_S_W_PH 339)
147 (UNSPEC_DPAQ_SA_L_W 340)
148 (UNSPEC_DPSQ_SA_L_W 341)
149 (UNSPEC_MAQ_S_W_PHL 342)
150 (UNSPEC_MAQ_S_W_PHR 343)
151 (UNSPEC_MAQ_SA_W_PHL 344)
152 (UNSPEC_MAQ_SA_W_PHR 345)
160 (UNSPEC_CMPGU_EQ_QB 353)
161 (UNSPEC_CMPGU_LT_QB 354)
162 (UNSPEC_CMPGU_LE_QB 355)
164 (UNSPEC_PACKRL_PH 357)
166 (UNSPEC_EXTR_R_W 359)
167 (UNSPEC_EXTR_RS_W 360)
168 (UNSPEC_EXTR_S_H 361)
176 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
177 (UNSPEC_ABSQ_S_QB 400)
179 (UNSPEC_ADDU_S_PH 402)
180 (UNSPEC_ADDUH_QB 403)
181 (UNSPEC_ADDUH_R_QB 404)
184 (UNSPEC_CMPGDU_EQ_QB 407)
185 (UNSPEC_CMPGDU_LT_QB 408)
186 (UNSPEC_CMPGDU_LE_QB 409)
187 (UNSPEC_DPA_W_PH 410)
188 (UNSPEC_DPS_W_PH 411)
194 (UNSPEC_MUL_S_PH 417)
195 (UNSPEC_MULQ_RS_W 418)
196 (UNSPEC_MULQ_S_PH 419)
197 (UNSPEC_MULQ_S_W 420)
198 (UNSPEC_MULSA_W_PH 421)
201 (UNSPEC_PRECR_QB_PH 424)
202 (UNSPEC_PRECR_SRA_PH_W 425)
203 (UNSPEC_PRECR_SRA_R_PH_W 426)
206 (UNSPEC_SHRA_R_QB 429)
209 (UNSPEC_SUBU_S_PH 432)
210 (UNSPEC_SUBUH_QB 433)
211 (UNSPEC_SUBUH_R_QB 434)
212 (UNSPEC_ADDQH_PH 435)
213 (UNSPEC_ADDQH_R_PH 436)
215 (UNSPEC_ADDQH_R_W 438)
216 (UNSPEC_SUBQH_PH 439)
217 (UNSPEC_SUBQH_R_PH 440)
219 (UNSPEC_SUBQH_R_W 442)
220 (UNSPEC_DPAX_W_PH 443)
221 (UNSPEC_DPSX_W_PH 444)
222 (UNSPEC_DPAQX_S_W_PH 445)
223 (UNSPEC_DPAQX_SA_W_PH 446)
224 (UNSPEC_DPSQX_S_W_PH 447)
225 (UNSPEC_DPSQX_SA_W_PH 448)
227 ;; ST Microelectronics Loongson-2E/2F.
228 (UNSPEC_LOONGSON_PAVG 500)
229 (UNSPEC_LOONGSON_PCMPEQ 501)
230 (UNSPEC_LOONGSON_PCMPGT 502)
231 (UNSPEC_LOONGSON_PEXTR 503)
232 (UNSPEC_LOONGSON_PINSR_0 504)
233 (UNSPEC_LOONGSON_PINSR_1 505)
234 (UNSPEC_LOONGSON_PINSR_2 506)
235 (UNSPEC_LOONGSON_PINSR_3 507)
236 (UNSPEC_LOONGSON_PMADD 508)
237 (UNSPEC_LOONGSON_PMOVMSK 509)
238 (UNSPEC_LOONGSON_PMULHU 510)
239 (UNSPEC_LOONGSON_PMULH 511)
240 (UNSPEC_LOONGSON_PMULL 512)
241 (UNSPEC_LOONGSON_PMULU 513)
242 (UNSPEC_LOONGSON_PASUBUB 514)
243 (UNSPEC_LOONGSON_BIADD 515)
244 (UNSPEC_LOONGSON_PSADBH 516)
245 (UNSPEC_LOONGSON_PSHUFH 517)
246 (UNSPEC_LOONGSON_PUNPCKH 518)
247 (UNSPEC_LOONGSON_PUNPCKL 519)
248 (UNSPEC_LOONGSON_PADDD 520)
249 (UNSPEC_LOONGSON_PSUBD 521)
251 ;; Used in loongson2ef.md
252 (UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
253 (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
254 (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
255 (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
257 (UNSPEC_MIPS_CACHE 600)
258 (UNSPEC_R10K_CACHE_BARRIER 601)
262 (include "predicates.md")
263 (include "constraints.md")
265 ;; ....................
269 ;; ....................
271 (define_attr "got" "unset,xgot_high,load"
272 (const_string "unset"))
274 ;; For jal instructions, this attribute is DIRECT when the target address
275 ;; is symbolic and INDIRECT when it is a register.
276 (define_attr "jal" "unset,direct,indirect"
277 (const_string "unset"))
279 ;; This attribute is YES if the instruction is a jal macro (not a
280 ;; real jal instruction).
282 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
283 ;; an instruction to restore $gp. Direct jals are also macros for
284 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
285 ;; the target address into a register.
286 (define_attr "jal_macro" "no,yes"
287 (cond [(eq_attr "jal" "direct")
288 (symbol_ref "((TARGET_CALL_CLOBBERED_GP
289 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS))
290 ? JAL_MACRO_YES : JAL_MACRO_NO)")
291 (eq_attr "jal" "indirect")
292 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
293 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
294 (const_string "no")))
296 ;; Classification of moves, extensions and truncations. Most values
297 ;; are as for "type" (see below) but there are also the following
298 ;; move-specific values:
300 ;; constN move an N-constraint integer into a MIPS16 register
301 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
302 ;; to produce a sign-extended DEST, even if SRC is not
303 ;; properly sign-extended
304 ;; andi a single ANDI instruction
305 ;; loadpool move a constant into a MIPS16 register by loading it
307 ;; shift_shift a shift left followed by a shift right
308 ;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
310 ;; This attribute is used to determine the instruction's length and
311 ;; scheduling type. For doubleword moves, the attribute always describes
312 ;; the split instructions; in some cases, it is more appropriate for the
313 ;; scheduling type to be "multi" instead.
314 (define_attr "move_type"
315 "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
316 const,constN,signext,sll0,andi,loadpool,shift_shift,lui_movf"
317 (const_string "unknown"))
319 ;; Main data type used by the insn
320 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
321 (const_string "unknown"))
323 ;; True if the main data type is twice the size of a word.
324 (define_attr "dword_mode" "no,yes"
325 (cond [(and (eq_attr "mode" "DI,DF")
326 (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
329 (and (eq_attr "mode" "TI,TF")
330 (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
331 (const_string "yes")]
332 (const_string "no")))
334 ;; Classification of each insn.
335 ;; branch conditional branch
336 ;; jump unconditional jump
337 ;; call unconditional call
338 ;; load load instruction(s)
339 ;; fpload floating point load
340 ;; fpidxload floating point indexed load
341 ;; store store instruction(s)
342 ;; fpstore floating point store
343 ;; fpidxstore floating point indexed store
344 ;; prefetch memory prefetch (register + offset)
345 ;; prefetchx memory indexed prefetch (register + register)
346 ;; condmove conditional moves
347 ;; mtc transfer to coprocessor
348 ;; mfc transfer from coprocessor
349 ;; mthilo transfer to hi/lo registers
350 ;; mfhilo transfer from hi/lo registers
351 ;; const load constant
352 ;; arith integer arithmetic instructions
353 ;; logical integer logical instructions
354 ;; shift integer shift instructions
355 ;; slt set less than instructions
356 ;; signext sign extend instructions
357 ;; clz the clz and clo instructions
358 ;; pop the pop instruction
359 ;; trap trap if instructions
360 ;; imul integer multiply 2 operands
361 ;; imul3 integer multiply 3 operands
362 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
363 ;; imadd integer multiply-add
364 ;; idiv integer divide 2 operands
365 ;; idiv3 integer divide 3 operands
366 ;; move integer register move ({,D}ADD{,U} with rt = 0)
367 ;; fmove floating point register move
368 ;; fadd floating point add/subtract
369 ;; fmul floating point multiply
370 ;; fmadd floating point multiply-add
371 ;; fdiv floating point divide
372 ;; frdiv floating point reciprocal divide
373 ;; frdiv1 floating point reciprocal divide step 1
374 ;; frdiv2 floating point reciprocal divide step 2
375 ;; fabs floating point absolute value
376 ;; fneg floating point negation
377 ;; fcmp floating point compare
378 ;; fcvt floating point convert
379 ;; fsqrt floating point square root
380 ;; frsqrt floating point reciprocal square root
381 ;; frsqrt1 floating point reciprocal square root step1
382 ;; frsqrt2 floating point reciprocal square root step2
383 ;; multi multiword sequence (or user asm statements)
385 ;; ghost an instruction that produces no real code
387 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
388 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
389 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
390 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
391 frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
392 (cond [(eq_attr "jal" "!unset") (const_string "call")
393 (eq_attr "got" "load") (const_string "load")
395 ;; If a doubleword move uses these expensive instructions,
396 ;; it is usually better to schedule them in the same way
397 ;; as the singleword form, rather than as "multi".
398 (eq_attr "move_type" "load") (const_string "load")
399 (eq_attr "move_type" "fpload") (const_string "fpload")
400 (eq_attr "move_type" "store") (const_string "store")
401 (eq_attr "move_type" "fpstore") (const_string "fpstore")
402 (eq_attr "move_type" "mtc") (const_string "mtc")
403 (eq_attr "move_type" "mfc") (const_string "mfc")
404 (eq_attr "move_type" "mthilo") (const_string "mthilo")
405 (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
407 ;; These types of move are always single insns.
408 (eq_attr "move_type" "fmove") (const_string "fmove")
409 (eq_attr "move_type" "loadpool") (const_string "load")
410 (eq_attr "move_type" "signext") (const_string "signext")
411 (eq_attr "move_type" "sll0") (const_string "shift")
412 (eq_attr "move_type" "andi") (const_string "logical")
414 ;; These types of move are always split.
415 (eq_attr "move_type" "constN,shift_shift")
416 (const_string "multi")
418 ;; These types of move are split for doubleword modes only.
419 (and (eq_attr "move_type" "move,const")
420 (eq_attr "dword_mode" "yes"))
421 (const_string "multi")
422 (eq_attr "move_type" "move") (const_string "move")
423 (eq_attr "move_type" "const") (const_string "const")]
424 ;; We classify "lui_movf" as "unknown" rather than "multi"
425 ;; because we don't split it. FIXME: we should split instead.
426 (const_string "unknown")))
428 ;; Mode for conversion types (fcvt)
429 ;; I2S integer to float single (SI/DI to SF)
430 ;; I2D integer to float double (SI/DI to DF)
431 ;; S2I float to integer (SF to SI/DI)
432 ;; D2I float to integer (DF to SI/DI)
433 ;; D2S double to float single
434 ;; S2D float single to double
436 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
437 (const_string "unknown"))
439 ;; Is this an extended instruction in mips16 mode?
440 (define_attr "extended_mips16" "no,yes"
441 (if_then_else (ior (eq_attr "move_type" "sll0")
442 (eq_attr "type" "branch")
443 (eq_attr "jal" "direct"))
445 (const_string "no")))
447 ;; Length of instruction in bytes.
448 (define_attr "length" ""
449 (cond [(and (eq_attr "extended_mips16" "yes")
450 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
453 ;; Direct branch instructions have a range of [-0x40000,0x3fffc].
454 ;; If a branch is outside this range, we have a choice of two
455 ;; sequences. For PIC, an out-of-range branch like:
460 ;; becomes the equivalent of:
469 ;; where the load address can be up to three instructions long
472 ;; The non-PIC case is similar except that we use a direct
473 ;; jump instead of an la/jr pair. Since the target of this
474 ;; jump is an absolute 28-bit bit address (the other bits
475 ;; coming from the address of the delay slot) this form cannot
476 ;; cross a 256MB boundary. We could provide the option of
477 ;; using la/jr in this case too, but we do not do so at
480 ;; Note that this value does not account for the delay slot
481 ;; instruction, whose length is added separately. If the RTL
482 ;; pattern has no explicit delay slot, mips_adjust_insn_length
483 ;; will add the length of the implicit nop. The values for
484 ;; forward and backward branches will be different as well.
485 (eq_attr "type" "branch")
486 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
487 (le (minus (pc) (match_dup 1)) (const_int 131068)))
489 (ne (symbol_ref "flag_pic") (const_int 0))
493 ;; "Ghost" instructions occupy no space.
494 (eq_attr "type" "ghost")
497 (eq_attr "got" "load")
498 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
501 (eq_attr "got" "xgot_high")
504 ;; In general, constant-pool loads are extended instructions.
505 (eq_attr "move_type" "loadpool")
508 ;; LUI_MOVFs are decomposed into two separate instructions.
509 (eq_attr "move_type" "lui_movf")
512 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
513 ;; They are extended instructions on MIPS16 targets.
514 (eq_attr "move_type" "shift_shift")
515 (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
519 ;; Check for doubleword moves that are decomposed into two
521 (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
522 (eq_attr "dword_mode" "yes"))
525 ;; Doubleword CONST{,N} moves are split into two word
527 (and (eq_attr "move_type" "const,constN")
528 (eq_attr "dword_mode" "yes"))
529 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
531 ;; Otherwise, constants, loads and stores are handled by external
533 (eq_attr "move_type" "const,constN")
534 (symbol_ref "mips_const_insns (operands[1]) * 4")
535 (eq_attr "move_type" "load,fpload")
536 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
537 (eq_attr "move_type" "store,fpstore")
538 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
540 ;; In the worst case, a call macro will take 8 instructions:
542 ;; lui $25,%call_hi(FOO)
544 ;; lw $25,%call_lo(FOO)($25)
550 (eq_attr "jal_macro" "yes")
553 ;; Various VR4120 errata require a nop to be inserted after a macc
554 ;; instruction. The assembler does this for us, so account for
555 ;; the worst-case length here.
556 (and (eq_attr "type" "imadd")
557 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
560 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
561 ;; the result of the second one is missed. The assembler should work
562 ;; around this by inserting a nop after the first dmult.
563 (and (eq_attr "type" "imul,imul3")
564 (and (eq_attr "mode" "DI")
565 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
568 (eq_attr "type" "idiv,idiv3")
569 (symbol_ref "mips_idiv_insns () * 4")
572 ;; Attribute describing the processor. This attribute must match exactly
573 ;; with the processor_type enumeration in mips.h.
575 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
576 (const (symbol_ref "mips_tune_attr")))
578 ;; The type of hardware hazard associated with this instruction.
579 ;; DELAY means that the next instruction cannot read the result
580 ;; of this one. HILO means that the next two instructions cannot
581 ;; write to HI or LO.
582 (define_attr "hazard" "none,delay,hilo"
583 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
584 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
585 (const_string "delay")
587 (and (eq_attr "type" "mfc,mtc")
588 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
589 (const_string "delay")
591 (and (eq_attr "type" "fcmp")
592 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
593 (const_string "delay")
595 ;; The r4000 multiplication patterns include an mflo instruction.
596 (and (eq_attr "type" "imul")
597 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
598 (const_string "hilo")
600 (and (eq_attr "type" "mfhilo")
601 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
602 (const_string "hilo")]
603 (const_string "none")))
605 ;; Is it a single instruction?
606 (define_attr "single_insn" "no,yes"
607 (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
608 ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
610 ;; Can the instruction be put into a delay slot?
611 (define_attr "can_delay" "no,yes"
612 (if_then_else (and (eq_attr "type" "!branch,call,jump")
613 (and (eq_attr "hazard" "none")
614 (eq_attr "single_insn" "yes")))
616 (const_string "no")))
618 ;; Attribute defining whether or not we can use the branch-likely
620 (define_attr "branch_likely" "no,yes"
621 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
623 (const_string "no")))
625 ;; True if an instruction might assign to hi or lo when reloaded.
626 ;; This is used by the TUNE_MACC_CHAINS code.
627 (define_attr "may_clobber_hilo" "no,yes"
628 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
630 (const_string "no")))
632 ;; Describe a user's asm statement.
633 (define_asm_attributes
634 [(set_attr "type" "multi")
635 (set_attr "can_delay" "no")])
637 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
638 ;; from the same template.
639 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
641 ;; A copy of GPR that can be used when a pattern has two independent
643 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
645 ;; This mode iterator allows :HILO to be used as the mode of the
646 ;; concatenated HI and LO registers.
647 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
649 ;; This mode iterator allows :P to be used for patterns that operate on
650 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
651 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
653 ;; This mode iterator allows :MOVECC to be used anywhere that a
654 ;; conditional-move-type condition is needed.
655 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
656 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
658 ;; 32-bit integer moves for which we provide move patterns.
659 (define_mode_iterator IMOVE32
668 (V4UQQ "TARGET_DSP")])
670 ;; 64-bit modes for which we provide move patterns.
671 (define_mode_iterator MOVE64
673 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
674 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
675 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
676 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
678 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
679 (define_mode_iterator MOVE128 [TI TF])
681 ;; This mode iterator allows the QI and HI extension patterns to be
682 ;; defined from the same template.
683 (define_mode_iterator SHORT [QI HI])
685 ;; Likewise the 64-bit truncate-and-shift patterns.
686 (define_mode_iterator SUBDI [QI HI SI])
688 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
689 ;; floating-point mode is allowed.
690 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
691 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
692 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
694 ;; Like ANYF, but only applies to scalar modes.
695 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
696 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
698 ;; A floating-point mode for which moves involving FPRs may need to be split.
699 (define_mode_iterator SPLITF
700 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
701 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
702 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
703 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
704 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
705 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
706 (TF "TARGET_64BIT && TARGET_FLOAT64")])
708 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
709 ;; 32-bit version and "dsubu" in the 64-bit version.
710 (define_mode_attr d [(SI "") (DI "d")
711 (QQ "") (HQ "") (SQ "") (DQ "d")
712 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
713 (HA "") (SA "") (DA "d")
714 (UHA "") (USA "") (UDA "d")])
716 ;; Same as d but upper-case.
717 (define_mode_attr D [(SI "") (DI "D")
718 (QQ "") (HQ "") (SQ "") (DQ "D")
719 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
720 (HA "") (SA "") (DA "D")
721 (UHA "") (USA "") (UDA "D")])
723 ;; This attribute gives the length suffix for a sign- or zero-extension
725 (define_mode_attr size [(QI "b") (HI "h")])
727 ;; This attributes gives the mode mask of a SHORT.
728 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
730 ;; Mode attributes for GPR loads and stores.
731 (define_mode_attr load [(SI "lw") (DI "ld")])
732 (define_mode_attr store [(SI "sw") (DI "sd")])
734 ;; Similarly for MIPS IV indexed FPR loads and stores.
735 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
736 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
738 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
739 ;; are different. Some forms of unextended addiu have an 8-bit immediate
740 ;; field but the equivalent daddiu has only a 5-bit field.
741 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
743 ;; This attribute gives the best constraint to use for registers of
745 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
747 ;; This attribute gives the format suffix for floating-point operations.
748 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
750 ;; This attribute gives the upper-case mode name for one unit of a
751 ;; floating-point mode.
752 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
754 ;; This attribute gives the integer mode that has the same size as a
756 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
757 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
758 (HA "HI") (SA "SI") (DA "DI")
759 (UHA "HI") (USA "SI") (UDA "DI")
760 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
761 (V2HQ "SI") (V2HA "SI")])
763 ;; This attribute gives the integer mode that has half the size of
764 ;; the controlling mode.
765 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
766 (V2SI "SI") (V4HI "SI") (V8QI "SI")
769 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
771 ;; In certain cases, div.s and div.ps may have a rounding error
772 ;; and/or wrong inexact flag.
774 ;; Therefore, we only allow div.s if not working around SB-1 rev2
775 ;; errata or if a slight loss of precision is OK.
776 (define_mode_attr divide_condition
777 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
778 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
780 ;; This attribute gives the conditions under which SQRT.fmt instructions
782 (define_mode_attr sqrt_condition
783 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
785 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
786 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
787 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
788 ;; so for safety's sake, we apply this restriction to all targets.
789 (define_mode_attr recip_condition
791 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
792 (V2SF "TARGET_SB1")])
794 ;; This code iterator allows signed and unsigned widening multiplications
795 ;; to use the same template.
796 (define_code_iterator any_extend [sign_extend zero_extend])
798 ;; This code iterator allows the two right shift instructions to be
799 ;; generated from the same template.
800 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
802 ;; This code iterator allows the three shift instructions to be generated
803 ;; from the same template.
804 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
806 ;; This code iterator allows unsigned and signed division to be generated
807 ;; from the same template.
808 (define_code_iterator any_div [div udiv])
810 ;; This code iterator allows unsigned and signed modulus to be generated
811 ;; from the same template.
812 (define_code_iterator any_mod [mod umod])
814 ;; This code iterator allows all native floating-point comparisons to be
815 ;; generated from the same template.
816 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
818 ;; This code iterator is used for comparisons that can be implemented
819 ;; by swapping the operands.
820 (define_code_iterator swapped_fcond [ge gt unge ungt])
822 ;; Equality operators.
823 (define_code_iterator equality_op [eq ne])
825 ;; These code iterators allow the signed and unsigned scc operations to use
826 ;; the same template.
827 (define_code_iterator any_gt [gt gtu])
828 (define_code_iterator any_ge [ge geu])
829 (define_code_iterator any_lt [lt ltu])
830 (define_code_iterator any_le [le leu])
832 ;; <u> expands to an empty string when doing a signed operation and
833 ;; "u" when doing an unsigned operation.
834 (define_code_attr u [(sign_extend "") (zero_extend "u")
842 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
843 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
845 ;; <optab> expands to the name of the optab for a particular code.
846 (define_code_attr optab [(ashift "ashl")
855 ;; <insn> expands to the name of the insn that implements a particular code.
856 (define_code_attr insn [(ashift "sll")
865 ;; <immediate_insn> expands to the name of the insn that implements
866 ;; a particular code to operate on immediate values.
867 (define_code_attr immediate_insn [(ior "ori")
871 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
872 (define_code_attr fcond [(unordered "un")
880 ;; Similar, but for swapped conditions.
881 (define_code_attr swapped_fcond [(ge "le")
886 ;; The value of the bit when the branch is taken for branch_bit patterns.
887 ;; Comparison is always against zero so this depends on the operator.
888 (define_code_attr bbv [(eq "0") (ne "1")])
890 ;; This is the inverse value of bbv.
891 (define_code_attr bbinv [(eq "1") (ne "0")])
893 ;; .........................
895 ;; Branch, call and jump delay slots
897 ;; .........................
899 (define_delay (and (eq_attr "type" "branch")
900 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
901 (eq_attr "branch_likely" "yes"))
902 [(eq_attr "can_delay" "yes")
904 (eq_attr "can_delay" "yes")])
906 ;; Branches that don't have likely variants do not annul on false.
907 (define_delay (and (eq_attr "type" "branch")
908 (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
909 (eq_attr "branch_likely" "no"))
910 [(eq_attr "can_delay" "yes")
914 (define_delay (eq_attr "type" "jump")
915 [(eq_attr "can_delay" "yes")
919 (define_delay (and (eq_attr "type" "call")
920 (eq_attr "jal_macro" "no"))
921 [(eq_attr "can_delay" "yes")
925 ;; Pipeline descriptions.
927 ;; generic.md provides a fallback for processors without a specific
928 ;; pipeline description. It is derived from the old define_function_unit
929 ;; version and uses the "alu" and "imuldiv" units declared below.
931 ;; Some of the processor-specific files are also derived from old
932 ;; define_function_unit descriptions and simply override the parts of
933 ;; generic.md that don't apply. The other processor-specific files
934 ;; are self-contained.
935 (define_automaton "alu,imuldiv")
937 (define_cpu_unit "alu" "alu")
938 (define_cpu_unit "imuldiv" "imuldiv")
940 ;; Ghost instructions produce no real code and introduce no hazards.
941 ;; They exist purely to express an effect on dataflow.
942 (define_insn_reservation "ghost" 0
943 (eq_attr "type" "ghost")
964 (include "loongson2ef.md")
965 (include "octeon.md")
969 (include "generic.md")
972 ;; ....................
976 ;; ....................
980 [(trap_if (const_int 1) (const_int 0))]
983 if (ISA_HAS_COND_TRAP)
985 else if (TARGET_MIPS16)
990 [(set_attr "type" "trap")])
992 (define_expand "ctrap<mode>4"
993 [(trap_if (match_operator 0 "comparison_operator"
994 [(match_operand:GPR 1 "reg_or_0_operand")
995 (match_operand:GPR 2 "arith_operand")])
996 (match_operand 3 "const_0_operand"))]
999 mips_expand_conditional_trap (operands[0]);
1003 (define_insn "*conditional_trap<mode>"
1004 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1005 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1006 (match_operand:GPR 2 "arith_operand" "dI")])
1010 [(set_attr "type" "trap")])
1013 ;; ....................
1017 ;; ....................
1020 (define_insn "add<mode>3"
1021 [(set (match_operand:ANYF 0 "register_operand" "=f")
1022 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1023 (match_operand:ANYF 2 "register_operand" "f")))]
1025 "add.<fmt>\t%0,%1,%2"
1026 [(set_attr "type" "fadd")
1027 (set_attr "mode" "<UNITMODE>")])
1029 (define_expand "add<mode>3"
1030 [(set (match_operand:GPR 0 "register_operand")
1031 (plus:GPR (match_operand:GPR 1 "register_operand")
1032 (match_operand:GPR 2 "arith_operand")))]
1035 (define_insn "*add<mode>3"
1036 [(set (match_operand:GPR 0 "register_operand" "=d,d")
1037 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
1038 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1043 [(set_attr "type" "arith")
1044 (set_attr "mode" "<MODE>")])
1046 (define_insn "*add<mode>3_mips16"
1047 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1048 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1049 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1057 [(set_attr "type" "arith")
1058 (set_attr "mode" "<MODE>")
1059 (set_attr_alternative "length"
1060 [(if_then_else (match_operand 2 "m16_simm8_8")
1063 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1066 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1069 (if_then_else (match_operand 2 "m16_simm4_1")
1074 ;; On the mips16, we can sometimes split an add of a constant which is
1075 ;; a 4 byte instruction into two adds which are both 2 byte
1076 ;; instructions. There are two cases: one where we are adding a
1077 ;; constant plus a register to another register, and one where we are
1078 ;; simply adding a constant to a register.
1081 [(set (match_operand:SI 0 "d_operand")
1082 (plus:SI (match_dup 0)
1083 (match_operand:SI 1 "const_int_operand")))]
1084 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1085 && ((INTVAL (operands[1]) > 0x7f
1086 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1087 || (INTVAL (operands[1]) < - 0x80
1088 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1089 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1090 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1092 HOST_WIDE_INT val = INTVAL (operands[1]);
1096 operands[1] = GEN_INT (0x7f);
1097 operands[2] = GEN_INT (val - 0x7f);
1101 operands[1] = GEN_INT (- 0x80);
1102 operands[2] = GEN_INT (val + 0x80);
1107 [(set (match_operand:SI 0 "d_operand")
1108 (plus:SI (match_operand:SI 1 "d_operand")
1109 (match_operand:SI 2 "const_int_operand")))]
1110 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1111 && REGNO (operands[0]) != REGNO (operands[1])
1112 && ((INTVAL (operands[2]) > 0x7
1113 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1114 || (INTVAL (operands[2]) < - 0x8
1115 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1116 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1117 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1119 HOST_WIDE_INT val = INTVAL (operands[2]);
1123 operands[2] = GEN_INT (0x7);
1124 operands[3] = GEN_INT (val - 0x7);
1128 operands[2] = GEN_INT (- 0x8);
1129 operands[3] = GEN_INT (val + 0x8);
1134 [(set (match_operand:DI 0 "d_operand")
1135 (plus:DI (match_dup 0)
1136 (match_operand:DI 1 "const_int_operand")))]
1137 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1138 && ((INTVAL (operands[1]) > 0xf
1139 && INTVAL (operands[1]) <= 0xf + 0xf)
1140 || (INTVAL (operands[1]) < - 0x10
1141 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1142 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1143 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1145 HOST_WIDE_INT val = INTVAL (operands[1]);
1149 operands[1] = GEN_INT (0xf);
1150 operands[2] = GEN_INT (val - 0xf);
1154 operands[1] = GEN_INT (- 0x10);
1155 operands[2] = GEN_INT (val + 0x10);
1160 [(set (match_operand:DI 0 "d_operand")
1161 (plus:DI (match_operand:DI 1 "d_operand")
1162 (match_operand:DI 2 "const_int_operand")))]
1163 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1164 && REGNO (operands[0]) != REGNO (operands[1])
1165 && ((INTVAL (operands[2]) > 0x7
1166 && INTVAL (operands[2]) <= 0x7 + 0xf)
1167 || (INTVAL (operands[2]) < - 0x8
1168 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1169 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1170 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1172 HOST_WIDE_INT val = INTVAL (operands[2]);
1176 operands[2] = GEN_INT (0x7);
1177 operands[3] = GEN_INT (val - 0x7);
1181 operands[2] = GEN_INT (- 0x8);
1182 operands[3] = GEN_INT (val + 0x8);
1186 (define_insn "*addsi3_extended"
1187 [(set (match_operand:DI 0 "register_operand" "=d,d")
1189 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1190 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1191 "TARGET_64BIT && !TARGET_MIPS16"
1195 [(set_attr "type" "arith")
1196 (set_attr "mode" "SI")])
1198 ;; Split this insn so that the addiu splitters can have a crack at it.
1199 ;; Use a conservative length estimate until the split.
1200 (define_insn_and_split "*addsi3_extended_mips16"
1201 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1203 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1204 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1205 "TARGET_64BIT && TARGET_MIPS16"
1207 "&& reload_completed"
1208 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1209 { operands[3] = gen_lowpart (SImode, operands[0]); }
1210 [(set_attr "type" "arith")
1211 (set_attr "mode" "SI")
1212 (set_attr "extended_mips16" "yes")])
1214 ;; Combiner patterns for unsigned byte-add.
1216 (define_insn "*baddu_si_eb"
1217 [(set (match_operand:SI 0 "register_operand" "=d")
1220 (plus:SI (match_operand:SI 1 "register_operand" "d")
1221 (match_operand:SI 2 "register_operand" "d")) 3)))]
1222 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1224 [(set_attr "type" "arith")])
1226 (define_insn "*baddu_si_el"
1227 [(set (match_operand:SI 0 "register_operand" "=d")
1230 (plus:SI (match_operand:SI 1 "register_operand" "d")
1231 (match_operand:SI 2 "register_operand" "d")) 0)))]
1232 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1234 [(set_attr "type" "arith")])
1236 (define_insn "*baddu_di<mode>"
1237 [(set (match_operand:GPR 0 "register_operand" "=d")
1240 (plus:DI (match_operand:DI 1 "register_operand" "d")
1241 (match_operand:DI 2 "register_operand" "d")))))]
1242 "ISA_HAS_BADDU && TARGET_64BIT"
1244 [(set_attr "type" "arith")])
1247 ;; ....................
1251 ;; ....................
1254 (define_insn "sub<mode>3"
1255 [(set (match_operand:ANYF 0 "register_operand" "=f")
1256 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1257 (match_operand:ANYF 2 "register_operand" "f")))]
1259 "sub.<fmt>\t%0,%1,%2"
1260 [(set_attr "type" "fadd")
1261 (set_attr "mode" "<UNITMODE>")])
1263 (define_insn "sub<mode>3"
1264 [(set (match_operand:GPR 0 "register_operand" "=d")
1265 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1266 (match_operand:GPR 2 "register_operand" "d")))]
1269 [(set_attr "type" "arith")
1270 (set_attr "mode" "<MODE>")])
1272 (define_insn "*subsi3_extended"
1273 [(set (match_operand:DI 0 "register_operand" "=d")
1275 (minus:SI (match_operand:SI 1 "register_operand" "d")
1276 (match_operand:SI 2 "register_operand" "d"))))]
1279 [(set_attr "type" "arith")
1280 (set_attr "mode" "DI")])
1283 ;; ....................
1287 ;; ....................
1290 (define_expand "mul<mode>3"
1291 [(set (match_operand:SCALARF 0 "register_operand")
1292 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1293 (match_operand:SCALARF 2 "register_operand")))]
1297 (define_insn "*mul<mode>3"
1298 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1299 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1300 (match_operand:SCALARF 2 "register_operand" "f")))]
1301 "!TARGET_4300_MUL_FIX"
1302 "mul.<fmt>\t%0,%1,%2"
1303 [(set_attr "type" "fmul")
1304 (set_attr "mode" "<MODE>")])
1306 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1307 ;; operands may corrupt immediately following multiplies. This is a
1308 ;; simple fix to insert NOPs.
1310 (define_insn "*mul<mode>3_r4300"
1311 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1312 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1313 (match_operand:SCALARF 2 "register_operand" "f")))]
1314 "TARGET_4300_MUL_FIX"
1315 "mul.<fmt>\t%0,%1,%2\;nop"
1316 [(set_attr "type" "fmul")
1317 (set_attr "mode" "<MODE>")
1318 (set_attr "length" "8")])
1320 (define_insn "mulv2sf3"
1321 [(set (match_operand:V2SF 0 "register_operand" "=f")
1322 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1323 (match_operand:V2SF 2 "register_operand" "f")))]
1324 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1326 [(set_attr "type" "fmul")
1327 (set_attr "mode" "SF")])
1329 ;; The original R4000 has a cpu bug. If a double-word or a variable
1330 ;; shift executes while an integer multiplication is in progress, the
1331 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1332 ;; with the mult on the R4000.
1334 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1335 ;; (also valid for MIPS R4000MC processors):
1337 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1338 ;; this errata description.
1339 ;; The following code sequence causes the R4000 to incorrectly
1340 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1341 ;; instruction. If the dsra32 instruction is executed during an
1342 ;; integer multiply, the dsra32 will only shift by the amount in
1343 ;; specified in the instruction rather than the amount plus 32
1345 ;; instruction 1: mult rs,rt integer multiply
1346 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1347 ;; right arithmetic + 32
1348 ;; Workaround: A dsra32 instruction placed after an integer
1349 ;; multiply should not be one of the 11 instructions after the
1350 ;; multiply instruction."
1354 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1355 ;; the following description.
1356 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1357 ;; 64-bit versions) may produce incorrect results under the
1358 ;; following conditions:
1359 ;; 1) An integer multiply is currently executing
1360 ;; 2) These types of shift instructions are executed immediately
1361 ;; following an integer divide instruction.
1363 ;; 1) Make sure no integer multiply is running wihen these
1364 ;; instruction are executed. If this cannot be predicted at
1365 ;; compile time, then insert a "mfhi" to R0 instruction
1366 ;; immediately after the integer multiply instruction. This
1367 ;; will cause the integer multiply to complete before the shift
1369 ;; 2) Separate integer divide and these two classes of shift
1370 ;; instructions by another instruction or a noop."
1372 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1375 (define_expand "mul<mode>3"
1376 [(set (match_operand:GPR 0 "register_operand")
1377 (mult:GPR (match_operand:GPR 1 "register_operand")
1378 (match_operand:GPR 2 "register_operand")))]
1381 if (TARGET_LOONGSON_2EF)
1382 emit_insn (gen_mul<mode>3_mul3_ls2ef (operands[0], operands[1],
1384 else if (ISA_HAS_<D>MUL3)
1385 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1386 else if (TARGET_FIX_R4000)
1387 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1390 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1394 (define_insn "mul<mode>3_mul3_ls2ef"
1395 [(set (match_operand:GPR 0 "register_operand" "=d")
1396 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1397 (match_operand:GPR 2 "register_operand" "d")))]
1398 "TARGET_LOONGSON_2EF"
1399 "<d>multu.g\t%0,%1,%2"
1400 [(set_attr "type" "imul3nc")
1401 (set_attr "mode" "<MODE>")])
1403 (define_insn "mul<mode>3_mul3"
1404 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1405 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1406 (match_operand:GPR 2 "register_operand" "d,d")))
1407 (clobber (match_scratch:GPR 3 "=l,X"))]
1410 if (which_alternative == 1)
1411 return "<d>mult\t%1,%2";
1412 if (<MODE>mode == SImode && TARGET_MIPS3900)
1413 return "mult\t%0,%1,%2";
1414 return "<d>mul\t%0,%1,%2";
1416 [(set_attr "type" "imul3,imul")
1417 (set_attr "mode" "<MODE>")])
1419 ;; If a register gets allocated to LO, and we spill to memory, the reload
1420 ;; will include a move from LO to a GPR. Merge it into the multiplication
1421 ;; if it can set the GPR directly.
1424 ;; Operand 1: GPR (1st multiplication operand)
1425 ;; Operand 2: GPR (2nd multiplication operand)
1426 ;; Operand 3: GPR (destination)
1429 [(set (match_operand:SI 0 "lo_operand")
1430 (mult:SI (match_operand:SI 1 "d_operand")
1431 (match_operand:SI 2 "d_operand")))
1432 (clobber (scratch:SI))])
1433 (set (match_operand:SI 3 "d_operand")
1435 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1438 (mult:SI (match_dup 1)
1440 (clobber (match_dup 0))])])
1442 (define_insn "mul<mode>3_internal"
1443 [(set (match_operand:GPR 0 "register_operand" "=l")
1444 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1445 (match_operand:GPR 2 "register_operand" "d")))]
1448 [(set_attr "type" "imul")
1449 (set_attr "mode" "<MODE>")])
1451 (define_insn "mul<mode>3_r4000"
1452 [(set (match_operand:GPR 0 "register_operand" "=d")
1453 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1454 (match_operand:GPR 2 "register_operand" "d")))
1455 (clobber (match_scratch:GPR 3 "=l"))]
1457 "<d>mult\t%1,%2\;mflo\t%0"
1458 [(set_attr "type" "imul")
1459 (set_attr "mode" "<MODE>")
1460 (set_attr "length" "8")])
1462 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1463 ;; of "mult; mflo". They have the same latency, but the first form gives
1464 ;; us an extra cycle to compute the operands.
1467 ;; Operand 1: GPR (1st multiplication operand)
1468 ;; Operand 2: GPR (2nd multiplication operand)
1469 ;; Operand 3: GPR (destination)
1471 [(set (match_operand:SI 0 "lo_operand")
1472 (mult:SI (match_operand:SI 1 "d_operand")
1473 (match_operand:SI 2 "d_operand")))
1474 (set (match_operand:SI 3 "d_operand")
1476 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1481 (plus:SI (mult:SI (match_dup 1)
1485 (plus:SI (mult:SI (match_dup 1)
1489 ;; Multiply-accumulate patterns
1491 ;; This pattern is first matched by combine, which tries to use the
1492 ;; pattern wherever it can. We don't know until later whether it
1493 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1494 ;; so we need to keep both options open.
1496 ;; The second alternative has a "?" marker because it is generally
1497 ;; one instruction more costly than the first alternative. This "?"
1498 ;; marker is enough to convey the relative costs to the register
1501 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1502 ;; reloads of the other operands, even though operands 4 and 5 need no
1503 ;; copy instructions. Reload therefore thinks that the second alternative
1504 ;; is two reloads more costly than the first. We add "*?*?" to the first
1505 ;; alternative as a counterweight.
1506 (define_insn "*mul_acc_si"
1507 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1508 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1509 (match_operand:SI 2 "register_operand" "d,d"))
1510 (match_operand:SI 3 "register_operand" "0,d")))
1511 (clobber (match_scratch:SI 4 "=X,l"))
1512 (clobber (match_scratch:SI 5 "=X,&d"))]
1513 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1517 [(set_attr "type" "imadd")
1518 (set_attr "mode" "SI")
1519 (set_attr "length" "4,8")])
1521 ;; The same idea applies here. The middle alternative needs one less
1522 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1523 (define_insn "*mul_acc_si_r3900"
1524 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1525 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1526 (match_operand:SI 2 "register_operand" "d,d,d"))
1527 (match_operand:SI 3 "register_operand" "0,l,d")))
1528 (clobber (match_scratch:SI 4 "=X,3,l"))
1529 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1530 "TARGET_MIPS3900 && !TARGET_MIPS16"
1535 [(set_attr "type" "imadd")
1536 (set_attr "mode" "SI")
1537 (set_attr "length" "4,4,8")])
1539 ;; Split *mul_acc_si if both the source and destination accumulator
1542 [(set (match_operand:SI 0 "d_operand")
1543 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1544 (match_operand:SI 2 "d_operand"))
1545 (match_operand:SI 3 "d_operand")))
1546 (clobber (match_operand:SI 4 "lo_operand"))
1547 (clobber (match_operand:SI 5 "d_operand"))]
1549 [(parallel [(set (match_dup 5)
1550 (mult:SI (match_dup 1) (match_dup 2)))
1551 (clobber (match_dup 4))])
1552 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1555 (define_insn "*macc"
1556 [(set (match_operand:SI 0 "register_operand" "=l,d")
1557 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1558 (match_operand:SI 2 "register_operand" "d,d"))
1559 (match_operand:SI 3 "register_operand" "0,l")))
1560 (clobber (match_scratch:SI 4 "=X,3"))]
1563 if (which_alternative == 1)
1564 return "macc\t%0,%1,%2";
1565 else if (TARGET_MIPS5500)
1566 return "madd\t%1,%2";
1568 /* The VR4130 assumes that there is a two-cycle latency between a macc
1569 that "writes" to $0 and an instruction that reads from it. We avoid
1570 this by assigning to $1 instead. */
1571 return "%[macc\t%@,%1,%2%]";
1573 [(set_attr "type" "imadd")
1574 (set_attr "mode" "SI")])
1576 (define_insn "*msac"
1577 [(set (match_operand:SI 0 "register_operand" "=l,d")
1578 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1579 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1580 (match_operand:SI 3 "register_operand" "d,d"))))
1581 (clobber (match_scratch:SI 4 "=X,1"))]
1584 if (which_alternative == 1)
1585 return "msac\t%0,%2,%3";
1586 else if (TARGET_MIPS5500)
1587 return "msub\t%2,%3";
1589 return "msac\t$0,%2,%3";
1591 [(set_attr "type" "imadd")
1592 (set_attr "mode" "SI")])
1594 ;; An msac-like instruction implemented using negation and a macc.
1595 (define_insn_and_split "*msac_using_macc"
1596 [(set (match_operand:SI 0 "register_operand" "=l,d")
1597 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1598 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1599 (match_operand:SI 3 "register_operand" "d,d"))))
1600 (clobber (match_scratch:SI 4 "=X,1"))
1601 (clobber (match_scratch:SI 5 "=d,d"))]
1602 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1604 "&& reload_completed"
1606 (neg:SI (match_dup 3)))
1609 (plus:SI (mult:SI (match_dup 2)
1612 (clobber (match_dup 4))])]
1614 [(set_attr "type" "imadd")
1615 (set_attr "length" "8")])
1617 ;; Patterns generated by the define_peephole2 below.
1619 (define_insn "*macc2"
1620 [(set (match_operand:SI 0 "register_operand" "=l")
1621 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1622 (match_operand:SI 2 "register_operand" "d"))
1624 (set (match_operand:SI 3 "register_operand" "=d")
1625 (plus:SI (mult:SI (match_dup 1)
1628 "ISA_HAS_MACC && reload_completed"
1630 [(set_attr "type" "imadd")
1631 (set_attr "mode" "SI")])
1633 (define_insn "*msac2"
1634 [(set (match_operand:SI 0 "register_operand" "=l")
1635 (minus:SI (match_dup 0)
1636 (mult:SI (match_operand:SI 1 "register_operand" "d")
1637 (match_operand:SI 2 "register_operand" "d"))))
1638 (set (match_operand:SI 3 "register_operand" "=d")
1639 (minus:SI (match_dup 0)
1640 (mult:SI (match_dup 1)
1642 "ISA_HAS_MSAC && reload_completed"
1644 [(set_attr "type" "imadd")
1645 (set_attr "mode" "SI")])
1647 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1651 ;; Operand 1: macc/msac
1652 ;; Operand 2: GPR (destination)
1655 [(set (match_operand:SI 0 "lo_operand")
1656 (match_operand:SI 1 "macc_msac_operand"))
1657 (clobber (scratch:SI))])
1658 (set (match_operand:SI 2 "d_operand")
1661 [(parallel [(set (match_dup 0)
1666 ;; When we have a three-address multiplication instruction, it should
1667 ;; be faster to do a separate multiply and add, rather than moving
1668 ;; something into LO in order to use a macc instruction.
1670 ;; This peephole needs a scratch register to cater for the case when one
1671 ;; of the multiplication operands is the same as the destination.
1673 ;; Operand 0: GPR (scratch)
1675 ;; Operand 2: GPR (addend)
1676 ;; Operand 3: GPR (destination)
1677 ;; Operand 4: macc/msac
1678 ;; Operand 5: new multiplication
1679 ;; Operand 6: new addition/subtraction
1681 [(match_scratch:SI 0 "d")
1682 (set (match_operand:SI 1 "lo_operand")
1683 (match_operand:SI 2 "d_operand"))
1686 [(set (match_operand:SI 3 "d_operand")
1687 (match_operand:SI 4 "macc_msac_operand"))
1688 (clobber (match_dup 1))])]
1689 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1690 [(parallel [(set (match_dup 0)
1692 (clobber (match_dup 1))])
1696 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1697 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1698 operands[2], operands[0]);
1701 ;; Same as above, except LO is the initial target of the macc.
1703 ;; Operand 0: GPR (scratch)
1705 ;; Operand 2: GPR (addend)
1706 ;; Operand 3: macc/msac
1707 ;; Operand 4: GPR (destination)
1708 ;; Operand 5: new multiplication
1709 ;; Operand 6: new addition/subtraction
1711 [(match_scratch:SI 0 "d")
1712 (set (match_operand:SI 1 "lo_operand")
1713 (match_operand:SI 2 "d_operand"))
1717 (match_operand:SI 3 "macc_msac_operand"))
1718 (clobber (scratch:SI))])
1720 (set (match_operand:SI 4 "d_operand")
1722 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1723 [(parallel [(set (match_dup 0)
1725 (clobber (match_dup 1))])
1729 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1730 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1731 operands[2], operands[0]);
1734 ;; See the comment above *mul_add_si for details.
1735 (define_insn "*mul_sub_si"
1736 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1737 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1738 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1739 (match_operand:SI 3 "register_operand" "d,d"))))
1740 (clobber (match_scratch:SI 4 "=X,l"))
1741 (clobber (match_scratch:SI 5 "=X,&d"))]
1742 "GENERATE_MADD_MSUB"
1746 [(set_attr "type" "imadd")
1747 (set_attr "mode" "SI")
1748 (set_attr "length" "4,8")])
1750 ;; Split *mul_sub_si if both the source and destination accumulator
1753 [(set (match_operand:SI 0 "d_operand")
1754 (minus:SI (match_operand:SI 1 "d_operand")
1755 (mult:SI (match_operand:SI 2 "d_operand")
1756 (match_operand:SI 3 "d_operand"))))
1757 (clobber (match_operand:SI 4 "lo_operand"))
1758 (clobber (match_operand:SI 5 "d_operand"))]
1760 [(parallel [(set (match_dup 5)
1761 (mult:SI (match_dup 2) (match_dup 3)))
1762 (clobber (match_dup 4))])
1763 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1766 (define_insn "*muls"
1767 [(set (match_operand:SI 0 "register_operand" "=l,d")
1768 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1769 (match_operand:SI 2 "register_operand" "d,d"))))
1770 (clobber (match_scratch:SI 3 "=X,l"))]
1775 [(set_attr "type" "imul,imul3")
1776 (set_attr "mode" "SI")])
1778 (define_expand "<u>mulsidi3"
1779 [(set (match_operand:DI 0 "register_operand")
1780 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1781 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1782 "!TARGET_64BIT || !TARGET_FIX_R4000"
1785 emit_insn (gen_<u>mulsidi3_64bit (operands[0], operands[1], operands[2]));
1786 else if (TARGET_FIX_R4000)
1787 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1790 emit_insn (gen_<u>mulsidi3_32bit (operands[0], operands[1], operands[2]));
1794 (define_insn "<u>mulsidi3_32bit"
1795 [(set (match_operand:DI 0 "register_operand" "=x")
1796 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1797 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1798 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1800 [(set_attr "type" "imul")
1801 (set_attr "mode" "SI")])
1803 (define_insn "<u>mulsidi3_32bit_r4000"
1804 [(set (match_operand:DI 0 "register_operand" "=d")
1805 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1806 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1807 (clobber (match_scratch:DI 3 "=x"))]
1808 "!TARGET_64BIT && TARGET_FIX_R4000"
1809 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1810 [(set_attr "type" "imul")
1811 (set_attr "mode" "SI")
1812 (set_attr "length" "12")])
1814 (define_insn_and_split "<u>mulsidi3_64bit"
1815 [(set (match_operand:DI 0 "register_operand" "=d")
1816 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1817 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1818 (clobber (match_scratch:TI 3 "=x"))
1819 (clobber (match_scratch:DI 4 "=d"))]
1820 "TARGET_64BIT && !TARGET_FIX_R4000"
1822 "&& reload_completed"
1824 (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
1825 (any_extend:DI (match_dup 2)))]
1828 ;; OP4 <- LO, OP0 <- HI
1829 (set (match_dup 4) (match_dup 5))
1830 (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
1834 (ashift:DI (match_dup 4)
1837 (lshiftrt:DI (match_dup 4)
1840 ;; Shift OP0 into place.
1842 (ashift:DI (match_dup 0)
1845 ;; OR the two halves together
1847 (ior:DI (match_dup 0)
1849 { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
1850 [(set_attr "type" "imul")
1851 (set_attr "mode" "SI")
1852 (set_attr "length" "24")])
1854 (define_insn "<u>mulsidi3_64bit_hilo"
1855 [(set (match_operand:TI 0 "register_operand" "=x")
1858 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1859 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1861 "TARGET_64BIT && !TARGET_FIX_R4000"
1863 [(set_attr "type" "imul")
1864 (set_attr "mode" "SI")])
1866 ;; Widening multiply with negation.
1867 (define_insn "*muls<u>_di"
1868 [(set (match_operand:DI 0 "register_operand" "=x")
1871 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1872 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1873 "!TARGET_64BIT && ISA_HAS_MULS"
1875 [(set_attr "type" "imul")
1876 (set_attr "mode" "SI")])
1878 (define_insn "<u>msubsidi4"
1879 [(set (match_operand:DI 0 "register_operand" "=ka")
1881 (match_operand:DI 3 "register_operand" "0")
1883 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1884 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1885 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1888 return "msub<u>\t%q0,%1,%2";
1889 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1890 return "msub<u>\t%1,%2";
1892 return "msac<u>\t$0,%1,%2";
1894 [(set_attr "type" "imadd")
1895 (set_attr "mode" "SI")])
1897 ;; _highpart patterns
1899 (define_expand "<su>mulsi3_highpart"
1900 [(set (match_operand:SI 0 "register_operand")
1903 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1904 (any_extend:DI (match_operand:SI 2 "register_operand")))
1909 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1913 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1918 (define_insn_and_split "<su>mulsi3_highpart_internal"
1919 [(set (match_operand:SI 0 "register_operand" "=d")
1922 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1923 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1925 (clobber (match_scratch:SI 3 "=l"))]
1927 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1928 "&& reload_completed && !TARGET_FIX_R4000"
1935 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1936 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1937 emit_insn (gen_mfhisi_ti (operands[0], hilo));
1941 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1942 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1943 emit_insn (gen_mfhisi_di (operands[0], hilo));
1947 [(set_attr "type" "imul")
1948 (set_attr "mode" "SI")
1949 (set_attr "length" "8")])
1951 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1952 [(set (match_operand:SI 0 "register_operand" "=d")
1956 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1957 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1959 (clobber (match_scratch:SI 3 "=l"))]
1961 "mulhi<u>\t%0,%1,%2"
1962 [(set_attr "type" "imul3")
1963 (set_attr "mode" "SI")])
1965 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1966 [(set (match_operand:SI 0 "register_operand" "=d")
1971 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1972 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1974 (clobber (match_scratch:SI 3 "=l"))]
1976 "mulshi<u>\t%0,%1,%2"
1977 [(set_attr "type" "imul3")
1978 (set_attr "mode" "SI")])
1980 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1981 ;; errata MD(0), which says that dmultu does not always produce the
1983 (define_insn_and_split "<su>muldi3_highpart"
1984 [(set (match_operand:DI 0 "register_operand" "=d")
1987 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1988 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1990 (clobber (match_scratch:DI 3 "=l"))]
1991 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1992 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
1993 "&& reload_completed && !TARGET_FIX_R4000"
1998 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1999 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2000 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2003 [(set_attr "type" "imul")
2004 (set_attr "mode" "DI")
2005 (set_attr "length" "8")])
2007 (define_expand "<u>mulditi3"
2008 [(set (match_operand:TI 0 "register_operand")
2009 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2010 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2011 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2013 if (TARGET_FIX_R4000)
2014 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2016 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2021 (define_insn "<u>mulditi3_internal"
2022 [(set (match_operand:TI 0 "register_operand" "=x")
2023 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2024 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2026 && !TARGET_FIX_R4000
2027 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2029 [(set_attr "type" "imul")
2030 (set_attr "mode" "DI")])
2032 (define_insn "<u>mulditi3_r4000"
2033 [(set (match_operand:TI 0 "register_operand" "=d")
2034 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2035 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2036 (clobber (match_scratch:TI 3 "=x"))]
2039 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2040 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2041 [(set_attr "type" "imul")
2042 (set_attr "mode" "DI")
2043 (set_attr "length" "12")])
2045 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2046 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2048 (define_insn "madsi"
2049 [(set (match_operand:SI 0 "register_operand" "+l")
2050 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2051 (match_operand:SI 2 "register_operand" "d"))
2055 [(set_attr "type" "imadd")
2056 (set_attr "mode" "SI")])
2058 (define_insn "<u>maddsidi4"
2059 [(set (match_operand:DI 0 "register_operand" "=ka")
2061 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2062 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2063 (match_operand:DI 3 "register_operand" "0")))]
2064 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
2068 return "mad<u>\t%1,%2";
2069 else if (ISA_HAS_DSPR2)
2070 return "madd<u>\t%q0,%1,%2";
2071 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2072 return "madd<u>\t%1,%2";
2074 /* See comment in *macc. */
2075 return "%[macc<u>\t%@,%1,%2%]";
2077 [(set_attr "type" "imadd")
2078 (set_attr "mode" "SI")])
2080 ;; Floating point multiply accumulate instructions.
2082 (define_insn "*madd4<mode>"
2083 [(set (match_operand:ANYF 0 "register_operand" "=f")
2084 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2085 (match_operand:ANYF 2 "register_operand" "f"))
2086 (match_operand:ANYF 3 "register_operand" "f")))]
2087 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2088 "madd.<fmt>\t%0,%3,%1,%2"
2089 [(set_attr "type" "fmadd")
2090 (set_attr "mode" "<UNITMODE>")])
2092 (define_insn "*madd3<mode>"
2093 [(set (match_operand:ANYF 0 "register_operand" "=f")
2094 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2095 (match_operand:ANYF 2 "register_operand" "f"))
2096 (match_operand:ANYF 3 "register_operand" "0")))]
2097 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2098 "madd.<fmt>\t%0,%1,%2"
2099 [(set_attr "type" "fmadd")
2100 (set_attr "mode" "<UNITMODE>")])
2102 (define_insn "*msub4<mode>"
2103 [(set (match_operand:ANYF 0 "register_operand" "=f")
2104 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2105 (match_operand:ANYF 2 "register_operand" "f"))
2106 (match_operand:ANYF 3 "register_operand" "f")))]
2107 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2108 "msub.<fmt>\t%0,%3,%1,%2"
2109 [(set_attr "type" "fmadd")
2110 (set_attr "mode" "<UNITMODE>")])
2112 (define_insn "*msub3<mode>"
2113 [(set (match_operand:ANYF 0 "register_operand" "=f")
2114 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2115 (match_operand:ANYF 2 "register_operand" "f"))
2116 (match_operand:ANYF 3 "register_operand" "0")))]
2117 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2118 "msub.<fmt>\t%0,%1,%2"
2119 [(set_attr "type" "fmadd")
2120 (set_attr "mode" "<UNITMODE>")])
2122 (define_insn "*nmadd4<mode>"
2123 [(set (match_operand:ANYF 0 "register_operand" "=f")
2124 (neg:ANYF (plus:ANYF
2125 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2126 (match_operand:ANYF 2 "register_operand" "f"))
2127 (match_operand:ANYF 3 "register_operand" "f"))))]
2128 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2129 && TARGET_FUSED_MADD
2130 && HONOR_SIGNED_ZEROS (<MODE>mode)
2131 && !HONOR_NANS (<MODE>mode)"
2132 "nmadd.<fmt>\t%0,%3,%1,%2"
2133 [(set_attr "type" "fmadd")
2134 (set_attr "mode" "<UNITMODE>")])
2136 (define_insn "*nmadd3<mode>"
2137 [(set (match_operand:ANYF 0 "register_operand" "=f")
2138 (neg:ANYF (plus:ANYF
2139 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2140 (match_operand:ANYF 2 "register_operand" "f"))
2141 (match_operand:ANYF 3 "register_operand" "0"))))]
2142 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2143 && TARGET_FUSED_MADD
2144 && HONOR_SIGNED_ZEROS (<MODE>mode)
2145 && !HONOR_NANS (<MODE>mode)"
2146 "nmadd.<fmt>\t%0,%1,%2"
2147 [(set_attr "type" "fmadd")
2148 (set_attr "mode" "<UNITMODE>")])
2150 (define_insn "*nmadd4<mode>_fastmath"
2151 [(set (match_operand:ANYF 0 "register_operand" "=f")
2153 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2154 (match_operand:ANYF 2 "register_operand" "f"))
2155 (match_operand:ANYF 3 "register_operand" "f")))]
2156 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2157 && TARGET_FUSED_MADD
2158 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2159 && !HONOR_NANS (<MODE>mode)"
2160 "nmadd.<fmt>\t%0,%3,%1,%2"
2161 [(set_attr "type" "fmadd")
2162 (set_attr "mode" "<UNITMODE>")])
2164 (define_insn "*nmadd3<mode>_fastmath"
2165 [(set (match_operand:ANYF 0 "register_operand" "=f")
2167 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2168 (match_operand:ANYF 2 "register_operand" "f"))
2169 (match_operand:ANYF 3 "register_operand" "0")))]
2170 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2171 && TARGET_FUSED_MADD
2172 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2173 && !HONOR_NANS (<MODE>mode)"
2174 "nmadd.<fmt>\t%0,%1,%2"
2175 [(set_attr "type" "fmadd")
2176 (set_attr "mode" "<UNITMODE>")])
2178 (define_insn "*nmsub4<mode>"
2179 [(set (match_operand:ANYF 0 "register_operand" "=f")
2180 (neg:ANYF (minus:ANYF
2181 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2182 (match_operand:ANYF 3 "register_operand" "f"))
2183 (match_operand:ANYF 1 "register_operand" "f"))))]
2184 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2185 && TARGET_FUSED_MADD
2186 && HONOR_SIGNED_ZEROS (<MODE>mode)
2187 && !HONOR_NANS (<MODE>mode)"
2188 "nmsub.<fmt>\t%0,%1,%2,%3"
2189 [(set_attr "type" "fmadd")
2190 (set_attr "mode" "<UNITMODE>")])
2192 (define_insn "*nmsub3<mode>"
2193 [(set (match_operand:ANYF 0 "register_operand" "=f")
2194 (neg:ANYF (minus:ANYF
2195 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2196 (match_operand:ANYF 3 "register_operand" "f"))
2197 (match_operand:ANYF 1 "register_operand" "0"))))]
2198 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2199 && TARGET_FUSED_MADD
2200 && HONOR_SIGNED_ZEROS (<MODE>mode)
2201 && !HONOR_NANS (<MODE>mode)"
2202 "nmsub.<fmt>\t%0,%1,%2"
2203 [(set_attr "type" "fmadd")
2204 (set_attr "mode" "<UNITMODE>")])
2206 (define_insn "*nmsub4<mode>_fastmath"
2207 [(set (match_operand:ANYF 0 "register_operand" "=f")
2209 (match_operand:ANYF 1 "register_operand" "f")
2210 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2211 (match_operand:ANYF 3 "register_operand" "f"))))]
2212 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2213 && TARGET_FUSED_MADD
2214 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2215 && !HONOR_NANS (<MODE>mode)"
2216 "nmsub.<fmt>\t%0,%1,%2,%3"
2217 [(set_attr "type" "fmadd")
2218 (set_attr "mode" "<UNITMODE>")])
2220 (define_insn "*nmsub3<mode>_fastmath"
2221 [(set (match_operand:ANYF 0 "register_operand" "=f")
2223 (match_operand:ANYF 1 "register_operand" "f")
2224 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2225 (match_operand:ANYF 3 "register_operand" "0"))))]
2226 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2227 && TARGET_FUSED_MADD
2228 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2229 && !HONOR_NANS (<MODE>mode)"
2230 "nmsub.<fmt>\t%0,%1,%2"
2231 [(set_attr "type" "fmadd")
2232 (set_attr "mode" "<UNITMODE>")])
2235 ;; ....................
2237 ;; DIVISION and REMAINDER
2239 ;; ....................
2242 (define_expand "div<mode>3"
2243 [(set (match_operand:ANYF 0 "register_operand")
2244 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2245 (match_operand:ANYF 2 "register_operand")))]
2246 "<divide_condition>"
2248 if (const_1_operand (operands[1], <MODE>mode))
2249 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2250 operands[1] = force_reg (<MODE>mode, operands[1]);
2253 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2255 ;; If an mfc1 or dmfc1 happens to access the floating point register
2256 ;; file at the same time a long latency operation (div, sqrt, recip,
2257 ;; sqrt) iterates an intermediate result back through the floating
2258 ;; point register file bypass, then instead returning the correct
2259 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2260 ;; result of the long latency operation.
2262 ;; The workaround is to insert an unconditional 'mov' from/to the
2263 ;; long latency op destination register.
2265 (define_insn "*div<mode>3"
2266 [(set (match_operand:ANYF 0 "register_operand" "=f")
2267 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2268 (match_operand:ANYF 2 "register_operand" "f")))]
2269 "<divide_condition>"
2272 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2274 return "div.<fmt>\t%0,%1,%2";
2276 [(set_attr "type" "fdiv")
2277 (set_attr "mode" "<UNITMODE>")
2278 (set (attr "length")
2279 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2283 (define_insn "*recip<mode>3"
2284 [(set (match_operand:ANYF 0 "register_operand" "=f")
2285 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2286 (match_operand:ANYF 2 "register_operand" "f")))]
2287 "<recip_condition> && flag_unsafe_math_optimizations"
2290 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2292 return "recip.<fmt>\t%0,%2";
2294 [(set_attr "type" "frdiv")
2295 (set_attr "mode" "<UNITMODE>")
2296 (set (attr "length")
2297 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2301 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2302 ;; with negative operands. We use special libgcc functions instead.
2303 (define_insn_and_split "divmod<mode>4"
2304 [(set (match_operand:GPR 0 "register_operand" "=l")
2305 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2306 (match_operand:GPR 2 "register_operand" "d")))
2307 (set (match_operand:GPR 3 "register_operand" "=d")
2308 (mod:GPR (match_dup 1)
2310 "!TARGET_FIX_VR4120"
2312 "&& reload_completed"
2319 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2320 emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2321 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2325 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2326 emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2327 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2331 [(set_attr "type" "idiv")
2332 (set_attr "mode" "<MODE>")
2333 (set_attr "length" "8")])
2335 (define_insn_and_split "udivmod<mode>4"
2336 [(set (match_operand:GPR 0 "register_operand" "=l")
2337 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2338 (match_operand:GPR 2 "register_operand" "d")))
2339 (set (match_operand:GPR 3 "register_operand" "=d")
2340 (umod:GPR (match_dup 1)
2351 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2352 emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
2353 emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
2357 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2358 emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
2359 emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
2363 [(set_attr "type" "idiv")
2364 (set_attr "mode" "<MODE>")
2365 (set_attr "length" "8")])
2367 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2368 [(set (match_operand:HILO 0 "register_operand" "=x")
2370 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2371 (match_operand:GPR 2 "register_operand" "d"))]
2374 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2375 [(set_attr "type" "idiv")
2376 (set_attr "mode" "<GPR:MODE>")])
2379 ;; ....................
2383 ;; ....................
2385 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2386 ;; "*div[sd]f3" comment for details).
2388 (define_insn "sqrt<mode>2"
2389 [(set (match_operand:ANYF 0 "register_operand" "=f")
2390 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2394 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2396 return "sqrt.<fmt>\t%0,%1";
2398 [(set_attr "type" "fsqrt")
2399 (set_attr "mode" "<UNITMODE>")
2400 (set (attr "length")
2401 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2405 (define_insn "*rsqrt<mode>a"
2406 [(set (match_operand:ANYF 0 "register_operand" "=f")
2407 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2408 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2409 "<recip_condition> && flag_unsafe_math_optimizations"
2412 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2414 return "rsqrt.<fmt>\t%0,%2";
2416 [(set_attr "type" "frsqrt")
2417 (set_attr "mode" "<UNITMODE>")
2418 (set (attr "length")
2419 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2423 (define_insn "*rsqrt<mode>b"
2424 [(set (match_operand:ANYF 0 "register_operand" "=f")
2425 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2426 (match_operand:ANYF 2 "register_operand" "f"))))]
2427 "<recip_condition> && flag_unsafe_math_optimizations"
2430 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2432 return "rsqrt.<fmt>\t%0,%2";
2434 [(set_attr "type" "frsqrt")
2435 (set_attr "mode" "<UNITMODE>")
2436 (set (attr "length")
2437 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2442 ;; ....................
2446 ;; ....................
2448 ;; Do not use the integer abs macro instruction, since that signals an
2449 ;; exception on -2147483648 (sigh).
2451 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2452 ;; invalid; it does not clear their sign bits. We therefore can't use
2453 ;; abs.fmt if the signs of NaNs matter.
2455 (define_insn "abs<mode>2"
2456 [(set (match_operand:ANYF 0 "register_operand" "=f")
2457 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2458 "!HONOR_NANS (<MODE>mode)"
2460 [(set_attr "type" "fabs")
2461 (set_attr "mode" "<UNITMODE>")])
2464 ;; ...................
2466 ;; Count leading zeroes.
2468 ;; ...................
2471 (define_insn "clz<mode>2"
2472 [(set (match_operand:GPR 0 "register_operand" "=d")
2473 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2476 [(set_attr "type" "clz")
2477 (set_attr "mode" "<MODE>")])
2480 ;; ...................
2482 ;; Count number of set bits.
2484 ;; ...................
2487 (define_insn "popcount<mode>2"
2488 [(set (match_operand:GPR 0 "register_operand" "=d")
2489 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2492 [(set_attr "type" "pop")
2493 (set_attr "mode" "<MODE>")])
2496 ;; ....................
2498 ;; NEGATION and ONE'S COMPLEMENT
2500 ;; ....................
2502 (define_insn "negsi2"
2503 [(set (match_operand:SI 0 "register_operand" "=d")
2504 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2508 return "neg\t%0,%1";
2510 return "subu\t%0,%.,%1";
2512 [(set_attr "type" "arith")
2513 (set_attr "mode" "SI")])
2515 (define_insn "negdi2"
2516 [(set (match_operand:DI 0 "register_operand" "=d")
2517 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2518 "TARGET_64BIT && !TARGET_MIPS16"
2520 [(set_attr "type" "arith")
2521 (set_attr "mode" "DI")])
2523 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2524 ;; invalid; it does not flip their sign bit. We therefore can't use
2525 ;; neg.fmt if the signs of NaNs matter.
2527 (define_insn "neg<mode>2"
2528 [(set (match_operand:ANYF 0 "register_operand" "=f")
2529 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2530 "!HONOR_NANS (<MODE>mode)"
2532 [(set_attr "type" "fneg")
2533 (set_attr "mode" "<UNITMODE>")])
2535 (define_insn "one_cmpl<mode>2"
2536 [(set (match_operand:GPR 0 "register_operand" "=d")
2537 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2541 return "not\t%0,%1";
2543 return "nor\t%0,%.,%1";
2545 [(set_attr "type" "logical")
2546 (set_attr "mode" "<MODE>")])
2549 ;; ....................
2553 ;; ....................
2556 ;; Many of these instructions use trivial define_expands, because we
2557 ;; want to use a different set of constraints when TARGET_MIPS16.
2559 (define_expand "and<mode>3"
2560 [(set (match_operand:GPR 0 "register_operand")
2561 (and:GPR (match_operand:GPR 1 "register_operand")
2562 (match_operand:GPR 2 "uns_arith_operand")))]
2566 operands[2] = force_reg (<MODE>mode, operands[2]);
2569 (define_insn "*and<mode>3"
2570 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2571 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2572 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2577 [(set_attr "type" "logical")
2578 (set_attr "mode" "<MODE>")])
2580 (define_insn "*and<mode>3_mips16"
2581 [(set (match_operand:GPR 0 "register_operand" "=d")
2582 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2583 (match_operand:GPR 2 "register_operand" "d")))]
2586 [(set_attr "type" "logical")
2587 (set_attr "mode" "<MODE>")])
2589 (define_expand "ior<mode>3"
2590 [(set (match_operand:GPR 0 "register_operand")
2591 (ior:GPR (match_operand:GPR 1 "register_operand")
2592 (match_operand:GPR 2 "uns_arith_operand")))]
2596 operands[2] = force_reg (<MODE>mode, operands[2]);
2599 (define_insn "*ior<mode>3"
2600 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2601 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2602 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2607 [(set_attr "type" "logical")
2608 (set_attr "mode" "<MODE>")])
2610 (define_insn "*ior<mode>3_mips16"
2611 [(set (match_operand:GPR 0 "register_operand" "=d")
2612 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2613 (match_operand:GPR 2 "register_operand" "d")))]
2616 [(set_attr "type" "logical")
2617 (set_attr "mode" "<MODE>")])
2619 (define_expand "xor<mode>3"
2620 [(set (match_operand:GPR 0 "register_operand")
2621 (xor:GPR (match_operand:GPR 1 "register_operand")
2622 (match_operand:GPR 2 "uns_arith_operand")))]
2627 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2628 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2629 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2634 [(set_attr "type" "logical")
2635 (set_attr "mode" "<MODE>")])
2638 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2639 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2640 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2646 [(set_attr "type" "logical,arith,arith")
2647 (set_attr "mode" "<MODE>")
2648 (set_attr_alternative "length"
2650 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2655 (define_insn "*nor<mode>3"
2656 [(set (match_operand:GPR 0 "register_operand" "=d")
2657 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2658 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2661 [(set_attr "type" "logical")
2662 (set_attr "mode" "<MODE>")])
2665 ;; ....................
2669 ;; ....................
2673 (define_insn "truncdfsf2"
2674 [(set (match_operand:SF 0 "register_operand" "=f")
2675 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2676 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2678 [(set_attr "type" "fcvt")
2679 (set_attr "cnv_mode" "D2S")
2680 (set_attr "mode" "SF")])
2682 ;; Integer truncation patterns. Truncating SImode values to smaller
2683 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2684 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2685 ;; need to make sure that the lower 32 bits are properly sign-extended
2686 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2687 ;; smaller than SImode is equivalent to two separate truncations:
2690 ;; DI ---> HI == DI ---> SI ---> HI
2691 ;; DI ---> QI == DI ---> SI ---> QI
2693 ;; Step A needs a real instruction but step B does not.
2695 (define_insn "truncdisi2"
2696 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2697 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2702 [(set_attr "move_type" "sll0,store")
2703 (set_attr "mode" "SI")])
2705 (define_insn "truncdihi2"
2706 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2707 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2712 [(set_attr "move_type" "sll0,store")
2713 (set_attr "mode" "SI")])
2715 (define_insn "truncdiqi2"
2716 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2717 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2722 [(set_attr "move_type" "sll0,store")
2723 (set_attr "mode" "SI")])
2725 ;; Combiner patterns to optimize shift/truncate combinations.
2727 (define_insn "*ashr_trunc<mode>"
2728 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2730 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2731 (match_operand:DI 2 "const_arith_operand" ""))))]
2732 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
2734 [(set_attr "type" "shift")
2735 (set_attr "mode" "<MODE>")])
2737 (define_insn "*lshr32_trunc<mode>"
2738 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2740 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2742 "TARGET_64BIT && !TARGET_MIPS16"
2744 [(set_attr "type" "shift")
2745 (set_attr "mode" "<MODE>")])
2747 ;; Logical shift by 32 or more results in proper SI values so
2748 ;; truncation is removed by the middle end.
2749 (define_insn "*<optab>_trunc<mode>_exts"
2750 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2752 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
2753 (match_operand:DI 2 "const_arith_operand" ""))))]
2754 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
2756 [(set_attr "type" "arith")
2757 (set_attr "mode" "<MODE>")])
2759 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
2760 ;; use the shift/truncate patterns above.
2762 (define_insn_and_split "*extenddi_truncate<mode>"
2763 [(set (match_operand:DI 0 "register_operand" "=d")
2765 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2766 "TARGET_64BIT && !TARGET_MIPS16"
2768 "&& reload_completed"
2770 (ashift:DI (match_dup 1)
2773 (ashiftrt:DI (match_dup 2)
2776 operands[2] = gen_lowpart (DImode, operands[0]);
2777 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2780 (define_insn_and_split "*extendsi_truncate<mode>"
2781 [(set (match_operand:SI 0 "register_operand" "=d")
2783 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2784 "TARGET_64BIT && !TARGET_MIPS16"
2786 "&& reload_completed"
2788 (ashift:DI (match_dup 1)
2791 (truncate:SI (ashiftrt:DI (match_dup 2)
2794 operands[2] = gen_lowpart (DImode, operands[0]);
2795 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2798 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2800 (define_insn "*zero_extend<mode>_trunchi"
2801 [(set (match_operand:GPR 0 "register_operand" "=d")
2803 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2804 "TARGET_64BIT && !TARGET_MIPS16"
2805 "andi\t%0,%1,0xffff"
2806 [(set_attr "type" "logical")
2807 (set_attr "mode" "<MODE>")])
2809 (define_insn "*zero_extend<mode>_truncqi"
2810 [(set (match_operand:GPR 0 "register_operand" "=d")
2812 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2813 "TARGET_64BIT && !TARGET_MIPS16"
2815 [(set_attr "type" "logical")
2816 (set_attr "mode" "<MODE>")])
2819 [(set (match_operand:HI 0 "register_operand" "=d")
2821 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2822 "TARGET_64BIT && !TARGET_MIPS16"
2824 [(set_attr "type" "logical")
2825 (set_attr "mode" "HI")])
2828 ;; ....................
2832 ;; ....................
2836 (define_insn_and_split "zero_extendsidi2"
2837 [(set (match_operand:DI 0 "register_operand" "=d,d")
2838 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2843 "&& reload_completed && REG_P (operands[1])"
2845 (ashift:DI (match_dup 1) (const_int 32)))
2847 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2848 { operands[1] = gen_lowpart (DImode, operands[1]); }
2849 [(set_attr "move_type" "shift_shift,load")
2850 (set_attr "mode" "DI")])
2852 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2853 ;; because of TRULY_NOOP_TRUNCATION.
2855 (define_insn_and_split "*clear_upper32"
2856 [(set (match_operand:DI 0 "register_operand" "=d,d")
2857 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
2858 (const_int 4294967295)))]
2861 if (which_alternative == 0)
2864 operands[1] = gen_lowpart (SImode, operands[1]);
2865 return "lwu\t%0,%1";
2867 "&& reload_completed && REG_P (operands[1])"
2869 (ashift:DI (match_dup 1) (const_int 32)))
2871 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2873 [(set_attr "move_type" "shift_shift,load")
2874 (set_attr "mode" "DI")])
2876 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2877 [(set (match_operand:GPR 0 "register_operand")
2878 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2881 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2882 && !memory_operand (operands[1], <SHORT:MODE>mode))
2884 emit_insn (gen_and<GPR:mode>3 (operands[0],
2885 gen_lowpart (<GPR:MODE>mode, operands[1]),
2886 force_reg (<GPR:MODE>mode,
2887 GEN_INT (<SHORT:mask>))));
2892 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2893 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2895 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2898 andi\t%0,%1,<SHORT:mask>
2899 l<SHORT:size>u\t%0,%1"
2900 [(set_attr "move_type" "andi,load")
2901 (set_attr "mode" "<GPR:MODE>")])
2903 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2904 [(set (match_operand:GPR 0 "register_operand" "=d")
2905 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2907 "ze<SHORT:size>\t%0"
2908 ;; This instruction is effectively a special encoding of ANDI.
2909 [(set_attr "move_type" "andi")
2910 (set_attr "mode" "<GPR:MODE>")])
2912 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2913 [(set (match_operand:GPR 0 "register_operand" "=d")
2914 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2916 "l<SHORT:size>u\t%0,%1"
2917 [(set_attr "move_type" "load")
2918 (set_attr "mode" "<GPR:MODE>")])
2920 (define_expand "zero_extendqihi2"
2921 [(set (match_operand:HI 0 "register_operand")
2922 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2925 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2927 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2933 (define_insn "*zero_extendqihi2"
2934 [(set (match_operand:HI 0 "register_operand" "=d,d")
2935 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2940 [(set_attr "move_type" "andi,load")
2941 (set_attr "mode" "HI")])
2943 (define_insn "*zero_extendqihi2_mips16"
2944 [(set (match_operand:HI 0 "register_operand" "=d")
2945 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2948 [(set_attr "move_type" "load")
2949 (set_attr "mode" "HI")])
2952 ;; ....................
2956 ;; ....................
2959 ;; Those for integer source operand are ordered widest source type first.
2961 ;; When TARGET_64BIT, all SImode integer registers should already be in
2962 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2963 ;; therefore get rid of register->register instructions if we constrain
2964 ;; the source to be in the same register as the destination.
2966 ;; The register alternative has type "arith" so that the pre-reload
2967 ;; scheduler will treat it as a move. This reflects what happens if
2968 ;; the register alternative needs a reload.
2969 (define_insn_and_split "extendsidi2"
2970 [(set (match_operand:DI 0 "register_operand" "=d,d")
2971 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2976 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2979 emit_note (NOTE_INSN_DELETED);
2982 [(set_attr "move_type" "move,load")
2983 (set_attr "mode" "DI")])
2985 (define_expand "extend<SHORT:mode><GPR:mode>2"
2986 [(set (match_operand:GPR 0 "register_operand")
2987 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2990 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2991 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2992 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2996 l<SHORT:size>\t%0,%1"
2997 [(set_attr "move_type" "signext,load")
2998 (set_attr "mode" "<GPR:MODE>")])
3000 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3001 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3003 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3004 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3007 l<SHORT:size>\t%0,%1"
3008 "&& reload_completed && REG_P (operands[1])"
3009 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3010 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3012 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3013 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3014 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3016 [(set_attr "move_type" "shift_shift,load")
3017 (set_attr "mode" "<GPR:MODE>")])
3019 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3020 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3022 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3025 se<SHORT:size>\t%0,%1
3026 l<SHORT:size>\t%0,%1"
3027 [(set_attr "move_type" "signext,load")
3028 (set_attr "mode" "<GPR:MODE>")])
3030 (define_expand "extendqihi2"
3031 [(set (match_operand:HI 0 "register_operand")
3032 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3035 (define_insn "*extendqihi2_mips16e"
3036 [(set (match_operand:HI 0 "register_operand" "=d,d")
3037 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3042 [(set_attr "move_type" "signext,load")
3043 (set_attr "mode" "SI")])
3045 (define_insn_and_split "*extendqihi2"
3046 [(set (match_operand:HI 0 "register_operand" "=d,d")
3048 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3049 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3053 "&& reload_completed && REG_P (operands[1])"
3054 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3055 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3057 operands[0] = gen_lowpart (SImode, operands[0]);
3058 operands[1] = gen_lowpart (SImode, operands[1]);
3059 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3060 - GET_MODE_BITSIZE (QImode));
3062 [(set_attr "move_type" "shift_shift,load")
3063 (set_attr "mode" "SI")])
3065 (define_insn "*extendqihi2_seb"
3066 [(set (match_operand:HI 0 "register_operand" "=d,d")
3068 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3073 [(set_attr "move_type" "signext,load")
3074 (set_attr "mode" "SI")])
3076 (define_insn "extendsfdf2"
3077 [(set (match_operand:DF 0 "register_operand" "=f")
3078 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3079 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3081 [(set_attr "type" "fcvt")
3082 (set_attr "cnv_mode" "S2D")
3083 (set_attr "mode" "DF")])
3086 ;; ....................
3090 ;; ....................
3092 (define_expand "fix_truncdfsi2"
3093 [(set (match_operand:SI 0 "register_operand")
3094 (fix:SI (match_operand:DF 1 "register_operand")))]
3095 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3097 if (!ISA_HAS_TRUNC_W)
3099 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3104 (define_insn "fix_truncdfsi2_insn"
3105 [(set (match_operand:SI 0 "register_operand" "=f")
3106 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3107 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3109 [(set_attr "type" "fcvt")
3110 (set_attr "mode" "DF")
3111 (set_attr "cnv_mode" "D2I")])
3113 (define_insn "fix_truncdfsi2_macro"
3114 [(set (match_operand:SI 0 "register_operand" "=f")
3115 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3116 (clobber (match_scratch:DF 2 "=d"))]
3117 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3120 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3122 return "trunc.w.d %0,%1,%2";
3124 [(set_attr "type" "fcvt")
3125 (set_attr "mode" "DF")
3126 (set_attr "cnv_mode" "D2I")
3127 (set_attr "length" "36")])
3129 (define_expand "fix_truncsfsi2"
3130 [(set (match_operand:SI 0 "register_operand")
3131 (fix:SI (match_operand:SF 1 "register_operand")))]
3134 if (!ISA_HAS_TRUNC_W)
3136 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3141 (define_insn "fix_truncsfsi2_insn"
3142 [(set (match_operand:SI 0 "register_operand" "=f")
3143 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3144 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3146 [(set_attr "type" "fcvt")
3147 (set_attr "mode" "SF")
3148 (set_attr "cnv_mode" "S2I")])
3150 (define_insn "fix_truncsfsi2_macro"
3151 [(set (match_operand:SI 0 "register_operand" "=f")
3152 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3153 (clobber (match_scratch:SF 2 "=d"))]
3154 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3157 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3159 return "trunc.w.s %0,%1,%2";
3161 [(set_attr "type" "fcvt")
3162 (set_attr "mode" "SF")
3163 (set_attr "cnv_mode" "S2I")
3164 (set_attr "length" "36")])
3167 (define_insn "fix_truncdfdi2"
3168 [(set (match_operand:DI 0 "register_operand" "=f")
3169 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3170 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3172 [(set_attr "type" "fcvt")
3173 (set_attr "mode" "DF")
3174 (set_attr "cnv_mode" "D2I")])
3177 (define_insn "fix_truncsfdi2"
3178 [(set (match_operand:DI 0 "register_operand" "=f")
3179 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3180 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3182 [(set_attr "type" "fcvt")
3183 (set_attr "mode" "SF")
3184 (set_attr "cnv_mode" "S2I")])
3187 (define_insn "floatsidf2"
3188 [(set (match_operand:DF 0 "register_operand" "=f")
3189 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3190 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3192 [(set_attr "type" "fcvt")
3193 (set_attr "mode" "DF")
3194 (set_attr "cnv_mode" "I2D")])
3197 (define_insn "floatdidf2"
3198 [(set (match_operand:DF 0 "register_operand" "=f")
3199 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3200 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3202 [(set_attr "type" "fcvt")
3203 (set_attr "mode" "DF")
3204 (set_attr "cnv_mode" "I2D")])
3207 (define_insn "floatsisf2"
3208 [(set (match_operand:SF 0 "register_operand" "=f")
3209 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3212 [(set_attr "type" "fcvt")
3213 (set_attr "mode" "SF")
3214 (set_attr "cnv_mode" "I2S")])
3217 (define_insn "floatdisf2"
3218 [(set (match_operand:SF 0 "register_operand" "=f")
3219 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3220 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3222 [(set_attr "type" "fcvt")
3223 (set_attr "mode" "SF")
3224 (set_attr "cnv_mode" "I2S")])
3227 (define_expand "fixuns_truncdfsi2"
3228 [(set (match_operand:SI 0 "register_operand")
3229 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3230 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3232 rtx reg1 = gen_reg_rtx (DFmode);
3233 rtx reg2 = gen_reg_rtx (DFmode);
3234 rtx reg3 = gen_reg_rtx (SImode);
3235 rtx label1 = gen_label_rtx ();
3236 rtx label2 = gen_label_rtx ();
3238 REAL_VALUE_TYPE offset;
3240 real_2expN (&offset, 31, DFmode);
3242 if (reg1) /* Turn off complaints about unreached code. */
3244 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3245 do_pending_stack_adjust ();
3247 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3248 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3250 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3251 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3252 gen_rtx_LABEL_REF (VOIDmode, label2)));
3255 emit_label (label1);
3256 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3257 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3258 (BITMASK_HIGH, SImode)));
3260 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3261 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3263 emit_label (label2);
3265 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3266 fields, and can't be used for REG_NOTES anyway). */
3267 emit_use (stack_pointer_rtx);
3273 (define_expand "fixuns_truncdfdi2"
3274 [(set (match_operand:DI 0 "register_operand")
3275 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3276 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3278 rtx reg1 = gen_reg_rtx (DFmode);
3279 rtx reg2 = gen_reg_rtx (DFmode);
3280 rtx reg3 = gen_reg_rtx (DImode);
3281 rtx label1 = gen_label_rtx ();
3282 rtx label2 = gen_label_rtx ();
3284 REAL_VALUE_TYPE offset;
3286 real_2expN (&offset, 63, DFmode);
3288 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3289 do_pending_stack_adjust ();
3291 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3292 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3294 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3295 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3296 gen_rtx_LABEL_REF (VOIDmode, label2)));
3299 emit_label (label1);
3300 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3301 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3302 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3304 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3305 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3307 emit_label (label2);
3309 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3310 fields, and can't be used for REG_NOTES anyway). */
3311 emit_use (stack_pointer_rtx);
3316 (define_expand "fixuns_truncsfsi2"
3317 [(set (match_operand:SI 0 "register_operand")
3318 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3321 rtx reg1 = gen_reg_rtx (SFmode);
3322 rtx reg2 = gen_reg_rtx (SFmode);
3323 rtx reg3 = gen_reg_rtx (SImode);
3324 rtx label1 = gen_label_rtx ();
3325 rtx label2 = gen_label_rtx ();
3327 REAL_VALUE_TYPE offset;
3329 real_2expN (&offset, 31, SFmode);
3331 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3332 do_pending_stack_adjust ();
3334 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3335 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3337 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3338 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3339 gen_rtx_LABEL_REF (VOIDmode, label2)));
3342 emit_label (label1);
3343 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3344 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3345 (BITMASK_HIGH, SImode)));
3347 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3348 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3350 emit_label (label2);
3352 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3353 fields, and can't be used for REG_NOTES anyway). */
3354 emit_use (stack_pointer_rtx);
3359 (define_expand "fixuns_truncsfdi2"
3360 [(set (match_operand:DI 0 "register_operand")
3361 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3362 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3364 rtx reg1 = gen_reg_rtx (SFmode);
3365 rtx reg2 = gen_reg_rtx (SFmode);
3366 rtx reg3 = gen_reg_rtx (DImode);
3367 rtx label1 = gen_label_rtx ();
3368 rtx label2 = gen_label_rtx ();
3370 REAL_VALUE_TYPE offset;
3372 real_2expN (&offset, 63, SFmode);
3374 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3375 do_pending_stack_adjust ();
3377 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3378 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3380 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3381 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3382 gen_rtx_LABEL_REF (VOIDmode, label2)));
3385 emit_label (label1);
3386 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3387 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3388 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3390 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3391 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3393 emit_label (label2);
3395 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3396 fields, and can't be used for REG_NOTES anyway). */
3397 emit_use (stack_pointer_rtx);
3402 ;; ....................
3406 ;; ....................
3408 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3410 (define_expand "extv"
3411 [(set (match_operand 0 "register_operand")
3412 (sign_extract (match_operand 1 "nonimmediate_operand")
3413 (match_operand 2 "const_int_operand")
3414 (match_operand 3 "const_int_operand")))]
3417 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3418 INTVAL (operands[2]),
3419 INTVAL (operands[3])))
3421 else if (register_operand (operands[1], GET_MODE (operands[0]))
3422 && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
3424 if (GET_MODE (operands[0]) == DImode)
3425 emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
3428 emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
3436 (define_insn "extv<mode>"
3437 [(set (match_operand:GPR 0 "register_operand" "=d")
3438 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3439 (match_operand 2 "const_int_operand" "")
3440 (match_operand 3 "const_int_operand" "")))]
3441 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3442 "exts\t%0,%1,%3,%m2"
3443 [(set_attr "type" "arith")
3444 (set_attr "mode" "<MODE>")])
3447 (define_expand "extzv"
3448 [(set (match_operand 0 "register_operand")
3449 (zero_extract (match_operand 1 "nonimmediate_operand")
3450 (match_operand 2 "const_int_operand")
3451 (match_operand 3 "const_int_operand")))]
3454 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3455 INTVAL (operands[2]),
3456 INTVAL (operands[3])))
3458 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3459 INTVAL (operands[3])))
3461 if (GET_MODE (operands[0]) == DImode)
3462 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3465 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3473 (define_insn "extzv<mode>"
3474 [(set (match_operand:GPR 0 "register_operand" "=d")
3475 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3476 (match_operand 2 "const_int_operand" "")
3477 (match_operand 3 "const_int_operand" "")))]
3478 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3479 INTVAL (operands[3]))"
3480 "<d>ext\t%0,%1,%3,%2"
3481 [(set_attr "type" "arith")
3482 (set_attr "mode" "<MODE>")])
3484 (define_insn "*extzv_trunc<mode>_exts"
3485 [(set (match_operand:GPR 0 "register_operand" "=d")
3487 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3488 (match_operand 2 "const_int_operand" "")
3489 (match_operand 3 "const_int_operand" ""))))]
3490 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3492 [(set_attr "type" "arith")
3493 (set_attr "mode" "<MODE>")])
3496 (define_expand "insv"
3497 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3498 (match_operand 1 "immediate_operand")
3499 (match_operand 2 "immediate_operand"))
3500 (match_operand 3 "reg_or_0_operand"))]
3503 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3504 INTVAL (operands[1]),
3505 INTVAL (operands[2])))
3507 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3508 INTVAL (operands[2])))
3510 if (GET_MODE (operands[0]) == DImode)
3511 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3514 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3522 (define_insn "insv<mode>"
3523 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3524 (match_operand:SI 1 "immediate_operand" "I")
3525 (match_operand:SI 2 "immediate_operand" "I"))
3526 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3527 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3528 INTVAL (operands[2]))"
3529 "<d>ins\t%0,%z3,%2,%1"
3530 [(set_attr "type" "arith")
3531 (set_attr "mode" "<MODE>")])
3533 ;; Combiner pattern for cins (clear and insert bit field). We can
3534 ;; implement mask-and-shift-left operation with this. Note that if
3535 ;; the upper bit of the mask is set in an SImode operation, the mask
3536 ;; itself will be sign-extended. mask_low_and_shift_len will
3537 ;; therefore be greater than our threshold of 32.
3539 (define_insn "*cins<mode>"
3540 [(set (match_operand:GPR 0 "register_operand" "=d")
3542 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3543 (match_operand:GPR 2 "const_int_operand" ""))
3544 (match_operand:GPR 3 "const_int_operand" "")))]
3546 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3549 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3550 return "cins\t%0,%1,%2,%m3";
3552 [(set_attr "type" "shift")
3553 (set_attr "mode" "<MODE>")])
3555 ;; Unaligned word moves generated by the bit field patterns.
3557 ;; As far as the rtl is concerned, both the left-part and right-part
3558 ;; instructions can access the whole field. However, the real operand
3559 ;; refers to just the first or the last byte (depending on endianness).
3560 ;; We therefore use two memory operands to each instruction, one to
3561 ;; describe the rtl effect and one to use in the assembly output.
3563 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3564 ;; This allows us to use the standard length calculations for the "load"
3565 ;; and "store" type attributes.
3567 (define_insn "mov_<load>l"
3568 [(set (match_operand:GPR 0 "register_operand" "=d")
3569 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3570 (match_operand:QI 2 "memory_operand" "m")]
3572 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3574 [(set_attr "move_type" "load")
3575 (set_attr "mode" "<MODE>")])
3577 (define_insn "mov_<load>r"
3578 [(set (match_operand:GPR 0 "register_operand" "=d")
3579 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3580 (match_operand:QI 2 "memory_operand" "m")
3581 (match_operand:GPR 3 "register_operand" "0")]
3582 UNSPEC_LOAD_RIGHT))]
3583 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3585 [(set_attr "move_type" "load")
3586 (set_attr "mode" "<MODE>")])
3588 (define_insn "mov_<store>l"
3589 [(set (match_operand:BLK 0 "memory_operand" "=m")
3590 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3591 (match_operand:QI 2 "memory_operand" "m")]
3592 UNSPEC_STORE_LEFT))]
3593 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3595 [(set_attr "move_type" "store")
3596 (set_attr "mode" "<MODE>")])
3598 (define_insn "mov_<store>r"
3599 [(set (match_operand:BLK 0 "memory_operand" "+m")
3600 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3601 (match_operand:QI 2 "memory_operand" "m")
3603 UNSPEC_STORE_RIGHT))]
3604 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3606 [(set_attr "move_type" "store")
3607 (set_attr "mode" "<MODE>")])
3609 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3610 ;; The required value is:
3612 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3614 ;; which translates to:
3616 ;; lui op0,%highest(op1)
3617 ;; daddiu op0,op0,%higher(op1)
3619 ;; daddiu op0,op0,%hi(op1)
3622 ;; The split is deferred until after flow2 to allow the peephole2 below
3624 (define_insn_and_split "*lea_high64"
3625 [(set (match_operand:DI 0 "register_operand" "=d")
3626 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3627 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3629 "&& epilogue_completed"
3630 [(set (match_dup 0) (high:DI (match_dup 2)))
3631 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3632 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3633 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3634 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3636 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3637 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3639 [(set_attr "length" "20")])
3641 ;; Use a scratch register to reduce the latency of the above pattern
3642 ;; on superscalar machines. The optimized sequence is:
3644 ;; lui op1,%highest(op2)
3646 ;; daddiu op1,op1,%higher(op2)
3648 ;; daddu op1,op1,op0
3650 [(set (match_operand:DI 1 "d_operand")
3651 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3652 (match_scratch:DI 0 "d")]
3653 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3654 [(set (match_dup 1) (high:DI (match_dup 3)))
3655 (set (match_dup 0) (high:DI (match_dup 4)))
3656 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3657 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3658 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3660 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3661 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3664 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3665 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3666 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3667 ;; used once. We can then use the sequence:
3669 ;; lui op0,%highest(op1)
3671 ;; daddiu op0,op0,%higher(op1)
3672 ;; daddiu op2,op2,%lo(op1)
3674 ;; daddu op0,op0,op2
3676 ;; which takes 4 cycles on most superscalar targets.
3677 (define_insn_and_split "*lea64"
3678 [(set (match_operand:DI 0 "register_operand" "=d")
3679 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3680 (clobber (match_scratch:DI 2 "=&d"))]
3681 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3683 "&& reload_completed"
3684 [(set (match_dup 0) (high:DI (match_dup 3)))
3685 (set (match_dup 2) (high:DI (match_dup 4)))
3686 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3687 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3688 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3689 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3691 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3692 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3694 [(set_attr "length" "24")])
3696 ;; Split HIGHs into:
3701 ;; on MIPS16 targets.
3703 [(set (match_operand:SI 0 "d_operand")
3704 (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
3705 "TARGET_MIPS16 && reload_completed"
3706 [(set (match_dup 0) (match_dup 2))
3707 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3709 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3712 ;; Insns to fetch a symbol from a big GOT.
3714 (define_insn_and_split "*xgot_hi<mode>"
3715 [(set (match_operand:P 0 "register_operand" "=d")
3716 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3717 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3719 "&& reload_completed"
3720 [(set (match_dup 0) (high:P (match_dup 2)))
3721 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3723 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3724 operands[3] = pic_offset_table_rtx;
3726 [(set_attr "got" "xgot_high")
3727 (set_attr "mode" "<MODE>")])
3729 (define_insn_and_split "*xgot_lo<mode>"
3730 [(set (match_operand:P 0 "register_operand" "=d")
3731 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3732 (match_operand:P 2 "got_disp_operand" "")))]
3733 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3735 "&& reload_completed"
3737 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3738 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3739 [(set_attr "got" "load")
3740 (set_attr "mode" "<MODE>")])
3742 ;; Insns to fetch a symbol from a normal GOT.
3744 (define_insn_and_split "*got_disp<mode>"
3745 [(set (match_operand:P 0 "register_operand" "=d")
3746 (match_operand:P 1 "got_disp_operand" ""))]
3747 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
3749 "&& reload_completed"
3750 [(set (match_dup 0) (match_dup 2))]
3751 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
3752 [(set_attr "got" "load")
3753 (set_attr "mode" "<MODE>")])
3755 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3757 (define_insn_and_split "*got_page<mode>"
3758 [(set (match_operand:P 0 "register_operand" "=d")
3759 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3760 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
3762 "&& reload_completed"
3763 [(set (match_dup 0) (match_dup 2))]
3764 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
3765 [(set_attr "got" "load")
3766 (set_attr "mode" "<MODE>")])
3768 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
3769 (define_expand "unspec_got<mode>"
3770 [(unspec:P [(match_operand:P 0)
3771 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
3773 ;; Lower-level instructions for loading an address from the GOT.
3774 ;; We could use MEMs, but an unspec gives more optimization
3777 (define_insn "load_got<mode>"
3778 [(set (match_operand:P 0 "register_operand" "=d")
3779 (unspec:P [(match_operand:P 1 "register_operand" "d")
3780 (match_operand:P 2 "immediate_operand" "")]
3783 "<load>\t%0,%R2(%1)"
3784 [(set_attr "got" "load")
3785 (set_attr "mode" "<MODE>")])
3787 ;; Instructions for adding the low 16 bits of an address to a register.
3788 ;; Operand 2 is the address: mips_print_operand works out which relocation
3789 ;; should be applied.
3791 (define_insn "*low<mode>"
3792 [(set (match_operand:P 0 "register_operand" "=d")
3793 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3794 (match_operand:P 2 "immediate_operand" "")))]
3796 "<d>addiu\t%0,%1,%R2"
3797 [(set_attr "type" "arith")
3798 (set_attr "mode" "<MODE>")])
3800 (define_insn "*low<mode>_mips16"
3801 [(set (match_operand:P 0 "register_operand" "=d")
3802 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3803 (match_operand:P 2 "immediate_operand" "")))]
3806 [(set_attr "type" "arith")
3807 (set_attr "mode" "<MODE>")
3808 (set_attr "extended_mips16" "yes")])
3810 ;; Expose MIPS16 uses of the global pointer after reload if the function
3811 ;; is responsible for setting up the register itself.
3813 [(set (match_operand:GPR 0 "d_operand")
3814 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
3815 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
3816 [(set (match_dup 0) (match_dup 1))]
3817 { operands[1] = pic_offset_table_rtx; })
3819 ;; Allow combine to split complex const_int load sequences, using operand 2
3820 ;; to store the intermediate results. See move_operand for details.
3822 [(set (match_operand:GPR 0 "register_operand")
3823 (match_operand:GPR 1 "splittable_const_int_operand"))
3824 (clobber (match_operand:GPR 2 "register_operand"))]
3828 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3832 ;; Likewise, for symbolic operands.
3834 [(set (match_operand:P 0 "register_operand")
3835 (match_operand:P 1))
3836 (clobber (match_operand:P 2 "register_operand"))]
3837 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3838 [(set (match_dup 0) (match_dup 3))]
3840 mips_split_symbol (operands[2], operands[1],
3841 MAX_MACHINE_MODE, &operands[3]);
3844 ;; 64-bit integer moves
3846 ;; Unlike most other insns, the move insns can't be split with
3847 ;; different predicates, because register spilling and other parts of
3848 ;; the compiler, have memoized the insn number already.
3850 (define_expand "movdi"
3851 [(set (match_operand:DI 0 "")
3852 (match_operand:DI 1 ""))]
3855 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3859 ;; For mips16, we need a special case to handle storing $31 into
3860 ;; memory, since we don't have a constraint to match $31. This
3861 ;; instruction can be generated by save_restore_insns.
3863 (define_insn "*mov<mode>_ra"
3864 [(set (match_operand:GPR 0 "stack_operand" "=m")
3868 [(set_attr "move_type" "store")
3869 (set_attr "mode" "<MODE>")])
3871 (define_insn "*movdi_32bit"
3872 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
3873 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
3874 "!TARGET_64BIT && !TARGET_MIPS16
3875 && (register_operand (operands[0], DImode)
3876 || reg_or_0_operand (operands[1], DImode))"
3877 { return mips_output_move (operands[0], operands[1]); }
3878 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
3879 (set_attr "mode" "DI")])
3881 (define_insn "*movdi_32bit_mips16"
3882 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3883 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3884 "!TARGET_64BIT && TARGET_MIPS16
3885 && (register_operand (operands[0], DImode)
3886 || register_operand (operands[1], DImode))"
3887 { return mips_output_move (operands[0], operands[1]); }
3888 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
3889 (set_attr "mode" "DI")])
3891 (define_insn "*movdi_64bit"
3892 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3893 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3894 "TARGET_64BIT && !TARGET_MIPS16
3895 && (register_operand (operands[0], DImode)
3896 || reg_or_0_operand (operands[1], DImode))"
3897 { return mips_output_move (operands[0], operands[1]); }
3898 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3899 (set_attr "mode" "DI")])
3901 (define_insn "*movdi_64bit_mips16"
3902 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3903 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3904 "TARGET_64BIT && TARGET_MIPS16
3905 && (register_operand (operands[0], DImode)
3906 || register_operand (operands[1], DImode))"
3907 { return mips_output_move (operands[0], operands[1]); }
3908 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3909 (set_attr "mode" "DI")])
3911 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3912 ;; when the original load is a 4 byte instruction but the add and the
3913 ;; load are 2 2 byte instructions.
3916 [(set (match_operand:DI 0 "d_operand")
3917 (mem:DI (plus:DI (match_dup 0)
3918 (match_operand:DI 1 "const_int_operand"))))]
3919 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3920 && !TARGET_DEBUG_D_MODE
3921 && ((INTVAL (operands[1]) < 0
3922 && INTVAL (operands[1]) >= -0x10)
3923 || (INTVAL (operands[1]) >= 32 * 8
3924 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3925 || (INTVAL (operands[1]) >= 0
3926 && INTVAL (operands[1]) < 32 * 8
3927 && (INTVAL (operands[1]) & 7) != 0))"
3928 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3929 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3931 HOST_WIDE_INT val = INTVAL (operands[1]);
3934 operands[2] = const0_rtx;
3935 else if (val >= 32 * 8)
3939 operands[1] = GEN_INT (0x8 + off);
3940 operands[2] = GEN_INT (val - off - 0x8);
3946 operands[1] = GEN_INT (off);
3947 operands[2] = GEN_INT (val - off);
3951 ;; 32-bit Integer moves
3953 ;; Unlike most other insns, the move insns can't be split with
3954 ;; different predicates, because register spilling and other parts of
3955 ;; the compiler, have memoized the insn number already.
3957 (define_expand "mov<mode>"
3958 [(set (match_operand:IMOVE32 0 "")
3959 (match_operand:IMOVE32 1 ""))]
3962 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
3966 ;; The difference between these two is whether or not ints are allowed
3967 ;; in FP registers (off by default, use -mdebugh to enable).
3969 (define_insn "*mov<mode>_internal"
3970 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3971 (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3973 && (register_operand (operands[0], <MODE>mode)
3974 || reg_or_0_operand (operands[1], <MODE>mode))"
3975 { return mips_output_move (operands[0], operands[1]); }
3976 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3977 (set_attr "mode" "SI")])
3979 (define_insn "*mov<mode>_mips16"
3980 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
3981 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
3983 && (register_operand (operands[0], <MODE>mode)
3984 || register_operand (operands[1], <MODE>mode))"
3985 { return mips_output_move (operands[0], operands[1]); }
3986 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
3987 (set_attr "mode" "SI")])
3989 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3990 ;; when the original load is a 4 byte instruction but the add and the
3991 ;; load are 2 2 byte instructions.
3994 [(set (match_operand:SI 0 "d_operand")
3995 (mem:SI (plus:SI (match_dup 0)
3996 (match_operand:SI 1 "const_int_operand"))))]
3997 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3998 && ((INTVAL (operands[1]) < 0
3999 && INTVAL (operands[1]) >= -0x80)
4000 || (INTVAL (operands[1]) >= 32 * 4
4001 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4002 || (INTVAL (operands[1]) >= 0
4003 && INTVAL (operands[1]) < 32 * 4
4004 && (INTVAL (operands[1]) & 3) != 0))"
4005 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4006 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4008 HOST_WIDE_INT val = INTVAL (operands[1]);
4011 operands[2] = const0_rtx;
4012 else if (val >= 32 * 4)
4016 operands[1] = GEN_INT (0x7c + off);
4017 operands[2] = GEN_INT (val - off - 0x7c);
4023 operands[1] = GEN_INT (off);
4024 operands[2] = GEN_INT (val - off);
4028 ;; On the mips16, we can split a load of certain constants into a load
4029 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4033 [(set (match_operand:SI 0 "d_operand")
4034 (match_operand:SI 1 "const_int_operand"))]
4035 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4036 && INTVAL (operands[1]) >= 0x100
4037 && INTVAL (operands[1]) <= 0xff + 0x7f"
4038 [(set (match_dup 0) (match_dup 1))
4039 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4041 int val = INTVAL (operands[1]);
4043 operands[1] = GEN_INT (0xff);
4044 operands[2] = GEN_INT (val - 0xff);
4047 ;; This insn handles moving CCmode values. It's really just a
4048 ;; slightly simplified copy of movsi_internal2, with additional cases
4049 ;; to move a condition register to a general register and to move
4050 ;; between the general registers and the floating point registers.
4052 (define_insn "movcc"
4053 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
4054 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
4055 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4056 { return mips_output_move (operands[0], operands[1]); }
4057 [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
4058 (set_attr "mode" "SI")])
4060 ;; Reload condition code registers. reload_incc and reload_outcc
4061 ;; both handle moves from arbitrary operands into condition code
4062 ;; registers. reload_incc handles the more common case in which
4063 ;; a source operand is constrained to be in a condition-code
4064 ;; register, but has not been allocated to one.
4066 ;; Sometimes, such as in movcc, we have a CCmode destination whose
4067 ;; constraints do not include 'z'. reload_outcc handles the case
4068 ;; when such an operand is allocated to a condition-code register.
4070 ;; Note that reloads from a condition code register to some
4071 ;; other location can be done using ordinary moves. Moving
4072 ;; into a GPR takes a single movcc, moving elsewhere takes
4073 ;; two. We can leave these cases to the generic reload code.
4074 (define_expand "reload_incc"
4075 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4076 (match_operand:CC 1 "general_operand" ""))
4077 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4078 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4080 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4084 (define_expand "reload_outcc"
4085 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
4086 (match_operand:CC 1 "register_operand" ""))
4087 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
4088 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
4090 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
4094 ;; MIPS4 supports loading and storing a floating point register from
4095 ;; the sum of two general registers. We use two versions for each of
4096 ;; these four instructions: one where the two general registers are
4097 ;; SImode, and one where they are DImode. This is because general
4098 ;; registers will be in SImode when they hold 32-bit values, but,
4099 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4100 ;; instructions will still work correctly.
4102 ;; ??? Perhaps it would be better to support these instructions by
4103 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
4104 ;; these instructions can only be used to load and store floating
4105 ;; point registers, that would probably cause trouble in reload.
4107 (define_insn "*<ANYF:loadx>_<P:mode>"
4108 [(set (match_operand:ANYF 0 "register_operand" "=f")
4109 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4110 (match_operand:P 2 "register_operand" "d"))))]
4112 "<ANYF:loadx>\t%0,%1(%2)"
4113 [(set_attr "type" "fpidxload")
4114 (set_attr "mode" "<ANYF:UNITMODE>")])
4116 (define_insn "*<ANYF:storex>_<P:mode>"
4117 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4118 (match_operand:P 2 "register_operand" "d")))
4119 (match_operand:ANYF 0 "register_operand" "f"))]
4121 "<ANYF:storex>\t%0,%1(%2)"
4122 [(set_attr "type" "fpidxstore")
4123 (set_attr "mode" "<ANYF:UNITMODE>")])
4125 ;; Scaled indexed address load.
4126 ;; Per md.texi, we only need to look for a pattern with multiply in the
4127 ;; address expression, not shift.
4129 (define_insn "*lwxs"
4130 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4132 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
4134 (match_operand:SI 2 "register_operand" "d"))))]
4137 [(set_attr "type" "load")
4138 (set_attr "mode" "SI")])
4140 ;; 16-bit Integer moves
4142 ;; Unlike most other insns, the move insns can't be split with
4143 ;; different predicates, because register spilling and other parts of
4144 ;; the compiler, have memoized the insn number already.
4145 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4147 (define_expand "movhi"
4148 [(set (match_operand:HI 0 "")
4149 (match_operand:HI 1 ""))]
4152 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4156 (define_insn "*movhi_internal"
4157 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4158 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4160 && (register_operand (operands[0], HImode)
4161 || reg_or_0_operand (operands[1], HImode))"
4162 { return mips_output_move (operands[0], operands[1]); }
4163 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4164 (set_attr "mode" "HI")])
4166 (define_insn "*movhi_mips16"
4167 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4168 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4170 && (register_operand (operands[0], HImode)
4171 || register_operand (operands[1], HImode))"
4172 { return mips_output_move (operands[0], operands[1]); }
4173 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4174 (set_attr "mode" "HI")])
4176 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4177 ;; when the original load is a 4 byte instruction but the add and the
4178 ;; load are 2 2 byte instructions.
4181 [(set (match_operand:HI 0 "d_operand")
4182 (mem:HI (plus:SI (match_dup 0)
4183 (match_operand:SI 1 "const_int_operand"))))]
4184 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4185 && ((INTVAL (operands[1]) < 0
4186 && INTVAL (operands[1]) >= -0x80)
4187 || (INTVAL (operands[1]) >= 32 * 2
4188 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4189 || (INTVAL (operands[1]) >= 0
4190 && INTVAL (operands[1]) < 32 * 2
4191 && (INTVAL (operands[1]) & 1) != 0))"
4192 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4193 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4195 HOST_WIDE_INT val = INTVAL (operands[1]);
4198 operands[2] = const0_rtx;
4199 else if (val >= 32 * 2)
4203 operands[1] = GEN_INT (0x7e + off);
4204 operands[2] = GEN_INT (val - off - 0x7e);
4210 operands[1] = GEN_INT (off);
4211 operands[2] = GEN_INT (val - off);
4215 ;; 8-bit Integer moves
4217 ;; Unlike most other insns, the move insns can't be split with
4218 ;; different predicates, because register spilling and other parts of
4219 ;; the compiler, have memoized the insn number already.
4220 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4222 (define_expand "movqi"
4223 [(set (match_operand:QI 0 "")
4224 (match_operand:QI 1 ""))]
4227 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4231 (define_insn "*movqi_internal"
4232 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4233 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4235 && (register_operand (operands[0], QImode)
4236 || reg_or_0_operand (operands[1], QImode))"
4237 { return mips_output_move (operands[0], operands[1]); }
4238 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4239 (set_attr "mode" "QI")])
4241 (define_insn "*movqi_mips16"
4242 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4243 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4245 && (register_operand (operands[0], QImode)
4246 || register_operand (operands[1], QImode))"
4247 { return mips_output_move (operands[0], operands[1]); }
4248 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4249 (set_attr "mode" "QI")])
4251 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4252 ;; when the original load is a 4 byte instruction but the add and the
4253 ;; load are 2 2 byte instructions.
4256 [(set (match_operand:QI 0 "d_operand")
4257 (mem:QI (plus:SI (match_dup 0)
4258 (match_operand:SI 1 "const_int_operand"))))]
4259 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4260 && ((INTVAL (operands[1]) < 0
4261 && INTVAL (operands[1]) >= -0x80)
4262 || (INTVAL (operands[1]) >= 32
4263 && INTVAL (operands[1]) <= 31 + 0x7f))"
4264 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4265 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4267 HOST_WIDE_INT val = INTVAL (operands[1]);
4270 operands[2] = const0_rtx;
4273 operands[1] = GEN_INT (0x7f);
4274 operands[2] = GEN_INT (val - 0x7f);
4278 ;; 32-bit floating point moves
4280 (define_expand "movsf"
4281 [(set (match_operand:SF 0 "")
4282 (match_operand:SF 1 ""))]
4285 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4289 (define_insn "*movsf_hardfloat"
4290 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4291 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4293 && (register_operand (operands[0], SFmode)
4294 || reg_or_0_operand (operands[1], SFmode))"
4295 { return mips_output_move (operands[0], operands[1]); }
4296 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4297 (set_attr "mode" "SF")])
4299 (define_insn "*movsf_softfloat"
4300 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4301 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4302 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4303 && (register_operand (operands[0], SFmode)
4304 || reg_or_0_operand (operands[1], SFmode))"
4305 { return mips_output_move (operands[0], operands[1]); }
4306 [(set_attr "move_type" "move,load,store")
4307 (set_attr "mode" "SF")])
4309 (define_insn "*movsf_mips16"
4310 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4311 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4313 && (register_operand (operands[0], SFmode)
4314 || register_operand (operands[1], SFmode))"
4315 { return mips_output_move (operands[0], operands[1]); }
4316 [(set_attr "move_type" "move,move,move,load,store")
4317 (set_attr "mode" "SF")])
4319 ;; 64-bit floating point moves
4321 (define_expand "movdf"
4322 [(set (match_operand:DF 0 "")
4323 (match_operand:DF 1 ""))]
4326 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4330 (define_insn "*movdf_hardfloat"
4331 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4332 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4333 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4334 && (register_operand (operands[0], DFmode)
4335 || reg_or_0_operand (operands[1], DFmode))"
4336 { return mips_output_move (operands[0], operands[1]); }
4337 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4338 (set_attr "mode" "DF")])
4340 (define_insn "*movdf_softfloat"
4341 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4342 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4343 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4344 && (register_operand (operands[0], DFmode)
4345 || reg_or_0_operand (operands[1], DFmode))"
4346 { return mips_output_move (operands[0], operands[1]); }
4347 [(set_attr "move_type" "move,load,store")
4348 (set_attr "mode" "DF")])
4350 (define_insn "*movdf_mips16"
4351 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4352 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4354 && (register_operand (operands[0], DFmode)
4355 || register_operand (operands[1], DFmode))"
4356 { return mips_output_move (operands[0], operands[1]); }
4357 [(set_attr "move_type" "move,move,move,load,store")
4358 (set_attr "mode" "DF")])
4360 ;; 128-bit integer moves
4362 (define_expand "movti"
4363 [(set (match_operand:TI 0)
4364 (match_operand:TI 1))]
4367 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4371 (define_insn "*movti"
4372 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4373 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4376 && (register_operand (operands[0], TImode)
4377 || reg_or_0_operand (operands[1], TImode))"
4379 [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
4380 (set_attr "mode" "TI")])
4382 (define_insn "*movti_mips16"
4383 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4384 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4387 && (register_operand (operands[0], TImode)
4388 || register_operand (operands[1], TImode))"
4390 [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
4391 (set_attr "mode" "TI")])
4393 ;; 128-bit floating point moves
4395 (define_expand "movtf"
4396 [(set (match_operand:TF 0)
4397 (match_operand:TF 1))]
4400 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4404 ;; This pattern handles both hard- and soft-float cases.
4405 (define_insn "*movtf"
4406 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4407 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4410 && (register_operand (operands[0], TFmode)
4411 || reg_or_0_operand (operands[1], TFmode))"
4413 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4414 (set_attr "mode" "TF")])
4416 (define_insn "*movtf_mips16"
4417 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4418 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4421 && (register_operand (operands[0], TFmode)
4422 || register_operand (operands[1], TFmode))"
4424 [(set_attr "move_type" "move,move,move,load,store")
4425 (set_attr "mode" "TF")])
4428 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4429 (match_operand:MOVE64 1 "move_operand"))]
4430 "reload_completed && !TARGET_64BIT
4431 && mips_split_64bit_move_p (operands[0], operands[1])"
4434 mips_split_doubleword_move (operands[0], operands[1]);
4439 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4440 (match_operand:MOVE128 1 "move_operand"))]
4441 "TARGET_64BIT && reload_completed"
4444 mips_split_doubleword_move (operands[0], operands[1]);
4448 ;; When generating mips16 code, split moves of negative constants into
4449 ;; a positive "li" followed by a negation.
4451 [(set (match_operand 0 "d_operand")
4452 (match_operand 1 "const_int_operand"))]
4453 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4457 (neg:SI (match_dup 2)))]
4459 operands[2] = gen_lowpart (SImode, operands[0]);
4460 operands[3] = GEN_INT (-INTVAL (operands[1]));
4463 ;; 64-bit paired-single floating point moves
4465 (define_expand "movv2sf"
4466 [(set (match_operand:V2SF 0)
4467 (match_operand:V2SF 1))]
4468 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4470 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4474 (define_insn "*movv2sf"
4475 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4476 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4478 && TARGET_PAIRED_SINGLE_FLOAT
4479 && (register_operand (operands[0], V2SFmode)
4480 || reg_or_0_operand (operands[1], V2SFmode))"
4481 { return mips_output_move (operands[0], operands[1]); }
4482 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4483 (set_attr "mode" "DF")])
4485 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4486 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4488 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4489 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4490 ;; and the errata related to -mfix-vr4130.
4491 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4492 [(set (match_operand:GPR 0 "register_operand" "=d")
4493 (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
4496 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4497 [(set_attr "move_type" "mfhilo")
4498 (set_attr "mode" "<GPR:MODE>")])
4500 ;; Set the high part of a HI/LO value, given that the low part has
4501 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4502 ;; why we can't just use (reg:GPR HI_REGNUM).
4503 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4504 [(set (match_operand:HILO 0 "register_operand" "=x")
4505 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4506 (match_operand:GPR 2 "register_operand" "l")]
4510 [(set_attr "move_type" "mthilo")
4511 (set_attr "mode" "SI")])
4513 ;; Emit a doubleword move in which exactly one of the operands is
4514 ;; a floating-point register. We can't just emit two normal moves
4515 ;; because of the constraints imposed by the FPU register model;
4516 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4517 ;; the FPR whole and use special patterns to refer to each word of
4518 ;; the other operand.
4520 (define_expand "move_doubleword_fpr<mode>"
4521 [(set (match_operand:SPLITF 0)
4522 (match_operand:SPLITF 1))]
4525 if (FP_REG_RTX_P (operands[0]))
4527 rtx low = mips_subword (operands[1], 0);
4528 rtx high = mips_subword (operands[1], 1);
4529 emit_insn (gen_load_low<mode> (operands[0], low));
4530 if (TARGET_FLOAT64 && !TARGET_64BIT)
4531 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4533 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4537 rtx low = mips_subword (operands[0], 0);
4538 rtx high = mips_subword (operands[0], 1);
4539 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4540 if (TARGET_FLOAT64 && !TARGET_64BIT)
4541 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4543 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4548 ;; Load the low word of operand 0 with operand 1.
4549 (define_insn "load_low<mode>"
4550 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4551 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4555 operands[0] = mips_subword (operands[0], 0);
4556 return mips_output_move (operands[0], operands[1]);
4558 [(set_attr "move_type" "mtc,fpload")
4559 (set_attr "mode" "<HALFMODE>")])
4561 ;; Load the high word of operand 0 from operand 1, preserving the value
4563 (define_insn "load_high<mode>"
4564 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4565 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4566 (match_operand:SPLITF 2 "register_operand" "0,0")]
4570 operands[0] = mips_subword (operands[0], 1);
4571 return mips_output_move (operands[0], operands[1]);
4573 [(set_attr "move_type" "mtc,fpload")
4574 (set_attr "mode" "<HALFMODE>")])
4576 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4577 ;; high word and 0 to store the low word.
4578 (define_insn "store_word<mode>"
4579 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4580 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4581 (match_operand 2 "const_int_operand")]
4582 UNSPEC_STORE_WORD))]
4585 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4586 return mips_output_move (operands[0], operands[1]);
4588 [(set_attr "move_type" "mfc,fpstore")
4589 (set_attr "mode" "<HALFMODE>")])
4591 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4592 ;; value in the low word.
4593 (define_insn "mthc1<mode>"
4594 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4595 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4596 (match_operand:SPLITF 2 "register_operand" "0")]
4598 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4600 [(set_attr "move_type" "mtc")
4601 (set_attr "mode" "<HALFMODE>")])
4603 ;; Move high word of operand 1 to operand 0 using mfhc1.
4604 (define_insn "mfhc1<mode>"
4605 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4606 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4608 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4610 [(set_attr "move_type" "mfc")
4611 (set_attr "mode" "<HALFMODE>")])
4613 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4614 (define_expand "load_const_gp_<mode>"
4615 [(set (match_operand:P 0 "register_operand" "=d")
4616 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4618 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4619 ;; of _gp from the start of this function. Operand 1 is the incoming
4620 ;; function address.
4621 (define_insn_and_split "loadgp_newabi_<mode>"
4622 [(set (match_operand:P 0 "register_operand" "=d")
4623 (unspec_volatile:P [(match_operand:P 1)
4624 (match_operand:P 2 "register_operand" "d")]
4626 "mips_current_loadgp_style () == LOADGP_NEWABI"
4629 [(set (match_dup 0) (match_dup 3))
4630 (set (match_dup 0) (match_dup 4))
4631 (set (match_dup 0) (match_dup 5))]
4633 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4634 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4635 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4637 [(set_attr "length" "12")])
4639 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4640 (define_insn_and_split "loadgp_absolute_<mode>"
4641 [(set (match_operand:P 0 "register_operand" "=d")
4642 (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4643 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4648 mips_emit_move (operands[0], operands[1]);
4651 [(set_attr "length" "8")])
4653 ;; This blockage instruction prevents the gp load from being
4654 ;; scheduled after an implicit use of gp. It also prevents
4655 ;; the load from being deleted as dead.
4656 (define_insn "loadgp_blockage"
4657 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4660 [(set_attr "type" "ghost")
4661 (set_attr "mode" "none")])
4663 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4664 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4665 (define_insn_and_split "loadgp_rtp_<mode>"
4666 [(set (match_operand:P 0 "register_operand" "=d")
4667 (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
4668 (match_operand:P 2 "symbol_ref_operand")]
4670 "mips_current_loadgp_style () == LOADGP_RTP"
4673 [(set (match_dup 0) (high:P (match_dup 3)))
4674 (set (match_dup 0) (unspec:P [(match_dup 0)
4675 (match_dup 3)] UNSPEC_LOAD_GOT))
4676 (set (match_dup 0) (unspec:P [(match_dup 0)
4677 (match_dup 4)] UNSPEC_LOAD_GOT))]
4679 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
4680 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
4682 [(set_attr "length" "12")])
4684 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
4685 ;; global pointer and operand 1 is the MIPS16 register that holds
4686 ;; the required value.
4687 (define_insn_and_split "copygp_mips16"
4688 [(set (match_operand:SI 0 "register_operand" "=y")
4689 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
4693 "&& reload_completed"
4694 [(set (match_dup 0) (match_dup 1))])
4696 ;; Emit a .cprestore directive, which normally expands to a single store
4697 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4698 ;; code so that jals inside inline asms will work correctly.
4699 (define_insn "cprestore"
4700 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4705 if (set_nomacro && which_alternative == 1)
4706 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4708 return ".cprestore\t%0";
4710 [(set_attr "type" "store")
4711 (set_attr "length" "4,12")])
4713 ;; Expand in-line code to clear the instruction cache between operand[0] and
4715 (define_expand "clear_cache"
4716 [(match_operand 0 "pmode_register_operand")
4717 (match_operand 1 "pmode_register_operand")]
4723 mips_expand_synci_loop (operands[0], operands[1]);
4724 emit_insn (gen_sync ());
4725 emit_insn (Pmode == SImode
4726 ? gen_clear_hazard_si ()
4727 : gen_clear_hazard_di ());
4729 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4731 rtx len = gen_reg_rtx (Pmode);
4732 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4733 MIPS_ICACHE_SYNC (operands[0], len);
4739 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4743 (define_insn "synci"
4744 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4749 (define_insn "rdhwr_synci_step_<mode>"
4750 [(set (match_operand:P 0 "register_operand" "=d")
4751 (unspec_volatile [(const_int 1)]
4756 (define_insn "clear_hazard_<mode>"
4757 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4758 (clobber (reg:P 31))]
4761 return "%(%<bal\t1f\n"
4763 "1:\t<d>addiu\t$31,$31,12\n"
4767 [(set_attr "length" "20")])
4769 ;; Cache operations for R4000-style caches.
4770 (define_insn "mips_cache"
4771 [(set (mem:BLK (scratch))
4772 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
4773 (match_operand:QI 1 "address_operand" "p")]
4774 UNSPEC_MIPS_CACHE))]
4778 ;; Similar, but with the operands hard-coded to an R10K cache barrier
4779 ;; operation. We keep the pattern distinct so that we can identify
4780 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
4781 ;; the operation is never inserted into a delay slot.
4782 (define_insn "r10k_cache_barrier"
4783 [(set (mem:BLK (scratch))
4784 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
4787 [(set_attr "can_delay" "no")])
4789 ;; Block moves, see mips.c for more details.
4790 ;; Argument 0 is the destination
4791 ;; Argument 1 is the source
4792 ;; Argument 2 is the length
4793 ;; Argument 3 is the alignment
4795 (define_expand "movmemsi"
4796 [(parallel [(set (match_operand:BLK 0 "general_operand")
4797 (match_operand:BLK 1 "general_operand"))
4798 (use (match_operand:SI 2 ""))
4799 (use (match_operand:SI 3 "const_int_operand"))])]
4800 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4802 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4809 ;; ....................
4813 ;; ....................
4815 (define_expand "<optab><mode>3"
4816 [(set (match_operand:GPR 0 "register_operand")
4817 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4818 (match_operand:SI 2 "arith_operand")))]
4821 /* On the mips16, a shift of more than 8 is a four byte instruction,
4822 so, for a shift between 8 and 16, it is just as fast to do two
4823 shifts of 8 or less. If there is a lot of shifting going on, we
4824 may win in CSE. Otherwise combine will put the shifts back
4825 together again. This can be called by mips_function_arg, so we must
4826 be careful not to allocate a new register if we've reached the
4830 && GET_CODE (operands[2]) == CONST_INT
4831 && INTVAL (operands[2]) > 8
4832 && INTVAL (operands[2]) <= 16
4833 && !reload_in_progress
4834 && !reload_completed)
4836 rtx temp = gen_reg_rtx (<MODE>mode);
4838 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4839 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4840 GEN_INT (INTVAL (operands[2]) - 8)));
4845 (define_insn "*<optab><mode>3"
4846 [(set (match_operand:GPR 0 "register_operand" "=d")
4847 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4848 (match_operand:SI 2 "arith_operand" "dI")))]
4851 if (GET_CODE (operands[2]) == CONST_INT)
4852 operands[2] = GEN_INT (INTVAL (operands[2])
4853 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4855 return "<d><insn>\t%0,%1,%2";
4857 [(set_attr "type" "shift")
4858 (set_attr "mode" "<MODE>")])
4860 (define_insn "*<optab>si3_extend"
4861 [(set (match_operand:DI 0 "register_operand" "=d")
4863 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4864 (match_operand:SI 2 "arith_operand" "dI"))))]
4865 "TARGET_64BIT && !TARGET_MIPS16"
4867 if (GET_CODE (operands[2]) == CONST_INT)
4868 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4870 return "<insn>\t%0,%1,%2";
4872 [(set_attr "type" "shift")
4873 (set_attr "mode" "SI")])
4875 (define_insn "*<optab>si3_mips16"
4876 [(set (match_operand:SI 0 "register_operand" "=d,d")
4877 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4878 (match_operand:SI 2 "arith_operand" "d,I")))]
4881 if (which_alternative == 0)
4882 return "<insn>\t%0,%2";
4884 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4885 return "<insn>\t%0,%1,%2";
4887 [(set_attr "type" "shift")
4888 (set_attr "mode" "SI")
4889 (set_attr_alternative "length"
4891 (if_then_else (match_operand 2 "m16_uimm3_b")
4895 ;; We need separate DImode MIPS16 patterns because of the irregularity
4897 (define_insn "*ashldi3_mips16"
4898 [(set (match_operand:DI 0 "register_operand" "=d,d")
4899 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4900 (match_operand:SI 2 "arith_operand" "d,I")))]
4901 "TARGET_64BIT && TARGET_MIPS16"
4903 if (which_alternative == 0)
4904 return "dsll\t%0,%2";
4906 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4907 return "dsll\t%0,%1,%2";
4909 [(set_attr "type" "shift")
4910 (set_attr "mode" "DI")
4911 (set_attr_alternative "length"
4913 (if_then_else (match_operand 2 "m16_uimm3_b")
4917 (define_insn "*ashrdi3_mips16"
4918 [(set (match_operand:DI 0 "register_operand" "=d,d")
4919 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4920 (match_operand:SI 2 "arith_operand" "d,I")))]
4921 "TARGET_64BIT && TARGET_MIPS16"
4923 if (GET_CODE (operands[2]) == CONST_INT)
4924 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4926 return "dsra\t%0,%2";
4928 [(set_attr "type" "shift")
4929 (set_attr "mode" "DI")
4930 (set_attr_alternative "length"
4932 (if_then_else (match_operand 2 "m16_uimm3_b")
4936 (define_insn "*lshrdi3_mips16"
4937 [(set (match_operand:DI 0 "register_operand" "=d,d")
4938 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4939 (match_operand:SI 2 "arith_operand" "d,I")))]
4940 "TARGET_64BIT && TARGET_MIPS16"
4942 if (GET_CODE (operands[2]) == CONST_INT)
4943 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4945 return "dsrl\t%0,%2";
4947 [(set_attr "type" "shift")
4948 (set_attr "mode" "DI")
4949 (set_attr_alternative "length"
4951 (if_then_else (match_operand 2 "m16_uimm3_b")
4955 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4958 [(set (match_operand:GPR 0 "d_operand")
4959 (any_shift:GPR (match_operand:GPR 1 "d_operand")
4960 (match_operand:GPR 2 "const_int_operand")))]
4961 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4962 && INTVAL (operands[2]) > 8
4963 && INTVAL (operands[2]) <= 16"
4964 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4965 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4966 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4968 ;; If we load a byte on the mips16 as a bitfield, the resulting
4969 ;; sequence of instructions is too complicated for combine, because it
4970 ;; involves four instructions: a load, a shift, a constant load into a
4971 ;; register, and an and (the key problem here is that the mips16 does
4972 ;; not have and immediate). We recognize a shift of a load in order
4973 ;; to make it simple enough for combine to understand.
4975 ;; The length here is the worst case: the length of the split version
4976 ;; will be more accurate.
4977 (define_insn_and_split ""
4978 [(set (match_operand:SI 0 "register_operand" "=d")
4979 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4980 (match_operand:SI 2 "immediate_operand" "I")))]
4984 [(set (match_dup 0) (match_dup 1))
4985 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4987 [(set_attr "type" "load")
4988 (set_attr "mode" "SI")
4989 (set_attr "length" "16")])
4991 (define_insn "rotr<mode>3"
4992 [(set (match_operand:GPR 0 "register_operand" "=d")
4993 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4994 (match_operand:SI 2 "arith_operand" "dI")))]
4997 if (GET_CODE (operands[2]) == CONST_INT)
4998 gcc_assert (INTVAL (operands[2]) >= 0
4999 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5001 return "<d>ror\t%0,%1,%2";
5003 [(set_attr "type" "shift")
5004 (set_attr "mode" "<MODE>")])
5007 ;; ....................
5009 ;; CONDITIONAL BRANCHES
5011 ;; ....................
5013 ;; Conditional branches on floating-point equality tests.
5015 (define_insn "*branch_fp"
5018 (match_operator 0 "equality_operator"
5019 [(match_operand:CC 2 "register_operand" "z")
5021 (label_ref (match_operand 1 "" ""))
5025 return mips_output_conditional_branch (insn, operands,
5026 MIPS_BRANCH ("b%F0", "%Z2%1"),
5027 MIPS_BRANCH ("b%W0", "%Z2%1"));
5029 [(set_attr "type" "branch")
5030 (set_attr "mode" "none")])
5032 (define_insn "*branch_fp_inverted"
5035 (match_operator 0 "equality_operator"
5036 [(match_operand:CC 2 "register_operand" "z")
5039 (label_ref (match_operand 1 "" ""))))]
5042 return mips_output_conditional_branch (insn, operands,
5043 MIPS_BRANCH ("b%W0", "%Z2%1"),
5044 MIPS_BRANCH ("b%F0", "%Z2%1"));
5046 [(set_attr "type" "branch")
5047 (set_attr "mode" "none")])
5049 ;; Conditional branches on ordered comparisons with zero.
5051 (define_insn "*branch_order<mode>"
5054 (match_operator 0 "order_operator"
5055 [(match_operand:GPR 2 "register_operand" "d")
5057 (label_ref (match_operand 1 "" ""))
5060 { return mips_output_order_conditional_branch (insn, operands, false); }
5061 [(set_attr "type" "branch")
5062 (set_attr "mode" "none")])
5064 (define_insn "*branch_order<mode>_inverted"
5067 (match_operator 0 "order_operator"
5068 [(match_operand:GPR 2 "register_operand" "d")
5071 (label_ref (match_operand 1 "" ""))))]
5073 { return mips_output_order_conditional_branch (insn, operands, true); }
5074 [(set_attr "type" "branch")
5075 (set_attr "mode" "none")])
5077 ;; Conditional branch on equality comparison.
5079 (define_insn "*branch_equality<mode>"
5082 (match_operator 0 "equality_operator"
5083 [(match_operand:GPR 2 "register_operand" "d")
5084 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5085 (label_ref (match_operand 1 "" ""))
5089 return mips_output_conditional_branch (insn, operands,
5090 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
5091 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
5093 [(set_attr "type" "branch")
5094 (set_attr "mode" "none")])
5096 (define_insn "*branch_equality<mode>_inverted"
5099 (match_operator 0 "equality_operator"
5100 [(match_operand:GPR 2 "register_operand" "d")
5101 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5103 (label_ref (match_operand 1 "" ""))))]
5106 return mips_output_conditional_branch (insn, operands,
5107 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
5108 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
5110 [(set_attr "type" "branch")
5111 (set_attr "mode" "none")])
5115 (define_insn "*branch_equality<mode>_mips16"
5118 (match_operator 0 "equality_operator"
5119 [(match_operand:GPR 1 "register_operand" "d,t")
5121 (match_operand 2 "pc_or_label_operand" "")
5122 (match_operand 3 "pc_or_label_operand" "")))]
5125 if (operands[2] != pc_rtx)
5127 if (which_alternative == 0)
5128 return "b%C0z\t%1,%2";
5130 return "bt%C0z\t%2";
5134 if (which_alternative == 0)
5135 return "b%N0z\t%1,%3";
5137 return "bt%N0z\t%3";
5140 [(set_attr "type" "branch")
5141 (set_attr "mode" "none")])
5143 (define_expand "cbranch<mode>4"
5145 (if_then_else (match_operator 0 "comparison_operator"
5146 [(match_operand:GPR 1 "register_operand")
5147 (match_operand:GPR 2 "nonmemory_operand")])
5148 (label_ref (match_operand 3 ""))
5152 mips_expand_conditional_branch (operands);
5156 (define_expand "cbranch<mode>4"
5158 (if_then_else (match_operator 0 "comparison_operator"
5159 [(match_operand:SCALARF 1 "register_operand")
5160 (match_operand:SCALARF 2 "register_operand")])
5161 (label_ref (match_operand 3 ""))
5165 mips_expand_conditional_branch (operands);
5169 ;; Used to implement built-in functions.
5170 (define_expand "condjump"
5172 (if_then_else (match_operand 0)
5173 (label_ref (match_operand 1))
5176 ;; Branch if bit is set/clear.
5178 (define_insn "*branch_bit<bbv><mode>"
5181 (equality_op (zero_extract:GPR
5182 (match_operand:GPR 0 "register_operand" "d")
5184 (match_operand 2 "const_int_operand" ""))
5186 (label_ref (match_operand 1 ""))
5188 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5191 mips_output_conditional_branch (insn, operands,
5192 MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"),
5193 MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"));
5195 [(set_attr "type" "branch")
5196 (set_attr "mode" "none")
5197 (set_attr "branch_likely" "no")])
5199 (define_insn "*branch_bit<bbv><mode>_inverted"
5202 (equality_op (zero_extract:GPR
5203 (match_operand:GPR 0 "register_operand" "d")
5205 (match_operand 2 "const_int_operand" ""))
5208 (label_ref (match_operand 1 ""))))]
5209 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5212 mips_output_conditional_branch (insn, operands,
5213 MIPS_BRANCH ("bbit<bbinv>", "%0,%2,%1"),
5214 MIPS_BRANCH ("bbit<bbv>", "%0,%2,%1"));
5216 [(set_attr "type" "branch")
5217 (set_attr "mode" "none")
5218 (set_attr "branch_likely" "no")])
5221 ;; ....................
5223 ;; SETTING A REGISTER FROM A COMPARISON
5225 ;; ....................
5227 ;; Destination is always set in SI mode.
5229 (define_expand "cstore<mode>4"
5230 [(set (match_operand:SI 0 "register_operand")
5231 (match_operator:SI 1 "mips_cstore_operator"
5232 [(match_operand:GPR 2 "register_operand")
5233 (match_operand:GPR 3 "nonmemory_operand")]))]
5236 mips_expand_scc (operands);
5240 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5241 [(set (match_operand:GPR2 0 "register_operand" "=d")
5242 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5244 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5246 [(set_attr "type" "slt")
5247 (set_attr "mode" "<GPR:MODE>")])
5249 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5250 [(set (match_operand:GPR2 0 "register_operand" "=t")
5251 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5253 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5255 [(set_attr "type" "slt")
5256 (set_attr "mode" "<GPR:MODE>")])
5258 ;; Generate sltiu unless using seq results in better code.
5259 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5260 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5261 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5262 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5268 [(set_attr "type" "slt")
5269 (set_attr "mode" "<GPR:MODE>")])
5271 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5272 [(set (match_operand:GPR2 0 "register_operand" "=d")
5273 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5275 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5277 [(set_attr "type" "slt")
5278 (set_attr "mode" "<GPR:MODE>")])
5280 ;; Generate sltu unless using sne results in better code.
5281 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5282 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5283 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5284 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5290 [(set_attr "type" "slt")
5291 (set_attr "mode" "<GPR:MODE>")])
5293 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5294 [(set (match_operand:GPR2 0 "register_operand" "=d")
5295 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5296 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5299 [(set_attr "type" "slt")
5300 (set_attr "mode" "<GPR:MODE>")])
5302 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5303 [(set (match_operand:GPR2 0 "register_operand" "=t")
5304 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5305 (match_operand:GPR 2 "register_operand" "d")))]
5308 [(set_attr "type" "slt")
5309 (set_attr "mode" "<GPR:MODE>")])
5311 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5312 [(set (match_operand:GPR2 0 "register_operand" "=d")
5313 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5317 [(set_attr "type" "slt")
5318 (set_attr "mode" "<GPR:MODE>")])
5320 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5321 [(set (match_operand:GPR2 0 "register_operand" "=d")
5322 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5323 (match_operand:GPR 2 "arith_operand" "dI")))]
5326 [(set_attr "type" "slt")
5327 (set_attr "mode" "<GPR:MODE>")])
5329 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5330 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5331 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5332 (match_operand:GPR 2 "arith_operand" "d,I")))]
5335 [(set_attr "type" "slt")
5336 (set_attr "mode" "<GPR:MODE>")
5337 (set_attr_alternative "length"
5339 (if_then_else (match_operand 2 "m16_uimm8_1")
5343 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5344 [(set (match_operand:GPR2 0 "register_operand" "=d")
5345 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5346 (match_operand:GPR 2 "sle_operand" "")))]
5349 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5350 return "slt<u>\t%0,%1,%2";
5352 [(set_attr "type" "slt")
5353 (set_attr "mode" "<GPR:MODE>")])
5355 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5356 [(set (match_operand:GPR2 0 "register_operand" "=t")
5357 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5358 (match_operand:GPR 2 "sle_operand" "")))]
5361 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5362 return "slt<u>\t%1,%2";
5364 [(set_attr "type" "slt")
5365 (set_attr "mode" "<GPR:MODE>")
5366 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5371 ;; ....................
5373 ;; FLOATING POINT COMPARISONS
5375 ;; ....................
5377 (define_insn "s<code>_<mode>"
5378 [(set (match_operand:CC 0 "register_operand" "=z")
5379 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5380 (match_operand:SCALARF 2 "register_operand" "f")))]
5382 "c.<fcond>.<fmt>\t%Z0%1,%2"
5383 [(set_attr "type" "fcmp")
5384 (set_attr "mode" "FPSW")])
5386 (define_insn "s<code>_<mode>"
5387 [(set (match_operand:CC 0 "register_operand" "=z")
5388 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5389 (match_operand:SCALARF 2 "register_operand" "f")))]
5391 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5392 [(set_attr "type" "fcmp")
5393 (set_attr "mode" "FPSW")])
5396 ;; ....................
5398 ;; UNCONDITIONAL BRANCHES
5400 ;; ....................
5402 ;; Unconditional branches.
5406 (label_ref (match_operand 0 "" "")))]
5411 if (get_attr_length (insn) <= 8)
5412 return "%*b\t%l0%/";
5415 output_asm_insn (mips_output_load_label (), operands);
5416 return "%*jr\t%@%/%]";
5420 return "%*j\t%l0%/";
5422 [(set_attr "type" "jump")
5423 (set_attr "mode" "none")
5424 (set (attr "length")
5425 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5426 ;; in range, otherwise load the address of the branch target into
5427 ;; $at and then jump to it.
5429 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5430 (lt (abs (minus (match_dup 0)
5431 (plus (pc) (const_int 4))))
5432 (const_int 131072)))
5433 (const_int 4) (const_int 16)))])
5435 ;; We need a different insn for the mips16, because a mips16 branch
5436 ;; does not have a delay slot.
5440 (label_ref (match_operand 0 "" "")))]
5443 [(set_attr "type" "branch")
5444 (set_attr "mode" "none")])
5446 (define_expand "indirect_jump"
5447 [(set (pc) (match_operand 0 "register_operand"))]
5450 operands[0] = force_reg (Pmode, operands[0]);
5451 if (Pmode == SImode)
5452 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5454 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5458 (define_insn "indirect_jump<mode>"
5459 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5462 [(set_attr "type" "jump")
5463 (set_attr "mode" "none")])
5465 (define_expand "tablejump"
5467 (match_operand 0 "register_operand"))
5468 (use (label_ref (match_operand 1 "")))]
5471 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5472 operands[0] = expand_binop (Pmode, add_optab,
5473 convert_to_mode (Pmode, operands[0], false),
5474 gen_rtx_LABEL_REF (Pmode, operands[1]),
5476 else if (TARGET_GPWORD)
5477 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5478 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5479 else if (TARGET_RTP_PIC)
5481 /* When generating RTP PIC, we use case table entries that are relative
5482 to the start of the function. Add the function's address to the
5484 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5485 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5486 start, 0, 0, OPTAB_WIDEN);
5489 if (Pmode == SImode)
5490 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5492 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5496 (define_insn "tablejump<mode>"
5498 (match_operand:P 0 "register_operand" "d"))
5499 (use (label_ref (match_operand 1 "" "")))]
5502 [(set_attr "type" "jump")
5503 (set_attr "mode" "none")])
5505 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5506 ;; While it is possible to either pull it off the stack (in the
5507 ;; o32 case) or recalculate it given t9 and our target label,
5508 ;; it takes 3 or 4 insns to do so.
5510 (define_expand "builtin_setjmp_setup"
5511 [(use (match_operand 0 "register_operand"))]
5516 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5517 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5521 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5522 ;; that older code did recalculate the gp from $25. Continue to jump through
5523 ;; $25 for compatibility (we lose nothing by doing so).
5525 (define_expand "builtin_longjmp"
5526 [(use (match_operand 0 "register_operand"))]
5529 /* The elements of the buffer are, in order: */
5530 int W = GET_MODE_SIZE (Pmode);
5531 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5532 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5533 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5534 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5535 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5536 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5537 The target is bound to be using $28 as the global pointer
5538 but the current function might not be. */
5539 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5541 /* This bit is similar to expand_builtin_longjmp except that it
5542 restores $gp as well. */
5543 mips_emit_move (hard_frame_pointer_rtx, fp);
5544 mips_emit_move (pv, lab);
5545 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5546 mips_emit_move (gp, gpv);
5547 emit_use (hard_frame_pointer_rtx);
5548 emit_use (stack_pointer_rtx);
5550 emit_indirect_jump (pv);
5555 ;; ....................
5557 ;; Function prologue/epilogue
5559 ;; ....................
5562 (define_expand "prologue"
5566 mips_expand_prologue ();
5570 ;; Block any insns from being moved before this point, since the
5571 ;; profiling call to mcount can use various registers that aren't
5572 ;; saved or used to pass arguments.
5574 (define_insn "blockage"
5575 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5578 [(set_attr "type" "ghost")
5579 (set_attr "mode" "none")])
5581 (define_expand "epilogue"
5585 mips_expand_epilogue (false);
5589 (define_expand "sibcall_epilogue"
5593 mips_expand_epilogue (true);
5597 ;; Trivial return. Make it look like a normal return insn as that
5598 ;; allows jump optimizations to work better.
5600 (define_expand "return"
5602 "mips_can_use_return_insn ()"
5603 { mips_expand_before_return (); })
5605 (define_insn "*return"
5607 "mips_can_use_return_insn ()"
5609 [(set_attr "type" "jump")
5610 (set_attr "mode" "none")])
5614 (define_insn "return_internal"
5616 (use (match_operand 0 "pmode_register_operand" ""))]
5619 [(set_attr "type" "jump")
5620 (set_attr "mode" "none")])
5622 ;; Exception return.
5623 (define_insn "mips_eret"
5625 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
5628 [(set_attr "type" "trap")
5629 (set_attr "mode" "none")])
5631 ;; Debug exception return.
5632 (define_insn "mips_deret"
5634 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
5637 [(set_attr "type" "trap")
5638 (set_attr "mode" "none")])
5640 ;; Disable interrupts.
5641 (define_insn "mips_di"
5642 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
5645 [(set_attr "type" "trap")
5646 (set_attr "mode" "none")])
5648 ;; Execution hazard barrier.
5649 (define_insn "mips_ehb"
5650 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
5653 [(set_attr "type" "trap")
5654 (set_attr "mode" "none")])
5656 ;; Read GPR from previous shadow register set.
5657 (define_insn "mips_rdpgpr"
5658 [(set (match_operand:SI 0 "register_operand" "=d")
5659 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
5663 [(set_attr "type" "move")
5664 (set_attr "mode" "SI")])
5666 ;; Move involving COP0 registers.
5667 (define_insn "cop0_move"
5668 [(set (match_operand:SI 0 "register_operand" "=B,d")
5669 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
5672 { return mips_output_move (operands[0], operands[1]); }
5673 [(set_attr "type" "mtc,mfc")
5674 (set_attr "mode" "SI")])
5676 ;; This is used in compiling the unwind routines.
5677 (define_expand "eh_return"
5678 [(use (match_operand 0 "general_operand"))]
5681 if (GET_MODE (operands[0]) != word_mode)
5682 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5684 emit_insn (gen_eh_set_lr_di (operands[0]));
5686 emit_insn (gen_eh_set_lr_si (operands[0]));
5690 ;; Clobber the return address on the stack. We can't expand this
5691 ;; until we know where it will be put in the stack frame.
5693 (define_insn "eh_set_lr_si"
5694 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5695 (clobber (match_scratch:SI 1 "=&d"))]
5699 (define_insn "eh_set_lr_di"
5700 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5701 (clobber (match_scratch:DI 1 "=&d"))]
5706 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5707 (clobber (match_scratch 1))]
5711 mips_set_return_address (operands[0], operands[1]);
5715 (define_expand "exception_receiver"
5719 /* See the comment above load_call<mode> for details. */
5720 emit_insn (gen_set_got_version ());
5722 /* If we have a call-clobbered $gp, restore it from its save slot. */
5723 if (HAVE_restore_gp)
5724 emit_insn (gen_restore_gp ());
5728 (define_expand "nonlocal_goto_receiver"
5732 /* See the comment above load_call<mode> for details. */
5733 emit_insn (gen_set_got_version ());
5737 ;; Restore $gp from its .cprestore stack slot. The instruction remains
5738 ;; volatile until all uses of $28 are exposed.
5739 (define_insn_and_split "restore_gp"
5741 (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
5742 (clobber (match_scratch:SI 0 "=&d"))]
5743 "TARGET_CALL_CLOBBERED_GP"
5745 "&& reload_completed"
5748 mips_restore_gp (operands[0]);
5751 [(set_attr "type" "load")
5752 (set_attr "length" "12")])
5755 ;; ....................
5759 ;; ....................
5761 ;; Instructions to load a call address from the GOT. The address might
5762 ;; point to a function or to a lazy binding stub. In the latter case,
5763 ;; the stub will use the dynamic linker to resolve the function, which
5764 ;; in turn will change the GOT entry to point to the function's real
5767 ;; This means that every call, even pure and constant ones, can
5768 ;; potentially modify the GOT entry. And once a stub has been called,
5769 ;; we must not call it again.
5771 ;; We represent this restriction using an imaginary, fixed, call-saved
5772 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
5773 ;; live throughout the function and to change its value after every
5774 ;; potential call site. This stops any rtx value that uses the register
5775 ;; from being computed before an earlier call. To do this, we:
5777 ;; - Ensure that the register is live on entry to the function,
5778 ;; so that it is never thought to be used uninitalized.
5780 ;; - Ensure that the register is live on exit from the function,
5781 ;; so that it is live throughout.
5783 ;; - Make each call (lazily-bound or not) use the current value
5784 ;; of GOT_VERSION_REGNUM, so that updates of the register are
5785 ;; not moved across call boundaries.
5787 ;; - Add "ghost" definitions of the register to the beginning of
5788 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
5789 ;; edges may involve calls that normal paths don't. (E.g. the
5790 ;; unwinding code that handles a non-call exception may change
5791 ;; lazily-bound GOT entries.) We do this by making the
5792 ;; exception_receiver and nonlocal_goto_receiver expanders emit
5793 ;; a set_got_version instruction.
5795 ;; - After each call (lazily-bound or not), use a "ghost"
5796 ;; update_got_version instruction to change the register's value.
5797 ;; This instruction mimics the _possible_ effect of the dynamic
5798 ;; resolver during the call and it remains live even if the call
5799 ;; itself becomes dead.
5801 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
5802 ;; The register is therefore not a valid register_operand
5803 ;; and cannot be moved to or from other registers.
5805 ;; Convenience expander that generates the rhs of a load_call<mode> insn.
5806 (define_expand "unspec_call<mode>"
5807 [(unspec:P [(match_operand:P 0)
5809 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL)])
5811 (define_insn "load_call<mode>"
5812 [(set (match_operand:P 0 "register_operand" "=d")
5813 (unspec:P [(match_operand:P 1 "register_operand" "d")
5814 (match_operand:P 2 "immediate_operand" "")
5815 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
5817 "<load>\t%0,%R2(%1)"
5818 [(set_attr "got" "load")
5819 (set_attr "mode" "<MODE>")])
5821 (define_insn "set_got_version"
5822 [(set (reg:SI GOT_VERSION_REGNUM)
5823 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
5826 [(set_attr "type" "ghost")])
5828 (define_insn "update_got_version"
5829 [(set (reg:SI GOT_VERSION_REGNUM)
5830 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
5833 [(set_attr "type" "ghost")])
5835 ;; Sibling calls. All these patterns use jump instructions.
5837 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5838 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5839 ;; is defined in terms of call_insn_operand, the same is true of the
5842 ;; When we use an indirect jump, we need a register that will be
5843 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5844 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5845 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5848 (define_expand "sibcall"
5849 [(parallel [(call (match_operand 0 "")
5850 (match_operand 1 ""))
5851 (use (match_operand 2 "")) ;; next_arg_reg
5852 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5855 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
5856 operands[1], operands[2], false);
5860 (define_insn "sibcall_internal"
5861 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5862 (match_operand 1 "" ""))]
5863 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5864 { return MIPS_CALL ("j", operands, 0); }
5865 [(set_attr "type" "call")])
5867 (define_expand "sibcall_value"
5868 [(parallel [(set (match_operand 0 "")
5869 (call (match_operand 1 "")
5870 (match_operand 2 "")))
5871 (use (match_operand 3 ""))])] ;; next_arg_reg
5874 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
5875 operands[2], operands[3], false);
5879 (define_insn "sibcall_value_internal"
5880 [(set (match_operand 0 "register_operand" "")
5881 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5882 (match_operand 2 "" "")))]
5883 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5884 { return MIPS_CALL ("j", operands, 1); }
5885 [(set_attr "type" "call")])
5887 (define_insn "sibcall_value_multiple_internal"
5888 [(set (match_operand 0 "register_operand" "")
5889 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5890 (match_operand 2 "" "")))
5891 (set (match_operand 3 "register_operand" "")
5892 (call (mem:SI (match_dup 1))
5894 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5895 { return MIPS_CALL ("j", operands, 1); }
5896 [(set_attr "type" "call")])
5898 (define_expand "call"
5899 [(parallel [(call (match_operand 0 "")
5900 (match_operand 1 ""))
5901 (use (match_operand 2 "")) ;; next_arg_reg
5902 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5905 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
5906 operands[1], operands[2], false);
5910 ;; This instruction directly corresponds to an assembly-language "jal".
5911 ;; There are four cases:
5914 ;; Both symbolic and register destinations are OK. The pattern
5915 ;; always expands to a single mips instruction.
5917 ;; - -mabicalls/-mno-explicit-relocs:
5918 ;; Again, both symbolic and register destinations are OK.
5919 ;; The call is treated as a multi-instruction black box.
5921 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5922 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5925 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5926 ;; Only "jal $25" is allowed. The call is actually two instructions:
5927 ;; "jalr $25" followed by an insn to reload $gp.
5929 ;; In the last case, we can generate the individual instructions with
5930 ;; a define_split. There are several things to be wary of:
5932 ;; - We can't expose the load of $gp before reload. If we did,
5933 ;; it might get removed as dead, but reload can introduce new
5934 ;; uses of $gp by rematerializing constants.
5936 ;; - We shouldn't restore $gp after calls that never return.
5937 ;; It isn't valid to insert instructions between a noreturn
5938 ;; call and the following barrier.
5940 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5941 ;; instruction preserves $gp and so have no effect on its liveness.
5942 ;; But once we generate the separate insns, it becomes obvious that
5943 ;; $gp is not live on entry to the call.
5945 ;; ??? The operands[2] = insn check is a hack to make the original insn
5946 ;; available to the splitter.
5947 (define_insn_and_split "call_internal"
5948 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5949 (match_operand 1 "" ""))
5950 (clobber (reg:SI 31))]
5952 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5953 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5956 mips_split_call (operands[2], gen_call_split (operands[0], operands[1]));
5959 [(set_attr "jal" "indirect,direct")])
5961 (define_insn "call_split"
5962 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5963 (match_operand 1 "" ""))
5964 (clobber (reg:SI 31))
5965 (clobber (reg:SI 28))]
5966 "TARGET_SPLIT_CALLS"
5967 { return MIPS_CALL ("jal", operands, 0); }
5968 [(set_attr "type" "call")])
5970 ;; A pattern for calls that must be made directly. It is used for
5971 ;; MIPS16 calls that the linker may need to redirect to a hard-float
5972 ;; stub; the linker relies on the call relocation type to detect when
5973 ;; such redirection is needed.
5974 (define_insn_and_split "call_internal_direct"
5975 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5978 (clobber (reg:SI 31))]
5980 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5981 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5984 mips_split_call (operands[2],
5985 gen_call_direct_split (operands[0], operands[1]));
5988 [(set_attr "type" "call")])
5990 (define_insn "call_direct_split"
5991 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5994 (clobber (reg:SI 31))
5995 (clobber (reg:SI 28))]
5996 "TARGET_SPLIT_CALLS"
5997 { return MIPS_CALL ("jal", operands, 0); }
5998 [(set_attr "type" "call")])
6000 (define_expand "call_value"
6001 [(parallel [(set (match_operand 0 "")
6002 (call (match_operand 1 "")
6003 (match_operand 2 "")))
6004 (use (match_operand 3 ""))])] ;; next_arg_reg
6007 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6008 operands[2], operands[3], false);
6012 ;; See comment for call_internal.
6013 (define_insn_and_split "call_value_internal"
6014 [(set (match_operand 0 "register_operand" "")
6015 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6016 (match_operand 2 "" "")))
6017 (clobber (reg:SI 31))]
6019 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6020 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6023 mips_split_call (operands[3],
6024 gen_call_value_split (operands[0], operands[1],
6028 [(set_attr "jal" "indirect,direct")])
6030 (define_insn "call_value_split"
6031 [(set (match_operand 0 "register_operand" "")
6032 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6033 (match_operand 2 "" "")))
6034 (clobber (reg:SI 31))
6035 (clobber (reg:SI 28))]
6036 "TARGET_SPLIT_CALLS"
6037 { return MIPS_CALL ("jal", operands, 1); }
6038 [(set_attr "type" "call")])
6040 ;; See call_internal_direct.
6041 (define_insn_and_split "call_value_internal_direct"
6042 [(set (match_operand 0 "register_operand")
6043 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6046 (clobber (reg:SI 31))]
6048 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6049 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
6052 mips_split_call (operands[3],
6053 gen_call_value_direct_split (operands[0], operands[1],
6057 [(set_attr "type" "call")])
6059 (define_insn "call_value_direct_split"
6060 [(set (match_operand 0 "register_operand")
6061 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6064 (clobber (reg:SI 31))
6065 (clobber (reg:SI 28))]
6066 "TARGET_SPLIT_CALLS"
6067 { return MIPS_CALL ("jal", operands, 1); }
6068 [(set_attr "type" "call")])
6070 ;; See comment for call_internal.
6071 (define_insn_and_split "call_value_multiple_internal"
6072 [(set (match_operand 0 "register_operand" "")
6073 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6074 (match_operand 2 "" "")))
6075 (set (match_operand 3 "register_operand" "")
6076 (call (mem:SI (match_dup 1))
6078 (clobber (reg:SI 31))]
6080 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
6081 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
6084 mips_split_call (operands[4],
6085 gen_call_value_multiple_split (operands[0], operands[1],
6086 operands[2], operands[3]));
6089 [(set_attr "jal" "indirect,direct")])
6091 (define_insn "call_value_multiple_split"
6092 [(set (match_operand 0 "register_operand" "")
6093 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
6094 (match_operand 2 "" "")))
6095 (set (match_operand 3 "register_operand" "")
6096 (call (mem:SI (match_dup 1))
6098 (clobber (reg:SI 31))
6099 (clobber (reg:SI 28))]
6100 "TARGET_SPLIT_CALLS"
6101 { return MIPS_CALL ("jal", operands, 1); }
6102 [(set_attr "type" "call")])
6104 ;; Call subroutine returning any type.
6106 (define_expand "untyped_call"
6107 [(parallel [(call (match_operand 0 "")
6109 (match_operand 1 "")
6110 (match_operand 2 "")])]
6115 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6117 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6119 rtx set = XVECEXP (operands[2], 0, i);
6120 mips_emit_move (SET_DEST (set), SET_SRC (set));
6123 emit_insn (gen_blockage ());
6128 ;; ....................
6132 ;; ....................
6136 (define_insn "prefetch"
6137 [(prefetch (match_operand:QI 0 "address_operand" "p")
6138 (match_operand 1 "const_int_operand" "n")
6139 (match_operand 2 "const_int_operand" "n"))]
6140 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6142 if (TARGET_LOONGSON_2EF)
6143 /* Loongson 2[ef] use load to $0 to perform prefetching. */
6144 return "ld\t$0,%a0";
6145 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6146 return "pref\t%1,%a0";
6148 [(set_attr "type" "prefetch")])
6150 (define_insn "*prefetch_indexed_<mode>"
6151 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6152 (match_operand:P 1 "register_operand" "d"))
6153 (match_operand 2 "const_int_operand" "n")
6154 (match_operand 3 "const_int_operand" "n"))]
6155 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6157 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6158 return "prefx\t%2,%1(%0)";
6160 [(set_attr "type" "prefetchx")])
6166 [(set_attr "type" "nop")
6167 (set_attr "mode" "none")])
6169 ;; Like nop, but commented out when outside a .set noreorder block.
6170 (define_insn "hazard_nop"
6179 [(set_attr "type" "nop")])
6181 ;; MIPS4 Conditional move instructions.
6183 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6184 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6186 (match_operator:MOVECC 4 "equality_operator"
6187 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6189 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6190 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6195 [(set_attr "type" "condmove")
6196 (set_attr "mode" "<GPR:MODE>")])
6198 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6199 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6200 (if_then_else:SCALARF
6201 (match_operator:MOVECC 4 "equality_operator"
6202 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6204 (match_operand:SCALARF 2 "register_operand" "f,0")
6205 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6206 "ISA_HAS_FP_CONDMOVE"
6208 mov%T4.<fmt>\t%0,%2,%1
6209 mov%t4.<fmt>\t%0,%3,%1"
6210 [(set_attr "type" "condmove")
6211 (set_attr "mode" "<SCALARF:MODE>")])
6213 ;; These are the main define_expand's used to make conditional moves.
6215 (define_expand "mov<mode>cc"
6216 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6217 (set (match_operand:GPR 0 "register_operand")
6218 (if_then_else:GPR (match_dup 5)
6219 (match_operand:GPR 2 "reg_or_0_operand")
6220 (match_operand:GPR 3 "reg_or_0_operand")))]
6223 mips_expand_conditional_move (operands);
6227 (define_expand "mov<mode>cc"
6228 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6229 (set (match_operand:SCALARF 0 "register_operand")
6230 (if_then_else:SCALARF (match_dup 5)
6231 (match_operand:SCALARF 2 "register_operand")
6232 (match_operand:SCALARF 3 "register_operand")))]
6233 "ISA_HAS_FP_CONDMOVE"
6235 mips_expand_conditional_move (operands);
6240 ;; ....................
6242 ;; mips16 inline constant tables
6244 ;; ....................
6247 (define_insn "consttable_int"
6248 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6249 (match_operand 1 "const_int_operand" "")]
6250 UNSPEC_CONSTTABLE_INT)]
6253 assemble_integer (operands[0], INTVAL (operands[1]),
6254 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6257 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6259 (define_insn "consttable_float"
6260 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6261 UNSPEC_CONSTTABLE_FLOAT)]
6266 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6267 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6268 assemble_real (d, GET_MODE (operands[0]),
6269 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6272 [(set (attr "length")
6273 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6275 (define_insn "align"
6276 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6279 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6282 [(match_operand 0 "small_data_pattern")]
6285 { operands[0] = mips_rewrite_small_data (operands[0]); })
6288 ;; ....................
6290 ;; MIPS16e Save/Restore
6292 ;; ....................
6295 (define_insn "*mips16e_save_restore"
6296 [(match_parallel 0 ""
6297 [(set (match_operand:SI 1 "register_operand")
6298 (plus:SI (match_dup 1)
6299 (match_operand:SI 2 "const_int_operand")))])]
6300 "operands[1] == stack_pointer_rtx
6301 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6302 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6303 [(set_attr "type" "arith")
6304 (set_attr "extended_mips16" "yes")])
6306 ;; Thread-Local Storage
6308 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6309 ;; MIPS architecture defines this register, and no current
6310 ;; implementation provides it; instead, any OS which supports TLS is
6311 ;; expected to trap and emulate this instruction. rdhwr is part of the
6312 ;; MIPS 32r2 specification, but we use it on any architecture because
6313 ;; we expect it to be emulated. Use .set to force the assembler to
6316 ;; We do not use a constraint to force the destination to be $3
6317 ;; because $3 can appear explicitly as a function return value.
6318 ;; If we leave the use of $3 implicit in the constraints until
6319 ;; reload, we may end up making a $3 return value live across
6320 ;; the instruction, leading to a spill failure when reloading it.
6321 (define_insn_and_split "tls_get_tp_<mode>"
6322 [(set (match_operand:P 0 "register_operand" "=d")
6323 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6324 (clobber (reg:P TLS_GET_TP_REGNUM))]
6325 "HAVE_AS_TLS && !TARGET_MIPS16"
6327 "&& reload_completed"
6328 [(set (reg:P TLS_GET_TP_REGNUM)
6329 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6330 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6332 [(set_attr "type" "unknown")
6333 ; Since rdhwr always generates a trap for now, putting it in a delay
6334 ; slot would make the kernel's emulation of it much slower.
6335 (set_attr "can_delay" "no")
6336 (set_attr "mode" "<MODE>")
6337 (set_attr "length" "8")])
6339 (define_insn "*tls_get_tp_<mode>_split"
6340 [(set (reg:P TLS_GET_TP_REGNUM)
6341 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6342 "HAVE_AS_TLS && !TARGET_MIPS16"
6343 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6344 [(set_attr "type" "unknown")
6345 ; See tls_get_tp_<mode>
6346 (set_attr "can_delay" "no")
6347 (set_attr "mode" "<MODE>")])
6349 ;; Synchronization instructions.
6353 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6355 (include "mips-ps-3d.md")
6357 ; The MIPS DSP Instructions.
6359 (include "mips-dsp.md")
6361 ; The MIPS DSP REV 2 Instructions.
6363 (include "mips-dspr2.md")
6365 ; MIPS fixed-point instructions.
6366 (include "mips-fixed.md")
6368 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6369 (include "loongson.md")