1 # Copyright
(C
) 1999-2023 Free Software Foundation
, Inc.
3 # This
program is free software
; you can redistribute it and
/or modify
4 # it under the terms of the GNU General Public License as published by
5 # the Free Software Foundation
; either version
3 of the License
, or
6 #
(at your option
) any later version.
8 # This
program is distributed in the hope that it will be useful
,
9 # but WITHOUT
ANY WARRANTY
; without even the implied warranty of
10 # MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. See the
11 # GNU General Public License
for more details.
13 # You should have received a copy of the GNU General Public License
14 # along with GCC
; see the file COPYING3.
If not see
15 #
<http
://www.gnu.org
/licenses
/>.
17 # Please email
any bugs
, comments
, and
/or additions to this file to
:
18 # gcc
-patches@gcc.gnu.org
20 # This file defines procs
for determining features supported by the target.
22 # Try to
compile the code given by CONTENTS into an output file of
23 # type TYPE
, where TYPE is as
for target_compile.
Return a list
24 # whose first element contains the compiler messages and whose
25 # second element is the
name of the output file.
27 # BASENAME is a prefix to use
for source and output files.
28 #
If ARGS is not empty
, its first element is a string that
29 # should be added to the command line.
31 # Assume by default that CONTENTS is C code.
32 # Otherwise
, code should contain
:
33 #
"/* Assembly" for assembly code,
36 #
"! Fortran" for Fortran code,
38 #
"// ObjC++" for ObjC++
41 # and
"(* Modula-2" for Modula-2
42 #
If the tool is ObjC
/ObjC
++ then we overide the extension to .m
/.mm to
43 # allow
for ObjC
/ObjC
++ specific flags.
45 proc check_compile
{basename type contents
args} {
47 verbose
"check_compile tool: $tool for $basename"
49 # Save additional_sources to avoid compiling testsuite
's sources
50 # against check_compile's source.
51 global additional_sources
52 if [info exists additional_sources
] {
53 set tmp_additional_sources
"$additional_sources"
54 set additional_sources
""
57 if { [llength $
args] > 0 } {
58 set options
[list
"additional_flags=[lindex $args 0]"]
62 # Silence
"command-line option [...] is valid for [...] but not for [...]"
63 # that we may easily run into here
, if more than one language is involved.
64 lappend options additional_flags
=-Wno
-complain
-wrong
-lang
66 switch -glob
-- $contents
{
67 "*/\\* Assembly*" { set src ${basename}[pid].S }
68 "*! Fortran*" { set src ${basename}[pid].f90 }
69 "*// C++*" { set src ${basename}[pid].cc }
70 "*// D*" { set src ${basename}[pid].d }
71 "*// ObjC++*" { set src ${basename}[pid].mm }
72 "*/\\* ObjC*" { set src ${basename}[pid].m }
73 "*// Go*" { set src ${basename}[pid].go }
74 "*// Rust*" { set src ${basename}[pid].rs }
75 "*(\\* Modula-2*" { set src ${basename}[pid].mod }
78 "objc" { set src ${basename}[pid].m }
79 "obj-c++" { set src ${basename}[pid].mm }
80 default
{ set src $
{basename
}[pid
].c
}
85 set compile_type $type
87 assembly
{ set output $
{basename
}[pid
].s
}
88 object
{ set output $
{basename
}[pid
].o
}
89 executable
{ set output $
{basename
}[pid
].exe
}
92 set output $
{basename
}[pid
].s
93 lappend options
"additional_flags=-fdump-$type"
94 set compile_type assembly
100 global compiler_flags
101 set save_compiler_flags $compiler_flags
102 set lines
[$
{tool
}_target_compile $src $output $compile_type
"$options"]
103 set compiler_flags $save_compiler_flags
106 set scan_output $output
107 # Don
't try folding this into the switch above; calling "glob" before the
108 # file is created won't work.
109 if [regexp
"rtl-(.*)" $type dummy rtl_type] {
110 set scan_output
"[glob $src.\[0-9\]\[0-9\]\[0-9\]r.$rtl_type]"
112 } elseif
[regexp
"tree-(.*)" $type dummy tree_type] {
113 set scan_output
"[glob $src.\[0-9\]\[0-9\]\[0-9\]t.$tree_type]"
117 # Restore additional_sources.
118 if [info exists additional_sources
] {
119 set additional_sources
"$tmp_additional_sources"
122 return [list $lines $scan_output
]
125 proc current_target_name
{ } {
127 if [info exists target_info
(target
,name)] {
128 set answer $target_info
(target
,name)
135 # Implement an effective
-target check
for property PROP by invoking
136 # the Tcl command
ARGS and seeing
if it returns true.
138 proc check_cached_effective_target
{ prop
args } {
141 set target
[current_target_name
]
142 if {![info exists et_cache
($prop
,$target
)]} {
143 verbose
"check_cached_effective_target $prop: checking $target" 2
144 if {[string is true
-strict $
args] ||
[string is false
-strict $
args]} {
145 error
{check_cached_effective_target condition already evaluated
; did you pass
[...
] instead of the expected
{...
}?
}
147 set code
[catch
{uplevel eval $
args} result
]
148 if {$code
!= 0 && $code
!= 2} {
149 return -code $code $result
151 set et_cache
($prop
,$target
) $result
154 set value $et_cache
($prop
,$target
)
155 verbose
"check_cached_effective_target $prop: returning $value for $target" 2
159 # Implements a version of check_cached_effective_target that also takes et_index
160 # into account when creating the
key for the
cache.
161 proc check_cached_effective_target_indexed
{ prop
args } {
163 set key "$et_index $prop"
164 verbose
"check_cached_effective_target_index $prop: returning $key" 2
166 return [check_cached_effective_target $
key [list uplevel eval $
args]]
169 # Clear effective
-target
cache. This is useful after testing
170 # effective
-target features and overriding TEST_ALWAYS_FLAGS and
/or
172 #
If one changes ALWAYS_CXXFLAGS or TEST_ALWAYS_FLAGS
then they should
173 #
do a clear_effective_target_cache at the end as the target
cache can
174 # make decisions based upon the flags
, and those decisions need to be
175 # redone when the flags change. An example of this is the
176 # asan_init
/asan_finish pair.
178 proc clear_effective_target_cache
{ } {
183 # Like check_compile
, but
delete the output file and
return true
if the
184 # compiler printed no messages.
185 proc check_no_compiler_messages_nocache
{args} {
186 set result
[eval check_compile $
args]
187 set lines
[lindex $result
0]
188 set output
[lindex $result
1]
189 remote_file build
delete $output
190 return [string match
"" $lines]
193 # Like check_no_compiler_messages_nocache
, but
cache the result.
194 # PROP is the
property we
're checking, and doubles as a prefix for
195 # temporary filenames.
196 proc check_no_compiler_messages {prop args} {
197 return [check_cached_effective_target $prop {
198 eval [list check_no_compiler_messages_nocache $prop] $args
202 # Like check_compile, but return true if the compiler printed no
203 # messages and if the contents of the output file satisfy PATTERN.
204 # If PATTERN has the form "!REGEXP", the contents satisfy it if they
205 # don't match regular expression REGEXP
, otherwise they satisfy it
206 #
if they
do match regular expression PATTERN.
(PATTERN can start
207 # with something like
"[!]" if the regular expression needs to match
208 #
"!" as the first character.)
210 #
Delete the output file before returning. The other arguments are
211 # as
for check_compile.
212 proc check_no_messages_and_pattern_nocache
{basename pattern
args} {
215 set result
[eval
[list check_compile $basename
] $
args]
216 set lines
[lindex $result
0]
217 set output
[lindex $result
1]
220 if { [string match
"" $lines] } {
221 set chan
[open
"$output"]
222 set invert
[regexp
{^
!(.
*)} $pattern dummy pattern
]
223 set ok
[expr
{ [regexp $pattern
[read $chan
]] != $invert
}]
227 remote_file build
delete $output
231 # Like check_no_messages_and_pattern_nocache
, but
cache the result.
232 # PROP is the
property we
're checking, and doubles as a prefix for
233 # temporary filenames.
234 proc check_no_messages_and_pattern {prop pattern args} {
235 return [check_cached_effective_target $prop {
236 eval [list check_no_messages_and_pattern_nocache $prop $pattern] $args
240 # Try to compile and run an executable from code CONTENTS. Return true
241 # if the compiler reports no messages and if execution "passes" in the
242 # usual DejaGNU sense. The arguments are as for check_compile, with
243 # TYPE implicitly being "executable".
244 proc check_runtime_nocache {basename contents args} {
247 set result [eval [list check_compile $basename executable $contents] $args]
248 set lines [lindex $result 0]
249 set output [lindex $result 1]
252 if { [string match "" $lines] } {
253 # No error messages, everything is OK.
254 set result [remote_load target "./$output" "" ""]
255 set status [lindex $result 0]
256 verbose "check_runtime_nocache $basename: status is <$status>" 2
257 if { $status == "pass" } {
261 remote_file build delete $output
265 # Like check_runtime_nocache, but cache the result. PROP is the
266 # property we're checking
, and doubles as a prefix
for temporary
268 proc check_runtime
{prop
args} {
271 return [check_cached_effective_target $prop
{
272 eval
[list check_runtime_nocache $prop
] $
args
276 #
Return 1 if GCC was configured with $pattern.
277 proc check_configured_with
{ pattern
} {
280 set options
[list
"additional_flags=-v"]
281 set gcc_output
[$
{tool
}_target_compile
"" "" "none" $options]
282 if { [ regexp
"Configured with: \[^\n\]*$pattern" $gcc_output ] } {
283 verbose
"Matched: $pattern" 2
287 verbose
"Failed to match: $pattern" 2
291 ###############################
292 # proc check_weak_available
{ }
293 ###############################
295 # weak symbols are only supported in some configs
/object formats
296 # this proc returns
1 if they
're supported, 0 if they're not
, or
-1 if unsure
298 proc check_weak_available
{ } {
301 # All mips targets should support it
303 if { [ string first
"mips" $target_cpu ] >= 0 } {
307 # All AIX targets should support it
309 if { [istarget
*-*-aix
*] } {
313 # All solaris2 targets should support it
315 if { [istarget
*-*-solaris2
*] } {
319 # Windows targets Cygwin and MingW32 support it
321 if { [istarget
*-*-cygwin
*] ||
[istarget
*-*-mingw
*] } {
325 # nvptx
(nearly
) supports it
327 if { [istarget nvptx
-*-*] } {
331 # pdp11 doesn
't support it
333 if { [istarget pdp11*-*-*] } {
337 # VxWorks hardly supports it (vx7 RTPs only)
339 if { [istarget *-*-vxworks*] } {
343 # ELF and ECOFF support it. a.out does with gas/gld but may also with
344 # other linkers, so we should try it
346 set objformat [gcc_target_object_format]
354 unknown { return -1 }
359 # return options to add to enable weak undefined symbols.
361 proc add_options_for_weak_undefined { flags } {
362 if { [istarget *-*-darwin*] } {
363 lappend flags "-Wl,-undefined,dynamic_lookup"
364 if { [istarget *-*-darwin\[89\]*] } {
365 lappend flags "-Wl,-flat_namespace"
371 # return 1 if weak undefined symbols are supported.
373 proc check_effective_target_weak_undefined { } {
374 if { [istarget hppa*-*-hpux*] } {
377 return [check_runtime weak_undefined {
378 extern void foo () __attribute__((weak));
379 int main (void) { if (foo) return 1; return 0; }
380 } [add_options_for_weak_undefined ""]]
383 ###############################
384 # proc check_weak_override_available { }
385 ###############################
387 # Like check_weak_available, but return 0 if weak symbol definitions
388 # cannot be overridden.
390 proc check_weak_override_available { } {
391 if { [istarget *-*-mingw*] } {
394 return [check_weak_available]
397 # Return 1 if VMA is equal to LMA for the .data section, 0
398 # otherwise. Cache the result.
400 proc check_effective_target_vma_equals_lma { } {
403 return [check_cached_effective_target vma_equals_lma {
404 set src vma_equals_lma[pid].c
405 set exe vma_equals_lma[pid].exe
406 verbose "check_effective_target_vma_equals_lma compiling testfile $src" 2
407 set f [open $src "w"]
408 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
409 puts $f "int foo = 42; void main() {}"
411 set lines [${tool}_target_compile $src $exe executable ""]
414 if [string match "" $lines] then {
417 set objdump_name [find_binutils_prog objdump]
418 set output [remote_exec host "$objdump_name" "--section-headers --section=.data $exe"]
419 set output [lindex $output 1]
421 remote_file build delete $exe
423 # Example output of objdump:
424 #vma_equals_lma9059.exe: file format elf32-littlearm
427 #Idx Name Size VMA LMA File off Algn
428 # 6 .data 00000558 20000000 08002658 00020000 2**3
429 # CONTENTS, ALLOC, LOAD, DATA
431 # Capture LMA and VMA columns for .data section
432 if ![ regexp {\d*\d+\s+\.data\s+\d+\s+(\d+)\s+(\d+)} $output dummy vma lma ] {
433 verbose "Could not parse objdump output" 2
436 return [string equal $vma $lma]
439 remote_file build delete $exe
440 verbose "Could not determine if VMA is equal to LMA. Assuming not equal." 2
446 # The "noinit" attribute is only supported by some targets.
447 # This proc returns 1 if it's supported
, 0 if it
's not.
449 proc check_effective_target_noinit { } {
450 if { [istarget arm*-*-eabi]
451 || [istarget msp430-*-*] } {
458 # The "persistent" attribute is only supported by some targets.
459 # This proc returns 1 if it's supported
, 0 if it
's not.
461 proc check_effective_target_persistent { } {
462 if { [istarget arm*-*-eabi]
463 || [istarget msp430-*-*] } {
470 ###############################
471 # proc check_visibility_available { what_kind }
472 ###############################
474 # The visibility attribute is only support in some object formats
475 # This proc returns 1 if it is supported, 0 if not.
476 # The argument is the kind of visibility, default/protected/hidden/internal.
478 proc check_visibility_available { what_kind } {
479 if [string match "" $what_kind] { set what_kind "hidden" }
481 return [check_no_compiler_messages visibility_available_$what_kind object "
482 void f() __attribute__((visibility(\"$what_kind\")));
487 ###############################
488 # proc check_alias_available { }
489 ###############################
491 # Determine if the target toolchain supports the alias attribute.
493 # Returns 2 if the target supports aliases. Returns 1 if the target
494 # only supports weak aliased. Returns 0 if the target does not
495 # support aliases at all. Returns -1 if support for aliases could not
498 proc check_alias_available { } {
501 return [check_cached_effective_target alias_available {
504 verbose "check_alias_available compiling testfile $src" 2
505 set f [open $src "w"]
506 # Compile a small test program. The definition of "g" is
507 # necessary to keep the Solaris assembler from complaining
509 puts $f "#ifdef __cplusplus\nextern \"C\"\n#endif\n"
510 puts $f "void g() {} void f() __attribute__((alias(\"g\")));"
512 set lines [${tool}_target_compile $src $obj object ""]
514 remote_file build delete $obj
516 if [string match "" $lines] then {
517 # No error messages, everything is OK.
520 if [regexp "alias definitions not supported" $lines] {
521 verbose "check_alias_available target does not support aliases" 2
523 set objformat [gcc_target_object_format]
525 if { $objformat == "elf" } {
526 verbose "check_alias_available but target uses ELF format, so it ought to" 2
532 if [regexp "only weak aliases are supported" $lines] {
533 verbose "check_alias_available target supports only weak aliases" 2
543 # Returns 1 if the target toolchain supports strong aliases, 0 otherwise.
545 proc check_effective_target_alias { } {
546 if { [check_alias_available] < 2 } {
553 # Returns 1 if the target uses the ELF object format, 0 otherwise.
555 proc check_effective_target_elf { } {
556 if { [gcc_target_object_format] == "elf" } {
563 # Returns 1 if the target toolchain supports ifunc, 0 otherwise.
565 proc check_ifunc_available { } {
566 return [check_no_compiler_messages ifunc_available object {
571 typedef void F (void);
572 F* g (void) { return &f_; }
573 void f () __attribute__ ((ifunc ("g")));
580 # Returns true if --gc-sections is supported on the target.
582 proc check_gc_sections_available { } {
585 return [check_cached_effective_target gc_sections_available {
586 # Some targets don't support gc
-sections despite whatever
's
587 # advertised by ld's options.
588 if { [istarget alpha
*-*-*]
589 ||
[istarget ia64
-*-*] } {
593 # elf2flt uses
-q
(--emit
-relocs
), which is incompatible with
595 if { [board_info target
exists ldflags
]
596 && [regexp
" -elf2flt\[ =\]" " [board_info target ldflags] "] } {
600 # VxWorks kernel modules are relocatable objects linked with
-r
,
601 #
while RTP executables are linked with
-q
(--emit
-relocs
).
602 # Both of these options are incompatible with
--gc
-sections.
603 if { [istarget
*-*-vxworks
*] } {
607 # Check
if the
ld used by gcc supports
--gc
-sections.
608 set options
[list
"additional_flags=-print-prog-name=ld"]
609 set gcc_ld
[lindex
[$
{tool
}_target_compile
"" "" "none" $options] 0]
610 set ld_output
[remote_exec host
"$gcc_ld" "--help"]
611 if { [ string first
"--gc-sections" $ld_output ] >= 0 } {
619 # Returns
1 if "dot" is supported on the host.
621 proc check_dot_available
{ } {
622 verbose
"check_dot_available" 2
624 set status [remote_exec host
"dot" "-V"]
625 verbose
" status: $status" 2
626 if { [lindex $
status 0] != 0 } {
632 #
Return 1 if according to target_info struct and explicit target list
633 # target is supposed to support trampolines.
635 proc check_effective_target_trampolines
{ } {
636 if [target_info
exists gcc
,no_trampolines
] {
639 if { [istarget avr
-*-*]
640 ||
[istarget msp430
-*-*]
641 ||
[istarget nvptx
-*-*]
642 ||
[istarget pru
-*-*]
643 ||
[istarget bpf
-*-*] } {
649 #
Return 1 if target has limited stack size.
651 proc check_effective_target_stack_size
{ } {
652 #
For nvptx target
, stack size limits are relevant
for execution only.
653 if { [istarget nvptx
-*-*] } {
654 # Find
'dg-do-what' in an outer frame.
657 upvar $level dg
-do-what dg
-do-what
658 if [info exists dg
-do-what
] then break
661 verbose
"check_effective_target_stack_size: found dg-do-what at level $level" 2
663 if { ![string equal
[lindex $
{dg
-do-what
} 0] run
] } {
668 if [target_info
exists gcc
,stack_size
] {
674 #
Return the value attribute of an effective target
, otherwise
return 0.
676 proc dg
-effective
-target
-value
{ effective_target
} {
677 if { "$effective_target" == "stack_size" } {
678 if [check_effective_target_stack_size
] {
679 return [target_info gcc
,stack_size
]
686 #
Return 1 if signal.h is supported.
688 proc check_effective_target_signal
{ } {
689 if [target_info
exists gcc
,signal_suppress
] {
695 #
Return 1 if according to target_info struct and explicit target list
696 # target disables
-fdelete
-null
-pointer
-checks. Targets should
return 0
697 #
if they simply default to
-fno
-delete-null
-pointer
-checks but obey
698 #
-fdelete
-null
-pointer
-checks when passed explicitly
(and tests that
699 # depend
on this option should
do that
).
701 proc check_effective_target_keeps_null_pointer_checks
{ } {
702 if [target_info
exists keeps_null_pointer_checks
] {
705 if { [istarget msp430
-*-*]
706 ||
[istarget avr
-*-*] } {
712 #
Return the autofdo profile wrapper
714 # Linux by default allows
516KB of perf event buffers
715 # in
/proc
/sys
/kernel
/perf_event_mlock_kb
716 # Each individual perf tries to grab it
717 # This causes problems with parallel test suite runs. Instead
718 #
limit us to
8 pages
(32K
), which should be good enough
719 #
for the small test programs. With the default settings
720 # this allows parallelism of
16 and higher of parallel gcc
-auto
-profile
721 proc profopt
-perf
-wrapper
{ } {
723 return "$srcdir/../config/i386/gcc-auto-profile --all -m8 "
726 #
Return true
if profiling is supported
on the target.
728 proc check_profiling_available
{ test_what
} {
729 verbose
"Profiling argument is <$test_what>" 1
731 # These conditions depend
on the
argument so examine them before
732 # looking at the
cache variable.
734 # Tree profiling requires TLS runtime support.
735 if { $test_what
== "-fprofile-generate" } {
736 if { ![check_effective_target_tls_runtime
] } {
741 if { $test_what
== "-fauto-profile" } {
742 if { !([istarget i?
86-*-linux
*] ||
[istarget x86_64
-*-linux
*]) } {
743 verbose
"autofdo only supported on linux"
746 # not cross compiling?
748 verbose
"autofdo not supported for non native builds"
751 set event
[profopt
-perf
-wrapper
]
753 verbose
"autofdo not supported"
757 set status [remote_exec host
"$srcdir/../config/i386/gcc-auto-profile" "-m8 true -v >/dev/null"]
758 if { [lindex $
status 0] != 0 } {
759 verbose
"autofdo not supported because perf does not work"
763 # no good way to check this in advance
-- check later instead.
764 #
set status [remote_exec host
"create_gcov" "2>/dev/null"]
765 #
if { [lindex $
status 0] != 255 } {
766 # verbose
"autofdo not supported due to missing create_gcov"
771 # Support
for -p
on solaris2 relies
on mcrt1.o which comes with the
772 # vendor compiler. We cannot reliably predict the directory where the
773 # vendor compiler
(and thus mcrt1.o
) is installed so we can
't
774 # necessarily find mcrt1.o even if we have it.
775 if { [istarget *-*-solaris2*] && $test_what == "-p" } {
779 # We don't yet support profiling
for MIPS16.
780 if { [istarget mips
*-*-*]
781 && ![check_effective_target_nomips16
]
782 && ($test_what
== "-p" || $test_what == "-pg") } {
786 # MinGW does not support
-p.
787 if { [istarget
*-*-mingw
*] && $test_what
== "-p" } {
791 # cygwin does not support
-p.
792 if { [istarget
*-*-cygwin
*] && $test_what
== "-p" } {
796 # uClibc does not have gcrt1.o.
797 if { [check_effective_target_uclibc
]
798 && ($test_what
== "-p" || $test_what == "-pg") } {
802 # Now examine the
cache variable.
803 set profiling_working \
804 [check_cached_effective_target profiling_available
{
805 # Some targets don
't have any implementation of __bb_init_func or are
806 # missing other needed machinery.
807 if {[istarget aarch64*-*-elf]
808 || [istarget am3*-*-linux*]
809 || [istarget amdgcn-*-*]
810 || [istarget arm*-*-eabi*]
811 || [istarget arm*-*-elf]
812 || [istarget arm*-*-symbianelf*]
813 || [istarget avr-*-*]
814 || [istarget bfin-*-*]
815 || [istarget cris-*-*]
816 || [istarget csky-*-elf*]
817 || [istarget fido-*-elf]
818 || [istarget h8300-*-*]
819 || [istarget lm32-*-*]
820 || [istarget m32c-*-elf]
821 || [istarget m68k-*-elf]
822 || [istarget m68k-*-uclinux*]
823 || [istarget mips*-*-elf*]
824 || [istarget mmix-*-*]
825 || [istarget mn10300-*-elf*]
826 || [istarget moxie-*-elf*]
827 || [istarget msp430-*-*]
828 || [istarget nds32*-*-elf]
829 || [istarget nios2-*-elf]
830 || [istarget nvptx-*-*]
831 || [istarget powerpc-*-eabi*]
832 || [istarget powerpc-*-elf]
833 || [istarget pru-*-*]
835 || [istarget tic6x-*-elf]
836 || [istarget visium-*-*]
837 || [istarget xstormy16-*]
838 || [istarget xtensa*-*-elf]
839 || [istarget *-*-rtems*]
840 || [istarget *-*-vxworks*] } {
847 # -pg link test result can't be cached since it may change between
849 if { $profiling_working
== 1
850 && ![check_no_compiler_messages_nocache profiling executable
{
851 int main
() { return 0; } } "-pg"] } {
852 set profiling_working
0
855 return $profiling_working
858 # Check to see
if a target is
"freestanding". This is as per the definition
859 # in Section
4 of C99 standard. Effectively
, it is a target which supports no
860 # extra headers or libraries other than what is considered essential.
861 proc check_effective_target_freestanding
{ } {
862 if { [istarget nvptx
-*-*] } {
868 # Check to see that file I
/O functions are available.
869 proc check_effective_target_fileio
{ } {
870 return [check_no_compiler_messages fileio_available executable
{
873 char
*n
= tmpnam
(NULL
);
874 FILE
*f
= fopen
(n
, "w");
881 #
Return 1 if target has packed layout of structure members by
882 # default
, 0 otherwise. Note that this is slightly different than
883 # whether the target has
"natural alignment": both attributes may be
886 proc check_effective_target_default_packed
{ } {
887 return [check_no_compiler_messages default_packed assembly
{
888 struct x
{ char a
; long b
; } c
;
889 int s
[sizeof
(c
) == sizeof
(char
) + sizeof
(long
) ?
1 : -1];
893 #
Return 1 if target has PCC_BITFIELD_TYPE_MATTERS defined. See
894 # documentation
, where the test also comes from.
896 proc check_effective_target_pcc_bitfield_type_matters
{ } {
897 # PCC_BITFIELD_TYPE_MATTERS isn
't just about unnamed or empty
898 # bitfields, but let's stick to the example code from the docs.
899 return [check_no_compiler_messages pcc_bitfield_type_matters assembly
{
900 struct foo1
{ char x
; char
:0; char y
; };
901 struct foo2
{ char x
; int :0; char y
; };
902 int s
[sizeof
(struct foo1
) != sizeof
(struct foo2
) ?
1 : -1];
906 # Add to FLAGS all the target
-specific flags needed to use thread
-local storage.
908 proc add_options_for_tls
{ flags
} {
909 #
On AIX
, __tls_get_addr
/___tls_get_addr only lives in
910 # libthread
, so always pass
-pthread
for native TLS.
911 # Need to duplicate native TLS check from
912 # check_effective_target_tls_native to avoid recursion.
913 if { ([istarget powerpc
-ibm
-aix
*]) &&
914 [check_no_messages_and_pattern tls_native
"!emutls" assembly {
916 int f
(void
) { return i
; }
917 void g
(int j
) { i
= j
; }
919 return "-pthread [g++_link_flags [get_multilibs "-pthread"] ] $flags "
924 #
Return 1 if indirect jumps are supported
, 0 otherwise.
926 proc check_effective_target_indirect_jumps
{} {
927 if { [istarget nvptx
-*-*] ||
[istarget bpf
-*-*] } {
933 #
Return 1 if nonlocal
goto is supported
, 0 otherwise.
935 proc check_effective_target_nonlocal_goto
{} {
936 if { [istarget nvptx
-*-*] ||
[istarget bpf
-*-*] } {
942 #
Return 1 if global constructors are supported
, 0 otherwise.
944 proc check_effective_target_global_constructor
{} {
945 if { [istarget nvptx
-*-*]
946 ||
[istarget bpf
-*-*] } {
952 #
Return 1 if taking label
values is supported
, 0 otherwise.
954 proc check_effective_target_label_values
{} {
955 if { [istarget nvptx
-*-*] ||
[target_info
exists gcc
,no_label_values
] } {
962 #
Return 1 if builtin_return_address and builtin_frame_address are
963 # supported
, 0 otherwise.
965 proc check_effective_target_return_address
{} {
966 if { [istarget nvptx
-*-*] } {
969 # No notion of
return address in eBPF.
970 if { [istarget bpf
-*-*] } {
973 # It could be supported
on amdgcn
, but isn
't yet.
974 if { [istarget amdgcn*-*-*] } {
980 # Return 1 if the assembler does not verify function types against
981 # calls, 0 otherwise. Such verification will typically show up problems
982 # with K&R C function declarations.
984 proc check_effective_target_untyped_assembly {} {
985 if { [istarget nvptx-*-*] } {
991 # Return 1 if alloca is supported, 0 otherwise.
993 proc check_effective_target_alloca {} {
994 if { [istarget bpf-*-*] } {
997 if { [istarget nvptx-*-*] } {
998 return [check_no_compiler_messages alloca assembly {
1000 void g (int n) { f (__builtin_alloca (n)); }
1006 # Return 1 if thread local storage (TLS) is supported, 0 otherwise.
1008 proc check_effective_target_tls {} {
1009 return [check_no_compiler_messages tls assembly {
1011 int f (void) { return i; }
1012 void g (int j) { i = j; }
1016 # Return 1 if *native* thread local storage (TLS) is supported, 0 otherwise.
1018 proc check_effective_target_tls_native {} {
1019 # VxWorks uses emulated TLS machinery, but with non-standard helper
1020 # functions, so we fail to automatically detect it.
1021 if { [istarget *-*-vxworks*] } {
1025 return [check_no_messages_and_pattern tls_native "!emutls" assembly {
1027 int f (void) { return i; }
1028 void g (int j) { i = j; }
1032 # Return 1 if *emulated* thread local storage (TLS) is supported, 0 otherwise.
1034 proc check_effective_target_tls_emulated {} {
1035 # VxWorks uses emulated TLS machinery, but with non-standard helper
1036 # functions, so we fail to automatically detect it.
1037 if { [istarget *-*-vxworks*] } {
1041 return [check_no_messages_and_pattern tls_emulated "emutls" assembly {
1043 int f (void) { return i; }
1044 void g (int j) { i = j; }
1048 # Return 1 if TLS executables can run correctly, 0 otherwise.
1050 proc check_effective_target_tls_runtime {} {
1051 return [check_runtime tls_runtime {
1052 __thread int thr __attribute__((tls_model("global-dynamic"))) = 0;
1053 int main (void) { return thr; }
1054 } [add_options_for_tls ""]]
1057 # Return 1 if atomic compare-and-swap is supported on 'int'
1059 proc check_effective_target_cas_char {} {
1060 return [check_no_compiler_messages cas_char assembly {
1061 #ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
1067 proc check_effective_target_cas_int {} {
1068 return [check_no_compiler_messages cas_int assembly {
1069 #if __INT_MAX__ == 0x7fff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
1071 #elif __INT_MAX__ == 0x7fffffff && __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
1079 # Return 1 if -ffunction-sections is supported, 0 otherwise.
1081 proc check_effective_target_function_sections {} {
1082 # Darwin has its own scheme and silently accepts -ffunction-sections.
1083 if { [istarget *-*-darwin*] } {
1087 return [check_no_compiler_messages functionsections assembly {
1089 } "-ffunction-sections"]
1092 # Return 1 if instruction scheduling is available, 0 otherwise.
1094 proc check_effective_target_scheduling {} {
1095 return [check_no_compiler_messages scheduling object {
1097 } "-fschedule-insns"]
1100 # Return 1 if trapping arithmetic is available, 0 otherwise.
1102 proc check_effective_target_trapping {} {
1103 return [check_no_compiler_messages trapping object {
1104 int add (int a, int b) { return a + b; }
1108 # Return 1 if compilation with -fgraphite is error-free for trivial
1109 # code, 0 otherwise.
1111 proc check_effective_target_fgraphite {} {
1112 return [check_no_compiler_messages fgraphite object {
1117 # Return 1 if compiled with --enable-offload-targets=
1118 # This affects host compilation as ENABLE_OFFLOAD then evaluates to true.
1119 proc check_effective_target_offloading_enabled {} {
1120 return [check_configured_with "--enable-offload-targets"]
1123 # Return 1 if compilation with -fopenacc is error-free for trivial
1124 # code, 0 otherwise.
1126 proc check_effective_target_fopenacc {} {
1127 # nvptx/amdgcn can be built with the device-side bits of openacc, but it
1128 # does not make sense to test it as an openacc host.
1129 if [istarget nvptx-*-*] { return 0 }
1130 if [istarget amdgcn-*-*] { return 0 }
1132 return [check_no_compiler_messages fopenacc object {
1137 # Return 1 if compilation with -fopenmp is error-free for trivial
1138 # code, 0 otherwise.
1140 proc check_effective_target_fopenmp {} {
1141 # nvptx/amdgcn can be built with the device-side bits of libgomp, but it
1142 # does not make sense to test it as an openmp host.
1143 if [istarget nvptx-*-*] { return 0 }
1144 if [istarget amdgcn-*-*] { return 0 }
1146 return [check_no_compiler_messages fopenmp object {
1151 # Return 1 if compilation with -fgnu-tm is error-free for trivial
1152 # code, 0 otherwise.
1154 proc check_effective_target_fgnu_tm {} {
1155 return [check_no_compiler_messages fgnu_tm object {
1160 # Return 1 if the target supports mmap, 0 otherwise.
1162 proc check_effective_target_mmap {} {
1163 return [check_function_available "mmap"]
1166 # Return 1 if the target supports sysconf, 0 otherwise.
1168 proc check_effective_target_sysconf {} {
1169 # VxWorks has sysconf in rtp mode only, but our way to test can't
1170 # tell kernel
mode doesn
't, as we're doing partial links
for
1171 # kernel modules. We can tell by checking
for a declaration
, or
1172 #
for some sysconf parm
, because configurations that don
't offer
1173 # sysconf don't have either.
1174 if { [istarget
*-*-vxworks
*] } {
1175 return [check_no_compiler_messages sysconfdecl assembly
{
1177 int f
() { return sysconf
(_SC_PAGESIZE
); }
1180 return [check_function_available
"sysconf"]
1183 #
Return 1 if the target supports dlopen
, 0 otherwise.
1184 proc check_effective_target_dlopen
{} {
1185 return [check_no_compiler_messages dlopen executable
{
1187 int main
(void
) { dlopen
("dummy.so", RTLD_NOW); }
1188 } [add_options_for_dlopen
""]]
1191 proc add_options_for_dlopen
{ flags
} {
1192 return "$flags -ldl"
1195 #
Return 1 if the target supports clone
, 0 otherwise.
1196 proc check_effective_target_clone
{} {
1197 return [check_function_available
"clone"]
1200 #
Return 1 if the target supports posix_memalign
, 0 otherwise.
1201 proc check_effective_target_posix_memalign
{} {
1202 if { [istarget
*-*-vxworks
*] } {
1203 # VxWorks doesn
't have posix_memalign but our way to test
1204 # can't tell as we
're doing partial links for kernel modules.
1207 return [check_function_available "posix_memalign"]
1210 # Return 1 if the target supports setrlimit, 0 otherwise.
1211 proc check_effective_target_setrlimit {} {
1212 # Darwin has non-posix compliant RLIMIT_AS
1213 if { [istarget *-*-darwin*] } {
1216 return [check_function_available "setrlimit"]
1219 # Return 1 if the target supports gettimeofday, 0 otherwise.
1220 proc check_effective_target_gettimeofday {} {
1221 return [check_function_available "gettimeofday"]
1224 # Return 1 if the target supports swapcontext, 0 otherwise.
1225 proc check_effective_target_swapcontext {} {
1226 return [check_no_compiler_messages swapcontext executable {
1227 #include <ucontext.h>
1230 ucontext_t orig_context,child_context;
1231 if (swapcontext(&child_context, &orig_context) < 0) { }
1236 # Return 1 if the target supports POSIX threads, 0 otherwise.
1237 proc check_effective_target_pthread {} {
1238 return [check_no_compiler_messages pthread object {
1239 #include <pthread.h>
1244 # Return 1 if the target supports both Unix and internet sockets, 0 otherwise.
1245 proc check_effective_target_sockets {} {
1246 return [check_no_compiler_messages socket executable {
1247 #include <sys/socket.h>
1249 #include <netinet/in.h>
1251 socket(AF_UNIX, SOCK_STREAM, 0);
1252 socket(AF_INET, SOCK_DGRAM, 0);
1258 # Return 1 if compilation with -mpe-aligned-commons is error-free
1259 # for trivial code, 0 otherwise.
1261 proc check_effective_target_pe_aligned_commons {} {
1262 if { [istarget *-*-cygwin*] || [istarget *-*-mingw*] } {
1263 return [check_no_compiler_messages pe_aligned_commons object {
1265 } "-mpe-aligned-commons"]
1270 # Return 1 if the target supports -static
1271 proc check_effective_target_static {} {
1272 if { [istarget arm*-*-uclinuxfdpiceabi] } {
1275 return [check_no_compiler_messages static executable {
1276 int main (void) { return 0; }
1280 # Return 1 if the target supports -fstack-protector
1281 proc check_effective_target_fstack_protector {} {
1282 if { [istarget hppa*-*-*] } {
1285 return [check_runtime fstack_protector {
1287 int main (int argc, char *argv[]) {
1289 return !strcpy (buf, strrchr (argv[0], '/'));
1291 } "-fstack-protector"]
1294 # Return 1 if the target supports -fstack-check or -fstack-check=$stack_kind
1295 proc check_stack_check_available { stack_kind } {
1296 if [string match "" $stack_kind] then {
1297 set stack_opt "-fstack-check"
1298 } else { set stack_opt "-fstack-check=$stack_kind" }
1300 return [check_no_compiler_messages stack_check_$stack_kind executable {
1301 int main (void) { return 0; }
1305 # Return 1 if the target supports stack scrubbing.
1306 proc check_effective_target_strub {} {
1307 return [check_no_compiler_messages strub assembly {
1308 void __attribute__ ((__strub__)) fn (void) {}
1312 # Return 1 if compilation with -freorder-blocks-and-partition is error-free
1313 # for trivial code, 0 otherwise. As some targets (ARM for example) only
1314 # warn when -fprofile-use is also supplied we test that combination too.
1316 proc check_effective_target_freorder {} {
1317 if { [check_no_compiler_messages freorder object {
1319 } "-freorder-blocks-and-partition"]
1320 && [check_no_compiler_messages fprofile_use_freorder object {
1322 } "-fprofile-use -freorder-blocks-and-partition -Wno-missing-profile"] } {
1328 # Return 1 if -fpic and -fPIC are supported, as in no warnings or errors
1329 # emitted, 0 otherwise. Whether a shared library can actually be built is
1330 # out of scope for this test.
1332 proc check_effective_target_fpic { } {
1333 # Note that M68K has a multilib that supports -fpic but not
1334 # -fPIC, so we need to check both. We test with a program that
1335 # requires GOT references.
1336 foreach arg {fpic fPIC} {
1337 if [check_no_compiler_messages $arg object {
1338 extern int foo (void); extern int bar;
1339 int baz (void) { return foo () + bar; }
1347 # On AArch64, if -fpic is not supported, then we will fall back to -fPIC
1348 # silently. So, we can't rely
on above
"check_effective_target_fpic" as it
1349 # assumes compiler will give warning
if -fpic not supported. Here we check
1350 # whether binutils supports those new
-fpic relocation modifiers
, and assume
1351 #
-fpic is supported
if there is binutils support. GCC configuration will
1352 # enable
-fpic
for AArch64 in this case.
1354 #
"check_effective_target_aarch64_small_fpic" is dedicated for checking small
1355 # memory
model -fpic relocation types.
1357 proc check_effective_target_aarch64_small_fpic
{ } {
1358 if { [istarget aarch64
*-*-*] } {
1359 return [check_no_compiler_messages aarch64_small_fpic object
{
1360 void foo
(void
) { asm
("ldr x0, [x2, #:gotpage_lo15:globalsym]"); }
1367 #
On AArch64
, instruction sequence
for TLS LE under
-mtls
-size
=32 will utilize
1368 # the relocation modifier
"tprel_g0_nc" together with MOVK, it's only supported
1369 # in binutils since
2015-03-04 as PR gas
/17843.
1371 # This test directive make sure binutils support all features needed by TLS LE
1372 # under
-mtls
-size
=32 on AArch64.
1374 proc check_effective_target_aarch64_tlsle32
{ } {
1375 if { [istarget aarch64
*-*-*] } {
1376 return [check_no_compiler_messages aarch64_tlsle32 object
{
1377 void foo
(void
) { asm
("movk x1,#:tprel_g0_nc:t1"); }
1384 #
Return 1 if -shared is supported
, as in no warnings or errors
1385 # emitted
, 0 otherwise.
1387 proc check_effective_target_shared
{ } {
1388 # Note that M68K has a multilib that supports
-fpic but not
1389 #
-fPIC
, so we need to check both. We test with a
program that
1390 # requires GOT references.
1391 return [check_no_compiler_messages shared executable
{
1392 extern
int foo
(void
); extern
int bar
;
1393 int baz
(void
) { return foo
() + bar
; }
1397 #
Return 1 if -pie
, -fpie and
-fPIE are supported
, 0 otherwise.
1399 proc check_effective_target_pie
{ } {
1400 if { [istarget
*-*-darwin\
[912\
]*]
1401 ||
[istarget
*-*-dragonfly
*]
1402 ||
[istarget
*-*-freebsd
*]
1403 ||
[istarget
*-*-linux
*]
1404 ||
[istarget arm
*-*-uclinuxfdpiceabi
]
1405 ||
[istarget
*-*-gnu
*]
1406 ||
[istarget
*-*-amdhsa
]} {
1409 if { [istarget
*-*-solaris2.1\
[1-9\
]*] } {
1410 # Full PIE support was added in Solaris
11.3, but gcc errors out
1411 #
if missing
, so check
for that.
1412 return [check_no_compiler_messages pie executable
{
1413 int main
(void
) { return 0; }
1419 #
Return true
if the target supports
-mpaired
-single
(as used
on MIPS
).
1421 proc check_effective_target_mpaired_single
{ args } {
1422 return [check_no_compiler_messages mpaired_single object
{
1427 #
Return true
if the target has access to FPU instructions.
1429 proc check_effective_target_hard_float
{ } {
1430 # This should work
on cores that only have single
-precision
,
1431 # and should also correctly handle legacy cores that had thumb1 and
1432 # lacked FP support
for that
, but had it in Arm state.
1433 if { [istarget arm
*-*-*] } {
1434 return [check_no_compiler_messages hard_float assembly
{
1436 #error __arm_soft_float
1441 if { [istarget loongarch
*-*-*] } {
1442 return [check_no_compiler_messages hard_float assembly
{
1443 #
if (defined __loongarch_soft_float
)
1444 #error __loongarch_soft_float
1449 if { [istarget mips
*-*-*] } {
1450 return [check_no_compiler_messages hard_float assembly
{
1451 #
if (defined __mips_soft_float || defined __mips16
)
1452 #error __mips_soft_float || __mips16
1457 # This proc is actually checking the availabilty of FPU
1458 # support
for doubles
, so
on the RX we must fail
if the
1459 #
64-bit double multilib has been selected.
1460 if { [istarget rx
-*-*] } {
1462 #
return [check_no_compiler_messages hard_float assembly
{
1463 #
if defined __RX_64_BIT_DOUBLES__
1464 #error __RX_64_BIT_DOUBLES__
1469 # The generic test doesn
't work for C-SKY because some cores have
1470 # hard float for single precision only.
1471 if { [istarget csky*-*-*] } {
1472 return [check_no_compiler_messages hard_float assembly {
1473 #if defined __csky_soft_float__
1474 #error __csky_soft_float__
1479 # The generic test equates hard_float with "no call for adding doubles".
1480 return [check_no_messages_and_pattern hard_float "!\\(call" rtl-expand {
1481 double a (double b, double c) { return b + c; }
1485 # Return true if the target is a 64-bit MIPS target.
1487 proc check_effective_target_mips64 { } {
1488 return [check_no_compiler_messages mips64 assembly {
1495 # Return true if the target is a MIPS target that does not produce
1498 proc check_effective_target_nomips16 { } {
1499 return [check_no_compiler_messages nomips16 object {
1503 /* A cheap way of testing for -mflip-mips16. */
1504 void foo (void) { asm ("addiu $20,$20,1"); }
1505 void bar (void) { asm ("addiu $20,$20,1"); }
1510 # Add the options needed for MIPS16 function attributes. At the moment,
1511 # we don't support MIPS16 PIC.
1513 proc add_options_for_mips16_attribute
{ flags
} {
1514 return "$flags -mno-abicalls -fno-pic -DMIPS16=__attribute__((mips16))"
1517 #
Return true
if we can force a
mode that allows MIPS16 code generation.
1518 # We don
't support MIPS16 PIC, and only support MIPS16 -mhard-float
1521 proc check_effective_target_mips16_attribute { } {
1522 return [check_no_compiler_messages mips16_attribute assembly {
1526 #if defined __mips_hard_float \
1527 && (!defined _ABIO32 || _MIPS_SIM != _ABIO32) \
1528 && (!defined _ABIO64 || _MIPS_SIM != _ABIO64)
1529 #error __mips_hard_float && (!_ABIO32 || !_ABIO64)
1531 } [add_options_for_mips16_attribute ""]]
1534 # Return 1 if the target supports long double larger than double when
1535 # using the new ABI, 0 otherwise.
1537 proc check_effective_target_mips_newabi_large_long_double { } {
1538 return [check_no_compiler_messages mips_newabi_large_long_double object {
1539 int dummy[sizeof(long double) > sizeof(double) ? 1 : -1];
1543 # Return true if the target is a MIPS target that has access
1544 # to the LL and SC instructions.
1546 proc check_effective_target_mips_llsc { } {
1547 if { ![istarget mips*-*-*] } {
1550 # Assume that these instructions are always implemented for
1551 # non-elf* targets, via emulation if necessary.
1552 if { ![istarget *-*-elf*] } {
1555 # Otherwise assume LL/SC support for everything but MIPS I.
1556 return [check_no_compiler_messages mips_llsc assembly {
1563 # Return true if the target is a MIPS target that uses in-place relocations.
1565 proc check_effective_target_mips_rel { } {
1566 if { ![istarget mips*-*-*] } {
1569 return [check_no_compiler_messages mips_rel object {
1570 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1571 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1572 #error _ABIN32 && (_ABIN32 || _ABI64)
1577 # Return true if the target is a MIPS target that uses the EABI.
1579 proc check_effective_target_mips_eabi { } {
1580 if { ![istarget mips*-*-*] } {
1583 return [check_no_compiler_messages mips_eabi object {
1590 # Return 1 if the current multilib does not generate PIC by default.
1592 proc check_effective_target_nonpic { } {
1593 return [check_no_compiler_messages nonpic assembly {
1600 # Return 1 if the current multilib generates PIE by default.
1602 proc check_effective_target_pie_enabled { } {
1603 return [check_no_compiler_messages pie_enabled assembly {
1610 # Return 1 if the target generates -fstack-protector by default.
1612 proc check_effective_target_fstack_protector_enabled {} {
1613 return [ check_no_compiler_messages fstack_protector_enabled assembly {
1614 #if !defined(__SSP__) && !defined(__SSP_ALL__) && \
1615 !defined(__SSP_STRONG__) && !defined(__SSP_EXPICIT__)
1621 # Return 1 if the target does not use a status wrapper.
1623 proc check_effective_target_unwrapped { } {
1624 if { [target_info needs_status_wrapper] != "" \
1625 && [target_info needs_status_wrapper] != "0" } {
1631 # Return true if iconv is supported on the target. In particular IBM1047.
1633 proc check_iconv_available { test_what } {
1636 # If the tool configuration file has not set libiconv, try "-liconv"
1637 if { ![info exists libiconv] } {
1638 set libiconv "-liconv"
1640 set test_what [lindex $test_what 1]
1641 return [check_runtime_nocache $test_what [subst {
1647 cd = iconv_open ("$test_what", "UTF-8");
1648 if (cd == (iconv_t) -1)
1655 # Return true if the atomic library is supported on the target.
1656 proc check_effective_target_libatomic_available { } {
1657 return [check_no_compiler_messages libatomic_available executable {
1658 int main (void) { return 0; }
1662 # Return 1 if an ASCII locale is supported on this host, 0 otherwise.
1664 proc check_ascii_locale_available { } {
1668 # Return true if named sections are supported on this target.
1670 proc check_named_sections_available { } {
1671 return [check_no_compiler_messages named_sections assembly {
1672 int __attribute__ ((section("whatever"))) foo;
1676 # Return true if the "naked" function attribute is supported on this target.
1678 proc check_effective_target_naked_functions { } {
1679 return [check_no_compiler_messages naked_functions assembly {
1680 void f() __attribute__((naked));
1684 # Return 1 if the target supports Fortran real kinds larger than real(8),
1687 # When the target name changes, replace the cached result.
1689 proc check_effective_target_fortran_large_real { } {
1690 return [check_no_compiler_messages fortran_large_real executable {
1692 integer,parameter :: k = selected_real_kind (precision (0.0_8) + 1)
1699 # Return 1 if the target supports Fortran real kind real(16),
1700 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1701 # this checks for Real(16) only; the other returned real(10) if
1702 # both real(10) and real(16) are available.
1704 # When the target name changes, replace the cached result.
1706 proc check_effective_target_fortran_real_16 { } {
1707 return [check_no_compiler_messages fortran_real_16 executable {
1715 # Return 1 if the target supports Fortran real kind 10,
1716 # 0 otherwise. Contrary to check_effective_target_fortran_large_real
1717 # this checks for real(10) only.
1719 # When the target name changes, replace the cached result.
1721 proc check_effective_target_fortran_real_10 { } {
1722 return [check_no_compiler_messages fortran_real_10 executable {
1730 # Return 1 if the target supports Fortran real kind C_FLOAT128,
1731 # 0 otherwise. This differs from check_effective_target_fortran_real_16
1732 # because _Float128 has the additional requirement that it be the
1733 # 128-bit IEEE encoding; even if _Float128 is available in C, it may not
1734 # have a corresponding Fortran kind on targets (PowerPC) that use some
1735 # other encoding for long double/TFmode/real(16).
1736 proc check_effective_target_fortran_real_c_float128 { } {
1737 return [check_no_compiler_messages fortran_real_c_float128 executable {
1740 real(kind=c_float128) :: x
1746 # Return 1 if the target supports Fortran's IEEE modules
,
1749 # When the target
name changes
, replace the cached result.
1751 proc check_effective_target_fortran_ieee
{ flags
} {
1752 return [check_no_compiler_messages fortran_ieee executable
{
1754 use
, intrinsic
:: ieee_features
1760 #
Return 1 if the target supports
SQRT for the
largest floating
-point
1761 # type.
(Some targets lack the libm support
for this FP type.
)
1762 #
On most targets
, this check effectively checks either whether sqrtl is
1763 # available or
on __float128 systems whether libquadmath is installed
,
1764 # which provides sqrtq.
1766 # When the target
name changes
, replace the cached result.
1768 proc check_effective_target_fortran_largest_fp_has_sqrt
{ } {
1769 return [check_no_compiler_messages fortran_largest_fp_has_sqrt executable
{
1771 use iso_fortran_env
, only
: real_kinds
1772 integer,parameter
:: maxFP
= real_kinds
(ubound
(real_kinds
,dim
=1))
1773 real
(kind
=maxFP
), volatile
:: x
1781 #
Return 1 if the target supports Fortran
integer kinds larger than
1782 #
integer(8), 0 otherwise.
1784 # When the target
name changes
, replace the cached result.
1786 proc check_effective_target_fortran_large_int
{ } {
1787 return [check_no_compiler_messages fortran_large_int executable
{
1789 integer,parameter
:: k
= selected_int_kind
(range
(0_8
) + 1)
1790 integer(kind
=k
) :: i
1795 #
Return 1 if the target supports Fortran
integer(16), 0 otherwise.
1797 # When the target
name changes
, replace the cached result.
1799 proc check_effective_target_fortran_integer_16
{ } {
1800 return [check_no_compiler_messages fortran_integer_16 executable
{
1807 #
Return 1 if we can statically link libgfortran
, 0 otherwise.
1809 # When the target
name changes
, replace the cached result.
1811 proc check_effective_target_static_libgfortran
{ } {
1812 return [check_no_compiler_messages static_libgfortran executable
{
1819 #
Return 1 if we can use the
-rdynamic option
, 0 otherwise.
1821 proc check_effective_target_rdynamic
{ } {
1822 return [check_no_compiler_messages rdynamic executable
{
1823 int main
() { return 0; }
1827 proc check_linker_plugin_available
{ } {
1828 return [check_no_compiler_messages_nocache linker_plugin executable
{
1829 int main
() { return 0; }
1830 } "-flto -fuse-linker-plugin"]
1833 #
Return 1 if the target is RV32
, 0 otherwise.
Cache the result.
1835 proc check_effective_target_rv32
{ } {
1836 # Check that we are compiling
for RV32 by checking the xlen size.
1837 return [check_no_compiler_messages riscv_rv32 assembly
{
1838 #
if !defined
(__riscv_xlen
)
1839 #error
"__riscv_xlen not defined!"
1841 #
if __riscv_xlen
!= 32
1848 #
Return 1 if the target is RV64
, 0 otherwise.
Cache the result.
1850 proc check_effective_target_rv64
{ } {
1851 # Check that we are compiling
for RV64 by checking the xlen size.
1852 return [check_no_compiler_messages riscv_rv64 assembly
{
1853 #
if !defined
(__riscv_xlen
)
1854 #error
"__riscv_xlen not defined!"
1856 #
if __riscv_xlen
!= 64
1863 #
Return 1 if the target abi is __riscv_float_abi_soft
, 0 otherwise.
1866 proc check_effective_target_rv_float_abi_soft
{ } {
1867 # Check that we are compiling
for RV64 by checking the xlen size.
1868 return [check_no_compiler_messages riscv_riscv_float_abi_soft assembly
{
1869 #ifndef __riscv_float_abi_soft
1870 #error
"Not __riscv_float_abi_soft"
1875 #
Return 1 if the target arch supports the atomic extension
, 0 otherwise.
1878 proc check_effective_target_riscv_a
{ } {
1879 return [check_no_compiler_messages riscv_ext_a assembly
{
1881 #error
"Not __riscv_a"
1886 #
Return 1 if the target arch supports the double precision floating point
1887 # extension
, 0 otherwise.
Cache the result.
1889 proc check_effective_target_riscv_d
{ } {
1890 return [check_no_compiler_messages riscv_ext_d assembly
{
1892 #error
"Not __riscv_d"
1897 #
Return 1 if the target arch supports the vector extension
, 0 otherwise.
1900 proc check_effective_target_riscv_v
{ } {
1901 return [check_no_compiler_messages riscv_ext_v assembly
{
1903 #error
"Not __riscv_v"
1908 #
Return 1 if the target arch supports the Zvfh extension
, 0 otherwise.
1911 proc check_effective_target_riscv_zvfh
{ } {
1912 return [check_no_compiler_messages riscv_ext_zvfh assembly
{
1913 #ifndef __riscv_zvfh
1914 #error
"Not __riscv_zvfh"
1919 #
Return 1 if the target arch supports half float
, 0 otherwise.
1920 # Note
, this differs from the test performed by
1921 #
/* dg
-skip
-if "" { *-*-* } { "*" } { "-march=rv*zfh*" } */
1922 # in that it takes default behaviour into account.
1925 proc check_effective_target_riscv_zfh
{ } {
1926 return [check_no_compiler_messages riscv_ext_zfh assembly
{
1928 #error
"Not __riscv_zfh"
1933 #
Return 1 if the target arch supports the TSO memory ordering extension
,
1934 #
0 otherwise.
Cache the result.
1936 proc check_effective_target_riscv_ztso
{ } {
1937 return [check_no_compiler_messages riscv_ext_ztso assembly
{
1938 #ifndef __riscv_ztso
1939 #error
"Not __riscv_ztso"
1944 #
Return 1 if the target arch supports the Zbb extension
, 0 otherwise.
1947 proc check_effective_target_riscv_zbb
{ } {
1948 return [check_no_compiler_messages riscv_ext_zbb assembly
{
1950 #error
"Not __riscv_zbb"
1955 #
Return 1 if we can
execute code when using dg
-add
-options riscv_v
1957 proc check_effective_target_riscv_v_ok
{ } {
1958 #
If the target already supports v without
any added options
,
1959 # we may assume we can
execute just fine.
1960 if { [check_effective_target_riscv_v
] } {
1964 # check
if we can
execute vector insns with the given hardware or
1966 set gcc_march
[regsub
{[[:alnum
:]]*} [riscv_get_arch
] &v
]
1967 if { [check_runtime $
{gcc_march
}_exec
{
1968 int main
() { asm
("vsetivli t0, 9, e8, m1, tu, ma"); return 0; } } "-march=${gcc_march}"] } {
1972 # Possible future extensions
: If the target is a simulator
, dg
-add
-options
1973 # might change its config to make it allow vector insns
, or we might use
1974 # options to
set special elf flags
/ sections to effect that.
1979 #
Return 1 if we can
execute code when using dg
-add
-options riscv_zfh
1981 proc check_effective_target_riscv_zfh_ok
{ } {
1982 #
If the target already supports zfh without
any added options
,
1983 # we may assume we can
execute just fine.
1984 # ??? Other cases we should
consider:
1985 #
- target
/ simulator already supports zfh extension
- test
for that.
1986 #
- target is a simulator
, and dg
-add
-options knows how to enable zfh support in that simulator
1987 if { [check_effective_target_riscv_zfh
] } {
1991 # check
if we can
execute zfh insns with the given hardware or
1993 set gcc_march
[riscv_get_arch
]
1994 if { [check_runtime $
{gcc_march
}_zfh_exec
{
1995 int main
() { asm
("feq.h a3,fa5,fa4"); return 0; } } "-march=${gcc_march}_zfh"] } {
1999 # Possible future extensions
: If the target is a simulator
, dg
-add
-options
2000 # might change its config to make it allow half float insns
, or we might
2001 # use options to
set special elf flags
/ sections to effect that.
2006 #
Return 1 if we can
execute code when using dg
-add
-options riscv_zvfh
2008 proc check_effective_target_riscv_zvfh_ok
{ } {
2009 #
If the target already supports v without
any added options
,
2010 # we may assume we can
execute just fine.
2011 if { [check_effective_target_riscv_zvfh
] } {
2015 # check
if we can
execute vector insns with the given hardware or
2017 set gcc_march
[regsub
{[[:alnum
:]]*} [riscv_get_arch
] &v
]
2018 if { [check_runtime $
{gcc_march
}_exec
{
2021 asm
("vsetivli zero,8,e16,m1,ta,ma");
2022 asm
("vfadd.vv v8,v8,v16" : : : "v8");
2024 } } "-march=${gcc_march}"] } {
2031 proc riscv_get_arch
{ } {
2033 # ???
do we neeed to add more extensions to the list below?
2034 foreach ext
{ i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvfh ztso
} {
2035 if { [check_no_compiler_messages riscv_ext_$ext assembly
[string map
[list DEF __riscv_$ext
] {
2040 if { [string length $ext
] > 1 } {
2043 set gcc_march $gcc_march$ext
2045 if { [string equal $gcc_march
"imafd"] } {
2049 if { [check_effective_target_rv32
] } {
2050 set gcc_march rv32$gcc_march
2051 } elseif
{ [check_effective_target_rv64
] } {
2052 set gcc_march rv64$gcc_march
2059 proc add_options_for_riscv_a
{ flags
} {
2060 if { [lsearch $flags
-march
=*] >= 0 } {
2061 #
If there are multiple
-march flags
, we have to adjust all of them.
2062 set expanded_flags
[regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*)g
+} $flags
\\1imafd
]
2063 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*[b
-eg
-rt
-wy
]*)a
*} $expanded_flags
\\1a
]
2065 if { [check_effective_target_riscv_a
] } {
2068 return "$flags -march=[regsub {(rv[[:digit:]]*[b-eg-rt-wy]*)a*} [riscv_get_arch] &a]"
2071 proc add_options_for_riscv_d
{ flags
} {
2072 if { [lsearch $flags
-march
=*] >= 0 } {
2073 #
If there are multiple
-march flags
, we have to adjust all of them.
2074 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*[a
-ce
-rt
-wy
]*)d
*} $flags
\\1d
]
2076 if { [check_effective_target_riscv_d
] } {
2079 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &d]"
2082 proc add_options_for_riscv_v
{ flags
} {
2083 if { [lsearch $flags
-march
=*] >= 0 } {
2084 #
If there are multiple
-march flags
, we have to adjust all of them.
2085 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=rv
[[:digit
:]]*[a
-rt
-uwy
]*)v
*} $flags
\\1v
]
2087 if { [check_effective_target_riscv_v
] } {
2090 return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]"
2093 proc add_options_for_riscv_zfh
{ flags
} {
2094 if { [lsearch $flags
-march
=*] >= 0 } {
2095 #
If there are multiple
-march flags
, we have to adjust all of them.
2096 set flags
[regsub
-all
-- {(?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*} $flags
&_zfh
]
2097 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*_zfh
[[:alnum
:]_.
]*)_zfh
} $flags
\\1 ]
2099 if { [check_effective_target_riscv_zfh
] } {
2102 return "$flags -march=[riscv_get_arch]_zfh"
2105 proc add_options_for_riscv_ztso
{ flags
} {
2106 if { [lsearch $flags
-march
=*] >= 0 } {
2107 #
If there are multiple
-march flags
, we have to adjust all of them.
2108 set flags
[regsub
-all
-- {(?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*} $flags
&_ztso
]
2109 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*_ztso
[[:alnum
:]_.
]*)_ztso
} $flags
\\1 ]
2111 if { [check_effective_target_riscv_ztso
] } {
2114 return "$flags -march=[riscv_get_arch]_ztso"
2117 proc add_options_for_riscv_zvfh
{ flags
} {
2118 if { [lsearch $flags
-march
=*] >= 0 } {
2119 #
If there are multiple
-march flags
, we have to adjust all of them.
2120 set flags
[regsub
-all
-- {(?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*} $flags
&_zvfh
]
2121 return [regsub
-all
-- {((?
:^|
[[:space
:]])-march
=[[:alnum
:]_.
]*_zvfh
[[:alnum
:]_.
]*)_zvfh
} $flags
\\1 ]
2123 if { [check_effective_target_riscv_zvfh
] } {
2126 return "$flags -march=[riscv_get_arch]_zvfh"
2129 #
Return 1 if the target OS supports running SSE executables
, 0
2130 # otherwise.
Cache the result.
2132 proc check_sse_os_support_available
{ } {
2133 return [check_cached_effective_target sse_os_support_available
{
2134 #
If this is not the right target
then we can skip the test.
2135 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2143 #
Return 1 if the target OS supports running AVX executables
, 0
2144 # otherwise.
Cache the result.
2146 proc check_avx_os_support_available
{ } {
2147 return [check_cached_effective_target avx_os_support_available
{
2148 #
If this is not the right target
then we can skip the test.
2149 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2152 # Check that OS has AVX and SSE saving enabled.
2153 check_runtime_nocache avx_os_support_available
{
2156 unsigned
int eax
, edx
;
2158 asm
("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2159 return (eax
& 0x06) != 0x06;
2166 #
Return 1 if the target OS supports running AVX executables
, 0
2167 # otherwise.
Cache the result.
2169 proc check_avx512_os_support_available
{ } {
2170 return [check_cached_effective_target avx512_os_support_available
{
2171 #
If this is not the right target
then we can skip the test.
2172 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2175 # Check that OS has AVX512
, AVX and SSE saving enabled.
2176 check_runtime_nocache avx512_os_support_available
{
2179 unsigned
int eax
, edx
;
2181 asm
("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
2182 return (eax
& 0xe6) != 0xe6;
2189 #
Return 1 if the target supports executing SSE instructions
, 0
2190 # otherwise.
Cache the result.
2192 proc check_sse_hw_available
{ } {
2193 return [check_cached_effective_target sse_hw_available
{
2194 #
If this is not the right target
then we can skip the test.
2195 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2198 check_runtime_nocache sse_hw_available
{
2202 unsigned
int eax
, ebx
, ecx
, edx
;
2203 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2206 return !(edx
& bit_SSE
);
2213 #
Return 1 if the target supports executing SSE2 instructions
, 0
2214 # otherwise.
Cache the result.
2216 proc check_sse2_hw_available
{ } {
2217 return [check_cached_effective_target sse2_hw_available
{
2218 #
If this is not the right target
then we can skip the test.
2219 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2222 check_runtime_nocache sse2_hw_available
{
2226 unsigned
int eax
, ebx
, ecx
, edx
;
2227 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2230 return !(edx
& bit_SSE2
);
2237 #
Return 1 if the target supports executing SSE4 instructions
, 0
2238 # otherwise.
Cache the result.
2240 proc check_sse4_hw_available
{ } {
2241 return [check_cached_effective_target sse4_hw_available
{
2242 #
If this is not the right target
then we can skip the test.
2243 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2246 check_runtime_nocache sse4_hw_available
{
2250 unsigned
int eax
, ebx
, ecx
, edx
;
2251 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2254 return !(ecx
& bit_SSE4_2
);
2261 #
Return 1 if the target supports executing AVX instructions
, 0
2262 # otherwise.
Cache the result.
2264 proc check_avx_hw_available
{ } {
2265 return [check_cached_effective_target avx_hw_available
{
2266 #
If this is not the right target
then we can skip the test.
2267 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2270 check_runtime_nocache avx_hw_available
{
2274 unsigned
int eax
, ebx
, ecx
, edx
;
2275 if (!__get_cpuid
(1, &eax
, &ebx
, &ecx
, &edx
))
2278 return ((ecx
& (bit_AVX | bit_OSXSAVE
))
2279 != (bit_AVX | bit_OSXSAVE
));
2286 #
Return 1 if the target supports executing AVX2 instructions
, 0
2287 # otherwise.
Cache the result.
2289 proc check_avx2_hw_available
{ } {
2290 return [check_cached_effective_target avx2_hw_available
{
2291 #
If this is not the right target
then we can skip the test.
2292 if { !([istarget x86_64
-*-*] ||
[istarget i?
86-*-*]) } {
2295 check_runtime_nocache avx2_hw_available
{
2300 unsigned
int eax
, ebx
, ecx
, edx
;
2302 if (__get_cpuid_max
(0, NULL
) < 7)
2305 __cpuid
(1, eax
, ebx
, ecx
, edx
);
2307 if (!(ecx
& bit_OSXSAVE
))
2310 __cpuid_count
(7, 0, eax
, ebx
, ecx
, edx
);
2312 return !(ebx
& bit_AVX2
);
2319 #
Return 1 if the target supports executing AVX512 foundation instructions
, 0
2320 # otherwise.
Cache the result.
2322 proc check_avx512f_hw_available
{ } {
2323 return [check_cached_effective_target avx512f_hw_available
{
2324 #
If this is not the right target
then we can skip the test.
2325 if { !([istarget x86_64
-*-*] ||
[istarget i?
86-*-*]) } {
2328 check_runtime_nocache avx512f_hw_available
{
2333 unsigned
int eax
, ebx
, ecx
, edx
;
2335 if (__get_cpuid_max
(0, NULL
) < 7)
2338 __cpuid
(1, eax
, ebx
, ecx
, edx
);
2340 if (!(ecx
& bit_OSXSAVE
))
2343 __cpuid_count
(7, 0, eax
, ebx
, ecx
, edx
);
2345 return !(ebx
& bit_AVX512F
);
2352 #
Return 1 if the target supports running SSE executables
, 0 otherwise.
2354 proc check_effective_target_sse_runtime
{ } {
2355 if { [check_effective_target_sse
]
2356 && [check_sse_hw_available
]
2357 && [check_sse_os_support_available
] } {
2363 #
Return 1 if the target supports running SSE2 executables
, 0 otherwise.
2365 proc check_effective_target_sse2_runtime
{ } {
2366 if { [check_effective_target_sse2
]
2367 && [check_sse2_hw_available
]
2368 && [check_sse_os_support_available
] } {
2374 #
Return 1 if the target supports running SSE4 executables
, 0 otherwise.
2376 proc check_effective_target_sse4_runtime
{ } {
2377 if { [check_effective_target_sse4
]
2378 && [check_sse4_hw_available
]
2379 && [check_sse_os_support_available
] } {
2385 #
Return 1 if the target supports running AVX executables
, 0 otherwise.
2387 proc check_effective_target_avx_runtime
{ } {
2388 if { [check_effective_target_avx
]
2389 && [check_avx_hw_available
]
2390 && [check_avx_os_support_available
] } {
2396 #
Return 1 if the target supports running AVX2 executables
, 0 otherwise.
2398 proc check_effective_target_avx2_runtime
{ } {
2399 if { [check_effective_target_avx2
]
2400 && [check_avx2_hw_available
]
2401 && [check_avx_os_support_available
] } {
2407 #
Return 1 if the target supports running AVX512f executables
, 0 otherwise.
2409 proc check_effective_target_avx512f_runtime
{ } {
2410 if { [check_effective_target_avx512f
]
2411 && [check_avx512f_hw_available
]
2412 && [check_avx512_os_support_available
] } {
2418 #
Return 1 if bmi2 instructions can be compiled.
2419 proc check_effective_target_bmi2
{ } {
2420 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
2423 return [check_no_compiler_messages bmi2 object
{
2425 _bzhi_u32
(unsigned
int __X
, unsigned
int __Y
)
2427 return __builtin_ia32_bzhi_si
(__X
, __Y
);
2432 #
Return 1 if the target supports executing MIPS Paired
-Single instructions
,
2433 #
0 otherwise.
Cache the result.
2435 proc check_mpaired_single_hw_available
{ } {
2436 return [check_cached_effective_target mpaired_single_hw_available
{
2437 #
If this is not the right target
then we can skip the test.
2438 if { !([istarget mips
*-*-*]) } {
2441 check_runtime_nocache mpaired_single_hw_available
{
2444 asm volatile
("pll.ps $f2,$f4,$f6");
2452 #
Return 1 if the target supports executing Loongson vector instructions
,
2453 #
0 otherwise.
Cache the result.
2455 proc check_mips_loongson_mmi_hw_available
{ } {
2456 return [check_cached_effective_target mips_loongson_mmi_hw_available
{
2457 #
If this is not the right target
then we can skip the test.
2458 if { !([istarget mips
*-*-*]) } {
2461 check_runtime_nocache mips_loongson_mmi_hw_available
{
2462 #
include <loongson
-mmiintrin.h
>
2465 asm volatile
("paddw $f2,$f4,$f6");
2473 #
Return 1 if the target supports executing MIPS MSA instructions
, 0
2474 # otherwise.
Cache the result.
2476 proc check_mips_msa_hw_available
{ } {
2477 return [check_cached_effective_target mips_msa_hw_available
{
2478 #
If this is not the right target
then we can skip the test.
2479 if { !([istarget mips
*-*-*]) } {
2482 check_runtime_nocache mips_msa_hw_available
{
2483 #
if !defined
(__mips_msa
)
2484 #error
"MSA NOT AVAIL"
2486 #
if !(((__mips
== 64) ||
(__mips
== 32)) && (__mips_isa_rev
>= 2))
2487 #error
"MSA NOT AVAIL FOR ISA REV < 2"
2489 #
if !defined
(__mips_hard_float
)
2490 #error
"MSA HARD_FLOAT REQUIRED"
2492 #
if __mips_fpr
!= 64
2493 #error
"MSA 64-bit FPR REQUIRED"
2499 v8i16 v
= __builtin_msa_ldi_h
(0);
2509 #
Return 1 if the target supports running MIPS Paired
-Single
2510 # executables
, 0 otherwise.
2512 proc check_effective_target_mpaired_single_runtime
{ } {
2513 if { [check_effective_target_mpaired_single
"-mpaired-single"]
2514 && [check_mpaired_single_hw_available
] } {
2520 #
Return 1 if the target supports running Loongson executables
, 0 otherwise.
2522 proc check_effective_target_mips_loongson_mmi_runtime
{ } {
2523 if { [check_effective_target_mips_loongson_mmi
"-mloongson-mmi"]
2524 && [check_mips_loongson_mmi_hw_available
] } {
2530 #
Return 1 if the target supports running MIPS MSA executables
, 0 otherwise.
2532 proc check_effective_target_mips_msa_runtime
{ } {
2533 if { [check_effective_target_mips_msa
"-mmsa"]
2534 && [check_mips_msa_hw_available
] } {
2540 #
Return 1 if we are compiling
for 64-bit PowerPC but we
do not use direct
2541 #
move instructions
for moves from GPR to FPR.
2543 proc check_effective_target_powerpc64_no_dm
{ } {
2544 # The
"mulld" checks if we are generating PowerPC64 code. The "lfd"
2545 # checks
if we
do not use direct moves
, but use the old
-fashioned
2546 # slower
move-via
-the
-stack.
2547 return [check_no_messages_and_pattern powerpc64_no_dm \
2548 {\mmulld\M.
*\mlfd
} assembly
{
2549 double f
(long long x
) { return x
*x
; }
2553 #
Return 1 if the target supports the __builtin_cpu_supports built
-in
,
2554 # including having a new enough library to support the test.
Cache the result.
2555 # Require at least a power7 to run
on.
2557 proc check_ppc_cpu_supports_hw_available
{ } {
2558 return [check_cached_effective_target ppc_cpu_supports_hw_available
{
2559 # Some simulators are known to not support VSX
/power8 instructions.
2560 #
For now
, disable
on Darwin
2561 if { [istarget powerpc
-*-eabi
]
2562 ||
[istarget powerpc
*-*-eabispe
]
2563 ||
[istarget
*-*-darwin
*]} {
2567 check_runtime_nocache ppc_cpu_supports_hw_available
{
2571 asm volatile
("xxlor vs0,vs0,vs0");
2573 asm volatile
("xxlor 0,0,0");
2575 if (!__builtin_cpu_supports
("vsx"))
2584 #
Return 1 if the target supports executing
750CL paired
-single instructions
, 0
2585 # otherwise.
Cache the result.
2587 proc check_750cl_hw_available
{ } {
2588 return [check_cached_effective_target
750cl_hw_available
{
2589 #
If this is not the right target
then we can skip the test.
2590 if { ![istarget powerpc
-*paired
*] } {
2593 check_runtime_nocache
750cl_hw_available
{
2597 asm volatile
("ps_mul v0,v0,v0");
2599 asm volatile
("ps_mul 0,0,0");
2608 #
Return 1 if the target supports executing power8 vector instructions
, 0
2609 # otherwise.
Cache the result.
2611 proc check_p8vector_hw_available
{ } {
2612 return [check_cached_effective_target p8vector_hw_available
{
2613 # Some simulators are known to not support VSX
/power8 instructions.
2614 #
For now
, disable
on Darwin
2615 if { [istarget powerpc
-*-eabi
]
2616 ||
[istarget powerpc
*-*-eabispe
]
2617 ||
[istarget
*-*-darwin
*]} {
2620 set options
"-mpower8-vector"
2621 check_runtime_nocache p8vector_hw_available
{
2625 asm volatile
("xxlorc vs0,vs0,vs0");
2627 asm volatile
("xxlorc 0,0,0");
2636 #
Return 1 if the target supports executing power9 vector instructions
, 0
2637 # otherwise.
Cache the result.
2639 proc check_p9vector_hw_available
{ } {
2640 return [check_cached_effective_target p9vector_hw_available
{
2641 # Some simulators are known to not support VSX
/power8
/power9
2642 # instructions.
For now
, disable
on Darwin.
2643 if { [istarget powerpc
-*-eabi
]
2644 ||
[istarget powerpc
*-*-eabispe
]
2645 ||
[istarget
*-*-darwin
*]} {
2648 set options
"-mpower9-vector"
2649 check_runtime_nocache p9vector_hw_available
{
2653 vector double v
= (vector double
) { 0.0, 0.0 };
2654 asm
("xsxexpdp %0,%1" : "+r" (e) : "wa" (v));
2662 #
Return 1 if the PowerPC target generates PC
-relative instructions
2663 # automatically
for targets that support PC
-relative instructions.
2664 proc check_effective_target_powerpc_pcrel
{ } {
2665 return [check_no_messages_and_pattern powerpc_pcrel \
2666 {\mpla\M
} assembly
{
2667 static unsigned short s
;
2668 unsigned short
*p_foo
(void
) { return &s
; }
2669 } {-O2
-mcpu
=power10
}]
2672 #
Return 1 if the PowerPC target generates prefixed instructions automatically
2673 #
for targets that support prefixed instructions.
2674 proc check_effective_target_powerpc_prefixed_addr
{ } {
2675 return [check_no_messages_and_pattern powerpc_prefixed_addr \
2676 {\mplwz\M
} assembly
{
2677 unsigned
int foo
(unsigned
int *p
) { return p
[0x12345]; }
2678 } {-O2
-mcpu
=power10
}]
2681 #
Return 1 if the target supports executing power9 modulo instructions
, 0
2682 # otherwise.
Cache the result.
2684 proc check_p9modulo_hw_available
{ } {
2685 return [check_cached_effective_target p9modulo_hw_available
{
2686 # Some simulators are known to not support VSX
/power8
/power9
2687 # instructions.
For now
, disable
on Darwin.
2688 if { [istarget powerpc
-*-eabi
]
2689 ||
[istarget powerpc
*-*-eabispe
]
2690 ||
[istarget
*-*-darwin
*]} {
2693 set options
"-mmodulo"
2694 check_runtime_nocache p9modulo_hw_available
{
2697 int i
= 5, j
= 3, r
= -1;
2698 asm
("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
2707 #
Return 1 if the target supports executing power10 instructions
, 0 otherwise.
2708 #
Cache the result. It is assumed that
if a simulator does not support the
2709 # power10 instructions
, that it will generate an error and this test will fail.
2711 proc check_power10_hw_available
{ } {
2712 return [check_cached_effective_target power10_hw_available
{
2713 check_runtime_nocache power10_hw_available
{
2716 /* Set e first and use
+r to check
if pli actually works.
*/
2718 asm
("pli %0,%1" : "+r" (e) : "n" (0x12345));
2727 #
Return 1 if the target supports executing MMA instructions
, 0 otherwise.
2728 #
Cache the result. It is assumed that
if a simulator does not support the
2729 # MMA instructions
, that it will generate an error and this test will fail.
2731 proc check_ppc_mma_hw_available
{ } {
2732 return [check_cached_effective_target ppc_mma_hw_available
{
2733 check_runtime_nocache ppc_mma_hw_available
{
2734 #
include <altivec.h
>
2735 typedef double v4sf_t __attribute__
((vector_size
(16)));
2742 __builtin_mma_xxsetaccz
(&acc0
);
2743 __builtin_mma_disassemble_acc
(result
, &acc0
);
2744 if (result
[0][0] != 0.0)
2752 #
Return 1 if the target supports executing __float128
on PowerPC via software
2753 # emulation
, 0 otherwise.
Cache the result.
2755 proc check_ppc_float128_sw_available
{ } {
2756 return [check_cached_effective_target ppc_float128_sw_available
{
2757 # Some simulators are known to not support VSX
/power8
/power9
2758 # instructions.
For now
, disable
on Darwin and VxWorks.
2759 if { [istarget
*-*-vxworks
*]
2760 ||
[istarget powerpc
-*-eabi
]
2761 ||
[istarget powerpc
*-*-eabispe
]
2762 ||
[istarget
*-*-darwin
*]} {
2765 set options
"-mfloat128 -mvsx"
2766 check_runtime_nocache ppc_float128_sw_available
{
2767 volatile __float128 x
= 1.0q
;
2768 volatile __float128 y
= 2.0q
;
2771 __float128 z
= x
+ y
;
2779 #
Return 1 if the target supports executing __float128
on PowerPC via power9
2780 # hardware instructions
, 0 otherwise.
Cache the result.
2782 proc check_ppc_float128_hw_available
{ } {
2783 return [check_cached_effective_target ppc_float128_hw_available
{
2784 # Some simulators are known to not support VSX
/power8
/power9
2785 # instructions.
For now
, disable
on Darwin.
2786 if { [istarget
*-*-vxworks
*]
2787 ||
[istarget powerpc
-*-eabi
]
2788 ||
[istarget powerpc
*-*-eabispe
]
2789 ||
[istarget
*-*-darwin
*]} {
2792 set options
"-mfloat128 -mvsx -mfloat128-hardware -mpower9-vector"
2793 check_runtime_nocache ppc_float128_hw_available
{
2794 volatile __float128 x
= 1.0q
;
2795 volatile __float128 y
= 2.0q
;
2798 __float128 z
= x
+ y
;
2799 __float128 w
= -1.0q
;
2801 __asm__
("xsaddqp %0,%1,%2" : "+v" (w) : "v" (x), "v" (y));
2802 return ((z
!= 3.0q
) ||
(z
!= w
));
2809 # See
if the __ieee128 keyword is understood.
2810 proc check_effective_target_ppc_ieee128_ok
{ } {
2811 return [check_cached_effective_target ppc_ieee128_ok
{
2812 # disable
on AIX and VxWorks.
2813 if { [istarget
*-*-aix
*]
2814 ||
[istarget
*-*-vxworks
*]} {
2817 set options
"-mfloat128"
2818 check_runtime_nocache ppc_ieee128_ok
{
2829 # Check
if GCC and GLIBC supports explicitly specifying that the long double
2830 # format uses the IBM
128-bit extended double format. Under little endian
2831 # PowerPC Linux
, you need GLIBC
2.32 or later to be able to use a different
2832 # long double format
for running a
program than the
system default.
2834 proc check_effective_target_long_double_ibm128
{ } {
2835 return [check_runtime_nocache long_double_ibm128
{
2838 /* use volatile to prevent optimization.
*/
2839 volatile __ibm128 a
= (__ibm128
) 3.0;
2840 volatile long double one
= 1.0L;
2841 volatile long double two
= 2.0L;
2842 volatile long double b
;
2848 if (sizeof
(long double
) != 16)
2851 /* eliminate removing volatile cast warning.
*/
2854 if (memcmp
(&a2
, &b2
, 16) != 0)
2856 sprintf
(buffer
, "%lg", b);
2857 return strcmp
(buffer
, "3") != 0;
2859 } [add_options_for_long_double_ibm128
""]]
2862 #
Return the appropriate options to specify that long double uses the IBM
2863 #
128-bit format
on PowerPC.
2865 proc add_options_for_long_double_ibm128
{ flags
} {
2866 if { [istarget powerpc
*-*-*] } {
2867 return "$flags -mlong-double-128 -Wno-psabi -mabi=ibmlongdouble"
2872 # Check
if GCC and GLIBC supports explicitly specifying that the long double
2873 # format uses the IEEE
128-bit format. Under little endian PowerPC Linux
, you
2874 # need GLIBC
2.32 or later to be able to use a different long double format
for
2875 # running a
program than the
system default.
2877 proc check_effective_target_long_double_ieee128
{ } {
2878 return [check_runtime_nocache long_double_ieee128
{
2881 /* use volatile to prevent optimization.
*/
2882 volatile _Float128 a
= 3.0f128
;
2883 volatile long double one
= 1.0L;
2884 volatile long double two
= 2.0L;
2885 volatile long double b
;
2891 if (sizeof
(long double
) != 16)
2894 /* eliminate removing volatile cast warning.
*/
2897 if (memcmp
(&a2
, &b2
, 16) != 0)
2899 sprintf
(buffer
, "%lg", b);
2900 return strcmp
(buffer
, "3") != 0;
2902 } [add_options_for_long_double_ieee128
""]]
2905 #
Return the appropriate options to specify that long double uses the IBM
2906 #
128-bit format
on PowerPC.
2907 proc add_options_for_long_double_ieee128
{ flags
} {
2908 if { [istarget powerpc
*-*-*] } {
2909 return "$flags -mlong-double-128 -Wno-psabi -mabi=ieeelongdouble"
2914 # Check
if GCC and GLIBC supports explicitly specifying that the long double
2915 # format uses the IEEE
64-bit. Under little endian PowerPC Linux
, you need
2916 # GLIBC
2.32 or later to be able to use a different long double format
for
2917 # running a
program than the
system default.
2919 proc check_effective_target_long_double_64bit
{ } {
2920 return [check_runtime_nocache long_double_64bit
{
2923 /* use volatile to prevent optimization.
*/
2924 volatile double a
= 3.0;
2925 volatile long double one
= 1.0L;
2926 volatile long double two
= 2.0L;
2927 volatile long double b
;
2933 if (sizeof
(long double
) != 8)
2936 /* eliminate removing volatile cast warning.
*/
2939 if (memcmp
(&a2
, &b2
, 16) != 0)
2941 sprintf
(buffer
, "%lg", b);
2942 return strcmp
(buffer
, "3") != 0;
2944 } [add_options_for_ppc_long_double_override_64bit
""]]
2947 #
Return the appropriate options to specify that long double uses the IEEE
2948 #
64-bit format
on PowerPC.
2950 proc add_options_for_long_double_64bit
{ flags
} {
2951 if { [istarget powerpc
*-*-*] } {
2952 return "$flags -mlong-double-64"
2957 #
Return 1 if the target supports executing VSX instructions
, 0
2958 # otherwise.
Cache the result.
2960 proc check_vsx_hw_available
{ } {
2961 return [check_cached_effective_target vsx_hw_available
{
2962 # Some simulators are known to not support VSX instructions.
2963 #
For now
, disable
on Darwin
2964 if { [istarget powerpc
-*-eabi
]
2965 ||
[istarget powerpc
*-*-eabispe
]
2966 ||
[istarget
*-*-darwin
*]} {
2970 check_runtime_nocache vsx_hw_available
{
2974 asm volatile
("xxlor vs0,vs0,vs0");
2976 asm volatile
("xxlor 0,0,0");
2985 #
Return 1 if the target supports executing AltiVec instructions
, 0
2986 # otherwise.
Cache the result.
2988 proc check_vmx_hw_available
{ } {
2989 return [check_cached_effective_target vmx_hw_available
{
2990 # Some simulators are known to not support VMX instructions.
2991 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] } {
2994 # Most targets don
't require special flags for this test case, but
2995 # Darwin does. Just to be sure, make sure VSX is not enabled for
2996 # the altivec tests.
2997 if { [istarget *-*-darwin*]
2998 || [istarget *-*-aix*] } {
2999 set options "-maltivec -mno-vsx"
3001 set options "-mno-vsx"
3003 check_runtime_nocache vmx_hw_available {
3007 asm volatile ("vor v0,v0,v0");
3009 asm volatile ("vor 0,0,0");
3018 proc check_ppc_recip_hw_available { } {
3019 return [check_cached_effective_target ppc_recip_hw_available {
3020 # Some simulators may not support FRE/FRES/FRSQRTE/FRSQRTES
3021 # For now, disable on Darwin
3022 if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} {
3025 set options "-mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb"
3026 check_runtime_nocache ppc_recip_hw_available {
3027 volatile double d_recip, d_rsqrt, d_four = 4.0;
3028 volatile float f_recip, f_rsqrt, f_four = 4.0f;
3031 asm volatile ("fres %0,%1" : "=f" (f_recip) : "f" (f_four));
3032 asm volatile ("fre %0,%1" : "=d" (d_recip) : "d" (d_four));
3033 asm volatile ("frsqrtes %0,%1" : "=f" (f_rsqrt) : "f" (f_four));
3034 asm volatile ("frsqrte %0,%1" : "=f" (d_rsqrt) : "d" (d_four));
3042 # Return 1 if the target supports executing AltiVec and Cell PPU
3043 # instructions, 0 otherwise. Cache the result.
3045 proc check_effective_target_cell_hw { } {
3046 return [check_cached_effective_target cell_hw_available {
3047 # Some simulators are known to not support VMX and PPU instructions.
3048 if { [istarget powerpc-*-eabi*] } {
3051 # Most targets don't require special flags
for this test
3052 # case
, but Darwin and AIX
do.
3053 if { [istarget
*-*-darwin
*]
3054 ||
[istarget
*-*-aix
*] } {
3055 set options
"-maltivec -mcpu=cell"
3057 set options
"-mcpu=cell"
3059 check_runtime_nocache cell_hw_available
{
3063 asm volatile
("vor v0,v0,v0");
3064 asm volatile
("lvlx v0,r0,r0");
3066 asm volatile
("vor 0,0,0");
3067 asm volatile
("lvlx 0,0,0");
3076 #
Return 1 if the target supports executing
64-bit instructions
, 0
3077 # otherwise.
Cache the result.
3079 proc check_effective_target_powerpc64
{ } {
3080 global powerpc64_available_saved
3083 if [info exists powerpc64_available_saved
] {
3084 verbose
"check_effective_target_powerpc64 returning saved $powerpc64_available_saved" 2
3086 set powerpc64_available_saved
0
3088 # Some simulators are known to not support powerpc64 instructions.
3089 if { [istarget powerpc
-*-eabi
*] ||
[istarget powerpc
-ibm
-aix
*] } {
3090 verbose
"check_effective_target_powerpc64 returning 0" 2
3091 return $powerpc64_available_saved
3094 #
Set up
, compile, and
execute a test
program containing a
64-bit
3095 # instruction.
Include the current process ID in the file
3096 # names to prevent conflicts with invocations
for multiple
3101 set f
[open $src
"w"]
3102 puts $f
"int main() {"
3103 puts $f
"#ifdef __MACH__"
3104 puts $f
" asm volatile (\"extsw r0,r0\");"
3106 puts $f
" asm volatile (\"extsw 0,0\");"
3108 puts $f
" return 0; }"
3111 set opts
"additional_flags=-mcpu=G5"
3113 verbose
"check_effective_target_powerpc64 compiling testfile $src" 2
3114 set lines
[$
{tool
}_target_compile $src $exe executable
"$opts"]
3117 if [string match
"" $lines] then {
3118 # No error message
, compilation succeeded.
3119 set result
[$
{tool
}_load
"./$exe" "" ""]
3120 set status [lindex $result
0]
3121 remote_file build
delete $exe
3122 verbose
"check_effective_target_powerpc64 testfile status is <$status>" 2
3124 if { $
status == "pass" } then {
3125 set powerpc64_available_saved
1
3128 verbose
"check_effective_target_powerpc64 testfile compilation failed" 2
3132 return $powerpc64_available_saved
3135 # GCC
3.4.0 for powerpc64
-*-linux
* included an ABI fix
for passing
3136 # complex float arguments. This affects gfortran tests that
call cabsf
3137 # in libm built by an earlier compiler.
Return 0 if libm uses the same
3138 #
argument passing as the compiler under test
, 1 otherwise.
3140 proc check_effective_target_broken_cplxf_arg
{ } {
3141 # Skip the work
for targets known not to be affected.
3142 if { ![istarget powerpc
*-*-linux
*] ||
![is
-effective
-target lp64
] } {
3146 return [check_cached_effective_target broken_cplxf_arg
{
3147 check_runtime_nocache broken_cplxf_arg
{
3148 #
include <complex.h
>
3149 extern void abort
(void
);
3150 float fabsf
(float
);
3151 float cabsf
(_Complex float
);
3158 if (fabsf
(f
- 5.0) > 0.0001)
3159 /* Yes
, it
's broken. */
3161 /* All fine, not broken. */
3168 # Return 1 is this is a TI C6X target supporting C67X instructions
3169 proc check_effective_target_ti_c67x { } {
3170 return [check_no_compiler_messages ti_c67x assembly {
3171 #if !defined(_TMS320C6700)
3172 #error !_TMS320C6700
3177 # Return 1 is this is a TI C6X target supporting C64X+ instructions
3178 proc check_effective_target_ti_c64xp { } {
3179 return [check_no_compiler_messages ti_c64xp assembly {
3180 #if !defined(_TMS320C6400_PLUS)
3181 #error !_TMS320C6400_PLUS
3186 # Check if a -march=... option is given, as part of (earlier) options.
3187 proc check_effective_target_march_option { } {
3188 return [check-flags [list "" { *-*-* } { "-march=*" } { "" } ]]
3191 proc check_alpha_max_hw_available { } {
3192 return [check_runtime alpha_max_hw_available {
3193 int main() { return __builtin_alpha_amask(1<<8) != 0; }
3197 # Returns true iff the FUNCTION is available on the target system.
3198 # (This is essentially a Tcl implementation of Autoconf's
3201 proc check_function_available
{ function
} {
3202 return [check_no_compiler_messages $
{function
}_available \
3208 int main
() { $function
(); }
3212 # Returns true iff
"fork" is available on the target system.
3214 proc check_fork_available
{} {
3215 if { [istarget
*-*-vxworks
*] } {
3216 # VxWorks doesn
't have fork but our way to test can't
3217 # tell as we
're doing partial links for kernel modules.
3220 if { [istarget cris-*-*] } {
3221 # Compiling and linking works, and an executable running e.g.
3222 # gcc.dg/torture/ftrapv-1.c works on now-historical hardware,
3223 # but the GNU simulator emits an error for the fork syscall.
3224 return [check_effective_target_hw]
3226 return [check_function_available "fork"]
3229 # Returns true iff "mkfifo" is available on the target system.
3231 proc check_mkfifo_available {} {
3232 if { [istarget *-*-cygwin*] } {
3233 # Cygwin has mkfifo, but support is incomplete.
3237 return [check_function_available "mkfifo"]
3240 # Returns true iff "__cxa_atexit" is used on the target system.
3242 proc check_cxa_atexit_available { } {
3243 return [check_cached_effective_target cxa_atexit_available {
3244 if { [istarget *-*-vxworks] } {
3245 # vxworks doesn't have __cxa_atexit but subsequent test passes.
3248 check_runtime_nocache cxa_atexit_available
{
3251 static unsigned
int count;
3268 Y
() { f
(); count = 2; }
3277 int main
() { return 0; }
3283 proc check_effective_target_objc2
{ } {
3284 return [check_no_compiler_messages objc2 object
{
3293 proc check_effective_target_next_runtime
{ } {
3294 return [check_no_compiler_messages objc2 object
{
3295 #ifdef __NEXT_RUNTIME__
3298 #error
!__NEXT_RUNTIME__
3303 #
Return 1 if we
're generating code for big-endian memory order.
3305 proc check_effective_target_be { } {
3306 return [check_no_compiler_messages be object {
3307 int dummy[__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ? 1 : -1];
3311 # Return 1 if we're generating code
for little
-endian memory order.
3313 proc check_effective_target_le
{ } {
3314 return [check_no_compiler_messages le object
{
3315 int dummy
[__BYTE_ORDER__
== __ORDER_LITTLE_ENDIAN__ ?
1 : -1];
3319 #
Return 1 if we can link a
program with
2+GB of data.
3321 proc check_effective_target_two_plus_gigs
{ } {
3322 return [check_no_compiler_messages two_plus_gigs executable
{
3323 char dummy
[0x80000000];
3324 int main
() { return 0; }
3328 #
Return 1 if we
're generating 32-bit code using default options, 0
3331 proc check_effective_target_ilp32 { } {
3332 return [check_no_compiler_messages ilp32 object {
3333 int dummy[sizeof (int) == 4
3334 && sizeof (void *) == 4
3335 && sizeof (long) == 4 ? 1 : -1];
3339 # Return 1 if we're generating ia32 code using default options
, 0
3342 proc check_effective_target_ia32
{ } {
3343 return [check_no_compiler_messages ia32 object
{
3344 int dummy
[sizeof
(int) == 4
3345 && sizeof
(void
*) == 4
3346 && sizeof
(long
) == 4 ?
1 : -1] = { __i386__
};
3350 #
Return 1 if we
're generating x32 code using default options, 0
3353 proc check_effective_target_x32 { } {
3354 return [check_no_compiler_messages x32 object {
3355 int dummy[sizeof (int) == 4
3356 && sizeof (void *) == 4
3357 && sizeof (long) == 4 ? 1 : -1] = { __x86_64__ };
3361 # Return 1 if we're generating
32-bit integers using default
3362 # options
, 0 otherwise.
3364 proc check_effective_target_int32
{ } {
3365 return [check_no_compiler_messages int32 object
{
3366 int dummy
[sizeof
(int) == 4 ?
1 : -1];
3370 #
Return 1 if we
're generating 32-bit or larger integers using default
3371 # options, 0 otherwise.
3373 proc check_effective_target_int32plus { } {
3374 return [check_no_compiler_messages int32plus object {
3375 int dummy[sizeof (int) >= 4 ? 1 : -1];
3379 # Return 1 if we're generating
64-bit long long using default options
,
3382 proc check_effective_target_longlong64
{ } {
3383 return [check_no_compiler_messages longlong64 object
{
3384 int dummy
[sizeof
(long long
) == 8 ?
1 : -1];
3388 #
Return 1 if we
're generating 32-bit or larger pointers using default
3389 # options, 0 otherwise.
3391 proc check_effective_target_ptr32plus { } {
3392 # The msp430 has 16-bit or 20-bit pointers. The 20-bit pointer is stored
3393 # in a 32-bit slot when in memory, so sizeof(void *) returns 4, but it
3394 # cannot really hold a 32-bit address, so we always return false here.
3395 if { [istarget msp430-*-*] } {
3399 return [check_no_compiler_messages ptr32plus object {
3400 int dummy[sizeof (void *) >= 4 ? 1 : -1];
3404 # Return 1 if we support 16-bit or larger array and structure sizes
3405 # using default options, 0 otherwise.
3406 # This implies at least a 20-bit address space, as no targets have an address
3407 # space between 16 and 20 bits.
3409 proc check_effective_target_size20plus { } {
3410 return [check_no_compiler_messages size20plus object {
3415 # Return 1 if target supports function pointers, 0 otherwise.
3417 proc check_effective_target_function_pointers { } {
3418 if { [istarget pru-*-*] } {
3419 return [check_no_compiler_messages func_ptr_avail assembly {
3420 #ifdef __PRU_EABI_GNU__
3428 # Return 1 if target supports arbitrarily large return values, 0 otherwise.
3430 proc check_effective_target_large_return_values { } {
3431 if { [istarget pru-*-*] } {
3432 return [check_no_compiler_messages large_return_values assembly {
3433 #ifdef __PRU_EABI_GNU__
3440 # Return 1 if we support 20-bit or larger array and structure sizes
3441 # using default options, 0 otherwise.
3442 # This implies at least a 24-bit address space, as no targets have an address
3443 # space between 20 and 24 bits.
3445 proc check_effective_target_size24plus { } {
3446 return [check_no_compiler_messages size24plus object {
3447 char dummy[524289L];
3451 # Return 1 if we support 24-bit or larger array and structure sizes
3452 # using default options, 0 otherwise.
3453 # This implies at least a 32-bit address space, as no targets have an address
3454 # space between 24 and 32 bits.
3456 proc check_effective_target_size32plus { } {
3457 return [check_no_compiler_messages size32plus object {
3458 char dummy[16777217L];
3462 # Returns 1 if we're generating
16-bit or smaller integers with the
3463 # default options
, 0 otherwise.
3465 proc check_effective_target_int16
{ } {
3466 return [check_no_compiler_messages int16 object
{
3467 int dummy
[sizeof
(int) < 4 ?
1 : -1];
3471 #
Return 1 if we
're generating 64-bit code using default options, 0
3474 proc check_effective_target_lp64 { } {
3475 return [check_no_compiler_messages lp64 object {
3476 int dummy[sizeof (int) == 4
3477 && sizeof (void *) == 8
3478 && sizeof (long) == 8 ? 1 : -1];
3482 # Return 1 if we're generating
64-bit code using default llp64 options
,
3485 proc check_effective_target_llp64
{ } {
3486 return [check_no_compiler_messages llp64 object
{
3487 int dummy
[sizeof
(int) == 4
3488 && sizeof
(void
*) == 8
3489 && sizeof
(long long
) == 8
3490 && sizeof
(long
) == 4 ?
1 : -1];
3494 #
Return 1 if long and
int have different sizes
,
3497 proc check_effective_target_long_neq_int
{ } {
3498 return [check_no_compiler_messages long_ne_int object
{
3499 int dummy
[sizeof
(int) != sizeof
(long
) ?
1 : -1];
3503 #
Return 1 if int size is equal to float size
,
3506 proc check_effective_target_int_eq_float
{ } {
3507 return [check_no_compiler_messages int_eq_float object
{
3508 int dummy
[sizeof
(int) >= sizeof
(float
) ?
1 : -1];
3512 #
Return 1 if short size is equal to
int size
,
3515 proc check_effective_target_short_eq_int
{ } {
3516 return [check_no_compiler_messages short_eq_int object
{
3517 int dummy
[sizeof
(short
) == sizeof
(int) ?
1 : -1];
3521 #
Return 1 if pointer size is equal to short size
,
3524 proc check_effective_target_ptr_eq_short
{ } {
3525 return [check_no_compiler_messages ptr_eq_short object
{
3526 int dummy
[sizeof
(void
*) == sizeof
(short
) ?
1 : -1];
3530 #
Return 1 if pointer size is equal to long size
,
3533 proc check_effective_target_ptr_eq_long
{ } {
3534 # sizeof
(void
*) == 4 for msp430
-elf
-mlarge which is equal to
3535 # sizeof
(long
). Avoid false positive.
3536 if { [istarget msp430
-*-*] } {
3539 return [check_no_compiler_messages ptr_eq_long object
{
3540 int dummy
[sizeof
(void
*) == sizeof
(long
) ?
1 : -1];
3544 #
Return 1 if the target supports long double larger than double
,
3547 proc check_effective_target_large_long_double
{ } {
3548 return [check_no_compiler_messages large_long_double object
{
3549 int dummy
[sizeof
(long double
) > sizeof
(double
) ?
1 : -1];
3553 #
Return 1 if the target supports double larger than float
,
3556 proc check_effective_target_large_double
{ } {
3557 return [check_no_compiler_messages large_double object
{
3558 int dummy
[sizeof
(double
) > sizeof
(float
) ?
1 : -1];
3562 #
Return 1 if the target supports long double of
128 bits
,
3565 proc check_effective_target_longdouble128
{ } {
3566 return [check_no_compiler_messages longdouble128 object
{
3567 int dummy
[sizeof
(long double
) == 16 ?
1 : -1];
3571 #
Return 1 if the target supports long double of
64 bits
,
3574 proc check_effective_target_longdouble64
{ } {
3575 return [check_no_compiler_messages longdouble64 object
{
3576 int dummy
[sizeof
(long double
) == 8 ?
1 : -1];
3580 #
Return 1 if the target supports double of
64 bits
,
3583 proc check_effective_target_double64
{ } {
3584 return [check_no_compiler_messages double64 object
{
3585 int dummy
[sizeof
(double
) == 8 ?
1 : -1];
3589 #
Return 1 if the target supports double of at least
64 bits
,
3592 proc check_effective_target_double64plus
{ } {
3593 return [check_no_compiler_messages double64plus object
{
3594 int dummy
[sizeof
(double
) >= 8 ?
1 : -1];
3598 #
Return 1 if the target supports
'w' suffix
on floating constant
3601 proc check_effective_target_has_w_floating_suffix
{ } {
3603 if [check_effective_target_c
++] {
3604 append opts
"-std=gnu++03"
3606 return [check_no_compiler_messages w_fp_suffix object
{
3611 #
Return 1 if the target supports
'q' suffix
on floating constant
3614 proc check_effective_target_has_q_floating_suffix
{ } {
3616 if [check_effective_target_c
++] {
3617 append opts
"-std=gnu++03"
3619 return [check_no_compiler_messages q_fp_suffix object
{
3624 #
Return 1 if the target supports the _FloatN
/ _FloatNx type
3625 # indicated in the function
name, 0 otherwise.
3627 proc check_effective_target_float16
{} {
3628 return [check_no_compiler_messages_nocache float16 object
{
3629 _Float16 foo
(_Float16 x
) { return x
; }
3630 } [add_options_for_float16
""]]
3633 proc check_effective_target_float32
{} {
3634 return [check_no_compiler_messages_nocache float32 object
{
3636 } [add_options_for_float32
""]]
3639 proc check_effective_target_float64
{} {
3640 return [check_no_compiler_messages_nocache float64 object
{
3642 } [add_options_for_float64
""]]
3645 proc check_effective_target_float128
{} {
3646 return [check_no_compiler_messages_nocache float128 object
{
3648 } [add_options_for_float128
""]]
3651 proc check_effective_target_float32x
{} {
3652 return [check_no_compiler_messages_nocache float32x object
{
3654 } [add_options_for_float32x
""]]
3657 proc check_effective_target_float64x
{} {
3658 return [check_no_compiler_messages_nocache float64x object
{
3660 } [add_options_for_float64x
""]]
3663 proc check_effective_target_float128x
{} {
3664 return [check_no_compiler_messages_nocache float128x object
{
3666 } [add_options_for_float128x
""]]
3669 # Likewise
, but runtime support
for any special options used as well
3670 # as
compile-time support is required.
3672 proc check_effective_target_float16_runtime
{} {
3673 return [check_effective_target_float16
]
3676 proc check_effective_target_float32_runtime
{} {
3677 return [check_effective_target_float32
]
3680 proc check_effective_target_float64_runtime
{} {
3681 return [check_effective_target_float64
]
3684 proc check_effective_target_float128_runtime
{} {
3685 if { ![check_effective_target_float128
] } {
3688 if { [istarget powerpc
*-*-*] } {
3689 return [check_effective_target_base_quadfloat_support
]
3694 proc check_effective_target_float32x_runtime
{} {
3695 return [check_effective_target_float32x
]
3698 proc check_effective_target_float64x_runtime
{} {
3699 if { ![check_effective_target_float64x
] } {
3702 if { [istarget powerpc
*-*-*] } {
3703 return [check_effective_target_base_quadfloat_support
]
3708 proc check_effective_target_float128x_runtime
{} {
3709 return [check_effective_target_float128x
]
3712 #
Return 1 if the target hardware supports
any options added
for
3713 # _FloatN and _FloatNx types
, 0 otherwise.
3715 proc check_effective_target_floatn_nx_runtime
{} {
3716 if { [istarget powerpc
*-*-aix
*] } {
3719 if { [istarget powerpc
*-*-*] } {
3720 return [check_effective_target_base_quadfloat_support
]
3725 # Add options needed to use the _FloatN
/ _FloatNx type indicated in
3726 # the function
name.
3728 proc add_options_for_float16
{ flags
} {
3729 if { [istarget arm
*-*-*] } {
3730 return "$flags -mfp16-format=ieee"
3732 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
3733 return "$flags -msse2"
3738 proc add_options_for_float32
{ flags
} {
3742 proc add_options_for_float64
{ flags
} {
3746 proc add_options_for_float128
{ flags
} {
3747 return [add_options_for___float128
"$flags"]
3750 proc add_options_for_float32x
{ flags
} {
3754 proc add_options_for_float64x
{ flags
} {
3755 return [add_options_for___float128
"$flags"]
3758 proc add_options_for_float128x
{ flags
} {
3762 #
Return 1 if the target supports __float128
,
3765 proc check_effective_target___float128
{ } {
3766 if { [istarget powerpc
*-*-*] } {
3767 return [check_ppc_float128_sw_available
]
3769 if { [istarget ia64
-*-*]
3770 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
3776 proc add_options_for___float128
{ flags
} {
3777 if { [istarget powerpc
*-*-linux
*] } {
3778 return "$flags -mfloat128 -mvsx"
3783 #
Return 1 if the target supports
any special run
-time requirements
3784 #
for __float128 or _Float128
,
3787 proc check_effective_target_base_quadfloat_support
{ } {
3788 if { [istarget powerpc
*-*-*] } {
3789 return [check_vsx_hw_available
]
3794 #
Return 1 if the target supports the __bf16 type
, 0 otherwise.
3796 proc check_effective_target_bfloat16
{} {
3797 return [check_no_compiler_messages_nocache bfloat16 object
{
3798 __bf16 foo
(__bf16 x
) { return x
+ x
; }
3799 } [add_options_for_bfloat16
""]]
3802 proc check_effective_target_bfloat16_runtime
{} {
3803 return [check_effective_target_bfloat16
]
3806 proc add_options_for_bfloat16
{ flags
} {
3810 #
Return 1 if the target supports all four forms of fused multiply
-add
3811 #
(fma
, fms
, fnma
, and fnms
) for both float and double.
3813 proc check_effective_target_scalar_all_fma
{ } {
3814 return [istarget aarch64
*-*-*]
3817 #
Return 1 if the target supports compiling fixed
-point
,
3820 proc check_effective_target_fixed_point
{ } {
3821 return [check_no_compiler_messages fixed_point object
{
3822 _Sat _Fract x
; _Sat _Accum y
;
3826 #
Return 1 if the target supports _BitInt
(N
), 0 otherwise.
3828 proc check_effective_target_bitint
{ } {
3829 return [check_no_compiler_messages bitint object
{
3830 _BitInt
(2) a
= 1wb
;
3831 unsigned _BitInt
(__BITINT_MAXWIDTH__
) b
= 0uwb
;
3835 #
Return 1 if the target supports _BitInt
(128), 0 otherwise.
3837 proc check_effective_target_bitint128
{ } {
3838 return [check_no_compiler_messages bitint128 object
{
3839 _BitInt
(2) a
= 1wb
;
3840 unsigned _BitInt
(128) b
= 0uwb
;
3844 #
Return 1 if the target supports _BitInt
(575), 0 otherwise.
3846 proc check_effective_target_bitint575
{ } {
3847 return [check_no_compiler_messages bitint575 object
{
3848 _BitInt
(2) a
= 1wb
;
3849 unsigned _BitInt
(575) b
= 0uwb
;
3853 #
Return 1 if the target supports compiling decimal floating point
,
3856 proc check_effective_target_dfp_nocache
{ } {
3857 verbose
"check_effective_target_dfp_nocache: compiling source" 2
3858 set ret
[check_no_compiler_messages_nocache dfp object
{
3859 float x __attribute__
((mode(DD
)));
3861 verbose
"check_effective_target_dfp_nocache: returning $ret" 2
3865 proc check_effective_target_dfprt_nocache
{ } {
3866 return [check_runtime_nocache dfprt
{
3867 typedef float d64 __attribute__
((mode(DD
)));
3868 d64 x
= 1.2df
, y
= 2.3dd
, z
;
3869 int main
() { z
= x
+ y
; return 0; }
3873 #
Return 1 if the target supports compiling Decimal Floating Point
,
3876 # This won
't change for different subtargets so cache the result.
3878 proc check_effective_target_dfp { } {
3879 return [check_cached_effective_target dfp {
3880 check_effective_target_dfp_nocache
3884 # Return 1 if the target supports linking and executing Decimal Floating
3885 # Point, 0 otherwise.
3887 # This won't change
for different subtargets so
cache the result.
3889 proc check_effective_target_dfprt
{ } {
3890 return [check_cached_effective_target dfprt
{
3891 check_effective_target_dfprt_nocache
3895 #
Return 1 if the target uses the BID format
for Decimal Floating
3896 # Point
, 0 otherwise.
3898 proc check_effective_target_dfp_bid
{ } {
3899 if { [istarget aarch64
*-*-*]
3900 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]} {
3906 #
Return 1 iff target has unsigned plain
'char' by default.
3908 proc check_effective_target_unsigned_char
{} {
3909 return [check_no_compiler_messages unsigned_char assembly
{
3914 proc check_effective_target_powerpc_popcntb_ok
{ } {
3915 return [check_cached_effective_target powerpc_popcntb_ok
{
3917 # Disable
on Darwin.
3918 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] ||
[istarget
*-*-darwin
*]} {
3921 check_runtime_nocache powerpc_popcntb_ok
{
3923 volatile
int a
= 0x12345678;
3926 asm volatile
("popcntb %0,%1" : "=r" (r) : "r" (a));
3934 #
Return 1 if the target supports executing DFP hardware instructions
,
3935 #
0 otherwise.
Cache the result.
3937 proc check_dfp_hw_available
{ } {
3938 return [check_cached_effective_target dfp_hw_available
{
3939 #
For now
, disable
on Darwin
3940 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] ||
[istarget
*-*-darwin
*]} {
3943 check_runtime_nocache dfp_hw_available
{
3944 volatile _Decimal64 r
;
3945 volatile _Decimal64 a
= 4.0DD
;
3946 volatile _Decimal64 b
= 2.0DD
;
3949 asm volatile
("dadd %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3950 asm volatile
("dsub %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3951 asm volatile
("dmul %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3952 asm volatile
("ddiv %0,%1,%2" : "=d" (r) : "d" (a), "d" (b));
3955 } "-mcpu=power6 -mhard-float"
3960 #
Return 1 if the target supports compiling and assembling UCN
, 0 otherwise.
3962 proc check_effective_target_ucn_nocache
{ } {
3963 #
-std
=c99 is only valid
for C
3964 if [check_effective_target_c
] {
3965 set ucnopts
"-std=c99"
3969 verbose
"check_effective_target_ucn_nocache: compiling source" 2
3970 set ret
[check_no_compiler_messages_nocache ucn object
{
3973 verbose
"check_effective_target_ucn_nocache: returning $ret" 2
3977 #
Return 1 if the target supports compiling and assembling UCN
, 0 otherwise.
3979 # This won
't change for different subtargets, so cache the result.
3981 proc check_effective_target_ucn { } {
3982 return [check_cached_effective_target ucn {
3983 check_effective_target_ucn_nocache
3987 # Return 1 if the target needs a command line argument to enable a SIMD
3990 proc check_effective_target_vect_cmdline_needed { } {
3991 global et_vect_cmdline_needed_target_name
3993 if { ![info exists et_vect_cmdline_needed_target_name] } {
3994 set et_vect_cmdline_needed_target_name ""
3997 # If the target has changed since we set the cached value, clear it.
3998 set current_target [current_target_name]
3999 if { $current_target != $et_vect_cmdline_needed_target_name } {
4000 verbose "check_effective_target_vect_cmdline_needed: `$et_vect_cmdline_needed_target_name' `$current_target
'" 2
4001 set et_vect_cmdline_needed_target_name $current_target
4002 if { [info exists et_vect_cmdline_needed_saved] } {
4003 verbose "check_effective_target_vect_cmdline_needed: removing cached result" 2
4004 unset et_vect_cmdline_needed_saved
4008 return [check_cached_effective_target vect_cmdline_needed {
4009 if { [istarget alpha*-*-*]
4010 || [istarget ia64-*-*]
4011 || (([istarget i?86-*-*] || [istarget x86_64-*-*])
4012 && ![is-effective-target ia32])
4013 || ([istarget powerpc*-*-*]
4014 && ([check_effective_target_powerpc_spe]
4015 || [check_effective_target_powerpc_altivec]))
4016 || ([istarget sparc*-*-*] && [check_effective_target_sparc_vis])
4017 || ([istarget arm*-*-*] && [check_effective_target_arm_neon])
4018 || [istarget aarch64*-*-*]
4019 || [istarget amdgcn*-*-*]
4020 || [istarget riscv*-*-*]} {
4027 # Return 1 if the target supports hardware vectors of int, 0 otherwise.
4029 # This won't change
for different subtargets so
cache the result.
4031 proc check_effective_target_vect_int
{ } {
4032 return [check_cached_effective_target_indexed vect_int
{
4034 [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
4035 ||
([istarget powerpc
*-*-*]
4036 && ![istarget powerpc
-*-linux
*paired
*])
4037 ||
[istarget amdgcn
-*-*]
4038 ||
[istarget sparc
*-*-*]
4039 ||
[istarget alpha
*-*-*]
4040 ||
[istarget ia64
-*-*]
4041 ||
[istarget aarch64
*-*-*]
4042 ||
[is
-effective
-target arm_neon
]
4043 ||
([istarget mips
*-*-*]
4044 && ([et
-is
-effective
-target mips_loongson_mmi
]
4045 ||
[et
-is
-effective
-target mips_msa
]))
4046 ||
([istarget s390
*-*-*]
4047 && [check_effective_target_s390_vx
])
4048 ||
([istarget riscv
*-*-*]
4049 && [check_effective_target_riscv_v
])
4053 #
Return 1 if the target supports hardware vectorization of complex additions of
4054 # byte
, 0 otherwise.
4056 # This won
't change for different subtargets so cache the result.
4058 proc check_effective_target_vect_complex_add_byte { } {
4059 return [check_cached_effective_target_indexed vect_complex_add_byte {
4061 ([check_effective_target_aarch64_sve2]
4062 && [check_effective_target_aarch64_little_endian])
4063 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4064 && [check_effective_target_arm_little_endian])
4068 # Return 1 if the target supports hardware vectorization of complex additions of
4069 # short, 0 otherwise.
4071 # This won't change
for different subtargets so
cache the result.
4073 proc check_effective_target_vect_complex_add_short
{ } {
4074 return [check_cached_effective_target_indexed vect_complex_add_short
{
4076 ([check_effective_target_aarch64_sve2
]
4077 && [check_effective_target_aarch64_little_endian
])
4078 ||
([check_effective_target_arm_v8_1m_mve_fp_ok
]
4079 && [check_effective_target_arm_little_endian
])
4083 #
Return 1 if the target supports hardware vectorization of complex additions of
4086 # This won
't change for different subtargets so cache the result.
4088 proc check_effective_target_vect_complex_add_int { } {
4089 return [check_cached_effective_target_indexed vect_complex_add_int {
4091 ([check_effective_target_aarch64_sve2]
4092 && [check_effective_target_aarch64_little_endian])
4093 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4094 && [check_effective_target_arm_little_endian])
4098 # Return 1 if the target supports hardware vectorization of complex additions of
4099 # long, 0 otherwise.
4101 # This won't change
for different subtargets so
cache the result.
4103 proc check_effective_target_vect_complex_add_long
{ } {
4104 return [check_cached_effective_target_indexed vect_complex_add_long
{
4106 ([check_effective_target_aarch64_sve2
]
4107 && [check_effective_target_aarch64_little_endian
])
4108 ||
([check_effective_target_arm_v8_1m_mve_fp_ok
]
4109 && [check_effective_target_arm_little_endian
])
4113 #
Return 1 if the target supports hardware vectorization of complex additions of
4114 # half
, 0 otherwise.
4116 # This won
't change for different subtargets so cache the result.
4118 proc check_effective_target_vect_complex_add_half { } {
4119 return [check_cached_effective_target_indexed vect_complex_add_half {
4121 ([check_effective_target_arm_v8_3a_fp16_complex_neon_ok]
4122 && ([check_effective_target_aarch64_little_endian]
4123 || [check_effective_target_arm_little_endian]))
4124 || ([check_effective_target_aarch64_sve2]
4125 && [check_effective_target_aarch64_little_endian])
4126 || ([check_effective_target_arm_v8_1m_mve_fp_ok]
4127 && [check_effective_target_arm_little_endian])
4131 # Return 1 if the target supports hardware vectorization of complex additions of
4132 # float, 0 otherwise.
4134 # This won't change
for different subtargets so
cache the result.
4136 proc check_effective_target_vect_complex_add_float
{ } {
4137 return [check_cached_effective_target_indexed vect_complex_add_float
{
4139 ([check_effective_target_arm_v8_3a_complex_neon_ok
]
4140 && ([check_effective_target_aarch64_little_endian
]
4141 ||
[check_effective_target_arm_little_endian
]))
4142 ||
([check_effective_target_aarch64_sve2
]
4143 && [check_effective_target_aarch64_little_endian
])
4144 ||
([check_effective_target_arm_v8_1m_mve_fp_ok
]
4145 && [check_effective_target_arm_little_endian
])
4149 #
Return 1 if the target supports hardware vectorization of complex additions of
4150 # double
, 0 otherwise.
4152 # This won
't change for different subtargets so cache the result.
4154 proc check_effective_target_vect_complex_add_double { } {
4155 return [check_cached_effective_target_indexed vect_complex_add_double {
4157 (([check_effective_target_arm_v8_3a_complex_neon_ok]
4158 && [check_effective_target_aarch64_little_endian])
4159 || ([check_effective_target_aarch64_sve2]
4160 && [check_effective_target_aarch64_little_endian]))
4164 # Return 1 if the target supports signed int->float conversion
4167 proc check_effective_target_vect_intfloat_cvt { } {
4168 return [check_cached_effective_target_indexed vect_intfloat_cvt {
4169 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
4170 || ([istarget powerpc*-*-*]
4171 && ![istarget powerpc-*-linux*paired*])
4172 || [is-effective-target arm_neon]
4173 || ([istarget mips*-*-*]
4174 && [et-is-effective-target mips_msa])
4175 || [istarget amdgcn-*-*]
4176 || ([istarget s390*-*-*]
4177 && [check_effective_target_s390_vxe2])
4178 || ([istarget riscv*-*-*]
4179 && [check_effective_target_riscv_v]) }}]
4182 # Return 1 if the target supports signed double->int conversion
4185 proc check_effective_target_vect_doubleint_cvt { } {
4186 return [check_cached_effective_target_indexed vect_doubleint_cvt {
4187 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4188 && [check_no_compiler_messages vect_doubleint_cvt assembly {
4189 #ifdef __tune_atom__
4190 # error No double vectorizer support.
4193 || [istarget aarch64*-*-*]
4194 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4195 || ([istarget mips*-*-*]
4196 && [et-is-effective-target mips_msa])
4197 || ([istarget s390*-*-*]
4198 && [check_effective_target_s390_vx])
4199 || ([istarget riscv*-*-*]
4200 && [check_effective_target_riscv_v]) }}]
4203 # Return 1 if the target supports signed int->double conversion
4206 proc check_effective_target_vect_intdouble_cvt { } {
4207 return [check_cached_effective_target_indexed vect_intdouble_cvt {
4208 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4209 && [check_no_compiler_messages vect_intdouble_cvt assembly {
4210 #ifdef __tune_atom__
4211 # error No double vectorizer support.
4214 || [istarget aarch64*-*-*]
4215 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
4216 || ([istarget mips*-*-*]
4217 && [et-is-effective-target mips_msa])
4218 || ([istarget s390*-*-*]
4219 && [check_effective_target_s390_vx])
4220 || ([istarget riscv*-*-*]
4221 && [check_effective_target_riscv_v]) }}]
4224 #Return 1 if we're supporting __int128
for target
, 0 otherwise.
4226 proc check_effective_target_int128
{ } {
4227 return [check_no_compiler_messages int128 object
{
4229 #ifndef __SIZEOF_INT128__
4238 #
Return 1 if the target supports unsigned
int->float conversion
4241 proc check_effective_target_vect_uintfloat_cvt
{ } {
4242 return [check_cached_effective_target_indexed vect_uintfloat_cvt
{
4243 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
4244 ||
([istarget powerpc
*-*-*]
4245 && ![istarget powerpc
-*-linux
*paired
*])
4246 ||
[istarget aarch64
*-*-*]
4247 ||
[is
-effective
-target arm_neon
]
4248 ||
([istarget mips
*-*-*]
4249 && [et
-is
-effective
-target mips_msa
])
4250 ||
[istarget amdgcn
-*-*]
4251 ||
([istarget s390
*-*-*]
4252 && [check_effective_target_s390_vxe2
])
4253 ||
([istarget riscv
*-*-*]
4254 && [check_effective_target_riscv_v
]) }}]
4258 #
Return 1 if the target supports signed float
->int conversion
4261 proc check_effective_target_vect_floatint_cvt
{ } {
4262 return [check_cached_effective_target_indexed vect_floatint_cvt
{
4263 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
4264 ||
([istarget powerpc
*-*-*]
4265 && ![istarget powerpc
-*-linux
*paired
*])
4266 ||
[is
-effective
-target arm_neon
]
4267 ||
([istarget mips
*-*-*]
4268 && [et
-is
-effective
-target mips_msa
])
4269 ||
[istarget amdgcn
-*-*]
4270 ||
([istarget s390
*-*-*]
4271 && [check_effective_target_s390_vxe2
])
4272 ||
([istarget riscv
*-*-*]
4273 && [check_effective_target_riscv_v
]) }}]
4276 #
Return 1 if the target supports unsigned float
->int conversion
4279 proc check_effective_target_vect_floatuint_cvt
{ } {
4280 return [check_cached_effective_target_indexed vect_floatuint_cvt
{
4281 expr
{ ([istarget powerpc
*-*-*]
4282 && ![istarget powerpc
-*-linux
*paired
*])
4283 ||
[is
-effective
-target arm_neon
]
4284 ||
([istarget mips
*-*-*]
4285 && [et
-is
-effective
-target mips_msa
])
4286 ||
[istarget amdgcn
-*-*]
4287 ||
([istarget s390
*-*-*]
4288 && [check_effective_target_s390_vxe2
])
4289 ||
([istarget riscv
*-*-*]
4290 && [check_effective_target_riscv_v
]) }}]
4293 #
Return 1 if the target supports vector
integer char
-> long long extend optab
4296 proc check_effective_target_vect_ext_char_longlong
{ } {
4297 return [check_cached_effective_target_indexed vect_ext_char_longlong
{
4298 expr
{ ([istarget riscv
*-*-*]
4299 && [check_effective_target_riscv_v
]) }}]
4302 #
Return 1 if peeling
for alignment might be profitable
on the target
4305 proc check_effective_target_vect_peeling_profitable
{ } {
4306 return [check_cached_effective_target_indexed vect_peeling_profitable
{
4307 expr
{ ([istarget s390
*-*-*]
4308 && [check_effective_target_s390_vx
])
4309 ||
[check_effective_target_vect_element_align_preferred
] }}]
4312 #
Return 1 if the target supports #pragma omp declare simd
, 0 otherwise.
4314 # This won
't change for different subtargets so cache the result.
4316 proc check_effective_target_vect_simd_clones { } {
4317 # On i?86/x86_64 #pragma omp declare simd builds a sse2, avx,
4318 # avx2 and avx512f clone. Only the right clone for the
4319 # specified arch will be chosen, but still we need to at least
4320 # be able to assemble avx512f.
4321 return [check_cached_effective_target_indexed vect_simd_clones {
4322 expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
4323 && [check_effective_target_avx512f])
4324 || [istarget amdgcn-*-*] }}]
4327 # Return 1 if this is a AArch64 target supporting big endian
4328 proc check_effective_target_aarch64_big_endian { } {
4329 return [check_no_compiler_messages aarch64_big_endian assembly {
4330 #if !defined(__aarch64__) || !defined(__AARCH64EB__)
4331 #error !__aarch64__ || !__AARCH64EB__
4336 # Return 1 if this is a AArch64 target supporting little endian
4337 proc check_effective_target_aarch64_little_endian { } {
4338 if { ![istarget aarch64*-*-*] } {
4342 return [check_no_compiler_messages aarch64_little_endian assembly {
4343 #if !defined(__aarch64__) || defined(__AARCH64EB__)
4349 # Return 1 if this is an AArch64 target supporting SVE.
4350 proc check_effective_target_aarch64_sve { } {
4351 if { ![istarget aarch64*-*-*] } {
4354 return [check_no_compiler_messages aarch64_sve assembly {
4355 #if !defined (__ARM_FEATURE_SVE)
4361 # Return 1 if this is an AArch64 target supporting SVE2.
4362 proc check_effective_target_aarch64_sve2 { } {
4363 if { ![istarget aarch64*-*-*] } {
4366 return [check_no_compiler_messages aarch64_sve2 assembly {
4367 #if !defined (__ARM_FEATURE_SVE2)
4373 # Return 1 if this is an AArch64 target only supporting SVE (not SVE2).
4374 proc check_effective_target_aarch64_sve1_only { } {
4375 return [expr { [check_effective_target_aarch64_sve]
4376 && ![check_effective_target_aarch64_sve2] }]
4379 # Return the size in bits of an SVE vector, or 0 if the size is variable.
4380 proc aarch64_sve_bits { } {
4381 return [check_cached_effective_target aarch64_sve_bits {
4384 set src dummy[pid].c
4385 set f [open $src "w"]
4386 puts $f "int bits = __ARM_FEATURE_SVE_BITS;"
4388 set output [${tool}_target_compile $src "" preprocess ""]
4391 regsub {.*bits = ([^;]*);.*} $output {\1} bits
4396 # Return 1 if this is an AArch64 target that generates instructions for SME.
4397 proc check_effective_target_aarch64_sme { } {
4398 if { ![istarget aarch64*-*-*] } {
4401 return [check_no_compiler_messages aarch64_sme assembly {
4402 #if !defined (__ARM_FEATURE_SME)
4408 # Return 1 if this is an AArch64 target that generates instructions for SME.
4409 proc check_effective_target_aarch64_sme2 { } {
4410 if { ![istarget aarch64*-*-*] } {
4413 return [check_no_compiler_messages aarch64_sme2 assembly {
4414 #if !defined (__ARM_FEATURE_SME2)
4420 # Return 1 if this is a compiler supporting ARC atomic operations
4421 proc check_effective_target_arc_atomic { } {
4422 return [check_no_compiler_messages arc_atomic assembly {
4423 #if !defined(__ARC_ATOMIC__)
4429 # Return 1 if this is an arm target using 32-bit instructions
4430 proc check_effective_target_arm32 { } {
4431 if { ![istarget arm*-*-*] } {
4435 return [check_no_compiler_messages arm32 assembly {
4436 #if !defined(__arm__) || (defined(__thumb__) && !defined(__thumb2__))
4437 #error !__arm || __thumb__ && !__thumb2__
4442 # Return 1 if this is an arm target not using Thumb
4443 proc check_effective_target_arm_nothumb { } {
4444 if { ![istarget arm*-*-*] } {
4448 return [check_no_compiler_messages arm_nothumb assembly {
4449 #if !defined(__arm__) || (defined(__thumb__) || defined(__thumb2__))
4450 #error !__arm__ || __thumb || __thumb2__
4455 # Return 1 if this is a little-endian ARM target
4456 proc check_effective_target_arm_little_endian { } {
4457 if { ![istarget arm*-*-*] } {
4461 return [check_no_compiler_messages arm_little_endian assembly {
4462 #if !defined(__arm__) || !defined(__ARMEL__)
4463 #error !__arm__ || !__ARMEL__
4468 # Return 1 if this is an ARM target that only supports aligned vector accesses
4469 proc check_effective_target_arm_vect_no_misalign { } {
4470 if { ![istarget arm*-*-*] } {
4474 return [check_no_compiler_messages arm_vect_no_misalign assembly {
4475 #if !defined(__arm__) \
4476 || (defined(__ARM_FEATURE_UNALIGNED) \
4477 && defined(__ARMEL__))
4478 #error !__arm__ || (__ARMEL__ && __ARM_FEATURE_UNALIGNED)
4484 # Return 1 if this is an ARM target supporting -mfloat-abi=soft. Some
4485 # multilibs may be incompatible with this option.
4487 proc check_effective_target_arm_soft_ok { } {
4488 return [check_no_compiler_messages arm_soft_ok object {
4491 int main (void) { return 0; }
4492 } "-mfloat-abi=soft"]
4495 # Return 1 if this is an ARM target supporting -mfloat-abi=soft even
4496 # for linking. Some multilibs may be incompatible with this option,
4497 # and some linkers may reject incompatible options.
4499 proc check_effective_target_arm_soft_ok_link { } {
4500 return [check_no_compiler_messages arm_soft_ok_link executable {
4503 int main (void) { return 0; }
4504 } "-mfloat-abi=soft"]
4507 # Return 1 if this is an ARM target supporting -mfpu=vfp with an
4510 proc check_effective_target_arm_vfp_ok_nocache { } {
4511 global et_arm_vfp_flags
4512 set et_arm_vfp_flags ""
4513 if { [check_effective_target_arm32] } {
4514 foreach flags {"-mfpu=vfp" "-mfpu=vfp -mfloat-abi=softfp" "-mfpu=vfp -mfloat-abi=hard"} {
4515 if { [check_no_compiler_messages_nocache arm_vfp_ok object {
4517 #error __ARM_FP not defined
4520 set et_arm_vfp_flags $flags
4529 proc check_effective_target_arm_vfp_ok { } {
4530 return [check_cached_effective_target arm_vfp_ok \
4531 check_effective_target_arm_vfp_ok_nocache]
4534 # Add the options needed to compile code with -mfpu=vfp. We need either
4535 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4536 # specified by the multilib, use it.
4538 proc add_options_for_arm_vfp { flags } {
4539 if { ! [check_effective_target_arm_vfp_ok] } {
4542 global et_arm_vfp_flags
4543 return "$flags $et_arm_vfp_flags"
4546 # Return 1 if this is an ARM target supporting -mfpu=vfp3
4547 # -mfloat-abi=softfp.
4549 proc check_effective_target_arm_vfp3_ok { } {
4550 if { [check_effective_target_arm32] } {
4551 return [check_no_compiler_messages arm_vfp3_ok object {
4553 } "-mfpu=vfp3 -mfloat-abi=softfp"]
4559 # Return 1 if this is an ARM target supporting -mfpu=fp-armv8
4560 # -mfloat-abi=softfp.
4561 proc check_effective_target_arm_v8_vfp_ok {} {
4562 if { [check_effective_target_arm32] } {
4563 return [check_no_compiler_messages arm_v8_vfp_ok object {
4566 __asm__ volatile ("vrinta.f32.f32 s0, s0");
4569 } "-mfpu=fp-armv8 -mfloat-abi=softfp"]
4575 # Return 1 if this is an ARM target supporting -mfpu=vfp
4576 # -mfloat-abi=hard. Some multilibs may be incompatible with these
4579 proc check_effective_target_arm_hard_vfp_ok { } {
4580 if { [check_effective_target_arm32]
4581 && ! [check-flags [list "" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" }]] } {
4582 return [check_no_compiler_messages arm_hard_vfp_ok executable {
4583 int main() { return 0;}
4584 } "-mfpu=vfp -mfloat-abi=hard"]
4590 # Return 1 if this is an ARM target defining __ARM_FP. We may need
4591 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4592 # incompatible with these options. Also set et_arm_fp_flags to the
4593 # best options to add.
4595 proc check_effective_target_arm_fp_ok_nocache { } {
4596 global et_arm_fp_flags
4597 set et_arm_fp_flags ""
4598 if { [check_effective_target_arm32] } {
4599 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4600 if { [check_no_compiler_messages_nocache arm_fp_ok object {
4602 #error __ARM_FP not defined
4605 set et_arm_fp_flags $flags
4614 proc check_effective_target_arm_fp_ok { } {
4615 return [check_cached_effective_target arm_fp_ok \
4616 check_effective_target_arm_fp_ok_nocache]
4619 # Add the options needed to define __ARM_FP. We need either
4620 # -mfloat-abi=softfp or -mfloat-abi=hard, but if one is already
4621 # specified by the multilib, use it.
4623 proc add_options_for_arm_fp { flags } {
4624 if { ! [check_effective_target_arm_fp_ok] } {
4627 global et_arm_fp_flags
4628 return "$flags $et_arm_fp_flags"
4631 # Return 1 if this is an ARM target defining __ARM_FP with
4632 # double-precision support. We may need -mfloat-abi=softfp or
4633 # equivalent options. Some multilibs may be incompatible with these
4634 # options. Also set et_arm_fp_dp_flags to the best options to add.
4636 proc check_effective_target_arm_fp_dp_ok_nocache { } {
4637 global et_arm_fp_dp_flags
4638 set et_arm_fp_dp_flags ""
4639 if { [check_effective_target_arm32] } {
4640 foreach flags {"" "-mfloat-abi=softfp" "-mfloat-abi=hard"} {
4641 if { [check_no_compiler_messages_nocache arm_fp_dp_ok object {
4643 #error __ARM_FP not defined
4645 #if ((__ARM_FP & 8) == 0)
4646 #error __ARM_FP indicates that double-precision is not supported
4649 set et_arm_fp_dp_flags $flags
4658 proc check_effective_target_arm_fp_dp_ok { } {
4659 return [check_cached_effective_target arm_fp_dp_ok \
4660 check_effective_target_arm_fp_dp_ok_nocache]
4663 # Add the options needed to define __ARM_FP with double-precision
4664 # support. We need either -mfloat-abi=softfp or -mfloat-abi=hard, but
4665 # if one is already specified by the multilib, use it.
4667 proc add_options_for_arm_fp_dp { flags } {
4668 if { ! [check_effective_target_arm_fp_dp_ok] } {
4671 global et_arm_fp_dp_flags
4672 return "$flags $et_arm_fp_dp_flags"
4675 # Return 1 if this is an ARM target that supports DSP multiply with
4676 # current multilib flags.
4678 proc check_effective_target_arm_dsp { } {
4679 return [check_no_compiler_messages arm_dsp assembly {
4680 #ifndef __ARM_FEATURE_DSP
4683 #include <arm_acle.h>
4688 # Return 1 if this is an ARM target that supports unaligned word/halfword
4689 # load/store instructions.
4691 proc check_effective_target_arm_unaligned { } {
4692 return [check_no_compiler_messages arm_unaligned assembly {
4693 #ifndef __ARM_FEATURE_UNALIGNED
4694 #error no unaligned support
4700 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4701 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4702 # incompatible with these options. Also set et_arm_crypto_flags to the
4703 # best options to add.
4705 proc check_effective_target_arm_crypto_ok_nocache { } {
4706 global et_arm_crypto_flags
4707 set et_arm_crypto_flags ""
4708 if { [check_effective_target_arm_v8_neon_ok] } {
4709 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=crypto-neon-fp-armv8" "-mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp"} {
4710 if { [check_no_compiler_messages_nocache arm_crypto_ok object {
4711 #include "arm_neon.h"
4713 foo (uint8x16_t a, uint8x16_t b)
4715 return vaeseq_u8 (a, b);
4718 set et_arm_crypto_flags $flags
4727 # Return 1 if this is an ARM target supporting -mfpu=crypto-neon-fp-armv8
4729 proc check_effective_target_arm_crypto_ok { } {
4730 return [check_cached_effective_target arm_crypto_ok \
4731 check_effective_target_arm_crypto_ok_nocache]
4734 # Add options for crypto extensions.
4735 proc add_options_for_arm_crypto { flags } {
4736 if { ! [check_effective_target_arm_crypto_ok] } {
4739 global et_arm_crypto_flags
4740 return "$flags $et_arm_crypto_flags"
4743 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4744 # or -mfloat-abi=hard, but if one is already specified by the
4745 # multilib, use it. Similarly, if a -mfpu option already enables
4746 # NEON, do not add -mfpu=neon.
4748 proc add_options_for_arm_neon { flags } {
4749 if { ! [check_effective_target_arm_neon_ok] } {
4752 global et_arm_neon_flags
4753 return "$flags $et_arm_neon_flags"
4756 proc add_options_for_arm_v8_vfp { flags } {
4757 if { ! [check_effective_target_arm_v8_vfp_ok] } {
4760 return "$flags -mfpu=fp-armv8 -mfloat-abi=softfp"
4763 proc add_options_for_arm_v8_neon { flags } {
4764 if { ! [check_effective_target_arm_v8_neon_ok] } {
4767 global et_arm_v8_neon_flags
4768 return "$flags $et_arm_v8_neon_flags -march=armv8-a"
4771 # Add the options needed for ARMv8.1 Adv.SIMD. Also adds the ARMv8 NEON
4772 # options for AArch64 and for ARM.
4774 proc add_options_for_arm_v8_1a_neon { flags } {
4775 if { ! [check_effective_target_arm_v8_1a_neon_ok] } {
4778 global et_arm_v8_1a_neon_flags
4779 return "$flags $et_arm_v8_1a_neon_flags"
4782 # Add the options needed for ARMv8.2 with the scalar FP16 extension.
4783 # Also adds the ARMv8 FP options for ARM and for AArch64.
4785 proc add_options_for_arm_v8_2a_fp16_scalar { flags } {
4786 if { ! [check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
4789 global et_arm_v8_2a_fp16_scalar_flags
4790 return "$flags $et_arm_v8_2a_fp16_scalar_flags"
4793 # Add the options needed for ARMv8.2 with the FP16 extension. Also adds
4794 # the ARMv8 NEON options for ARM and for AArch64.
4796 proc add_options_for_arm_v8_2a_fp16_neon { flags } {
4797 if { ! [check_effective_target_arm_v8_2a_fp16_neon_ok] } {
4800 global et_arm_v8_2a_fp16_neon_flags
4801 return "$flags $et_arm_v8_2a_fp16_neon_flags"
4804 proc add_options_for_arm_crc { flags } {
4805 if { ! [check_effective_target_arm_crc_ok] } {
4808 global et_arm_crc_flags
4809 return "$flags $et_arm_crc_flags"
4812 # Add the options needed for NEON. We need either -mfloat-abi=softfp
4813 # or -mfloat-abi=hard, but if one is already specified by the
4814 # multilib, use it. Similarly, if a -mfpu option already enables
4815 # NEON, do not add -mfpu=neon.
4817 proc add_options_for_arm_neonv2 { flags } {
4818 if { ! [check_effective_target_arm_neonv2_ok] } {
4821 global et_arm_neonv2_flags
4822 return "$flags $et_arm_neonv2_flags"
4825 # Add the options needed for vfp3.
4826 proc add_options_for_arm_vfp3 { flags } {
4827 if { ! [check_effective_target_arm_vfp3_ok] } {
4830 return "$flags -mfpu=vfp3 -mfloat-abi=softfp"
4833 # Return 1 if this is an ARM target supporting -mfpu=neon
4834 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
4835 # incompatible with these options. Also set et_arm_neon_flags to the
4836 # best options to add.
4838 proc check_effective_target_arm_neon_ok_nocache { } {
4839 global et_arm_neon_flags
4840 set et_arm_neon_flags ""
4841 if { [check_effective_target_arm32] } {
4842 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp" "-mfpu=neon -mfloat-abi=softfp -march=armv7-a" "-mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard" "-mfpu=neon -mfloat-abi=hard -march=armv7-a"} {
4843 if { [check_no_compiler_messages_nocache arm_neon_ok object {
4844 #include <arm_neon.h>
4846 #ifndef __ARM_NEON__
4849 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
4850 configured for -mcpu=arm926ej-s, for example. */
4851 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M
'
4852 #error Architecture does not support NEON.
4855 set et_arm_neon_flags $flags
4864 proc check_effective_target_arm_neon_ok { } {
4865 return [check_cached_effective_target arm_neon_ok \
4866 check_effective_target_arm_neon_ok_nocache]
4870 # Return 1 if this is an ARM target supporting the SIMD32 intrinsics
4871 # from arm_acle.h. Some multilibs may be incompatible with these options.
4872 # Also set et_arm_simd32_flags to the best options to add.
4873 # arm_acle.h includes stdint.h which can cause trouble with incompatible
4874 # -mfloat-abi= options.
4876 proc check_effective_target_arm_simd32_ok_nocache { } {
4877 global et_arm_simd32_flags
4878 set et_arm_simd32_flags ""
4879 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard"} {
4880 if { [check_no_compiler_messages_nocache arm_simd32_ok object {
4881 #include <arm_acle.h>
4883 #ifndef __ARM_FEATURE_SIMD32
4887 set et_arm_simd32_flags $flags
4895 proc check_effective_target_arm_simd32_ok { } {
4896 return [check_cached_effective_target arm_simd32_ok \
4897 check_effective_target_arm_simd32_ok_nocache]
4900 proc add_options_for_arm_simd32 { flags } {
4901 if { ! [check_effective_target_arm_simd32_ok] } {
4904 global et_arm_simd32_flags
4905 return "$flags $et_arm_simd32_flags"
4908 # Return 1 if this is an ARM target supporting the __ssat and __usat
4909 # saturation intrinsics from arm_acle.h. Some multilibs may be
4910 # incompatible with these options. Also set et_arm_sat_flags to the
4911 # best options to add. arm_acle.h includes stdint.h which can cause
4912 # trouble with incompatible -mfloat-abi= options.
4914 proc check_effective_target_arm_sat_ok_nocache { } {
4915 global et_arm_sat_flags
4916 set et_arm_sat_flags ""
4917 foreach flags {"" "-march=armv6" "-march=armv6 -mfloat-abi=softfp" "-march=armv6 -mfloat-abi=hard -mfpu=vfp"} {
4918 if { [check_no_compiler_messages_nocache et_arm_sat_flags object {
4919 #include <arm_acle.h>
4921 #ifndef __ARM_FEATURE_SAT
4925 set et_arm_sat_flags $flags
4933 proc check_effective_target_arm_sat_ok { } {
4934 return [check_cached_effective_target et_arm_sat_flags \
4935 check_effective_target_arm_sat_ok_nocache]
4938 proc add_options_for_arm_sat { flags } {
4939 if { ! [check_effective_target_arm_sat_ok] } {
4942 global et_arm_sat_flags
4943 return "$flags $et_arm_sat_flags"
4946 # Return 1 if this is an ARM target supporting the DSP intrinsics from
4947 # arm_acle.h. Some multilibs may be incompatible with these options.
4948 # Also set et_arm_dsp_flags to the best options to add.
4949 # arm_acle.h includes stdint.h which can cause trouble with incompatible
4950 # -mfloat-abi= options.
4951 # check_effective_target_arm_dsp also exists, which checks the current
4952 # multilib, without trying other options.
4954 proc check_effective_target_arm_dsp_ok_nocache { } {
4955 global et_arm_dsp_flags
4956 set et_arm_dsp_flags ""
4957 foreach flags {"" "-march=armv5te" "-march=armv5te -mfloat-abi=softfp" "-march=armv5te -mfloat-abi=hard"} {
4958 if { [check_no_compiler_messages_nocache et_arm_dsp_ok object {
4959 #include <arm_acle.h>
4961 #ifndef __ARM_FEATURE_DSP
4965 set et_arm_dsp_flags $flags
4973 proc check_effective_target_arm_dsp_ok { } {
4974 return [check_cached_effective_target et_arm_dsp_flags \
4975 check_effective_target_arm_dsp_ok_nocache]
4978 proc add_options_for_arm_dsp { flags } {
4979 if { ! [check_effective_target_arm_dsp_ok] } {
4982 global et_arm_dsp_flags
4983 return "$flags $et_arm_dsp_flags"
4986 # Return 1 if this is an ARM target supporting -mfpu=neon without any
4987 # -mfloat-abi= option. Useful in tests where add_options is not
4988 # supported (such as lto tests).
4990 proc check_effective_target_arm_neon_ok_no_float_abi_nocache { } {
4991 if { [check_effective_target_arm32] } {
4992 foreach flags {"-mfpu=neon"} {
4993 if { [check_no_compiler_messages_nocache arm_neon_ok_no_float_abi object {
4994 #include <arm_neon.h>
4996 #ifndef __ARM_NEON__
4999 /* Avoid the case where a test adds -mfpu=neon, but the toolchain is
5000 configured for -mcpu=arm926ej-s, for example. */
5001 #if __ARM_ARCH < 7 || __ARM_ARCH_PROFILE == 'M
'
5002 #error Architecture does not support NEON.
5013 proc check_effective_target_arm_neon_ok_no_float_abi { } {
5014 return [check_cached_effective_target arm_neon_ok_no_float_abi \
5015 check_effective_target_arm_neon_ok_no_float_abi_nocache]
5018 proc check_effective_target_arm_crc_ok_nocache { } {
5019 global et_arm_crc_flags
5020 set et_arm_crc_flags "-march=armv8-a+crc"
5021 return [check_no_compiler_messages_nocache arm_crc_ok object {
5022 #if !defined (__ARM_FEATURE_CRC32)
5025 #include <arm_acle.h>
5026 } "$et_arm_crc_flags"]
5029 proc check_effective_target_arm_crc_ok { } {
5030 return [check_cached_effective_target arm_crc_ok \
5031 check_effective_target_arm_crc_ok_nocache]
5034 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5035 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5036 # incompatible with these options. Also set et_arm_neon_fp16_flags to
5037 # the best options to add.
5039 proc check_effective_target_arm_neon_fp16_ok_nocache { } {
5040 global et_arm_neon_fp16_flags
5041 global et_arm_neon_flags
5042 set et_arm_neon_fp16_flags ""
5043 if { [check_effective_target_arm32]
5044 && [check_effective_target_arm_neon_ok] } {
5045 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5046 "-mfpu=neon-fp16 -mfloat-abi=softfp"
5047 "-mfp16-format=ieee"
5048 "-mfloat-abi=softfp -mfp16-format=ieee"
5049 "-mfpu=neon-fp16 -mfp16-format=ieee"
5050 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5051 if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
5052 #include "arm_neon.h"
5054 foo (float32x4_t arg)
5056 return vcvt_f16_f32 (arg);
5058 } "$et_arm_neon_flags $flags"] } {
5059 set et_arm_neon_fp16_flags [concat $et_arm_neon_flags $flags]
5068 proc check_effective_target_arm_neon_fp16_ok { } {
5069 return [check_cached_effective_target arm_neon_fp16_ok \
5070 check_effective_target_arm_neon_fp16_ok_nocache]
5073 # Return 1 if this is an ARM target supporting -mfpu=neon-fp16
5074 # and -mfloat-abi=softfp together. Some multilibs may be
5075 # incompatible with these options. Also set et_arm_neon_softfp_fp16_flags to
5076 # the best options to add.
5078 proc check_effective_target_arm_neon_softfp_fp16_ok_nocache { } {
5079 global et_arm_neon_softfp_fp16_flags
5080 global et_arm_neon_flags
5081 set et_arm_neon_softfp_fp16_flags ""
5082 if { [check_effective_target_arm32]
5083 && [check_effective_target_arm_neon_ok] } {
5084 foreach flags {"-mfpu=neon-fp16 -mfloat-abi=softfp"
5085 "-mfpu=neon-fp16 -mfloat-abi=softfp -mfp16-format=ieee"} {
5086 if { [check_no_compiler_messages_nocache arm_neon_softfp_fp16_ok object {
5087 #include "arm_neon.h"
5089 foo (float32x4_t arg)
5091 return vcvt_f16_f32 (arg);
5093 } "$et_arm_neon_flags $flags"] } {
5094 set et_arm_neon_softfp_fp16_flags [concat $et_arm_neon_flags $flags]
5103 proc check_effective_target_arm_neon_softfp_fp16_ok { } {
5104 return [check_cached_effective_target arm_neon_softfp_fp16_ok \
5105 check_effective_target_arm_neon_softfp_fp16_ok_nocache]
5110 proc check_effective_target_arm_neon_fp16_hw { } {
5111 if {! [check_effective_target_arm_neon_fp16_ok] } {
5114 global et_arm_neon_fp16_flags
5115 check_runtime arm_neon_fp16_hw {
5117 main (int argc, char **argv)
5119 asm ("vcvt.f32.f16 q1, d0");
5122 } $et_arm_neon_fp16_flags
5125 proc add_options_for_arm_neon_fp16 { flags } {
5126 if { ! [check_effective_target_arm_neon_fp16_ok] } {
5129 global et_arm_neon_fp16_flags
5130 return "$flags $et_arm_neon_fp16_flags"
5133 proc add_options_for_arm_neon_softfp_fp16 { flags } {
5134 if { ! [check_effective_target_arm_neon_softfp_fp16_ok] } {
5137 global et_arm_neon_softfp_fp16_flags
5138 return "$flags $et_arm_neon_softfp_fp16_flags"
5141 proc add_options_for_aarch64_sve { flags } {
5142 if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } {
5145 return "$flags -march=armv8.2-a+sve"
5148 # Return 1 if this is an ARM target supporting the FP16 alternative
5149 # format. Some multilibs may be incompatible with the options needed. Also
5150 # set et_arm_neon_fp16_flags to the best options to add.
5152 proc check_effective_target_arm_fp16_alternative_ok_nocache { } {
5153 if { [istarget *-*-vxworks7*] } {
5154 # Not supported by the target system.
5157 global et_arm_neon_fp16_flags
5158 set et_arm_neon_fp16_flags ""
5159 if { [check_effective_target_arm32] } {
5160 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5161 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5162 if { [check_no_compiler_messages_nocache \
5163 arm_fp16_alternative_ok object {
5164 #if !defined (__ARM_FP16_FORMAT_ALTERNATIVE)
5165 #error __ARM_FP16_FORMAT_ALTERNATIVE not defined
5167 } "$flags -mfp16-format=alternative"] } {
5168 set et_arm_neon_fp16_flags "$flags -mfp16-format=alternative"
5177 proc check_effective_target_arm_fp16_alternative_ok { } {
5178 return [check_cached_effective_target arm_fp16_alternative_ok \
5179 check_effective_target_arm_fp16_alternative_ok_nocache]
5182 # Return 1 if this is an ARM target supports specifying the FP16 none
5183 # format. Some multilibs may be incompatible with the options needed.
5185 proc check_effective_target_arm_fp16_none_ok_nocache { } {
5186 if { [check_effective_target_arm32] } {
5187 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp16"
5188 "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
5189 if { [check_no_compiler_messages_nocache \
5190 arm_fp16_none_ok object {
5191 #if defined (__ARM_FP16_FORMAT_ALTERNATIVE)
5192 #error __ARM_FP16_FORMAT_ALTERNATIVE defined
5194 #if defined (__ARM_FP16_FORMAT_IEEE)
5195 #error __ARM_FP16_FORMAT_IEEE defined
5197 } "$flags -mfp16-format=none"] } {
5206 proc check_effective_target_arm_fp16_none_ok { } {
5207 return [check_cached_effective_target arm_fp16_none_ok \
5208 check_effective_target_arm_fp16_none_ok_nocache]
5211 # Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8
5212 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5213 # incompatible with these options. Also set et_arm_v8_neon_flags to the
5214 # best options to add.
5216 proc check_effective_target_arm_v8_neon_ok_nocache { } {
5217 global et_arm_v8_neon_flags
5218 set et_arm_v8_neon_flags ""
5219 if { [check_effective_target_arm32] } {
5220 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
5221 if { [check_no_compiler_messages_nocache arm_v8_neon_ok object {
5223 #error not armv8 or later
5225 #include "arm_neon.h"
5229 __asm__ volatile ("vrintn.f32 q0, q0");
5231 } "$flags -march=armv8-a"] } {
5232 set et_arm_v8_neon_flags $flags
5241 proc check_effective_target_arm_v8_neon_ok { } {
5242 return [check_cached_effective_target arm_v8_neon_ok \
5243 check_effective_target_arm_v8_neon_ok_nocache]
5246 # Return 1 if this is an ARM target supporting -mfpu=neon-vfpv4
5247 # -mfloat-abi=softfp or equivalent options. Some multilibs may be
5248 # incompatible with these options. Also set et_arm_neonv2_flags to the
5249 # best options to add.
5251 proc check_effective_target_arm_neonv2_ok_nocache { } {
5252 global et_arm_neonv2_flags
5253 global et_arm_neon_flags
5254 set et_arm_neonv2_flags ""
5255 if { [check_effective_target_arm32]
5256 && [check_effective_target_arm_neon_ok] } {
5257 foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
5258 if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
5259 #include "arm_neon.h"
5261 foo (float32x2_t a, float32x2_t b, float32x2_t c)
5263 return vfma_f32 (a, b, c);
5265 } "$et_arm_neon_flags $flags"] } {
5266 set et_arm_neonv2_flags [concat $et_arm_neon_flags $flags]
5275 proc check_effective_target_arm_neonv2_ok { } {
5276 return [check_cached_effective_target arm_neonv2_ok \
5277 check_effective_target_arm_neonv2_ok_nocache]
5280 # Add the options needed for VFP FP16 support. We need either
5281 # -mfloat-abi=softfp or -mfloat-abi=hard. If one is already specified by
5282 # the multilib, use it.
5284 proc add_options_for_arm_fp16 { flags } {
5285 if { ! [check_effective_target_arm_fp16_ok] } {
5288 global et_arm_fp16_flags
5289 return "$flags $et_arm_fp16_flags"
5292 # Add the options needed to enable support for IEEE format
5293 # half-precision support. This is valid for ARM targets.
5295 proc add_options_for_arm_fp16_ieee { flags } {
5296 if { ! [check_effective_target_arm_fp16_ok] } {
5299 global et_arm_fp16_flags
5300 return "$flags $et_arm_fp16_flags -mfp16-format=ieee"
5303 # Add the options needed to enable support for ARM Alternative format
5304 # half-precision support. This is valid for ARM targets.
5306 proc add_options_for_arm_fp16_alternative { flags } {
5307 if { ! [check_effective_target_arm_fp16_ok] } {
5310 global et_arm_fp16_flags
5311 return "$flags $et_arm_fp16_flags -mfp16-format=alternative"
5314 # Return 1 if this is an ARM target that can support a VFP fp16 variant.
5315 # Skip multilibs that are incompatible with these options and set
5316 # et_arm_fp16_flags to the best options to add. This test is valid for
5319 proc check_effective_target_arm_fp16_ok_nocache { } {
5320 global et_arm_fp16_flags
5321 set et_arm_fp16_flags ""
5322 if { ! [check_effective_target_arm32] } {
5326 [list "" { *-*-* } { "-mfpu=*" } \
5327 { "-mfpu=*fp16*" "-mfpu=*fpv[4-9]*" \
5328 "-mfpu=*fpv[1-9][0-9]*" "-mfpu=*fp-armv8*" } ]] {
5329 # Multilib flags would override -mfpu.
5332 if [check-flags [list "" { *-*-* } { "-mfloat-abi=soft" } { "" } ]] {
5333 # Must generate floating-point instructions.
5336 if [check_effective_target_arm_hf_eabi] {
5337 # Use existing float-abi and force an fpu which supports fp16
5338 set et_arm_fp16_flags "-mfpu=vfpv4"
5341 if [check-flags [list "" { *-*-* } { "-mfpu=*" } { "" } ]] {
5342 # The existing -mfpu value is OK; use it, but add softfp.
5343 set et_arm_fp16_flags "-mfloat-abi=softfp"
5346 # Add -mfpu for a VFP fp16 variant since there is no preprocessor
5347 # macro to check for this support.
5348 set flags "-mfpu=vfpv4 -mfloat-abi=softfp"
5349 if { [check_no_compiler_messages_nocache arm_fp16_ok assembly {
5352 set et_arm_fp16_flags "$flags"
5359 proc check_effective_target_arm_fp16_ok { } {
5360 return [check_cached_effective_target arm_fp16_ok \
5361 check_effective_target_arm_fp16_ok_nocache]
5364 # Return 1 if the target supports executing VFP FP16 instructions, 0
5365 # otherwise. This test is valid for ARM only.
5367 proc check_effective_target_arm_fp16_hw { } {
5368 if {! [check_effective_target_arm_fp16_ok] } {
5371 global et_arm_fp16_flags
5372 check_runtime arm_fp16_hw {
5374 main (int argc, char **argv)
5378 asm ("vcvtb.f32.f16 %0, %1"
5379 : "=w" (r) : "w" (a)
5380 : /* No clobbers. */);
5381 return (r == 1.0) ? 0 : 1;
5383 } "$et_arm_fp16_flags -mfp16-format=ieee"
5386 # Creates a series of routines that return 1 if the given architecture
5387 # can be selected and a routine to give the flags to select that architecture
5388 # Note: Extra flags may be added to disable options from newer compilers
5389 # (Thumb in particular - but others may be added in the future).
5390 # Warning: Do not use check_effective_target_arm_arch_*_ok for architecture
5391 # extension (eg. ARMv8.1-A) since there is no macro defined for them. See
5392 # how only __ARM_ARCH_8A__ is checked for ARMv8.1-A.
5393 # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
5394 # /* { dg-add-options arm_arch_v5t } */
5395 # /* { dg-require-effective-target arm_arch_v5t_multilib } */
5396 foreach { armfunc armflag armdefs } {
5397 v4 "-march=armv4 -marm" __ARM_ARCH_4__
5398 v4t "-march=armv4t -mfloat-abi=softfp" __ARM_ARCH_4T__
5399 v4t_arm "-march=armv4t -marm" "__ARM_ARCH_4T__ && !__thumb__"
5400 v4t_thumb "-march=armv4t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_4T__ && __thumb__"
5401 v5t "-march=armv5t -mfloat-abi=softfp" __ARM_ARCH_5T__
5402 v5t_arm "-march=armv5t -marm" "__ARM_ARCH_5T__ && !__thumb__"
5403 v5t_thumb "-march=armv5t -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5T__ && __thumb__"
5404 v5te "-march=armv5te+fp -mfloat-abi=softfp" __ARM_ARCH_5TE__
5405 v5te_arm "-march=armv5te+fp -marm" "__ARM_ARCH_5TE__ && !__thumb__"
5406 v5te_thumb "-march=armv5te+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_5TE__ && __thumb__"
5407 xscale_arm "-mcpu=xscale -mfloat-abi=soft -marm" "__XSCALE__ && !__thumb__"
5408 v6 "-march=armv6+fp -mfloat-abi=softfp" __ARM_ARCH_6__
5409 v6_arm "-march=armv6+fp -marm" "__ARM_ARCH_6__ && !__thumb__"
5410 v6_thumb "-march=armv6+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6__ && __thumb__"
5411 v6k "-march=armv6k+fp -mfloat-abi=softfp" __ARM_ARCH_6K__
5412 v6k_arm "-march=armv6k+fp -marm" "__ARM_ARCH_6K__ && !__thumb__"
5413 v6k_thumb "-march=armv6k+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6K__ && __thumb__"
5414 v6t2 "-march=armv6t2+fp" __ARM_ARCH_6T2__
5415 v6z "-march=armv6z+fp -mfloat-abi=softfp" __ARM_ARCH_6Z__
5416 v6z_arm "-march=armv6z+fp -marm" "__ARM_ARCH_6Z__ && !__thumb__"
5417 v6z_thumb "-march=armv6z+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6Z__ && __thumb__"
5418 v6m "-march=armv6-m -mthumb -mfloat-abi=soft" __ARM_ARCH_6M__
5419 v7a "-march=armv7-a+fp" __ARM_ARCH_7A__
5420 v7a_arm "-march=armv7-a+fp -marm" "__ARM_ARCH_7A__ && !__thumb__"
5421 v7a_neon "-march=armv7-a+simd -mfpu=auto -mfloat-abi=softfp" "__ARM_ARCH_7A__ && __ARM_NEON__"
5422 v7r "-march=armv7-r+fp" __ARM_ARCH_7R__
5423 v7m "-march=armv7-m -mthumb -mfloat-abi=soft" __ARM_ARCH_7M__
5424 v7em "-march=armv7e-m+fp -mthumb" __ARM_ARCH_7EM__
5425 v7ve "-march=armv7ve+fp -marm"
5426 "__ARM_ARCH_7A__ && __ARM_FEATURE_IDIV"
5427 v8a "-march=armv8-a+simd" __ARM_ARCH_8A__
5428 v8a_hard "-march=armv8-a+simd -mfpu=auto -mfloat-abi=hard" __ARM_ARCH_8A__
5429 v8_1a "-march=armv8.1-a+simd" __ARM_ARCH_8A__
5430 v8_2a "-march=armv8.2-a+simd" __ARM_ARCH_8A__
5431 v8r "-march=armv8-r+fp.sp" __ARM_ARCH_8R__
5432 v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
5433 __ARM_ARCH_8M_BASE__
5434 v8m_main "-march=armv8-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5435 v8_1m_main "-march=armv8.1-m.main+fp -mthumb" __ARM_ARCH_8M_MAIN__
5436 v9a "-march=armv9-a+simd" __ARM_ARCH_9A__ } {
5437 eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
5438 proc check_effective_target_arm_arch_FUNC_ok { } {
5439 return [check_no_compiler_messages arm_arch_FUNC_ok assembly {
5451 proc add_options_for_arm_arch_FUNC { flags } {
5452 return "$flags FLAG"
5455 proc check_effective_target_arm_arch_FUNC_link { } {
5456 return [check_no_compiler_messages arm_arch_FUNC_link executable {
5459 int main (void) { return 0; }
5460 } [add_options_for_arm_arch_FUNC ""]]
5463 proc check_effective_target_arm_arch_FUNC_multilib { } {
5464 return [check_runtime arm_arch_FUNC_multilib {
5470 } [add_options_for_arm_arch_FUNC ""]]
5475 # Return 1 if GCC was configured with --with-mode=
5476 proc check_effective_target_default_mode { } {
5478 return [check_configured_with "with-mode="]
5481 # Return 1 if this is an ARM target where -marm causes ARM to be
5484 proc check_effective_target_arm_arm_ok { } {
5485 return [check_no_compiler_messages arm_arm_ok assembly {
5486 #if !defined (__arm__) || defined (__thumb__) || defined (__thumb2__)
5487 #error !__arm__ || __thumb__ || __thumb2__
5493 # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
5496 proc check_effective_target_arm_thumb1_ok { } {
5497 return [check_no_compiler_messages arm_thumb1_ok assembly {
5498 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5499 #error !__arm__ || !__thumb__ || __thumb2__
5501 int foo (int i) { return i; }
5505 # Return 1 is this is an ARM target where -mthumb causes Thumb-2 to be
5508 proc check_effective_target_arm_thumb2_ok { } {
5509 return [check_no_compiler_messages arm_thumb2_ok assembly {
5510 #if !defined(__thumb2__)
5513 int foo (int i) { return i; }
5517 # Return 1 if this is an ARM target where Thumb-1 is used without options
5518 # added by the test.
5520 proc check_effective_target_arm_thumb1 { } {
5521 return [check_no_compiler_messages arm_thumb1 assembly {
5522 #if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
5523 #error !__arm__ || !__thumb__ || __thumb2__
5529 # Return 1 if this is an ARM target where Thumb-2 is used without options
5530 # added by the test.
5532 proc check_effective_target_arm_thumb2 { } {
5533 return [check_no_compiler_messages arm_thumb2 assembly {
5534 #if !defined(__thumb2__)
5541 # Return 1 if this is an ARM target where conditional execution is available.
5543 proc check_effective_target_arm_cond_exec { } {
5544 return [check_no_compiler_messages arm_cond_exec assembly {
5545 #if defined(__arm__) && defined(__thumb__) && !defined(__thumb2__)
5552 # Return 1 if this is an ARM cortex-M profile cpu
5554 proc check_effective_target_arm_cortex_m { } {
5555 if { ![istarget arm*-*-*] } {
5558 return [check_no_compiler_messages arm_cortex_m assembly {
5559 #if defined(__ARM_ARCH_ISA_ARM)
5560 #error __ARM_ARCH_ISA_ARM is defined
5566 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5567 # used and MOVT/MOVW instructions to be available.
5569 proc check_effective_target_arm_thumb1_movt_ok {} {
5570 if [check_effective_target_arm_thumb1_ok] {
5571 return [check_no_compiler_messages arm_movt object {
5575 asm ("movt r0, #42");
5583 # Return 1 if this is an ARM target where -mthumb causes Thumb-1 to be
5584 # used and CBZ and CBNZ instructions are available.
5586 proc check_effective_target_arm_thumb1_cbz_ok {} {
5587 if [check_effective_target_arm_thumb1_ok] {
5588 return [check_no_compiler_messages arm_cbz object {
5592 asm ("cbz r0, 2f\n2:");
5600 # Return 1 if this is an Arm target which supports the Armv6t2 extensions.
5601 # This can be either in Arm state or in Thumb state.
5603 proc check_effective_target_arm_arch_v6t2_hw {} {
5604 if [check_effective_target_arm_arch_v6t2_ok] {
5605 return [check_runtime arm_arch_v6t2 {
5609 asm ("bfc r0, #1, #2");
5612 } [add_options_for_arm_arch_v6t2 ""]]
5618 # Return 1 if this is an ARM target where ARMv8-M Security Extensions is
5621 proc check_effective_target_arm_cmse_ok {} {
5622 return [check_no_compiler_messages arm_cmse object {
5631 # Return 1 if the target supports executing CMSE instructions, 0
5632 # otherwise. Cache the result.
5634 proc check_effective_target_arm_cmse_hw { } {
5635 return [check_runtime arm_cmse_hw_available {
5639 asm ("ldr\t%0, =0xe000ed44\n" \
5641 "sg" : "=l" (id_pfr1));
5642 /* Exit with code 0 iff security extension is available. */
5643 return !(id_pfr1 & 0xf0);
5648 # Return 1 if the target supports executing MVE instructions, 0
5651 proc check_effective_target_arm_mve_hw {} {
5652 return [check_runtime arm_mve_hw_available {
5658 asm ("sqrshrl %Q1, %R1, #64, %2"
5660 : "0" (a), "r" (b));
5663 } [add_options_for_arm_v8_1m_mve_fp ""]]
5666 # Return 1 if this is an ARM target where ARMv8-M Security Extensions with
5667 # clearing instructions (clrm, vscclrm, vstr/vldr with FPCXT) is available.
5669 proc check_effective_target_arm_cmse_clear_ok {} {
5670 return [check_no_compiler_messages arm_cmse_clear object {
5674 asm ("clrm {r1, r2}");
5679 # Return 1 if this is an ARM target supporting
5680 # -mbranch-protection=standard, 0 otherwise.
5682 proc check_effective_target_mbranch_protection_ok {} {
5684 return [check_no_compiler_messages mbranch_protection_ok object {
5685 int main (void) { return 0; }
5686 } "-mbranch-protection=standard"]
5689 # Return 1 if the target supports executing PACBTI instructions, 0
5692 proc check_effective_target_arm_pacbti_hw {} {
5693 return [check_runtime arm_pacbti_hw_available {
5694 __attribute__ ((naked)) int
5697 asm ("pac r12, lr, sp");
5699 asm ("autg r12, lr, sp");
5702 } "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard -mthumb -mfloat-abi=hard"]
5705 # Return 1 if this compilation turns on string_ops_prefer_neon on.
5707 proc check_effective_target_arm_tune_string_ops_prefer_neon { } {
5708 return [check_no_messages_and_pattern arm_tune_string_ops_prefer_neon "@string_ops_prefer_neon:\t1" assembly {
5709 int foo (void) { return 0; }
5710 } "-O2 -mprint-tune-info" ]
5713 # Return 1 if the target supports executing NEON instructions, 0
5714 # otherwise. Cache the result.
5716 proc check_effective_target_arm_neon_hw { } {
5717 return [check_runtime arm_neon_hw_available {
5721 long long a = 0, b = 1;
5722 asm ("vorr %P0, %P1, %P2"
5724 : "0" (a), "w" (b));
5727 } [add_options_for_arm_neon ""]]
5730 # Return true if this is an AArch64 target that can run SVE code.
5732 proc check_effective_target_aarch64_sve_hw { } {
5733 if { ![istarget aarch64*-*-*] } {
5736 return [check_runtime aarch64_sve_hw_available {
5740 asm volatile ("ptrue p0.b");
5743 } [add_options_for_aarch64_sve ""]]
5746 # Return true if this is an AArch64 target that can run SVE2 code.
5748 proc check_effective_target_aarch64_sve2_hw { } {
5749 if { ![istarget aarch64*-*-*] } {
5752 return [check_runtime aarch64_sve2_hw_available {
5756 asm volatile ("addp z0.b, p0/m, z0.b, z1.b");
5762 # Return true if this is an AArch64 target that can run SVE code and
5763 # if its SVE vectors have exactly BITS bits.
5765 proc aarch64_sve_hw_bits { bits } {
5766 if { ![check_effective_target_aarch64_sve_hw] } {
5769 return [check_runtime aarch64_sve${bits}_hw [subst {
5774 asm volatile ("cntd %0" : "=r" (res));
5775 if (res * 64 != $bits)
5779 }] [add_options_for_aarch64_sve ""]]
5782 # Return true if this is an AArch64 target that can run SVE code and
5783 # if its SVE vectors have exactly 256 bits.
5785 foreach N { 128 256 512 1024 2048 } {
5786 eval [string map [list N $N] {
5787 proc check_effective_target_aarch64_sveN_hw { } {
5788 return [aarch64_sve_hw_bits N]
5793 proc check_effective_target_arm_neonv2_hw { } {
5794 return [check_runtime arm_neon_hwv2_available {
5795 #include "arm_neon.h"
5799 float32x2_t a, b, c;
5800 asm ("vfma.f32 %P0, %P1, %P2"
5802 : "w" (b), "w" (c));
5805 } [add_options_for_arm_neonv2 ""]]
5808 # ID_AA64PFR1_EL1.BT using bits[3:0] == 1 implies BTI implimented.
5809 proc check_effective_target_aarch64_bti_hw { } {
5810 if { ![istarget aarch64*-*-*] } {
5813 return [check_runtime aarch64_bti_hw_available {
5818 asm volatile ("mrs %0, id_aa64pfr1_el1" : "=r" (a));
5819 return !((a & 0xf) == 1);
5824 # Return 1 if the target supports executing the armv8.3-a FJCVTZS
5826 proc check_effective_target_aarch64_fjcvtzs_hw { } {
5827 if { ![istarget aarch64*-*-*] } {
5830 return [check_runtime aarch64_fjcvtzs_hw_available {
5836 asm volatile ("fjcvtzs %w0, %d1"
5839 : /* No clobbers. */);
5842 } "-march=armv8.3-a" ]
5845 # Return 1 if GCC was configured with --enable-standard-branch-protection
5846 proc check_effective_target_default_branch_protection { } {
5847 return [check_configured_with "enable-standard-branch-protection"]
5850 # Return 1 if this is an ARM target supporting -mfloat-abi=softfp.
5852 proc check_effective_target_arm_softfp_ok { } {
5853 return [check_no_compiler_messages arm_softfp_ok object {
5856 int main (void) { return 0; }
5857 } "-mfloat-abi=softfp"]
5860 # Return 1 if this is an ARM target supporting -mfloat-abi=hard.
5862 proc check_effective_target_arm_hard_ok { } {
5863 return [check_no_compiler_messages arm_hard_ok object {
5866 int main (void) { return 0; }
5867 } "-mfloat-abi=hard"]
5870 # Return 1 if this is an ARM target supporting MVE.
5871 proc check_effective_target_arm_mve { } {
5872 if { ![istarget arm*-*-*] } {
5875 return [check_no_compiler_messages arm_mve assembly {
5876 #if !defined (__ARM_FEATURE_MVE)
5882 # Return 1 if the target supports ARMv8.1-M MVE with floating point
5883 # instructions, 0 otherwise. The test is valid for ARM.
5884 # Record the command line options needed.
5886 proc check_effective_target_arm_v8_1m_mve_fp_ok_nocache { } {
5887 global et_arm_v8_1m_mve_fp_flags
5888 set et_arm_v8_1m_mve_fp_flags ""
5890 if { ![istarget arm*-*-*] } {
5894 # Iterate through sets of options to find the compiler flags that
5895 # need to be added to the -march option.
5896 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve.fp" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve.fp"} {
5897 if { [check_no_compiler_messages_nocache \
5898 arm_v8_1m_mve_fp_ok object {
5899 #include <arm_mve.h>
5900 #if !(__ARM_FEATURE_MVE & 2)
5901 #error "__ARM_FEATURE_MVE for floating point not defined"
5903 #if __ARM_BIG_ENDIAN
5904 #error "MVE intrinsics are not supported in Big-Endian mode."
5906 } "$flags -mthumb"] } {
5907 set et_arm_v8_1m_mve_fp_flags "$flags -mthumb --save-temps"
5915 proc check_effective_target_arm_v8_1m_mve_fp_ok { } {
5916 return [check_cached_effective_target arm_v8_1m_mve_fp_ok \
5917 check_effective_target_arm_v8_1m_mve_fp_ok_nocache]
5920 proc add_options_for_arm_v8_1m_mve_fp { flags } {
5921 if { ! [check_effective_target_arm_v8_1m_mve_fp_ok] } {
5924 global et_arm_v8_1m_mve_fp_flags
5925 return "$flags $et_arm_v8_1m_mve_fp_flags"
5928 # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0
5929 # otherwise. The test is valid for AArch64 and ARM. Record the command
5930 # line options needed.
5932 proc check_effective_target_arm_v8_1a_neon_ok_nocache { } {
5933 global et_arm_v8_1a_neon_flags
5934 set et_arm_v8_1a_neon_flags ""
5936 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
5940 # Iterate through sets of options to find the compiler flags that
5941 # need to be added to the -march option. Start with the empty set
5942 # since AArch64 only needs the -march setting.
5943 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
5944 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
5945 foreach arches { "-march=armv8-a+rdma" "-march=armv8.1-a" } {
5946 if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object {
5947 #if !defined (__ARM_FEATURE_QRDMX)
5948 #error "__ARM_FEATURE_QRDMX not defined"
5950 } "$flags $arches"] } {
5951 set et_arm_v8_1a_neon_flags "$flags $arches"
5960 proc check_effective_target_arm_v8_1a_neon_ok { } {
5961 return [check_cached_effective_target arm_v8_1a_neon_ok \
5962 check_effective_target_arm_v8_1a_neon_ok_nocache]
5965 # Return 1 if the target supports ARMv8.2 scalar FP16 arithmetic
5966 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
5967 # Record the command line options needed.
5969 proc check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache { } {
5970 global et_arm_v8_2a_fp16_scalar_flags
5971 set et_arm_v8_2a_fp16_scalar_flags ""
5973 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
5977 # Iterate through sets of options to find the compiler flags that
5978 # need to be added to the -march option.
5979 foreach flags {"" "-mfpu=fp-armv8" "-mfloat-abi=softfp" \
5980 "-mfpu=fp-armv8 -mfloat-abi=softfp"} {
5981 if { [check_no_compiler_messages_nocache \
5982 arm_v8_2a_fp16_scalar_ok object {
5983 #if !defined (__ARM_FEATURE_FP16_SCALAR_ARITHMETIC)
5984 #error "__ARM_FEATURE_FP16_SCALAR_ARITHMETIC not defined"
5986 } "$flags -march=armv8.2-a+fp16"] } {
5987 set et_arm_v8_2a_fp16_scalar_flags "$flags -march=armv8.2-a+fp16"
5995 proc check_effective_target_arm_v8_2a_fp16_scalar_ok { } {
5996 return [check_cached_effective_target arm_v8_2a_fp16_scalar_ok \
5997 check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache]
6000 # Return 1 if the target supports ARMv8.2 Adv.SIMD FP16 arithmetic
6001 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6002 # Record the command line options needed.
6004 proc check_effective_target_arm_v8_2a_fp16_neon_ok_nocache { } {
6005 global et_arm_v8_2a_fp16_neon_flags
6006 set et_arm_v8_2a_fp16_neon_flags ""
6008 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6012 # Iterate through sets of options to find the compiler flags that
6013 # need to be added to the -march option.
6014 foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \
6015 "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
6016 if { [check_no_compiler_messages_nocache \
6017 arm_v8_2a_fp16_neon_ok object {
6018 #if !defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
6019 #error "__ARM_FEATURE_FP16_VECTOR_ARITHMETIC not defined"
6021 } "$flags -march=armv8.2-a+fp16"] } {
6022 set et_arm_v8_2a_fp16_neon_flags "$flags -march=armv8.2-a+fp16"
6030 proc check_effective_target_arm_v8_2a_fp16_neon_ok { } {
6031 return [check_cached_effective_target arm_v8_2a_fp16_neon_ok \
6032 check_effective_target_arm_v8_2a_fp16_neon_ok_nocache]
6035 # Return 1 if the target supports ARMv8.2 Adv.SIMD Dot Product
6036 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6037 # Record the command line options needed.
6039 proc check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache { } {
6040 global et_arm_v8_2a_dotprod_neon_flags
6041 set et_arm_v8_2a_dotprod_neon_flags ""
6043 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6047 # Iterate through sets of options to find the compiler flags that
6048 # need to be added to the -march option.
6049 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6050 if { [check_no_compiler_messages_nocache \
6051 arm_v8_2a_dotprod_neon_ok object {
6053 #if !defined (__ARM_FEATURE_DOTPROD)
6054 #error "__ARM_FEATURE_DOTPROD not defined"
6056 } "$flags -march=armv8.2-a+dotprod"] } {
6057 set et_arm_v8_2a_dotprod_neon_flags "$flags -march=armv8.2-a+dotprod"
6065 # Return 1 if the target supports ARMv8.1-M MVE
6066 # instructions, 0 otherwise. The test is valid for ARM.
6067 # Record the command line options needed.
6069 proc check_effective_target_arm_v8_1m_mve_ok_nocache { } {
6070 global et_arm_v8_1m_mve_flags
6071 set et_arm_v8_1m_mve_flags ""
6073 if { ![istarget arm*-*-*] } {
6077 # Iterate through sets of options to find the compiler flags that
6078 # need to be added to the -march option.
6079 foreach flags {"" "-mfloat-abi=softfp -mfpu=auto -march=armv8.1-m.main+mve" "-mfloat-abi=hard -mfpu=auto -march=armv8.1-m.main+mve"} {
6080 if { [check_no_compiler_messages_nocache \
6081 arm_v8_1m_mve_ok object {
6082 #if !defined (__ARM_FEATURE_MVE)
6083 #error "__ARM_FEATURE_MVE not defined"
6085 #if __ARM_BIG_ENDIAN
6086 #error "MVE intrinsics are not supported in Big-Endian mode."
6088 #include <arm_mve.h>
6089 } "$flags -mthumb"] } {
6090 set et_arm_v8_1m_mve_flags "$flags -mthumb --save-temps"
6098 proc check_effective_target_arm_v8_1m_mve_ok { } {
6099 return [check_cached_effective_target arm_v8_1m_mve_ok \
6100 check_effective_target_arm_v8_1m_mve_ok_nocache]
6103 proc add_options_for_arm_v8_1m_mve { flags } {
6104 if { ! [check_effective_target_arm_v8_1m_mve_ok] } {
6107 global et_arm_v8_1m_mve_flags
6108 return "$flags $et_arm_v8_1m_mve_flags"
6111 proc check_effective_target_arm_v8_2a_dotprod_neon_ok { } {
6112 return [check_cached_effective_target arm_v8_2a_dotprod_neon_ok \
6113 check_effective_target_arm_v8_2a_dotprod_neon_ok_nocache]
6116 proc add_options_for_arm_v8_2a_dotprod_neon { flags } {
6117 if { ! [check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6120 global et_arm_v8_2a_dotprod_neon_flags
6121 return "$flags $et_arm_v8_2a_dotprod_neon_flags"
6124 # Return 1 if the target supports ARMv8.2+i8mm Adv.SIMD Dot Product
6125 # instructions, 0 otherwise. The test is valid for ARM and for AArch64.
6126 # Record the command line options needed.
6128 proc check_effective_target_arm_v8_2a_i8mm_ok_nocache { } {
6129 global et_arm_v8_2a_i8mm_flags
6130 set et_arm_v8_2a_i8mm_flags ""
6132 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6136 # Iterate through sets of options to find the compiler flags that
6137 # need to be added to the -march option.
6138 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6139 if { [check_no_compiler_messages_nocache \
6140 arm_v8_2a_i8mm_ok object {
6141 #include <arm_neon.h>
6142 #if !defined (__ARM_FEATURE_MATMUL_INT8)
6143 #error "__ARM_FEATURE_MATMUL_INT8 not defined"
6145 } "$flags -march=armv8.2-a+i8mm"] } {
6146 set et_arm_v8_2a_i8mm_flags "$flags -march=armv8.2-a+i8mm"
6154 proc check_effective_target_arm_v8_2a_i8mm_ok { } {
6155 return [check_cached_effective_target arm_v8_2a_i8mm_ok \
6156 check_effective_target_arm_v8_2a_i8mm_ok_nocache]
6159 proc add_options_for_arm_v8_2a_i8mm { flags } {
6160 if { ! [check_effective_target_arm_v8_2a_i8mm_ok] } {
6163 global et_arm_v8_2a_i8mm_flags
6164 return "$flags $et_arm_v8_2a_i8mm_flags"
6167 # Return 1 if the target supports FP16 VFMAL and VFMSL
6168 # instructions, 0 otherwise.
6169 # Record the command line options needed.
6171 proc check_effective_target_arm_fp16fml_neon_ok_nocache { } {
6172 global et_arm_fp16fml_neon_flags
6173 set et_arm_fp16fml_neon_flags ""
6175 if { ![istarget arm*-*-*] } {
6179 # Iterate through sets of options to find the compiler flags that
6180 # need to be added to the -march option.
6181 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8"} {
6182 if { [check_no_compiler_messages_nocache \
6183 arm_fp16fml_neon_ok assembly {
6184 #include <arm_neon.h>
6186 foo (float32x2_t r, float16x4_t a, float16x4_t b)
6188 return vfmlal_high_f16 (r, a, b);
6190 } "$flags -march=armv8.2-a+fp16fml"] } {
6191 set et_arm_fp16fml_neon_flags "$flags -march=armv8.2-a+fp16fml"
6199 proc check_effective_target_arm_fp16fml_neon_ok { } {
6200 return [check_cached_effective_target arm_fp16fml_neon_ok \
6201 check_effective_target_arm_fp16fml_neon_ok_nocache]
6204 proc add_options_for_arm_fp16fml_neon { flags } {
6205 if { ! [check_effective_target_arm_fp16fml_neon_ok] } {
6208 global et_arm_fp16fml_neon_flags
6209 return "$flags $et_arm_fp16fml_neon_flags"
6212 # Return 1 if the target supports BFloat16 SIMD instructions, 0 otherwise.
6213 # The test is valid for ARM and for AArch64.
6215 proc check_effective_target_arm_v8_2a_bf16_neon_ok_nocache { } {
6216 global et_arm_v8_2a_bf16_neon_flags
6217 set et_arm_v8_2a_bf16_neon_flags ""
6219 if { ![istarget arm*-*-*] && ![istarget aarch64*-*-*] } {
6223 foreach flags {"" "-mfloat-abi=softfp -mfpu=neon-fp-armv8" "-mfloat-abi=hard -mfpu=neon-fp-armv8" } {
6224 if { [check_no_compiler_messages_nocache arm_v8_2a_bf16_neon_ok object {
6225 #include <arm_neon.h>
6226 #if !defined (__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)
6227 #error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC not defined"
6229 } "$flags -march=armv8.2-a+bf16"] } {
6230 set et_arm_v8_2a_bf16_neon_flags "$flags -march=armv8.2-a+bf16"
6238 proc check_effective_target_arm_v8_2a_bf16_neon_ok { } {
6239 return [check_cached_effective_target arm_v8_2a_bf16_neon_ok \
6240 check_effective_target_arm_v8_2a_bf16_neon_ok_nocache]
6243 proc add_options_for_arm_v8_2a_bf16_neon { flags } {
6244 if { ! [check_effective_target_arm_v8_2a_bf16_neon_ok] } {
6247 global et_arm_v8_2a_bf16_neon_flags
6248 return "$flags $et_arm_v8_2a_bf16_neon_flags"
6251 # A series of routines are created to 1) check if a given architecture is
6252 # effective (check_effective_target_*_ok) and then 2) give the corresponding
6253 # flags that enable the architecture (add_options_for_*).
6254 # The series includes:
6255 # arm_v8m_main_cde: Armv8-m CDE (Custom Datapath Extension).
6256 # arm_v8m_main_cde_fp: Armv8-m CDE with FP registers.
6257 # arm_v8_1m_main_cde_mve: Armv8.1-m CDE with MVE.
6258 # arm_v8_1m_main_cde_mve_fp: Armv8.1-m CDE with MVE with FP support.
6260 # /* { dg-require-effective-target arm_v8m_main_cde_ok } */
6261 # /* { dg-add-options arm_v8m_main_cde } */
6262 # The tests are valid for Arm.
6264 foreach { armfunc armflag armdef arminc } {
6266 "-march=armv8-m.main+cdecp0+cdecp6 -mthumb"
6267 "defined (__ARM_FEATURE_CDE)"
6270 "-march=armv8-m.main+fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6271 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FP)"
6273 arm_v8_1m_main_cde_mve
6274 "-march=armv8.1-m.main+mve+cdecp0+cdecp6 -mthumb -mfpu=auto"
6275 "defined (__ARM_FEATURE_CDE) && defined (__ARM_FEATURE_MVE)"
6276 "#include <arm_mve.h>"
6277 arm_v8_1m_main_cde_mve_fp
6278 "-march=armv8.1-m.main+mve.fp+cdecp0+cdecp6 -mthumb -mfpu=auto"
6279 "defined (__ARM_FEATURE_CDE) || __ARM_FEATURE_MVE == 3"
6280 "#include <arm_mve.h>"
6282 eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef INC $arminc ] {
6283 proc check_effective_target_FUNC_ok_nocache { } {
6284 global et_FUNC_flags
6285 set et_FUNC_flags ""
6287 if { ![istarget arm*-*-*] } {
6291 if { [check_no_compiler_messages_nocache FUNC_ok assembly {
6295 #include <arm_cde.h>
6298 set et_FUNC_flags "FLAG"
6305 proc check_effective_target_FUNC_ok { } {
6306 return [check_cached_effective_target FUNC_ok \
6307 check_effective_target_FUNC_ok_nocache]
6310 proc add_options_for_FUNC { flags } {
6311 if { ! [check_effective_target_FUNC_ok] } {
6314 global et_FUNC_flags
6315 return "$flags $et_FUNC_flags"
6318 proc check_effective_target_FUNC_link { } {
6319 if { ! [check_effective_target_FUNC_ok] } {
6322 return [check_no_compiler_messages FUNC_link executable {
6326 #include <arm_cde.h>
6333 } [add_options_for_FUNC ""]]
6336 proc check_effective_target_FUNC_multilib { } {
6337 if { ! [check_effective_target_FUNC_ok] } {
6340 return [check_runtime FUNC_multilib {
6344 #include <arm_cde.h>
6351 } [add_options_for_FUNC ""]]
6356 # Return 1 if the target supports executing ARMv8 NEON instructions, 0
6359 proc check_effective_target_arm_v8_neon_hw { } {
6360 return [check_runtime arm_v8_neon_hw_available {
6361 #include "arm_neon.h"
6365 float32x2_t a = { 1.0f, 2.0f };
6366 #ifdef __ARM_ARCH_ISA_A64
6367 asm ("frinta %0.2s, %1.2s"
6371 asm ("vrinta.f32 %P0, %P1"
6375 return a[0] == 2.0f;
6377 } [add_options_for_arm_v8_neon ""]]
6380 # Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
6381 # otherwise. The test is valid for AArch64 and ARM.
6383 proc check_effective_target_arm_v8_1a_neon_hw { } {
6384 if { ![check_effective_target_arm_v8_1a_neon_ok] } {
6387 return [check_runtime arm_v8_1a_neon_hw_available {
6391 #ifdef __ARM_ARCH_ISA_A64
6392 __Int32x2_t a = {0, 1};
6393 __Int32x2_t b = {0, 2};
6396 asm ("sqrdmlah %0.2s, %1.2s, %2.2s"
6399 : /* No clobbers. */);
6403 __simd64_int32_t a = {0, 1};
6404 __simd64_int32_t b = {0, 2};
6405 __simd64_int32_t result;
6407 asm ("vqrdmlah.s32 %P0, %P1, %P2"
6410 : /* No clobbers. */);
6415 } [add_options_for_arm_v8_1a_neon ""]]
6418 # Return 1 if the target supports executing floating point instructions from
6419 # ARMv8.2 with the FP16 extension, 0 otherwise. The test is valid for ARM and
6422 proc check_effective_target_arm_v8_2a_fp16_scalar_hw { } {
6423 if { ![check_effective_target_arm_v8_2a_fp16_scalar_ok] } {
6426 return [check_runtime arm_v8_2a_fp16_scalar_hw_available {
6433 #ifdef __ARM_ARCH_ISA_A64
6435 asm ("fabs %h0, %h1"
6438 : /* No clobbers. */);
6442 asm ("vabs.f16 %0, %1"
6445 : /* No clobbers. */);
6449 return (result == 1.0) ? 0 : 1;
6451 } [add_options_for_arm_v8_2a_fp16_scalar ""]]
6454 # Return 1 if the target supports executing Adv.SIMD instructions from ARMv8.2
6455 # with the FP16 extension, 0 otherwise. The test is valid for ARM and for
6458 proc check_effective_target_arm_v8_2a_fp16_neon_hw { } {
6459 if { ![check_effective_target_arm_v8_2a_fp16_neon_ok] } {
6462 return [check_runtime arm_v8_2a_fp16_neon_hw_available {
6466 #ifdef __ARM_ARCH_ISA_A64
6468 __Float16x4_t a = {1.0, -1.0, 1.0, -1.0};
6469 __Float16x4_t result;
6471 asm ("fabs %0.4h, %1.4h"
6474 : /* No clobbers. */);
6478 __simd64_float16_t a = {1.0, -1.0, 1.0, -1.0};
6479 __simd64_float16_t result;
6481 asm ("vabs.f16 %P0, %P1"
6484 : /* No clobbers. */);
6488 return (result[0] == 1.0) ? 0 : 1;
6490 } [add_options_for_arm_v8_2a_fp16_neon ""]]
6493 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6494 # with the Dot Product extension, 0 otherwise. The test is valid for ARM and for
6497 proc check_effective_target_arm_v8_2a_dotprod_neon_hw { } {
6498 if { ![check_effective_target_arm_v8_2a_dotprod_neon_ok] } {
6501 return [check_runtime arm_v8_2a_dotprod_neon_hw_available {
6502 #include "arm_neon.h"
6507 uint32x2_t results = {0,0};
6508 uint8x8_t a = {1,1,1,1,2,2,2,2};
6509 uint8x8_t b = {2,2,2,2,3,3,3,3};
6511 #ifdef __ARM_ARCH_ISA_A64
6512 asm ("udot %0.2s, %1.8b, %2.8b"
6515 : /* No clobbers. */);
6518 asm ("vudot.u8 %P0, %P1, %P2"
6521 : /* No clobbers. */);
6524 return (results[0] == 8 && results[1] == 24) ? 1 : 0;
6526 } [add_options_for_arm_v8_2a_dotprod_neon ""]]
6529 # Return 1 if the target supports executing AdvSIMD instructions from ARMv8.2
6530 # with the i8mm extension, 0 otherwise. The test is valid for ARM and for
6533 proc check_effective_target_arm_v8_2a_i8mm_neon_hw { } {
6534 if { ![check_effective_target_arm_v8_2a_i8mm_ok] } {
6537 return [check_runtime arm_v8_2a_i8mm_neon_hw_available {
6538 #include "arm_neon.h"
6543 uint32x2_t results = {0,0};
6544 uint8x8_t a = {1,1,1,1,2,2,2,2};
6545 int8x8_t b = {2,2,2,2,3,3,3,3};
6547 #ifdef __ARM_ARCH_ISA_A64
6548 asm ("usdot %0.2s, %1.8b, %2.8b"
6551 : /* No clobbers. */);
6554 asm ("vusdot.u8 %P0, %P1, %P2"
6557 : /* No clobbers. */);
6560 return (vget_lane_u32 (results, 0) == 8
6561 && vget_lane_u32 (results, 1) == 24) ? 1 : 0;
6563 } [add_options_for_arm_v8_2a_i8mm ""]]
6566 # Return 1 if this is a ARM target with NEON enabled.
6568 proc check_effective_target_arm_neon { } {
6569 if { [check_effective_target_arm32] } {
6570 return [check_no_compiler_messages arm_neon object {
6571 #ifndef __ARM_NEON__
6582 proc check_effective_target_arm_neonv2 { } {
6583 if { [check_effective_target_arm32] } {
6584 return [check_no_compiler_messages arm_neon object {
6585 #ifndef __ARM_NEON__
6588 #ifndef __ARM_FEATURE_FMA
6600 # Return 1 if this is an ARM target with load acquire and store release
6601 # instructions for 8-, 16- and 32-bit types.
6603 proc check_effective_target_arm_acq_rel { } {
6604 return [check_no_compiler_messages arm_acq_rel object {
6606 load_acquire_store_release (void)
6608 asm ("lda r0, [r1]\n\t"
6614 : : : "r0", "memory");
6619 # Add the options needed for MIPS Paired-Single.
6621 proc add_options_for_mpaired_single { flags } {
6622 if { ! [check_effective_target_mpaired_single "-mpaired-single"] } {
6625 return "$flags -mpaired-single"
6628 # Add the options needed for MIPS SIMD Architecture.
6630 proc add_options_for_mips_msa { flags } {
6631 if { ! [check_effective_target_mips_msa "-mmsa"] } {
6634 return "$flags -mmsa"
6637 # Add the options needed for MIPS Loongson MMI Architecture.
6639 proc add_options_for_mips_loongson_mmi { flags } {
6640 if { ! [check_effective_target_mips_loongson_mmi "-mloongson-mmi"] } {
6643 return "$flags -mloongson-mmi"
6647 # Return 1 if this a Loongson-2E or -2F target using an ABI that supports
6648 # the Loongson vector modes.
6650 proc check_effective_target_mips_loongson_mmi { args } {
6651 return [check_no_compiler_messages loongson assembly {
6652 #if !defined(__mips_loongson_mmi)
6653 #error !__mips_loongson_mmi
6655 #if !defined(__mips_loongson_vector_rev)
6656 #error !__mips_loongson_vector_rev
6661 # Return 1 if this is a MIPS target that supports the legacy NAN.
6663 proc check_effective_target_mips_nanlegacy { } {
6664 return [check_no_compiler_messages nanlegacy assembly {
6666 int main () { return 0; }
6670 # Return 1 if an MSA program can be compiled to object
6672 proc check_effective_target_mips_msa { args } {
6673 if ![check_effective_target_nomips16] {
6676 return [check_no_compiler_messages msa object {
6677 #if !defined(__mips_msa)
6678 #error "MSA NOT AVAIL"
6680 #if !(((__mips == 64) || (__mips == 32)) && (__mips_isa_rev >= 2))
6681 #error "MSA NOT AVAIL FOR ISA REV < 2"
6683 #if !defined(__mips_hard_float)
6684 #error "MSA HARD_FLOAT REQUIRED"
6686 #if __mips_fpr != 64
6687 #error "MSA 64-bit FPR REQUIRED"
6693 v8i16 v = __builtin_msa_ldi_h (1);
6701 # Return 1 if this is an ARM target that adheres to the ABI for the ARM
6704 proc check_effective_target_arm_eabi { } {
6705 return [check_no_compiler_messages arm_eabi object {
6706 #ifndef __ARM_EABI__
6714 # Return 1 if this is an ARM target that adheres to the hard-float variant of
6715 # the ABI for the ARM Architecture (e.g. -mfloat-abi=hard).
6717 proc check_effective_target_arm_hf_eabi { } {
6718 return [check_no_compiler_messages arm_hf_eabi object {
6719 #if !defined(__ARM_EABI__) || !defined(__ARM_PCS_VFP)
6720 #error not hard-float EABI
6727 # Return 1 if this is an ARM target uses emulated floating point
6730 proc check_effective_target_arm_softfloat { } {
6731 return [check_no_compiler_messages arm_softfloat object {
6732 #if !defined(__SOFTFP__)
6733 #error not soft-float EABI
6740 # Return 1 if this is an ARM target supporting -mcpu=iwmmxt.
6741 # Some multilibs may be incompatible with this option.
6743 proc check_effective_target_arm_iwmmxt_ok { } {
6744 if { [check_effective_target_arm32] } {
6745 return [check_no_compiler_messages arm_iwmmxt_ok object {
6753 # Return true if LDRD/STRD instructions are prefered over LDM/STM instructions
6754 # for an ARM target.
6755 proc check_effective_target_arm_prefer_ldrd_strd { } {
6756 if { ![check_effective_target_arm32] } {
6760 return [check_no_messages_and_pattern arm_prefer_ldrd_strd "strd\tr" assembly {
6761 void foo (void) { __asm__ ("" ::: "r4", "r5"); }
6765 # Return true if LDRD/STRD instructions are available on this target.
6766 proc check_effective_target_arm_ldrd_strd_ok { } {
6767 if { ![check_effective_target_arm32] } {
6771 return [check_no_compiler_messages arm_ldrd_strd_ok object {
6774 __UINT64_TYPE__ a = 1, b = 10;
6775 __UINT64_TYPE__ *c = &b;
6776 // `a` will be in a valid register since it's a DImode quantity.
6785 #
Return 1 if this is a PowerPC target supporting
-meabi.
6787 proc check_effective_target_powerpc_eabi_ok
{ } {
6788 if { [istarget powerpc
*-*-*] } {
6789 return [check_no_compiler_messages powerpc_eabi_ok object
{
6797 #
Return 1 if this is a PowerPC target with floating
-point registers.
6799 proc check_effective_target_powerpc_fprs
{ } {
6800 if { [istarget powerpc
*-*-*]
6801 ||
[istarget rs6000
-*-*] } {
6802 return [check_no_compiler_messages powerpc_fprs object
{
6814 #
Return 1 if this is a PowerPC target with hardware double
-precision
6817 proc check_effective_target_powerpc_hard_double
{ } {
6818 if { [istarget powerpc
*-*-*]
6819 ||
[istarget rs6000
-*-*] } {
6820 return [check_no_compiler_messages powerpc_hard_double object
{
6832 #
Return 1 if this is a PowerPC target with hardware floating point
sqrt.
6834 proc check_effective_target_powerpc_sqrt
{ } {
6835 # We need to be PowerPC
, and we need to have hardware fp enabled.
6836 if {![check_effective_target_powerpc_fprs
]} {
6840 return [check_no_compiler_messages powerpc_sqrt object
{
6844 #error _ARCH_PPCSQ is not defined
6850 #
Return 1 if this is a PowerPC target supporting
-maltivec.
6852 proc check_effective_target_powerpc_altivec_ok
{ } {
6853 # Not PowerPC
, then not ok
6854 if { !([istarget powerpc
*-*-*] ||
[istarget rs6000
-*-*]) } { return 0 }
6856 # Paired Single
, then not ok
6857 if { [istarget powerpc
-*-linux
*paired
*] } { return 0 }
6859 # AltiVec is not supported
on AIX before
5.3.
6860 if { [istarget powerpc
*-*-aix4
*]
6861 ||
[istarget powerpc
*-*-aix5.1
*]
6862 ||
[istarget powerpc
*-*-aix5.2
*] } { return 0 }
6864 #
Return true iff compiling with
-maltivec does not error.
6865 return [check_no_compiler_messages powerpc_altivec_ok object
{
6870 #
Return 1 if this is a PowerPC target supporting
-mpower8
-vector
6872 proc check_effective_target_powerpc_p8vector_ok
{ } {
6873 if { ([istarget powerpc
*-*-*]
6874 && ![istarget powerpc
-*-linux
*paired
*])
6875 ||
[istarget rs6000
-*-*] } {
6876 # AltiVec is not supported
on AIX before
5.3.
6877 if { [istarget powerpc
*-*-aix4
*]
6878 ||
[istarget powerpc
*-*-aix5.1
*]
6879 ||
[istarget powerpc
*-*-aix5.2
*] } {
6882 # Darwin doesn
't run on power8, so far.
6883 if { [istarget *-*-darwin*] } {
6886 return [check_no_compiler_messages powerpc_p8vector_ok object {
6888 asm volatile ("xxlorc 0,0,0");
6891 } "-mpower8-vector"]
6897 # Return 1 if this is a PowerPC target supporting -mpower9-vector
6899 proc check_effective_target_powerpc_p9vector_ok { } {
6900 if { ([istarget powerpc*-*-*]
6901 && ![istarget powerpc-*-linux*paired*])
6902 || [istarget rs6000-*-*] } {
6903 # AltiVec is not supported on AIX before 5.3.
6904 if { [istarget powerpc*-*-aix4*]
6905 || [istarget powerpc*-*-aix5.1*]
6906 || [istarget powerpc*-*-aix5.2*] } {
6909 # Darwin doesn't run
on power9
, so far.
6910 if { [istarget
*-*-darwin
*] } {
6913 return [check_no_compiler_messages powerpc_p9vector_ok object
{
6916 vector double v
= (vector double
) { 0.0, 0.0 };
6917 asm
("xsxexpdp %0,%1" : "+r" (e) : "wa" (v));
6920 } "-mpower9-vector"]
6926 #
Return 1 if this is a PowerPC target supporting
-mmodulo
6928 proc check_effective_target_powerpc_p9modulo_ok
{ } {
6929 if { ([istarget powerpc
*-*-*]
6930 && ![istarget powerpc
-*-linux
*paired
*])
6931 ||
[istarget rs6000
-*-*] } {
6932 # AltiVec is not supported
on AIX before
5.3.
6933 if { [istarget powerpc
*-*-aix4
*]
6934 ||
[istarget powerpc
*-*-aix5.1
*]
6935 ||
[istarget powerpc
*-*-aix5.2
*] } {
6938 return [check_no_compiler_messages powerpc_p9modulo_ok object
{
6940 int i
= 5, j
= 3, r
= -1;
6941 asm
("modsw %0,%1,%2" : "+r" (r) : "r" (i), "r" (j));
6950 #
return 1 if our compiler returns the ARCH_PWR defines with the options
6951 # as provided by the test.
6952 proc check_effective_target_has_arch_pwr5
{ } {
6953 return [check_no_compiler_messages_nocache arch_pwr5 assembly
{
6957 #error does not have power5 support.
6959 /* "has power5 support" */
6962 } [current_compiler_flags
]]
6965 proc check_effective_target_has_arch_pwr6
{ } {
6966 return [check_no_compiler_messages_nocache arch_pwr6 assembly
{
6970 #error does not have power6 support.
6972 /* "has power6 support" */
6975 } [current_compiler_flags
]]
6978 proc check_effective_target_has_arch_pwr7
{ } {
6979 return [check_no_compiler_messages_nocache arch_pwr7 assembly
{
6983 #error does not have power7 support.
6985 /* "has power7 support" */
6988 } [current_compiler_flags
]]
6991 proc check_effective_target_has_arch_pwr8
{ } {
6992 return [check_no_compiler_messages_nocache arch_pwr8 assembly
{
6996 #error does not have power8 support.
6998 /* "has power8 support" */
7001 } [current_compiler_flags
]]
7004 proc check_effective_target_has_arch_pwr9
{ } {
7005 return [check_no_compiler_messages_nocache arch_pwr9 assembly
{
7009 #error does not have power9 support.
7011 /* "has power9 support" */
7014 } [current_compiler_flags
]]
7017 proc check_effective_target_has_arch_pwr10
{ } {
7018 return [check_no_compiler_messages_nocache arch_pwr10 assembly
{
7022 #error does not have power10 support.
7024 /* "has power10 support" */
7027 } [current_compiler_flags
]]
7030 proc check_effective_target_has_arch_ppc64
{ } {
7031 return [check_no_compiler_messages_nocache arch_ppc64 assembly
{
7035 #error does not have ppc64 support.
7037 /* "has ppc64 support" */
7040 } [current_compiler_flags
]]
7043 #
Return 1 if this is a PowerPC target supporting
-mcpu
=power10.
7044 #
Limit this to
64-bit linux systems
for now until other targets support
7047 proc check_effective_target_power10_ok
{ } {
7048 if { ([istarget powerpc64
*-*-linux
*]) } {
7049 return [check_no_compiler_messages power10_ok object
{
7052 asm
("pli %0,%1" : "=r" (e) : "n" (0x12345));
7061 #
Return 1 if this is a PowerPC target supporting
-mfloat128 via either
7062 # software emulation
on power7
/power8 systems or hardware support
on power9.
7064 proc check_effective_target_powerpc_float128_sw_ok
{ } {
7065 if { ([istarget powerpc
*-*-*]
7066 && ![istarget powerpc
-*-linux
*paired
*])
7067 ||
[istarget rs6000
-*-*] } {
7068 # AltiVec is not supported
on AIX before
5.3.
7069 if { [istarget powerpc
*-*-aix4
*]
7070 ||
[istarget powerpc
*-*-aix5.1
*]
7071 ||
[istarget powerpc
*-*-aix5.2
*] } {
7074 # Darwin doesn
't have VSX, so no soft support for float128.
7075 if { [istarget *-*-darwin*] } {
7078 return [check_no_compiler_messages powerpc_float128_sw_ok object {
7079 volatile __float128 x = 1.0q;
7080 volatile __float128 y = 2.0q;
7082 __float128 z = x + y;
7085 } "-mfloat128 -mvsx"]
7091 # Return 1 if this is a PowerPC target supporting -mfloat128 via hardware
7092 # support on power9.
7094 proc check_effective_target_powerpc_float128_hw_ok { } {
7095 if { ([istarget powerpc*-*-*]
7096 && ![istarget powerpc-*-linux*paired*])
7097 || [istarget rs6000-*-*] } {
7098 # AltiVec is not supported on AIX before 5.3.
7099 if { [istarget powerpc*-*-aix4*]
7100 || [istarget powerpc*-*-aix5.1*]
7101 || [istarget powerpc*-*-aix5.2*] } {
7104 # Darwin doesn't run
on any machine with float128 h
/w so far.
7105 if { [istarget
*-*-darwin
*] } {
7108 return [check_no_compiler_messages powerpc_float128_hw_ok object
{
7109 volatile __float128 x
= 1.0q
;
7110 volatile __float128 y
= 2.0q
;
7113 __asm__
("xsaddqp %0,%1,%2" : "=v" (z) : "v" (x), "v" (y));
7116 } "-mfloat128-hardware"]
7122 #
Return 1 if current options
define float128
, 0 otherwise.
7124 proc check_effective_target_ppc_float128
{ } {
7125 return [check_no_compiler_messages_nocache ppc_float128 object
{
7128 #ifndef __FLOAT128__
7135 #
Return 1 if current options generate float128 insns
, 0 otherwise.
7137 proc check_effective_target_ppc_float128_insns
{ } {
7138 return [check_no_compiler_messages_nocache ppc_float128 object
{
7141 #ifndef __FLOAT128_HARDWARE__
7148 #
Return 1 if current options generate VSX instructions
, 0 otherwise.
7150 proc check_effective_target_powerpc_vsx
{ } {
7151 return [check_no_compiler_messages_nocache powerpc_vsx object
{
7161 #
Return 1 if this is a PowerPC target supporting
-mvsx
7163 proc check_effective_target_powerpc_vsx_ok
{ } {
7164 if { ([istarget powerpc
*-*-*]
7165 && ![istarget powerpc
-*-linux
*paired
*])
7166 ||
[istarget rs6000
-*-*] } {
7167 # VSX is not supported
on AIX before
7.1.
7168 if { [istarget powerpc
*-*-aix4
*]
7169 ||
[istarget powerpc
*-*-aix5
*]
7170 ||
[istarget powerpc
*-*-aix6
*] } {
7173 # Darwin doesn
't have VSX, even if it's used with an assembler
7174 # which recognises the insns.
7175 if { [istarget
*-*-darwin
*] } {
7178 return [check_no_compiler_messages powerpc_vsx_ok object
{
7180 asm volatile
("xxlor 0,0,0");
7189 #
Return 1 if this is a PowerPC target supporting
-mhtm
7191 proc check_effective_target_powerpc_htm_ok
{ } {
7192 if { ([istarget powerpc
*-*-*]
7193 && ![istarget powerpc
-*-linux
*paired
*])
7194 ||
[istarget rs6000
-*-*] } {
7195 # HTM is not supported
on AIX yet.
7196 if { [istarget powerpc
*-*-aix
*] } {
7199 return [check_no_compiler_messages powerpc_htm_ok object
{
7201 asm volatile
("tbegin. 0");
7210 #
Return 1 if the target supports executing HTM hardware instructions
,
7211 #
0 otherwise.
Cache the result.
7213 proc check_htm_hw_available
{ } {
7214 return [check_cached_effective_target htm_hw_available
{
7215 #
For now
, disable
on Darwin
7216 if { [istarget powerpc
-*-eabi
] ||
[istarget powerpc
*-*-eabispe
] ||
[istarget
*-*-darwin
*]} {
7219 check_runtime_nocache htm_hw_available
{
7229 #
Return 1 if this is a PowerPC target supporting
-mcpu
=cell.
7231 proc check_effective_target_powerpc_ppu_ok
{ } {
7232 if [check_effective_target_powerpc_altivec_ok
] {
7233 return [check_no_compiler_messages cell_asm_available object
{
7236 asm volatile
("lvlx v0,v0,v0");
7238 asm volatile
("lvlx 0,0,0");
7248 #
Return 1 if this is a PowerPC target that supports SPU.
7250 proc check_effective_target_powerpc_spu
{ } {
7251 if { [istarget powerpc
*-*-linux
*] } {
7252 return [check_effective_target_powerpc_altivec_ok
]
7258 #
Return 1 if this is a PowerPC SPE target. The check includes options
7259 # specified by dg
-options
for this test
, so don
't cache the result.
7261 proc check_effective_target_powerpc_spe_nocache { } {
7262 if { [istarget powerpc*-*-*] } {
7263 return [check_no_compiler_messages_nocache powerpc_spe object {
7269 } [current_compiler_flags]]
7275 # Return 1 if this is a PowerPC target with SPE enabled.
7277 proc check_effective_target_powerpc_spe { } {
7278 if { [istarget powerpc*-*-*] } {
7279 return [check_no_compiler_messages powerpc_spe object {
7291 # Return 1 if this is a PowerPC target with Altivec enabled.
7293 proc check_effective_target_powerpc_altivec { } {
7294 if { [istarget powerpc*-*-*] } {
7295 return [check_no_compiler_messages powerpc_altivec object {
7307 # Return 1 if this is a PowerPC 405 target. The check includes options
7308 # specified by dg-options for this test, so don't
cache the result.
7310 proc check_effective_target_powerpc_405_nocache
{ } {
7311 if { [istarget powerpc
*-*-*] ||
[istarget rs6000
-*-*] } {
7312 return [check_no_compiler_messages_nocache powerpc_405 object
{
7318 } [current_compiler_flags
]]
7324 #
Return 1 if this is a PowerPC target using the ELFv2 ABI.
7326 proc check_effective_target_powerpc_elfv2
{ } {
7327 if { [istarget powerpc
*-*-*] } {
7328 return [check_no_compiler_messages powerpc_elfv2 object
{
7330 #error not ELF v2 ABI
7340 #
Return 1 if this is a PowerPC target supporting
-mrop
-protect
7342 proc check_effective_target_rop_ok
{ } {
7343 return [check_effective_target_power10_ok
] && [check_effective_target_powerpc_elfv2
]
7346 # The VxWorks SPARC simulator accepts only EM_SPARC executables and
7347 # chokes
on EM_SPARC32PLUS or EM_SPARCV9 executables.
Return 1 if the
7348 # test environment appears to run executables
on such a simulator.
7350 proc check_effective_target_ultrasparc_hw
{ } {
7351 return [check_runtime ultrasparc_hw
{
7352 int main
() { return 0; }
7353 } "-mcpu=ultrasparc"]
7356 #
Return 1 if the test environment supports executing UltraSPARC VIS2
7357 # instructions. We check this by attempting
: "bmask %g0, %g0, %g0"
7359 proc check_effective_target_ultrasparc_vis2_hw
{ } {
7360 return [check_runtime ultrasparc_vis2_hw
{
7361 int main
() { __asm__
(".word 0x81b00320"); return 0; }
7362 } "-mcpu=ultrasparc3"]
7365 #
Return 1 if the test environment supports executing UltraSPARC VIS3
7366 # instructions. We check this by attempting
: "addxc %g0, %g0, %g0"
7368 proc check_effective_target_ultrasparc_vis3_hw
{ } {
7369 return [check_runtime ultrasparc_vis3_hw
{
7370 int main
() { __asm__
(".word 0x81b00220"); return 0; }
7374 #
Return 1 if this is a SPARC
-V9 target.
7376 proc check_effective_target_sparc_v9
{ } {
7377 if { [istarget sparc
*-*-*] } {
7378 return [check_no_compiler_messages sparc_v9 object
{
7380 asm volatile
("return %i7+8");
7389 #
Return 1 if this is a SPARC target with VIS enabled.
7391 proc check_effective_target_sparc_vis
{ } {
7392 if { [istarget sparc
*-*-*] } {
7393 return [check_no_compiler_messages sparc_vis object
{
7405 #
Return 1 if the target supports hardware vector shift operation.
7407 proc check_effective_target_vect_shift
{ } {
7408 return [check_cached_effective_target_indexed vect_shift
{
7409 expr
{([istarget powerpc
*-*-*]
7410 && ![istarget powerpc
-*-linux
*paired
*])
7411 ||
[istarget ia64
-*-*]
7412 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7413 ||
[istarget aarch64
*-*-*]
7414 ||
[is
-effective
-target arm_neon
]
7415 ||
([istarget mips
*-*-*]
7416 && ([et
-is
-effective
-target mips_msa
]
7417 ||
[et
-is
-effective
-target mips_loongson_mmi
]))
7418 ||
([istarget s390
*-*-*]
7419 && [check_effective_target_s390_vx
])
7420 ||
[istarget amdgcn
-*-*]
7421 ||
([istarget riscv
*-*-*]
7422 && [check_effective_target_riscv_v
]) }}]
7425 #
Return 1 if the target supports hardware vector shift by register operation.
7427 proc check_effective_target_vect_var_shift
{ } {
7428 return [check_cached_effective_target_indexed vect_var_shift
{
7429 expr
{(([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7430 && [check_avx2_available
])
7431 ||
[istarget aarch64
*-*-*]
7432 ||
([istarget riscv
*-*-*]
7433 && [check_effective_target_riscv_v
])
7437 proc check_effective_target_whole_vector_shift
{ } {
7438 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7439 ||
[istarget ia64
-*-*]
7440 ||
[istarget aarch64
*-*-*]
7441 ||
[istarget powerpc64
*-*-*]
7442 ||
([is
-effective
-target arm_neon
]
7443 && [check_effective_target_arm_little_endian
])
7444 ||
([istarget mips
*-*-*]
7445 && [et
-is
-effective
-target mips_loongson_mmi
])
7446 ||
([istarget s390
*-*-*]
7447 && [check_effective_target_s390_vx
])
7448 ||
[istarget amdgcn
-*-*]
7449 ||
([istarget riscv
*-*-*]
7450 && [check_effective_target_riscv_v
]) } {
7456 verbose
"check_effective_target_vect_long: returning $answer" 2
7460 #
Return 1 if the target supports vector bswap operations.
7462 proc check_effective_target_vect_bswap
{ } {
7463 return [check_cached_effective_target_indexed vect_bswap
{
7464 expr
{ ([istarget aarch64
*-*-*]
7465 ||
[is
-effective
-target arm_neon
]
7466 ||
[istarget amdgcn
-*-*])
7467 ||
([istarget s390
*-*-*]
7468 && [check_effective_target_s390_vx
]) }}]
7471 #
Return 1 if the target supports comparison of
bool vectors
for at
7472 # least one vector length.
7474 proc check_effective_target_vect_bool_cmp
{ } {
7475 return [check_cached_effective_target_indexed vect_bool_cmp
{
7476 expr
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7477 ||
[istarget aarch64
*-*-*]
7478 ||
[is
-effective
-target arm_neon
]
7479 ||
([istarget riscv
*-*-*]
7480 && [check_effective_target_riscv_v
]) }}]
7483 #
Return 1 if the target supports addition of char vectors
for at least
7484 # one vector length.
7486 proc check_effective_target_vect_char_add
{ } {
7487 return [check_cached_effective_target_indexed vect_char_add
{
7489 [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7490 ||
([istarget powerpc
*-*-*]
7491 && ![istarget powerpc
-*-linux
*paired
*])
7492 ||
[istarget amdgcn
-*-*]
7493 ||
[istarget ia64
-*-*]
7494 ||
[istarget aarch64
*-*-*]
7495 ||
[is
-effective
-target arm_neon
]
7496 ||
([istarget mips
*-*-*]
7497 && ([et
-is
-effective
-target mips_loongson_mmi
]
7498 ||
[et
-is
-effective
-target mips_msa
]))
7499 ||
([istarget s390
*-*-*]
7500 && [check_effective_target_s390_vx
])
7501 ||
([istarget riscv
*-*-*]
7502 && [check_effective_target_riscv_v
])
7506 #
Return 1 if the target supports hardware vector shift operation
for char.
7508 proc check_effective_target_vect_shift_char
{ } {
7509 return [check_cached_effective_target_indexed vect_shift_char
{
7510 expr
{ ([istarget powerpc
*-*-*]
7511 && ![istarget powerpc
-*-linux
*paired
*])
7512 ||
[is
-effective
-target arm_neon
]
7513 ||
([istarget mips
*-*-*]
7514 && [et
-is
-effective
-target mips_msa
])
7515 ||
([istarget s390
*-*-*]
7516 && [check_effective_target_s390_vx
])
7517 ||
[istarget amdgcn
-*-*]
7518 ||
([istarget riscv
*-*-*]
7519 && [check_effective_target_riscv_v
]) }}]
7522 #
Return 1 if the target supports hardware vectors of long
, 0 otherwise.
7524 # This can change
for different subtargets so
do not
cache the result.
7526 proc check_effective_target_vect_long
{ } {
7527 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7528 ||
(([istarget powerpc
*-*-*]
7529 && ![istarget powerpc
-*-linux
*paired
*])
7530 && [check_effective_target_ilp32
])
7531 ||
[is
-effective
-target arm_neon
]
7532 ||
([istarget sparc
*-*-*] && [check_effective_target_ilp32
])
7533 ||
[istarget aarch64
*-*-*]
7534 ||
([istarget mips
*-*-*]
7535 && [et
-is
-effective
-target mips_msa
])
7536 ||
([istarget s390
*-*-*]
7537 && [check_effective_target_s390_vx
])
7538 ||
[istarget amdgcn
-*-*]
7539 ||
([istarget riscv
*-*-*]
7540 && [check_effective_target_riscv_v
]) } {
7546 verbose
"check_effective_target_vect_long: returning $answer" 2
7550 #
Return 1 if the target supports hardware vectors of float when
7551 #
-funsafe
-math
-optimizations is enabled
, 0 otherwise.
7553 # This won
't change for different subtargets so cache the result.
7555 proc check_effective_target_vect_float { } {
7556 return [check_cached_effective_target_indexed vect_float {
7557 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7558 || [istarget powerpc*-*-*]
7559 || [istarget mips-sde-elf]
7560 || [istarget mipsisa64*-*-*]
7561 || [istarget ia64-*-*]
7562 || [istarget aarch64*-*-*]
7563 || ([istarget mips*-*-*]
7564 && [et-is-effective-target mips_msa])
7565 || [is-effective-target arm_neon]
7566 || ([istarget s390*-*-*]
7567 && [check_effective_target_s390_vxe])
7568 || [istarget amdgcn-*-*]
7569 || ([istarget riscv*-*-*]
7570 && [check_effective_target_riscv_v]) }}]
7573 # Return 1 if the target supports hardware vectors of float without
7574 # -funsafe-math-optimizations being enabled, 0 otherwise.
7576 proc check_effective_target_vect_float_strict { } {
7577 return [expr { [check_effective_target_vect_float]
7578 && ![istarget arm*-*-*] }]
7581 # Return 1 if the target supports hardware vectors of double, 0 otherwise.
7583 # This won't change
for different subtargets so
cache the result.
7585 proc check_effective_target_vect_double
{ } {
7586 return [check_cached_effective_target_indexed vect_double
{
7587 expr
{ (([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7588 && [check_no_compiler_messages vect_double assembly
{
7589 #ifdef __tune_atom__
7590 # error No double vectorizer support.
7593 ||
[istarget aarch64
*-*-*]
7594 ||
([istarget powerpc
*-*-*] && [check_vsx_hw_available
])
7595 ||
([istarget mips
*-*-*]
7596 && [et
-is
-effective
-target mips_msa
])
7597 ||
([istarget s390
*-*-*]
7598 && [check_effective_target_s390_vx
])
7599 ||
[istarget amdgcn
-*-*]
7600 ||
([istarget riscv
*-*-*]
7601 && [check_effective_target_riscv_v
])} }]
7604 #
Return 1 if the target supports conditional addition
, subtraction
,
7605 # multiplication
, division
, minimum and maximum
on vectors of double
,
7606 # via the cond_ optabs.
Return 0 otherwise.
7608 proc check_effective_target_vect_double_cond_arith
{ } {
7609 return [expr
{ [check_effective_target_aarch64_sve
]
7610 ||
[check_effective_target_riscv_v
] }]
7613 #
Return 1 if the target supports hardware vectors of long long
, 0 otherwise.
7615 # This won
't change for different subtargets so cache the result.
7617 proc check_effective_target_vect_long_long { } {
7618 return [check_cached_effective_target_indexed vect_long_long {
7619 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7620 || ([istarget mips*-*-*]
7621 && [et-is-effective-target mips_msa])
7622 || ([istarget s390*-*-*]
7623 && [check_effective_target_s390_vx])
7624 || ([istarget powerpc*-*-*]
7625 && ![istarget powerpc-*-linux*paired*]
7626 && [check_effective_target_has_arch_pwr8])
7627 || [istarget aarch64*-*-*]
7628 || ([istarget riscv*-*-*]
7629 && [check_effective_target_riscv_v])}}]
7633 # Return 1 if the target plus current options does not support a vector
7634 # max instruction on "int", 0 otherwise.
7636 # This won't change
for different subtargets so
cache the result.
7638 proc check_effective_target_vect_no_int_min_max
{ } {
7639 return [check_cached_effective_target_indexed vect_no_int_min_max
{
7640 expr
{ [istarget sparc
*-*-*]
7641 ||
[istarget alpha
*-*-*]
7642 ||
([istarget mips
*-*-*]
7643 && [et
-is
-effective
-target mips_loongson_mmi
]) }}]
7646 #
Return 1 if the target plus current options does not support a vector
7647 # add instruction
on "int", 0 otherwise.
7649 # This won
't change for different subtargets so cache the result.
7651 proc check_effective_target_vect_no_int_add { } {
7652 # Alpha only supports vector add on V8QI and V4HI.
7653 return [check_cached_effective_target_indexed vect_no_int_add {
7654 expr { [istarget alpha*-*-*] }}]
7657 # Return 1 if the target plus current options does not support vector
7658 # bitwise instructions, 0 otherwise.
7660 # This won't change
for different subtargets so
cache the result.
7662 proc check_effective_target_vect_no_bitwise
{ } {
7663 return [check_cached_effective_target_indexed vect_no_bitwise
{ return 0 }]
7666 #
Return 1 if the target plus current options supports vector permutation
,
7669 # This won
't change for different subtargets so cache the result.
7671 proc check_effective_target_vect_perm { } {
7672 return [check_cached_effective_target_indexed vect_perm {
7673 expr { [is-effective-target arm_neon]
7674 || [istarget aarch64*-*-*]
7675 || [istarget powerpc*-*-*]
7676 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7677 || ([istarget mips*-*-*]
7678 && ([et-is-effective-target mpaired_single]
7679 || [et-is-effective-target mips_msa]))
7680 || ([istarget s390*-*-*]
7681 && [check_effective_target_s390_vx])
7682 || [istarget amdgcn-*-*]
7683 || ([istarget riscv*-*-*]
7684 && [check_effective_target_riscv_v]) }}]
7687 # Return 1 if, for some VF:
7689 # - the target's default vector size is VF
* ELEMENT_BITS bits
7691 #
- it is possible to implement the equivalent of
:
7693 #
int<ELEMENT_BITS
>_t s1
[COUNT][COUNT * VF
], s2
[COUNT * VF
];
7694 #
for (int i
= 0; i
< COUNT; ++i
)
7695 #
for (int j
= 0; j
< COUNT * VF
; ++j
)
7696 # s1
[i
][j
] = s2
[j
- j
% COUNT + i
]
7698 # using only a single
2-vector permute
for each vector in s1.
7700 # E.g.
for COUNT == 3 and vector length
4, the two arrays would be
:
7702 # s2 | a0 a1 a2 a3 | b0 b1 b2 b3 | c0 c1 c2 c3
7703 #
------+-------------+-------------+------------
7704 # s1
[0] | a0 a0 a0 a3 | a3 a3 b2 b2 | b2 c1 c1 c1
7705 # s1
[1] | a1 a1 a1 b0 | b0 b0 b3 b3 | b3 c2 c2 c2
7706 # s1
[2] | a2 a2 a2 b1 | b1 b1 c0 c0 | c0 c3 c3 c3
7708 # Each s1 permute requires only two of a
, b and c.
7710 # The distance between the start of vector n in s1
[0] and the start
7711 # of vector n in s2 is
:
7713 # A
= (n
* VF
) % COUNT
7715 # The corresponding value
for the end of vector n is
:
7717 # B
= (n
* VF
+ VF
- 1) % COUNT
7719 # Subtracting i from each value gives the corresponding difference
7720 #
for s1
[i
]. The condition being tested by this function is false
7721 # iff A
- i
> 0 and B
- i
< 0 for some i and n
, such that the first
7722 # element
for s1
[i
] comes from vector n
- 1 of s2 and the last element
7723 # comes from vector n
+ 1 of s2. The condition is therefore true iff
7724 # A
<= B
for all n. This is turn means the condition is true iff
:
7726 #
(n
* VF
) % COUNT + (VF
- 1) % COUNT < COUNT
7728 #
for all n.
COUNT - (n
* VF
) % COUNT is bounded by gcd
(VF
, COUNT),
7729 # and will be that value
for at least one n in
[0, COUNT), so we want
:
7731 #
(VF
- 1) % COUNT < gcd
(VF
, COUNT)
7733 proc vect_perm_supported
{ count element_bits
} {
7734 set vector_bits
[lindex
[available_vector_sizes
] 0]
7735 # The number of vectors has to be a power of
2 when permuting
7736 #
variable-length vectors.
7737 if { $vector_bits
<= 0 && ($
count & -$
count) != $
count } {
7740 set vf
[expr
{ $vector_bits
/ $element_bits
}]
7742 # Compute gcd
(VF
, COUNT).
7745 while { $temp1
> 0 } {
7746 set temp2
[expr
{ $gcd
% $temp1
}]
7750 return [expr
{ ($vf
- 1) % $
count < $gcd
}]
7753 #
Return 1 if the target supports SLP permutation of
3 vectors when each
7754 # element has
32 bits.
7756 proc check_effective_target_vect_perm3_int
{ } {
7757 return [expr
{ [check_effective_target_vect_perm
]
7758 && [vect_perm_supported
3 32] }]
7761 #
Return 1 if the target plus current options supports vector permutation
7762 #
on byte
-sized elements
, 0 otherwise.
7764 # This won
't change for different subtargets so cache the result.
7766 proc check_effective_target_vect_perm_byte { } {
7767 return [check_cached_effective_target_indexed vect_perm_byte {
7768 expr { ([is-effective-target arm_neon]
7769 && [is-effective-target arm_little_endian])
7770 || ([istarget aarch64*-*-*]
7771 && [is-effective-target aarch64_little_endian])
7772 || [istarget powerpc*-*-*]
7773 || ([istarget mips-*.*]
7774 && [et-is-effective-target mips_msa])
7775 || ([istarget s390*-*-*]
7776 && [check_effective_target_s390_vx])
7777 || [istarget amdgcn-*-*]
7778 || ([istarget riscv*-*-*]
7779 && [check_effective_target_riscv_v]) }}]
7782 # Return 1 if the target supports SLP permutation of 3 vectors when each
7783 # element has 8 bits.
7785 proc check_effective_target_vect_perm3_byte { } {
7786 return [expr { [check_effective_target_vect_perm_byte]
7787 && [vect_perm_supported 3 8] }]
7790 # Return 1 if the target plus current options supports vector permutation
7791 # on short-sized elements, 0 otherwise.
7793 # This won't change
for different subtargets so
cache the result.
7795 proc check_effective_target_vect_perm_short
{ } {
7796 return [check_cached_effective_target_indexed vect_perm_short
{
7797 expr
{ ([is
-effective
-target arm_neon
]
7798 && [is
-effective
-target arm_little_endian
])
7799 ||
([istarget aarch64
*-*-*]
7800 && [is
-effective
-target aarch64_little_endian
])
7801 ||
[istarget powerpc
*-*-*]
7802 ||
(([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
7803 && [check_ssse3_available
])
7804 ||
([istarget mips
*-*-*]
7805 && [et
-is
-effective
-target mips_msa
])
7806 ||
([istarget s390
*-*-*]
7807 && [check_effective_target_s390_vx
])
7808 ||
[istarget amdgcn
-*-*]
7809 ||
([istarget riscv
*-*-*]
7810 && [check_effective_target_riscv_v
]) }}]
7813 #
Return 1 if the target supports SLP permutation of
3 vectors when each
7814 # element has
16 bits.
7816 proc check_effective_target_vect_perm3_short
{ } {
7817 return [expr
{ [check_effective_target_vect_perm_short
]
7818 && [vect_perm_supported
3 16] }]
7821 #
Return 1 if the target plus current options supports folding of
7822 # copysign into XORSIGN.
7824 # This won
't change for different subtargets so cache the result.
7826 proc check_effective_target_xorsign { } {
7827 return [check_cached_effective_target_indexed xorsign {
7828 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
7829 || [istarget aarch64*-*-*] || [istarget arm*-*-*] }}]
7832 # Return 1 if the target plus current options supports a vector
7833 # widening summation of *short* args into *int* result, 0 otherwise.
7835 # This won't change
for different subtargets so
cache the result.
7837 proc check_effective_target_vect_widen_sum_hi_to_si_pattern
{ } {
7838 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si_pattern
{
7839 expr
{ [istarget powerpc
*-*-*]
7840 ||
([istarget aarch64
*-*-*]
7841 && ![check_effective_target_aarch64_sve
])
7842 ||
[is
-effective
-target arm_neon
]
7843 ||
[istarget ia64
-*-*] }}]
7846 #
Return 1 if the target plus current options supports a vector
7847 # widening summation of
*short
* args into
*int* result
, 0 otherwise.
7848 # A target can also support this widening summation
if it can support
7849 # promotion
(unpacking
) from shorts to ints.
7851 # This won
't change for different subtargets so cache the result.
7853 proc check_effective_target_vect_widen_sum_hi_to_si { } {
7854 return [check_cached_effective_target_indexed vect_widen_sum_hi_to_si {
7855 expr { [check_effective_target_vect_unpack]
7856 || [istarget powerpc*-*-*]
7857 || [istarget ia64-*-*]
7858 || [istarget riscv*-*-*] }}]
7861 # Return 1 if the target plus current options supports a vector
7862 # widening summation of *char* args into *short* result, 0 otherwise.
7863 # A target can also support this widening summation if it can support
7864 # promotion (unpacking) from chars to shorts.
7866 # This won't change
for different subtargets so
cache the result.
7868 proc check_effective_target_vect_widen_sum_qi_to_hi
{ } {
7869 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_hi
{
7870 expr
{ [check_effective_target_vect_unpack
]
7871 ||
[is
-effective
-target arm_neon
]
7872 ||
[istarget ia64
-*-*]
7873 ||
[istarget riscv
*-*-*] }}]
7876 #
Return 1 if the target plus current options supports a vector
7877 # widening summation of
*char
* args into
*int* result
, 0 otherwise.
7879 # This won
't change for different subtargets so cache the result.
7881 proc check_effective_target_vect_widen_sum_qi_to_si { } {
7882 return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si {
7883 expr { [istarget powerpc*-*-*]
7884 || [istarget riscv*-*-*] }}]
7887 # Return 1 if the target plus current options supports a vector
7888 # widening multiplication of *char* args into *short* result, 0 otherwise.
7889 # A target can also support this widening multplication if it can support
7890 # promotion (unpacking) from chars to shorts, and vect_short_mult (non-widening
7891 # multiplication of shorts).
7893 # This won't change
for different subtargets so
cache the result.
7896 proc check_effective_target_vect_widen_mult_qi_to_hi
{ } {
7897 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi
{
7898 expr
{ ([check_effective_target_vect_unpack
]
7899 && [check_effective_target_vect_short_mult
])
7900 ||
([istarget powerpc
*-*-*]
7901 ||
([istarget aarch64
*-*-*]
7902 && ![check_effective_target_aarch64_sve
])
7903 ||
[is
-effective
-target arm_neon
]
7904 ||
([istarget s390
*-*-*]
7905 && [check_effective_target_s390_vx
]))
7906 ||
[istarget amdgcn
-*-*] }}]
7909 #
Return 1 if the target plus current options supports a vector
7910 # widening multiplication of
*short
* args into
*int* result
, 0 otherwise.
7911 # A target can also support this widening multplication
if it can support
7912 # promotion
(unpacking
) from shorts to ints
, and vect_int_mult
(non
-widening
7913 # multiplication of ints
).
7915 # This won
't change for different subtargets so cache the result.
7918 proc check_effective_target_vect_widen_mult_hi_to_si { } {
7919 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si {
7920 expr { ([check_effective_target_vect_unpack]
7921 && [check_effective_target_vect_int_mult])
7922 || ([istarget powerpc*-*-*]
7923 || [istarget ia64-*-*]
7924 || ([istarget aarch64*-*-*]
7925 && ![check_effective_target_aarch64_sve])
7926 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7927 || [is-effective-target arm_neon]
7928 || ([istarget s390*-*-*]
7929 && [check_effective_target_s390_vx]))
7930 || [istarget amdgcn-*-*] }}]
7933 # Return 1 if the target plus current options supports a vector
7934 # widening multiplication of *char* args into *short* result, 0 otherwise.
7936 # This won't change
for different subtargets so
cache the result.
7938 proc check_effective_target_vect_widen_mult_qi_to_hi_pattern
{ } {
7939 return [check_cached_effective_target_indexed vect_widen_mult_qi_to_hi_pattern
{
7940 expr
{ [istarget powerpc
*-*-*]
7941 ||
([is
-effective
-target arm_neon
]
7942 && [check_effective_target_arm_little_endian
])
7943 ||
([istarget s390
*-*-*]
7944 && [check_effective_target_s390_vx
])
7945 ||
[istarget amdgcn
-*-*] }}]
7948 #
Return 1 if the target plus current options supports a vector
7949 # widening multiplication of
*short
* args into
*int* result
, 0 otherwise.
7951 # This won
't change for different subtargets so cache the result.
7953 proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
7954 return [check_cached_effective_target_indexed vect_widen_mult_hi_to_si_pattern {
7955 expr { [istarget powerpc*-*-*]
7956 || [istarget ia64-*-*]
7957 || [istarget i?86-*-*] || [istarget x86_64-*-*]
7958 || ([is-effective-target arm_neon]
7959 && [check_effective_target_arm_little_endian])
7960 || ([istarget s390*-*-*]
7961 && [check_effective_target_s390_vx])
7962 || [istarget amdgcn-*-*] }}]
7965 # Return 1 if the target plus current options supports a vector
7966 # widening multiplication of *int* args into *long* result, 0 otherwise.
7968 # This won't change
for different subtargets so
cache the result.
7970 proc check_effective_target_vect_widen_mult_si_to_di_pattern
{ } {
7971 return [check_cached_effective_target_indexed vect_widen_mult_si_to_di_pattern
{
7972 expr
{ [istarget ia64
-*-*]
7973 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
7974 ||
([istarget s390
*-*-*]
7975 && [check_effective_target_s390_vx
]) }}]
7978 #
Return 1 if the target plus current options supports a vector
7979 # widening shift
, 0 otherwise.
7981 # This won
't change for different subtargets so cache the result.
7983 proc check_effective_target_vect_widen_shift { } {
7984 return [check_cached_effective_target_indexed vect_widen_shift {
7985 expr { [is-effective-target arm_neon] }}]
7988 # Return 1 if the target plus current options supports a vector
7989 # dot-product of signed chars, 0 otherwise.
7991 # This won't change
for different subtargets so
cache the result.
7993 proc check_effective_target_vect_sdot_qi
{ } {
7994 return [check_cached_effective_target_indexed vect_sdot_qi
{
7995 expr
{ [istarget ia64
-*-*]
7996 ||
[istarget aarch64
*-*-*]
7997 ||
[istarget arm
*-*-*]
7998 ||
([istarget mips
*-*-*]
7999 && [et
-is
-effective
-target mips_msa
])
8000 ||
([istarget riscv
*-*-*]
8001 && [check_effective_target_riscv_v
]) }}]
8004 #
Return 1 if the target plus current options supports a vector
8005 # dot
-product of unsigned chars
, 0 otherwise.
8007 # This won
't change for different subtargets so cache the result.
8009 proc check_effective_target_vect_udot_qi { } {
8010 return [check_cached_effective_target_indexed vect_udot_qi {
8011 expr { [istarget powerpc*-*-*]
8012 || [istarget aarch64*-*-*]
8013 || [istarget arm*-*-*]
8014 || [istarget ia64-*-*]
8015 || ([istarget mips*-*-*]
8016 && [et-is-effective-target mips_msa])
8017 || ([istarget riscv*-*-*]
8018 && [check_effective_target_riscv_v]) }}]
8021 # Return 1 if the target plus current options supports a vector
8022 # dot-product where one operand of the multiply is signed char
8023 # and the other unsigned chars, 0 otherwise.
8025 # This won't change
for different subtargets so
cache the result.
8027 proc check_effective_target_vect_usdot_qi
{ } {
8028 return [check_cached_effective_target_indexed vect_usdot_qi
{
8029 expr
{ [istarget aarch64
*-*-*]
8030 ||
[istarget arm
*-*-*] }}]
8034 #
Return 1 if the target plus current options supports a vector
8035 # dot
-product of signed shorts
, 0 otherwise.
8037 # This won
't change for different subtargets so cache the result.
8039 proc check_effective_target_vect_sdot_hi { } {
8040 return [check_cached_effective_target_indexed vect_sdot_hi {
8041 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8042 || [istarget ia64-*-*]
8043 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8044 || ([istarget mips*-*-*]
8045 && [et-is-effective-target mips_msa])
8046 || ([istarget riscv*-*-*]
8047 && [check_effective_target_riscv_v]) }}]
8050 # Return 1 if the target plus current options supports a vector
8051 # dot-product of unsigned shorts, 0 otherwise.
8053 # This won't change
for different subtargets so
cache the result.
8055 proc check_effective_target_vect_udot_hi
{ } {
8056 return [check_cached_effective_target_indexed vect_udot_hi
{
8057 expr
{ ([istarget powerpc
*-*-*] && ![istarget powerpc
-*-linux
*paired
*])
8058 ||
([istarget mips
*-*-*]
8059 && [et
-is
-effective
-target mips_msa
])
8060 ||
([istarget riscv
*-*-*]
8061 && [check_effective_target_riscv_v
]) }}]
8064 #
Return 1 if the target plus current options supports a vector
8065 # sad operation of unsigned chars
, 0 otherwise.
8067 # This won
't change for different subtargets so cache the result.
8069 proc check_effective_target_vect_usad_char { } {
8070 return [check_cached_effective_target_indexed vect_usad_char {
8071 expr { [istarget i?86-*-*]
8072 || [istarget x86_64-*-*]
8073 || ([istarget aarch64*-*-*]
8074 && ![check_effective_target_aarch64_sve])
8075 || ([istarget powerpc*-*-*]
8076 && [check_p9vector_hw_available])
8077 || ([istarget riscv*-*-*]
8078 && [check_effective_target_riscv_v]) }}]
8081 # Return 1 if the target plus current options supports both signed
8082 # and unsigned average operations on vectors of bytes.
8084 proc check_effective_target_vect_avg_qi {} {
8085 return [expr { ([istarget aarch64*-*-*]
8086 && ![check_effective_target_aarch64_sve1_only])
8087 || ([istarget riscv*-*-*]
8088 && [check_effective_target_riscv_v]) }]
8091 # Return 1 if the target plus current options supports both signed
8092 # and unsigned multiply-high-with-round-and-scale operations
8093 # on vectors of half-words.
8095 proc check_effective_target_vect_mulhrs_hi {} {
8096 return [expr { [istarget aarch64*-*-*]
8097 && [check_effective_target_aarch64_sve2] }]
8100 # Return 1 if the target plus current options supports signed division
8101 # by power-of-2 operations on vectors of 4-byte integers.
8103 proc check_effective_target_vect_sdiv_pow2_si {} {
8104 return [expr { ([istarget aarch64*-*-*]
8105 && [check_effective_target_aarch64_sve]) }]
8108 # Return 1 if the target plus current options supports a vector
8109 # demotion (packing) of shorts (to chars) and ints (to shorts)
8110 # using modulo arithmetic, 0 otherwise.
8112 # This won't change
for different subtargets so
cache the result.
8114 proc check_effective_target_vect_pack_trunc
{ } {
8115 return [check_cached_effective_target_indexed vect_pack_trunc
{
8116 expr
{ ([istarget powerpc
*-*-*] && ![istarget powerpc
-*-linux
*paired
*])
8117 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8118 ||
[istarget aarch64
*-*-*]
8119 ||
([istarget arm
*-*-*] && [check_effective_target_arm_neon_ok
]
8120 && [check_effective_target_arm_little_endian
])
8121 ||
([istarget mips
*-*-*]
8122 && [et
-is
-effective
-target mips_msa
])
8123 ||
([istarget s390
*-*-*]
8124 && [check_effective_target_s390_vx
])
8125 ||
[istarget amdgcn
*-*-*]
8126 ||
([istarget riscv
*-*-*]
8127 && [check_effective_target_riscv_v
]) }}]
8130 #
Return 1 if the target plus current options supports a vector
8131 # promotion
(unpacking
) of chars
(to shorts
) and shorts
(to ints
), 0 otherwise.
8133 # This won
't change for different subtargets so cache the result.
8135 proc check_effective_target_vect_unpack { } {
8136 return [check_cached_effective_target_indexed vect_unpack {
8137 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
8138 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8139 || [istarget ia64-*-*]
8140 || [istarget aarch64*-*-*]
8141 || ([istarget mips*-*-*]
8142 && [et-is-effective-target mips_msa])
8143 || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]
8144 && [check_effective_target_arm_little_endian])
8145 || ([istarget s390*-*-*]
8146 && [check_effective_target_s390_vx])
8147 || [istarget amdgcn*-*-*]
8148 || ([istarget riscv*-*-*]
8149 && [check_effective_target_riscv_v]) }}]
8152 # Return 1 if the target plus current options does not guarantee
8153 # that its STACK_BOUNDARY is >= the reguired vector alignment.
8155 # This won't change
for different subtargets so
cache the result.
8157 proc check_effective_target_unaligned_stack
{ } {
8158 return [check_cached_effective_target_indexed unaligned_stack
{ expr
0 }]
8161 #
Return 1 if the target plus current options does not support a vector
8162 # alignment mechanism
, 0 otherwise.
8164 # This won
't change for different subtargets so cache the result.
8166 proc check_effective_target_vect_no_align { } {
8167 return [check_cached_effective_target_indexed vect_no_align {
8168 expr { [istarget mipsisa64*-*-*]
8169 || [istarget mips-sde-elf]
8170 || [istarget sparc*-*-*]
8171 || [istarget ia64-*-*]
8172 || [check_effective_target_arm_vect_no_misalign]
8173 || ([istarget powerpc*-*-*] && [check_p8vector_hw_available])
8174 || ([istarget mips*-*-*]
8175 && [et-is-effective-target mips_loongson_mmi]) }}]
8178 # Return 1 if the target supports a vector misalign access, 0 otherwise.
8180 # This won't change
for different subtargets so
cache the result.
8182 proc check_effective_target_vect_hw_misalign
{ } {
8183 return [check_cached_effective_target_indexed vect_hw_misalign
{
8184 if { [istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
8185 ||
([istarget powerpc
*-*-*] && [check_p8vector_hw_available
])
8186 ||
[istarget aarch64
*-*-*]
8187 ||
([istarget mips
*-*-*] && [et
-is
-effective
-target mips_msa
])
8188 ||
([istarget s390
*-*-*]
8189 && [check_effective_target_s390_vx
])
8190 ||
([istarget riscv
*-*-*]) } {
8193 if { [istarget arm
*-*-*]
8194 && ![check_effective_target_arm_vect_no_misalign
] } {
8202 #
Return 1 if arrays are aligned to the vector alignment
8203 # boundary
, 0 otherwise.
8205 proc check_effective_target_vect_aligned_arrays
{ } {
8206 set et_vect_aligned_arrays
0
8207 if { (([istarget i?
86-*-*] ||
[istarget x86_64
-*-*])
8208 && !([is
-effective
-target ia32
]
8209 ||
([check_avx_available
] && ![check_prefer_avx128
]))) } {
8210 set et_vect_aligned_arrays
1
8213 verbose
"check_effective_target_vect_aligned_arrays:\
8214 returning $et_vect_aligned_arrays
" 2
8215 return $et_vect_aligned_arrays
8218 #
Return 1 if the biggest alignment required by target is
1 * BITS_PER_UNIT.
8219 # In such case the target does not impose
any alignment constraints.
8221 proc check_effective_target_no_alignment_constraints
{ } {
8222 return [check_runtime_nocache no_alignment_constraints
{
8226 return __BIGGEST_ALIGNMENT__
== 1 ?
0 : 1;
8231 #
Return 1 if types of size
32 bit or less are naturally aligned
8232 #
(aligned to their type
-size
), 0 otherwise.
8234 # This won
't change for different subtargets so cache the result.
8236 proc check_effective_target_natural_alignment_32 { } {
8237 # FIXME: 32bit powerpc: guaranteed only if MASK_ALIGN_NATURAL/POWER.
8238 # FIXME: m68k has -malign-int
8239 return [check_cached_effective_target_indexed natural_alignment_32 {
8240 if { ([istarget *-*-darwin*] && [is-effective-target lp64])
8241 || [istarget avr-*-*]
8242 || [istarget m68k-*-linux*]
8243 || [istarget pru-*-*]
8244 || [istarget stormy16-*-*]
8245 || [istarget rl78-*-*]
8246 || [istarget pdp11-*-*]
8247 || [istarget msp430-*-*]
8248 || [istarget m32c-*-*]
8249 || [istarget cris-*-*] } {
8257 # Return 1 if types of size 64 bit or less are naturally aligned (aligned to their
8258 # type-size), 0 otherwise.
8260 # This won't change
for different subtargets so
cache the result.
8262 proc check_effective_target_natural_alignment_64
{ } {
8263 return [check_cached_effective_target_indexed natural_alignment_64
{
8264 expr
{ [is
-effective
-target natural_alignment_32
]
8265 && [is
-effective
-target lp64
] && ![istarget
*-*-darwin
*] }
8269 #
Return 1 if all vector types are naturally aligned
(aligned to their
8270 # type
-size
), 0 otherwise.
8272 proc check_effective_target_vect_natural_alignment
{ } {
8273 set et_vect_natural_alignment
1
8274 if { [check_effective_target_arm_eabi
]
8275 ||
[istarget nvptx
-*-*]
8276 ||
[istarget s390
*-*-*]
8277 ||
[istarget amdgcn
-*-*] } {
8278 set et_vect_natural_alignment
0
8280 verbose
"check_effective_target_vect_natural_alignment:\
8281 returning $et_vect_natural_alignment
" 2
8282 return $et_vect_natural_alignment
8285 #
Return true
if the target supports the check_raw_ptrs and check_war_ptrs
8286 # optabs
on vectors.
8288 proc check_effective_target_vect_check_ptrs
{ } {
8289 return [check_effective_target_aarch64_sve2
]
8292 #
Return true
if fully
-masked loops are supported.
8294 proc check_effective_target_vect_fully_masked
{ } {
8295 return [expr
{ [check_effective_target_aarch64_sve
]
8296 ||
[istarget amdgcn
*-*-*]
8297 ||
[check_effective_target_riscv_v
] }]
8300 #
Return true
if the target supports the @code
{len_load
} and
8301 # @code
{len_store
} optabs.
8303 proc check_effective_target_vect_len_load_store
{ } {
8304 return [expr
{ [check_effective_target_has_arch_pwr9
]
8305 ||
[check_effective_target_s390_vx
]
8306 ||
[check_effective_target_riscv_v
] }]
8309 #
Return the value of parameter vect
-partial
-vector
-usage specified
for
8310 # target by checking the output of
"-Q --help=params". Return zero if
8311 # the desirable pattern isn
't found.
8313 proc check_vect_partial_vector_usage { } {
8316 return [check_cached_effective_target vect_partial_vector_usage {
8317 set result [check_compile vect_partial_vector_usage assembly {
8319 } "-Q --help=params" ]
8321 # Get compiler emitted messages and delete generated file.
8322 set lines [lindex $result 0]
8323 set output [lindex $result 1]
8324 remote_file build delete $output
8326 set pattern {=vect-partial-vector-usage=<0,2>\s+([0-2])}
8327 # Capture the usage value to val, set it to zero if not found.
8328 if { ![regexp $pattern $lines whole val] } then {
8336 # Return true if the target supports loop vectorization with partial vectors
8337 # and @code{vect-partial-vector-usage} is set to 1.
8339 proc check_effective_target_vect_partial_vectors_usage_1 { } {
8340 return [expr { ([check_effective_target_vect_fully_masked]
8341 || [check_effective_target_vect_len_load_store])
8342 && [check_vect_partial_vector_usage] == 1 }]
8345 # Return true if the target supports loop vectorization with partial vectors
8346 # and @code{vect-partial-vector-usage} is set to 2.
8348 proc check_effective_target_vect_partial_vectors_usage_2 { } {
8349 return [expr { ([check_effective_target_vect_fully_masked]
8350 || [check_effective_target_vect_len_load_store])
8351 && [check_vect_partial_vector_usage] == 2 }]
8354 # Return true if the target supports loop vectorization with partial vectors
8355 # and @code{vect-partial-vector-usage} is nonzero.
8357 proc check_effective_target_vect_partial_vectors { } {
8358 return [expr { ([check_effective_target_vect_fully_masked]
8359 || [check_effective_target_vect_len_load_store])
8360 && [check_vect_partial_vector_usage] != 0 }]
8363 # Return 1 if the target doesn't prefer
any alignment beyond element
8364 # alignment during vectorization.
8366 proc check_effective_target_vect_element_align_preferred
{ } {
8367 return [expr
{ ([check_effective_target_aarch64_sve
]
8368 && [check_effective_target_vect_variable_length
])
8369 ||
[check_effective_target_riscv_v
] }]
8372 #
Return true
if vectorization of v2qi
/v4qi
/v8qi
/v16qi
/v2hi store is enabed.
8373 #
Return zero
if the desirable pattern isn
't found.
8374 # It's used by Warray
-bounds
/Wstringop
-overflow testcases which are
8375 # regressed by O2 vectorization
, refer to PR102697
/PR102462
/PR102706
8376 proc check_vect_slp_store_usage
{ pattern macro
} {
8379 set result
[check_compile slp_aligned_store_usage assembly
{
8380 extern void sink
(void
* );
8381 #
define Ac8
(AC8
){ 0, 1, 2, 3, 4, 5, 6, 7 }
8382 #
define Ac16
(AC16
){ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }
8384 typedef struct AC16
{ char a
[16]; } AC16
;
8385 extern char a16
[16];
8392 typedef struct AC8
{ char a
[8]; } AC8
;
8406 extern void sink
(void
*);
8410 struct A1 a
= { 0, { } };
8427 #
define Ac4
(AC4
){ 0, 1, 2, 3 }
8428 typedef struct AC4
{ char a
[4]; } AC4
;
8476 *(short
*) (b
+ 2) = 1;
8485 foo4_2
(struct Ax
*p
)
8491 struct A
{ int i
; };
8492 struct B
{ int j
; struct A a
[4]; };
8499 char cbuf2
[2 * sizeof
(struct C
)] = { };
8503 struct C
*p
= (struct C
*)&cbuf2
;
8510 struct A
{ int i
; };
8511 struct B
{ int j
; struct A a
[2]; };
8518 char cbuf2
[2 * sizeof
(struct C
)] = { };
8522 struct C
*p
= (struct C
*)&cbuf2
;
8528 } "-O2 -fopt-info-all -D$macro" ]
8530 #
Get compiler emitted messages and
delete generated file.
8531 set lines
[lindex $result
0]
8532 set output
[lindex $result
1]
8533 remote_file build
delete $output
8535 # Check pattern exits in lines
, set it to zero
if not found.
8536 if { [regexp $pattern $lines
] } then {
8543 #
Return the true
if target support vectorization of
2-byte char stores
8544 # with
2-byte aligned address at plain O2.
8545 # NB
: This target should be removed after real issues are fixed
for
8546 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8547 # this target since tests in check_vect_slp_store_usage
8548 # is the exact match of relative testcases
8549 proc check_effective_target_vect_slp_v2qi_store_align
{ } {
8550 set pattern
{add new stmt
: MEM
<vector\
(2\
) char
>}
8551 set macro
"TEST_V2QI"
8552 return [check_cached_effective_target vect_slp_v2qi_store_align
{
8553 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8556 #
Return the true
if target support vectorization of
2-byte char stores
8557 # with unaligned address at plain O2.
8558 proc check_effective_target_vect_slp_v2qi_store_unalign
{ } {
8559 set pattern
{add new stmt
: MEM
<vector\
(2\
) char
>}
8560 set macro
"TEST_V2QI_2"
8561 return [check_cached_effective_target vect_slp_v2qi_store_unalign
{
8562 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8565 #
Return the true
if target support vectorization of
4-byte char stores
8566 # with
4-byte aligned address at plain O2.
8567 # NB
: This target should be removed after real issues are fixed
for
8568 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8569 # this target since tests in check_vect_slp_store_usage
8570 # is the exact match of relative testcases
8571 proc check_effective_target_vect_slp_v4qi_store_align
{ } {
8572 set pattern
{add new stmt
: MEM
<vector\
(4\
) char
>}
8573 set macro
"TEST_V4QI"
8574 return [check_cached_effective_target vect_slp_v4qi_store_align
{
8575 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8578 #
Return the true
if target support vectorization of
4-byte char stores
8579 # with unaligned address at plain O2.
8580 proc check_effective_target_vect_slp_v4qi_store_unalign
{ } {
8581 set pattern
{add new stmt
: MEM
<vector\
(4\
) char
>}
8582 set macro
"TEST_V4QI_2"
8583 return [check_cached_effective_target vect_slp_v4qi_store_unalign
{
8584 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8587 #
Return the true
if target support block
move for
8588 #
8-byte aligned
4-byte size struct initialization.
8589 proc check_effective_target_struct_4char_block_move
{ } {
8590 set pattern
{not vectorized
: more than one data ref in stmt
:}
8591 set macro
"TEST_V4QI_3"
8592 return [check_cached_effective_target struct_4char_block_move
{
8593 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8596 #
Return the true
if target support vectorization of
4-byte char stores
8597 # with unaligned address or store them with a constant pool at plain O2.
8598 proc check_effective_target_vect_slp_v4qi_store_unalign_1
{ } {
8599 set pattern
{add new stmt
: MEM
<vector\
(4\
) char
>}
8600 set macro
"TEST_V4QI_3"
8601 return [check_cached_effective_target vect_slp_v4qi_store_unalign_1
{
8602 expr
{ [check_vect_slp_store_usage $pattern $macro
]
8603 ||
[check_effective_target_struct_4char_block_move
] } }]
8606 #
Return the true
if target support block
move for
8607 #
8-byte aligned
8-byte size struct initialization.
8608 proc check_effective_target_struct_8char_block_move
{ } {
8609 set pattern
{not vectorized
: more than one data ref in stmt
:}
8610 set macro
"TEST_V8QI"
8611 return [check_cached_effective_target struct_8char_block_move
{
8612 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8615 #
Return the true
if target support vectorization of
8-byte char stores
8616 # with unaligned address or store them with a constant pool at plain O2.
8617 # NB
: This target should be removed after real issues are fixed
for
8618 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8619 # this target since tests in check_vect_slp_store_usage
8620 # is the exact match of relative testcases
8621 proc check_effective_target_vect_slp_v8qi_store_unalign_1
{ } {
8622 set pattern
{add new stmt
: MEM
<vector\
(8\
) char
>}
8623 set macro
"TEST_V8QI"
8624 return [check_cached_effective_target vect_slp_v8qi_store_unalign_1
{
8625 expr
{ [check_vect_slp_store_usage $pattern $macro
]
8626 ||
[check_effective_target_struct_8char_block_move
] } }]
8629 #
Return the true
if target support block
move for
8630 #
8-byte aligned
16-byte size struct initialization.
8631 proc check_effective_target_struct_16char_block_move
{ } {
8632 set pattern
{not vectorized
: more than one data ref in stmt
:}
8633 set macro
"TEST_V16QI"
8634 return [check_cached_effective_target struct_16char_block_move
{
8635 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8638 #
Return the true
if target support vectorization of
16-byte char stores
8639 # with unaligned address or store them with a constant pool at plain O2.
8640 # NB
: This target should be removed after real issues are fixed
for
8641 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8642 # this target since tests in check_vect_slp_store_usage
8643 # is the exact match of relative testcases
8644 proc check_effective_target_vect_slp_v16qi_store_unalign_1
{ } {
8645 set pattern
{add new stmt
: MEM
<vector\
(16\
) char
>}
8646 set macro
"TEST_V16QI"
8647 return [check_cached_effective_target vect_slp_v16qi_store_unalign_1
{
8648 expr
{ [check_vect_slp_store_usage $pattern $macro
]
8649 ||
[check_effective_target_struct_16char_block_move
] } }]
8652 #
Return the true
if target support vectorization of
4-byte short stores
8653 # with unaligned address at plain O2.
8654 # NB
: This target should be removed after real issues are fixed
for
8655 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8656 # this target since tests in check_vect_slp_store_usage
8657 # is the exact match of relative testcases
8658 proc check_effective_target_vect_slp_v2hi_store_unalign
{ } {
8659 set pattern
{add new stmt
: MEM
<vector\
(2\
) short
int>}
8660 set macro
"TEST_V2HI"
8661 return [check_cached_effective_target vect_slp_v2hi_store_unalign
{
8662 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8665 #
Return the true
if target support vectorization of
4-byte short stores
8666 # with
4-byte aligned address at plain O2.
8667 proc check_effective_target_vect_slp_v2hi_store_align
{ } {
8668 set pattern
{add new stmt
: MEM
<vector\
(2\
) short
int>}
8669 set macro
"TEST_V2HI_2"
8670 return [check_cached_effective_target vect_slp_v2hi_store_align
{
8671 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8674 #
Return the true
if target support vectorization of
8-byte short stores
8675 # with unaligned address at plain O2.
8676 # NB
: This target should be removed after real issues are fixed
for
8677 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8678 # this target since tests in check_vect_slp_store_usage
8679 # is the exact match of relative testcases
8680 proc check_effective_target_vect_slp_v4hi_store_unalign
{ } {
8681 set pattern
{add new stmt
: MEM
<vector\
(4\
) short
int>}
8682 set macro
"TEST_V4HI"
8683 return [check_cached_effective_target vect_slp_v4hi_store_unalign
{
8684 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8687 #
Return the true
if target support vectorization of
8-byte
int stores
8688 # with
8-byte aligned address at plain O2.
8689 # NB
: This target should be removed after real issues are fixed
for
8690 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8691 # this target since tests in check_vect_slp_store_usage
8692 # is the exact match of relative testcases
8693 proc check_effective_target_vect_slp_v2si_store_align
{ } {
8694 set pattern
{add new stmt
: MEM
<vector\
(2\
) int>}
8695 set macro
"TEST_V2SI"
8696 return [check_cached_effective_target vect_slp_v2si_store_align
{
8697 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8700 #
Return the true
if target support vectorization of
16-byte
int stores
8701 # with unaligned address at plain O2.
8702 # NB
: This target should be removed after real issues are fixed
for
8703 #
-Wstringop
-overflow with O2 vect. Be careful
if you want to reuse
8704 # this target since tests in check_vect_slp_store_usage
8705 # is the exact match of relative testcases
8706 proc check_effective_target_vect_slp_v4si_store_unalign
{ } {
8707 set pattern
{add new stmt
: MEM
<vector\
(4\
) int>}
8708 set macro
"TEST_V4SI"
8709 return [check_cached_effective_target vect_slp_v4si_store_unalign
{
8710 expr
[check_vect_slp_store_usage $pattern $macro
] }]
8713 #
Return 1 if we can align stack data to the preferred vector alignment.
8715 proc check_effective_target_vect_align_stack_vars
{ } {
8716 if { [check_effective_target_aarch64_sve
] } {
8717 return [check_effective_target_vect_variable_length
]
8722 #
Return 1 if vector alignment
(for types of size
32 bit or less
) is reachable
, 0 otherwise.
8724 proc check_effective_target_vector_alignment_reachable
{ } {
8725 set et_vector_alignment_reachable
0
8726 if { [check_effective_target_vect_aligned_arrays
]
8727 ||
[check_effective_target_natural_alignment_32
] } {
8728 set et_vector_alignment_reachable
1
8730 verbose
"check_effective_target_vector_alignment_reachable:\
8731 returning $et_vector_alignment_reachable
" 2
8732 return $et_vector_alignment_reachable
8735 #
Return 1 if vector alignment
for 64 bit is reachable
, 0 otherwise.
8737 proc check_effective_target_vector_alignment_reachable_for_64bit
{ } {
8738 set et_vector_alignment_reachable_for_64bit
0
8739 if { [check_effective_target_vect_aligned_arrays
]
8740 ||
[check_effective_target_natural_alignment_64
] } {
8741 set et_vector_alignment_reachable_for_64bit
1
8743 verbose
"check_effective_target_vector_alignment_reachable_for_64bit:\
8744 returning $et_vector_alignment_reachable_for_64bit
" 2
8745 return $et_vector_alignment_reachable_for_64bit
8748 #
Return 1 if the target only requires element alignment
for vector accesses
8750 proc check_effective_target_vect_element_align
{ } {
8751 return [check_cached_effective_target_indexed vect_element_align
{
8752 expr
{ ([istarget arm
*-*-*]
8753 && ![check_effective_target_arm_vect_no_misalign
])
8754 ||
[check_effective_target_vect_hw_misalign
]
8755 ||
[istarget amdgcn
-*-*] }}]
8758 #
Return 1 if we expect to see unaligned accesses in at least some
8761 proc check_effective_target_vect_unaligned_possible
{ } {
8762 return [expr
{ ![check_effective_target_vect_element_align_preferred
]
8763 && (![check_effective_target_vect_no_align
]
8764 ||
[check_effective_target_vect_hw_misalign
]) }]
8767 #
Return 1 if the target supports vector LOAD_LANES operations
, 0 otherwise.
8769 proc check_effective_target_vect_load_lanes
{ } {
8770 # We don
't support load_lanes correctly on big-endian arm.
8771 return [check_cached_effective_target vect_load_lanes {
8772 expr { ([check_effective_target_arm_little_endian]
8773 && [check_effective_target_arm_neon_ok])
8774 || [istarget aarch64*-*-*]
8775 || [istarget riscv*-*-*] }}]
8778 # Return 1 if the target supports vector masked loads.
8780 proc check_effective_target_vect_masked_load { } {
8781 return [expr { [check_avx_available]
8782 || [check_effective_target_aarch64_sve]
8783 || [istarget amdgcn*-*-*]
8784 || [check_effective_target_riscv_v] } ]
8787 # Return 1 if the target supports vector masked stores.
8789 proc check_effective_target_vect_masked_store { } {
8790 return [expr { [check_avx_available]
8791 || [check_effective_target_aarch64_sve]
8792 || [istarget amdgcn*-*-*]
8793 || [check_effective_target_riscv_v] }]
8796 # Return 1 if the target supports vector gather loads via internal functions.
8798 proc check_effective_target_vect_gather_load_ifn { } {
8799 return [expr { [check_effective_target_aarch64_sve]
8800 || [istarget amdgcn*-*-*]
8801 || [check_effective_target_riscv_v] }]
8804 # Return 1 if the target supports vector scatter stores.
8806 proc check_effective_target_vect_scatter_store { } {
8807 return [expr { [check_effective_target_aarch64_sve]
8808 || [istarget amdgcn*-*-*]
8809 || [check_effective_target_riscv_v] }]
8812 # Return 1 if the target supports vector conditional operations, 0 otherwise.
8814 proc check_effective_target_vect_condition { } {
8815 return [check_cached_effective_target_indexed vect_condition {
8816 expr { [istarget aarch64*-*-*]
8817 || [istarget powerpc*-*-*]
8818 || [istarget ia64-*-*]
8819 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8820 || ([istarget mips*-*-*]
8821 && [et-is-effective-target mips_msa])
8822 || ([istarget arm*-*-*]
8823 && [check_effective_target_arm_neon_ok])
8824 || ([istarget s390*-*-*]
8825 && [check_effective_target_s390_vx])
8826 || [istarget amdgcn-*-*]
8827 || ([istarget riscv*-*-*]
8828 && [check_effective_target_riscv_v]) }}]
8831 # Return 1 if the target supports vector conditional operations where
8832 # the comparison has different type from the lhs, 0 otherwise.
8834 proc check_effective_target_vect_cond_mixed { } {
8835 return [check_cached_effective_target_indexed vect_cond_mixed {
8836 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
8837 || [istarget aarch64*-*-*]
8838 || [istarget powerpc*-*-*]
8839 || ([istarget arm*-*-*]
8840 && [check_effective_target_arm_neon_ok])
8841 || ([istarget mips*-*-*]
8842 && [et-is-effective-target mips_msa])
8843 || ([istarget s390*-*-*]
8844 && [check_effective_target_s390_vx])
8845 || [istarget amdgcn-*-*]
8846 || ([istarget riscv*-*-*]
8847 && [check_effective_target_riscv_v]) }}]
8850 # Return 1 if the target supports vector char multiplication, 0 otherwise.
8852 proc check_effective_target_vect_char_mult { } {
8853 return [check_cached_effective_target_indexed vect_char_mult {
8854 expr { [istarget aarch64*-*-*]
8855 || [istarget ia64-*-*]
8856 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8857 || [check_effective_target_arm32]
8858 || [check_effective_target_powerpc_altivec]
8859 || ([istarget mips*-*-*]
8860 && [et-is-effective-target mips_msa])
8861 || ([istarget s390*-*-*]
8862 && [check_effective_target_s390_vx])
8863 || [istarget amdgcn-*-*]
8864 || ([istarget riscv*-*-*]
8865 && [check_effective_target_riscv_v]) }}]
8868 # Return 1 if the target supports vector short multiplication, 0 otherwise.
8870 proc check_effective_target_vect_short_mult { } {
8871 return [check_cached_effective_target_indexed vect_short_mult {
8872 expr { [istarget ia64-*-*]
8873 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8874 || [istarget powerpc*-*-*]
8875 || [istarget aarch64*-*-*]
8876 || [check_effective_target_arm32]
8877 || ([istarget mips*-*-*]
8878 && ([et-is-effective-target mips_msa]
8879 || [et-is-effective-target mips_loongson_mmi]))
8880 || ([istarget s390*-*-*]
8881 && [check_effective_target_s390_vx])
8882 || [istarget amdgcn-*-*]
8883 || ([istarget riscv*-*-*]
8884 && [check_effective_target_riscv_v]) }}]
8887 # Return 1 if the target supports vector int multiplication, 0 otherwise.
8889 proc check_effective_target_vect_int_mult { } {
8890 return [check_cached_effective_target_indexed vect_int_mult {
8891 expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*-linux*paired*])
8892 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8893 || [istarget ia64-*-*]
8894 || [istarget aarch64*-*-*]
8895 || ([istarget mips*-*-*]
8896 && [et-is-effective-target mips_msa])
8897 || [check_effective_target_arm32]
8898 || ([istarget s390*-*-*]
8899 && [check_effective_target_s390_vx])
8900 || [istarget amdgcn-*-*]
8901 || ([istarget riscv*-*-*]
8902 && [check_effective_target_riscv_v]) }}]
8905 # Return 1 if the target supports 64 bit hardware vector
8906 # multiplication of long operands with a long result, 0 otherwise.
8908 # This can change for different subtargets so do not cache the result.
8910 proc check_effective_target_vect_long_mult { } {
8911 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
8912 || (([istarget powerpc*-*-*]
8913 && ![istarget powerpc-*-linux*paired*])
8914 && [check_effective_target_ilp32])
8915 || [is-effective-target arm_neon]
8916 || ([istarget sparc*-*-*] && [check_effective_target_ilp32])
8917 || [istarget aarch64*-*-*]
8918 || ([istarget mips*-*-*]
8919 && [et-is-effective-target mips_msa])
8920 || ([istarget riscv*-*-*]
8921 && [check_effective_target_riscv_v]) } {
8927 verbose "check_effective_target_vect_long_mult: returning $answer" 2
8931 # Return 1 if the target supports vector int modulus, 0 otherwise.
8933 proc check_effective_target_vect_int_mod { } {
8934 return [check_cached_effective_target_indexed vect_int_mod {
8935 expr { ([istarget powerpc*-*-*]
8936 && [check_effective_target_has_arch_pwr10])
8937 || [istarget amdgcn-*-*]
8938 || ([istarget loongarch*-*-*]
8939 && [check_effective_target_loongarch_sx])
8940 || ([istarget riscv*-*-*]
8941 && [check_effective_target_riscv_v]) }}]
8944 # Return 1 if the target supports vector even/odd elements extraction, 0 otherwise.
8946 proc check_effective_target_vect_extract_even_odd { } {
8947 return [check_cached_effective_target_indexed extract_even_odd {
8948 expr { [istarget aarch64*-*-*]
8949 || [istarget powerpc*-*-*]
8950 || [is-effective-target arm_neon]
8951 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8952 || [istarget ia64-*-*]
8953 || ([istarget mips*-*-*]
8954 && ([et-is-effective-target mips_msa]
8955 || [et-is-effective-target mpaired_single]))
8956 || ([istarget s390*-*-*]
8957 && [check_effective_target_s390_vx])
8958 || ([istarget riscv*-*-*]
8959 && [check_effective_target_riscv_v]) }}]
8962 # Return 1 if the target supports vector interleaving, 0 otherwise.
8964 proc check_effective_target_vect_interleave { } {
8965 return [check_cached_effective_target_indexed vect_interleave {
8966 expr { [istarget aarch64*-*-*]
8967 || [istarget powerpc*-*-*]
8968 || [is-effective-target arm_neon]
8969 || [istarget i?86-*-*] || [istarget x86_64-*-*]
8970 || [istarget ia64-*-*]
8971 || ([istarget mips*-*-*]
8972 && ([et-is-effective-target mpaired_single]
8973 || [et-is-effective-target mips_msa]))
8974 || ([istarget s390*-*-*]
8975 && [check_effective_target_s390_vx])
8976 || ([istarget riscv*-*-*]
8977 && [check_effective_target_riscv_v]) }}]
8980 foreach N {2 3 4 5 6 7 8} {
8981 eval [string map [list N $N] {
8982 # Return 1 if the target supports 2-vector interleaving
8983 proc check_effective_target_vect_stridedN { } {
8984 return [check_cached_effective_target_indexed vect_stridedN {
8986 && [check_effective_target_vect_interleave]
8987 && [check_effective_target_vect_extract_even_odd] } {
8990 if { ([istarget arm*-*-*]
8991 || [istarget aarch64*-*-*]) && N >= 2 && N <= 4 } {
8994 if { ([istarget riscv*-*-*]) && N >= 2 && N <= 8 } {
8997 if [check_effective_target_vect_fully_masked] {
9006 # Return the list of vector sizes (in bits) that each target supports.
9007 # A vector length of "0" indicates variable-length vectors.
9009 proc available_vector_sizes { } {
9011 if { [istarget aarch64*-*-*] } {
9012 if { [check_effective_target_aarch64_sve] } {
9013 lappend result [aarch64_sve_bits]
9015 lappend result 128 64
9016 } elseif { [istarget arm*-*-*]
9017 && [check_effective_target_arm_neon_ok] } {
9018 lappend result 128 64
9019 } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
9020 if { [check_avx_available] && ![check_prefer_avx128] } {
9024 if { ![is-effective-target ia32] } {
9028 } elseif { [istarget sparc*-*-*] } {
9030 } elseif { [istarget amdgcn*-*-*] } {
9031 # 6 different lane counts, and 4 element sizes
9032 lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2
9033 } elseif { [istarget riscv*-*-*] } {
9034 if { [check_effective_target_riscv_v] } {
9035 lappend result 0 32 64 128 256 512 1024
9039 # The traditional default asumption.
9045 # Return 1 if the target supports multiple vector sizes
9047 proc check_effective_target_vect_multiple_sizes { } {
9048 return [expr { [llength [available_vector_sizes]] > 1 }]
9051 # Return true if variable-length vectors are supported.
9053 proc check_effective_target_vect_variable_length { } {
9054 return [expr { [lindex [available_vector_sizes] 0] == 0 }]
9057 # Return 1 if the target supports vectors of 1024 bits.
9059 proc check_effective_target_vect1024 { } {
9060 return [expr { [lsearch -exact [available_vector_sizes] 1024] >= 0 }]
9063 # Return 1 if the target supports vectors of 512 bits.
9065 proc check_effective_target_vect512 { } {
9066 return [expr { [lsearch -exact [available_vector_sizes] 512] >= 0 }]
9069 # Return 1 if the target supports vectors of 256 bits.
9071 proc check_effective_target_vect256 { } {
9072 return [expr { [lsearch -exact [available_vector_sizes] 256] >= 0 }]
9075 # Return 1 if the target supports vectors of 128 bits.
9077 proc check_effective_target_vect128 { } {
9078 return [expr { [lsearch -exact [available_vector_sizes] 128] >= 0 }]
9081 # Return 1 if the target supports vectors of 64 bits.
9083 proc check_effective_target_vect64 { } {
9084 return [expr { [lsearch -exact [available_vector_sizes] 64] >= 0 }]
9087 # Return 1 if the target supports vectors of 32 bits.
9089 proc check_effective_target_vect32 { } {
9090 return [expr { [lsearch -exact [available_vector_sizes] 32] >= 0 }]
9093 # Return 1 if the target supports vector copysignf calls.
9095 proc check_effective_target_vect_call_copysignf { } {
9096 return [check_cached_effective_target_indexed vect_call_copysignf {
9097 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
9098 || [istarget powerpc*-*-*]
9099 || [istarget aarch64*-*-*]
9100 || [istarget amdgcn-*-*]
9101 || ([istarget riscv*-*-*]
9102 && [check_effective_target_riscv_v]) }}]
9105 # Return 1 if the target supports hardware square root instructions.
9107 proc check_effective_target_sqrt_insn { } {
9108 return [check_cached_effective_target sqrt_insn {
9109 expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
9110 || [check_effective_target_powerpc_sqrt]
9111 || [istarget aarch64*-*-*]
9112 || ([istarget arm*-*-*] && [check_effective_target_arm_vfp_ok])
9113 || ([istarget s390*-*-*]
9114 && [check_effective_target_s390_vx])
9115 || [istarget amdgcn-*-*] }}]
9118 # Return any additional options to enable square root intructions.
9120 proc add_options_for_sqrt_insn { flags } {
9121 if { [istarget amdgcn*-*-*] } {
9122 return "$flags -ffast-math"
9124 if { [istarget arm*-*-*] } {
9125 return [add_options_for_arm_vfp "$flags"]
9130 # Return 1 if the target supports vector sqrtf calls.
9132 proc check_effective_target_vect_call_sqrtf { } {
9133 return [check_cached_effective_target_indexed vect_call_sqrtf {
9134 expr { [istarget aarch64*-*-*]
9135 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9136 || ([istarget powerpc*-*-*] && [check_vsx_hw_available])
9137 || ([istarget s390*-*-*]
9138 && [check_effective_target_s390_vx])
9139 || [istarget amdgcn-*-*]
9140 || ([istarget riscv*-*-*]
9141 && [check_effective_target_riscv_v]) }}]
9144 # Return 1 if the target supports vector lrint calls.
9146 proc check_effective_target_vect_call_lrint { } {
9147 set et_vect_call_lrint 0
9148 if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
9149 && [check_effective_target_ilp32])
9150 || [istarget amdgcn-*-*] } {
9151 set et_vect_call_lrint 1
9154 verbose "check_effective_target_vect_call_lrint: returning $et_vect_call_lrint" 2
9155 return $et_vect_call_lrint
9158 # Return 1 if the target supports vector btrunc calls.
9160 proc check_effective_target_vect_call_btrunc { } {
9161 return [check_cached_effective_target_indexed vect_call_btrunc {
9162 expr { [istarget aarch64*-*-*]
9163 || [istarget amdgcn-*-*] }}]
9166 # Return 1 if the target supports vector btruncf calls.
9168 proc check_effective_target_vect_call_btruncf { } {
9169 return [check_cached_effective_target_indexed vect_call_btruncf {
9170 expr { [istarget aarch64*-*-*]
9171 || [istarget amdgcn-*-*] }}]
9174 # Return 1 if the target supports vector ceil calls.
9176 proc check_effective_target_vect_call_ceil { } {
9177 return [check_cached_effective_target_indexed vect_call_ceil {
9178 expr { [istarget aarch64*-*-*]
9179 || [istarget amdgcn-*-*] }}]
9182 # Return 1 if the target supports vector ceilf calls.
9184 proc check_effective_target_vect_call_ceilf { } {
9185 return [check_cached_effective_target_indexed vect_call_ceilf {
9186 expr { [istarget aarch64*-*-*]
9187 || [istarget amdgcn-*-*] }}]
9190 # Return 1 if the target supports vector floor calls.
9192 proc check_effective_target_vect_call_floor { } {
9193 return [check_cached_effective_target_indexed vect_call_floor {
9194 expr { [istarget aarch64*-*-*]
9195 || [istarget amdgcn-*-*] }}]
9198 # Return 1 if the target supports vector floorf calls.
9200 proc check_effective_target_vect_call_floorf { } {
9201 return [check_cached_effective_target_indexed vect_call_floorf {
9202 expr { [istarget aarch64*-*-*]
9203 || [istarget amdgcn-*-*] }}]
9206 # Return 1 if the target supports vector lceil calls.
9208 proc check_effective_target_vect_call_lceil { } {
9209 return [check_cached_effective_target_indexed vect_call_lceil {
9210 expr { [istarget aarch64*-*-*] }}]
9213 # Return 1 if the target supports vector lfloor calls.
9215 proc check_effective_target_vect_call_lfloor { } {
9216 return [check_cached_effective_target_indexed vect_call_lfloor {
9217 expr { [istarget aarch64*-*-*] }}]
9220 # Return 1 if the target supports vector nearbyint calls.
9222 proc check_effective_target_vect_call_nearbyint { } {
9223 return [check_cached_effective_target_indexed vect_call_nearbyint {
9224 expr { [istarget aarch64*-*-*] }}]
9227 # Return 1 if the target supports vector nearbyintf calls.
9229 proc check_effective_target_vect_call_nearbyintf { } {
9230 return [check_cached_effective_target_indexed vect_call_nearbyintf {
9231 expr { [istarget aarch64*-*-*] }}]
9234 # Return 1 if the target supports vector round calls.
9236 proc check_effective_target_vect_call_round { } {
9237 return [check_cached_effective_target_indexed vect_call_round {
9238 expr { [istarget aarch64*-*-*] }}]
9241 # Return 1 if the target supports vector roundf calls.
9243 proc check_effective_target_vect_call_roundf { } {
9244 return [check_cached_effective_target_indexed vect_call_roundf {
9245 expr { [istarget aarch64*-*-*] }}]
9248 # Return 1 if the target supports AND, OR and XOR reduction.
9250 proc check_effective_target_vect_logical_reduc { } {
9251 return [expr { [check_effective_target_aarch64_sve]
9252 || [istarget amdgcn-*-*]
9253 || [check_effective_target_riscv_v]
9254 || [istarget i?86-*-*] || [istarget x86_64-*-*]}]
9257 # Return 1 if the target supports the fold_extract_last optab.
9259 proc check_effective_target_vect_fold_extract_last { } {
9260 return [expr { [check_effective_target_aarch64_sve]
9261 || [istarget amdgcn*-*-*]
9262 || [check_effective_target_riscv_v] }]
9265 # Return 1 if the target supports section-anchors
9267 proc check_effective_target_section_anchors { } {
9268 return [check_cached_effective_target section_anchors {
9269 expr { [istarget powerpc*-*-*]
9270 || [istarget arm*-*-*]
9271 || [istarget aarch64*-*-*] }}]
9274 # Return 1 if the target supports atomic operations on "int_128" values.
9276 proc check_effective_target_sync_int_128 { } {
9280 # Return 1 if the target supports atomic operations on "int_128" values
9281 # and can execute them.
9282 # This requires support for both compare-and-swap and true atomic loads.
9284 proc check_effective_target_sync_int_128_runtime { } {
9288 # Return 1 if the target supports atomic operations on "long long".
9290 # Note: 32bit x86 targets require -march=pentium in dg-options.
9291 # Note: 32bit s390 targets require -mzarch in dg-options.
9293 proc check_effective_target_sync_long_long { } {
9294 if { [istarget i?86-*-*] || [istarget x86_64-*-*]
9295 || [istarget aarch64*-*-*]
9296 || [istarget arm*-*-*]
9297 || [istarget alpha*-*-*]
9298 || ([istarget sparc*-*-*] && [check_effective_target_lp64])
9299 || [istarget s390*-*-*] } {
9306 # Return 1 if the target supports popcount on long.
9308 proc check_effective_target_popcountl { } {
9309 return [check_no_messages_and_pattern popcountl "!\\(call" rtl-expand {
9312 return __builtin_popcountl (b);
9317 # Return 1 if the target supports popcount on long long.
9319 proc check_effective_target_popcountll { } {
9320 return [check_no_messages_and_pattern popcountll "!\\(call" rtl-expand {
9321 int foo (long long b)
9323 return __builtin_popcountll (b);
9329 # Return 1 if the target supports popcount on int.
9331 proc check_effective_target_popcount { } {
9332 return [check_no_messages_and_pattern popcount "!\\(call" rtl-expand {
9335 return __builtin_popcount (b);
9340 # Return 1 if the target supports clz on int.
9342 proc check_effective_target_clz { } {
9343 return [check_no_messages_and_pattern clz "!\\(call" rtl-expand {
9346 return __builtin_clz (b);
9351 # Return 1 if the target supports clz on long.
9353 proc check_effective_target_clzl { } {
9354 return [check_no_messages_and_pattern clzl "!\\(call" rtl-expand {
9357 return __builtin_clzl (b);
9362 # Return 1 if the target supports clz on long long.
9364 proc check_effective_target_clzll { } {
9365 return [check_no_messages_and_pattern clzll "!\\(call" rtl-expand {
9366 int foo (long long b)
9368 return __builtin_clzll (b);
9373 # Return 1 if the target supports ctz on int.
9375 proc check_effective_target_ctz { } {
9376 return [check_no_messages_and_pattern ctz "!\\(call" rtl-expand {
9379 return __builtin_ctz (b);
9384 # Return 1 if the target supports ctz on long.
9386 proc check_effective_target_ctzl { } {
9387 return [check_no_messages_and_pattern ctzl "!\\(call" rtl-expand {
9390 return __builtin_ctzl (b);
9395 # Return 1 if the target supports ctz on long long.
9397 proc check_effective_target_ctzll { } {
9398 return [check_no_messages_and_pattern ctzll "!\\(call" rtl-expand {
9399 int foo (long long b)
9401 return __builtin_ctzll (b);
9406 # Return 1 if the target supports atomic operations on "long long"
9407 # and can execute them.
9409 # Note: 32bit x86 targets require -march=pentium in dg-options.
9411 proc check_effective_target_sync_long_long_runtime { } {
9412 if { (([istarget x86_64-*-*] || [istarget i?86-*-*])
9413 && [check_cached_effective_target sync_long_long_available {
9414 check_runtime_nocache sync_long_long_available {
9418 unsigned int eax, ebx, ecx, edx;
9419 if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
9420 return !(edx & bit_CMPXCHG8B);
9425 || [istarget aarch64*-*-*]
9426 || [istarget arm*-*-uclinuxfdpiceabi]
9427 || ([istarget arm*-*-linux-*]
9428 && [check_runtime sync_longlong_runtime {
9434 if (sizeof (long long) != 8)
9437 /* Just check for native;
9438 checking for kernel fallback is tricky. */
9439 asm volatile ("ldrexd r0,r1, [%0]"
9440 : : "r" (&l1) : "r0", "r1");
9444 || [istarget alpha*-*-*]
9445 || ([istarget sparc*-*-*]
9446 && [check_effective_target_lp64]
9447 && [check_effective_target_ultrasparc_hw])
9448 || ([istarget powerpc*-*-*] && [check_effective_target_lp64]) } {
9455 # Return 1 if the target supports byte swap instructions.
9457 proc check_effective_target_bswap { } {
9458 return [check_cached_effective_target bswap {
9459 expr { [istarget aarch64*-*-*]
9460 || [istarget alpha*-*-*]
9461 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9462 || [istarget m68k-*-*]
9463 || [istarget powerpc*-*-*]
9464 || [istarget rs6000-*-*]
9465 || [istarget s390*-*-*]
9466 || ([istarget riscv*-*-*]
9467 && [check_no_compiler_messages_nocache riscv_zbb object {
9468 #if __riscv_zbb <= 0
9469 #error ZBB is not enabled
9473 || ([istarget arm*-*-*]
9474 && [check_no_compiler_messages_nocache arm_v6_or_later object {
9476 #error not armv6 or later
9482 # Return 1 if the target supports atomic operations on "int" and "long".
9484 proc check_effective_target_sync_int_long { } {
9485 # This is intentionally powerpc but not rs6000, rs6000 doesn't have the
9486 #
load-reserved/store
-conditional instructions.
9487 return [check_cached_effective_target sync_int_long
{
9488 expr
{ [istarget ia64
-*-*]
9489 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
9490 ||
[istarget aarch64
*-*-*]
9491 ||
[istarget alpha
*-*-*]
9492 ||
[istarget arm
*-*-linux
-*]
9493 ||
[istarget arm
*-*-uclinuxfdpiceabi
]
9494 ||
([istarget arm
*-*-*]
9495 && [check_effective_target_arm_acq_rel
])
9496 ||
[istarget bfin
*-*linux
*]
9497 ||
[istarget hppa
*-*linux
*]
9498 ||
[istarget s390
*-*-*]
9499 ||
[istarget powerpc
*-*-*]
9500 ||
[istarget cris
-*-*]
9501 ||
([istarget sparc
*-*-*] && [check_effective_target_sparc_v9
])
9502 ||
([istarget arc
*-*-*] && [check_effective_target_arc_atomic
])
9503 ||
[check_effective_target_mips_llsc
]
9504 ||
[istarget nvptx
*-*-*]
9508 #
Return 1 if the target supports atomic operations
on "int" and "long" on
9511 proc check_effective_target_sync_int_long_stack
{ } {
9512 return [check_cached_effective_target sync_int_long_stack
{
9513 expr
{ ![istarget nvptx
*-*-*]
9514 && [check_effective_target_sync_int_long
]
9518 #
Return 1 if the target supports atomic operations
on "char" and "short".
9520 proc check_effective_target_sync_char_short
{ } {
9521 # This is intentionally powerpc but not rs6000
, rs6000 doesn
't have the
9522 # load-reserved/store-conditional instructions.
9523 return [check_cached_effective_target sync_char_short {
9524 expr { [istarget aarch64*-*-*]
9525 || [istarget ia64-*-*]
9526 || [istarget i?86-*-*] || [istarget x86_64-*-*]
9527 || [istarget alpha*-*-*]
9528 || [istarget arm*-*-linux-*]
9529 || [istarget arm*-*-uclinuxfdpiceabi]
9530 || ([istarget arm*-*-*]
9531 && [check_effective_target_arm_acq_rel])
9532 || [istarget hppa*-*linux*]
9533 || [istarget s390*-*-*]
9534 || [istarget powerpc*-*-*]
9535 || [istarget cris-*-*]
9536 || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
9537 || ([istarget arc*-*-*] && [check_effective_target_arc_atomic])
9538 || [istarget loongarch*-*-*]
9539 || [check_effective_target_mips_llsc] }}]
9542 # Return 1 if thread_fence does not rely on __sync_synchronize
9545 proc check_effective_target_thread_fence {} {
9546 return [check_no_compiler_messages thread_fence executable {
9548 __atomic_thread_fence (__ATOMIC_SEQ_CST);
9554 # Return 1 if the target uses a ColdFire FPU.
9556 proc check_effective_target_coldfire_fpu { } {
9557 return [check_no_compiler_messages coldfire_fpu assembly {
9564 # Return true if this is a uClibc target.
9566 proc check_effective_target_uclibc {} {
9567 return [check_no_compiler_messages uclibc object {
9568 #include <features.h>
9569 #if !defined (__UCLIBC__)
9575 # Return true if this is a uclibc target and if the uclibc feature
9576 # described by __$feature__ is not present.
9578 proc check_missing_uclibc_feature {feature} {
9579 return [check_no_compiler_messages $feature object "
9580 #include <features.h>
9581 #if !defined (__UCLIBC) || defined (__${feature}__)
9587 # Return true if this is a Newlib target.
9589 proc check_effective_target_newlib {} {
9590 return [check_no_compiler_messages newlib object {
9595 # Return true if GCC was configured with --enable-newlib-nano-formatted-io
9596 proc check_effective_target_newlib_nano_io { } {
9597 return [check_configured_with "--enable-newlib-nano-formatted-io"]
9600 # Some newlib versions don't provide a frexpl and instead depend
9601 #
on frexp to implement long double conversions in their printf
-like
9602 # functions. This leads to broken results. Detect such versions here.
9604 proc check_effective_target_newlib_broken_long_double_io
{} {
9605 if { [is
-effective
-target newlib
] && ![is
-effective
-target frexpl
] } {
9611 #
Return true
if this is NOT a Bionic target.
9613 proc check_effective_target_non_bionic
{} {
9614 return [check_no_compiler_messages non_bionic object
{
9616 #
if defined
(__BIONIC__
)
9622 #
Return true
if this target has error.h header.
9624 proc check_effective_target_error_h
{} {
9625 return [check_no_compiler_messages error_h object
{
9630 #
Return true
if this target has tgmath.h header.
9632 proc check_effective_target_tgmath_h
{} {
9633 return [check_no_compiler_messages tgmath_h object
{
9638 #
Return true
if target
's libc supports complex functions.
9640 proc check_effective_target_libc_has_complex_functions {} {
9641 return [check_no_compiler_messages libc_has_complex_functions object {
9642 #include <complex.h>
9647 # (a) an error of a few ULP is expected in string to floating-point
9648 # conversion functions; and
9649 # (b) overflow is not always detected correctly by those functions.
9651 proc check_effective_target_lax_strtofp {} {
9652 # By default, assume that all uClibc targets suffer from this.
9653 return [check_effective_target_uclibc]
9656 # Return 1 if this is a target for which wcsftime is a dummy
9657 # function that always returns 0.
9659 proc check_effective_target_dummy_wcsftime {} {
9660 # By default, assume that all uClibc targets suffer from this.
9661 return [check_effective_target_uclibc]
9664 # Return 1 if constructors with initialization priority arguments are
9665 # supposed on this target.
9667 proc check_effective_target_init_priority {} {
9668 return [check_no_compiler_messages init_priority assembly "
9669 void f() __attribute__((constructor (1000)));
9674 # Return 1 if the target matches the effective target 'arg', 0 otherwise.
9675 # This can be used with any check_* proc that takes no argument and
9676 # returns only 1 or 0. It could be used with check_* procs that take
9677 # arguments with keywords that pass particular arguments.
9679 proc is-effective-target { arg } {
9682 if { ![info exists et_index] } {
9683 # Initialize the effective target index that is used in some
9684 # check_effective_target_* procs.
9687 if { [info procs check_effective_target_${arg}] != [list] } {
9688 set selected [check_effective_target_${arg}]
9691 "vmx_hw" { set selected [check_vmx_hw_available] }
9692 "vsx_hw" { set selected [check_vsx_hw_available] }
9693 "p8vector_hw" { set selected [check_p8vector_hw_available] }
9694 "p9vector_hw" { set selected [check_p9vector_hw_available] }
9695 "p9modulo_hw" { set selected [check_p9modulo_hw_available] }
9696 "power10_hw" { set selected [check_power10_hw_available] }
9697 "ppc_float128_sw" { set selected [check_ppc_float128_sw_available] }
9698 "ppc_float128_hw" { set selected [check_ppc_float128_hw_available] }
9699 "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] }
9700 "ppc_cpu_supports_hw" { set selected [check_ppc_cpu_supports_hw_available] }
9701 "ppc_mma_hw" { set selected [check_ppc_mma_hw_available] }
9702 "dfp_hw" { set selected [check_dfp_hw_available] }
9703 "htm_hw" { set selected [check_htm_hw_available] }
9704 "named_sections" { set selected [check_named_sections_available] }
9705 "gc_sections" { set selected [check_gc_sections_available] }
9706 "cxa_atexit" { set selected [check_cxa_atexit_available] }
9707 default { error "unknown effective target keyword `$arg'" }
9711 verbose
"is-effective-target: $arg $selected" 2
9715 #
Return 1 if the
argument is an effective
-target keyword
, 0 otherwise.
9717 proc is
-effective
-target
-keyword
{ arg } {
9718 if { [info procs check_effective_target_$
{arg}] != [list
] } {
9721 # These have different names
for their check_
* procs.
9723 "vmx_hw" { return 1 }
9724 "vsx_hw" { return 1 }
9725 "p8vector_hw" { return 1 }
9726 "p9vector_hw" { return 1 }
9727 "p9modulo_hw" { return 1 }
9728 "power10_hw" { return 1 }
9729 "ppc_float128_sw" { return 1 }
9730 "ppc_float128_hw" { return 1 }
9731 "ppc_recip_hw" { return 1 }
9732 "ppc_mma_hw" { return 1 }
9733 "dfp_hw" { return 1 }
9734 "htm_hw" { return 1 }
9735 "named_sections" { return 1 }
9736 "gc_sections" { return 1 }
9737 "cxa_atexit" { return 1 }
9738 "ppc_cpu_supports_hw" { return 1 }
9739 default
{ return 0 }
9744 #
Execute tests
for all targets in EFFECTIVE_TARGETS list.
Set et_index to
9745 # indicate what target is currently being processed. This is
for
9746 # the vectorizer tests
, e.g. vect_int
, to keep track what target supports
9749 proc et
-dg
-runtest
{ runtest testcases flags default
-extra
-flags
} {
9750 global dg
-do-what
-default
9751 global EFFECTIVE_TARGETS
9754 if { [llength $EFFECTIVE_TARGETS
] > 0 } {
9755 foreach target $EFFECTIVE_TARGETS
{
9756 set target_flags $flags
9757 set dg
-do-what
-default
compile
9758 set et_index
[lsearch
-exact $EFFECTIVE_TARGETS $target
]
9759 if { [info procs add_options_for_$
{target
}] != [list
] } {
9760 set target_flags
[add_options_for_$
{target
} "$flags"]
9762 if { [info procs check_effective_target_$
{target
}_runtime
]
9763 != [list
] && [check_effective_target_$
{target
}_runtime
] } {
9764 set dg
-do-what
-default run
9766 $runtest $testcases $target_flags $
{default
-extra
-flags
}
9770 $runtest $testcases $flags $
{default
-extra
-flags
}
9774 #
Return 1 if a target matches the target in EFFECTIVE_TARGETS at index
9775 # et_index
, 0 otherwise.
9777 proc et
-is
-effective
-target
{ target
} {
9778 global EFFECTIVE_TARGETS
9781 if { [info exists EFFECTIVE_TARGETS
] } {
9782 if { [llength $EFFECTIVE_TARGETS
] > $et_index
9783 && [lindex $EFFECTIVE_TARGETS $et_index
] == $target
} {
9789 return [check_effective_target_$
{target
}]
9793 #
Return 1 if target default to short enums
9795 proc check_effective_target_short_enums
{ } {
9796 return [check_no_compiler_messages short_enums assembly
{
9798 int s
[sizeof
(enum foo
) == 1 ?
1 : -1];
9802 #
Return 1 if target supports merging string constants at link time.
9804 proc check_effective_target_string_merging
{ } {
9805 return [check_no_messages_and_pattern string_merging \
9806 "rodata\\.str" assembly {
9807 const char
*var
= "String";
9811 #
Return 1 if target has the basic signed and unsigned types in
9812 #
<stdint.h
>, 0 otherwise. This will be obsolete when GCC ensures a
9813 # working
<stdint.h
> for all targets.
9815 proc check_effective_target_stdint_types
{ } {
9816 return [check_no_compiler_messages stdint_types assembly
{
9818 int8_t a
; int16_t b
; int32_t c
; int64_t d
;
9819 uint8_t e
; uint16_t f
; uint32_t g
; uint64_t h
;
9823 # Like check_effective_target_stdint_types
, but test what happens when
9824 #
-mbig
-endian is passed. This test only makes sense
on targets that
9825 # support
-mbig
-endian
; it will fail elsewhere.
9827 proc check_effective_target_stdint_types_mbig_endian
{ } {
9828 return [check_no_compiler_messages stdint_types_mbig_endian assembly
{
9830 int8_t a
; int16_t b
; int32_t c
; int64_t d
;
9831 uint8_t e
; uint16_t f
; uint32_t g
; uint64_t h
;
9835 #
Return 1 if target has the basic signed and unsigned types in
9836 #
<inttypes.h
>, 0 otherwise. This is
for tests that GCC
's notions of
9837 # these types agree with those in the header, as some systems have
9838 # only <inttypes.h>.
9840 proc check_effective_target_inttypes_types { } {
9841 return [check_no_compiler_messages inttypes_types assembly {
9842 #include <inttypes.h>
9843 int8_t a; int16_t b; int32_t c; int64_t d;
9844 uint8_t e; uint16_t f; uint32_t g; uint64_t h;
9848 # Return 1 if programs are intended to be run on a simulator
9849 # (i.e. slowly) rather than hardware (i.e. fast).
9851 proc check_effective_target_simulator { } {
9853 # All "src/sim" simulators set this one.
9854 if [board_info target exists is_simulator] {
9855 return [board_info target is_simulator]
9858 # The "sid" simulators don't
set that one
, but at least they
set
9860 if [board_info target
exists slow_simulator
] {
9861 return [board_info target slow_simulator
]
9867 #
Return 1 if programs are intended to be run
on hardware rather than
9870 proc check_effective_target_hw
{ } {
9872 # All
"src/sim" simulators set this one.
9873 if [board_info target
exists is_simulator
] {
9874 if [board_info target is_simulator
] {
9881 # The
"sid" simulators don't set that one, but at least they set
9883 if [board_info target
exists slow_simulator
] {
9884 if [board_info target slow_simulator
] {
9894 #
Return 1 if the target is a VxWorks kernel.
9896 proc check_effective_target_vxworks_kernel
{ } {
9897 return [check_no_compiler_messages vxworks_kernel assembly
{
9898 #
if !defined __vxworks || defined __RTP__
9904 #
Return 1 if the target is a VxWorks RTP.
9906 proc check_effective_target_vxworks_rtp
{ } {
9907 return [check_no_compiler_messages vxworks_rtp assembly
{
9908 #
if !defined __vxworks ||
!defined __RTP__
9914 #
Return 1 if the target is expected to provide wide character support.
9916 proc check_effective_target_wchar
{ } {
9917 if {[check_missing_uclibc_feature UCLIBC_HAS_WCHAR
]} {
9920 return [check_no_compiler_messages wchar assembly
{
9925 #
Return 1 if the target has
<pthread.h
>.
9927 proc check_effective_target_pthread_h
{ } {
9928 return [check_no_compiler_messages pthread_h assembly
{
9929 #
include <pthread.h
>
9933 #
Return 1 if the target can truncate a file from a file
-descriptor
,
9934 # as used by libgfortran
/io
/unix.c
:fd_truncate
; i.e. ftruncate or
9935 # chsize. We test
for a trivially functional truncation
; no stubs.
9936 # As libgfortran uses _FILE_OFFSET_BITS
64, we
do too
; it
'll cause a
9937 # different function to be used.
9939 proc check_effective_target_fd_truncate { } {
9941 #define _FILE_OFFSET_BITS 64
9948 FILE *f = fopen ("tst.tmp", "wb");
9950 const char t[] = "test writing more than ten characters";
9954 write (fd, t, sizeof (t) - 1);
9956 if (ftruncate (fd, 10) != 0)
9965 f = fopen ("tst.tmp", "rb");
9966 if (fread (s, 1, sizeof (s), f) != 10 || strncmp (s, t, 10) != 0)
9974 if { [check_runtime ftruncate $prog] } {
9978 regsub "ftruncate" $prog "chsize" prog
9979 return [check_runtime chsize $prog]
9982 # Add to FLAGS all the target-specific flags needed to enable
9983 # full IEEE compliance mode.
9985 proc add_options_for_ieee { flags } {
9986 if { [istarget alpha*-*-*]
9987 || [istarget sh*-*-*] } {
9988 return "$flags -mieee"
9990 if { [istarget rx-*-*] } {
9991 return "$flags -mnofpu"
9996 if {![info exists flags_to_postpone]} {
9997 set flags_to_postpone ""
10000 # Add to FLAGS the flags needed to enable functions to bind locally
10001 # when using pic/PIC passes in the testsuite.
10002 proc add_options_for_bind_pic_locally { flags } {
10003 global flags_to_postpone
10005 # Instead of returning 'flags
' with the -fPIE or -fpie appended, we save it
10006 # in 'flags_to_postpone
' and append it later in gcc_target_compile procedure in
10007 # order to make sure that the multilib_flags doesn't override this.
10009 if {[check_no_compiler_messages using_pic2 assembly
{
10011 #error __PIC__
!= 2
10014 set flags_to_postpone
"-fPIE"
10017 if {[check_no_compiler_messages using_pic1 assembly
{
10019 #error __PIC__
!= 1
10022 set flags_to_postpone
"-fpie"
10028 # Add to FLAGS the flags needed to enable
64-bit vectors.
10030 proc add_options_for_double_vectors
{ flags
} {
10031 if [is
-effective
-target arm_neon_ok
] {
10032 return "$flags -mvectorize-with-neon-double"
10038 # Add to FLAGS the flags needed to
define the STACK_SIZE macro.
10040 proc add_options_for_stack_size
{ flags
} {
10041 if [is
-effective
-target stack_size
] {
10042 set stack_size
[dg
-effective
-target
-value stack_size
]
10043 return "$flags -DSTACK_SIZE=$stack_size"
10049 #
Return 1 if the target provides a full C99 runtime.
10051 proc check_effective_target_c99_runtime
{ } {
10052 return [check_cached_effective_target c99_runtime
{
10055 set file
[open
"$srcdir/gcc.dg/builtins-config.h"]
10056 set contents
[read $file
]
10059 #ifndef HAVE_C99_RUNTIME
10060 #error
!HAVE_C99_RUNTIME
10063 check_no_compiler_messages_nocache c99_runtime assembly $contents
10067 #
Return 1 if the target supports DWARF CFI directives.
10069 proc check_effective_target_cfi
{ } {
10070 return [check_no_compiler_messages cfi assembly
{
10071 #ifdef __GCC_HAVE_DWARF2_CFI_ASM
10079 #
Return 1 if the target provides the D runtime.
10081 proc check_effective_target_d_runtime
{ } {
10082 return [check_no_compiler_messages d_runtime executable
{
10086 extern
(C
) int main
() {
10092 #
Return 1 if the target provides the D standard library.
10094 proc check_effective_target_d_runtime_has_std_library
{ } {
10095 return [check_no_compiler_messages d_runtime_has_std_library executable
{
10099 extern
(C
) int main
() {
10101 real function
(real
) pcos
= &cos;
10107 #
Return 1 if target wchar_t is at least
4 bytes.
10109 proc check_effective_target_4byte_wchar_t
{ } {
10110 return [check_no_compiler_messages
4byte_wchar_t object
{
10111 int dummy
[sizeof
(__WCHAR_TYPE__
) >= 4 ?
1 : -1];
10115 #
Return 1 if the target supports automatic stack alignment.
10117 proc check_effective_target_automatic_stack_alignment
{ } {
10118 # Ordinarily x86 supports automatic stack alignment ...
10119 if { [istarget i?
86*-*-*] ||
[istarget x86_64
-*-*] } then {
10120 if { [istarget
*-*-mingw
*] ||
[istarget
*-*-cygwin
*] } {
10121 # ... except Win64 SEH doesn
't. Succeed for Win32 though.
10122 return [check_effective_target_ilp32];
10129 # Return true if we are compiling for AVX target.
10131 proc check_avx_available { } {
10132 if { [check_no_compiler_messages avx_available assembly {
10142 # Return true if we are compiling for AVX2 target.
10144 proc check_avx2_available { } {
10145 if { [check_no_compiler_messages avx2_available assembly {
10155 # Return true if we are compiling for SSSE3 target.
10157 proc check_ssse3_available { } {
10158 if { [check_no_compiler_messages sse3a_available assembly {
10168 # Return true if 32- and 16-bytes vectors are available.
10170 proc check_effective_target_vect_sizes_32B_16B { } {
10171 return [expr { [available_vector_sizes] == [list 256 128] }]
10174 # Return true if 16- and 8-bytes vectors are available.
10176 proc check_effective_target_vect_sizes_16B_8B { } {
10177 if { [check_avx_available]
10178 || [is-effective-target arm_neon]
10179 || [istarget aarch64*-*-*]
10180 || [check_effective_target_riscv_v] } {
10188 # Return true if 128-bits vectors are preferred even if 256-bits vectors
10191 proc check_prefer_avx128 { } {
10192 if ![check_avx_available] {
10195 return [check_no_messages_and_pattern avx_explicit "xmm" assembly {
10196 float a[1024],b[1024],c[1024];
10197 void foo (void) { int i; for (i = 0; i < 1024; i++) a[i]=b[i]+c[i];}
10198 } "-O2 -ftree-vectorize"]
10202 # Return 1 if avx512fp16 instructions can be compiled.
10204 proc check_effective_target_avx512fp16 { } {
10205 return [check_no_compiler_messages avx512fp16 object {
10208 asm volatile ("vmovw %edi, %xmm0");
10209 asm volatile ("vfcmulcph %xmm1, %xmm2, %xmm3{%k1}");
10211 } "-O2 -mavx512fp16" ]
10214 # Return 1 if avx512f instructions can be compiled.
10216 proc check_effective_target_avx512f { } {
10217 return [check_no_compiler_messages avx512f object {
10218 typedef double __m512d __attribute__ ((__vector_size__ (64)));
10219 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10221 __m512d _mm512_add (__m512d a)
10223 return __builtin_ia32_addpd512_mask (a, a, a, 1, 4);
10226 __m128d _mm128_add (__m128d a)
10228 return __builtin_ia32_addsd_round (a, a, 8);
10231 __m128d _mm128_getmant (__m128d a)
10233 return __builtin_ia32_getmantsd_round (a, a, 0, 8);
10235 } "-O2 -mavx512f" ]
10238 # Return 1 if avx instructions can be compiled.
10240 proc check_effective_target_avx { } {
10241 if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } {
10244 return [check_no_compiler_messages avx object {
10245 void _mm256_zeroall (void)
10247 __builtin_ia32_vzeroall ();
10252 # Return 1 if avx2 instructions can be compiled.
10253 proc check_effective_target_avx2 { } {
10254 return [check_no_compiler_messages avx2 object {
10255 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10257 mm256_is32_andnotsi256 (__v4di __X, __v4di __Y)
10259 return __builtin_ia32_andnotsi256 (__X, __Y);
10264 # Return 1 if avxvnni instructions can be compiled.
10265 proc check_effective_target_avxvnni { } {
10266 return [check_no_compiler_messages avxvnni object {
10267 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10269 _mm256_dpbusd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10271 return __builtin_ia32_vpdpbusd_v8si (__A, __B, __C);
10276 # Return 1 if avxifma instructions can be compiled.
10277 proc check_effective_target_avxifma { } {
10278 return [check_no_compiler_messages avxifma object {
10279 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10281 _mm256_maddlo_epu64 (__v4di __A, __v4di __B, __v4di __C)
10283 return __builtin_ia32_vpmadd52luq256 (__A, __B, __C);
10285 } "-O0 -mavxifma" ]
10288 # Return 1 if avxvnniint8 instructions can be compiled.
10289 proc check_effective_target_avxvnniint8 { } {
10290 return [check_no_compiler_messages avxvnniint8 object {
10291 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10293 _mm256_dpbssd_epi32 (__v8si __A, __v8si __B, __v8si __C)
10295 return __builtin_ia32_vpdpbssd256 (__A, __B, __C);
10297 } "-O0 -mavxvnniint8" ]
10300 # Return 1 if avxneconvert instructions can be compiled.
10301 proc check_effective_target_avxneconvert { } {
10302 return [check_no_compiler_messages avxneconvert object {
10303 typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
10305 _mm_bcstnebf16_ps (const void *__P)
10307 return (__m128) __builtin_ia32_vbcstnebf162ps128 ((const __bf16 *) __P);
10309 } "-O0 -mavxneconvert" ]
10312 # Return 1 if cmpccxadd instructions can be compiled.
10313 proc check_effective_target_cmpccxadd { } {
10314 return [check_no_compiler_messages cmpccxadd object {
10315 int _cmpccxadd_epi32 (int *__A, int __B, int __C, const int __D)
10317 return (int)__builtin_ia32_cmpccxadd (__A, __B, __C, 1);
10322 # Return 1 if raoint instructions can be compiled.
10323 proc check_effective_target_raoint { } {
10324 return [check_no_compiler_messages raoint object {
10326 _aadd_si32 (int *__A, int __B)
10328 return __builtin_ia32_aadd32((int *)__A, __B);
10333 # Return 1 if amx-complex instructions can be compiled.
10334 proc check_effective_target_amx_complex { } {
10335 return [check_no_compiler_messages amx_complex object {
10339 __asm__ volatile ("tcmmimfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
10341 } "-mamx-complex" ]
10344 # Return 1 if avxvnniint16 instructions can be compiled.
10345 proc check_effective_target_avxvnniint16 { } {
10346 return [check_no_compiler_messages avxvnniint16 object {
10347 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10349 _mm256_dpwsud_avx_epi32 (__v8si __A, __v8si __B, __v8si __C)
10351 return __builtin_ia32_vpdpwsud256 (__A, __B, __C);
10353 } "-O0 -mavxvnniint16" ]
10356 # Return 1 if sm3 instructions can be compiled.
10357 proc check_effective_target_sm3 { } {
10358 return [check_no_compiler_messages sm3 object {
10359 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10360 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10362 _mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C)
10364 return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A,
10371 # Return 1 if sha512 instructions can be compiled.
10372 proc check_effective_target_sha512 { } {
10373 return [check_no_compiler_messages sha512 object {
10374 typedef long long __m256i __attribute__ ((__vector_size__ (32)));
10375 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10377 _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B)
10379 return (__m256i) __builtin_ia32_vsha512msg2 ((__v4di) __A,
10385 # Return 1 if sm4 instructions can be compiled.
10386 proc check_effective_target_sm4 { } {
10387 return [check_no_compiler_messages sm4 object {
10388 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10389 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10391 _mm_sm4key4_epi32 (__m128i __A, __m128i __B)
10393 return (__m128i) __builtin_ia32_vsm4key4128 ((__v4si) __A,
10399 proc check_effective_target_apxf { } {
10400 return [check_no_compiler_messages apxf object {
10404 __asm__ volatile ("add\t%%r16, %%r31" ::);
10409 # Return 1 if sse instructions can be compiled.
10410 proc check_effective_target_sse { } {
10411 return [check_no_compiler_messages sse object {
10414 __builtin_ia32_stmxcsr ();
10420 # Return 1 if sse2 instructions can be compiled.
10421 proc check_effective_target_sse2 { } {
10422 return [check_no_compiler_messages sse2 object {
10423 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10425 __m128i _mm_srli_si128 (__m128i __A, int __N)
10427 return (__m128i)__builtin_ia32_psrldqi128 (__A, 8);
10432 # Return 1 if sse4.1 instructions can be compiled.
10433 proc check_effective_target_sse4 { } {
10434 return [check_no_compiler_messages sse4.1 object {
10435 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10436 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10438 __m128i _mm_mullo_epi32 (__m128i __X, __m128i __Y)
10440 return (__m128i) __builtin_ia32_pmulld128 ((__v4si)__X,
10446 # Return 1 if F16C instructions can be compiled.
10448 proc check_effective_target_f16c { } {
10449 return [check_no_compiler_messages f16c object {
10450 #include "immintrin.h"
10452 foo (unsigned short val)
10454 return _cvtsh_ss (val);
10459 proc check_effective_target_ms_hook_prologue { } {
10460 if { [check_no_compiler_messages ms_hook_prologue object {
10461 void __attribute__ ((__ms_hook_prologue__)) foo ();
10469 # Return 1 if 3dnow instructions can be compiled.
10470 proc check_effective_target_3dnow { } {
10471 return [check_no_compiler_messages 3dnow object {
10472 typedef int __m64 __attribute__ ((__vector_size__ (8)));
10473 typedef float __v2sf __attribute__ ((__vector_size__ (8)));
10475 __m64 _m_pfadd (__m64 __A, __m64 __B)
10477 return (__m64) __builtin_ia32_pfadd ((__v2sf)__A, (__v2sf)__B);
10482 # Return 1 if sse3 instructions can be compiled.
10483 proc check_effective_target_sse3 { } {
10484 return [check_no_compiler_messages sse3 object {
10485 typedef double __m128d __attribute__ ((__vector_size__ (16)));
10486 typedef double __v2df __attribute__ ((__vector_size__ (16)));
10488 __m128d _mm_addsub_pd (__m128d __X, __m128d __Y)
10490 return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y);
10495 # Return 1 if ssse3 instructions can be compiled.
10496 proc check_effective_target_ssse3 { } {
10497 return [check_no_compiler_messages ssse3 object {
10498 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10499 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10501 __m128i _mm_abs_epi32 (__m128i __X)
10503 return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X);
10508 # Return 1 if aes instructions can be compiled.
10509 proc check_effective_target_aes { } {
10510 return [check_no_compiler_messages aes object {
10511 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10512 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10514 __m128i _mm_aesimc_si128 (__m128i __X)
10516 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10521 # Return 1 if vaes instructions can be compiled.
10522 proc check_effective_target_vaes { } {
10523 return [check_no_compiler_messages vaes object {
10524 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10525 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10527 __m128i _mm_aesimc_si128 (__m128i __X)
10529 return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
10531 } "-O2 -maes -mavx" ]
10534 # Return 1 if pclmul instructions can be compiled.
10535 proc check_effective_target_pclmul { } {
10536 return [check_no_compiler_messages pclmul object {
10537 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10538 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10540 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10542 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10549 # Return 1 if vpclmul instructions can be compiled.
10550 proc check_effective_target_vpclmul { } {
10551 return [check_no_compiler_messages vpclmul object {
10552 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10553 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10555 __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
10557 return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
10561 } "-O2 -mpclmul -mavx" ]
10564 # Return 1 if sse4a instructions can be compiled.
10565 proc check_effective_target_sse4a { } {
10566 return [check_no_compiler_messages sse4a object {
10567 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10568 typedef long long __v2di __attribute__ ((__vector_size__ (16)));
10570 __m128i _mm_insert_si64 (__m128i __X,__m128i __Y)
10572 return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y);
10577 # Return 1 if fma4 instructions can be compiled.
10578 proc check_effective_target_fma4 { } {
10579 return [check_no_compiler_messages fma4 object {
10580 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10581 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10582 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10584 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10591 # Return 1 if fma instructions can be compiled.
10592 proc check_effective_target_fma { } {
10593 return [check_no_compiler_messages fma object {
10594 typedef float __m128 __attribute__ ((__vector_size__ (16)));
10595 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10596 __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
10598 return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
10605 # Return 1 if xop instructions can be compiled.
10606 proc check_effective_target_xop { } {
10607 return [check_no_compiler_messages xop object {
10608 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10609 typedef short __v8hi __attribute__ ((__vector_size__ (16)));
10610 __m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C)
10612 return (__m128i) __builtin_ia32_vpmacssww ((__v8hi)__A,
10619 # Return 1 if lzcnt instruction can be compiled.
10620 proc check_effective_target_lzcnt { } {
10621 return [check_no_compiler_messages lzcnt object {
10622 unsigned short _lzcnt (unsigned short __X)
10624 return __builtin_clzs (__X);
10629 # Return 1 if bmi instructions can be compiled.
10630 proc check_effective_target_bmi { } {
10631 return [check_no_compiler_messages bmi object {
10632 unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y)
10634 return __builtin_ia32_bextr_u32 (__X, __Y);
10639 # Return 1 if ADX instructions can be compiled.
10640 proc check_effective_target_adx { } {
10641 return [check_no_compiler_messages adx object {
10643 _adxcarry_u32 (unsigned char __CF, unsigned int __X,
10644 unsigned int __Y, unsigned int *__P)
10646 return __builtin_ia32_addcarryx_u32 (__CF, __X, __Y, __P);
10651 # Return 1 if rtm instructions can be compiled.
10652 proc check_effective_target_rtm { } {
10653 return [check_no_compiler_messages rtm object {
10657 return __builtin_ia32_xend ();
10662 # Return 1 if avx512vl instructions can be compiled.
10663 proc check_effective_target_avx512vl { } {
10664 return [check_no_compiler_messages avx512vl object {
10665 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10667 mm256_and_epi64 (__v4di __X, __v4di __Y)
10670 return __builtin_ia32_pandq256_mask (__X, __Y, __W, -1);
10675 # Return 1 if avx512cd instructions can be compiled.
10676 proc check_effective_target_avx512cd { } {
10677 return [check_no_compiler_messages avx512cd_trans object {
10678 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10680 _mm512_conflict_epi64 (__v8di __W, __v8di __A)
10682 return (__v8di) __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A,
10686 } "-Wno-psabi -mavx512cd" ]
10689 # Return 1 if avx512er instructions can be compiled.
10690 proc check_effective_target_avx512er { } {
10691 return [check_no_compiler_messages avx512er_trans object {
10692 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
10694 mm512_exp2a23_ps (__v16sf __X)
10696 return __builtin_ia32_exp2ps_mask (__X, __X, -1, 4);
10698 } "-Wno-psabi -mavx512er" ]
10701 # Return 1 if sha instructions can be compiled.
10702 proc check_effective_target_sha { } {
10703 return [check_no_compiler_messages sha object {
10704 typedef long long __m128i __attribute__ ((__vector_size__ (16)));
10705 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10707 __m128i _mm_sha1msg1_epu32 (__m128i __X, __m128i __Y)
10709 return (__m128i) __builtin_ia32_sha1msg1 ((__v4si)__X,
10715 # Return 1 if avx512dq instructions can be compiled.
10716 proc check_effective_target_avx512dq { } {
10717 return [check_no_compiler_messages avx512dq object {
10718 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10720 _mm512_mask_mullo_epi64 (__v8di __W, __v8di __A, __v8di __B)
10722 return (__v8di) __builtin_ia32_pmullq512_mask ((__v8di) __A,
10730 # Return 1 if avx512bw instructions can be compiled.
10731 proc check_effective_target_avx512bw { } {
10732 return [check_no_compiler_messages avx512bw object {
10733 typedef short __v32hi __attribute__ ((__vector_size__ (64)));
10735 _mm512_mask_mulhrs_epi16 (__v32hi __W, __v32hi __A, __v32hi __B)
10737 return (__v32hi) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A,
10745 # Return 1 if -Wa,-march=+noavx512bw is supported.
10746 proc check_effective_target_assembler_march_noavx512bw {} {
10747 if { [istarget i?86*-*-*] || [istarget x86_64*-*-*] } {
10748 return [check_no_compiler_messages assembler_march_noavx512bw object {
10750 } "-mno-avx512bw -Wa,-march=+noavx512bw"]
10755 # Return 1 if avx512vp2intersect instructions can be compiled.
10756 proc check_effective_target_avx512vp2intersect { } {
10757 return [check_no_compiler_messages avx512vp2intersect object {
10758 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10759 typedef short __mmask16;
10761 _mm512_2intersect_epi32 (__v16si __A, __v16si __B, __mmask16 *__U,
10764 __builtin_ia32_2intersectd512 (__U, __M, (__v16si) __A, (__v16si) __B);
10766 } "-mavx512vp2intersect" ]
10769 # Return 1 if avx512ifma instructions can be compiled.
10770 proc check_effective_target_avx512ifma { } {
10771 return [check_no_compiler_messages avx512ifma object {
10772 typedef long long __v8di __attribute__ ((__vector_size__ (64)));
10774 _mm512_madd52lo_epu64 (__v8di __X, __v8di __Y, __v8di __Z)
10776 return (__v8di) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __X,
10784 # Return 1 if avx512vbmi instructions can be compiled.
10785 proc check_effective_target_avx512vbmi { } {
10786 return [check_no_compiler_messages avx512vbmi object {
10787 typedef char __v64qi __attribute__ ((__vector_size__ (64)));
10789 _mm512_multishift_epi64_epi8 (__v64qi __X, __v64qi __Y)
10791 return (__v64qi) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X,
10799 # Return 1 if avx512_4fmaps instructions can be compiled.
10800 proc check_effective_target_avx5124fmaps { } {
10801 return [check_no_compiler_messages avx5124fmaps object {
10802 typedef float __v16sf __attribute__ ((__vector_size__ (64)));
10803 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
10806 _mm512_mask_4fmadd_ps (__v16sf __DEST, __v16sf __A, __v16sf __B, __v16sf __C,
10807 __v16sf __D, __v16sf __E, __v4sf *__F)
10809 return (__v16sf) __builtin_ia32_4fmaddps_mask ((__v16sf) __A,
10814 (const __v4sf *) __F,
10818 } "-mavx5124fmaps" ]
10821 # Return 1 if avx512_4vnniw instructions can be compiled.
10822 proc check_effective_target_avx5124vnniw { } {
10823 return [check_no_compiler_messages avx5124vnniw object {
10824 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10825 typedef int __v4si __attribute__ ((__vector_size__ (16)));
10828 _mm512_4dpwssd_epi32 (__v16si __A, __v16si __B, __v16si __C,
10829 __v16si __D, __v16si __E, __v4si *__F)
10831 return (__v16si) __builtin_ia32_vp4dpwssd ((__v16si) __B,
10836 (const __v4si *) __F);
10838 } "-mavx5124vnniw" ]
10841 # Return 1 if avx512_vpopcntdq instructions can be compiled.
10842 proc check_effective_target_avx512vpopcntdq { } {
10843 return [check_no_compiler_messages avx512vpopcntdq object {
10844 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10847 _mm512_popcnt_epi32 (__v16si __A)
10849 return (__v16si) __builtin_ia32_vpopcountd_v16si ((__v16si) __A);
10851 } "-mavx512vpopcntdq" ]
10854 # Return 1 if 128 or 256-bit avx512_vpopcntdq instructions can be compiled.
10855 proc check_effective_target_avx512vpopcntdqvl { } {
10856 return [check_no_compiler_messages avx512vpopcntdqvl object {
10857 typedef int __v8si __attribute__ ((__vector_size__ (32)));
10860 _mm256_popcnt_epi32 (__v8si __A)
10862 return (__v8si) __builtin_ia32_vpopcountd_v8si ((__v8si) __A);
10864 } "-mavx512vpopcntdq -mavx512vl" ]
10867 # Return 1 if gfni instructions can be compiled.
10868 proc check_effective_target_gfni { } {
10869 return [check_no_compiler_messages gfni object {
10870 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
10873 _mm_gf2p8affineinv_epi64_epi8 (__v16qi __A, __v16qi __B, const int __C)
10875 return (__v16qi) __builtin_ia32_vgf2p8affineinvqb_v16qi ((__v16qi) __A,
10882 # Return 1 if avx512vbmi2 instructions can be compiled.
10883 proc check_effective_target_avx512vbmi2 { } {
10884 return [check_no_compiler_messages avx512vbmi2 object {
10885 typedef char __v16qi __attribute__ ((__vector_size__ (16)));
10886 typedef unsigned long long __mmask16;
10889 _mm_mask_compress_epi8 (__v16qi __A, __mmask16 __B, __v16qi __C)
10891 return (__v16qi) __builtin_ia32_compressqi128_mask((__v16qi)__C,
10895 } "-mavx512vbmi2 -mavx512vl" ]
10898 # Return 1 if avx512vbmi2 instructions can be compiled.
10899 proc check_effective_target_avx512vnni { } {
10900 return [check_no_compiler_messages avx512vnni object {
10901 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10904 _mm_mask_compress_epi8 (__v16si __A, __v16si __B, __v16si __C)
10906 return (__v16si) __builtin_ia32_vpdpbusd_v16si ((__v16si)__A,
10910 } "-mavx512vnni -mavx512f" ]
10913 # Return 1 if vaes instructions can be compiled.
10914 proc check_effective_target_avx512vaes { } {
10915 return [check_no_compiler_messages avx512vaes object {
10917 typedef int __v16si __attribute__ ((__vector_size__ (64)));
10920 _mm256_aesdec_epi128 (__v32qi __A, __v32qi __B)
10922 return (__v32qi)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
10927 # Return 1 if amx-tile instructions can be compiled.
10928 proc check_effective_target_amx_tile { } {
10929 return [check_no_compiler_messages amx_tile object {
10933 __asm__ volatile ("tilerelease" ::);
10938 # Return 1 if amx-int8 instructions can be compiled.
10939 proc check_effective_target_amx_int8 { } {
10940 return [check_no_compiler_messages amx_int8 object {
10944 __asm__ volatile ("tdpbssd\t%%tmm1, %%tmm2, %%tmm3" ::);
10949 # Return 1 if amx-bf16 instructions can be compiled.
10950 proc check_effective_target_amx_bf16 { } {
10951 return [check_no_compiler_messages amx_bf16 object {
10955 __asm__ volatile ("tdpbf16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
10960 # Return 1 if amx-fp16 instructions can be compiled.
10961 proc check_effective_target_amx_fp16 { } {
10962 return [check_no_compiler_messages amx_fp16 object {
10966 __asm__ volatile ("tdpfp16ps\t%%tmm1, %%tmm2, %%tmm3" ::);
10971 # Return 1 if vpclmulqdq instructions can be compiled.
10972 proc check_effective_target_vpclmulqdq { } {
10973 return [check_no_compiler_messages vpclmulqdq object {
10974 typedef long long __v4di __attribute__ ((__vector_size__ (32)));
10977 _mm256_clmulepi64_epi128 (__v4di __A, __v4di __B)
10979 return (__v4di) __builtin_ia32_vpclmulqdq_v4di (__A, __B, 0);
10981 } "-mvpclmulqdq -mavx512vl" ]
10984 # Return 1 if avx512_bitalg instructions can be compiled.
10985 proc check_effective_target_avx512bitalg { } {
10986 return [check_no_compiler_messages avx512bitalg object {
10987 typedef short int __v32hi __attribute__ ((__vector_size__ (64)));
10990 _mm512_popcnt_epi16 (__v32hi __A)
10992 return (__v32hi) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A);
10994 } "-mavx512bitalg" ]
10997 # Return 1 if C wchar_t type is compatible with char16_t.
10999 proc check_effective_target_wchar_t_char16_t_compatible { } {
11000 return [check_no_compiler_messages wchar_t_char16_t object {
11002 __CHAR16_TYPE__ *p16 = &wc;
11003 char t[(((__CHAR16_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11007 # Return 1 if C wchar_t type is compatible with char32_t.
11009 proc check_effective_target_wchar_t_char32_t_compatible { } {
11010 return [check_no_compiler_messages wchar_t_char32_t object {
11012 __CHAR32_TYPE__ *p32 = &wc;
11013 char t[(((__CHAR32_TYPE__) -1) < 0 == ((__WCHAR_TYPE__) -1) < 0) ? 1 : -1];
11017 # Return 1 if pow10 function exists.
11019 proc check_effective_target_pow10 { } {
11020 return [check_runtime pow10 {
11030 # Return 1 if frexpl function exists.
11032 proc check_effective_target_frexpl { } {
11033 return [check_runtime frexpl {
11038 x = frexpl (5.0, &y);
11045 # Return 1 if issignaling function exists.
11046 proc check_effective_target_issignaling {} {
11047 return [check_runtime issignaling {
11048 #define _GNU_SOURCE
11052 return issignaling (0.0);
11057 # Return 1 if current options generate DFP instructions, 0 otherwise.
11058 proc check_effective_target_hard_dfp {} {
11059 return [check_no_messages_and_pattern hard_dfp "!adddd3" assembly {
11060 typedef float d64 __attribute__((mode(DD)));
11062 void foo (void) { z = x + y; }
11066 # Return 1 if string.h and wchar.h headers provide C++ requires overloads
11067 # for strchr etc. functions.
11069 proc check_effective_target_correct_iso_cpp_string_wchar_protos { } {
11070 return [check_no_compiler_messages correct_iso_cpp_string_wchar_protos assembly {
11071 #include <string.h>
11073 #if !defined(__cplusplus) \
11074 || !defined(__CORRECT_ISO_CPP_STRING_H_PROTO) \
11075 || !defined(__CORRECT_ISO_CPP_WCHAR_H_PROTO)
11076 ISO C++ correct string.h and wchar.h protos not supported.
11083 # Return 1 if GNU as is used.
11085 proc check_effective_target_gas { } {
11086 global use_gas_saved
11089 if {![info exists use_gas_saved]} {
11090 # Check if the as used by gcc is GNU as.
11091 set options [list "additional_flags=-print-prog-name=as"]
11092 set gcc_as [lindex [${tool}_target_compile "" "" "none" $options] 0]
11093 # Provide /dev/null as input, otherwise gas times out reading from
11095 set status [remote_exec host "$gcc_as" "-v /dev/null"]
11096 set as_output [lindex $status 1]
11097 if { [ string first "GNU" $as_output ] >= 0 } {
11098 # Some Darwin versions have an assembler which is based on an old
11099 # version of GAS (and reports GNU assembler in its -v output) but
11100 # but doesn't support many of the modern GAS features.
11101 if { [ string first
"cctools" $as_output ] >= 0 } {
11102 set use_gas_saved
0
11104 set use_gas_saved
1
11107 set use_gas_saved
0
11110 return $use_gas_saved
11113 #
Return 1 if GNU
ld is used.
11115 proc check_effective_target_gld
{ } {
11116 global use_gld_saved
11119 if {![info exists use_gld_saved
]} {
11120 # Check
if the
ld used by gcc is GNU
ld.
11121 set options
[list
"additional_flags=-print-prog-name=ld"]
11122 set gcc_ld
[lindex
[$
{tool
}_target_compile
"" "" "none" $options] 0]
11123 set status [remote_exec host
"$gcc_ld" "--version"]
11124 set ld_output
[lindex $
status 1]
11125 if { [ string first
"GNU" $ld_output ] >= 0 } {
11126 set use_gld_saved
1
11128 set use_gld_saved
0
11131 return $use_gld_saved
11134 #
Return 1 if the compiler has been configure with link
-time optimization
11137 proc check_effective_target_lto
{ } {
11138 if { [istarget
*-*-vxworks
*] } {
11139 # No LTO
on VxWorks
, with kernel modules
11140 # built with partial links
11143 if { [istarget nvptx
-*-*]
11144 ||
[istarget amdgcn
-*-*] } {
11147 return [check_no_compiler_messages lto object
{
11148 void foo
(void
) { }
11152 #
Return 1 if the compiler and linker support incremental link
-time
11155 proc check_effective_target_lto_incremental
{ } {
11156 if ![check_effective_target_lto
] {
11159 return [check_no_compiler_messages lto_incremental executable
{
11160 int main
() { return 0; }
11161 } "-flto -r -nostdlib"]
11164 #
Return 1 if the compiler has been configured with analyzer support.
11166 proc check_effective_target_analyzer
{ } {
11167 return [check_no_compiler_messages analyzer object
{
11168 void foo
(void
) { }
11172 #
Return 1 if -mx32
-maddress
-mode=short can
compile, 0 otherwise.
11174 proc check_effective_target_maybe_x32
{ } {
11175 return [check_no_compiler_messages maybe_x32 object
{
11177 } "-mx32 -maddress-mode=short"]
11180 #
Return 1 if this target supports the
-fsplit
-stack option
, 0
11183 proc check_effective_target_split_stack
{} {
11184 return [check_no_compiler_messages split_stack object
{
11185 void foo
(void
) { }
11189 #
Return 1 if this target supports the
-masm
=intel option
, 0
11192 proc check_effective_target_masm_intel
{} {
11193 return [check_no_compiler_messages masm_intel object
{
11194 extern void abort
(void
);
11198 #
Return 1 if the language
for the compiler under test is C.
11200 proc check_effective_target_c
{ } {
11202 if [string match $tool
"gcc"] {
11208 #
Return 1 if the language
for the compiler under test is C
++.
11210 proc check_effective_target_c
++ { } {
11212 if { [string match $tool
"g++"] || [string match $tool "libstdc++"] } {
11218 set cxx_default
"c++17"
11219 # Check whether the current active language standard supports the features
11220 # of C
++11/C
++14 by checking
for the presence of one of the
-std flags.
11221 # This assumes that the default
for the compiler is $cxx_default
, and that
11222 # there will never be multiple
-std
= arguments
on the command line.
11223 proc check_effective_target_c
++11_only
{ } {
11225 if ![check_effective_target_c
++] {
11228 if [check
-flags
{ { } { } { -std
=c
++0x
-std
=gnu
++0x
-std
=c
++11 -std
=gnu
++11 } }] {
11231 if { $cxx_default
== "c++11" && [check-flags { { } { } { } { -std=* } }] } {
11236 proc check_effective_target_c
++11 { } {
11237 if [check_effective_target_c
++11_only
] {
11240 return [check_effective_target_c
++14]
11242 proc check_effective_target_c
++11_down
{ } {
11243 if ![check_effective_target_c
++] {
11246 return [expr
![check_effective_target_c
++14] ]
11249 proc check_effective_target_c
++14_only
{ } {
11251 if ![check_effective_target_c
++] {
11254 if [check
-flags
{ { } { } { -std
=c
++14 -std
=gnu
++14 -std
=c
++14 -std
=gnu
++14 } }] {
11257 if { $cxx_default
== "c++14" && [check-flags { { } { } { } { -std=* } }] } {
11263 proc check_effective_target_c
++14 { } {
11264 if [check_effective_target_c
++14_only
] {
11267 return [check_effective_target_c
++17]
11269 proc check_effective_target_c
++14_down
{ } {
11270 if ![check_effective_target_c
++] {
11273 return [expr
![check_effective_target_c
++17] ]
11276 proc check_effective_target_c
++98_only
{ } {
11278 if ![check_effective_target_c
++] {
11281 if [check
-flags
{ { } { } { -std
=c
++98 -std
=gnu
++98 -std
=c
++03 -std
=gnu
++03 } }] {
11284 if { $cxx_default
== "c++98" && [check-flags { { } { } { } { -std=* } }] } {
11290 proc check_effective_target_c
++17_only
{ } {
11292 if ![check_effective_target_c
++] {
11295 if [check
-flags
{ { } { } { -std
=c
++17 -std
=gnu
++17 -std
=c
++1z
-std
=gnu
++1z
} }] {
11298 if { $cxx_default
== "c++17" && [check-flags { { } { } { } { -std=* } }] } {
11304 proc check_effective_target_c
++17 { } {
11305 if [check_effective_target_c
++17_only
] {
11308 return [check_effective_target_c
++2a
]
11310 proc check_effective_target_c
++17_down
{ } {
11311 if ![check_effective_target_c
++] {
11314 return [expr
![check_effective_target_c
++2a
] ]
11317 proc check_effective_target_c
++2a_only
{ } {
11319 if ![check_effective_target_c
++] {
11322 if [check
-flags
{ { } { } { -std
=c
++2a
-std
=gnu
++2a
-std
=c
++20 -std
=gnu
++20 } }] {
11325 if { $cxx_default
== "c++20" && [check-flags { { } { } { } { -std=* } }] } {
11330 proc check_effective_target_c
++2a
{ } {
11331 if [check_effective_target_c
++2a_only
] {
11334 return [check_effective_target_c
++23]
11337 proc check_effective_target_c
++20_only
{ } {
11338 return [check_effective_target_c
++2a_only
]
11341 proc check_effective_target_c
++20 { } {
11342 return [check_effective_target_c
++2a
]
11344 proc check_effective_target_c
++20_down
{ } {
11345 if ![check_effective_target_c
++] {
11348 return [expr
![check_effective_target_c
++23] ]
11351 proc check_effective_target_c
++23_only
{ } {
11353 if ![check_effective_target_c
++] {
11356 if [check
-flags
{ { } { } { -std
=c
++23 -std
=gnu
++23 -std
=c
++2b
-std
=gnu
++2b
} }] {
11359 if { $cxx_default
== "c++23" && [check-flags { { } { } { } { -std=* } }] } {
11364 proc check_effective_target_c
++23 { } {
11365 if [check_effective_target_c
++23_only
] {
11368 return [check_effective_target_c
++26]
11371 proc check_effective_target_c
++23_down
{ } {
11372 if ![check_effective_target_c
++] {
11375 return [expr
![check_effective_target_c
++26] ]
11378 proc check_effective_target_c
++26_only
{ } {
11380 if ![check_effective_target_c
++] {
11383 if [check
-flags
{ { } { } { -std
=c
++26 -std
=gnu
++26 -std
=c
++2c
-std
=gnu
++2c
} }] {
11386 if { $cxx_default
== "c++26" && [check-flags { { } { } { } { -std=* } }] } {
11392 proc check_effective_target_c
++26 { } {
11393 return [check_effective_target_c
++26_only
]
11396 # Check
for C
++ Concepts support
, i.e.
-fconcepts flag.
11397 proc check_effective_target_concepts
{ } {
11398 if [check_effective_target_c
++2a
] {
11401 return [check
-flags
{ "" { } { -fconcepts } }]
11404 proc check_effective_target_implicit_constexpr
{ } {
11405 return [check
-flags
{ "" { } { -fimplicit-constexpr } }]
11408 #
Return 1 if expensive testcases should be run.
11410 proc check_effective_target_run_expensive_tests
{ } {
11411 if { [getenv GCC_TEST_RUN_EXPENSIVE
] != "" } {
11417 # Returns
1 if "mempcpy" is available on the target system.
11419 proc check_effective_target_mempcpy
{} {
11420 if { [istarget
*-*-vxworks
*] } {
11421 # VxWorks doesn
't have mempcpy but our way to test fails
11422 # to detect as we're doing partial links
for kernel modules.
11425 return [check_function_available
"mempcpy"]
11428 # Returns
1 if "stpcpy" is available on the target system.
11430 proc check_effective_target_stpcpy
{} {
11431 return [check_function_available
"stpcpy"]
11434 # Returns
1 if "sigsetjmp" is available on the target system.
11435 # Also check
if "__sigsetjmp" is defined since that's what glibc
11438 proc check_effective_target_sigsetjmp
{} {
11439 if { [check_function_available
"sigsetjmp"]
11440 ||
[check_function_available
"__sigsetjmp"] } {
11446 # Check whether the vectorizer tests are supported by the target and
11447 # append additional target
-dependent
compile flags to DEFAULT_VECTCFLAGS.
11448 #
If a port wants to
execute the tests more than once it should append
11449 # the supported target to EFFECTIVE_TARGETS instead
, and the
compile flags
11450 # will be added by a
call to add_options_for_
<target
>.
11451 #
Set dg
-do-what
-default to either
compile or run
, depending
on target
11452 # capabilities.
Do not
set this
if the supported target is appended to
11453 # EFFECTIVE_TARGETS. Flags and this
variable will be
set by et
-dg
-runtest
11454 # automatically.
Return the number of effective targets
if vectorizer tests
11455 # are supported
, 0 otherwise.
11457 proc check_vect_support_and_set_flags
{ } {
11458 global DEFAULT_VECTCFLAGS
11459 global dg
-do-what
-default
11460 global EFFECTIVE_TARGETS
11462 if [istarget powerpc
-*paired
*] {
11463 lappend DEFAULT_VECTCFLAGS
"-mpaired"
11464 if [check_750cl_hw_available
] {
11465 set dg
-do-what
-default run
11467 set dg
-do-what
-default
compile
11469 } elseif
[istarget powerpc
*-*-*] {
11470 # Skip targets not supporting
-maltivec.
11471 if ![is
-effective
-target powerpc_altivec_ok
] {
11475 lappend DEFAULT_VECTCFLAGS
"-maltivec"
11476 if [check_p9vector_hw_available
] {
11477 lappend DEFAULT_VECTCFLAGS
"-mpower9-vector"
11478 } elseif
[check_p8vector_hw_available
] {
11479 lappend DEFAULT_VECTCFLAGS
"-mpower8-vector"
11480 } elseif
[check_vsx_hw_available
] {
11481 lappend DEFAULT_VECTCFLAGS
"-mvsx" "-mno-allow-movmisalign"
11484 if [check_vmx_hw_available
] {
11485 set dg
-do-what
-default run
11487 if [is
-effective
-target ilp32
] {
11488 # Specify a cpu that supports VMX
for compile-only tests.
11489 lappend DEFAULT_VECTCFLAGS
"-mcpu=970"
11491 set dg
-do-what
-default
compile
11493 } elseif
{ [istarget i?
86-*-*] ||
[istarget x86_64
-*-*] } {
11494 lappend DEFAULT_VECTCFLAGS
"-msse2"
11495 if { [check_effective_target_sse2_runtime
] } {
11496 set dg
-do-what
-default run
11498 set dg
-do-what
-default
compile
11500 } elseif
{ [istarget mips
*-*-*]
11501 && [check_effective_target_nomips16
] } {
11502 if { [check_effective_target_mpaired_single
"-mpaired-single"] } {
11503 lappend EFFECTIVE_TARGETS mpaired_single
11505 if { [check_effective_target_mips_loongson_mmi
"-mloongson-mmi"] } {
11506 lappend EFFECTIVE_TARGETS mips_loongson_mmi
11508 if { [check_effective_target_mips_msa
"-mmsa"] } {
11509 lappend EFFECTIVE_TARGETS mips_msa
11511 return [llength $EFFECTIVE_TARGETS
]
11512 } elseif
[istarget sparc
*-*-*] {
11513 lappend DEFAULT_VECTCFLAGS
"-mcpu=ultrasparc" "-mvis"
11514 if [check_effective_target_ultrasparc_hw
] {
11515 set dg
-do-what
-default run
11517 set dg
-do-what
-default
compile
11519 } elseif
[istarget alpha
*-*-*] {
11520 # Alpha
's vectorization capabilities are extremely limited.
11521 # It's more effort than its worth disabling all of the tests
11522 # that it cannot pass. But
if you actually want to see what
11523 # does work
, command out the
return.
11526 lappend DEFAULT_VECTCFLAGS
"-mmax"
11527 if [check_alpha_max_hw_available
] {
11528 set dg
-do-what
-default run
11530 set dg
-do-what
-default
compile
11532 } elseif
[istarget ia64
-*-*] {
11533 set dg
-do-what
-default run
11534 } elseif
[is
-effective
-target arm_neon_ok
] {
11535 eval lappend DEFAULT_VECTCFLAGS
[add_options_for_arm_neon
""]
11536 # NEON does not support denormals
, so is not used
for vectorization by
11537 # default to avoid loss of precision. We must pass
-ffast
-math to test
11538 # vectorization of float operations.
11539 lappend DEFAULT_VECTCFLAGS
"-ffast-math"
11540 if [is
-effective
-target arm_neon_hw
] {
11541 set dg
-do-what
-default run
11543 set dg
-do-what
-default
compile
11545 } elseif
[istarget aarch64
*-*-*] {
11546 set dg
-do-what
-default run
11547 } elseif
[istarget s390
*-*-*] {
11548 # The S
/390 backend
set a default of
2 for that value.
11549 # Override it to have the same situation as with other
11551 lappend DEFAULT_VECTCFLAGS
"--param" "min-vect-loop-bound=1"
11552 lappend DEFAULT_VECTCFLAGS
"--param" "max-unrolled-insns=200"
11553 lappend DEFAULT_VECTCFLAGS
"--param" "max-unroll-times=8"
11554 lappend DEFAULT_VECTCFLAGS
"--param" "max-completely-peeled-insns=200"
11555 lappend DEFAULT_VECTCFLAGS
"--param" "max-completely-peel-times=16"
11556 if [check_effective_target_s390_vxe2
] {
11557 lappend DEFAULT_VECTCFLAGS
"-march=z15" "-mzarch"
11558 set dg
-do-what
-default run
11559 } elseif
[check_effective_target_s390_vxe
] {
11560 lappend DEFAULT_VECTCFLAGS
"-march=z14" "-mzarch"
11561 set dg
-do-what
-default run
11562 } elseif
[check_effective_target_s390_vx
] {
11563 lappend DEFAULT_VECTCFLAGS
"-march=z13" "-mzarch"
11564 set dg
-do-what
-default run
11566 lappend DEFAULT_VECTCFLAGS
"-march=z14" "-mzarch"
11567 set dg
-do-what
-default
compile
11569 } elseif
[istarget amdgcn
-*-*] {
11570 set dg
-do-what
-default run
11571 } elseif
[istarget riscv64
-*-*] {
11572 if [check_effective_target_riscv_v
] {
11573 lappend DEFAULT_VECTCFLAGS
"--param" "riscv-vector-abi"
11574 set dg
-do-what
-default run
11576 lappend DEFAULT_VECTCFLAGS
"-march=rv64gcv_zvfh" "-mabi=lp64d"
11577 lappend DEFAULT_VECTCFLAGS
"--param" "riscv-autovec-preference=scalable"
11578 lappend DEFAULT_VECTCFLAGS
"--param" "riscv-vector-abi"
11579 set dg
-do-what
-default
compile
11581 } elseif
[istarget loongarch
*-*-*] {
11582 lappend DEFAULT_VECTCFLAGS
"-mdouble-float" "-mlasx"
11583 if [check_effective_target_loongarch_asx_hw
] {
11584 set dg
-do-what
-default run
11586 set dg
-do-what
-default
compile
11595 #
Return 1 if the target does
*not
* require strict alignment.
11597 proc check_effective_target_non_strict_align
{} {
11599 #
On ARM
, the default is to use STRICT_ALIGNMENT
, but there
11600 # are interfaces defined
for misaligned access and thus
11601 # depending
on the architecture levels unaligned access is
11603 if [istarget
"arm*-*-*"] {
11604 return [check_effective_target_arm_unaligned
]
11607 return [check_no_compiler_messages non_strict_align assembly
{
11609 typedef char __attribute__
((__aligned__
(__BIGGEST_ALIGNMENT__
))) c
;
11611 void foo
(void
) { z
= (c
*) y
; }
11615 #
Return 1 if the target supports
-mstrict
-align
(and
-mno
-strict
-align
).
11617 proc check_effective_target_opt_mstrict_align
{} {
11618 return [check_no_compiler_messages opt_mstrict_align assembly
{
11620 } "-mstrict-align -mno-strict-align"]
11623 #
Return 1 if the target has
<ucontext.h
>.
11625 proc check_effective_target_ucontext_h
{ } {
11626 return [check_no_compiler_messages ucontext_h assembly
{
11627 #
include <ucontext.h
>
11631 proc check_effective_target_aarch64_tiny
{ } {
11632 if { [istarget aarch64
*-*-*] } {
11633 return [check_no_compiler_messages aarch64_tiny object
{
11634 #ifdef __AARCH64_CMODEL_TINY__
11637 #error target not AArch64 tiny code
model
11645 # Create functions to check that the AArch64 assembler supports the
11646 # various architecture extensions via the .arch_extension pseudo
-op.
11648 foreach
{ aarch64_ext
} { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve"
11649 "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64"
11650 "sme" "sme-i16i64" "sme2" } {
11651 eval
[string map
[list FUNC $aarch64_ext
] {
11652 proc check_effective_target_aarch64_asm_FUNC_ok
{ } {
11653 if { [istarget aarch64
*-*-*] } {
11654 return [check_no_compiler_messages aarch64_FUNC_assembler object
{
11655 __asm__
(".arch_extension FUNC");
11656 } "-march=armv8-a+FUNC"]
11664 proc check_effective_target_aarch64_small
{ } {
11665 if { [istarget aarch64
*-*-*] } {
11666 return [check_no_compiler_messages aarch64_small object
{
11667 #ifdef __AARCH64_CMODEL_SMALL__
11670 #error target not AArch64 small code
model
11678 proc check_effective_target_aarch64_large
{ } {
11679 if { [istarget aarch64
*-*-*] } {
11680 return [check_no_compiler_messages aarch64_large object
{
11681 #ifdef __AARCH64_CMODEL_LARGE__
11684 #error target not AArch64 large code
model
11692 #
Return 1 if the assembler accepts the aarch64 .variant_pcs directive.
11694 proc check_effective_target_aarch64_variant_pcs
{ } {
11695 if { [istarget aarch64
*-*-*] } {
11696 return [check_no_compiler_messages aarch64_variant_pcs object
{
11697 __asm__
(".variant_pcs foo");
11704 #
Return 1 if this is a reduced AVR Tiny core. Such cores have different
11705 # register
set, instruction
set, addressing capabilities and ABI.
11707 proc check_effective_target_avr_tiny
{ } {
11708 if { [istarget avr
*-*-*] } {
11709 return [check_no_compiler_messages avr_tiny object
{
11710 #ifdef __AVR_TINY__
11713 #error target not a reduced AVR Tiny core
11721 #
Return 1 if <fenv.h
> is available.
11723 proc check_effective_target_fenv
{} {
11724 return [check_no_compiler_messages fenv object
{
11726 } [add_options_for_ieee
"-std=gnu99"]]
11729 #
Return 1 if <fenv.h
> is available with all the standard IEEE
11730 # exceptions and floating
-point exceptions are raised by arithmetic
11731 # operations.
(If the target requires special options
for "inexact"
11732 # exceptions
, those need to be specified in the testcases.
)
11734 proc check_effective_target_fenv_exceptions
{} {
11735 return [check_runtime fenv_exceptions
{
11737 #
include <stdlib.h
>
11738 #ifndef FE_DIVBYZERO
11739 # error Missing FE_DIVBYZERO
11742 # error Missing FE_INEXACT
11745 # error Missing FE_INVALID
11747 #ifndef FE_OVERFLOW
11748 # error Missing FE_OVERFLOW
11750 #ifndef FE_UNDERFLOW
11751 # error Missing FE_UNDERFLOW
11753 volatile float a
= 0.0f
, r
;
11758 if (fetestexcept
(FE_INVALID
))
11763 } [add_options_for_ieee
"-std=gnu99"]]
11766 #
Return 1 if <fenv.h
> is available with all the standard IEEE
11767 # exceptions and floating
-point exceptions are raised by arithmetic
11768 # operations
for decimal floating point.
(If the target requires
11769 # special options
for "inexact" exceptions, those need to be specified
11770 # in the testcases.
)
11772 proc check_effective_target_fenv_exceptions_dfp
{} {
11773 return [check_runtime fenv_exceptions_dfp
{
11775 #
include <stdlib.h
>
11776 #ifndef FE_DIVBYZERO
11777 # error Missing FE_DIVBYZERO
11780 # error Missing FE_INEXACT
11783 # error Missing FE_INVALID
11785 #ifndef FE_OVERFLOW
11786 # error Missing FE_OVERFLOW
11788 #ifndef FE_UNDERFLOW
11789 # error Missing FE_UNDERFLOW
11791 volatile _Decimal64 a
= 0.0DD
, r
;
11796 if (fetestexcept
(FE_INVALID
))
11801 } [add_options_for_ieee
"-std=gnu99"]]
11804 #
Return 1 if <fenv.h
> is available with all the standard IEEE
11805 # exceptions and floating
-point exceptions are raised by arithmetic
11806 # operations.
(If the target requires special options
for "inexact"
11807 # exceptions
, those need to be specified in the testcases.
)
11809 proc check_effective_target_fenv_exceptions_double
{} {
11810 return [check_runtime fenv_exceptions_double
{
11812 #
include <stdlib.h
>
11813 #ifndef FE_DIVBYZERO
11814 # error Missing FE_DIVBYZERO
11817 # error Missing FE_INEXACT
11820 # error Missing FE_INVALID
11822 #ifndef FE_OVERFLOW
11823 # error Missing FE_OVERFLOW
11825 #ifndef FE_UNDERFLOW
11826 # error Missing FE_UNDERFLOW
11828 volatile double a
= 0.0f
, r
;
11833 if (fetestexcept
(FE_INVALID
))
11838 } [add_options_for_ieee
"-std=gnu99"]]
11841 #
Return 1 if <fenv.h
> is available with all the standard IEEE
11842 # exceptions and floating
-point exceptions are raised by arithmetic
11843 # operations.
(If the target requires special options
for "inexact"
11844 # exceptions
, those need to be specified in the testcases.
)
11846 proc check_effective_target_fenv_exceptions_long_double
{} {
11847 return [check_runtime fenv_exceptions_long_double
{
11849 #
include <stdlib.h
>
11850 #ifndef FE_DIVBYZERO
11851 # error Missing FE_DIVBYZERO
11854 # error Missing FE_INEXACT
11857 # error Missing FE_INVALID
11859 #ifndef FE_OVERFLOW
11860 # error Missing FE_OVERFLOW
11862 #ifndef FE_UNDERFLOW
11863 # error Missing FE_UNDERFLOW
11865 volatile long double a
= 0.0f
, r
;
11870 if (fetestexcept
(FE_INVALID
))
11875 } [add_options_for_ieee
"-std=gnu99"]]
11878 #
Return 1 if -fexceptions is supported.
11880 proc check_effective_target_exceptions
{} {
11881 if { [istarget amdgcn
*-*-*] } {
11887 # Used to check
if the testing configuration supports exceptions.
11888 # Returns
0 if exceptions are unsupported or disabled
(e.g. by passing
11889 #
-fno
-exceptions
). Returns
1 if exceptions are enabled.
11890 proc check_effective_target_exceptions_enabled
{} {
11891 return [check_cached_effective_target exceptions_enabled
{
11892 if { [check_effective_target_exceptions
] } {
11893 return [check_no_compiler_messages exceptions_enabled assembly
{
11901 #
If exceptions aren
't supported, then they're not enabled.
11907 proc check_effective_target_tiny
{} {
11908 return [check_cached_effective_target tiny
{
11909 if { [istarget aarch64
*-*-*]
11910 && [check_effective_target_aarch64_tiny
] } {
11913 if { [istarget avr
-*-*]
11914 && [check_effective_target_avr_tiny
] } {
11917 # PRU
Program Counter is
16-bits
, and trampolines are not supported.
11918 # Hence directly declare as a tiny target.
11919 if [istarget pru
-*-*] {
11926 #
Return 1 if the target supports
-mbranch
-cost
=N option.
11928 proc check_effective_target_branch_cost
{} {
11929 if { [ istarget arm
*-*-*]
11930 ||
[istarget avr
*-*-*]
11931 ||
[istarget csky
*-*-*]
11932 ||
[istarget epiphany
*-*-*]
11933 ||
[istarget frv
*-*-*]
11934 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
11935 ||
[istarget loongarch
*-*-*]
11936 ||
[istarget mips
*-*-*]
11937 ||
[istarget s390
*-*-*]
11938 ||
[istarget riscv
*-*-*]
11939 ||
[istarget sh
*-*-*] } {
11945 # Record that dg
-final test TEST requires convential compilation.
11947 proc set_required_options_for
{ test
} {
11948 if { [info proc $test
] == "" } {
11949 perror
"$test does not exist"
11952 proc $
{test
}_required_options
{} {
11953 global gcc_set_required_options
11954 upvar
1 extra_tool_flags extra_tool_flags
11955 if {[regexp
-- "^scan-assembler" [info level 0]]
11956 && ![string match
"*-fident*" $extra_tool_flags]} {
11957 #
Do not let .ident confuse assembler scan tests
11958 return [list $gcc_set_required_options
"-fno-ident"]
11960 return $gcc_set_required_options
11964 # Record that dg
-final test scan
-ltrans
-tree
-dump
* requires
-flto
-partition
=one
11965 # in order to force a single partition
, allowing scan
-ltrans
-tree
-dump
* to scan
11966 # a dump file
*.exe.ltrans0.
*.
11968 proc scan
-ltrans
-tree
-dump_required_options
{} {
11969 return "-flto-partition=one"
11971 proc scan
-ltrans
-tree
-dump
-times_required_options
{} {
11972 return "-flto-partition=one"
11974 proc scan
-ltrans
-tree
-dump
-not_required_options
{} {
11975 return "-flto-partition=one"
11977 proc scan
-ltrans
-tree
-dump
-dem_required_options
{} {
11978 return "-flto-partition=one"
11980 proc scan
-ltrans
-tree
-dump
-dem
-not_required_options
{} {
11981 return "-flto-partition=one"
11984 #
Return 1 if the x86
-64 target supports PIE with copy reloc
, 0
11985 # otherwise.
Cache the result.
11987 proc check_effective_target_pie_copyreloc
{ } {
11989 global GCC_UNDER_TEST
11991 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
11995 # Need auto
-host.h to check linker support.
11996 if { ![file
exists ..
/..
/auto
-host.h
] } {
12000 return [check_cached_effective_target pie_copyreloc
{
12001 #
Set up and
compile to see
if linker supports PIE with copy
12002 # reloc.
Include the current process ID in the file names to
12003 # prevent conflicts with invocations
for multiple testsuites.
12008 set f
[open $src
"w"]
12009 puts $f
"#include \"../../auto-host.h\""
12010 puts $f
"#if HAVE_LD_PIE_COPYRELOC == 0"
12011 puts $f
"# error Linker does not support PIE with copy reloc."
12015 verbose
"check_effective_target_pie_copyreloc compiling testfile $src" 2
12016 set lines
[$
{tool
}_target_compile $src $
obj object
""]
12021 if [string match
"" $lines] then {
12022 verbose
"check_effective_target_pie_copyreloc testfile compilation passed" 2
12025 verbose
"check_effective_target_pie_copyreloc testfile compilation failed" 2
12031 #
Return 1 if the x86 target supports R_386_GOT32X relocation
, 0
12032 # otherwise.
Cache the result.
12034 proc check_effective_target_got32x_reloc
{ } {
12036 global GCC_UNDER_TEST
12038 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
12042 # Need auto
-host.h to check linker support.
12043 if { ![file
exists ..
/..
/auto
-host.h
] } {
12047 return [check_cached_effective_target got32x_reloc
{
12048 #
Include the current process ID in the file names to prevent
12049 # conflicts with invocations
for multiple testsuites.
12051 set src got32x
[pid
].c
12052 set obj got32x
[pid
].o
12054 set f
[open $src
"w"]
12055 puts $f
"#include \"../../auto-host.h\""
12056 puts $f
"#if HAVE_AS_IX86_GOT32X == 0"
12057 puts $f
"# error Assembler does not support R_386_GOT32X."
12061 verbose
"check_effective_target_got32x_reloc compiling testfile $src" 2
12062 set lines
[$
{tool
}_target_compile $src $
obj object
""]
12067 if [string match
"" $lines] then {
12068 verbose
"check_effective_target_got32x_reloc testfile compilation passed" 2
12071 verbose
"check_effective_target_got32x_reloc testfile compilation failed" 2
12076 return $got32x_reloc_available_saved
12079 #
Return 1 if the x86 target supports calling ___tls_get_addr via GOT
,
12080 #
0 otherwise.
Cache the result.
12082 proc check_effective_target_tls_get_addr_via_got
{ } {
12084 global GCC_UNDER_TEST
12086 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
12090 # Need auto
-host.h to check linker support.
12091 if { ![file
exists ..
/..
/auto
-host.h
] } {
12095 return [check_cached_effective_target tls_get_addr_via_got
{
12096 #
Include the current process ID in the file names to prevent
12097 # conflicts with invocations
for multiple testsuites.
12099 set src tls_get_addr_via_got
[pid
].c
12100 set obj tls_get_addr_via_got
[pid
].o
12102 set f
[open $src
"w"]
12103 puts $f
"#include \"../../auto-host.h\""
12104 puts $f
"#if HAVE_AS_IX86_TLS_GET_ADDR_GOT == 0"
12105 puts $f
"# error Assembler/linker do not support calling ___tls_get_addr via GOT."
12109 verbose
"check_effective_target_tls_get_addr_via_got compiling testfile $src" 2
12110 set lines
[$
{tool
}_target_compile $src $
obj object
""]
12115 if [string match
"" $lines] then {
12116 verbose
"check_effective_target_tls_get_addr_via_got testfile compilation passed" 2
12119 verbose
"check_effective_target_tls_get_addr_via_got testfile compilation failed" 2
12125 #
Return 1 if the target uses comdat groups.
12127 proc check_effective_target_comdat_group
{} {
12128 return [check_no_messages_and_pattern comdat_group
"\.section\[^\n\r]*,comdat|\.group\[^\n\r]*,#comdat" assembly {
12130 inline
int foo
() { return 1; }
12131 int (*fn
) () = foo
;
12135 #
Return 1 if target supports __builtin_eh_return
12136 proc check_effective_target_builtin_eh_return
{ } {
12137 return [check_no_compiler_messages builtin_eh_return object
{
12138 void test
(long l
, void
*p
)
12140 __builtin_eh_return
(l
, p
);
12145 #
Return 1 if the target supports
max reduction
for vectors.
12147 proc check_effective_target_vect_max_reduc
{ } {
12148 if { [istarget aarch64
*-*-*] ||
[is
-effective
-target arm_neon
]
12149 ||
[check_effective_target_riscv_v
] } {
12155 #
Return 1 if the compiler has been configured with nvptx offloading.
12157 proc check_effective_target_offload_nvptx
{ } {
12158 return [check_no_compiler_messages offload_nvptx assembly
{
12159 int main
() {return 0;}
12160 } "-foffload=nvptx-none" ]
12163 #
Return 1 if the compiler has been configured with gcn offloading.
12165 proc check_effective_target_offload_gcn
{ } {
12166 return [check_no_compiler_messages offload_gcn assembly
{
12167 int main
() {return 0;}
12168 } "-foffload=amdgcn-amdhsa" ]
12171 #
Return 1 if the target support
-fprofile
-update=atomic
12172 proc check_effective_target_profile_update_atomic
{} {
12173 return [check_no_compiler_messages profile_update_atomic assembly
{
12174 int main
(void
) { return 0; }
12175 } "-fprofile-update=atomic -fprofile-generate"]
12178 #
Return 1 if vector
(va
- vector add
) instructions are understood by
12179 # the assembler and can be executed. This also covers checking
for
12180 # the VX kernel feature. A kernel without that feature does not
12181 # enable the vector facility and the following check will die with a
12183 proc check_effective_target_s390_vx
{ } {
12184 if ![istarget s390
*-*-*] then {
12188 return [check_runtime s390_check_vx
{
12191 asm
("va %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12194 } "-march=z13 -mzarch" ]
12197 # Same as above but
for the z14 vector enhancement facility. Test
12198 # is performed with the vector nand instruction.
12199 proc check_effective_target_s390_vxe
{ } {
12200 if ![istarget s390
*-*-*] then {
12204 return [check_runtime s390_check_vxe
{
12207 asm
("vnn %%v24, %%v26, %%v28" : : : "v24", "v26", "v28");
12210 } "-march=z14 -mzarch" ]
12213 # Same as above but
for the arch13 vector enhancement facility. Test
12214 # is performed with the vector shift left double by bit instruction.
12215 proc check_effective_target_s390_vxe2
{ } {
12216 if ![istarget s390
*-*-*] then {
12220 return [check_runtime s390_check_vxe2
{
12223 asm
("vsld %%v24, %%v26, %%v28, 3" : : : "v24", "v26", "v28");
12226 } "-march=arch13 -mzarch" ]
12229 # Same as above but
for the arch14 NNPA facility.
12230 proc check_effective_target_s390_nnpa
{ } {
12231 if ![istarget s390
*-*-*] then {
12235 return [check_runtime s390_check_nnpa
{
12238 asm
("vzero %%v24\n\t"
12239 "vcrnf %%v24,%%v24,%%v24,0,2" : : : "v24");
12242 } "-march=arch14 -mzarch" ]
12245 #
For versions of ARM architectures that have hardware div insn
,
12246 #disable the divmod transform
12248 proc check_effective_target_arm_divmod_simode
{ } {
12249 return [check_no_compiler_messages arm_divmod assembly
{
12250 #ifdef __ARM_ARCH_EXT_IDIV__
12251 #error has div insn
12257 #
Return 1 if target supports divmod hardware insn or divmod libcall.
12259 proc check_effective_target_divmod
{ } {
12260 #TODO
: Add checks
for all targets that have either hardware divmod insn
12261 # or
define libfunc
for divmod.
12262 if { [istarget arm
*-*-*]
12263 ||
[istarget i?
86-*-*] ||
[istarget x86_64
-*-*]
12264 ||
[istarget amdgcn
-*-*] } {
12270 #
Return 1 if target supports divmod
for SImode. The reason
for
12271 # separating this from check_effective_target_divmod is that
12272 # some versions of ARM architecture
define div instruction
12273 # only
for simode
, and
for these archs
, we
do not want to enable
12274 # divmod transform
for simode.
12276 proc check_effective_target_divmod_simode
{ } {
12277 if { [istarget arm
*-*-*] } {
12278 return [check_effective_target_arm_divmod_simode
]
12281 return [check_effective_target_divmod
]
12284 #
Return 1 if store merging optimization is applicable
for target.
12285 # Store merging is not profitable
for targets like the avr which
12286 # can
load/store only one byte at a time. Use
int size as a proxy
12287 #
for the number of bytes the target can write
, and skip
for targets
12288 # with a smallish
(< 32) size.
12290 proc check_effective_target_store_merge
{ } {
12291 if { [is
-effective
-target non_strict_align
] && [is
-effective
-target int32plus
] } {
12298 #
Return 1 if we
're able to assemble rdrand
12300 proc check_effective_target_rdrand { } {
12301 return [check_no_compiler_messages_nocache rdrand object {
12306 __builtin_ia32_rdrand32_step(&val);
12312 # Return 1 if the target supports coprocessor instructions: cdp, ldc, ldcl,
12313 # stc, stcl, mcr and mrc.
12314 proc check_effective_target_arm_coproc1_ok_nocache { } {
12315 if { ![istarget arm*-*-*] } {
12318 return [check_no_compiler_messages_nocache arm_coproc1_ok assembly {
12319 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 4
12322 #include <arm_acle.h>
12326 proc check_effective_target_arm_coproc1_ok { } {
12327 return [check_cached_effective_target arm_coproc1_ok \
12328 check_effective_target_arm_coproc1_ok_nocache]
12331 # Return 1 if the target supports all coprocessor instructions checked by
12332 # check_effective_target_arm_coproc1_ok in addition to the following: cdp2,
12333 # ldc2, ldc2l, stc2, stc2l, mcr2 and mrc2.
12334 proc check_effective_target_arm_coproc2_ok_nocache { } {
12335 if { ![check_effective_target_arm_coproc1_ok] } {
12338 return [check_no_compiler_messages_nocache arm_coproc2_ok assembly {
12339 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 5
12342 #include <arm_acle.h>
12346 proc check_effective_target_arm_coproc2_ok { } {
12347 return [check_cached_effective_target arm_coproc2_ok \
12348 check_effective_target_arm_coproc2_ok_nocache]
12351 # Return 1 if the target supports all coprocessor instructions checked by
12352 # check_effective_target_arm_coproc2_ok in addition the following: mcrr and
12354 proc check_effective_target_arm_coproc3_ok_nocache { } {
12355 if { ![check_effective_target_arm_coproc2_ok] } {
12358 return [check_no_compiler_messages_nocache arm_coproc3_ok assembly {
12359 #if (__thumb__ && !__thumb2__) \
12360 || (__ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__))
12363 #include <arm_acle.h>
12367 proc check_effective_target_arm_coproc3_ok { } {
12368 return [check_cached_effective_target arm_coproc3_ok \
12369 check_effective_target_arm_coproc3_ok_nocache]
12372 # Return 1 if the target supports all coprocessor instructions checked by
12373 # check_effective_target_arm_coproc3_ok in addition the following: mcrr2 and
12375 proc check_effective_target_arm_coproc4_ok_nocache { } {
12376 if { ![check_effective_target_arm_coproc3_ok] } {
12379 return [check_no_compiler_messages_nocache arm_coproc4_ok assembly {
12380 #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 6
12383 #include <arm_acle.h>
12387 proc check_effective_target_arm_coproc4_ok { } {
12388 return [check_cached_effective_target arm_coproc4_ok \
12389 check_effective_target_arm_coproc4_ok_nocache]
12392 # Return 1 if the target supports the auto_inc_dec optimization pass.
12393 proc check_effective_target_autoincdec { } {
12394 if { ![check_no_compiler_messages auto_incdec assembly { void f () { }
12395 } "-O2 -fdump-rtl-auto_inc_dec" ] } {
12399 set dumpfile [glob -nocomplain "auto_incdec[pid].c.\[0-9\]\[0-9\]\[0-9\]r.auto_inc_dec"]
12400 if { [file exists $dumpfile ] } {
12401 file delete $dumpfile
12407 # Return 1 if the target has support for stack probing designed
12408 # to avoid stack-clash style attacks.
12410 # This is used to restrict the stack-clash mitigation tests to
12411 # just those targets that have been explicitly supported.
12413 # In addition to the prologue work on those targets, each target's
12414 # properties should be described in the functions below so that
12415 # tests
do not become a mess of unreadable target conditions.
12417 proc check_effective_target_supports_stack_clash_protection
{ } {
12419 if { [istarget x86_64
-*-*] ||
[istarget i?
86-*-*]
12420 ||
[istarget powerpc
*-*-*] ||
[istarget rs6000
*-*-*]
12421 ||
[istarget aarch64
*-**] ||
[istarget s390
*-*-*]
12422 ||
[istarget loongarch64
*-**] } {
12428 #
Return 1 if the target creates a frame pointer
for non
-leaf functions
12429 # Note we ignore cases where we apply tail
call optimization here.
12430 proc check_effective_target_frame_pointer_for_non_leaf
{ } {
12431 # Solaris
/x86 defaults to
-fno
-omit
-frame
-pointer.
12432 if { [istarget i?
86-*-solaris
*] ||
[istarget x86_64
-*-solaris
*] } {
12439 #
Return 1 if the target can perform tail
-call optimizations of the
12440 # most trivial type.
12441 proc check_effective_target_tail_call
{ } {
12442 return [check_no_messages_and_pattern tail_call
",SIBCALL" rtl-expand {
12443 __attribute__
((__noipa__
)) void foo
(void
) { }
12444 __attribute__
((__noipa__
)) void bar
(void
) { foo
(); }
12445 } {-O2
-fdump
-rtl
-expand
-all
}] ;# The
"SIBCALL" note requires a detailed dump.
12448 #
Return 1 if the target
's calling sequence or its ABI
12449 # create implicit stack probes at or prior to function entry.
12450 proc check_effective_target_caller_implicit_probes { } {
12452 # On x86/x86_64 the call instruction itself pushes the return
12453 # address onto the stack. That is an implicit probe of *sp.
12454 if { [istarget x86_64-*-*] || [istarget i?86-*-*] } {
12458 # On PPC, the ABI mandates that the address of the outer
12459 # frame be stored at *sp. Thus each allocation of stack
12460 # space is itself an implicit probe of *sp.
12461 if { [istarget powerpc*-*-*] || [istarget rs6000*-*-*] } {
12465 # s390's ABI has a register save area allocated by the
12466 # caller
for use by the callee. The mere existence does
12467 # not constitute a probe by the caller
, but when the slots
12468 # used by the callee those stores are implicit probes.
12469 if { [istarget s390
*-*-*] } {
12473 # Not strictly true
on aarch64
, but we have agreed that we will
12474 #
consider any function that pushes SP more than
3kbytes into
12475 # the guard
page as broken. This essentially means that we can
12476 #
consider the aarch64 as having a caller implicit probe at
12478 if { [istarget aarch64
*-*-*] } {
12482 if { [istarget loongarch64
*-*-*] } {
12489 # Targets that potentially realign the stack pointer often cause residual
12490 # stack allocations and make it difficult to elimination loops or residual
12491 # allocations
for dynamic stack allocations
12492 proc check_effective_target_callee_realigns_stack
{ } {
12493 if { [istarget x86_64
-*-*] ||
[istarget i?
86-*-*] } {
12499 #
Return 1 if CET instructions can be compiled.
12500 proc check_effective_target_cet
{ } {
12501 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
12504 return [check_no_compiler_messages cet object
{
12509 } "-O2 -fcf-protection" ]
12512 #
Return 1 if target supports floating point
"infinite"
12513 proc check_effective_target_inf
{ } {
12514 return [check_no_compiler_messages supports_inf assembly
{
12515 const double pinf
= __builtin_inf
();
12519 #
Return 1 if target supports floating point
"infinite" for float.
12520 proc check_effective_target_inff
{ } {
12521 return [check_no_compiler_messages supports_inff assembly
{
12522 const float pinf
= __builtin_inff
();
12526 #
Return 1 if the target supports ARMv8.3 Adv.SIMD Complex instructions
12527 # instructions
, 0 otherwise. The test is valid
for ARM and
for AArch64.
12528 # Record the command line options needed.
12530 proc check_effective_target_arm_v8_3a_complex_neon_ok_nocache
{ } {
12531 global et_arm_v8_3a_complex_neon_flags
12532 set et_arm_v8_3a_complex_neon_flags
""
12534 if { ![istarget arm
*-*-*] && ![istarget aarch64
*-*-*] } {
12538 # Iterate through sets of options to find the compiler flags that
12539 # need to be added to the
-march option.
12540 foreach flags
{"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12541 if { [check_no_compiler_messages_nocache \
12542 arm_v8_3a_complex_neon_ok assembly
{
12543 #
if !defined
(__ARM_FEATURE_COMPLEX
)
12544 #error
"__ARM_FEATURE_COMPLEX not defined"
12546 } "$flags -march=armv8.3-a"] } {
12547 set et_arm_v8_3a_complex_neon_flags
"$flags -march=armv8.3-a"
12555 proc check_effective_target_arm_v8_3a_complex_neon_ok
{ } {
12556 return [check_cached_effective_target arm_v8_3a_complex_neon_ok \
12557 check_effective_target_arm_v8_3a_complex_neon_ok_nocache
]
12560 proc add_options_for_arm_v8_3a_complex_neon
{ flags
} {
12561 if { ! [check_effective_target_arm_v8_3a_complex_neon_ok
] } {
12564 global et_arm_v8_3a_complex_neon_flags
12565 return "$flags $et_arm_v8_3a_complex_neon_flags"
12568 #
Return 1 if the target supports ARMv8.3 Adv.SIMD
+ FP16 Complex instructions
12569 # instructions
, 0 otherwise. The test is valid
for ARM and
for AArch64.
12570 # Record the command line options needed.
12572 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache
{ } {
12573 global et_arm_v8_3a_fp16_complex_neon_flags
12574 set et_arm_v8_3a_fp16_complex_neon_flags
""
12576 if { ![istarget arm
*-*-*] && ![istarget aarch64
*-*-*] } {
12580 # Iterate through sets of options to find the compiler flags that
12581 # need to be added to the
-march option.
12582 foreach flags
{"" "-mfloat-abi=softfp -mfpu=auto" "-mfloat-abi=hard -mfpu=auto"} {
12583 if { [check_no_compiler_messages_nocache \
12584 arm_v8_3a_fp16_complex_neon_ok assembly
{
12585 #
if !defined
(__ARM_FEATURE_COMPLEX
)
12586 #error
"__ARM_FEATURE_COMPLEX not defined"
12588 } "$flags -march=armv8.3-a+fp16"] } {
12589 set et_arm_v8_3a_fp16_complex_neon_flags \
12590 "$flags -march=armv8.3-a+fp16"
12598 proc check_effective_target_arm_v8_3a_fp16_complex_neon_ok
{ } {
12599 return [check_cached_effective_target arm_v8_3a_fp16_complex_neon_ok \
12600 check_effective_target_arm_v8_3a_fp16_complex_neon_ok_nocache
]
12603 proc add_options_for_arm_v8_3a_fp16_complex_neon
{ flags
} {
12604 if { ! [check_effective_target_arm_v8_3a_fp16_complex_neon_ok
] } {
12607 global et_arm_v8_3a_fp16_complex_neon_flags
12608 return "$flags $et_arm_v8_3a_fp16_complex_neon_flags"
12612 #
Return 1 if the target supports executing AdvSIMD instructions from ARMv8.3
12613 # with the complex instruction extension
, 0 otherwise. The test is valid
for
12614 # ARM and
for AArch64.
12616 proc check_effective_target_arm_v8_3a_complex_neon_hw
{ } {
12617 if { ![check_effective_target_arm_v8_3a_complex_neon_ok
] } {
12620 return [check_runtime arm_v8_3a_complex_neon_hw_available
{
12621 #
include "arm_neon.h"
12626 float32x2_t results
= {-4.0,5.0};
12627 float32x2_t a
= {1.0,3.0};
12628 float32x2_t b
= {2.0,5.0};
12630 #ifdef __ARM_ARCH_ISA_A64
12631 asm
("fcadd %0.2s, %1.2s, %2.2s, #90"
12634 : /* No clobbers.
*/);
12637 asm
("vcadd.f32 %P0, %P1, %P2, #90"
12640 : /* No clobbers.
*/);
12643 return (results
[0] == 8 && results
[1] == 24) ?
0 : 1;
12645 } [add_options_for_arm_v8_3a_complex_neon
""]]
12648 #
Return 1 if the assembler supports assembling the Armv8.3 pointer authentication B
key directive
12649 proc check_effective_target_arm_v8_3a_bkey_directive
{ } {
12650 return [check_no_compiler_messages cet object
{
12652 asm
(".cfi_b_key_frame");
12658 #
Return 1 if the target supports executing the Armv8.1
-M Mainline Low
12659 # Overhead Loop
, 0 otherwise. The test is valid
for ARM.
12661 proc check_effective_target_arm_v8_1_lob_ok
{ } {
12662 if { ![check_effective_target_arm_cortex_m
] } {
12665 return [check_runtime arm_v8_1_lob_hw_available
{
12669 asm
("movw r3, #10\n\t" /* movs? */
12670 "dls lr, r3" : : : "r3", "lr");
12673 asm
goto ("le lr, %l0" : : : "lr" : loop);
12676 } "-march=armv8.1-m.main -mthumb" ]
12680 #
Return 1 if this is an ARM target where Thumb
-2 is used without
12681 # options added by the test and the target does not support executing
12682 # the Armv8.1
-M Mainline Low Overhead Loop
, 0 otherwise. The test is
12685 proc check_effective_target_arm_thumb2_no_arm_v8_1_lob
{ } {
12686 if { [check_effective_target_arm_thumb2
]
12687 && ![check_effective_target_arm_v8_1_lob_ok
] } {
12693 #
Return 1 if this is an ARM target where
-mthumb causes Thumb
-2 to be
12694 # used and the target does not support executing the Armv8.1
-M
12695 # Mainline Low Overhead Loop
, 0 otherwise. The test is valid
for ARM.
12697 proc check_effective_target_arm_thumb2_ok_no_arm_v8_1_lob
{ } {
12698 if { [check_effective_target_arm_thumb2_ok
]
12699 && ![check_effective_target_arm_v8_1_lob_ok
] } {
12705 # Returns
1 if the target is using glibc
, 0 otherwise.
12707 proc check_effective_target_glibc
{ } {
12708 return [check_no_compiler_messages glibc_object assembly
{
12709 #
include <stdlib.h
>
12710 #
if !defined
(__GLIBC__
)
12716 #
Return 1 if the target plus current options supports a vector
12717 # complex addition with rotate of half and single float modes
, 0 otherwise.
12719 # This won
't change for different subtargets so cache the result.
12721 foreach N {hf sf} {
12722 eval [string map [list N $N] {
12723 proc check_effective_target_vect_complex_rot_N { } {
12724 return [check_cached_effective_target_indexed vect_complex_rot_N {
12725 expr { [istarget aarch64*-*-*]
12726 || [istarget arm*-*-*] }}]
12731 # Return 1 if the target plus current options supports a vector
12732 # complex addition with rotate of double float modes, 0 otherwise.
12734 # This won't change
for different subtargets so
cache the result.
12737 eval
[string map
[list N $N
] {
12738 proc check_effective_target_vect_complex_rot_N
{ } {
12739 return [check_cached_effective_target_indexed vect_complex_rot_N
{
12740 expr
{ [istarget aarch64
*-*-*] }}]
12745 #
Return 1 if this target uses an LLVM assembler and
/or linker
12746 proc check_effective_target_llvm_binutils
{ } {
12747 return [check_cached_effective_target llvm_binutils
{
12748 expr
{ [istarget amdgcn
*-*-*]
12749 ||
[check_effective_target_offload_gcn
] }}]
12752 #
Return 1 if the compiler supports
'-mfentry'.
12754 proc check_effective_target_mfentry
{ } {
12755 if { !([istarget i?
86-*-*] ||
[istarget x86_64
-*-*]) } {
12758 return [check_no_compiler_messages mfentry object
{
12759 void foo
(void
) { }
12763 #
Return 1 if this target supports indirect calls
12764 proc check_effective_target_indirect_calls
{ } {
12765 if { [istarget bpf
-*-*] } {
12771 #
Return 1 if we can use the
-lgccjit option
, 0 otherwise.
12773 proc check_effective_target_lgccjit
{ } {
12774 if { [info procs jit_target_compile
] == "" } then {
12775 global GCC_UNDER_TEST
12776 if ![info exists GCC_UNDER_TEST
] {
12777 set GCC_UNDER_TEST
"[find_gcc]"
12779 proc jit_target_compile
{ source dest type options
} [info body gcc_target_compile
]
12781 return [check_no_compiler_messages lgccjit executable
{
12782 int main
() { return 0; }
12786 #
Return 1 if the MSP430 small memory
model is in use.
12787 proc check_effective_target_msp430_small
{} {
12788 return [check_no_compiler_messages msp430_small assembly
{
12789 #
if (!defined __MSP430__ || defined __MSP430X_LARGE__
)
12790 #error
!msp430 || __MSP430X_LARGE__
12795 #
Return 1 if the MSP430 large memory
model is in use.
12796 proc check_effective_target_msp430_large
{} {
12797 return [check_no_compiler_messages msp430_large assembly
{
12798 #ifndef __MSP430X_LARGE__
12799 #error __MSP430X_LARGE__
12804 #
Return 1 if GCC was configured with
--with
-tune
=cortex
-a76
12805 proc check_effective_target_tune_cortex_a76
{ } {
12806 return [check_configured_with
"with-tune=cortex-a76"]
12809 #
Return 1 if the target has an efficient means to encode large initializers
12812 proc check_effective_target_large_initializer
{ } {
12813 if { [istarget nvptx
*-*-*] } {
12820 #
Return 1 if the target allows function prototype mismatches
12823 proc check_effective_target_non_strict_prototype
{ } {
12824 if { [istarget nvptx
*-*-*] } {
12831 # Returns
1 if the target toolchain supports extended
12832 # syntax of .symver directive
, 0 otherwise.
12834 proc check_symver_available
{ } {
12835 return [check_no_compiler_messages symver_available object
{
12836 int foo
(void
) { return 0; }
12838 asm volatile
(".symver foo,foo@VER_1, local");
12844 #
Return 1 if emitted assembly contains .ident directive.
12846 proc check_effective_target_ident_directive
{} {
12847 return [check_no_messages_and_pattern ident_directive \
12848 "(?n)^\[\t\]+\\.ident" assembly {
12853 #
Return 1 if we
're able to assemble movdiri and movdir64b
12855 proc check_effective_target_movdir { } {
12856 return [check_no_compiler_messages movdir object {
12858 foo (unsigned int *d, unsigned int s)
12860 __builtin_ia32_directstoreu_u32 (d, s);
12863 bar (void *d, const void *s)
12865 __builtin_ia32_movdir64b (d, s);
12867 } "-mmovdiri -mmovdir64b" ]
12870 # Return 1 if the target does not support address sanitizer, 0 otherwise
12872 proc check_effective_target_no_fsanitize_address {} {
12873 if ![check_no_compiler_messages fsanitize_address executable {
12874 int main (void) { return 0; }
12875 } "-fsanitize=address" ] {
12882 # Return 1 if this target supports 'R
' flag in .section directive, 0
12883 # otherwise. Cache the result.
12885 proc check_effective_target_R_flag_in_section { } {
12887 global GCC_UNDER_TEST
12889 # Need auto-host.h to check linker support.
12890 if { ![file exists ../../auto-host.h ] } {
12894 return [check_cached_effective_target R_flag_in_section {
12899 set f [open $src "w"]
12900 puts $f "#include \"../../auto-host.h\""
12901 puts $f "#if HAVE_GAS_SHF_GNU_RETAIN == 0 || HAVE_INITFINI_ARRAY_SUPPORT == 0"
12902 puts $f "# error Assembler does not support 'R
' flag in .section directive."
12906 verbose "check_effective_target_R_flag_in_section compiling testfile $src" 2
12907 set lines [${tool}_target_compile $src $obj assembly ""]
12912 if [string match "" $lines] then {
12913 verbose "check_effective_target_R_flag_in_section testfile compilation passed" 2
12916 verbose "check_effective_target_R_flag_in_section testfile compilation failed" 2
12922 # Return 1 if this target supports 'o
' flag in .section directive, 0
12923 # otherwise. Cache the result.
12925 proc check_effective_target_o_flag_in_section { } {
12927 global GCC_UNDER_TEST
12929 # Need auto-host.h to check linker support.
12930 if { ![file exists ../../auto-host.h ] } {
12934 return [check_cached_effective_target o_flag_in_section {
12939 set f [open $src "w"]
12940 puts $f "#include \"../../auto-host.h\""
12941 puts $f "#if HAVE_GAS_SECTION_LINK_ORDER == 0"
12942 puts $f "# error Assembler does not support 'o
' flag in .section directive."
12946 verbose "check_effective_target_o_flag_in_section compiling testfile $src" 2
12947 set lines [${tool}_target_compile $src $obj object ""]
12952 if [string match "" $lines] then {
12953 verbose "check_effective_target_o_flag_in_section testfile compilation passed" 2
12956 verbose "check_effective_target_o_flag_in_section testfile compilation failed" 2
12962 # Return 1 if the given assembler supports hardware transactional memory
12963 # instructions with machine type Power10, 0 otherwise. Cache the result.
12965 proc check_effective_target_powerpc_as_p10_htm { } {
12967 global GCC_UNDER_TEST
12969 # Need auto-host.h to check linker support.
12970 if { ![file exists ../../auto-host.h ] } {
12974 return [check_cached_effective_target powerpc_as_p10_htm {
12979 set f [open $src "w"]
12980 puts $f "#include \"../../auto-host.h\""
12981 puts $f "#if HAVE_AS_POWER10_HTM == 0"
12982 puts $f "# error Assembler does not support htm insns with power10."
12986 verbose "check_effective_target_powerpc_as_p10_htm compiling testfile $src" 2
12987 set lines [${tool}_target_compile $src $obj object ""]
12992 if [string match "" $lines] then {
12993 verbose "check_effective_target_powerpc_as_p10_htm testfile compilation passed" 2
12996 verbose "check_effective_target_powerpc_as_p10_htm testfile compilation failed" 2
13002 # return 1 if LRA is supported.
13004 proc check_effective_target_lra { } {
13005 if { [istarget hppa*-*-*] || [istarget avr-*-*] } {
13011 # Test whether optimizations are enabled ('__OPTIMIZE__
') per the
13012 # 'current_compiler_flags
' (thus don't
cache).
13014 proc check_effective_target___OPTIMIZE__
{} {
13015 return [check_no_compiler_messages_nocache __OPTIMIZE__ assembly
{
13016 #ifndef __OPTIMIZE__
13019 /* Avoid pedwarn about empty TU.
*/
13021 } [current_compiler_flags
]]
13024 #
Return 1 if python3
(>= 3.6) is available.
13026 proc check_effective_target_recent_python3
{ } {
13027 set result
[remote_exec host
"python3 -c \"import sys; assert sys.version_info >= (3, 6)\""]
13028 set status [lindex $result
0]
13029 if { $
status == 0 } then {
13036 #
Return 1 if python3 contains a module
13038 proc check_effective_target_python3_module
{ module
} {
13039 set result
[remote_exec host
"python3 -c \"import $module\""]
13040 set status [lindex $result
0]
13041 if { $
status == 0 } then {
13048 #
Return 1 if pytest module is available
for python3.
13050 proc check_effective_target_pytest3
{ } {
13051 set result
[remote_exec host
"python3 -m pytest --color=no -rap -s --tb=no --version"]
13052 set status [lindex $result
0]
13053 if { $
status == 0 } then {
13060 proc check_effective_target_property_1_needed
{ } {
13061 return [check_no_compiler_messages property_1_needed executable
{
13062 /* Assembly code
*/
13064 #
define __PROPERTY_ALIGN
3
13066 #
define __PROPERTY_ALIGN
2
13069 .section
".note.gnu.property", "a"
13070 .p2align __PROPERTY_ALIGN
13071 .long
1f
- 0f
/* name length.
*/
13072 .long
4f
- 1f
/* data length.
*/
13073 /* NT_GNU_PROPERTY_TYPE_0.
*/
13074 .long
5 /* note type.
*/
13076 .asciz
"GNU" /* vendor name. */
13078 .p2align __PROPERTY_ALIGN
13079 /* GNU_PROPERTY_1_NEEDED.
*/
13080 .long
0xb0008000 /* pr_type.
*/
13081 .long
3f
- 2f
/* pr_datasz.
*/
13083 /* GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS.
*/
13086 .p2align __PROPERTY_ALIGN
13095 #
Return 1 if this target has prog named
"$prog", 0 otherwise.
13097 proc check_is_prog_name_available
{ prog
} {
13100 set options
[list
"additional_flags=-print-prog-name=$prog"]
13101 set output
[lindex
[$
{tool
}_target_compile
"" "" "none" $options] 0]
13103 if { $output
== $prog
} {
13110 # returns
1 if target does selects a readonly section
for const volatile variables.
13111 proc check_effective_target_const_volatile_readonly_section
{ } {
13113 if { [istarget powerpc
-*-*]
13114 ||
[check
-flags
{ "" { powerpc64-*-* } { -m32 } }] } {
13120 #
Return 1 if the CORE
-V MAC extension is available.
13121 proc check_effective_target_cv_mac
{ } {
13122 if { !([istarget riscv
*-*-*]) } {
13125 return [check_no_compiler_messages cv_mac object
{
13128 asm
("cv.mac t0, t1, t2");
13130 } "-march=rv32i_xcvmac" ]
13133 #
Return 1 if the CORE
-V ALU extension is available.
13134 proc check_effective_target_cv_alu
{ } {
13135 if { !([istarget riscv
*-*-*]) } {
13138 return [check_no_compiler_messages cv_alu object
{
13141 asm
("cv.addn t0, t1, t2, 0");
13143 } "-march=rv32i_xcvalu" ]
13146 proc check_effective_target_loongarch_sx
{ } {
13147 return [check_no_compiler_messages loongarch_lsx assembly
{
13148 #
if !defined
(__loongarch_sx
)
13149 #error
"LSX not defined"
13154 proc check_effective_target_loongarch_sx_hw
{ } {
13155 return [check_runtime loongarch_sx_hw
{
13156 #
include <lsxintrin.h
>
13160 c
= __lsx_vand_v
(a
, b
);
13166 proc check_effective_target_loongarch_asx
{ } {
13167 return [check_no_compiler_messages loongarch_asx assembly
{
13168 #
if !defined
(__loongarch_asx
)
13169 #error
"LASX not defined"
13174 proc check_effective_target_loongarch_asx_hw
{ } {
13175 return [check_runtime loongarch_asx_hw
{
13176 #
include <lasxintrin.h
>
13180 c
= __lasx_xvand_v
(a
, b
);
13186 # Check whether LoongArch binutils supports call36 relocation.
13187 proc check_effective_target_loongarch_call36_support
{ } {
13188 return [check_no_compiler_messages loongarch_call36_support object
{
13189 /* Assembly code
*/
13190 pcaddu18i $r1
,%call36
(a
)
13195 # Appends necessary Python flags to extra
-tool
-flags
if Python.h is supported.
13196 # Otherwise
, modifies dg
-do-what.
13197 proc dg
-require
-python
-h
{ args } {
13198 upvar dg
-extra
-tool
-flags extra
-tool
-flags
13200 verbose
"ENTER dg-require-python-h" 2
13203 set result
[remote_exec host
"python3-config --includes"]
13204 set status [lindex $result
0]
13205 if { $
status == 0 } {
13206 # Remove trailing newline from python3
-config output.
13207 set python_flags
[string trim
[lindex $result
1]]
13208 if [check_no_compiler_messages python_h assembly
{
13209 #
include <Python.h
>
13210 int main
(void
) { return 0; }
13216 if { $supported
== 0 } {
13217 verbose
"Python.h not supported" 2
13218 upvar dg
-do-what dg
-do-what
13219 set dg
-do-what
[list
[lindex $
{dg
-do-what
} 0] "N" "P"]
13223 verbose
"Python flags are: $python_flags" 2
13225 verbose
"Before appending, extra-tool-flags: ${extra-tool-flags}" 3
13226 eval lappend extra
-tool
-flags $python_flags
13227 verbose
"After appending, extra-tool-flags: ${extra-tool-flags}" 3