1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2019 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 /* If we have non-legitimate address which is decomposed not in
363 the way we expected, don't do elimination here. In such case
364 the address will be reloaded and elimination will be done in
365 reload insn finally. */
366 if (REG_P (m_base_reg
))
367 lra_eliminate_reg_if_possible (m_base_loc
);
368 if (m_ad
->base_term2
!= NULL
)
369 *m_ad
->base_term2
= *m_ad
->base_term
;
371 if (m_index_loc
!= NULL
)
373 m_index_reg
= *m_index_loc
;
374 if (REG_P (m_index_reg
))
375 lra_eliminate_reg_if_possible (m_index_loc
);
379 address_eliminator::~address_eliminator ()
381 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
383 *m_base_loc
= m_base_reg
;
384 if (m_ad
->base_term2
!= NULL
)
385 *m_ad
->base_term2
= *m_ad
->base_term
;
387 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
388 *m_index_loc
= m_index_reg
;
391 /* Return true if the eliminated form of AD is a legitimate target address. */
393 valid_address_p (struct address_info
*ad
)
395 address_eliminator
eliminator (ad
);
396 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
399 /* Return true if the eliminated form of memory reference OP satisfies
400 extra (special) memory constraint CONSTRAINT. */
402 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
404 struct address_info ad
;
406 decompose_mem_address (&ad
, op
);
407 address_eliminator
eliminator (&ad
);
408 return constraint_satisfied_p (op
, constraint
);
411 /* Return true if the eliminated form of address AD satisfies extra
412 address constraint CONSTRAINT. */
414 satisfies_address_constraint_p (struct address_info
*ad
,
415 enum constraint_num constraint
)
417 address_eliminator
eliminator (ad
);
418 return constraint_satisfied_p (*ad
->outer
, constraint
);
421 /* Return true if the eliminated form of address OP satisfies extra
422 address constraint CONSTRAINT. */
424 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
426 struct address_info ad
;
428 decompose_lea_address (&ad
, &op
);
429 return satisfies_address_constraint_p (&ad
, constraint
);
432 /* Initiate equivalences for LRA. As we keep original equivalences
433 before any elimination, we need to make copies otherwise any change
434 in insns might change the equivalences. */
436 lra_init_equiv (void)
438 ira_expand_reg_equiv ();
439 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
443 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
444 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
445 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
446 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
450 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
452 /* Update equivalence for REGNO. We need to this as the equivalence
453 might contain other pseudos which are changed by their
456 update_equiv (int regno
)
460 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
461 ira_reg_equiv
[regno
].memory
462 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
465 ira_reg_equiv
[regno
].invariant
466 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
470 /* If we have decided to substitute X with another value, return that
471 value, otherwise return X. */
478 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
479 || ! ira_reg_equiv
[regno
].defined_p
480 || ! ira_reg_equiv
[regno
].profitable_p
481 || lra_get_regno_hard_regno (regno
) >= 0)
483 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
485 if (targetm
.cannot_substitute_mem_equiv_p (res
))
489 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
491 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
496 /* If we have decided to substitute X with the equivalent value,
497 return that value after elimination for INSN, otherwise return
500 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
502 rtx res
= get_equiv (x
);
504 if (x
== res
|| CONSTANT_P (res
))
506 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
507 false, false, 0, true);
510 /* Set up curr_operand_mode. */
512 init_curr_operand_mode (void)
514 int nop
= curr_static_id
->n_operands
;
515 for (int i
= 0; i
< nop
; i
++)
517 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
518 if (mode
== VOIDmode
)
520 /* The .md mode for address operands is the mode of the
521 addressed value rather than the mode of the address itself. */
522 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
525 mode
= curr_static_id
->operand
[i
].mode
;
527 curr_operand_mode
[i
] = mode
;
533 /* The page contains code to reuse input reloads. */
535 /* Structure describes input reload of the current insns. */
538 /* True for input reload of matched operands. */
540 /* Reloaded value. */
542 /* Reload pseudo used. */
546 /* The number of elements in the following array. */
547 static int curr_insn_input_reloads_num
;
548 /* Array containing info about input reloads. It is used to find the
549 same input reload and reuse the reload pseudo in this case. */
550 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
552 /* Initiate data concerning reuse of input reloads for the current
555 init_curr_insn_input_reloads (void)
557 curr_insn_input_reloads_num
= 0;
560 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
561 created input reload pseudo (only if TYPE is not OP_OUT). Don't
562 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
563 wrapped up in SUBREG. The result pseudo is returned through
564 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
565 reused the already created input reload pseudo. Use TITLE to
566 describe new registers for debug purposes. */
568 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
569 enum reg_class rclass
, bool in_subreg_p
,
570 const char *title
, rtx
*result_reg
)
573 enum reg_class new_class
;
574 bool unique_p
= false;
579 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
582 /* Prevent reuse value of expression with side effects,
583 e.g. volatile memory. */
584 if (! side_effects_p (original
))
585 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
587 if (! curr_insn_input_reloads
[i
].match_p
588 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
589 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
591 rtx reg
= curr_insn_input_reloads
[i
].reg
;
593 /* If input is equal to original and both are VOIDmode,
594 GET_MODE (reg) might be still different from mode.
595 Ensure we don't return *result_reg with wrong mode. */
596 if (GET_MODE (reg
) != mode
)
600 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
601 GET_MODE_SIZE (mode
)))
603 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
604 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
608 if (lra_dump_file
!= NULL
)
610 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
611 dump_value_slim (lra_dump_file
, original
, 1);
613 if (new_class
!= lra_get_allocno_class (regno
))
614 lra_change_class (regno
, new_class
, ", change to", false);
615 if (lra_dump_file
!= NULL
)
616 fprintf (lra_dump_file
, "\n");
619 /* If we have an input reload with a different mode, make sure it
620 will get a different hard reg. */
621 else if (REG_P (original
)
622 && REG_P (curr_insn_input_reloads
[i
].input
)
623 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
624 && (GET_MODE (original
)
625 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
628 *result_reg
= (unique_p
629 ? lra_create_new_reg_with_unique_value
630 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
631 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
632 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
633 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
634 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
639 /* The page contains major code to choose the current insn alternative
640 and generate reloads for it. */
642 /* Return the offset from REGNO of the least significant register
645 This function is used to tell whether two registers satisfy
646 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
648 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
649 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
651 lra_constraint_offset (int regno
, machine_mode mode
)
653 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
655 scalar_int_mode int_mode
;
657 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
658 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
659 return hard_regno_nregs (regno
, mode
) - 1;
663 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
664 if they are the same hard reg, and has special hacks for
665 auto-increment and auto-decrement. This is specifically intended for
666 process_alt_operands to use in determining whether two operands
667 match. X is the operand whose number is the lower of the two.
669 It is supposed that X is the output operand and Y is the input
670 operand. Y_HARD_REGNO is the final hard regno of register Y or
671 register in subreg Y as we know it now. Otherwise, it is a
674 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
677 RTX_CODE code
= GET_CODE (x
);
682 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
683 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
687 i
= get_hard_regno (x
, false);
691 if ((j
= y_hard_regno
) < 0)
694 i
+= lra_constraint_offset (i
, GET_MODE (x
));
695 j
+= lra_constraint_offset (j
, GET_MODE (y
));
700 /* If two operands must match, because they are really a single
701 operand of an assembler insn, then two post-increments are invalid
702 because the assembler insn would increment only once. On the
703 other hand, a post-increment matches ordinary indexing if the
704 post-increment is the output operand. */
705 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
706 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
708 /* Two pre-increments are invalid because the assembler insn would
709 increment only once. On the other hand, a pre-increment matches
710 ordinary indexing if the pre-increment is the input operand. */
711 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
712 || GET_CODE (y
) == PRE_MODIFY
)
713 return operands_match_p (x
, XEXP (y
, 0), -1);
717 if (code
== REG
&& REG_P (y
))
718 return REGNO (x
) == REGNO (y
);
720 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
721 && x
== SUBREG_REG (y
))
723 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
724 && SUBREG_REG (x
) == y
)
727 /* Now we have disposed of all the cases in which different rtx
729 if (code
!= GET_CODE (y
))
732 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
733 if (GET_MODE (x
) != GET_MODE (y
))
742 return label_ref_label (x
) == label_ref_label (y
);
744 return XSTR (x
, 0) == XSTR (y
, 0);
750 /* Compare the elements. If any pair of corresponding elements fail
751 to match, return false for the whole things. */
753 fmt
= GET_RTX_FORMAT (code
);
754 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
760 if (XWINT (x
, i
) != XWINT (y
, i
))
765 if (XINT (x
, i
) != XINT (y
, i
))
770 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
775 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
784 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
786 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
788 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
794 /* It is believed that rtx's at this level will never
795 contain anything but integers and other rtx's, except for
796 within LABEL_REFs and SYMBOL_REFs. */
804 /* True if X is a constant that can be forced into the constant pool.
805 MODE is the mode of the operand, or VOIDmode if not known. */
806 #define CONST_POOL_OK_P(MODE, X) \
807 ((MODE) != VOIDmode \
809 && GET_CODE (X) != HIGH \
810 && GET_MODE_SIZE (MODE).is_constant () \
811 && !targetm.cannot_force_const_mem (MODE, X))
813 /* True if C is a non-empty register class that has too few registers
814 to be safely used as a reload target class. */
815 #define SMALL_REGISTER_CLASS_P(C) \
816 (ira_class_hard_regs_num [(C)] == 1 \
817 || (ira_class_hard_regs_num [(C)] >= 1 \
818 && targetm.class_likely_spilled_p (C)))
820 /* If REG is a reload pseudo, try to make its class satisfying CL. */
822 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
824 enum reg_class rclass
;
826 /* Do not make more accurate class from reloads generated. They are
827 mostly moves with a lot of constraints. Making more accurate
828 class may results in very narrow class and impossibility of find
829 registers for several reloads of one insn. */
830 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
832 if (GET_CODE (reg
) == SUBREG
)
833 reg
= SUBREG_REG (reg
);
834 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
836 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
837 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
840 /* Searches X for any reference to a reg with the same value as REGNO,
841 returning the rtx of the reference found if any. Otherwise,
844 regno_val_use_in (unsigned int regno
, rtx x
)
850 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
853 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
854 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
858 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
861 else if (fmt
[i
] == 'E')
862 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
863 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
870 /* Return true if all current insn non-output operands except INS (it
871 has a negaitve end marker) do not use pseudos with the same value
874 check_conflict_input_operands (int regno
, signed char *ins
)
877 int n_operands
= curr_static_id
->n_operands
;
879 for (int nop
= 0; nop
< n_operands
; nop
++)
880 if (! curr_static_id
->operand
[nop
].is_operator
881 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
883 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
887 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
893 /* Generate reloads for matching OUT and INS (array of input operand
894 numbers with end marker -1) with reg class GOAL_CLASS, considering
895 output operands OUTS (similar array to INS) needing to be in different
896 registers. Add input and output reloads correspondingly to the lists
897 *BEFORE and *AFTER. OUT might be negative. In this case we generate
898 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
899 that the output operand is early clobbered for chosen alternative. */
901 match_reload (signed char out
, signed char *ins
, signed char *outs
,
902 enum reg_class goal_class
, rtx_insn
**before
,
903 rtx_insn
**after
, bool early_clobber_p
)
907 rtx new_in_reg
, new_out_reg
, reg
;
908 machine_mode inmode
, outmode
;
909 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
910 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
912 inmode
= curr_operand_mode
[ins
[0]];
913 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
914 push_to_sequence (*before
);
915 if (inmode
!= outmode
)
917 /* process_alt_operands has already checked that the mode sizes
919 if (partial_subreg_p (outmode
, inmode
))
922 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
924 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
925 LRA_SUBREG_P (new_out_reg
) = 1;
926 /* If the input reg is dying here, we can use the same hard
927 register for REG and IN_RTX. We do it only for original
928 pseudos as reload pseudos can die although original
929 pseudos still live where reload pseudos dies. */
930 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
931 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
933 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
934 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
939 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
941 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
942 /* NEW_IN_REG is non-paradoxical subreg. We don't want
943 NEW_OUT_REG living above. We add clobber clause for
944 this. This is just a temporary clobber. We can remove
945 it at the end of LRA work. */
946 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
947 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
948 LRA_SUBREG_P (new_in_reg
) = 1;
949 if (GET_CODE (in_rtx
) == SUBREG
)
951 rtx subreg_reg
= SUBREG_REG (in_rtx
);
953 /* If SUBREG_REG is dying here and sub-registers IN_RTX
954 and NEW_IN_REG are similar, we can use the same hard
955 register for REG and SUBREG_REG. */
956 if (REG_P (subreg_reg
)
957 && (int) REGNO (subreg_reg
) < lra_new_regno_start
958 && GET_MODE (subreg_reg
) == outmode
959 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
960 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
961 && (! early_clobber_p
962 || check_conflict_input_operands (REGNO (subreg_reg
),
964 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
970 /* Pseudos have values -- see comments for lra_reg_info.
971 Different pseudos with the same value do not conflict even if
972 they live in the same place. When we create a pseudo we
973 assign value of original pseudo (if any) from which we
974 created the new pseudo. If we create the pseudo from the
975 input pseudo, the new pseudo will have no conflict with the
976 input pseudo which is wrong when the input pseudo lives after
977 the insn and as the new pseudo value is changed by the insn
978 output. Therefore we create the new pseudo from the output
979 except the case when we have single matched dying input
982 We cannot reuse the current output register because we might
983 have a situation like "a <- a op b", where the constraints
984 force the second input operand ("b") to match the output
985 operand ("a"). "b" must then be copied into a new register
986 so that it doesn't clobber the current value of "a".
988 We can not use the same value if the output pseudo is
989 early clobbered or the input pseudo is mentioned in the
990 output, e.g. as an address part in memory, because
991 output reload will actually extend the pseudo liveness.
992 We don't care about eliminable hard regs here as we are
993 interesting only in pseudos. */
995 /* Matching input's register value is the same as one of the other
996 output operand. Output operands in a parallel insn must be in
997 different registers. */
998 out_conflict
= false;
1001 for (i
= 0; outs
[i
] >= 0; i
++)
1003 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1004 if (REG_P (other_out_rtx
)
1005 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1008 out_conflict
= true;
1014 new_in_reg
= new_out_reg
1015 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1016 && (int) REGNO (in_rtx
) < lra_new_regno_start
1017 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1018 && (! early_clobber_p
1019 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1021 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1023 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1024 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1027 /* In operand can be got from transformations before processing insn
1028 constraints. One example of such transformations is subreg
1029 reloading (see function simplify_operand_subreg). The new
1030 pseudos created by the transformations might have inaccurate
1031 class (ALL_REGS) and we should make their classes more
1033 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1034 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1035 *before
= get_insns ();
1037 /* Add the new pseudo to consider values of subsequent input reload
1039 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1040 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1041 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1042 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1043 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1046 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1047 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1048 *curr_id
->operand_loc
[in
] = new_in_reg
;
1050 lra_update_dups (curr_id
, ins
);
1053 /* See a comment for the input operand above. */
1054 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1055 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1058 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1060 *after
= get_insns ();
1063 *curr_id
->operand_loc
[out
] = new_out_reg
;
1064 lra_update_dup (curr_id
, out
);
1067 /* Return register class which is union of all reg classes in insn
1068 constraint alternative string starting with P. */
1069 static enum reg_class
1070 reg_class_from_constraints (const char *p
)
1073 enum reg_class op_class
= NO_REGS
;
1076 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1083 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1087 enum constraint_num cn
= lookup_constraint (p
);
1088 enum reg_class cl
= reg_class_for_constraint (cn
);
1091 if (insn_extra_address_constraint (cn
))
1093 = (reg_class_subunion
1094 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1095 ADDRESS
, SCRATCH
)]);
1099 op_class
= reg_class_subunion
[op_class
][cl
];
1102 while ((p
+= len
), c
);
1106 /* If OP is a register, return the class of the register as per
1107 get_reg_class, otherwise return NO_REGS. */
1108 static inline enum reg_class
1109 get_op_class (rtx op
)
1111 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1114 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1115 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1116 SUBREG for VAL to make them equal. */
1118 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1120 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1122 /* Usually size of mem_pseudo is greater than val size but in
1123 rare cases it can be less as it can be defined by target
1124 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1127 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1128 GET_CODE (val
) == SUBREG
1129 ? SUBREG_REG (val
) : val
);
1130 LRA_SUBREG_P (val
) = 1;
1134 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1135 LRA_SUBREG_P (mem_pseudo
) = 1;
1138 return to_p
? gen_move_insn (mem_pseudo
, val
)
1139 : gen_move_insn (val
, mem_pseudo
);
1142 /* Process a special case insn (register move), return true if we
1143 don't need to process it anymore. INSN should be a single set
1144 insn. Set up that RTL was changed through CHANGE_P and that hook
1145 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1148 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1151 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1153 enum reg_class dclass
, sclass
, secondary_class
;
1154 secondary_reload_info sri
;
1156 lra_assert (curr_insn_set
!= NULL_RTX
);
1157 dreg
= dest
= SET_DEST (curr_insn_set
);
1158 sreg
= src
= SET_SRC (curr_insn_set
);
1159 if (GET_CODE (dest
) == SUBREG
)
1160 dreg
= SUBREG_REG (dest
);
1161 if (GET_CODE (src
) == SUBREG
)
1162 sreg
= SUBREG_REG (src
);
1163 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1165 sclass
= dclass
= NO_REGS
;
1167 dclass
= get_reg_class (REGNO (dreg
));
1168 gcc_assert (dclass
< LIM_REG_CLASSES
);
1169 if (dclass
== ALL_REGS
)
1170 /* ALL_REGS is used for new pseudos created by transformations
1171 like reload of SUBREG_REG (see function
1172 simplify_operand_subreg). We don't know their class yet. We
1173 should figure out the class from processing the insn
1174 constraints not in this fast path function. Even if ALL_REGS
1175 were a right class for the pseudo, secondary_... hooks usually
1176 are not define for ALL_REGS. */
1179 sclass
= get_reg_class (REGNO (sreg
));
1180 gcc_assert (sclass
< LIM_REG_CLASSES
);
1181 if (sclass
== ALL_REGS
)
1182 /* See comments above. */
1184 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1186 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1187 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1189 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1194 if (! REG_P (dreg
) || ! REG_P (sreg
))
1196 sri
.prev_sri
= NULL
;
1197 sri
.icode
= CODE_FOR_nothing
;
1199 secondary_class
= NO_REGS
;
1200 /* Set up hard register for a reload pseudo for hook
1201 secondary_reload because some targets just ignore unassigned
1202 pseudos in the hook. */
1203 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1205 dregno
= REGNO (dreg
);
1206 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1210 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1212 sregno
= REGNO (sreg
);
1213 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1217 if (sclass
!= NO_REGS
)
1219 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1220 (reg_class_t
) sclass
,
1221 GET_MODE (src
), &sri
);
1222 if (sclass
== NO_REGS
1223 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1224 && dclass
!= NO_REGS
))
1226 enum reg_class old_sclass
= secondary_class
;
1227 secondary_reload_info old_sri
= sri
;
1229 sri
.prev_sri
= NULL
;
1230 sri
.icode
= CODE_FOR_nothing
;
1233 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1234 (reg_class_t
) dclass
,
1235 GET_MODE (src
), &sri
);
1236 /* Check the target hook consistency. */
1238 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1239 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1240 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1243 reg_renumber
[sregno
] = -1;
1245 reg_renumber
[dregno
] = -1;
1246 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1250 if (secondary_class
!= NO_REGS
)
1251 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1255 if (sri
.icode
== CODE_FOR_nothing
)
1256 lra_emit_move (new_reg
, src
);
1259 enum reg_class scratch_class
;
1261 scratch_class
= (reg_class_from_constraints
1262 (insn_data
[sri
.icode
].operand
[2].constraint
));
1263 scratch_reg
= (lra_create_new_reg_with_unique_value
1264 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1265 scratch_class
, "scratch"));
1266 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1269 before
= get_insns ();
1271 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1272 if (new_reg
!= NULL_RTX
)
1273 SET_SRC (curr_insn_set
) = new_reg
;
1276 if (lra_dump_file
!= NULL
)
1278 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1279 dump_insn_slim (lra_dump_file
, curr_insn
);
1281 lra_set_insn_deleted (curr_insn
);
1287 /* The following data describe the result of process_alt_operands.
1288 The data are used in curr_insn_transform to generate reloads. */
1290 /* The chosen reg classes which should be used for the corresponding
1292 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1293 /* True if the operand should be the same as another operand and that
1294 other operand does not need a reload. */
1295 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1296 /* True if the operand does not need a reload. */
1297 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1298 /* True if the operand can be offsetable memory. */
1299 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1300 /* The number of an operand to which given operand can be matched to. */
1301 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1302 /* The number of elements in the following array. */
1303 static int goal_alt_dont_inherit_ops_num
;
1304 /* Numbers of operands whose reload pseudos should not be inherited. */
1305 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1306 /* True if the insn commutative operands should be swapped. */
1307 static bool goal_alt_swapped
;
1308 /* The chosen insn alternative. */
1309 static int goal_alt_number
;
1311 /* True if the corresponding operand is the result of an equivalence
1313 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1315 /* The following five variables are used to choose the best insn
1316 alternative. They reflect final characteristics of the best
1319 /* Number of necessary reloads and overall cost reflecting the
1320 previous value and other unpleasantness of the best alternative. */
1321 static int best_losers
, best_overall
;
1322 /* Overall number hard registers used for reloads. For example, on
1323 some targets we need 2 general registers to reload DFmode and only
1324 one floating point register. */
1325 static int best_reload_nregs
;
1326 /* Overall number reflecting distances of previous reloading the same
1327 value. The distances are counted from the current BB start. It is
1328 used to improve inheritance chances. */
1329 static int best_reload_sum
;
1331 /* True if the current insn should have no correspondingly input or
1333 static bool no_input_reloads_p
, no_output_reloads_p
;
1335 /* True if we swapped the commutative operands in the current
1337 static int curr_swapped
;
1339 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1340 register of class CL. Add any input reloads to list BEFORE. AFTER
1341 is nonnull if *LOC is an automodified value; handle that case by
1342 adding the required output reloads to list AFTER. Return true if
1343 the RTL was changed.
1345 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1346 register. Return false if the address register is correct. */
1348 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1352 enum reg_class rclass
, new_class
;
1356 bool subreg_p
, before_p
= false;
1358 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1361 reg
= SUBREG_REG (*loc
);
1362 mode
= GET_MODE (reg
);
1364 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1365 between two registers with different classes, but there normally will
1366 be "mov" which transfers element of vector register into the general
1367 register, and this normally will be a subreg which should be reloaded
1368 as a whole. This is particularly likely to be triggered when
1369 -fno-split-wide-types specified. */
1371 || in_class_p (reg
, cl
, &new_class
)
1372 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1373 loc
= &SUBREG_REG (*loc
);
1377 mode
= GET_MODE (reg
);
1382 /* Always reload memory in an address even if the target supports
1384 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1389 regno
= REGNO (reg
);
1390 rclass
= get_reg_class (regno
);
1392 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1394 if (lra_dump_file
!= NULL
)
1396 fprintf (lra_dump_file
,
1397 "Changing pseudo %d in address of insn %u on equiv ",
1398 REGNO (reg
), INSN_UID (curr_insn
));
1399 dump_value_slim (lra_dump_file
, *loc
, 1);
1400 fprintf (lra_dump_file
, "\n");
1402 *loc
= copy_rtx (*loc
);
1404 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1409 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1410 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1413 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1417 lra_change_class (regno
, new_class
, " Change to", true);
1425 push_to_sequence (*before
);
1426 lra_emit_move (new_reg
, reg
);
1427 *before
= get_insns ();
1434 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1436 *after
= get_insns ();
1442 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1443 the insn to be inserted before curr insn. AFTER returns the
1444 the insn to be inserted after curr insn. ORIGREG and NEWREG
1445 are the original reg and new reg for reload. */
1447 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1452 push_to_sequence (*before
);
1453 lra_emit_move (newreg
, origreg
);
1454 *before
= get_insns ();
1460 lra_emit_move (origreg
, newreg
);
1462 *after
= get_insns ();
1467 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1468 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1470 /* Make reloads for subreg in operand NOP with internal subreg mode
1471 REG_MODE, add new reloads for further processing. Return true if
1472 any change was done. */
1474 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1477 rtx_insn
*before
, *after
;
1478 machine_mode mode
, innermode
;
1480 rtx operand
= *curr_id
->operand_loc
[nop
];
1481 enum reg_class regclass
;
1484 before
= after
= NULL
;
1486 if (GET_CODE (operand
) != SUBREG
)
1489 mode
= GET_MODE (operand
);
1490 reg
= SUBREG_REG (operand
);
1491 innermode
= GET_MODE (reg
);
1492 type
= curr_static_id
->operand
[nop
].type
;
1495 const bool addr_was_valid
1496 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1497 alter_subreg (curr_id
->operand_loc
[nop
], false);
1498 rtx subst
= *curr_id
->operand_loc
[nop
];
1499 lra_assert (MEM_P (subst
));
1502 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1503 MEM_ADDR_SPACE (subst
))
1504 || ((get_constraint_type (lookup_constraint
1505 (curr_static_id
->operand
[nop
].constraint
))
1506 != CT_SPECIAL_MEMORY
)
1507 /* We still can reload address and if the address is
1508 valid, we can remove subreg without reloading its
1510 && valid_address_p (GET_MODE (subst
),
1512 [ira_class_hard_regs
1513 [base_reg_class (GET_MODE (subst
),
1514 MEM_ADDR_SPACE (subst
),
1515 ADDRESS
, SCRATCH
)][0]],
1516 MEM_ADDR_SPACE (subst
))))
1518 /* If we change the address for a paradoxical subreg of memory, the
1519 new address might violate the necessary alignment or the access
1520 might be slow; take this into consideration. We need not worry
1521 about accesses beyond allocated memory for paradoxical memory
1522 subregs as we don't substitute such equiv memory (see processing
1523 equivalences in function lra_constraints) and because for spilled
1524 pseudos we allocate stack memory enough for the biggest
1525 corresponding paradoxical subreg.
1527 However, do not blindly simplify a (subreg (mem ...)) for
1528 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1529 data into a register when the inner is narrower than outer or
1530 missing important data from memory when the inner is wider than
1531 outer. This rule only applies to modes that are no wider than
1533 if (!(maybe_ne (GET_MODE_PRECISION (mode
),
1534 GET_MODE_PRECISION (innermode
))
1535 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1536 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1537 && WORD_REGISTER_OPERATIONS
)
1538 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1539 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1540 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1541 && targetm
.slow_unaligned_access (innermode
,
1545 *curr_id
->operand_loc
[nop
] = operand
;
1547 /* But if the address was not valid, we cannot reload the MEM without
1548 reloading the address first. */
1549 if (!addr_was_valid
)
1550 process_address (nop
, false, &before
, &after
);
1552 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1553 enum reg_class rclass
1554 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1555 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1556 reg
, rclass
, TRUE
, "slow mem", &new_reg
))
1558 bool insert_before
, insert_after
;
1559 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1561 insert_before
= (type
!= OP_OUT
1562 || partial_subreg_p (mode
, innermode
));
1563 insert_after
= type
!= OP_IN
;
1564 insert_move_for_subreg (insert_before
? &before
: NULL
,
1565 insert_after
? &after
: NULL
,
1568 SUBREG_REG (operand
) = new_reg
;
1570 /* Convert to MODE. */
1573 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1574 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1575 rclass
, TRUE
, "slow mem", &new_reg
))
1577 bool insert_before
, insert_after
;
1578 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1580 insert_before
= type
!= OP_OUT
;
1581 insert_after
= type
!= OP_IN
;
1582 insert_move_for_subreg (insert_before
? &before
: NULL
,
1583 insert_after
? &after
: NULL
,
1586 *curr_id
->operand_loc
[nop
] = new_reg
;
1587 lra_process_new_insns (curr_insn
, before
, after
,
1588 "Inserting slow mem reload");
1592 /* If the address was valid and became invalid, prefer to reload
1593 the memory. Typical case is when the index scale should
1594 correspond the memory. */
1595 *curr_id
->operand_loc
[nop
] = operand
;
1596 /* Do not return false here as the MEM_P (reg) will be processed
1597 later in this function. */
1599 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1601 alter_subreg (curr_id
->operand_loc
[nop
], false);
1604 else if (CONSTANT_P (reg
))
1606 /* Try to simplify subreg of constant. It is usually result of
1607 equivalence substitution. */
1608 if (innermode
== VOIDmode
1609 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1610 innermode
= curr_static_id
->operand
[nop
].mode
;
1611 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1612 SUBREG_BYTE (operand
))) != NULL_RTX
)
1614 *curr_id
->operand_loc
[nop
] = new_reg
;
1618 /* Put constant into memory when we have mixed modes. It generates
1619 a better code in most cases as it does not need a secondary
1620 reload memory. It also prevents LRA looping when LRA is using
1621 secondary reload memory again and again. */
1622 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1623 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1625 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1626 alter_subreg (curr_id
->operand_loc
[nop
], false);
1629 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1630 if there may be a problem accessing OPERAND in the outer
1633 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1634 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1635 /* Don't reload paradoxical subregs because we could be looping
1636 having repeatedly final regno out of hard regs range. */
1637 && (hard_regno_nregs (hard_regno
, innermode
)
1638 >= hard_regno_nregs (hard_regno
, mode
))
1639 && simplify_subreg_regno (hard_regno
, innermode
,
1640 SUBREG_BYTE (operand
), mode
) < 0
1641 /* Don't reload subreg for matching reload. It is actually
1642 valid subreg in LRA. */
1643 && ! LRA_SUBREG_P (operand
))
1644 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1646 enum reg_class rclass
;
1649 /* There is a big probability that we will get the same class
1650 for the new pseudo and we will get the same insn which
1651 means infinite looping. So spill the new pseudo. */
1654 /* The class will be defined later in curr_insn_transform. */
1656 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1658 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1659 rclass
, TRUE
, "subreg reg", &new_reg
))
1661 bool insert_before
, insert_after
;
1662 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1664 insert_before
= (type
!= OP_OUT
1665 || read_modify_subreg_p (operand
));
1666 insert_after
= (type
!= OP_IN
);
1667 insert_move_for_subreg (insert_before
? &before
: NULL
,
1668 insert_after
? &after
: NULL
,
1671 SUBREG_REG (operand
) = new_reg
;
1672 lra_process_new_insns (curr_insn
, before
, after
,
1673 "Inserting subreg reload");
1676 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1677 IRA allocates hardreg to the inner pseudo reg according to its mode
1678 instead of the outermode, so the size of the hardreg may not be enough
1679 to contain the outermode operand, in that case we may need to insert
1680 reload for the reg. For the following two types of paradoxical subreg,
1681 we need to insert reload:
1682 1. If the op_type is OP_IN, and the hardreg could not be paired with
1683 other hardreg to contain the outermode operand
1684 (checked by in_hard_reg_set_p), we need to insert the reload.
1685 2. If the op_type is OP_OUT or OP_INOUT.
1687 Here is a paradoxical subreg example showing how the reload is generated:
1689 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1690 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1692 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1693 here, if reg107 is assigned to hardreg R15, because R15 is the last
1694 hardreg, compiler cannot find another hardreg to pair with R15 to
1695 contain TImode data. So we insert a TImode reload reg180 for it.
1696 After reload is inserted:
1698 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1699 (reg:DI 107 [ __comp ])) -1
1700 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1701 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1703 Two reload hard registers will be allocated to reg180 to save TImode data
1706 For LRA pseudos this should normally be handled by the biggest_mode
1707 mechanism. However, it's possible for new uses of an LRA pseudo
1708 to be introduced after we've allocated it, such as when undoing
1709 inheritance, and the allocated register might not then be appropriate
1710 for the new uses. */
1711 else if (REG_P (reg
)
1712 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1713 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1714 && (hard_regno_nregs (hard_regno
, innermode
)
1715 < hard_regno_nregs (hard_regno
, mode
))
1716 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1718 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1720 || overlaps_hard_reg_set_p (lra_no_alloc_regs
,
1723 /* The class will be defined later in curr_insn_transform. */
1724 enum reg_class rclass
1725 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1727 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1728 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1731 bool insert_before
, insert_after
;
1733 PUT_MODE (new_reg
, mode
);
1734 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1735 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1737 insert_before
= (type
!= OP_OUT
);
1738 insert_after
= (type
!= OP_IN
);
1739 insert_move_for_subreg (insert_before
? &before
: NULL
,
1740 insert_after
? &after
: NULL
,
1743 SUBREG_REG (operand
) = new_reg
;
1744 lra_process_new_insns (curr_insn
, before
, after
,
1745 "Inserting paradoxical subreg reload");
1751 /* Return TRUE if X refers for a hard register from SET. */
1753 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1755 int i
, j
, x_hard_regno
;
1762 code
= GET_CODE (x
);
1763 mode
= GET_MODE (x
);
1766 mode
= wider_subreg_mode (x
);
1768 code
= GET_CODE (x
);
1773 x_hard_regno
= get_hard_regno (x
, true);
1774 return (x_hard_regno
>= 0
1775 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1779 struct address_info ad
;
1781 decompose_mem_address (&ad
, x
);
1782 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1784 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1787 fmt
= GET_RTX_FORMAT (code
);
1788 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1792 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1795 else if (fmt
[i
] == 'E')
1797 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1798 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1805 /* Return true if OP is a spilled pseudo. */
1807 spilled_pseudo_p (rtx op
)
1810 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1813 /* Return true if X is a general constant. */
1815 general_constant_p (rtx x
)
1817 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1821 reg_in_class_p (rtx reg
, enum reg_class cl
)
1824 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1825 return in_class_p (reg
, cl
, NULL
);
1828 /* Return true if SET of RCLASS contains no hard regs which can be
1831 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1837 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1838 COPY_HARD_REG_SET (temp
, set
);
1839 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1840 return (hard_reg_set_subset_p
1841 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1845 /* Used to check validity info about small class input operands. It
1846 should be incremented at start of processing an insn
1848 static unsigned int curr_small_class_check
= 0;
1850 /* Update number of used inputs of class OP_CLASS for operand NOP.
1851 Return true if we have more such class operands than the number of
1854 update_and_check_small_class_inputs (int nop
, enum reg_class op_class
)
1856 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1857 static int small_class_input_nums
[LIM_REG_CLASSES
];
1859 if (SMALL_REGISTER_CLASS_P (op_class
)
1860 /* We are interesting in classes became small because of fixing
1861 some hard regs, e.g. by an user through GCC options. */
1862 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
1864 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
1865 || curr_static_id
->operand
[nop
].early_clobber
))
1867 if (small_class_check
[op_class
] == curr_small_class_check
)
1868 small_class_input_nums
[op_class
]++;
1871 small_class_check
[op_class
] = curr_small_class_check
;
1872 small_class_input_nums
[op_class
] = 1;
1874 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
1880 /* Major function to choose the current insn alternative and what
1881 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1882 negative we should consider only this alternative. Return false if
1883 we can not choose the alternative or find how to reload the
1886 process_alt_operands (int only_alternative
)
1889 int nop
, overall
, nalt
;
1890 int n_alternatives
= curr_static_id
->n_alternatives
;
1891 int n_operands
= curr_static_id
->n_operands
;
1892 /* LOSERS counts the operands that don't fit this alternative and
1893 would require loading. */
1896 /* REJECT is a count of how undesirable this alternative says it is
1897 if any reloading is required. If the alternative matches exactly
1898 then REJECT is ignored, but otherwise it gets this much counted
1899 against it in addition to the reloading needed. */
1901 /* This is defined by '!' or '?' alternative constraint and added to
1902 reject. But in some cases it can be ignored. */
1905 /* The number of elements in the following array. */
1906 int early_clobbered_regs_num
;
1907 /* Numbers of operands which are early clobber registers. */
1908 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1909 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1910 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1911 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1912 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1913 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1914 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1915 /* The number of elements in the following array. */
1916 int curr_alt_dont_inherit_ops_num
;
1917 /* Numbers of operands whose reload pseudos should not be inherited. */
1918 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1920 /* The register when the operand is a subreg of register, otherwise the
1922 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1923 /* The register if the operand is a register or subreg of register,
1925 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1926 int hard_regno
[MAX_RECOG_OPERANDS
];
1927 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1928 int reload_nregs
, reload_sum
;
1932 /* Calculate some data common for all alternatives to speed up the
1934 for (nop
= 0; nop
< n_operands
; nop
++)
1938 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1939 /* The real hard regno of the operand after the allocation. */
1940 hard_regno
[nop
] = get_hard_regno (op
, true);
1942 operand_reg
[nop
] = reg
= op
;
1943 biggest_mode
[nop
] = GET_MODE (op
);
1944 if (GET_CODE (op
) == SUBREG
)
1946 biggest_mode
[nop
] = wider_subreg_mode (op
);
1947 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1950 operand_reg
[nop
] = NULL_RTX
;
1951 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1952 || ((int) REGNO (reg
)
1953 == lra_get_elimination_hard_regno (REGNO (reg
))))
1954 no_subreg_reg_operand
[nop
] = reg
;
1956 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1957 /* Just use natural mode for elimination result. It should
1958 be enough for extra constraints hooks. */
1959 = regno_reg_rtx
[hard_regno
[nop
]];
1962 /* The constraints are made of several alternatives. Each operand's
1963 constraint looks like foo,bar,... with commas separating the
1964 alternatives. The first alternatives for all operands go
1965 together, the second alternatives go together, etc.
1967 First loop over alternatives. */
1968 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1969 if (only_alternative
>= 0)
1970 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1972 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1974 /* Loop over operands for one constraint alternative. */
1975 if (!TEST_BIT (preferred
, nalt
))
1978 bool matching_early_clobber
[MAX_RECOG_OPERANDS
];
1979 curr_small_class_check
++;
1980 overall
= losers
= addr_losers
= 0;
1981 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
1982 for (nop
= 0; nop
< n_operands
; nop
++)
1984 int inc
= (curr_static_id
1985 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1986 if (lra_dump_file
!= NULL
&& inc
!= 0)
1987 fprintf (lra_dump_file
,
1988 " Staticly defined alt reject+=%d\n", inc
);
1989 static_reject
+= inc
;
1990 matching_early_clobber
[nop
] = 0;
1992 reject
+= static_reject
;
1993 early_clobbered_regs_num
= 0;
1995 for (nop
= 0; nop
< n_operands
; nop
++)
1999 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2000 bool win
, did_match
, offmemok
, early_clobber_p
;
2001 /* false => this operand can be reloaded somehow for this
2004 /* true => this operand can be reloaded if the alternative
2007 /* True if a constant forced into memory would be OK for
2010 enum reg_class this_alternative
, this_costly_alternative
;
2011 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2012 bool this_alternative_match_win
, this_alternative_win
;
2013 bool this_alternative_offmemok
;
2016 enum constraint_num cn
;
2018 opalt_num
= nalt
* n_operands
+ nop
;
2019 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2021 /* Fast track for no constraints at all. */
2022 curr_alt
[nop
] = NO_REGS
;
2023 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2024 curr_alt_win
[nop
] = true;
2025 curr_alt_match_win
[nop
] = false;
2026 curr_alt_offmemok
[nop
] = false;
2027 curr_alt_matches
[nop
] = -1;
2031 op
= no_subreg_reg_operand
[nop
];
2032 mode
= curr_operand_mode
[nop
];
2034 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2037 early_clobber_p
= false;
2038 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2040 this_costly_alternative
= this_alternative
= NO_REGS
;
2041 /* We update set of possible hard regs besides its class
2042 because reg class might be inaccurate. For example,
2043 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2044 is translated in HI_REGS because classes are merged by
2045 pairs and there is no accurate intermediate class. */
2046 CLEAR_HARD_REG_SET (this_alternative_set
);
2047 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2048 this_alternative_win
= false;
2049 this_alternative_match_win
= false;
2050 this_alternative_offmemok
= false;
2051 this_alternative_matches
= -1;
2053 /* An empty constraint should be excluded by the fast
2055 lra_assert (*p
!= 0 && *p
!= ',');
2058 /* Scan this alternative's specs for this operand; set WIN
2059 if the operand fits any letter in this alternative.
2060 Otherwise, clear BADOP if this operand could fit some
2061 letter after reloads, or set WINREG if this operand could
2062 fit after reloads provided the constraint allows some
2067 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2077 early_clobber_p
= true;
2081 op_reject
+= LRA_MAX_REJECT
;
2084 op_reject
+= LRA_LOSER_COST_FACTOR
;
2088 /* Ignore rest of this alternative. */
2092 case '0': case '1': case '2': case '3': case '4':
2093 case '5': case '6': case '7': case '8': case '9':
2098 m
= strtoul (p
, &end
, 10);
2101 lra_assert (nop
> m
);
2103 /* Reject matches if we don't know which operand is
2104 bigger. This situation would arguably be a bug in
2105 an .md pattern, but could also occur in a user asm. */
2106 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2107 GET_MODE_SIZE (biggest_mode
[nop
])))
2110 /* Don't match wrong asm insn operands for proper
2111 diagnostic later. */
2112 if (INSN_CODE (curr_insn
) < 0
2113 && (curr_operand_mode
[m
] == BLKmode
2114 || curr_operand_mode
[nop
] == BLKmode
)
2115 && curr_operand_mode
[m
] != curr_operand_mode
[nop
])
2118 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2119 /* We are supposed to match a previous operand.
2120 If we do, we win if that one did. If we do
2121 not, count both of the operands as losers.
2122 (This is too conservative, since most of the
2123 time only a single reload insn will be needed
2124 to make the two operands win. As a result,
2125 this alternative may be rejected when it is
2126 actually desirable.) */
2128 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2129 *curr_id
->operand_loc
[m
], m_hregno
))
2131 /* We should reject matching of an early
2132 clobber operand if the matching operand is
2133 not dying in the insn. */
2134 if (! curr_static_id
->operand
[m
].early_clobber
2135 || operand_reg
[nop
] == NULL_RTX
2136 || (find_regno_note (curr_insn
, REG_DEAD
,
2138 || REGNO (op
) == REGNO (operand_reg
[m
])))
2143 /* If we are matching a non-offsettable
2144 address where an offsettable address was
2145 expected, then we must reject this
2146 combination, because we can't reload
2148 if (curr_alt_offmemok
[m
]
2149 && MEM_P (*curr_id
->operand_loc
[m
])
2150 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2155 /* Operands don't match. If the operands are
2156 different user defined explicit hard registers,
2157 then we cannot make them match. */
2158 if ((REG_P (*curr_id
->operand_loc
[nop
])
2159 || SUBREG_P (*curr_id
->operand_loc
[nop
]))
2160 && (REG_P (*curr_id
->operand_loc
[m
])
2161 || SUBREG_P (*curr_id
->operand_loc
[m
])))
2163 rtx nop_reg
= *curr_id
->operand_loc
[nop
];
2164 if (SUBREG_P (nop_reg
))
2165 nop_reg
= SUBREG_REG (nop_reg
);
2166 rtx m_reg
= *curr_id
->operand_loc
[m
];
2167 if (SUBREG_P (m_reg
))
2168 m_reg
= SUBREG_REG (m_reg
);
2171 && HARD_REGISTER_P (nop_reg
)
2172 && REG_USERVAR_P (nop_reg
)
2174 && HARD_REGISTER_P (m_reg
)
2175 && REG_USERVAR_P (m_reg
))
2179 /* Both operands must allow a reload register,
2180 otherwise we cannot make them match. */
2181 if (curr_alt
[m
] == NO_REGS
)
2183 /* Retroactively mark the operand we had to
2184 match as a loser, if it wasn't already and
2185 it wasn't matched to a register constraint
2186 (e.g it might be matched by memory). */
2188 && (operand_reg
[m
] == NULL_RTX
2189 || hard_regno
[m
] < 0))
2193 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2194 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2197 /* Prefer matching earlyclobber alternative as
2198 it results in less hard regs required for
2199 the insn than a non-matching earlyclobber
2201 if (curr_static_id
->operand
[m
].early_clobber
)
2203 if (lra_dump_file
!= NULL
)
2206 " %d Matching earlyclobber alt:"
2209 if (!matching_early_clobber
[m
])
2212 matching_early_clobber
[m
] = 1;
2215 /* Otherwise we prefer no matching
2216 alternatives because it gives more freedom
2218 else if (operand_reg
[nop
] == NULL_RTX
2219 || (find_regno_note (curr_insn
, REG_DEAD
,
2220 REGNO (operand_reg
[nop
]))
2223 if (lra_dump_file
!= NULL
)
2226 " %d Matching alt: reject+=2\n",
2231 /* If we have to reload this operand and some
2232 previous operand also had to match the same
2233 thing as this operand, we don't know how to do
2235 if (!match_p
|| !curr_alt_win
[m
])
2237 for (i
= 0; i
< nop
; i
++)
2238 if (curr_alt_matches
[i
] == m
)
2246 this_alternative_matches
= m
;
2247 /* This can be fixed with reloads if the operand
2248 we are supposed to match can be fixed with
2251 this_alternative
= curr_alt
[m
];
2252 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2253 winreg
= this_alternative
!= NO_REGS
;
2259 || general_constant_p (op
)
2260 || spilled_pseudo_p (op
))
2266 cn
= lookup_constraint (p
);
2267 switch (get_constraint_type (cn
))
2270 cl
= reg_class_for_constraint (cn
);
2276 if (CONST_INT_P (op
)
2277 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2283 && satisfies_memory_constraint_p (op
, cn
))
2285 else if (spilled_pseudo_p (op
))
2288 /* If we didn't already win, we can reload constants
2289 via force_const_mem or put the pseudo value into
2290 memory, or make other memory by reloading the
2291 address like for 'o'. */
2292 if (CONST_POOL_OK_P (mode
, op
)
2293 || MEM_P (op
) || REG_P (op
)
2294 /* We can restore the equiv insn by a
2296 || equiv_substition_p
[nop
])
2303 /* An asm operand with an address constraint
2304 that doesn't satisfy address_operand has
2305 is_address cleared, so that we don't try to
2306 make a non-address fit. */
2307 if (!curr_static_id
->operand
[nop
].is_address
)
2309 /* If we didn't already win, we can reload the address
2310 into a base register. */
2311 if (satisfies_address_constraint_p (op
, cn
))
2313 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2319 if (constraint_satisfied_p (op
, cn
))
2323 case CT_SPECIAL_MEMORY
:
2325 && satisfies_memory_constraint_p (op
, cn
))
2327 else if (spilled_pseudo_p (op
))
2334 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2335 IOR_HARD_REG_SET (this_alternative_set
,
2336 reg_class_contents
[cl
]);
2339 this_costly_alternative
2340 = reg_class_subunion
[this_costly_alternative
][cl
];
2341 IOR_HARD_REG_SET (this_costly_alternative_set
,
2342 reg_class_contents
[cl
]);
2344 if (mode
== BLKmode
)
2349 if (hard_regno
[nop
] >= 0
2350 && in_hard_reg_set_p (this_alternative_set
,
2351 mode
, hard_regno
[nop
]))
2353 else if (hard_regno
[nop
] < 0
2354 && in_class_p (op
, this_alternative
, NULL
))
2359 if (c
!= ' ' && c
!= '\t')
2360 costly_p
= c
== '*';
2362 while ((p
+= len
), c
);
2364 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2365 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2366 /* Record which operands fit this alternative. */
2369 this_alternative_win
= true;
2370 if (operand_reg
[nop
] != NULL_RTX
)
2372 if (hard_regno
[nop
] >= 0)
2374 if (in_hard_reg_set_p (this_costly_alternative_set
,
2375 mode
, hard_regno
[nop
]))
2377 if (lra_dump_file
!= NULL
)
2378 fprintf (lra_dump_file
,
2379 " %d Costly set: reject++\n",
2386 /* Prefer won reg to spilled pseudo under other
2387 equal conditions for possibe inheritance. */
2390 if (lra_dump_file
!= NULL
)
2393 " %d Non pseudo reload: reject++\n",
2397 if (in_class_p (operand_reg
[nop
],
2398 this_costly_alternative
, NULL
))
2400 if (lra_dump_file
!= NULL
)
2403 " %d Non pseudo costly reload:"
2409 /* We simulate the behavior of old reload here.
2410 Although scratches need hard registers and it
2411 might result in spilling other pseudos, no reload
2412 insns are generated for the scratches. So it
2413 might cost something but probably less than old
2414 reload pass believes. */
2417 if (lra_dump_file
!= NULL
)
2418 fprintf (lra_dump_file
,
2419 " %d Scratch win: reject+=2\n",
2426 this_alternative_match_win
= true;
2429 int const_to_mem
= 0;
2432 reject
+= op_reject
;
2433 /* Never do output reload of stack pointer. It makes
2434 impossible to do elimination when SP is changed in
2436 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2437 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2440 /* If this alternative asks for a specific reg class, see if there
2441 is at least one allocatable register in that class. */
2443 = (this_alternative
== NO_REGS
2444 || (hard_reg_set_subset_p
2445 (reg_class_contents
[this_alternative
],
2446 lra_no_alloc_regs
)));
2448 /* For asms, verify that the class for this alternative is possible
2449 for the mode that is specified. */
2450 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2453 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2454 if (targetm
.hard_regno_mode_ok (i
, mode
)
2455 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2458 if (i
== FIRST_PSEUDO_REGISTER
)
2462 /* If this operand accepts a register, and if the
2463 register class has at least one allocatable register,
2464 then this operand can be reloaded. */
2465 if (winreg
&& !no_regs_p
)
2470 if (lra_dump_file
!= NULL
)
2471 fprintf (lra_dump_file
,
2472 " alt=%d: Bad operand -- refuse\n",
2477 if (this_alternative
!= NO_REGS
)
2479 HARD_REG_SET available_regs
;
2481 COPY_HARD_REG_SET (available_regs
,
2482 reg_class_contents
[this_alternative
]);
2483 AND_COMPL_HARD_REG_SET
2485 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2486 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2487 if (hard_reg_set_empty_p (available_regs
))
2489 /* There are no hard regs holding a value of given
2493 this_alternative
= NO_REGS
;
2494 if (lra_dump_file
!= NULL
)
2495 fprintf (lra_dump_file
,
2496 " %d Using memory because of"
2497 " a bad mode: reject+=2\n",
2503 if (lra_dump_file
!= NULL
)
2504 fprintf (lra_dump_file
,
2505 " alt=%d: Wrong mode -- refuse\n",
2512 /* If not assigned pseudo has a class which a subset of
2513 required reg class, it is a less costly alternative
2514 as the pseudo still can get a hard reg of necessary
2516 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2517 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2518 && ira_class_subset_p
[this_alternative
][cl
])
2520 if (lra_dump_file
!= NULL
)
2523 " %d Super set class reg: reject-=3\n", nop
);
2527 this_alternative_offmemok
= offmemok
;
2528 if (this_costly_alternative
!= NO_REGS
)
2530 if (lra_dump_file
!= NULL
)
2531 fprintf (lra_dump_file
,
2532 " %d Costly loser: reject++\n", nop
);
2535 /* If the operand is dying, has a matching constraint,
2536 and satisfies constraints of the matched operand
2537 which failed to satisfy the own constraints, most probably
2538 the reload for this operand will be gone. */
2539 if (this_alternative_matches
>= 0
2540 && !curr_alt_win
[this_alternative_matches
]
2542 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2543 && (hard_regno
[nop
] >= 0
2544 ? in_hard_reg_set_p (this_alternative_set
,
2545 mode
, hard_regno
[nop
])
2546 : in_class_p (op
, this_alternative
, NULL
)))
2548 if (lra_dump_file
!= NULL
)
2551 " %d Dying matched operand reload: reject++\n",
2557 /* Strict_low_part requires to reload the register
2558 not the sub-register. In this case we should
2559 check that a final reload hard reg can hold the
2561 if (curr_static_id
->operand
[nop
].strict_low
2563 && hard_regno
[nop
] < 0
2564 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2565 && ira_class_hard_regs_num
[this_alternative
] > 0
2566 && (!targetm
.hard_regno_mode_ok
2567 (ira_class_hard_regs
[this_alternative
][0],
2568 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2570 if (lra_dump_file
!= NULL
)
2573 " alt=%d: Strict low subreg reload -- refuse\n",
2579 if (operand_reg
[nop
] != NULL_RTX
2580 /* Output operands and matched input operands are
2581 not inherited. The following conditions do not
2582 exactly describe the previous statement but they
2583 are pretty close. */
2584 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2585 && (this_alternative_matches
< 0
2586 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2588 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2592 /* The value of reload_sum has sense only if we
2593 process insns in their order. It happens only on
2594 the first constraints sub-pass when we do most of
2596 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2597 reload_sum
+= last_reload
- bb_reload_num
;
2599 /* If this is a constant that is reloaded into the
2600 desired class by copying it to memory first, count
2601 that as another reload. This is consistent with
2602 other code and is required to avoid choosing another
2603 alternative when the constant is moved into memory.
2604 Note that the test here is precisely the same as in
2605 the code below that calls force_const_mem. */
2606 if (CONST_POOL_OK_P (mode
, op
)
2607 && ((targetm
.preferred_reload_class
2608 (op
, this_alternative
) == NO_REGS
)
2609 || no_input_reloads_p
))
2616 /* Alternative loses if it requires a type of reload not
2617 permitted for this insn. We can always reload
2618 objects with a REG_UNUSED note. */
2619 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2620 && no_output_reloads_p
2621 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2622 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2623 && no_input_reloads_p
&& ! const_to_mem
)
2624 || (this_alternative_matches
>= 0
2625 && (no_input_reloads_p
2626 || (no_output_reloads_p
2627 && (curr_static_id
->operand
2628 [this_alternative_matches
].type
!= OP_IN
)
2629 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2630 no_subreg_reg_operand
2631 [this_alternative_matches
])))))
2633 if (lra_dump_file
!= NULL
)
2636 " alt=%d: No input/otput reload -- refuse\n",
2641 /* Alternative loses if it required class pseudo can not
2642 hold value of required mode. Such insns can be
2643 described by insn definitions with mode iterators. */
2644 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2645 && ! hard_reg_set_empty_p (this_alternative_set
)
2646 /* It is common practice for constraints to use a
2647 class which does not have actually enough regs to
2648 hold the value (e.g. x86 AREG for mode requiring
2649 more one general reg). Therefore we have 2
2650 conditions to check that the reload pseudo can
2651 not hold the mode value. */
2652 && (!targetm
.hard_regno_mode_ok
2653 (ira_class_hard_regs
[this_alternative
][0],
2654 GET_MODE (*curr_id
->operand_loc
[nop
])))
2655 /* The above condition is not enough as the first
2656 reg in ira_class_hard_regs can be not aligned for
2657 multi-words mode values. */
2658 && (prohibited_class_reg_set_mode_p
2659 (this_alternative
, this_alternative_set
,
2660 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2662 if (lra_dump_file
!= NULL
)
2663 fprintf (lra_dump_file
,
2664 " alt=%d: reload pseudo for op %d "
2665 " can not hold the mode value -- refuse\n",
2670 /* Check strong discouragement of reload of non-constant
2671 into class THIS_ALTERNATIVE. */
2672 if (! CONSTANT_P (op
) && ! no_regs_p
2673 && (targetm
.preferred_reload_class
2674 (op
, this_alternative
) == NO_REGS
2675 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2676 && (targetm
.preferred_output_reload_class
2677 (op
, this_alternative
) == NO_REGS
))))
2679 if (lra_dump_file
!= NULL
)
2680 fprintf (lra_dump_file
,
2681 " %d Non-prefered reload: reject+=%d\n",
2682 nop
, LRA_MAX_REJECT
);
2683 reject
+= LRA_MAX_REJECT
;
2686 if (! (MEM_P (op
) && offmemok
)
2687 && ! (const_to_mem
&& constmemok
))
2689 /* We prefer to reload pseudos over reloading other
2690 things, since such reloads may be able to be
2691 eliminated later. So bump REJECT in other cases.
2692 Don't do this in the case where we are forcing a
2693 constant into memory and it will then win since
2694 we don't want to have a different alternative
2696 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2698 if (lra_dump_file
!= NULL
)
2701 " %d Non-pseudo reload: reject+=2\n",
2708 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2710 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2712 if (lra_dump_file
!= NULL
)
2715 " %d Small class reload: reject+=%d\n",
2716 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2717 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2721 /* We are trying to spill pseudo into memory. It is
2722 usually more costly than moving to a hard register
2723 although it might takes the same number of
2726 Non-pseudo spill may happen also. Suppose a target allows both
2727 register and memory in the operand constraint alternatives,
2728 then it's typical that an eliminable register has a substition
2729 of "base + offset" which can either be reloaded by a simple
2730 "new_reg <= base + offset" which will match the register
2731 constraint, or a similar reg addition followed by further spill
2732 to and reload from memory which will match the memory
2733 constraint, but this memory spill will be much more costly
2736 Code below increases the reject for both pseudo and non-pseudo
2739 && !(MEM_P (op
) && offmemok
)
2740 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2742 if (lra_dump_file
!= NULL
)
2745 " %d Spill %spseudo into memory: reject+=3\n",
2746 nop
, REG_P (op
) ? "" : "Non-");
2748 if (VECTOR_MODE_P (mode
))
2750 /* Spilling vectors into memory is usually more
2751 costly as they contain big values. */
2752 if (lra_dump_file
!= NULL
)
2755 " %d Spill vector pseudo: reject+=2\n",
2761 /* When we use an operand requiring memory in given
2762 alternative, the insn should write *and* read the
2763 value to/from memory it is costly in comparison with
2764 an insn alternative which does not use memory
2765 (e.g. register or immediate operand). We exclude
2766 memory operand for such case as we can satisfy the
2767 memory constraints by reloading address. */
2768 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2770 if (lra_dump_file
!= NULL
)
2773 " Using memory insn operand %d: reject+=3\n",
2778 /* If reload requires moving value through secondary
2779 memory, it will need one more insn at least. */
2780 if (this_alternative
!= NO_REGS
2781 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2782 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2783 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
2785 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2786 && (targetm
.secondary_memory_needed
2787 (GET_MODE (op
), this_alternative
, cl
)))))
2790 /* Input reloads can be inherited more often than output
2791 reloads can be removed, so penalize output
2793 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2795 if (lra_dump_file
!= NULL
)
2798 " %d Non input pseudo reload: reject++\n",
2803 if (MEM_P (op
) && offmemok
)
2805 else if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2807 if (lra_dump_file
!= NULL
)
2810 " %d Input/Output reload: reject+=%d\n",
2811 nop
, LRA_LOSER_COST_FACTOR
);
2812 reject
+= LRA_LOSER_COST_FACTOR
;
2816 if (early_clobber_p
&& ! scratch_p
)
2818 if (lra_dump_file
!= NULL
)
2819 fprintf (lra_dump_file
,
2820 " %d Early clobber: reject++\n", nop
);
2823 /* ??? We check early clobbers after processing all operands
2824 (see loop below) and there we update the costs more.
2825 Should we update the cost (may be approximately) here
2826 because of early clobber register reloads or it is a rare
2827 or non-important thing to be worth to do it. */
2828 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2829 - (addr_losers
== losers
? static_reject
: 0));
2830 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2832 if (lra_dump_file
!= NULL
)
2833 fprintf (lra_dump_file
,
2834 " alt=%d,overall=%d,losers=%d -- refuse\n",
2835 nalt
, overall
, losers
);
2839 if (update_and_check_small_class_inputs (nop
, this_alternative
))
2841 if (lra_dump_file
!= NULL
)
2842 fprintf (lra_dump_file
,
2843 " alt=%d, not enough small class regs -- refuse\n",
2847 curr_alt
[nop
] = this_alternative
;
2848 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2849 curr_alt_win
[nop
] = this_alternative_win
;
2850 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2851 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2852 curr_alt_matches
[nop
] = this_alternative_matches
;
2854 if (this_alternative_matches
>= 0
2855 && !did_match
&& !this_alternative_win
)
2856 curr_alt_win
[this_alternative_matches
] = false;
2858 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2859 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2862 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2863 /* Prevent processing non-move insns. */
2864 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2865 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2866 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2867 && REG_P (no_subreg_reg_operand
[0])
2868 && REG_P (no_subreg_reg_operand
[1])
2869 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2870 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2871 || (! curr_alt_win
[0] && curr_alt_win
[1]
2872 && REG_P (no_subreg_reg_operand
[1])
2873 /* Check that we reload memory not the memory
2875 && ! (curr_alt_offmemok
[0]
2876 && MEM_P (no_subreg_reg_operand
[0]))
2877 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2878 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2879 && REG_P (no_subreg_reg_operand
[0])
2880 /* Check that we reload memory not the memory
2882 && ! (curr_alt_offmemok
[1]
2883 && MEM_P (no_subreg_reg_operand
[1]))
2884 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2885 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2886 no_subreg_reg_operand
[1])
2887 || (targetm
.preferred_reload_class
2888 (no_subreg_reg_operand
[1],
2889 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2890 /* If it is a result of recent elimination in move
2891 insn we can transform it into an add still by
2892 using this alternative. */
2893 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
2894 /* Likewise if the source has been replaced with an
2895 equivalent value. This only happens once -- the reload
2896 will use the equivalent value instead of the register it
2897 replaces -- so there should be no danger of cycling. */
2898 && !equiv_substition_p
[1])))
2900 /* We have a move insn and a new reload insn will be similar
2901 to the current insn. We should avoid such situation as
2902 it results in LRA cycling. */
2903 if (lra_dump_file
!= NULL
)
2904 fprintf (lra_dump_file
,
2905 " Cycle danger: overall += LRA_MAX_REJECT\n");
2906 overall
+= LRA_MAX_REJECT
;
2909 curr_alt_dont_inherit_ops_num
= 0;
2910 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2912 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2913 HARD_REG_SET temp_set
;
2915 i
= early_clobbered_nops
[nop
];
2916 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2917 || hard_regno
[i
] < 0)
2919 lra_assert (operand_reg
[i
] != NULL_RTX
);
2920 clobbered_hard_regno
= hard_regno
[i
];
2921 CLEAR_HARD_REG_SET (temp_set
);
2922 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2923 first_conflict_j
= last_conflict_j
= -1;
2924 for (j
= 0; j
< n_operands
; j
++)
2926 /* We don't want process insides of match_operator and
2927 match_parallel because otherwise we would process
2928 their operands once again generating a wrong
2930 || curr_static_id
->operand
[j
].is_operator
)
2932 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2933 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2935 /* If we don't reload j-th operand, check conflicts. */
2936 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2937 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2939 if (first_conflict_j
< 0)
2940 first_conflict_j
= j
;
2941 last_conflict_j
= j
;
2942 /* Both the earlyclobber operand and conflicting operand
2943 cannot both be user defined hard registers. */
2944 if (HARD_REGISTER_P (operand_reg
[i
])
2945 && REG_USERVAR_P (operand_reg
[i
])
2946 && operand_reg
[j
] != NULL_RTX
2947 && HARD_REGISTER_P (operand_reg
[j
])
2948 && REG_USERVAR_P (operand_reg
[j
]))
2949 fatal_insn ("unable to generate reloads for "
2950 "impossible constraints:", curr_insn
);
2952 if (last_conflict_j
< 0)
2955 /* If an earlyclobber operand conflicts with another non-matching
2956 operand (ie, they have been assigned the same hard register),
2957 then it is better to reload the other operand, as there may
2958 exist yet another operand with a matching constraint associated
2959 with the earlyclobber operand. However, if one of the operands
2960 is an explicit use of a hard register, then we must reload the
2961 other non-hard register operand. */
2962 if (HARD_REGISTER_P (operand_reg
[i
])
2963 || (first_conflict_j
== last_conflict_j
2964 && operand_reg
[last_conflict_j
] != NULL_RTX
2965 && !curr_alt_match_win
[last_conflict_j
]
2966 && !HARD_REGISTER_P (operand_reg
[last_conflict_j
])))
2968 curr_alt_win
[last_conflict_j
] = false;
2969 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2972 if (lra_dump_file
!= NULL
)
2975 " %d Conflict early clobber reload: reject--\n",
2980 /* We need to reload early clobbered register and the
2981 matched registers. */
2982 for (j
= 0; j
< n_operands
; j
++)
2983 if (curr_alt_matches
[j
] == i
)
2985 curr_alt_match_win
[j
] = false;
2987 overall
+= LRA_LOSER_COST_FACTOR
;
2989 if (! curr_alt_match_win
[i
])
2990 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2993 /* Remember pseudos used for match reloads are never
2995 lra_assert (curr_alt_matches
[i
] >= 0);
2996 curr_alt_win
[curr_alt_matches
[i
]] = false;
2998 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
3000 if (lra_dump_file
!= NULL
)
3003 " %d Matched conflict early clobber reloads: "
3007 /* Early clobber was already reflected in REJECT. */
3008 if (!matching_early_clobber
[i
])
3010 lra_assert (reject
> 0);
3012 matching_early_clobber
[i
] = 1;
3014 overall
+= LRA_LOSER_COST_FACTOR
- 1;
3016 if (lra_dump_file
!= NULL
)
3017 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
3018 nalt
, overall
, losers
, reload_nregs
);
3020 /* If this alternative can be made to work by reloading, and it
3021 needs less reloading than the others checked so far, record
3022 it as the chosen goal for reloading. */
3023 if ((best_losers
!= 0 && losers
== 0)
3024 || (((best_losers
== 0 && losers
== 0)
3025 || (best_losers
!= 0 && losers
!= 0))
3026 && (best_overall
> overall
3027 || (best_overall
== overall
3028 /* If the cost of the reloads is the same,
3029 prefer alternative which requires minimal
3030 number of reload regs. */
3031 && (reload_nregs
< best_reload_nregs
3032 || (reload_nregs
== best_reload_nregs
3033 && (best_reload_sum
< reload_sum
3034 || (best_reload_sum
== reload_sum
3035 && nalt
< goal_alt_number
))))))))
3037 for (nop
= 0; nop
< n_operands
; nop
++)
3039 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3040 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3041 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3042 goal_alt
[nop
] = curr_alt
[nop
];
3043 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3045 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3046 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3047 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3048 goal_alt_swapped
= curr_swapped
;
3049 best_overall
= overall
;
3050 best_losers
= losers
;
3051 best_reload_nregs
= reload_nregs
;
3052 best_reload_sum
= reload_sum
;
3053 goal_alt_number
= nalt
;
3056 /* Everything is satisfied. Do not process alternatives
3065 /* Make reload base reg from address AD. */
3067 base_to_reg (struct address_info
*ad
)
3071 rtx new_inner
= NULL_RTX
;
3072 rtx new_reg
= NULL_RTX
;
3074 rtx_insn
*last_insn
= get_last_insn();
3076 lra_assert (ad
->disp
== ad
->disp_term
);
3077 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3078 get_index_code (ad
));
3079 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
3081 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3082 ad
->disp_term
== NULL
3085 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3087 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3088 code
= recog_memoized (insn
);
3091 delete_insns_since (last_insn
);
3098 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3100 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3105 lra_assert (ad
->base
== ad
->base_term
);
3106 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3107 get_index_code (ad
));
3108 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
3110 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3114 /* Make reload of index part of address AD. Return the new
3117 index_part_to_reg (struct address_info
*ad
)
3121 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3122 INDEX_REG_CLASS
, "index term");
3123 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3124 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3128 /* Return true if we can add a displacement to address AD, even if that
3129 makes the address invalid. The fix-up code requires any new address
3130 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3132 can_add_disp_p (struct address_info
*ad
)
3134 return (!ad
->autoinc_p
3135 && ad
->segment
== NULL
3136 && ad
->base
== ad
->base_term
3137 && ad
->disp
== ad
->disp_term
);
3140 /* Make equiv substitution in address AD. Return true if a substitution
3143 equiv_address_substitution (struct address_info
*ad
)
3145 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3147 HOST_WIDE_INT scale
;
3150 base_term
= strip_subreg (ad
->base_term
);
3151 if (base_term
== NULL
)
3152 base_reg
= new_base_reg
= NULL_RTX
;
3155 base_reg
= *base_term
;
3156 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3158 index_term
= strip_subreg (ad
->index_term
);
3159 if (index_term
== NULL
)
3160 index_reg
= new_index_reg
= NULL_RTX
;
3163 index_reg
= *index_term
;
3164 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3166 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3170 if (lra_dump_file
!= NULL
)
3172 fprintf (lra_dump_file
, "Changing address in insn %d ",
3173 INSN_UID (curr_insn
));
3174 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3176 if (base_reg
!= new_base_reg
)
3179 if (REG_P (new_base_reg
))
3181 *base_term
= new_base_reg
;
3184 else if (GET_CODE (new_base_reg
) == PLUS
3185 && REG_P (XEXP (new_base_reg
, 0))
3186 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3187 && can_add_disp_p (ad
))
3190 *base_term
= XEXP (new_base_reg
, 0);
3193 if (ad
->base_term2
!= NULL
)
3194 *ad
->base_term2
= *ad
->base_term
;
3196 if (index_reg
!= new_index_reg
)
3199 if (REG_P (new_index_reg
))
3201 *index_term
= new_index_reg
;
3204 else if (GET_CODE (new_index_reg
) == PLUS
3205 && REG_P (XEXP (new_index_reg
, 0))
3206 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3207 && can_add_disp_p (ad
)
3208 && (scale
= get_index_scale (ad
)))
3210 disp
+= offset
* scale
;
3211 *index_term
= XEXP (new_index_reg
, 0);
3215 if (maybe_ne (disp
, 0))
3217 if (ad
->disp
!= NULL
)
3218 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3221 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3222 update_address (ad
);
3226 if (lra_dump_file
!= NULL
)
3229 fprintf (lra_dump_file
, " -- no change\n");
3232 fprintf (lra_dump_file
, " on equiv ");
3233 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3234 fprintf (lra_dump_file
, "\n");
3240 /* Major function to make reloads for an address in operand NOP or
3241 check its correctness (If CHECK_ONLY_P is true). The supported
3244 1) an address that existed before LRA started, at which point it
3245 must have been valid. These addresses are subject to elimination
3246 and may have become invalid due to the elimination offset being out
3249 2) an address created by forcing a constant to memory
3250 (force_const_to_mem). The initial form of these addresses might
3251 not be valid, and it is this function's job to make them valid.
3253 3) a frame address formed from a register and a (possibly zero)
3254 constant offset. As above, these addresses might not be valid and
3255 this function must make them so.
3257 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3258 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3259 address. Return true for any RTL change.
3261 The function is a helper function which does not produce all
3262 transformations (when CHECK_ONLY_P is false) which can be
3263 necessary. It does just basic steps. To do all necessary
3264 transformations use function process_address. */
3266 process_address_1 (int nop
, bool check_only_p
,
3267 rtx_insn
**before
, rtx_insn
**after
)
3269 struct address_info ad
;
3271 HOST_WIDE_INT scale
;
3272 rtx op
= *curr_id
->operand_loc
[nop
];
3273 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3274 enum constraint_num cn
= lookup_constraint (constraint
);
3275 bool change_p
= false;
3278 && GET_MODE (op
) == BLKmode
3279 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3282 if (insn_extra_address_constraint (cn
)
3283 /* When we find an asm operand with an address constraint that
3284 doesn't satisfy address_operand to begin with, we clear
3285 is_address, so that we don't try to make a non-address fit.
3286 If the asm statement got this far, it's because other
3287 constraints are available, and we'll use them, disregarding
3288 the unsatisfiable address ones. */
3289 && curr_static_id
->operand
[nop
].is_address
)
3290 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3291 /* Do not attempt to decompose arbitrary addresses generated by combine
3292 for asm operands with loose constraints, e.g 'X'. */
3294 && !(INSN_CODE (curr_insn
) < 0
3295 && get_constraint_type (cn
) == CT_FIXED_FORM
3296 && constraint_satisfied_p (op
, cn
)))
3297 decompose_mem_address (&ad
, op
);
3298 else if (GET_CODE (op
) == SUBREG
3299 && MEM_P (SUBREG_REG (op
)))
3300 decompose_mem_address (&ad
, SUBREG_REG (op
));
3303 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3304 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3305 when INDEX_REG_CLASS is a single register class. */
3306 if (ad
.base_term
!= NULL
3307 && ad
.index_term
!= NULL
3308 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3309 && REG_P (*ad
.base_term
)
3310 && REG_P (*ad
.index_term
)
3311 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3312 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3314 std::swap (ad
.base
, ad
.index
);
3315 std::swap (ad
.base_term
, ad
.index_term
);
3318 change_p
= equiv_address_substitution (&ad
);
3319 if (ad
.base_term
!= NULL
3320 && (process_addr_reg
3321 (ad
.base_term
, check_only_p
, before
,
3323 && !(REG_P (*ad
.base_term
)
3324 && find_regno_note (curr_insn
, REG_DEAD
,
3325 REGNO (*ad
.base_term
)) != NULL_RTX
)
3327 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3328 get_index_code (&ad
)))))
3331 if (ad
.base_term2
!= NULL
)
3332 *ad
.base_term2
= *ad
.base_term
;
3334 if (ad
.index_term
!= NULL
3335 && process_addr_reg (ad
.index_term
, check_only_p
,
3336 before
, NULL
, INDEX_REG_CLASS
))
3339 /* Target hooks sometimes don't treat extra-constraint addresses as
3340 legitimate address_operands, so handle them specially. */
3341 if (insn_extra_address_constraint (cn
)
3342 && satisfies_address_constraint_p (&ad
, cn
))
3348 /* There are three cases where the shape of *AD.INNER may now be invalid:
3350 1) the original address was valid, but either elimination or
3351 equiv_address_substitution was applied and that made
3352 the address invalid.
3354 2) the address is an invalid symbolic address created by
3357 3) the address is a frame address with an invalid offset.
3359 4) the address is a frame address with an invalid base.
3361 All these cases involve a non-autoinc address, so there is no
3362 point revalidating other types. */
3363 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3366 /* Any index existed before LRA started, so we can assume that the
3367 presence and shape of the index is valid. */
3368 push_to_sequence (*before
);
3369 lra_assert (ad
.disp
== ad
.disp_term
);
3370 if (ad
.base
== NULL
)
3372 if (ad
.index
== NULL
)
3375 rtx_insn
*last
= get_last_insn ();
3377 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3379 rtx addr
= *ad
.inner
;
3381 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3384 /* addr => lo_sum (new_base, addr), case (2) above. */
3385 insn
= emit_insn (gen_rtx_SET
3387 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3388 code
= recog_memoized (insn
);
3391 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3392 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3394 /* Try to put lo_sum into register. */
3395 insn
= emit_insn (gen_rtx_SET
3397 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3398 code
= recog_memoized (insn
);
3401 *ad
.inner
= new_reg
;
3402 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3412 delete_insns_since (last
);
3417 /* addr => new_base, case (2) above. */
3418 lra_emit_move (new_reg
, addr
);
3420 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3422 insn
= NEXT_INSN (insn
))
3423 if (recog_memoized (insn
) < 0)
3425 if (insn
!= NULL_RTX
)
3427 /* Do nothing if we cannot generate right insns.
3428 This is analogous to reload pass behavior. */
3429 delete_insns_since (last
);
3433 *ad
.inner
= new_reg
;
3438 /* index * scale + disp => new base + index * scale,
3440 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3441 GET_CODE (*ad
.index
));
3443 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3444 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3445 lra_emit_move (new_reg
, *ad
.disp
);
3446 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3447 new_reg
, *ad
.index
);
3450 else if (ad
.index
== NULL
)
3455 rtx_insn
*insns
, *last_insn
;
3456 /* Try to reload base into register only if the base is invalid
3457 for the address but with valid offset, case (4) above. */
3459 new_reg
= base_to_reg (&ad
);
3461 /* base + disp => new base, cases (1) and (3) above. */
3462 /* Another option would be to reload the displacement into an
3463 index register. However, postreload has code to optimize
3464 address reloads that have the same base and different
3465 displacements, so reloading into an index register would
3466 not necessarily be a win. */
3467 if (new_reg
== NULL_RTX
)
3469 /* See if the target can split the displacement into a
3470 legitimate new displacement from a local anchor. */
3471 gcc_assert (ad
.disp
== ad
.disp_term
);
3472 poly_int64 orig_offset
;
3473 rtx offset1
, offset2
;
3474 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3475 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3479 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3480 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3483 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3485 insns
= get_insns ();
3486 last_insn
= get_last_insn ();
3487 /* If we generated at least two insns, try last insn source as
3488 an address. If we succeed, we generate one less insn. */
3490 && last_insn
!= insns
3491 && (set
= single_set (last_insn
)) != NULL_RTX
3492 && GET_CODE (SET_SRC (set
)) == PLUS
3493 && REG_P (XEXP (SET_SRC (set
), 0))
3494 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3496 *ad
.inner
= SET_SRC (set
);
3497 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3499 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3500 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3501 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3502 get_index_code (&ad
));
3503 regno
= REGNO (*ad
.base_term
);
3504 if (regno
>= FIRST_PSEUDO_REGISTER
3505 && cl
!= lra_get_allocno_class (regno
))
3506 lra_change_class (regno
, cl
, " Change to", true);
3507 new_reg
= SET_SRC (set
);
3508 delete_insns_since (PREV_INSN (last_insn
));
3513 *ad
.inner
= new_reg
;
3515 else if (ad
.disp_term
!= NULL
)
3517 /* base + scale * index + disp => new base + scale * index,
3519 gcc_assert (ad
.disp
== ad
.disp_term
);
3520 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3521 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3522 new_reg
, *ad
.index
);
3524 else if ((scale
= get_index_scale (&ad
)) == 1)
3526 /* The last transformation to one reg will be made in
3527 curr_insn_transform function. */
3531 else if (scale
!= 0)
3533 /* base + scale * index => base + new_reg,
3535 Index part of address may become invalid. For example, we
3536 changed pseudo on the equivalent memory and a subreg of the
3537 pseudo onto the memory of different mode for which the scale is
3539 new_reg
= index_part_to_reg (&ad
);
3540 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3541 *ad
.base_term
, new_reg
);
3545 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3547 rtx addr
= *ad
.inner
;
3549 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3550 /* addr => new_base. */
3551 lra_emit_move (new_reg
, addr
);
3552 *ad
.inner
= new_reg
;
3554 *before
= get_insns ();
3559 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3560 Use process_address_1 as a helper function. Return true for any
3563 If CHECK_ONLY_P is true, just check address correctness. Return
3564 false if the address correct. */
3566 process_address (int nop
, bool check_only_p
,
3567 rtx_insn
**before
, rtx_insn
**after
)
3571 while (process_address_1 (nop
, check_only_p
, before
, after
))
3580 /* Emit insns to reload VALUE into a new register. VALUE is an
3581 auto-increment or auto-decrement RTX whose operand is a register or
3582 memory location; so reloading involves incrementing that location.
3583 IN is either identical to VALUE, or some cheaper place to reload
3584 value being incremented/decremented from.
3586 INC_AMOUNT is the number to increment or decrement by (always
3587 positive and ignored for POST_MODIFY/PRE_MODIFY).
3589 Return pseudo containing the result. */
3591 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3593 /* REG or MEM to be copied and incremented. */
3594 rtx incloc
= XEXP (value
, 0);
3595 /* Nonzero if increment after copying. */
3596 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3597 || GET_CODE (value
) == POST_MODIFY
);
3602 rtx real_in
= in
== value
? incloc
: in
;
3606 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3608 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3609 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3610 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3611 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3612 inc
= XEXP (XEXP (value
, 1), 1);
3616 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3617 inc_amount
= -inc_amount
;
3619 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3622 if (! post
&& REG_P (incloc
))
3625 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3628 if (real_in
!= result
)
3630 /* First copy the location to the result register. */
3631 lra_assert (REG_P (result
));
3632 emit_insn (gen_move_insn (result
, real_in
));
3635 /* We suppose that there are insns to add/sub with the constant
3636 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3637 old reload worked with this assumption. If the assumption
3638 becomes wrong, we should use approach in function
3639 base_plus_disp_to_reg. */
3642 /* See if we can directly increment INCLOC. */
3643 last
= get_last_insn ();
3644 add_insn
= emit_insn (plus_p
3645 ? gen_add2_insn (incloc
, inc
)
3646 : gen_sub2_insn (incloc
, inc
));
3648 code
= recog_memoized (add_insn
);
3651 if (! post
&& result
!= incloc
)
3652 emit_insn (gen_move_insn (result
, incloc
));
3655 delete_insns_since (last
);
3658 /* If couldn't do the increment directly, must increment in RESULT.
3659 The way we do this depends on whether this is pre- or
3660 post-increment. For pre-increment, copy INCLOC to the reload
3661 register, increment it there, then save back. */
3664 if (real_in
!= result
)
3665 emit_insn (gen_move_insn (result
, real_in
));
3667 emit_insn (gen_add2_insn (result
, inc
));
3669 emit_insn (gen_sub2_insn (result
, inc
));
3670 if (result
!= incloc
)
3671 emit_insn (gen_move_insn (incloc
, result
));
3677 Because this might be a jump insn or a compare, and because
3678 RESULT may not be available after the insn in an input
3679 reload, we must do the incrementing before the insn being
3682 We have already copied IN to RESULT. Increment the copy in
3683 RESULT, save that back, then decrement RESULT so it has
3684 the original value. */
3686 emit_insn (gen_add2_insn (result
, inc
));
3688 emit_insn (gen_sub2_insn (result
, inc
));
3689 emit_insn (gen_move_insn (incloc
, result
));
3690 /* Restore non-modified value for the result. We prefer this
3691 way because it does not require an additional hard
3696 if (poly_int_rtx_p (inc
, &offset
))
3697 emit_insn (gen_add2_insn (result
,
3698 gen_int_mode (-offset
,
3699 GET_MODE (result
))));
3701 emit_insn (gen_sub2_insn (result
, inc
));
3704 emit_insn (gen_add2_insn (result
, inc
));
3709 /* Return true if the current move insn does not need processing as we
3710 already know that it satisfies its constraints. */
3712 simple_move_p (void)
3715 enum reg_class dclass
, sclass
;
3717 lra_assert (curr_insn_set
!= NULL_RTX
);
3718 dest
= SET_DEST (curr_insn_set
);
3719 src
= SET_SRC (curr_insn_set
);
3721 /* If the instruction has multiple sets we need to process it even if it
3722 is single_set. This can happen if one or more of the SETs are dead.
3724 if (multiple_sets (curr_insn
))
3727 return ((dclass
= get_op_class (dest
)) != NO_REGS
3728 && (sclass
= get_op_class (src
)) != NO_REGS
3729 /* The backend guarantees that register moves of cost 2
3730 never need reloads. */
3731 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3734 /* Swap operands NOP and NOP + 1. */
3736 swap_operands (int nop
)
3738 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3739 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3740 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3741 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3742 /* Swap the duplicates too. */
3743 lra_update_dup (curr_id
, nop
);
3744 lra_update_dup (curr_id
, nop
+ 1);
3747 /* Main entry point of the constraint code: search the body of the
3748 current insn to choose the best alternative. It is mimicking insn
3749 alternative cost calculation model of former reload pass. That is
3750 because machine descriptions were written to use this model. This
3751 model can be changed in future. Make commutative operand exchange
3754 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3755 constraints. Return true if any change happened during function
3758 If CHECK_ONLY_P is true then don't do any transformation. Just
3759 check that the insn satisfies all constraints. If the insn does
3760 not satisfy any constraint, return true. */
3762 curr_insn_transform (bool check_only_p
)
3769 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3770 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3771 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3772 rtx_insn
*before
, *after
;
3774 /* Flag that the insn has been changed through a transformation. */
3778 int max_regno_before
;
3779 int reused_alternative_num
;
3781 curr_insn_set
= single_set (curr_insn
);
3782 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3784 /* We assume that the corresponding insn alternative has no
3785 earlier clobbers. If it is not the case, don't define move
3786 cost equal to 2 for the corresponding register classes. */
3787 lra_set_used_insn_alternative (curr_insn
, LRA_NON_CLOBBERED_ALT
);
3791 no_input_reloads_p
= no_output_reloads_p
= false;
3792 goal_alt_number
= -1;
3793 change_p
= sec_mem_p
= false;
3794 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3795 reloads; neither are insns that SET cc0. Insns that use CC0 are
3796 not allowed to have any input reloads. */
3797 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3798 no_output_reloads_p
= true;
3800 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3801 no_input_reloads_p
= true;
3802 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3803 no_output_reloads_p
= true;
3805 n_operands
= curr_static_id
->n_operands
;
3806 n_alternatives
= curr_static_id
->n_alternatives
;
3808 /* Just return "no reloads" if insn has no operands with
3810 if (n_operands
== 0 || n_alternatives
== 0)
3813 max_regno_before
= max_reg_num ();
3815 for (i
= 0; i
< n_operands
; i
++)
3817 goal_alt_matched
[i
][0] = -1;
3818 goal_alt_matches
[i
] = -1;
3821 commutative
= curr_static_id
->commutative
;
3823 /* Now see what we need for pseudos that didn't get hard regs or got
3824 the wrong kind of hard reg. For this, we must consider all the
3825 operands together against the register constraints. */
3827 best_losers
= best_overall
= INT_MAX
;
3828 best_reload_sum
= 0;
3830 curr_swapped
= false;
3831 goal_alt_swapped
= false;
3834 /* Make equivalence substitution and memory subreg elimination
3835 before address processing because an address legitimacy can
3836 depend on memory mode. */
3837 for (i
= 0; i
< n_operands
; i
++)
3840 bool op_change_p
= false;
3842 if (curr_static_id
->operand
[i
].is_operator
)
3845 old
= op
= *curr_id
->operand_loc
[i
];
3846 if (GET_CODE (old
) == SUBREG
)
3847 old
= SUBREG_REG (old
);
3848 subst
= get_equiv_with_elimination (old
, curr_insn
);
3849 original_subreg_reg_mode
[i
] = VOIDmode
;
3850 equiv_substition_p
[i
] = false;
3853 equiv_substition_p
[i
] = true;
3854 subst
= copy_rtx (subst
);
3855 lra_assert (REG_P (old
));
3856 if (GET_CODE (op
) != SUBREG
)
3857 *curr_id
->operand_loc
[i
] = subst
;
3860 SUBREG_REG (op
) = subst
;
3861 if (GET_MODE (subst
) == VOIDmode
)
3862 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3864 if (lra_dump_file
!= NULL
)
3866 fprintf (lra_dump_file
,
3867 "Changing pseudo %d in operand %i of insn %u on equiv ",
3868 REGNO (old
), i
, INSN_UID (curr_insn
));
3869 dump_value_slim (lra_dump_file
, subst
, 1);
3870 fprintf (lra_dump_file
, "\n");
3872 op_change_p
= change_p
= true;
3874 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3877 lra_update_dup (curr_id
, i
);
3881 /* Reload address registers and displacements. We do it before
3882 finding an alternative because of memory constraints. */
3883 before
= after
= NULL
;
3884 for (i
= 0; i
< n_operands
; i
++)
3885 if (! curr_static_id
->operand
[i
].is_operator
3886 && process_address (i
, check_only_p
, &before
, &after
))
3891 lra_update_dup (curr_id
, i
);
3895 /* If we've changed the instruction then any alternative that
3896 we chose previously may no longer be valid. */
3897 lra_set_used_insn_alternative (curr_insn
, LRA_UNKNOWN_ALT
);
3899 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3900 && check_and_process_move (&change_p
, &sec_mem_p
))
3905 reused_alternative_num
= check_only_p
? LRA_UNKNOWN_ALT
: curr_id
->used_insn_alternative
;
3906 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3907 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3908 reused_alternative_num
, INSN_UID (curr_insn
));
3910 if (process_alt_operands (reused_alternative_num
))
3914 return ! alt_p
|| best_losers
!= 0;
3916 /* If insn is commutative (it's safe to exchange a certain pair of
3917 operands) then we need to try each alternative twice, the second
3918 time matching those two operands as if we had exchanged them. To
3919 do this, really exchange them in operands.
3921 If we have just tried the alternatives the second time, return
3922 operands to normal and drop through. */
3924 if (reused_alternative_num
< 0 && commutative
>= 0)
3926 curr_swapped
= !curr_swapped
;
3929 swap_operands (commutative
);
3933 swap_operands (commutative
);
3936 if (! alt_p
&& ! sec_mem_p
)
3938 /* No alternative works with reloads?? */
3939 if (INSN_CODE (curr_insn
) >= 0)
3940 fatal_insn ("unable to generate reloads for:", curr_insn
);
3941 error_for_asm (curr_insn
,
3942 "inconsistent operand constraints in an %<asm%>");
3943 lra_asm_error_p
= true;
3944 /* Avoid further trouble with this insn. Don't generate use
3945 pattern here as we could use the insn SP offset. */
3946 lra_set_insn_deleted (curr_insn
);
3950 /* If the best alternative is with operands 1 and 2 swapped, swap
3951 them. Update the operand numbers of any reloads already
3954 if (goal_alt_swapped
)
3956 if (lra_dump_file
!= NULL
)
3957 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3958 INSN_UID (curr_insn
));
3960 /* Swap the duplicates too. */
3961 swap_operands (commutative
);
3965 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3966 too conservatively. So we use the secondary memory only if there
3967 is no any alternative without reloads. */
3968 use_sec_mem_p
= false;
3970 use_sec_mem_p
= true;
3973 for (i
= 0; i
< n_operands
; i
++)
3974 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3976 use_sec_mem_p
= i
< n_operands
;
3981 int in
= -1, out
= -1;
3982 rtx new_reg
, src
, dest
, rld
;
3983 machine_mode sec_mode
, rld_mode
;
3985 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3986 dest
= SET_DEST (curr_insn_set
);
3987 src
= SET_SRC (curr_insn_set
);
3988 for (i
= 0; i
< n_operands
; i
++)
3989 if (*curr_id
->operand_loc
[i
] == dest
)
3991 else if (*curr_id
->operand_loc
[i
] == src
)
3993 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3994 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3995 out
= curr_static_id
->dup_num
[i
];
3996 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3997 in
= curr_static_id
->dup_num
[i
];
3998 lra_assert (out
>= 0 && in
>= 0
3999 && curr_static_id
->operand
[out
].type
== OP_OUT
4000 && curr_static_id
->operand
[in
].type
== OP_IN
);
4001 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
4002 rld_mode
= GET_MODE (rld
);
4003 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
4004 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
4005 NO_REGS
, "secondary");
4006 /* If the mode is changed, it should be wider. */
4007 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
4008 if (sec_mode
!= rld_mode
)
4010 /* If the target says specifically to use another mode for
4011 secondary memory moves we can not reuse the original
4013 after
= emit_spill_move (false, new_reg
, dest
);
4014 lra_process_new_insns (curr_insn
, NULL
, after
,
4015 "Inserting the sec. move");
4016 /* We may have non null BEFORE here (e.g. after address
4018 push_to_sequence (before
);
4019 before
= emit_spill_move (true, new_reg
, src
);
4021 before
= get_insns ();
4023 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
4024 lra_set_insn_deleted (curr_insn
);
4026 else if (dest
== rld
)
4028 *curr_id
->operand_loc
[out
] = new_reg
;
4029 lra_update_dup (curr_id
, out
);
4030 after
= emit_spill_move (false, new_reg
, dest
);
4031 lra_process_new_insns (curr_insn
, NULL
, after
,
4032 "Inserting the sec. move");
4036 *curr_id
->operand_loc
[in
] = new_reg
;
4037 lra_update_dup (curr_id
, in
);
4038 /* See comments above. */
4039 push_to_sequence (before
);
4040 before
= emit_spill_move (true, new_reg
, src
);
4042 before
= get_insns ();
4044 lra_process_new_insns (curr_insn
, before
, NULL
,
4045 "Inserting the sec. move");
4047 lra_update_insn_regno_info (curr_insn
);
4051 lra_assert (goal_alt_number
>= 0);
4052 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
4054 if (lra_dump_file
!= NULL
)
4058 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4059 goal_alt_number
, INSN_UID (curr_insn
));
4060 for (i
= 0; i
< n_operands
; i
++)
4062 p
= (curr_static_id
->operand_alternative
4063 [goal_alt_number
* n_operands
+ i
].constraint
);
4066 fprintf (lra_dump_file
, " (%d) ", i
);
4067 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4068 fputc (*p
, lra_dump_file
);
4070 if (INSN_CODE (curr_insn
) >= 0
4071 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4072 fprintf (lra_dump_file
, " {%s}", p
);
4073 if (maybe_ne (curr_id
->sp_offset
, 0))
4075 fprintf (lra_dump_file
, " (sp_off=");
4076 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4077 fprintf (lra_dump_file
, ")");
4079 fprintf (lra_dump_file
, "\n");
4082 /* Right now, for any pair of operands I and J that are required to
4083 match, with J < I, goal_alt_matches[I] is J. Add I to
4084 goal_alt_matched[J]. */
4086 for (i
= 0; i
< n_operands
; i
++)
4087 if ((j
= goal_alt_matches
[i
]) >= 0)
4089 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4091 /* We allow matching one output operand and several input
4094 || (curr_static_id
->operand
[j
].type
== OP_OUT
4095 && curr_static_id
->operand
[i
].type
== OP_IN
4096 && (curr_static_id
->operand
4097 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4098 goal_alt_matched
[j
][k
] = i
;
4099 goal_alt_matched
[j
][k
+ 1] = -1;
4102 for (i
= 0; i
< n_operands
; i
++)
4103 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4105 /* Any constants that aren't allowed and can't be reloaded into
4106 registers are here changed into memory references. */
4107 for (i
= 0; i
< n_operands
; i
++)
4108 if (goal_alt_win
[i
])
4111 enum reg_class new_class
;
4112 rtx reg
= *curr_id
->operand_loc
[i
];
4114 if (GET_CODE (reg
) == SUBREG
)
4115 reg
= SUBREG_REG (reg
);
4117 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4119 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4121 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4124 lra_change_class (regno
, new_class
, " Change to", true);
4130 const char *constraint
;
4132 rtx op
= *curr_id
->operand_loc
[i
];
4133 rtx subreg
= NULL_RTX
;
4134 machine_mode mode
= curr_operand_mode
[i
];
4136 if (GET_CODE (op
) == SUBREG
)
4139 op
= SUBREG_REG (op
);
4140 mode
= GET_MODE (op
);
4143 if (CONST_POOL_OK_P (mode
, op
)
4144 && ((targetm
.preferred_reload_class
4145 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4146 || no_input_reloads_p
))
4148 rtx tem
= force_const_mem (mode
, op
);
4151 if (subreg
!= NULL_RTX
)
4152 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4154 *curr_id
->operand_loc
[i
] = tem
;
4155 lra_update_dup (curr_id
, i
);
4156 process_address (i
, false, &before
, &after
);
4158 /* If the alternative accepts constant pool refs directly
4159 there will be no reload needed at all. */
4160 if (subreg
!= NULL_RTX
)
4162 /* Skip alternatives before the one requested. */
4163 constraint
= (curr_static_id
->operand_alternative
4164 [goal_alt_number
* n_operands
+ i
].constraint
);
4166 (c
= *constraint
) && c
!= ',' && c
!= '#';
4167 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4169 enum constraint_num cn
= lookup_constraint (constraint
);
4170 if ((insn_extra_memory_constraint (cn
)
4171 || insn_extra_special_memory_constraint (cn
))
4172 && satisfies_memory_constraint_p (tem
, cn
))
4175 if (c
== '\0' || c
== ',' || c
== '#')
4178 goal_alt_win
[i
] = true;
4184 for (i
= 0; i
< n_operands
; i
++)
4187 bool optional_p
= false;
4189 rtx op
= *curr_id
->operand_loc
[i
];
4191 if (goal_alt_win
[i
])
4193 if (goal_alt
[i
] == NO_REGS
4195 /* When we assign NO_REGS it means that we will not
4196 assign a hard register to the scratch pseudo by
4197 assigment pass and the scratch pseudo will be
4198 spilled. Spilled scratch pseudos are transformed
4199 back to scratches at the LRA end. */
4200 && lra_former_scratch_operand_p (curr_insn
, i
)
4201 && lra_former_scratch_p (REGNO (op
)))
4203 int regno
= REGNO (op
);
4204 lra_change_class (regno
, NO_REGS
, " Change to", true);
4205 if (lra_get_regno_hard_regno (regno
) >= 0)
4206 /* We don't have to mark all insn affected by the
4207 spilled pseudo as there is only one such insn, the
4209 reg_renumber
[regno
] = -1;
4210 lra_assert (bitmap_single_bit_set_p
4211 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4213 /* We can do an optional reload. If the pseudo got a hard
4214 reg, we might improve the code through inheritance. If
4215 it does not get a hard register we coalesce memory/memory
4216 moves later. Ignore move insns to avoid cycling. */
4218 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4219 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4220 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4221 && regno
< new_regno_start
4222 && ! lra_former_scratch_p (regno
)
4223 && reg_renumber
[regno
] < 0
4224 /* Check that the optional reload pseudo will be able to
4225 hold given mode value. */
4226 && ! (prohibited_class_reg_set_mode_p
4227 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4228 PSEUDO_REGNO_MODE (regno
)))
4229 && (curr_insn_set
== NULL_RTX
4230 || !((REG_P (SET_SRC (curr_insn_set
))
4231 || MEM_P (SET_SRC (curr_insn_set
))
4232 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4233 && (REG_P (SET_DEST (curr_insn_set
))
4234 || MEM_P (SET_DEST (curr_insn_set
))
4235 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4241 /* Operands that match previous ones have already been handled. */
4242 if (goal_alt_matches
[i
] >= 0)
4245 /* We should not have an operand with a non-offsettable address
4246 appearing where an offsettable address will do. It also may
4247 be a case when the address should be special in other words
4248 not a general one (e.g. it needs no index reg). */
4249 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4251 enum reg_class rclass
;
4252 rtx
*loc
= &XEXP (op
, 0);
4253 enum rtx_code code
= GET_CODE (*loc
);
4255 push_to_sequence (before
);
4256 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4258 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4259 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4260 /* This value does not matter for MODIFY. */
4261 GET_MODE_SIZE (GET_MODE (op
)));
4262 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4263 "offsetable address", &new_reg
))
4266 enum rtx_code code
= GET_CODE (addr
);
4268 if (code
== AND
&& CONST_INT_P (XEXP (addr
, 1)))
4269 /* (and ... (const_int -X)) is used to align to X bytes. */
4270 addr
= XEXP (*loc
, 0);
4271 lra_emit_move (new_reg
, addr
);
4273 emit_move_insn (new_reg
, gen_rtx_AND (GET_MODE (new_reg
), new_reg
, XEXP (*loc
, 1)));
4275 before
= get_insns ();
4278 lra_update_dup (curr_id
, i
);
4280 else if (goal_alt_matched
[i
][0] == -1)
4285 enum op_type type
= curr_static_id
->operand
[i
].type
;
4287 loc
= curr_id
->operand_loc
[i
];
4288 mode
= curr_operand_mode
[i
];
4289 if (GET_CODE (*loc
) == SUBREG
)
4291 reg
= SUBREG_REG (*loc
);
4292 poly_int64 byte
= SUBREG_BYTE (*loc
);
4294 /* Strict_low_part requires reloading the register and not
4295 just the subreg. Likewise for a strict subreg no wider
4296 than a word for WORD_REGISTER_OPERATIONS targets. */
4297 && (curr_static_id
->operand
[i
].strict_low
4298 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4300 = get_try_hard_regno (REGNO (reg
))) >= 0
4301 && (simplify_subreg_regno
4303 GET_MODE (reg
), byte
, mode
) < 0)
4304 && (goal_alt
[i
] == NO_REGS
4305 || (simplify_subreg_regno
4306 (ira_class_hard_regs
[goal_alt
[i
]][0],
4307 GET_MODE (reg
), byte
, mode
) >= 0)))
4308 || (partial_subreg_p (mode
, GET_MODE (reg
))
4309 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4311 && WORD_REGISTER_OPERATIONS
)))
4313 /* An OP_INOUT is required when reloading a subreg of a
4314 mode wider than a word to ensure that data beyond the
4315 word being reloaded is preserved. Also automatically
4316 ensure that strict_low_part reloads are made into
4317 OP_INOUT which should already be true from the backend
4320 && (curr_static_id
->operand
[i
].strict_low
4321 || read_modify_subreg_p (*loc
)))
4323 loc
= &SUBREG_REG (*loc
);
4324 mode
= GET_MODE (*loc
);
4328 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4329 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4332 push_to_sequence (before
);
4333 lra_emit_move (new_reg
, old
);
4334 before
= get_insns ();
4339 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4342 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4344 after
= get_insns ();
4348 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4349 if (goal_alt_dont_inherit_ops
[j
] == i
)
4351 lra_set_regno_unique_value (REGNO (new_reg
));
4354 lra_update_dup (curr_id
, i
);
4356 else if (curr_static_id
->operand
[i
].type
== OP_IN
4357 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4359 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4361 && (operands_match_p
4362 (*curr_id
->operand_loc
[i
],
4363 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4366 /* generate reloads for input and matched outputs. */
4367 match_inputs
[0] = i
;
4368 match_inputs
[1] = -1;
4369 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4370 goal_alt
[i
], &before
, &after
,
4371 curr_static_id
->operand_alternative
4372 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4375 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4376 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4377 && (operands_match_p
4378 (*curr_id
->operand_loc
[i
],
4379 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4381 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4383 /* Generate reloads for output and matched inputs. */
4384 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4385 &after
, curr_static_id
->operand_alternative
4386 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4387 else if (curr_static_id
->operand
[i
].type
== OP_IN
4388 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4391 /* Generate reloads for matched inputs. */
4392 match_inputs
[0] = i
;
4393 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4394 match_inputs
[j
+ 1] = k
;
4395 match_inputs
[j
+ 1] = -1;
4396 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4400 /* We must generate code in any case when function
4401 process_alt_operands decides that it is possible. */
4404 /* Memorise processed outputs so that output remaining to be processed
4405 can avoid using the same register value (see match_reload). */
4406 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4408 outputs
[n_outputs
++] = i
;
4409 outputs
[n_outputs
] = -1;
4416 lra_assert (REG_P (reg
));
4417 regno
= REGNO (reg
);
4418 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4419 if (GET_CODE (op
) == SUBREG
)
4420 op
= SUBREG_REG (op
);
4421 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4422 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4423 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4424 if (lra_dump_file
!= NULL
)
4425 fprintf (lra_dump_file
,
4426 " Making reload reg %d for reg %d optional\n",
4430 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4431 || max_regno_before
!= max_reg_num ())
4435 lra_update_operator_dups (curr_id
);
4436 /* Something changes -- process the insn. */
4437 lra_update_insn_regno_info (curr_insn
);
4439 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4443 /* Return true if INSN satisfies all constraints. In other words, no
4444 reload insns are needed. */
4446 lra_constrain_insn (rtx_insn
*insn
)
4448 int saved_new_regno_start
= new_regno_start
;
4449 int saved_new_insn_uid_start
= new_insn_uid_start
;
4453 curr_id
= lra_get_insn_recog_data (curr_insn
);
4454 curr_static_id
= curr_id
->insn_static_data
;
4455 new_insn_uid_start
= get_max_uid ();
4456 new_regno_start
= max_reg_num ();
4457 change_p
= curr_insn_transform (true);
4458 new_regno_start
= saved_new_regno_start
;
4459 new_insn_uid_start
= saved_new_insn_uid_start
;
4463 /* Return true if X is in LIST. */
4465 in_list_p (rtx x
, rtx list
)
4467 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4468 if (XEXP (list
, 0) == x
)
4473 /* Return true if X contains an allocatable hard register (if
4474 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4476 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4482 code
= GET_CODE (x
);
4485 int regno
= REGNO (x
);
4486 HARD_REG_SET alloc_regs
;
4490 if (regno
>= FIRST_PSEUDO_REGISTER
)
4491 regno
= lra_get_regno_hard_regno (regno
);
4494 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4495 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4499 if (regno
< FIRST_PSEUDO_REGISTER
)
4503 return lra_get_regno_hard_regno (regno
) < 0;
4506 fmt
= GET_RTX_FORMAT (code
);
4507 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4511 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4514 else if (fmt
[i
] == 'E')
4516 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4517 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4524 /* Process all regs in location *LOC and change them on equivalent
4525 substitution. Return true if any change was done. */
4527 loc_equivalence_change_p (rtx
*loc
)
4529 rtx subst
, reg
, x
= *loc
;
4530 bool result
= false;
4531 enum rtx_code code
= GET_CODE (x
);
4537 reg
= SUBREG_REG (x
);
4538 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4539 && GET_MODE (subst
) == VOIDmode
)
4541 /* We cannot reload debug location. Simplify subreg here
4542 while we know the inner mode. */
4543 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4544 GET_MODE (reg
), SUBREG_BYTE (x
));
4548 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4554 /* Scan all the operand sub-expressions. */
4555 fmt
= GET_RTX_FORMAT (code
);
4556 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4559 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4560 else if (fmt
[i
] == 'E')
4561 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4563 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4568 /* Similar to loc_equivalence_change_p, but for use as
4569 simplify_replace_fn_rtx callback. DATA is insn for which the
4570 elimination is done. If it null we don't do the elimination. */
4572 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4577 rtx subst
= (data
== NULL
4578 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4585 /* Maximum number of generated reload insns per an insn. It is for
4586 preventing this pass cycling in a bug case. */
4587 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4589 /* The current iteration number of this LRA pass. */
4590 int lra_constraint_iter
;
4592 /* True if we substituted equiv which needs checking register
4593 allocation correctness because the equivalent value contains
4594 allocatable hard registers or when we restore multi-register
4596 bool lra_risky_transformations_p
;
4598 /* Return true if REGNO is referenced in more than one block. */
4600 multi_block_pseudo_p (int regno
)
4602 basic_block bb
= NULL
;
4606 if (regno
< FIRST_PSEUDO_REGISTER
)
4609 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4611 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4612 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4617 /* Return true if LIST contains a deleted insn. */
4619 contains_deleted_insn_p (rtx_insn_list
*list
)
4621 for (; list
!= NULL_RTX
; list
= list
->next ())
4622 if (NOTE_P (list
->insn ())
4623 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4628 /* Return true if X contains a pseudo dying in INSN. */
4630 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4637 return (insn
!= NULL_RTX
4638 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4639 code
= GET_CODE (x
);
4640 fmt
= GET_RTX_FORMAT (code
);
4641 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4645 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4648 else if (fmt
[i
] == 'E')
4650 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4651 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4658 /* Return true if INSN contains a dying pseudo in INSN right hand
4661 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4663 rtx set
= single_set (insn
);
4665 gcc_assert (set
!= NULL
);
4666 return dead_pseudo_p (SET_SRC (set
), insn
);
4669 /* Return true if any init insn of REGNO contains a dying pseudo in
4670 insn right hand side. */
4672 init_insn_rhs_dead_pseudo_p (int regno
)
4674 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4678 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4679 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4684 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4685 reverse only if we have one init insn with given REGNO as a
4688 reverse_equiv_p (int regno
)
4690 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4695 if (! INSN_P (insns
->insn ())
4696 || insns
->next () != NULL
)
4698 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4700 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4703 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4704 call this function only for non-reverse equivalence. */
4706 contains_reloaded_insn_p (int regno
)
4709 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4711 for (; list
!= NULL
; list
= list
->next ())
4712 if ((set
= single_set (list
->insn ())) == NULL_RTX
4713 || ! REG_P (SET_DEST (set
))
4714 || (int) REGNO (SET_DEST (set
)) != regno
)
4719 /* Entry function of LRA constraint pass. Return true if the
4720 constraint pass did change the code. */
4722 lra_constraints (bool first_p
)
4725 int i
, hard_regno
, new_insns_num
;
4726 unsigned int min_len
, new_min_len
, uid
;
4727 rtx set
, x
, reg
, dest_reg
;
4728 basic_block last_bb
;
4731 lra_constraint_iter
++;
4732 if (lra_dump_file
!= NULL
)
4733 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4734 lra_constraint_iter
);
4736 if (pic_offset_table_rtx
4737 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4738 lra_risky_transformations_p
= true;
4740 /* On the first iteration we should check IRA assignment
4741 correctness. In rare cases, the assignments can be wrong as
4742 early clobbers operands are ignored in IRA. */
4743 lra_risky_transformations_p
= first_p
;
4744 new_insn_uid_start
= get_max_uid ();
4745 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4746 /* Mark used hard regs for target stack size calulations. */
4747 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4748 if (lra_reg_info
[i
].nrefs
!= 0
4749 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4753 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
4754 for (j
= 0; j
< nregs
; j
++)
4755 df_set_regs_ever_live (hard_regno
+ j
, true);
4757 /* Do elimination before the equivalence processing as we can spill
4758 some pseudos during elimination. */
4759 lra_eliminate (false, first_p
);
4760 auto_bitmap
equiv_insn_bitmap (®_obstack
);
4761 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4762 if (lra_reg_info
[i
].nrefs
!= 0)
4764 ira_reg_equiv
[i
].profitable_p
= true;
4765 reg
= regno_reg_rtx
[i
];
4766 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4768 bool pseudo_p
= contains_reg_p (x
, false, false);
4770 /* After RTL transformation, we can not guarantee that
4771 pseudo in the substitution was not reloaded which might
4772 make equivalence invalid. For example, in reverse
4779 the memory address register was reloaded before the 2nd
4781 if ((! first_p
&& pseudo_p
)
4782 /* We don't use DF for compilation speed sake. So it
4783 is problematic to update live info when we use an
4784 equivalence containing pseudos in more than one
4786 || (pseudo_p
&& multi_block_pseudo_p (i
))
4787 /* If an init insn was deleted for some reason, cancel
4788 the equiv. We could update the equiv insns after
4789 transformations including an equiv insn deletion
4790 but it is not worthy as such cases are extremely
4792 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4793 /* If it is not a reverse equivalence, we check that a
4794 pseudo in rhs of the init insn is not dying in the
4795 insn. Otherwise, the live info at the beginning of
4796 the corresponding BB might be wrong after we
4797 removed the insn. When the equiv can be a
4798 constant, the right hand side of the init insn can
4800 || (! reverse_equiv_p (i
)
4801 && (init_insn_rhs_dead_pseudo_p (i
)
4802 /* If we reloaded the pseudo in an equivalence
4803 init insn, we can not remove the equiv init
4804 insns and the init insns might write into
4805 const memory in this case. */
4806 || contains_reloaded_insn_p (i
)))
4807 /* Prevent access beyond equivalent memory for
4808 paradoxical subregs. */
4810 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
4811 GET_MODE_SIZE (GET_MODE (x
))))
4812 || (pic_offset_table_rtx
4813 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4814 && (targetm
.preferred_reload_class
4815 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4816 || contains_symbol_ref_p (x
))))
4817 ira_reg_equiv
[i
].defined_p
= false;
4818 if (contains_reg_p (x
, false, true))
4819 ira_reg_equiv
[i
].profitable_p
= false;
4820 if (get_equiv (reg
) != reg
)
4821 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4824 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4826 /* We should add all insns containing pseudos which should be
4827 substituted by their equivalences. */
4828 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
4829 lra_push_insn_by_uid (uid
);
4830 min_len
= lra_insn_stack_length ();
4834 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4836 curr_insn
= lra_pop_insn ();
4838 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4839 if (curr_bb
!= last_bb
)
4842 bb_reload_num
= lra_curr_reload_num
;
4844 if (min_len
> new_min_len
)
4846 min_len
= new_min_len
;
4849 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4851 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4852 MAX_RELOAD_INSNS_NUMBER
);
4854 if (DEBUG_INSN_P (curr_insn
))
4856 /* We need to check equivalence in debug insn and change
4857 pseudo to the equivalent value if necessary. */
4858 curr_id
= lra_get_insn_recog_data (curr_insn
);
4859 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4861 rtx old
= *curr_id
->operand_loc
[0];
4862 *curr_id
->operand_loc
[0]
4863 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4864 loc_equivalence_callback
, curr_insn
);
4865 if (old
!= *curr_id
->operand_loc
[0])
4867 lra_update_insn_regno_info (curr_insn
);
4872 else if (INSN_P (curr_insn
))
4874 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4876 dest_reg
= SET_DEST (set
);
4877 /* The equivalence pseudo could be set up as SUBREG in a
4878 case when it is a call restore insn in a mode
4879 different from the pseudo mode. */
4880 if (GET_CODE (dest_reg
) == SUBREG
)
4881 dest_reg
= SUBREG_REG (dest_reg
);
4882 if ((REG_P (dest_reg
)
4883 && (x
= get_equiv (dest_reg
)) != dest_reg
4884 /* Remove insns which set up a pseudo whose value
4885 can not be changed. Such insns might be not in
4886 init_insns because we don't update equiv data
4887 during insn transformations.
4889 As an example, let suppose that a pseudo got
4890 hard register and on the 1st pass was not
4891 changed to equivalent constant. We generate an
4892 additional insn setting up the pseudo because of
4893 secondary memory movement. Then the pseudo is
4894 spilled and we use the equiv constant. In this
4895 case we should remove the additional insn and
4896 this insn is not init_insns list. */
4897 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4898 /* Check that this is actually an insn setting
4899 up the equivalence. */
4900 || in_list_p (curr_insn
,
4902 [REGNO (dest_reg
)].init_insns
)))
4903 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4904 && in_list_p (curr_insn
,
4906 [REGNO (SET_SRC (set
))].init_insns
)))
4908 /* This is equiv init insn of pseudo which did not get a
4909 hard register -- remove the insn. */
4910 if (lra_dump_file
!= NULL
)
4912 fprintf (lra_dump_file
,
4913 " Removing equiv init insn %i (freq=%d)\n",
4914 INSN_UID (curr_insn
),
4915 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4916 dump_insn_slim (lra_dump_file
, curr_insn
);
4918 if (contains_reg_p (x
, true, false))
4919 lra_risky_transformations_p
= true;
4920 lra_set_insn_deleted (curr_insn
);
4924 curr_id
= lra_get_insn_recog_data (curr_insn
);
4925 curr_static_id
= curr_id
->insn_static_data
;
4926 init_curr_insn_input_reloads ();
4927 init_curr_operand_mode ();
4928 if (curr_insn_transform (false))
4930 /* Check non-transformed insns too for equiv change as USE
4931 or CLOBBER don't need reloads but can contain pseudos
4932 being changed on their equivalences. */
4933 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
4934 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4936 lra_update_insn_regno_info (curr_insn
);
4942 /* If we used a new hard regno, changed_p should be true because the
4943 hard reg is assigned to a new pseudo. */
4944 if (flag_checking
&& !changed_p
)
4946 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4947 if (lra_reg_info
[i
].nrefs
!= 0
4948 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4950 int j
, nregs
= hard_regno_nregs (hard_regno
,
4951 PSEUDO_REGNO_MODE (i
));
4953 for (j
= 0; j
< nregs
; j
++)
4954 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4960 static void initiate_invariants (void);
4961 static void finish_invariants (void);
4963 /* Initiate the LRA constraint pass. It is done once per
4966 lra_constraints_init (void)
4968 initiate_invariants ();
4971 /* Finalize the LRA constraint pass. It is done once per
4974 lra_constraints_finish (void)
4976 finish_invariants ();
4981 /* Structure describes invariants for ineheritance. */
4982 struct lra_invariant
4984 /* The order number of the invariant. */
4986 /* The invariant RTX. */
4988 /* The origin insn of the invariant. */
4992 typedef lra_invariant invariant_t
;
4993 typedef invariant_t
*invariant_ptr_t
;
4994 typedef const invariant_t
*const_invariant_ptr_t
;
4996 /* Pointer to the inheritance invariants. */
4997 static vec
<invariant_ptr_t
> invariants
;
4999 /* Allocation pool for the invariants. */
5000 static object_allocator
<lra_invariant
> *invariants_pool
;
5002 /* Hash table for the invariants. */
5003 static htab_t invariant_table
;
5005 /* Hash function for INVARIANT. */
5007 invariant_hash (const void *invariant
)
5009 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
5010 return lra_rtx_hash (inv
);
5013 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
5015 invariant_eq_p (const void *invariant1
, const void *invariant2
)
5017 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
5018 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
5020 return rtx_equal_p (inv1
, inv2
);
5023 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5024 invariant which is in the table. */
5025 static invariant_ptr_t
5026 insert_invariant (rtx invariant_rtx
)
5029 invariant_t invariant
;
5030 invariant_ptr_t invariant_ptr
;
5032 invariant
.invariant_rtx
= invariant_rtx
;
5033 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
5034 if (*entry_ptr
== NULL
)
5036 invariant_ptr
= invariants_pool
->allocate ();
5037 invariant_ptr
->invariant_rtx
= invariant_rtx
;
5038 invariant_ptr
->insn
= NULL
;
5039 invariants
.safe_push (invariant_ptr
);
5040 *entry_ptr
= (void *) invariant_ptr
;
5042 return (invariant_ptr_t
) *entry_ptr
;
5045 /* Initiate the invariant table. */
5047 initiate_invariants (void)
5049 invariants
.create (100);
5051 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
5052 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
5055 /* Finish the invariant table. */
5057 finish_invariants (void)
5059 htab_delete (invariant_table
);
5060 delete invariants_pool
;
5061 invariants
.release ();
5064 /* Make the invariant table empty. */
5066 clear_invariants (void)
5068 htab_empty (invariant_table
);
5069 invariants_pool
->release ();
5070 invariants
.truncate (0);
5075 /* This page contains code to do inheritance/split
5078 /* Number of reloads passed so far in current EBB. */
5079 static int reloads_num
;
5081 /* Number of calls passed so far in current EBB. */
5082 static int calls_num
;
5084 /* Current reload pseudo check for validity of elements in
5086 static int curr_usage_insns_check
;
5088 /* Info about last usage of registers in EBB to do inheritance/split
5089 transformation. Inheritance transformation is done from a spilled
5090 pseudo and split transformations from a hard register or a pseudo
5091 assigned to a hard register. */
5094 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5095 value INSNS is valid. The insns is chain of optional debug insns
5096 and a finishing non-debug insn using the corresponding reg. The
5097 value is also used to mark the registers which are set up in the
5098 current insn. The negated insn uid is used for this. */
5100 /* Value of global reloads_num at the last insn in INSNS. */
5102 /* Value of global reloads_nums at the last insn in INSNS. */
5104 /* It can be true only for splitting. And it means that the restore
5105 insn should be put after insn given by the following member. */
5107 /* Next insns in the current EBB which use the original reg and the
5108 original reg value is not changed between the current insn and
5109 the next insns. In order words, e.g. for inheritance, if we need
5110 to use the original reg value again in the next insns we can try
5111 to use the value in a hard register from a reload insn of the
5116 /* Map: regno -> corresponding pseudo usage insns. */
5117 static struct usage_insns
*usage_insns
;
5120 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5122 usage_insns
[regno
].check
= curr_usage_insns_check
;
5123 usage_insns
[regno
].insns
= insn
;
5124 usage_insns
[regno
].reloads_num
= reloads_num
;
5125 usage_insns
[regno
].calls_num
= calls_num
;
5126 usage_insns
[regno
].after_p
= after_p
;
5129 /* The function is used to form list REGNO usages which consists of
5130 optional debug insns finished by a non-debug insn using REGNO.
5131 RELOADS_NUM is current number of reload insns processed so far. */
5133 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5135 rtx next_usage_insns
;
5137 if (usage_insns
[regno
].check
== curr_usage_insns_check
5138 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5139 && DEBUG_INSN_P (insn
))
5141 /* Check that we did not add the debug insn yet. */
5142 if (next_usage_insns
!= insn
5143 && (GET_CODE (next_usage_insns
) != INSN_LIST
5144 || XEXP (next_usage_insns
, 0) != insn
))
5145 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5148 else if (NONDEBUG_INSN_P (insn
))
5149 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5151 usage_insns
[regno
].check
= 0;
5154 /* Return first non-debug insn in list USAGE_INSNS. */
5156 skip_usage_debug_insns (rtx usage_insns
)
5160 /* Skip debug insns. */
5161 for (insn
= usage_insns
;
5162 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5163 insn
= XEXP (insn
, 1))
5165 return safe_as_a
<rtx_insn
*> (insn
);
5168 /* Return true if we need secondary memory moves for insn in
5169 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5172 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5173 rtx usage_insns ATTRIBUTE_UNUSED
)
5179 if (inher_cl
== ALL_REGS
5180 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5182 lra_assert (INSN_P (insn
));
5183 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5185 dest
= SET_DEST (set
);
5188 lra_assert (inher_cl
!= NO_REGS
);
5189 cl
= get_reg_class (REGNO (dest
));
5190 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5191 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5194 /* Registers involved in inheritance/split in the current EBB
5195 (inheritance/split pseudos and original registers). */
5196 static bitmap_head check_only_regs
;
5198 /* Reload pseudos can not be involded in invariant inheritance in the
5200 static bitmap_head invalid_invariant_regs
;
5202 /* Do inheritance transformations for insn INSN, which defines (if
5203 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5204 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5205 form as the "insns" field of usage_insns. Return true if we
5206 succeed in such transformation.
5208 The transformations look like:
5211 ... p <- i (new insn)
5213 <- ... p ... <- ... i ...
5215 ... i <- p (new insn)
5216 <- ... p ... <- ... i ...
5218 <- ... p ... <- ... i ...
5219 where p is a spilled original pseudo and i is a new inheritance pseudo.
5222 The inheritance pseudo has the smallest class of two classes CL and
5223 class of ORIGINAL REGNO. */
5225 inherit_reload_reg (bool def_p
, int original_regno
,
5226 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5228 if (optimize_function_for_size_p (cfun
))
5231 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5232 rtx original_reg
= regno_reg_rtx
[original_regno
];
5233 rtx new_reg
, usage_insn
;
5234 rtx_insn
*new_insns
;
5236 lra_assert (! usage_insns
[original_regno
].after_p
);
5237 if (lra_dump_file
!= NULL
)
5238 fprintf (lra_dump_file
,
5239 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5240 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5242 if (lra_dump_file
!= NULL
)
5244 fprintf (lra_dump_file
,
5245 " Rejecting inheritance for %d "
5246 "because of disjoint classes %s and %s\n",
5247 original_regno
, reg_class_names
[cl
],
5248 reg_class_names
[rclass
]);
5249 fprintf (lra_dump_file
,
5250 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5254 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5255 /* We don't use a subset of two classes because it can be
5256 NO_REGS. This transformation is still profitable in most
5257 cases even if the classes are not intersected as register
5258 move is probably cheaper than a memory load. */
5259 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5261 if (lra_dump_file
!= NULL
)
5262 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5263 reg_class_names
[cl
], reg_class_names
[rclass
]);
5267 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5269 /* Reject inheritance resulting in secondary memory moves.
5270 Otherwise, there is a danger in LRA cycling. Also such
5271 transformation will be unprofitable. */
5272 if (lra_dump_file
!= NULL
)
5274 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5275 rtx set
= single_set (insn
);
5277 lra_assert (set
!= NULL_RTX
);
5279 rtx dest
= SET_DEST (set
);
5281 lra_assert (REG_P (dest
));
5282 fprintf (lra_dump_file
,
5283 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5284 "as secondary mem is needed\n",
5285 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5286 original_regno
, reg_class_names
[rclass
]);
5287 fprintf (lra_dump_file
,
5288 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5292 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5293 rclass
, "inheritance");
5296 lra_emit_move (original_reg
, new_reg
);
5298 lra_emit_move (new_reg
, original_reg
);
5299 new_insns
= get_insns ();
5301 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5303 if (lra_dump_file
!= NULL
)
5305 fprintf (lra_dump_file
,
5306 " Rejecting inheritance %d->%d "
5307 "as it results in 2 or more insns:\n",
5308 original_regno
, REGNO (new_reg
));
5309 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5310 fprintf (lra_dump_file
,
5311 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5315 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5316 lra_update_insn_regno_info (insn
);
5318 /* We now have a new usage insn for original regno. */
5319 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5320 if (lra_dump_file
!= NULL
)
5321 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5322 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5323 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5324 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5325 bitmap_set_bit (&check_only_regs
, original_regno
);
5326 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5328 lra_process_new_insns (insn
, NULL
, new_insns
,
5329 "Add original<-inheritance");
5331 lra_process_new_insns (insn
, new_insns
, NULL
,
5332 "Add inheritance<-original");
5333 while (next_usage_insns
!= NULL_RTX
)
5335 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5337 usage_insn
= next_usage_insns
;
5338 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5339 next_usage_insns
= NULL
;
5343 usage_insn
= XEXP (next_usage_insns
, 0);
5344 lra_assert (DEBUG_INSN_P (usage_insn
));
5345 next_usage_insns
= XEXP (next_usage_insns
, 1);
5347 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5348 DEBUG_INSN_P (usage_insn
));
5349 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5350 if (lra_dump_file
!= NULL
)
5352 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5353 fprintf (lra_dump_file
,
5354 " Inheritance reuse change %d->%d (bb%d):\n",
5355 original_regno
, REGNO (new_reg
),
5356 bb
? bb
->index
: -1);
5357 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5360 if (lra_dump_file
!= NULL
)
5361 fprintf (lra_dump_file
,
5362 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5366 /* Return true if we need a caller save/restore for pseudo REGNO which
5367 was assigned to a hard register. */
5369 need_for_call_save_p (int regno
)
5371 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5372 return (usage_insns
[regno
].calls_num
< calls_num
5373 && (overlaps_hard_reg_set_p
5375 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5376 ? lra_reg_info
[regno
].actual_call_used_reg_set
5377 : call_used_reg_set
,
5378 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5379 || (targetm
.hard_regno_call_part_clobbered
5380 (reg_renumber
[regno
], PSEUDO_REGNO_MODE (regno
)))));
5383 /* Global registers occurring in the current EBB. */
5384 static bitmap_head ebb_global_regs
;
5386 /* Return true if we need a split for hard register REGNO or pseudo
5387 REGNO which was assigned to a hard register.
5388 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5389 used for reloads since the EBB end. It is an approximation of the
5390 used hard registers in the split range. The exact value would
5391 require expensive calculations. If we were aggressive with
5392 splitting because of the approximation, the split pseudo will save
5393 the same hard register assignment and will be removed in the undo
5394 pass. We still need the approximation because too aggressive
5395 splitting would result in too inaccurate cost calculation in the
5396 assignment pass because of too many generated moves which will be
5397 probably removed in the undo pass. */
5399 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5401 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5403 lra_assert (hard_regno
>= 0);
5404 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5405 /* Don't split eliminable hard registers, otherwise we can
5406 split hard registers like hard frame pointer, which
5407 lives on BB start/end according to DF-infrastructure,
5408 when there is a pseudo assigned to the register and
5409 living in the same BB. */
5410 && (regno
>= FIRST_PSEUDO_REGISTER
5411 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5412 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5413 /* Don't split call clobbered hard regs living through
5414 calls, otherwise we might have a check problem in the
5415 assign sub-pass as in the most cases (exception is a
5416 situation when lra_risky_transformations_p value is
5417 true) the assign pass assumes that all pseudos living
5418 through calls are assigned to call saved hard regs. */
5419 && (regno
>= FIRST_PSEUDO_REGISTER
5420 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5421 || usage_insns
[regno
].calls_num
== calls_num
)
5422 /* We need at least 2 reloads to make pseudo splitting
5423 profitable. We should provide hard regno splitting in
5424 any case to solve 1st insn scheduling problem when
5425 moving hard register definition up might result in
5426 impossibility to find hard register for reload pseudo of
5427 small register class. */
5428 && (usage_insns
[regno
].reloads_num
5429 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5430 && (regno
< FIRST_PSEUDO_REGISTER
5431 /* For short living pseudos, spilling + inheritance can
5432 be considered a substitution for splitting.
5433 Therefore we do not splitting for local pseudos. It
5434 decreases also aggressiveness of splitting. The
5435 minimal number of references is chosen taking into
5436 account that for 2 references splitting has no sense
5437 as we can just spill the pseudo. */
5438 || (regno
>= FIRST_PSEUDO_REGISTER
5439 && lra_reg_info
[regno
].nrefs
> 3
5440 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5441 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5444 /* Return class for the split pseudo created from original pseudo with
5445 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5446 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5447 results in no secondary memory movements. */
5448 static enum reg_class
5449 choose_split_class (enum reg_class allocno_class
,
5450 int hard_regno ATTRIBUTE_UNUSED
,
5451 machine_mode mode ATTRIBUTE_UNUSED
)
5454 enum reg_class cl
, best_cl
= NO_REGS
;
5455 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5456 = REGNO_REG_CLASS (hard_regno
);
5458 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
5459 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5460 return allocno_class
;
5462 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5464 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
5465 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
5466 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5467 && (best_cl
== NO_REGS
5468 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5473 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5474 It only makes sense to call this function if NEW_REGNO is always
5475 equal to ORIGINAL_REGNO. */
5478 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5480 if (!ira_reg_equiv
[original_regno
].defined_p
)
5483 ira_expand_reg_equiv ();
5484 ira_reg_equiv
[new_regno
].defined_p
= true;
5485 if (ira_reg_equiv
[original_regno
].memory
)
5486 ira_reg_equiv
[new_regno
].memory
5487 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5488 if (ira_reg_equiv
[original_regno
].constant
)
5489 ira_reg_equiv
[new_regno
].constant
5490 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5491 if (ira_reg_equiv
[original_regno
].invariant
)
5492 ira_reg_equiv
[new_regno
].invariant
5493 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5496 /* Do split transformations for insn INSN, which defines or uses
5497 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5498 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5499 "insns" field of usage_insns. If TO is not NULL, we don't use
5500 usage_insns, we put restore insns after TO insn. It is a case when
5501 we call it from lra_split_hard_reg_for, outside the inheritance
5504 The transformations look like:
5507 ... s <- p (new insn -- save)
5509 ... p <- s (new insn -- restore)
5510 <- ... p ... <- ... p ...
5512 <- ... p ... <- ... p ...
5513 ... s <- p (new insn -- save)
5515 ... p <- s (new insn -- restore)
5516 <- ... p ... <- ... p ...
5518 where p is an original pseudo got a hard register or a hard
5519 register and s is a new split pseudo. The save is put before INSN
5520 if BEFORE_P is true. Return true if we succeed in such
5523 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5524 rtx next_usage_insns
, rtx_insn
*to
)
5526 enum reg_class rclass
;
5528 int hard_regno
, nregs
;
5529 rtx new_reg
, usage_insn
;
5530 rtx_insn
*restore
, *save
;
5535 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5537 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5538 hard_regno
= original_regno
;
5539 call_save_p
= false;
5541 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5542 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5543 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5544 as part of a multi-word register. In that case, or if the biggest
5545 mode was larger than a register, just use the reg_rtx. Otherwise,
5546 limit the size to that of the biggest access in the function. */
5547 if (mode
== VOIDmode
5548 || paradoxical_subreg_p (mode
, reg_rtx_mode
))
5550 original_reg
= regno_reg_rtx
[hard_regno
];
5551 mode
= reg_rtx_mode
;
5554 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5558 mode
= PSEUDO_REGNO_MODE (original_regno
);
5559 hard_regno
= reg_renumber
[original_regno
];
5560 nregs
= hard_regno_nregs (hard_regno
, mode
);
5561 rclass
= lra_get_allocno_class (original_regno
);
5562 original_reg
= regno_reg_rtx
[original_regno
];
5563 call_save_p
= need_for_call_save_p (original_regno
);
5565 lra_assert (hard_regno
>= 0);
5566 if (lra_dump_file
!= NULL
)
5567 fprintf (lra_dump_file
,
5568 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5572 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5573 hard_regno_nregs (hard_regno
, mode
),
5575 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5579 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5580 if (rclass
== NO_REGS
)
5582 if (lra_dump_file
!= NULL
)
5584 fprintf (lra_dump_file
,
5585 " Rejecting split of %d(%s): "
5586 "no good reg class for %d(%s)\n",
5588 reg_class_names
[lra_get_allocno_class (original_regno
)],
5590 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5593 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5597 /* Split_if_necessary can split hard registers used as part of a
5598 multi-register mode but splits each register individually. The
5599 mode used for each independent register may not be supported
5600 so reject the split. Splitting the wider mode should theoretically
5601 be possible but is not implemented. */
5602 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5604 if (lra_dump_file
!= NULL
)
5606 fprintf (lra_dump_file
,
5607 " Rejecting split of %d(%s): unsuitable mode %s\n",
5609 reg_class_names
[lra_get_allocno_class (original_regno
)],
5610 GET_MODE_NAME (mode
));
5613 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5617 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5618 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5620 int new_regno
= REGNO (new_reg
);
5621 save
= emit_spill_move (true, new_reg
, original_reg
);
5622 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5624 if (lra_dump_file
!= NULL
)
5628 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5629 original_regno
, new_regno
);
5630 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5631 fprintf (lra_dump_file
,
5632 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5636 restore
= emit_spill_move (false, new_reg
, original_reg
);
5637 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5639 if (lra_dump_file
!= NULL
)
5641 fprintf (lra_dump_file
,
5642 " Rejecting split %d->%d "
5643 "resulting in > 2 restore insns:\n",
5644 original_regno
, new_regno
);
5645 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5646 fprintf (lra_dump_file
,
5647 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5651 /* Transfer equivalence information to the spill register, so that
5652 if we fail to allocate the spill register, we have the option of
5653 rematerializing the original value instead of spilling to the stack. */
5654 if (!HARD_REGISTER_NUM_P (original_regno
)
5655 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5656 lra_copy_reg_equiv (new_regno
, original_regno
);
5657 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5658 bitmap_set_bit (&lra_split_regs
, new_regno
);
5661 lra_assert (next_usage_insns
== NULL
);
5667 /* We need check_only_regs only inside the inheritance pass. */
5668 bitmap_set_bit (&check_only_regs
, new_regno
);
5669 bitmap_set_bit (&check_only_regs
, original_regno
);
5670 after_p
= usage_insns
[original_regno
].after_p
;
5673 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5675 usage_insn
= next_usage_insns
;
5678 usage_insn
= XEXP (next_usage_insns
, 0);
5679 lra_assert (DEBUG_INSN_P (usage_insn
));
5680 next_usage_insns
= XEXP (next_usage_insns
, 1);
5681 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5683 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5684 if (lra_dump_file
!= NULL
)
5686 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5687 original_regno
, new_regno
);
5688 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5692 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5693 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5694 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5695 after_p
? NULL
: restore
,
5696 after_p
? restore
: NULL
,
5698 ? "Add reg<-save" : "Add reg<-split");
5699 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5700 before_p
? NULL
: save
,
5702 ? "Add save<-reg" : "Add split<-reg");
5704 /* If we are trying to split multi-register. We should check
5705 conflicts on the next assignment sub-pass. IRA can allocate on
5706 sub-register levels, LRA do this on pseudos level right now and
5707 this discrepancy may create allocation conflicts after
5709 lra_risky_transformations_p
= true;
5710 if (lra_dump_file
!= NULL
)
5711 fprintf (lra_dump_file
,
5712 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5716 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
5717 in the range [FROM, TO]. Return true if did a split. Otherwise,
5720 spill_hard_reg_in_range (int regno
, enum reg_class rclass
, rtx_insn
*from
, rtx_insn
*to
)
5727 HARD_REG_SET ignore
;
5729 lra_assert (from
!= NULL
&& to
!= NULL
);
5730 CLEAR_HARD_REG_SET (ignore
);
5731 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
5733 lra_insn_recog_data_t id
= lra_insn_recog_data
[uid
];
5734 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
5735 struct lra_insn_reg
*reg
;
5737 for (reg
= id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5738 if (reg
->regno
< FIRST_PSEUDO_REGISTER
)
5739 SET_HARD_REG_BIT (ignore
, reg
->regno
);
5740 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5741 SET_HARD_REG_BIT (ignore
, reg
->regno
);
5743 rclass_size
= ira_class_hard_regs_num
[rclass
];
5744 for (i
= 0; i
< rclass_size
; i
++)
5746 hard_regno
= ira_class_hard_regs
[rclass
][i
];
5747 if (! TEST_HARD_REG_BIT (lra_reg_info
[regno
].conflict_hard_regs
, hard_regno
)
5748 || TEST_HARD_REG_BIT (ignore
, hard_regno
))
5750 for (insn
= from
; insn
!= NEXT_INSN (to
); insn
= NEXT_INSN (insn
))
5752 struct lra_static_insn_data
*static_id
;
5753 struct lra_insn_reg
*reg
;
5757 if (bitmap_bit_p (&lra_reg_info
[hard_regno
].insn_bitmap
,
5760 static_id
= lra_get_insn_recog_data (insn
)->insn_static_data
;
5761 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5762 if (reg
->regno
== hard_regno
)
5767 if (insn
!= NEXT_INSN (to
))
5769 if (split_reg (TRUE
, hard_regno
, from
, NULL
, to
))
5775 /* Recognize that we need a split transformation for insn INSN, which
5776 defines or uses REGNO in its insn biggest MODE (we use it only if
5777 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5778 hard registers which might be used for reloads since the EBB end.
5779 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5780 uid before starting INSN processing. Return true if we succeed in
5781 such transformation. */
5783 split_if_necessary (int regno
, machine_mode mode
,
5784 HARD_REG_SET potential_reload_hard_regs
,
5785 bool before_p
, rtx_insn
*insn
, int max_uid
)
5789 rtx next_usage_insns
;
5791 if (regno
< FIRST_PSEUDO_REGISTER
)
5792 nregs
= hard_regno_nregs (regno
, mode
);
5793 for (i
= 0; i
< nregs
; i
++)
5794 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5795 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5796 /* To avoid processing the register twice or more. */
5797 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5798 && INSN_UID (next_usage_insns
) < max_uid
)
5799 || (GET_CODE (next_usage_insns
) == INSN_LIST
5800 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5801 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5802 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
, NULL
))
5807 /* Return TRUE if rtx X is considered as an invariant for
5810 invariant_p (const_rtx x
)
5817 code
= GET_CODE (x
);
5818 mode
= GET_MODE (x
);
5822 code
= GET_CODE (x
);
5823 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
5831 int i
, nregs
, regno
= REGNO (x
);
5833 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5834 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5835 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5837 nregs
= hard_regno_nregs (regno
, mode
);
5838 for (i
= 0; i
< nregs
; i
++)
5839 if (! fixed_regs
[regno
+ i
]
5840 /* A hard register may be clobbered in the current insn
5841 but we can ignore this case because if the hard
5842 register is used it should be set somewhere after the
5844 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5847 fmt
= GET_RTX_FORMAT (code
);
5848 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5852 if (! invariant_p (XEXP (x
, i
)))
5855 else if (fmt
[i
] == 'E')
5857 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5858 if (! invariant_p (XVECEXP (x
, i
, j
)))
5865 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5866 inheritance transformation (using dest_reg instead invariant in a
5867 subsequent insn). */
5869 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5871 invariant_ptr_t invariant_ptr
;
5872 rtx_insn
*insn
, *new_insns
;
5873 rtx insn_set
, insn_reg
, new_reg
;
5875 bool succ_p
= false;
5876 int dst_regno
= REGNO (dst_reg
);
5877 machine_mode dst_mode
= GET_MODE (dst_reg
);
5878 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5880 invariant_ptr
= insert_invariant (invariant_rtx
);
5881 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5883 /* We have a subsequent insn using the invariant. */
5884 insn_set
= single_set (insn
);
5885 lra_assert (insn_set
!= NULL
);
5886 insn_reg
= SET_DEST (insn_set
);
5887 lra_assert (REG_P (insn_reg
));
5888 insn_regno
= REGNO (insn_reg
);
5889 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5891 if (dst_mode
== GET_MODE (insn_reg
)
5892 /* We should consider only result move reg insns which are
5894 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5895 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5897 if (lra_dump_file
!= NULL
)
5898 fprintf (lra_dump_file
,
5899 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5900 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5901 cl
, "invariant inheritance");
5902 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5903 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5904 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5906 lra_emit_move (new_reg
, dst_reg
);
5907 new_insns
= get_insns ();
5909 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5910 "Add invariant inheritance<-original");
5912 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5913 new_insns
= get_insns ();
5915 lra_process_new_insns (insn
, NULL
, new_insns
,
5916 "Changing reload<-inheritance");
5917 lra_set_insn_deleted (insn
);
5919 if (lra_dump_file
!= NULL
)
5921 fprintf (lra_dump_file
,
5922 " Invariant inheritance reuse change %d (bb%d):\n",
5923 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5924 dump_insn_slim (lra_dump_file
, insn
);
5925 fprintf (lra_dump_file
,
5926 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5930 invariant_ptr
->insn
= curr_insn
;
5934 /* Check only registers living at the current program point in the
5936 static bitmap_head live_regs
;
5938 /* Update live info in EBB given by its HEAD and TAIL insns after
5939 inheritance/split transformation. The function removes dead moves
5942 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5947 rtx_insn
*prev_insn
;
5950 basic_block last_bb
, prev_bb
, curr_bb
;
5952 struct lra_insn_reg
*reg
;
5956 last_bb
= BLOCK_FOR_INSN (tail
);
5958 for (curr_insn
= tail
;
5959 curr_insn
!= PREV_INSN (head
);
5960 curr_insn
= prev_insn
)
5962 prev_insn
= PREV_INSN (curr_insn
);
5963 /* We need to process empty blocks too. They contain
5964 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5965 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5967 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5968 if (curr_bb
!= prev_bb
)
5970 if (prev_bb
!= NULL
)
5972 /* Update df_get_live_in (prev_bb): */
5973 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5974 if (bitmap_bit_p (&live_regs
, j
))
5975 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5977 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5979 if (curr_bb
!= last_bb
)
5981 /* Update df_get_live_out (curr_bb): */
5982 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5984 live_p
= bitmap_bit_p (&live_regs
, j
);
5986 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5987 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5993 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5995 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5999 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
6001 if (! NONDEBUG_INSN_P (curr_insn
))
6003 curr_id
= lra_get_insn_recog_data (curr_insn
);
6004 curr_static_id
= curr_id
->insn_static_data
;
6006 if ((set
= single_set (curr_insn
)) != NULL_RTX
6007 && REG_P (SET_DEST (set
))
6008 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
6009 && SET_DEST (set
) != pic_offset_table_rtx
6010 && bitmap_bit_p (&check_only_regs
, regno
)
6011 && ! bitmap_bit_p (&live_regs
, regno
))
6013 /* See which defined values die here. */
6014 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6015 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6016 bitmap_clear_bit (&live_regs
, reg
->regno
);
6017 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6018 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6019 bitmap_clear_bit (&live_regs
, reg
->regno
);
6020 if (curr_id
->arg_hard_regs
!= NULL
)
6021 /* Make clobbered argument hard registers die. */
6022 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6023 if (regno
>= FIRST_PSEUDO_REGISTER
)
6024 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
6025 /* Mark each used value as live. */
6026 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6027 if (reg
->type
!= OP_OUT
6028 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6029 bitmap_set_bit (&live_regs
, reg
->regno
);
6030 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6031 if (reg
->type
!= OP_OUT
6032 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6033 bitmap_set_bit (&live_regs
, reg
->regno
);
6034 if (curr_id
->arg_hard_regs
!= NULL
)
6035 /* Make used argument hard registers live. */
6036 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6037 if (regno
< FIRST_PSEUDO_REGISTER
6038 && bitmap_bit_p (&check_only_regs
, regno
))
6039 bitmap_set_bit (&live_regs
, regno
);
6040 /* It is quite important to remove dead move insns because it
6041 means removing dead store. We don't need to process them for
6045 if (lra_dump_file
!= NULL
)
6047 fprintf (lra_dump_file
, " Removing dead insn:\n ");
6048 dump_insn_slim (lra_dump_file
, curr_insn
);
6050 lra_set_insn_deleted (curr_insn
);
6055 /* The structure describes info to do an inheritance for the current
6056 insn. We need to collect such info first before doing the
6057 transformations because the transformations change the insn
6058 internal representation. */
6061 /* Original regno. */
6063 /* Subsequent insns which can inherit original reg value. */
6067 /* Array containing all info for doing inheritance from the current
6069 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
6071 /* Number elements in the previous array. */
6072 static int to_inherit_num
;
6074 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6075 structure to_inherit. */
6077 add_to_inherit (int regno
, rtx insns
)
6081 for (i
= 0; i
< to_inherit_num
; i
++)
6082 if (to_inherit
[i
].regno
== regno
)
6084 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
6085 to_inherit
[to_inherit_num
].regno
= regno
;
6086 to_inherit
[to_inherit_num
++].insns
= insns
;
6089 /* Return the last non-debug insn in basic block BB, or the block begin
6092 get_last_insertion_point (basic_block bb
)
6096 FOR_BB_INSNS_REVERSE (bb
, insn
)
6097 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
6102 /* Set up RES by registers living on edges FROM except the edge (FROM,
6103 TO) or by registers set up in a jump insn in BB FROM. */
6105 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
6108 struct lra_insn_reg
*reg
;
6112 lra_assert (to
!= NULL
);
6114 FOR_EACH_EDGE (e
, ei
, from
->succs
)
6116 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
6117 last
= get_last_insertion_point (from
);
6118 if (! JUMP_P (last
))
6120 curr_id
= lra_get_insn_recog_data (last
);
6121 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6122 if (reg
->type
!= OP_IN
)
6123 bitmap_set_bit (res
, reg
->regno
);
6126 /* Used as a temporary results of some bitmap calculations. */
6127 static bitmap_head temp_bitmap
;
6129 /* We split for reloads of small class of hard regs. The following
6130 defines how many hard regs the class should have to be qualified as
6131 small. The code is mostly oriented to x86/x86-64 architecture
6132 where some insns need to use only specific register or pair of
6133 registers and these register can live in RTL explicitly, e.g. for
6134 parameter passing. */
6135 static const int max_small_class_regs_num
= 2;
6137 /* Do inheritance/split transformations in EBB starting with HEAD and
6138 finishing on TAIL. We process EBB insns in the reverse order.
6139 Return true if we did any inheritance/split transformation in the
6142 We should avoid excessive splitting which results in worse code
6143 because of inaccurate cost calculations for spilling new split
6144 pseudos in such case. To achieve this we do splitting only if
6145 register pressure is high in given basic block and there are reload
6146 pseudos requiring hard registers. We could do more register
6147 pressure calculations at any given program point to avoid necessary
6148 splitting even more but it is to expensive and the current approach
6149 works well enough. */
6151 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6153 int i
, src_regno
, dst_regno
, nregs
;
6154 bool change_p
, succ_p
, update_reloads_num_p
;
6155 rtx_insn
*prev_insn
, *last_insn
;
6156 rtx next_usage_insns
, curr_set
;
6158 struct lra_insn_reg
*reg
;
6159 basic_block last_processed_bb
, curr_bb
= NULL
;
6160 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6164 bool head_p
, after_p
;
6167 curr_usage_insns_check
++;
6168 clear_invariants ();
6169 reloads_num
= calls_num
= 0;
6170 bitmap_clear (&check_only_regs
);
6171 bitmap_clear (&invalid_invariant_regs
);
6172 last_processed_bb
= NULL
;
6173 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6174 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
6175 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
6176 /* We don't process new insns generated in the loop. */
6177 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6179 prev_insn
= PREV_INSN (curr_insn
);
6180 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6181 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6182 if (last_processed_bb
!= curr_bb
)
6184 /* We are at the end of BB. Add qualified living
6185 pseudos for potential splitting. */
6186 to_process
= df_get_live_out (curr_bb
);
6187 if (last_processed_bb
!= NULL
)
6189 /* We are somewhere in the middle of EBB. */
6190 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6192 to_process
= &temp_bitmap
;
6194 last_processed_bb
= curr_bb
;
6195 last_insn
= get_last_insertion_point (curr_bb
);
6196 after_p
= (! JUMP_P (last_insn
)
6197 && (! CALL_P (last_insn
)
6198 || (find_reg_note (last_insn
,
6199 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6200 && ! SIBLING_CALL_P (last_insn
))));
6201 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6202 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6204 if ((int) j
>= lra_constraint_new_regno_start
)
6206 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6208 if (j
< FIRST_PSEUDO_REGISTER
)
6209 SET_HARD_REG_BIT (live_hard_regs
, j
);
6211 add_to_hard_reg_set (&live_hard_regs
,
6212 PSEUDO_REGNO_MODE (j
),
6214 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6218 src_regno
= dst_regno
= -1;
6219 curr_set
= single_set (curr_insn
);
6220 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6221 dst_regno
= REGNO (SET_DEST (curr_set
));
6222 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6223 src_regno
= REGNO (SET_SRC (curr_set
));
6224 update_reloads_num_p
= true;
6225 if (src_regno
< lra_constraint_new_regno_start
6226 && src_regno
>= FIRST_PSEUDO_REGISTER
6227 && reg_renumber
[src_regno
] < 0
6228 && dst_regno
>= lra_constraint_new_regno_start
6229 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6231 /* 'reload_pseudo <- original_pseudo'. */
6232 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6234 update_reloads_num_p
= false;
6236 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6237 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6238 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6239 curr_insn
, next_usage_insns
);
6243 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6244 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6245 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6246 reg_class_contents
[cl
]);
6248 else if (src_regno
< 0
6249 && dst_regno
>= lra_constraint_new_regno_start
6250 && invariant_p (SET_SRC (curr_set
))
6251 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6252 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6253 && ! bitmap_bit_p (&invalid_invariant_regs
,
6254 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6256 /* 'reload_pseudo <- invariant'. */
6257 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6259 update_reloads_num_p
= false;
6260 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6262 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6263 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6264 reg_class_contents
[cl
]);
6266 else if (src_regno
>= lra_constraint_new_regno_start
6267 && dst_regno
< lra_constraint_new_regno_start
6268 && dst_regno
>= FIRST_PSEUDO_REGISTER
6269 && reg_renumber
[dst_regno
] < 0
6270 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6271 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6272 && (next_usage_insns
6273 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6275 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6277 update_reloads_num_p
= false;
6278 /* 'original_pseudo <- reload_pseudo'. */
6279 if (! JUMP_P (curr_insn
)
6280 && inherit_reload_reg (true, dst_regno
, cl
,
6281 curr_insn
, next_usage_insns
))
6284 usage_insns
[dst_regno
].check
= 0;
6285 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6286 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6287 reg_class_contents
[cl
]);
6289 else if (INSN_P (curr_insn
))
6292 int max_uid
= get_max_uid ();
6294 curr_id
= lra_get_insn_recog_data (curr_insn
);
6295 curr_static_id
= curr_id
->insn_static_data
;
6297 /* Process insn definitions. */
6298 for (iter
= 0; iter
< 2; iter
++)
6299 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6302 if (reg
->type
!= OP_IN
6303 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6305 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6306 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6307 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6308 && (next_usage_insns
6309 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6311 struct lra_insn_reg
*r
;
6313 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6314 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6316 /* Don't do inheritance if the pseudo is also
6317 used in the insn. */
6319 /* We can not do inheritance right now
6320 because the current insn reg info (chain
6321 regs) can change after that. */
6322 add_to_inherit (dst_regno
, next_usage_insns
);
6324 /* We can not process one reg twice here because of
6325 usage_insns invalidation. */
6326 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6327 || reg_renumber
[dst_regno
] >= 0)
6328 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6332 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6333 potential_reload_hard_regs
,
6334 false, curr_insn
, max_uid
))
6336 CLEAR_HARD_REG_SET (s
);
6337 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6338 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6340 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6341 reg_renumber
[dst_regno
]);
6342 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
6344 /* We should invalidate potential inheritance or
6345 splitting for the current insn usages to the next
6346 usage insns (see code below) as the output pseudo
6348 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6349 && reg_renumber
[dst_regno
] < 0)
6350 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6351 && (dst_regno
< FIRST_PSEUDO_REGISTER
6352 || reg_renumber
[dst_regno
] >= 0)))
6354 /* Invalidate and mark definitions. */
6355 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6356 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6359 nregs
= hard_regno_nregs (dst_regno
,
6361 for (i
= 0; i
< nregs
; i
++)
6362 usage_insns
[dst_regno
+ i
].check
6363 = -(int) INSN_UID (curr_insn
);
6367 /* Process clobbered call regs. */
6368 if (curr_id
->arg_hard_regs
!= NULL
)
6369 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6370 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6371 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6372 = -(int) INSN_UID (curr_insn
);
6373 if (! JUMP_P (curr_insn
))
6374 for (i
= 0; i
< to_inherit_num
; i
++)
6375 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6376 ALL_REGS
, curr_insn
,
6377 to_inherit
[i
].insns
))
6379 if (CALL_P (curr_insn
))
6381 rtx cheap
, pat
, dest
;
6383 int regno
, hard_regno
;
6386 if ((cheap
= find_reg_note (curr_insn
,
6387 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6388 && ((cheap
= XEXP (cheap
, 0)), true)
6389 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6390 && (hard_regno
= reg_renumber
[regno
]) >= 0
6391 && usage_insns
[regno
].check
== curr_usage_insns_check
6392 /* If there are pending saves/restores, the
6393 optimization is not worth. */
6394 && usage_insns
[regno
].calls_num
== calls_num
- 1
6395 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6397 /* Restore the pseudo from the call result as
6398 REG_RETURNED note says that the pseudo value is
6399 in the call result and the pseudo is an argument
6401 pat
= PATTERN (curr_insn
);
6402 if (GET_CODE (pat
) == PARALLEL
)
6403 pat
= XVECEXP (pat
, 0, 0);
6404 dest
= SET_DEST (pat
);
6405 /* For multiple return values dest is PARALLEL.
6406 Currently we handle only single return value case. */
6410 emit_move_insn (cheap
, copy_rtx (dest
));
6411 restore
= get_insns ();
6413 lra_process_new_insns (curr_insn
, NULL
, restore
,
6414 "Inserting call parameter restore");
6415 /* We don't need to save/restore of the pseudo from
6417 usage_insns
[regno
].calls_num
= calls_num
;
6418 bitmap_set_bit (&check_only_regs
, regno
);
6423 /* Process insn usages. */
6424 for (iter
= 0; iter
< 2; iter
++)
6425 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6428 if ((reg
->type
!= OP_OUT
6429 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6430 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6432 if (src_regno
>= FIRST_PSEUDO_REGISTER
6433 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6435 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6436 && (next_usage_insns
6437 = usage_insns
[src_regno
].insns
) != NULL_RTX
6438 && NONDEBUG_INSN_P (curr_insn
))
6439 add_to_inherit (src_regno
, next_usage_insns
);
6440 else if (usage_insns
[src_regno
].check
6441 != -(int) INSN_UID (curr_insn
))
6442 /* Add usages but only if the reg is not set up
6443 in the same insn. */
6444 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6446 else if (src_regno
< FIRST_PSEUDO_REGISTER
6447 || reg_renumber
[src_regno
] >= 0)
6450 rtx_insn
*use_insn
= curr_insn
;
6452 before_p
= (JUMP_P (curr_insn
)
6453 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6454 if (NONDEBUG_INSN_P (curr_insn
)
6455 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6456 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6457 potential_reload_hard_regs
,
6458 before_p
, curr_insn
, max_uid
))
6461 lra_risky_transformations_p
= true;
6464 usage_insns
[src_regno
].check
= 0;
6466 use_insn
= PREV_INSN (curr_insn
);
6468 if (NONDEBUG_INSN_P (curr_insn
))
6470 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6471 add_to_hard_reg_set (&live_hard_regs
,
6472 reg
->biggest_mode
, src_regno
);
6474 add_to_hard_reg_set (&live_hard_regs
,
6475 PSEUDO_REGNO_MODE (src_regno
),
6476 reg_renumber
[src_regno
]);
6478 if (src_regno
>= FIRST_PSEUDO_REGISTER
)
6479 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6482 for (i
= 0; i
< hard_regno_nregs (src_regno
, reg
->biggest_mode
); i
++)
6483 add_next_usage_insn (src_regno
+ i
, use_insn
, reloads_num
);
6487 /* Process used call regs. */
6488 if (curr_id
->arg_hard_regs
!= NULL
)
6489 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6490 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6492 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6493 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6495 for (i
= 0; i
< to_inherit_num
; i
++)
6497 src_regno
= to_inherit
[i
].regno
;
6498 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6499 curr_insn
, to_inherit
[i
].insns
))
6502 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6505 if (update_reloads_num_p
6506 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6509 if ((REG_P (SET_DEST (curr_set
))
6510 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6511 && reg_renumber
[regno
] < 0
6512 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6513 || (REG_P (SET_SRC (curr_set
))
6514 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6515 && reg_renumber
[regno
] < 0
6516 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6518 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6520 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6521 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6522 reg_class_contents
[cl
]);
6525 if (NONDEBUG_INSN_P (curr_insn
))
6529 /* Invalidate invariants with changed regs. */
6530 curr_id
= lra_get_insn_recog_data (curr_insn
);
6531 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6532 if (reg
->type
!= OP_IN
)
6534 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6535 bitmap_set_bit (&invalid_invariant_regs
,
6536 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6538 curr_static_id
= curr_id
->insn_static_data
;
6539 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6540 if (reg
->type
!= OP_IN
)
6541 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6542 if (curr_id
->arg_hard_regs
!= NULL
)
6543 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6544 if (regno
>= FIRST_PSEUDO_REGISTER
)
6545 bitmap_set_bit (&invalid_invariant_regs
,
6546 regno
- FIRST_PSEUDO_REGISTER
);
6548 /* We reached the start of the current basic block. */
6549 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6550 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6552 /* We reached the beginning of the current block -- do
6553 rest of spliting in the current BB. */
6554 to_process
= df_get_live_in (curr_bb
);
6555 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6557 /* We are somewhere in the middle of EBB. */
6558 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6559 curr_bb
, &temp_bitmap
);
6560 to_process
= &temp_bitmap
;
6563 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6565 if ((int) j
>= lra_constraint_new_regno_start
)
6567 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6568 && usage_insns
[j
].check
== curr_usage_insns_check
6569 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6571 if (need_for_split_p (potential_reload_hard_regs
, j
))
6573 if (lra_dump_file
!= NULL
&& head_p
)
6575 fprintf (lra_dump_file
,
6576 " ----------------------------------\n");
6579 if (split_reg (false, j
, bb_note (curr_bb
),
6580 next_usage_insns
, NULL
))
6583 usage_insns
[j
].check
= 0;
6591 /* This value affects EBB forming. If probability of edge from EBB to
6592 a BB is not greater than the following value, we don't add the BB
6594 #define EBB_PROBABILITY_CUTOFF \
6595 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6597 /* Current number of inheritance/split iteration. */
6598 int lra_inheritance_iter
;
6600 /* Entry function for inheritance/split pass. */
6602 lra_inheritance (void)
6605 basic_block bb
, start_bb
;
6608 lra_inheritance_iter
++;
6609 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6611 timevar_push (TV_LRA_INHERITANCE
);
6612 if (lra_dump_file
!= NULL
)
6613 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6614 lra_inheritance_iter
);
6615 curr_usage_insns_check
= 0;
6616 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6617 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6618 usage_insns
[i
].check
= 0;
6619 bitmap_initialize (&check_only_regs
, ®_obstack
);
6620 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6621 bitmap_initialize (&live_regs
, ®_obstack
);
6622 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6623 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6624 FOR_EACH_BB_FN (bb
, cfun
)
6627 if (lra_dump_file
!= NULL
)
6628 fprintf (lra_dump_file
, "EBB");
6629 /* Form a EBB starting with BB. */
6630 bitmap_clear (&ebb_global_regs
);
6631 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6634 if (lra_dump_file
!= NULL
)
6635 fprintf (lra_dump_file
, " %d", bb
->index
);
6636 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6637 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6639 e
= find_fallthru_edge (bb
->succs
);
6642 if (e
->probability
.initialized_p ()
6643 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6647 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6648 if (lra_dump_file
!= NULL
)
6649 fprintf (lra_dump_file
, "\n");
6650 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6651 /* Remember that the EBB head and tail can change in
6653 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6655 bitmap_release (&ebb_global_regs
);
6656 bitmap_release (&temp_bitmap
);
6657 bitmap_release (&live_regs
);
6658 bitmap_release (&invalid_invariant_regs
);
6659 bitmap_release (&check_only_regs
);
6662 timevar_pop (TV_LRA_INHERITANCE
);
6667 /* This page contains code to undo failed inheritance/split
6670 /* Current number of iteration undoing inheritance/split. */
6671 int lra_undo_inheritance_iter
;
6673 /* Fix BB live info LIVE after removing pseudos created on pass doing
6674 inheritance/split which are REMOVED_PSEUDOS. */
6676 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6681 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6682 if (bitmap_clear_bit (live
, regno
)
6683 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6684 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6687 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6692 if (GET_CODE (reg
) == SUBREG
)
6693 reg
= SUBREG_REG (reg
);
6699 /* Delete a move INSN with destination reg DREGNO and a previous
6700 clobber insn with the same regno. The inheritance/split code can
6701 generate moves with preceding clobber and when we delete such moves
6702 we should delete the clobber insn too to keep the correct life
6705 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6707 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6709 lra_set_insn_deleted (insn
);
6710 lra_assert (dregno
>= 0);
6711 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6712 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6713 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6714 lra_set_insn_deleted (prev_insn
);
6717 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6718 return true if we did any change. The undo transformations for
6719 inheritance looks like
6723 p <- i, i <- p, and i <- i3
6724 where p is original pseudo from which inheritance pseudo i was
6725 created, i and i3 are removed inheritance pseudos, i2 is another
6726 not removed inheritance pseudo. All split pseudos or other
6727 occurrences of removed inheritance pseudos are changed on the
6728 corresponding original pseudos.
6730 The function also schedules insns changed and created during
6731 inheritance/split pass for processing by the subsequent constraint
6734 remove_inheritance_pseudos (bitmap remove_pseudos
)
6737 int regno
, sregno
, prev_sregno
, dregno
;
6740 rtx_insn
*prev_insn
;
6741 bool change_p
, done_p
;
6743 change_p
= ! bitmap_empty_p (remove_pseudos
);
6744 /* We can not finish the function right away if CHANGE_P is true
6745 because we need to marks insns affected by previous
6746 inheritance/split pass for processing by the subsequent
6748 FOR_EACH_BB_FN (bb
, cfun
)
6750 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6751 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6752 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6754 if (! INSN_P (curr_insn
))
6757 sregno
= dregno
= -1;
6758 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6759 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6761 dregno
= get_regno (SET_DEST (set
));
6762 sregno
= get_regno (SET_SRC (set
));
6765 if (sregno
>= 0 && dregno
>= 0)
6767 if (bitmap_bit_p (remove_pseudos
, dregno
)
6768 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6770 /* invariant inheritance pseudo <- original pseudo */
6771 if (lra_dump_file
!= NULL
)
6773 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6774 dump_insn_slim (lra_dump_file
, curr_insn
);
6775 fprintf (lra_dump_file
, "\n");
6777 delete_move_and_clobber (curr_insn
, dregno
);
6780 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6781 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6783 /* reload pseudo <- invariant inheritance pseudo */
6785 /* We can not just change the source. It might be
6786 an insn different from the move. */
6787 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6788 rtx_insn
*new_insns
= get_insns ();
6790 lra_assert (single_set (new_insns
) != NULL
6791 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6792 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6793 "Changing reload<-invariant inheritance");
6794 delete_move_and_clobber (curr_insn
, dregno
);
6797 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6798 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6799 || (bitmap_bit_p (remove_pseudos
, dregno
)
6800 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6801 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6802 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6803 || (bitmap_bit_p (remove_pseudos
, dregno
)
6804 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6805 /* One of the following cases:
6806 original <- removed inheritance pseudo
6807 removed inherit pseudo <- another removed inherit pseudo
6808 removed inherit pseudo <- original pseudo
6810 removed_split_pseudo <- original_reg
6811 original_reg <- removed_split_pseudo */
6813 if (lra_dump_file
!= NULL
)
6815 fprintf (lra_dump_file
, " Removing %s:\n",
6816 bitmap_bit_p (&lra_split_regs
, sregno
)
6817 || bitmap_bit_p (&lra_split_regs
, dregno
)
6818 ? "split" : "inheritance");
6819 dump_insn_slim (lra_dump_file
, curr_insn
);
6821 delete_move_and_clobber (curr_insn
, dregno
);
6824 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6825 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6827 /* Search the following pattern:
6828 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6829 original_pseudo <- inherit_or_split_pseudo1
6830 where the 2nd insn is the current insn and
6831 inherit_or_split_pseudo2 is not removed. If it is found,
6832 change the current insn onto:
6833 original_pseudo <- inherit_or_split_pseudo2. */
6834 for (prev_insn
= PREV_INSN (curr_insn
);
6835 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6836 prev_insn
= PREV_INSN (prev_insn
))
6838 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6839 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6840 /* There should be no subregs in insn we are
6841 searching because only the original reg might
6842 be in subreg when we changed the mode of
6843 load/store for splitting. */
6844 && REG_P (SET_DEST (prev_set
))
6845 && REG_P (SET_SRC (prev_set
))
6846 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6847 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6848 >= FIRST_PSEUDO_REGISTER
)
6849 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6851 /* As we consider chain of inheritance or
6852 splitting described in above comment we should
6853 check that sregno and prev_sregno were
6854 inheritance/split pseudos created from the
6855 same original regno. */
6856 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6857 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6858 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6859 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6861 lra_assert (GET_MODE (SET_SRC (prev_set
))
6862 == GET_MODE (regno_reg_rtx
[sregno
]));
6863 /* Although we have a single set, the insn can
6864 contain more one sregno register occurrence
6865 as a source. Change all occurrences. */
6866 lra_substitute_pseudo_within_insn (curr_insn
, sregno
,
6869 /* As we are finishing with processing the insn
6870 here, check the destination too as it might
6871 inheritance pseudo for another pseudo. */
6872 if (bitmap_bit_p (remove_pseudos
, dregno
)
6873 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6875 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6877 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6878 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6880 SET_DEST (set
) = restore_rtx
;
6882 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6883 lra_set_used_insn_alternative_by_uid
6884 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
6886 if (lra_dump_file
!= NULL
)
6888 fprintf (lra_dump_file
, " Change reload insn:\n");
6889 dump_insn_slim (lra_dump_file
, curr_insn
);
6896 struct lra_insn_reg
*reg
;
6897 bool restored_regs_p
= false;
6898 bool kept_regs_p
= false;
6900 curr_id
= lra_get_insn_recog_data (curr_insn
);
6901 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6904 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6905 if (restore_rtx
!= NULL_RTX
)
6907 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6909 lra_substitute_pseudo_within_insn
6910 (curr_insn
, regno
, restore_rtx
, false);
6911 restored_regs_p
= true;
6917 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6919 /* The instruction has changed since the previous
6920 constraints pass. */
6921 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6922 lra_set_used_insn_alternative_by_uid
6923 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
6925 else if (restored_regs_p
)
6926 /* The instruction has been restored to the form that
6927 it had during the previous constraints pass. */
6928 lra_update_insn_regno_info (curr_insn
);
6929 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6931 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6932 dump_insn_slim (lra_dump_file
, curr_insn
);
6940 /* If optional reload pseudos failed to get a hard register or was not
6941 inherited, it is better to remove optional reloads. We do this
6942 transformation after undoing inheritance to figure out necessity to
6943 remove optional reloads easier. Return true if we do any
6946 undo_optional_reloads (void)
6948 bool change_p
, keep_p
;
6949 unsigned int regno
, uid
;
6950 bitmap_iterator bi
, bi2
;
6953 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
6955 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6956 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6959 /* Keep optional reloads from previous subpasses. */
6960 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6961 /* If the original pseudo changed its allocation, just
6962 removing the optional pseudo is dangerous as the original
6963 pseudo will have longer live range. */
6964 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6966 else if (reg_renumber
[regno
] >= 0)
6967 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6969 insn
= lra_insn_recog_data
[uid
]->insn
;
6970 if ((set
= single_set (insn
)) == NULL_RTX
)
6972 src
= SET_SRC (set
);
6973 dest
= SET_DEST (set
);
6974 if (! REG_P (src
) || ! REG_P (dest
))
6976 if (REGNO (dest
) == regno
6977 /* Ignore insn for optional reloads itself. */
6978 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6979 /* Check only inheritance on last inheritance pass. */
6980 && (int) REGNO (src
) >= new_regno_start
6981 /* Check that the optional reload was inherited. */
6982 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6990 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
6991 if (lra_dump_file
!= NULL
)
6992 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6995 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
6996 auto_bitmap
insn_bitmap (®_obstack
);
6997 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
6999 if (lra_dump_file
!= NULL
)
7000 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
7001 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
7002 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
7004 insn
= lra_insn_recog_data
[uid
]->insn
;
7005 if ((set
= single_set (insn
)) != NULL_RTX
)
7007 src
= SET_SRC (set
);
7008 dest
= SET_DEST (set
);
7009 if (REG_P (src
) && REG_P (dest
)
7010 && ((REGNO (src
) == regno
7011 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
7013 || (REGNO (dest
) == regno
7014 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
7017 if (lra_dump_file
!= NULL
)
7019 fprintf (lra_dump_file
, " Deleting move %u\n",
7021 dump_insn_slim (lra_dump_file
, insn
);
7023 delete_move_and_clobber (insn
, REGNO (dest
));
7026 /* We should not worry about generation memory-memory
7027 moves here as if the corresponding inheritance did
7028 not work (inheritance pseudo did not get a hard reg),
7029 we remove the inheritance pseudo and the optional
7032 lra_substitute_pseudo_within_insn
7033 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
7034 lra_update_insn_regno_info (insn
);
7035 if (lra_dump_file
!= NULL
)
7037 fprintf (lra_dump_file
,
7038 " Restoring original insn:\n");
7039 dump_insn_slim (lra_dump_file
, insn
);
7043 /* Clear restore_regnos. */
7044 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7045 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7049 /* Entry function for undoing inheritance/split transformation. Return true
7050 if we did any RTL change in this pass. */
7052 lra_undo_inheritance (void)
7056 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
7061 lra_undo_inheritance_iter
++;
7062 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7064 if (lra_dump_file
!= NULL
)
7065 fprintf (lra_dump_file
,
7066 "\n********** Undoing inheritance #%d: **********\n\n",
7067 lra_undo_inheritance_iter
);
7068 auto_bitmap
remove_pseudos (®_obstack
);
7069 n_inherit
= n_all_inherit
= 0;
7070 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7071 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
7074 if (reg_renumber
[regno
] < 0
7075 /* If the original pseudo changed its allocation, just
7076 removing inheritance is dangerous as for changing
7077 allocation we used shorter live-ranges. */
7078 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
7079 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
7080 bitmap_set_bit (remove_pseudos
, regno
);
7084 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
7085 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
7086 n_inherit
, n_all_inherit
,
7087 (double) n_inherit
/ n_all_inherit
* 100);
7088 n_split
= n_all_split
= 0;
7089 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7090 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
7092 int restore_regno
= REGNO (restore_rtx
);
7095 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
7096 ? reg_renumber
[restore_regno
] : restore_regno
);
7097 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
7098 bitmap_set_bit (remove_pseudos
, regno
);
7102 if (lra_dump_file
!= NULL
)
7103 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
7104 regno
, restore_regno
);
7107 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
7108 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
7109 n_split
, n_all_split
,
7110 (double) n_split
/ n_all_split
* 100);
7111 change_p
= remove_inheritance_pseudos (remove_pseudos
);
7112 /* Clear restore_regnos. */
7113 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7114 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7115 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7116 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7117 change_p
= undo_optional_reloads () || change_p
;