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1 This is Info file gcc.info, produced by Makeinfo version 1.67 from the
2 input file gcc.texi.
4 This file documents the use and the internals of the GNU compiler.
6 Published by the Free Software Foundation 59 Temple Place - Suite 330
7 Boston, MA 02111-1307 USA
9 Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998
10 Free Software Foundation, Inc.
12 Permission is granted to make and distribute verbatim copies of this
13 manual provided the copyright notice and this permission notice are
14 preserved on all copies.
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17 this manual under the conditions for verbatim copying, provided also
18 that the sections entitled "GNU General Public License," "Funding for
19 Free Software," and "Protect Your Freedom--Fight `Look And Feel'" are
20 included exactly as in the original, and provided that the entire
21 resulting derived work is distributed under the terms of a permission
22 notice identical to this one.
24 Permission is granted to copy and distribute translations of this
25 manual into another language, under the above conditions for modified
26 versions, except that the sections entitled "GNU General Public
27 License," "Funding for Free Software," and "Protect Your Freedom--Fight
28 `Look And Feel'", and this permission notice, may be included in
29 translations approved by the Free Software Foundation instead of in the
30 original English.
32 \x1f
33 File: gcc.info, Node: Regs and Memory, Next: Arithmetic, Prev: Constants, Up: RTL
35 Registers and Memory
36 ====================
38 Here are the RTL expression types for describing access to machine
39 registers and to main memory.
41 `(reg:M N)'
42 For small values of the integer N (those that are less than
43 `FIRST_PSEUDO_REGISTER'), this stands for a reference to machine
44 register number N: a "hard register". For larger values of N, it
45 stands for a temporary value or "pseudo register". The compiler's
46 strategy is to generate code assuming an unlimited number of such
47 pseudo registers, and later convert them into hard registers or
48 into memory references.
50 M is the machine mode of the reference. It is necessary because
51 machines can generally refer to each register in more than one
52 mode. For example, a register may contain a full word but there
53 may be instructions to refer to it as a half word or as a single
54 byte, as well as instructions to refer to it as a floating point
55 number of various precisions.
57 Even for a register that the machine can access in only one mode,
58 the mode must always be specified.
60 The symbol `FIRST_PSEUDO_REGISTER' is defined by the machine
61 description, since the number of hard registers on the machine is
62 an invariant characteristic of the machine. Note, however, that
63 not all of the machine registers must be general registers. All
64 the machine registers that can be used for storage of data are
65 given hard register numbers, even those that can be used only in
66 certain instructions or can hold only certain types of data.
68 A hard register may be accessed in various modes throughout one
69 function, but each pseudo register is given a natural mode and is
70 accessed only in that mode. When it is necessary to describe an
71 access to a pseudo register using a nonnatural mode, a `subreg'
72 expression is used.
74 A `reg' expression with a machine mode that specifies more than
75 one word of data may actually stand for several consecutive
76 registers. If in addition the register number specifies a
77 hardware register, then it actually represents several consecutive
78 hardware registers starting with the specified one.
80 Each pseudo register number used in a function's RTL code is
81 represented by a unique `reg' expression.
83 Some pseudo register numbers, those within the range of
84 `FIRST_VIRTUAL_REGISTER' to `LAST_VIRTUAL_REGISTER' only appear
85 during the RTL generation phase and are eliminated before the
86 optimization phases. These represent locations in the stack frame
87 that cannot be determined until RTL generation for the function
88 has been completed. The following virtual register numbers are
89 defined:
91 `VIRTUAL_INCOMING_ARGS_REGNUM'
92 This points to the first word of the incoming arguments
93 passed on the stack. Normally these arguments are placed
94 there by the caller, but the callee may have pushed some
95 arguments that were previously passed in registers.
97 When RTL generation is complete, this virtual register is
98 replaced by the sum of the register given by
99 `ARG_POINTER_REGNUM' and the value of `FIRST_PARM_OFFSET'.
101 `VIRTUAL_STACK_VARS_REGNUM'
102 If `FRAME_GROWS_DOWNWARD' is defined, this points to
103 immediately above the first variable on the stack.
104 Otherwise, it points to the first variable on the stack.
106 `VIRTUAL_STACK_VARS_REGNUM' is replaced with the sum of the
107 register given by `FRAME_POINTER_REGNUM' and the value
108 `STARTING_FRAME_OFFSET'.
110 `VIRTUAL_STACK_DYNAMIC_REGNUM'
111 This points to the location of dynamically allocated memory
112 on the stack immediately after the stack pointer has been
113 adjusted by the amount of memory desired.
115 This virtual register is replaced by the sum of the register
116 given by `STACK_POINTER_REGNUM' and the value
117 `STACK_DYNAMIC_OFFSET'.
119 `VIRTUAL_OUTGOING_ARGS_REGNUM'
120 This points to the location in the stack at which outgoing
121 arguments should be written when the stack is pre-pushed
122 (arguments pushed using push insns should always use
123 `STACK_POINTER_REGNUM').
125 This virtual register is replaced by the sum of the register
126 given by `STACK_POINTER_REGNUM' and the value
127 `STACK_POINTER_OFFSET'.
129 `(subreg:M REG WORDNUM)'
130 `subreg' expressions are used to refer to a register in a machine
131 mode other than its natural one, or to refer to one register of a
132 multi-word `reg' that actually refers to several registers.
134 Each pseudo-register has a natural mode. If it is necessary to
135 operate on it in a different mode--for example, to perform a
136 fullword move instruction on a pseudo-register that contains a
137 single byte--the pseudo-register must be enclosed in a `subreg'.
138 In such a case, WORDNUM is zero.
140 Usually M is at least as narrow as the mode of REG, in which case
141 it is restricting consideration to only the bits of REG that are
142 in M.
144 Sometimes M is wider than the mode of REG. These `subreg'
145 expressions are often called "paradoxical". They are used in
146 cases where we want to refer to an object in a wider mode but do
147 not care what value the additional bits have. The reload pass
148 ensures that paradoxical references are only made to hard
149 registers.
151 The other use of `subreg' is to extract the individual registers of
152 a multi-register value. Machine modes such as `DImode' and
153 `TImode' can indicate values longer than a word, values which
154 usually require two or more consecutive registers. To access one
155 of the registers, use a `subreg' with mode `SImode' and a WORDNUM
156 that says which register.
158 Storing in a non-paradoxical `subreg' has undefined results for
159 bits belonging to the same word as the `subreg'. This laxity makes
160 it easier to generate efficient code for such instructions. To
161 represent an instruction that preserves all the bits outside of
162 those in the `subreg', use `strict_low_part' around the `subreg'.
164 The compilation parameter `WORDS_BIG_ENDIAN', if set to 1, says
165 that word number zero is the most significant part; otherwise, it
166 is the least significant part.
168 Between the combiner pass and the reload pass, it is possible to
169 have a paradoxical `subreg' which contains a `mem' instead of a
170 `reg' as its first operand. After the reload pass, it is also
171 possible to have a non-paradoxical `subreg' which contains a
172 `mem'; this usually occurs when the `mem' is a stack slot which
173 replaced a pseudo register.
175 Note that it is not valid to access a `DFmode' value in `SFmode'
176 using a `subreg'. On some machines the most significant part of a
177 `DFmode' value does not have the same format as a single-precision
178 floating value.
180 It is also not valid to access a single word of a multi-word value
181 in a hard register when less registers can hold the value than
182 would be expected from its size. For example, some 32-bit
183 machines have floating-point registers that can hold an entire
184 `DFmode' value. If register 10 were such a register `(subreg:SI
185 (reg:DF 10) 1)' would be invalid because there is no way to
186 convert that reference to a single machine register. The reload
187 pass prevents `subreg' expressions such as these from being formed.
189 The first operand of a `subreg' expression is customarily accessed
190 with the `SUBREG_REG' macro and the second operand is customarily
191 accessed with the `SUBREG_WORD' macro.
193 `(scratch:M)'
194 This represents a scratch register that will be required for the
195 execution of a single instruction and not used subsequently. It is
196 converted into a `reg' by either the local register allocator or
197 the reload pass.
199 `scratch' is usually present inside a `clobber' operation (*note
200 Side Effects::.).
202 `(cc0)'
203 This refers to the machine's condition code register. It has no
204 operands and may not have a machine mode. There are two ways to
205 use it:
207 * To stand for a complete set of condition code flags. This is
208 best on most machines, where each comparison sets the entire
209 series of flags.
211 With this technique, `(cc0)' may be validly used in only two
212 contexts: as the destination of an assignment (in test and
213 compare instructions) and in comparison operators comparing
214 against zero (`const_int' with value zero; that is to say,
215 `const0_rtx').
217 * To stand for a single flag that is the result of a single
218 condition. This is useful on machines that have only a
219 single flag bit, and in which comparison instructions must
220 specify the condition to test.
222 With this technique, `(cc0)' may be validly used in only two
223 contexts: as the destination of an assignment (in test and
224 compare instructions) where the source is a comparison
225 operator, and as the first operand of `if_then_else' (in a
226 conditional branch).
228 There is only one expression object of code `cc0'; it is the value
229 of the variable `cc0_rtx'. Any attempt to create an expression of
230 code `cc0' will return `cc0_rtx'.
232 Instructions can set the condition code implicitly. On many
233 machines, nearly all instructions set the condition code based on
234 the value that they compute or store. It is not necessary to
235 record these actions explicitly in the RTL because the machine
236 description includes a prescription for recognizing the
237 instructions that do so (by means of the macro
238 `NOTICE_UPDATE_CC'). *Note Condition Code::. Only instructions
239 whose sole purpose is to set the condition code, and instructions
240 that use the condition code, need mention `(cc0)'.
242 On some machines, the condition code register is given a register
243 number and a `reg' is used instead of `(cc0)'. This is usually the
244 preferable approach if only a small subset of instructions modify
245 the condition code. Other machines store condition codes in
246 general registers; in such cases a pseudo register should be used.
248 Some machines, such as the Sparc and RS/6000, have two sets of
249 arithmetic instructions, one that sets and one that does not set
250 the condition code. This is best handled by normally generating
251 the instruction that does not set the condition code, and making a
252 pattern that both performs the arithmetic and sets the condition
253 code register (which would not be `(cc0)' in this case). For
254 examples, search for `addcc' and `andcc' in `sparc.md'.
256 `(pc)'
257 This represents the machine's program counter. It has no operands
258 and may not have a machine mode. `(pc)' may be validly used only
259 in certain specific contexts in jump instructions.
261 There is only one expression object of code `pc'; it is the value
262 of the variable `pc_rtx'. Any attempt to create an expression of
263 code `pc' will return `pc_rtx'.
265 All instructions that do not jump alter the program counter
266 implicitly by incrementing it, but there is no need to mention
267 this in the RTL.
269 `(mem:M ADDR)'
270 This RTX represents a reference to main memory at an address
271 represented by the expression ADDR. M specifies how large a unit
272 of memory is accessed.
274 `(addressof:M REG)'
275 This RTX represents a request for the address of register REG.
276 Its mode is always `Pmode'. If there are any `addressof'
277 expressions left in the function after CSE, REG is forced into the
278 stack and the `addressof' expression is replaced with a `plus'
279 expression for the address of its stack slot.
281 \x1f
282 File: gcc.info, Node: Arithmetic, Next: Comparisons, Prev: Regs and Memory, Up: RTL
284 RTL Expressions for Arithmetic
285 ==============================
287 Unless otherwise specified, all the operands of arithmetic
288 expressions must be valid for mode M. An operand is valid for mode M
289 if it has mode M, or if it is a `const_int' or `const_double' and M is
290 a mode of class `MODE_INT'.
292 For commutative binary operations, constants should be placed in the
293 second operand.
295 `(plus:M X Y)'
296 Represents the sum of the values represented by X and Y carried
297 out in machine mode M.
299 `(lo_sum:M X Y)'
300 Like `plus', except that it represents that sum of X and the
301 low-order bits of Y. The number of low order bits is
302 machine-dependent but is normally the number of bits in a `Pmode'
303 item minus the number of bits set by the `high' code (*note
304 Constants::.).
306 M should be `Pmode'.
308 `(minus:M X Y)'
309 Like `plus' but represents subtraction.
311 `(compare:M X Y)'
312 Represents the result of subtracting Y from X for purposes of
313 comparison. The result is computed without overflow, as if with
314 infinite precision.
316 Of course, machines can't really subtract with infinite precision.
317 However, they can pretend to do so when only the sign of the
318 result will be used, which is the case when the result is stored
319 in the condition code. And that is the only way this kind of
320 expression may validly be used: as a value to be stored in the
321 condition codes.
323 The mode M is not related to the modes of X and Y, but instead is
324 the mode of the condition code value. If `(cc0)' is used, it is
325 `VOIDmode'. Otherwise it is some mode in class `MODE_CC', often
326 `CCmode'. *Note Condition Code::.
328 Normally, X and Y must have the same mode. Otherwise, `compare'
329 is valid only if the mode of X is in class `MODE_INT' and Y is a
330 `const_int' or `const_double' with mode `VOIDmode'. The mode of X
331 determines what mode the comparison is to be done in; thus it must
332 not be `VOIDmode'.
334 If one of the operands is a constant, it should be placed in the
335 second operand and the comparison code adjusted as appropriate.
337 A `compare' specifying two `VOIDmode' constants is not valid since
338 there is no way to know in what mode the comparison is to be
339 performed; the comparison must either be folded during the
340 compilation or the first operand must be loaded into a register
341 while its mode is still known.
343 `(neg:M X)'
344 Represents the negation (subtraction from zero) of the value
345 represented by X, carried out in mode M.
347 `(mult:M X Y)'
348 Represents the signed product of the values represented by X and Y
349 carried out in machine mode M.
351 Some machines support a multiplication that generates a product
352 wider than the operands. Write the pattern for this as
354 (mult:M (sign_extend:M X) (sign_extend:M Y))
356 where M is wider than the modes of X and Y, which need not be the
357 same.
359 Write patterns for unsigned widening multiplication similarly using
360 `zero_extend'.
362 `(div:M X Y)'
363 Represents the quotient in signed division of X by Y, carried out
364 in machine mode M. If M is a floating point mode, it represents
365 the exact quotient; otherwise, the integerized quotient.
367 Some machines have division instructions in which the operands and
368 quotient widths are not all the same; you should represent such
369 instructions using `truncate' and `sign_extend' as in,
371 (truncate:M1 (div:M2 X (sign_extend:M2 Y)))
373 `(udiv:M X Y)'
374 Like `div' but represents unsigned division.
376 `(mod:M X Y)'
377 `(umod:M X Y)'
378 Like `div' and `udiv' but represent the remainder instead of the
379 quotient.
381 `(smin:M X Y)'
382 `(smax:M X Y)'
383 Represents the smaller (for `smin') or larger (for `smax') of X
384 and Y, interpreted as signed integers in mode M.
386 `(umin:M X Y)'
387 `(umax:M X Y)'
388 Like `smin' and `smax', but the values are interpreted as unsigned
389 integers.
391 `(not:M X)'
392 Represents the bitwise complement of the value represented by X,
393 carried out in mode M, which must be a fixed-point machine mode.
395 `(and:M X Y)'
396 Represents the bitwise logical-and of the values represented by X
397 and Y, carried out in machine mode M, which must be a fixed-point
398 machine mode.
400 `(ior:M X Y)'
401 Represents the bitwise inclusive-or of the values represented by X
402 and Y, carried out in machine mode M, which must be a fixed-point
403 mode.
405 `(xor:M X Y)'
406 Represents the bitwise exclusive-or of the values represented by X
407 and Y, carried out in machine mode M, which must be a fixed-point
408 mode.
410 `(ashift:M X C)'
411 Represents the result of arithmetically shifting X left by C
412 places. X have mode M, a fixed-point machine mode. C be a
413 fixed-point mode or be a constant with mode `VOIDmode'; which mode
414 is determined by the mode called for in the machine description
415 entry for the left-shift instruction. For example, on the Vax,
416 the mode of C is `QImode' regardless of M.
418 `(lshiftrt:M X C)'
419 `(ashiftrt:M X C)'
420 Like `ashift' but for right shift. Unlike the case for left shift,
421 these two operations are distinct.
423 `(rotate:M X C)'
424 `(rotatert:M X C)'
425 Similar but represent left and right rotate. If C is a constant,
426 use `rotate'.
428 `(abs:M X)'
429 Represents the absolute value of X, computed in mode M.
431 `(sqrt:M X)'
432 Represents the square root of X, computed in mode M. Most often M
433 will be a floating point mode.
435 `(ffs:M X)'
436 Represents one plus the index of the least significant 1-bit in X,
437 represented as an integer of mode M. (The value is zero if X is
438 zero.) The mode of X need not be M; depending on the target
439 machine, various mode combinations may be valid.
441 \x1f
442 File: gcc.info, Node: Comparisons, Next: Bit Fields, Prev: Arithmetic, Up: RTL
444 Comparison Operations
445 =====================
447 Comparison operators test a relation on two operands and are
448 considered to represent a machine-dependent nonzero value described by,
449 but not necessarily equal to, `STORE_FLAG_VALUE' (*note Misc::.) if the
450 relation holds, or zero if it does not. The mode of the comparison
451 operation is independent of the mode of the data being compared. If
452 the comparison operation is being tested (e.g., the first operand of an
453 `if_then_else'), the mode must be `VOIDmode'. If the comparison
454 operation is producing data to be stored in some variable, the mode
455 must be in class `MODE_INT'. All comparison operations producing data
456 must use the same mode, which is machine-specific.
458 There are two ways that comparison operations may be used. The
459 comparison operators may be used to compare the condition codes `(cc0)'
460 against zero, as in `(eq (cc0) (const_int 0))'. Such a construct
461 actually refers to the result of the preceding instruction in which the
462 condition codes were set. The instructing setting the condition code
463 must be adjacent to the instruction using the condition code; only
464 `note' insns may separate them.
466 Alternatively, a comparison operation may directly compare two data
467 objects. The mode of the comparison is determined by the operands; they
468 must both be valid for a common machine mode. A comparison with both
469 operands constant would be invalid as the machine mode could not be
470 deduced from it, but such a comparison should never exist in RTL due to
471 constant folding.
473 In the example above, if `(cc0)' were last set to `(compare X Y)',
474 the comparison operation is identical to `(eq X Y)'. Usually only one
475 style of comparisons is supported on a particular machine, but the
476 combine pass will try to merge the operations to produce the `eq' shown
477 in case it exists in the context of the particular insn involved.
479 Inequality comparisons come in two flavors, signed and unsigned.
480 Thus, there are distinct expression codes `gt' and `gtu' for signed and
481 unsigned greater-than. These can produce different results for the same
482 pair of integer values: for example, 1 is signed greater-than -1 but not
483 unsigned greater-than, because -1 when regarded as unsigned is actually
484 `0xffffffff' which is greater than 1.
486 The signed comparisons are also used for floating point values.
487 Floating point comparisons are distinguished by the machine modes of
488 the operands.
490 `(eq:M X Y)'
491 1 if the values represented by X and Y are equal, otherwise 0.
493 `(ne:M X Y)'
494 1 if the values represented by X and Y are not equal, otherwise 0.
496 `(gt:M X Y)'
497 1 if the X is greater than Y. If they are fixed-point, the
498 comparison is done in a signed sense.
500 `(gtu:M X Y)'
501 Like `gt' but does unsigned comparison, on fixed-point numbers
502 only.
504 `(lt:M X Y)'
505 `(ltu:M X Y)'
506 Like `gt' and `gtu' but test for "less than".
508 `(ge:M X Y)'
509 `(geu:M X Y)'
510 Like `gt' and `gtu' but test for "greater than or equal".
512 `(le:M X Y)'
513 `(leu:M X Y)'
514 Like `gt' and `gtu' but test for "less than or equal".
516 `(if_then_else COND THEN ELSE)'
517 This is not a comparison operation but is listed here because it is
518 always used in conjunction with a comparison operation. To be
519 precise, COND is a comparison expression. This expression
520 represents a choice, according to COND, between the value
521 represented by THEN and the one represented by ELSE.
523 On most machines, `if_then_else' expressions are valid only to
524 express conditional jumps.
526 `(cond [TEST1 VALUE1 TEST2 VALUE2 ...] DEFAULT)'
527 Similar to `if_then_else', but more general. Each of TEST1,
528 TEST2, ... is performed in turn. The result of this expression is
529 the VALUE corresponding to the first non-zero test, or DEFAULT if
530 none of the tests are non-zero expressions.
532 This is currently not valid for instruction patterns and is
533 supported only for insn attributes. *Note Insn Attributes::.
535 \x1f
536 File: gcc.info, Node: Bit Fields, Next: Conversions, Prev: Comparisons, Up: RTL
538 Bit Fields
539 ==========
541 Special expression codes exist to represent bitfield instructions.
542 These types of expressions are lvalues in RTL; they may appear on the
543 left side of an assignment, indicating insertion of a value into the
544 specified bit field.
546 `(sign_extract:M LOC SIZE POS)'
547 This represents a reference to a sign-extended bit field contained
548 or starting in LOC (a memory or register reference). The bit field
549 is SIZE bits wide and starts at bit POS. The compilation option
550 `BITS_BIG_ENDIAN' says which end of the memory unit POS counts
551 from.
553 If LOC is in memory, its mode must be a single-byte integer mode.
554 If LOC is in a register, the mode to use is specified by the
555 operand of the `insv' or `extv' pattern (*note Standard Names::.)
556 and is usually a full-word integer mode, which is the default if
557 none is specified.
559 The mode of POS is machine-specific and is also specified in the
560 `insv' or `extv' pattern.
562 The mode M is the same as the mode that would be used for LOC if
563 it were a register.
565 `(zero_extract:M LOC SIZE POS)'
566 Like `sign_extract' but refers to an unsigned or zero-extended bit
567 field. The same sequence of bits are extracted, but they are
568 filled to an entire word with zeros instead of by sign-extension.
570 \x1f
571 File: gcc.info, Node: Conversions, Next: RTL Declarations, Prev: Bit Fields, Up: RTL
573 Conversions
574 ===========
576 All conversions between machine modes must be represented by
577 explicit conversion operations. For example, an expression which is
578 the sum of a byte and a full word cannot be written as `(plus:SI
579 (reg:QI 34) (reg:SI 80))' because the `plus' operation requires two
580 operands of the same machine mode. Therefore, the byte-sized operand
581 is enclosed in a conversion operation, as in
583 (plus:SI (sign_extend:SI (reg:QI 34)) (reg:SI 80))
585 The conversion operation is not a mere placeholder, because there
586 may be more than one way of converting from a given starting mode to
587 the desired final mode. The conversion operation code says how to do
588 it.
590 For all conversion operations, X must not be `VOIDmode' because the
591 mode in which to do the conversion would not be known. The conversion
592 must either be done at compile-time or X must be placed into a register.
594 `(sign_extend:M X)'
595 Represents the result of sign-extending the value X to machine
596 mode M. M must be a fixed-point mode and X a fixed-point value of
597 a mode narrower than M.
599 `(zero_extend:M X)'
600 Represents the result of zero-extending the value X to machine
601 mode M. M must be a fixed-point mode and X a fixed-point value of
602 a mode narrower than M.
604 `(float_extend:M X)'
605 Represents the result of extending the value X to machine mode M.
606 M must be a floating point mode and X a floating point value of a
607 mode narrower than M.
609 `(truncate:M X)'
610 Represents the result of truncating the value X to machine mode M.
611 M must be a fixed-point mode and X a fixed-point value of a mode
612 wider than M.
614 `(float_truncate:M X)'
615 Represents the result of truncating the value X to machine mode M.
616 M must be a floating point mode and X a floating point value of a
617 mode wider than M.
619 `(float:M X)'
620 Represents the result of converting fixed point value X, regarded
621 as signed, to floating point mode M.
623 `(unsigned_float:M X)'
624 Represents the result of converting fixed point value X, regarded
625 as unsigned, to floating point mode M.
627 `(fix:M X)'
628 When M is a fixed point mode, represents the result of converting
629 floating point value X to mode M, regarded as signed. How
630 rounding is done is not specified, so this operation may be used
631 validly in compiling C code only for integer-valued operands.
633 `(unsigned_fix:M X)'
634 Represents the result of converting floating point value X to
635 fixed point mode M, regarded as unsigned. How rounding is done is
636 not specified.
638 `(fix:M X)'
639 When M is a floating point mode, represents the result of
640 converting floating point value X (valid for mode M) to an
641 integer, still represented in floating point mode M, by rounding
642 towards zero.
644 \x1f
645 File: gcc.info, Node: RTL Declarations, Next: Side Effects, Prev: Conversions, Up: RTL
647 Declarations
648 ============
650 Declaration expression codes do not represent arithmetic operations
651 but rather state assertions about their operands.
653 `(strict_low_part (subreg:M (reg:N R) 0))'
654 This expression code is used in only one context: as the
655 destination operand of a `set' expression. In addition, the
656 operand of this expression must be a non-paradoxical `subreg'
657 expression.
659 The presence of `strict_low_part' says that the part of the
660 register which is meaningful in mode N, but is not part of mode M,
661 is not to be altered. Normally, an assignment to such a subreg is
662 allowed to have undefined effects on the rest of the register when
663 M is less than a word.
665 \x1f
666 File: gcc.info, Node: Side Effects, Next: Incdec, Prev: RTL Declarations, Up: RTL
668 Side Effect Expressions
669 =======================
671 The expression codes described so far represent values, not actions.
672 But machine instructions never produce values; they are meaningful only
673 for their side effects on the state of the machine. Special expression
674 codes are used to represent side effects.
676 The body of an instruction is always one of these side effect codes;
677 the codes described above, which represent values, appear only as the
678 operands of these.
680 `(set LVAL X)'
681 Represents the action of storing the value of X into the place
682 represented by LVAL. LVAL must be an expression representing a
683 place that can be stored in: `reg' (or `subreg' or
684 `strict_low_part'), `mem', `pc' or `cc0'.
686 If LVAL is a `reg', `subreg' or `mem', it has a machine mode; then
687 X must be valid for that mode.
689 If LVAL is a `reg' whose machine mode is less than the full width
690 of the register, then it means that the part of the register
691 specified by the machine mode is given the specified value and the
692 rest of the register receives an undefined value. Likewise, if
693 LVAL is a `subreg' whose machine mode is narrower than the mode of
694 the register, the rest of the register can be changed in an
695 undefined way.
697 If LVAL is a `strict_low_part' of a `subreg', then the part of the
698 register specified by the machine mode of the `subreg' is given
699 the value X and the rest of the register is not changed.
701 If LVAL is `(cc0)', it has no machine mode, and X may be either a
702 `compare' expression or a value that may have any mode. The
703 latter case represents a "test" instruction. The expression `(set
704 (cc0) (reg:M N))' is equivalent to `(set (cc0) (compare (reg:M N)
705 (const_int 0)))'. Use the former expression to save space during
706 the compilation.
708 If LVAL is `(pc)', we have a jump instruction, and the
709 possibilities for X are very limited. It may be a `label_ref'
710 expression (unconditional jump). It may be an `if_then_else'
711 (conditional jump), in which case either the second or the third
712 operand must be `(pc)' (for the case which does not jump) and the
713 other of the two must be a `label_ref' (for the case which does
714 jump). X may also be a `mem' or `(plus:SI (pc) Y)', where Y may
715 be a `reg' or a `mem'; these unusual patterns are used to
716 represent jumps through branch tables.
718 If LVAL is neither `(cc0)' nor `(pc)', the mode of LVAL must not
719 be `VOIDmode' and the mode of X must be valid for the mode of LVAL.
721 LVAL is customarily accessed with the `SET_DEST' macro and X with
722 the `SET_SRC' macro.
724 `(return)'
725 As the sole expression in a pattern, represents a return from the
726 current function, on machines where this can be done with one
727 instruction, such as Vaxes. On machines where a multi-instruction
728 "epilogue" must be executed in order to return from the function,
729 returning is done by jumping to a label which precedes the
730 epilogue, and the `return' expression code is never used.
732 Inside an `if_then_else' expression, represents the value to be
733 placed in `pc' to return to the caller.
735 Note that an insn pattern of `(return)' is logically equivalent to
736 `(set (pc) (return))', but the latter form is never used.
738 `(call FUNCTION NARGS)'
739 Represents a function call. FUNCTION is a `mem' expression whose
740 address is the address of the function to be called. NARGS is an
741 expression which can be used for two purposes: on some machines it
742 represents the number of bytes of stack argument; on others, it
743 represents the number of argument registers.
745 Each machine has a standard machine mode which FUNCTION must have.
746 The machine description defines macro `FUNCTION_MODE' to expand
747 into the requisite mode name. The purpose of this mode is to
748 specify what kind of addressing is allowed, on machines where the
749 allowed kinds of addressing depend on the machine mode being
750 addressed.
752 `(clobber X)'
753 Represents the storing or possible storing of an unpredictable,
754 undescribed value into X, which must be a `reg', `scratch' or
755 `mem' expression.
757 One place this is used is in string instructions that store
758 standard values into particular hard registers. It may not be
759 worth the trouble to describe the values that are stored, but it
760 is essential to inform the compiler that the registers will be
761 altered, lest it attempt to keep data in them across the string
762 instruction.
764 If X is `(mem:BLK (const_int 0))', it means that all memory
765 locations must be presumed clobbered.
767 Note that the machine description classifies certain hard
768 registers as "call-clobbered". All function call instructions are
769 assumed by default to clobber these registers, so there is no need
770 to use `clobber' expressions to indicate this fact. Also, each
771 function call is assumed to have the potential to alter any memory
772 location, unless the function is declared `const'.
774 If the last group of expressions in a `parallel' are each a
775 `clobber' expression whose arguments are `reg' or `match_scratch'
776 (*note RTL Template::.) expressions, the combiner phase can add
777 the appropriate `clobber' expressions to an insn it has
778 constructed when doing so will cause a pattern to be matched.
780 This feature can be used, for example, on a machine that whose
781 multiply and add instructions don't use an MQ register but which
782 has an add-accumulate instruction that does clobber the MQ
783 register. Similarly, a combined instruction might require a
784 temporary register while the constituent instructions might not.
786 When a `clobber' expression for a register appears inside a
787 `parallel' with other side effects, the register allocator
788 guarantees that the register is unoccupied both before and after
789 that insn. However, the reload phase may allocate a register used
790 for one of the inputs unless the `&' constraint is specified for
791 the selected alternative (*note Modifiers::.). You can clobber
792 either a specific hard register, a pseudo register, or a `scratch'
793 expression; in the latter two cases, GNU CC will allocate a hard
794 register that is available there for use as a temporary.
796 For instructions that require a temporary register, you should use
797 `scratch' instead of a pseudo-register because this will allow the
798 combiner phase to add the `clobber' when required. You do this by
799 coding (`clobber' (`match_scratch' ...)). If you do clobber a
800 pseudo register, use one which appears nowhere else--generate a
801 new one each time. Otherwise, you may confuse CSE.
803 There is one other known use for clobbering a pseudo register in a
804 `parallel': when one of the input operands of the insn is also
805 clobbered by the insn. In this case, using the same pseudo
806 register in the clobber and elsewhere in the insn produces the
807 expected results.
809 `(use X)'
810 Represents the use of the value of X. It indicates that the value
811 in X at this point in the program is needed, even though it may
812 not be apparent why this is so. Therefore, the compiler will not
813 attempt to delete previous instructions whose only effect is to
814 store a value in X. X must be a `reg' expression.
816 During the delayed branch scheduling phase, X may be an insn.
817 This indicates that X previously was located at this place in the
818 code and its data dependencies need to be taken into account.
819 These `use' insns will be deleted before the delayed branch
820 scheduling phase exits.
822 `(parallel [X0 X1 ...])'
823 Represents several side effects performed in parallel. The square
824 brackets stand for a vector; the operand of `parallel' is a vector
825 of expressions. X0, X1 and so on are individual side effect
826 expressions--expressions of code `set', `call', `return',
827 `clobber' or `use'.
829 "In parallel" means that first all the values used in the
830 individual side-effects are computed, and second all the actual
831 side-effects are performed. For example,
833 (parallel [(set (reg:SI 1) (mem:SI (reg:SI 1)))
834 (set (mem:SI (reg:SI 1)) (reg:SI 1))])
836 says unambiguously that the values of hard register 1 and the
837 memory location addressed by it are interchanged. In both places
838 where `(reg:SI 1)' appears as a memory address it refers to the
839 value in register 1 *before* the execution of the insn.
841 It follows that it is *incorrect* to use `parallel' and expect the
842 result of one `set' to be available for the next one. For
843 example, people sometimes attempt to represent a jump-if-zero
844 instruction this way:
846 (parallel [(set (cc0) (reg:SI 34))
847 (set (pc) (if_then_else
848 (eq (cc0) (const_int 0))
849 (label_ref ...)
850 (pc)))])
852 But this is incorrect, because it says that the jump condition
853 depends on the condition code value *before* this instruction, not
854 on the new value that is set by this instruction.
856 Peephole optimization, which takes place together with final
857 assembly code output, can produce insns whose patterns consist of
858 a `parallel' whose elements are the operands needed to output the
859 resulting assembler code--often `reg', `mem' or constant
860 expressions. This would not be well-formed RTL at any other stage
861 in compilation, but it is ok then because no further optimization
862 remains to be done. However, the definition of the macro
863 `NOTICE_UPDATE_CC', if any, must deal with such insns if you
864 define any peephole optimizations.
866 `(sequence [INSNS ...])'
867 Represents a sequence of insns. Each of the INSNS that appears in
868 the vector is suitable for appearing in the chain of insns, so it
869 must be an `insn', `jump_insn', `call_insn', `code_label',
870 `barrier' or `note'.
872 A `sequence' RTX is never placed in an actual insn during RTL
873 generation. It represents the sequence of insns that result from a
874 `define_expand' *before* those insns are passed to `emit_insn' to
875 insert them in the chain of insns. When actually inserted, the
876 individual sub-insns are separated out and the `sequence' is
877 forgotten.
879 After delay-slot scheduling is completed, an insn and all the
880 insns that reside in its delay slots are grouped together into a
881 `sequence'. The insn requiring the delay slot is the first insn
882 in the vector; subsequent insns are to be placed in the delay slot.
884 `INSN_ANNULLED_BRANCH_P' is set on an insn in a delay slot to
885 indicate that a branch insn should be used that will conditionally
886 annul the effect of the insns in the delay slots. In such a case,
887 `INSN_FROM_TARGET_P' indicates that the insn is from the target of
888 the branch and should be executed only if the branch is taken;
889 otherwise the insn should be executed only if the branch is not
890 taken. *Note Delay Slots::.
892 These expression codes appear in place of a side effect, as the body
893 of an insn, though strictly speaking they do not always describe side
894 effects as such:
896 `(asm_input S)'
897 Represents literal assembler code as described by the string S.
899 `(unspec [OPERANDS ...] INDEX)'
900 `(unspec_volatile [OPERANDS ...] INDEX)'
901 Represents a machine-specific operation on OPERANDS. INDEX
902 selects between multiple machine-specific operations.
903 `unspec_volatile' is used for volatile operations and operations
904 that may trap; `unspec' is used for other operations.
906 These codes may appear inside a `pattern' of an insn, inside a
907 `parallel', or inside an expression.
909 `(addr_vec:M [LR0 LR1 ...])'
910 Represents a table of jump addresses. The vector elements LR0,
911 etc., are `label_ref' expressions. The mode M specifies how much
912 space is given to each address; normally M would be `Pmode'.
914 `(addr_diff_vec:M BASE [LR0 LR1 ...])'
915 Represents a table of jump addresses expressed as offsets from
916 BASE. The vector elements LR0, etc., are `label_ref' expressions
917 and so is BASE. The mode M specifies how much space is given to
918 each address-difference.
920 \x1f
921 File: gcc.info, Node: Incdec, Next: Assembler, Prev: Side Effects, Up: RTL
923 Embedded Side-Effects on Addresses
924 ==================================
926 Four special side-effect expression codes appear as memory addresses.
928 `(pre_dec:M X)'
929 Represents the side effect of decrementing X by a standard amount
930 and represents also the value that X has after being decremented.
931 X must be a `reg' or `mem', but most machines allow only a `reg'.
932 M must be the machine mode for pointers on the machine in use.
933 The amount X is decremented by is the length in bytes of the
934 machine mode of the containing memory reference of which this
935 expression serves as the address. Here is an example of its use:
937 (mem:DF (pre_dec:SI (reg:SI 39)))
939 This says to decrement pseudo register 39 by the length of a
940 `DFmode' value and use the result to address a `DFmode' value.
942 `(pre_inc:M X)'
943 Similar, but specifies incrementing X instead of decrementing it.
945 `(post_dec:M X)'
946 Represents the same side effect as `pre_dec' but a different
947 value. The value represented here is the value X has before being
948 decremented.
950 `(post_inc:M X)'
951 Similar, but specifies incrementing X instead of decrementing it.
953 These embedded side effect expressions must be used with care.
954 Instruction patterns may not use them. Until the `flow' pass of the
955 compiler, they may occur only to represent pushes onto the stack. The
956 `flow' pass finds cases where registers are incremented or decremented
957 in one instruction and used as an address shortly before or after;
958 these cases are then transformed to use pre- or post-increment or
959 -decrement.
961 If a register used as the operand of these expressions is used in
962 another address in an insn, the original value of the register is used.
963 Uses of the register outside of an address are not permitted within the
964 same insn as a use in an embedded side effect expression because such
965 insns behave differently on different machines and hence must be treated
966 as ambiguous and disallowed.
968 An instruction that can be represented with an embedded side effect
969 could also be represented using `parallel' containing an additional
970 `set' to describe how the address register is altered. This is not
971 done because machines that allow these operations at all typically
972 allow them wherever a memory address is called for. Describing them as
973 additional parallel stores would require doubling the number of entries
974 in the machine description.
976 \x1f
977 File: gcc.info, Node: Assembler, Next: Insns, Prev: Incdec, Up: RTL
979 Assembler Instructions as Expressions
980 =====================================
982 The RTX code `asm_operands' represents a value produced by a
983 user-specified assembler instruction. It is used to represent an `asm'
984 statement with arguments. An `asm' statement with a single output
985 operand, like this:
987 asm ("foo %1,%2,%0" : "=a" (outputvar) : "g" (x + y), "di" (*z));
989 is represented using a single `asm_operands' RTX which represents the
990 value that is stored in `outputvar':
992 (set RTX-FOR-OUTPUTVAR
993 (asm_operands "foo %1,%2,%0" "a" 0
994 [RTX-FOR-ADDITION-RESULT RTX-FOR-*Z]
995 [(asm_input:M1 "g")
996 (asm_input:M2 "di")]))
998 Here the operands of the `asm_operands' RTX are the assembler template
999 string, the output-operand's constraint, the index-number of the output
1000 operand among the output operands specified, a vector of input operand
1001 RTX's, and a vector of input-operand modes and constraints. The mode
1002 M1 is the mode of the sum `x+y'; M2 is that of `*z'.
1004 When an `asm' statement has multiple output values, its insn has
1005 several such `set' RTX's inside of a `parallel'. Each `set' contains a
1006 `asm_operands'; all of these share the same assembler template and
1007 vectors, but each contains the constraint for the respective output
1008 operand. They are also distinguished by the output-operand index
1009 number, which is 0, 1, ... for successive output operands.