1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-flags.h"
40 #include "insn-attr.h"
41 #include "insn-codes.h"
45 #undef MAX /* sys/param.h may also define these */
49 #include <sys/types.h>
62 #if defined(USG) || defined(NO_STAB_H)
63 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
65 #include <stab.h> /* On BSD, use the system's stab.h. */
69 #define STAB_CODE_TYPE enum __stab_debug_code
71 #define STAB_CODE_TYPE int
76 extern char *getenv ();
77 extern char *mktemp ();
79 extern rtx
adj_offsettable_operand ();
80 extern rtx
copy_to_reg ();
83 extern tree
lookup_name ();
84 extern void pfatal_with_name ();
85 extern void warning ();
87 extern FILE *asm_out_file
;
89 /* Enumeration for all of the relational tests, so that we can build
90 arrays indexed by the test type, and not worry about the order
107 /* Global variables for machine-dependent things. */
109 /* Threshold for data being put into the small data/bss area, instead
110 of the normal data area (references to the small data/bss area take
111 1 instruction, and use the global pointer, references to the normal
112 data area takes 2 instructions). */
113 int mips_section_threshold
= -1;
115 /* Count the number of .file directives, so that .loc is up to date. */
116 int num_source_filenames
= 0;
118 /* Count the number of sdb related labels are generated (to find block
119 start and end boundaries). */
120 int sdb_label_count
= 0;
122 /* Next label # for each statement for Silicon Graphics IRIS systems. */
125 /* Non-zero if inside of a function, because the stupid MIPS asm can't
126 handle .files inside of functions. */
127 int inside_function
= 0;
129 /* Files to separate the text and the data output, so that all of the data
130 can be emitted before the text, which will mean that the assembler will
131 generate smaller code, based on the global pointer. */
132 FILE *asm_out_data_file
;
133 FILE *asm_out_text_file
;
135 /* Linked list of all externals that are to be emitted when optimizing
136 for the global pointer if they haven't been declared by the end of
137 the program with an appropriate .comm or initialization. */
140 struct extern_list
*next
; /* next external */
141 char *name
; /* name of the external */
142 int size
; /* size in bytes */
145 /* Name of the file containing the current function. */
146 char *current_function_file
= "";
148 /* Warning given that Mips ECOFF can't support changing files
149 within a function. */
150 int file_in_function_warning
= FALSE
;
152 /* Whether to suppress issuing .loc's because the user attempted
153 to change the filename within a function. */
154 int ignore_line_number
= FALSE
;
156 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
162 /* The next branch instruction is a branch likely, not branch normal. */
163 int mips_branch_likely
;
165 /* Count of delay slots and how many are filled. */
166 int dslots_load_total
;
167 int dslots_load_filled
;
168 int dslots_jump_total
;
169 int dslots_jump_filled
;
171 /* # of nops needed by previous insn */
172 int dslots_number_nops
;
174 /* Number of 1/2/3 word references to data items (ie, not jal's). */
177 /* registers to check for load delay */
178 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
180 /* Cached operands, and operator to compare for use in set/branch on
184 /* what type of branch to use */
185 enum cmp_type branch_type
;
187 /* Number of previously seen half-pic pointers and references. */
188 static int prev_half_pic_ptrs
= 0;
189 static int prev_half_pic_refs
= 0;
191 /* which cpu are we scheduling for */
192 enum processor_type mips_cpu
;
194 /* which instruction set architecture to use. */
197 #ifdef MIPS_ABI_DEFAULT
198 /* which ABI to use. This is defined to a constant in mips.h if the target
199 doesn't support multiple ABIs. */
200 enum mips_abi_type mips_abi
;
203 /* Strings to hold which cpu and instruction set architecture to use. */
204 char *mips_cpu_string
; /* for -mcpu=<xxx> */
205 char *mips_isa_string
; /* for -mips{1,2,3,4} */
206 char *mips_abi_string
; /* for -mabi={o32,32,n32,n64,64,eabi} */
208 /* If TRUE, we split addresses into their high and low parts in the RTL. */
209 int mips_split_addresses
;
211 /* Generating calls to position independent functions? */
212 enum mips_abicalls_type mips_abicalls
;
214 /* High and low marks for floating point values which we will accept
215 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
216 initialized in override_options. */
217 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
219 /* Array giving truth value on whether or not a given hard register
220 can support a given mode. */
221 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
223 /* Current frame information calculated by compute_frame_size. */
224 struct mips_frame_info current_frame_info
;
226 /* Zero structure to initialize current_frame_info. */
227 struct mips_frame_info zero_frame_info
;
229 /* Temporary filename used to buffer .text until end of program
231 static char *temp_filename
;
233 /* Pseudo-reg holding the address of the current function when
234 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
235 by mips_finalize_pic if it was created. */
236 rtx embedded_pic_fnaddr_rtx
;
238 /* List of all MIPS punctuation characters used by print_operand. */
239 char mips_print_operand_punct
[256];
241 /* Map GCC register number to debugger register number. */
242 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
244 /* Buffer to use to enclose a load/store operation with %{ %} to
245 turn on .set volatile. */
246 static char volatile_buffer
[60];
248 /* Hardware names for the registers. If -mrnames is used, this
249 will be overwritten with mips_sw_reg_names. */
251 char mips_reg_names
[][8] =
253 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
254 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
255 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
256 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
257 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
258 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
259 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
260 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
261 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
262 "$fcc5","$fcc6","$fcc7","$rap"
265 /* Mips software names for the registers, used to overwrite the
266 mips_reg_names array. */
268 char mips_sw_reg_names
[][8] =
270 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
271 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
272 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
273 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
274 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
275 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
276 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
277 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
278 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
279 "$fcc5","$fcc6","$fcc7","$rap"
282 /* Map hard register number to register class */
283 enum reg_class mips_regno_to_class
[] =
285 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
286 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
287 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
288 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
289 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
290 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
291 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
292 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
293 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
294 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
295 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
296 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
297 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
298 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
299 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
300 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
301 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
302 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
303 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
306 /* Map register constraint character to register class. */
307 enum reg_class mips_char_to_class
[256] =
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
358 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
359 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
360 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
361 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
362 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
363 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
364 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
365 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
366 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
367 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
368 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
369 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
370 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
371 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
372 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
376 /* Return truth value of whether OP can be used as an operands
377 where a register or 16 bit unsigned integer is needed. */
380 uns_arith_operand (op
, mode
)
382 enum machine_mode mode
;
384 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
387 return register_operand (op
, mode
);
390 /* Return truth value of whether OP can be used as an operands
391 where a 16 bit integer is needed */
394 arith_operand (op
, mode
)
396 enum machine_mode mode
;
398 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
401 return register_operand (op
, mode
);
404 /* Return truth value of whether OP can be used as an operand in a two
405 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
408 arith32_operand (op
, mode
)
410 enum machine_mode mode
;
412 if (GET_CODE (op
) == CONST_INT
)
415 return register_operand (op
, mode
);
418 /* Return truth value of whether OP is a integer which fits in 16 bits */
423 enum machine_mode mode
;
425 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
428 /* Return truth value of whether OP is a 32 bit integer which is too big to
429 be loaded with one instruction. */
434 enum machine_mode mode
;
438 if (GET_CODE (op
) != CONST_INT
)
442 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
445 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
448 if ((value
& 0x0000ffff) == 0) /* lui reg,value>>16 */
454 /* Return truth value of whether OP is a register or the constant 0. */
457 reg_or_0_operand (op
, mode
)
459 enum machine_mode mode
;
461 switch (GET_CODE (op
))
467 return (INTVAL (op
) == 0);
470 if (op
!= CONST0_RTX (mode
))
477 return register_operand (op
, mode
);
483 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
486 mips_const_double_ok (op
, mode
)
488 enum machine_mode mode
;
492 if (GET_CODE (op
) != CONST_DOUBLE
)
495 if (mode
== VOIDmode
)
498 if (mode
!= SFmode
&& mode
!= DFmode
)
501 if (op
== CONST0_RTX (mode
))
504 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
505 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
508 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
510 if (REAL_VALUE_ISNAN (d
))
513 if (REAL_VALUE_NEGATIVE (d
))
514 d
= REAL_VALUE_NEGATE (d
);
518 if (REAL_VALUES_LESS (d
, dfhigh
)
519 && REAL_VALUES_LESS (dflow
, d
))
524 if (REAL_VALUES_LESS (d
, sfhigh
)
525 && REAL_VALUES_LESS (sflow
, d
))
532 /* Accept the floating point constant 1 in the appropriate mode. */
535 const_float_1_operand (op
, mode
)
537 enum machine_mode mode
;
540 static REAL_VALUE_TYPE onedf
;
541 static REAL_VALUE_TYPE onesf
;
542 static int one_initialized
;
544 if (GET_CODE (op
) != CONST_DOUBLE
545 || mode
!= GET_MODE (op
)
546 || (mode
!= DFmode
&& mode
!= SFmode
))
549 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
551 /* We only initialize these values if we need them, since we will
552 never get called unless mips_isa >= 4. */
553 if (! one_initialized
)
555 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
556 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
557 one_initialized
= TRUE
;
561 return REAL_VALUES_EQUAL (d
, onedf
);
563 return REAL_VALUES_EQUAL (d
, onesf
);
566 /* Return truth value if a memory operand fits in a single instruction
567 (ie, register + small offset). */
570 simple_memory_operand (op
, mode
)
572 enum machine_mode mode
;
574 rtx addr
, plus0
, plus1
;
576 /* Eliminate non-memory operations */
577 if (GET_CODE (op
) != MEM
)
580 /* dword operations really put out 2 instructions, so eliminate them. */
581 /* ??? This isn't strictly correct. It is OK to accept multiword modes
582 here, since the length attributes are being set correctly, but only
583 if the address is offsettable. LO_SUM is not offsettable. */
584 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
587 /* Decode the address now. */
589 switch (GET_CODE (addr
))
599 return SMALL_INT (op
);
602 plus0
= XEXP (addr
, 0);
603 plus1
= XEXP (addr
, 1);
604 if (GET_CODE (plus0
) == REG
605 && GET_CODE (plus1
) == CONST_INT
606 && SMALL_INT (plus1
))
609 else if (GET_CODE (plus1
) == REG
610 && GET_CODE (plus0
) == CONST_INT
611 && SMALL_INT (plus0
))
618 /* We used to allow small symbol refs here (ie, stuff in .sdata
619 or .sbss), but this causes some bugs in G++. Also, it won't
620 interfere if the MIPS linker rewrites the store instruction
621 because the function is PIC. */
623 case LABEL_REF
: /* never gp relative */
627 /* If -G 0, we can never have a GP relative memory operation.
628 Also, save some time if not optimizing. */
633 rtx offset
= const0_rtx
;
634 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
635 if (GET_CODE (op
) != SYMBOL_REF
)
638 /* let's be paranoid.... */
639 if (! SMALL_INT (offset
))
645 return SYMBOL_REF_FLAG (addr
);
652 /* Return true if the code of this rtx pattern is EQ or NE. */
655 equality_op (op
, mode
)
657 enum machine_mode mode
;
659 if (mode
!= GET_MODE (op
))
662 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
665 /* Return true if the code is a relational operations (EQ, LE, etc.) */
670 enum machine_mode mode
;
672 if (mode
!= GET_MODE (op
))
675 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
678 /* Return true if the operand is either the PC or a label_ref. */
681 pc_or_label_operand (op
, mode
)
683 enum machine_mode mode
;
688 if (GET_CODE (op
) == LABEL_REF
)
694 /* Test for a valid operand for a call instruction.
695 Don't allow the arg pointer register or virtual regs
696 since they may change into reg + const, which the patterns
700 call_insn_operand (op
, mode
)
702 enum machine_mode mode
;
704 if (CONSTANT_ADDRESS_P (op
)
705 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
706 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
707 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
712 /* Return true if OPERAND is valid as a source operand for a move
716 move_operand (op
, mode
)
718 enum machine_mode mode
;
720 /* Accept any general operand after reload has started; doing so
721 avoids losing if reload does an in-place replacement of a register
722 with a SYMBOL_REF or CONST. */
723 return (general_operand (op
, mode
)
724 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
725 || reload_in_progress
726 || reload_completed
));
731 /* Return true if OPERAND is valid as a source operand for movdi.
732 This accepts not only general_operand, but also sign extended
733 constants and registers. We need to accept sign extended constants
734 in case a sign extended register which is used in an expression,
735 and is equivalent to a constant, is spilled. */
738 movdi_operand (op
, mode
)
740 enum machine_mode mode
;
744 && GET_CODE (op
) == SIGN_EXTEND
745 && GET_MODE (op
) == DImode
746 && (GET_MODE (XEXP (op
, 0)) == SImode
747 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
748 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
749 && (register_operand (XEXP (op
, 0), SImode
)
750 || immediate_operand (XEXP (op
, 0), SImode
)))
753 return general_operand (op
, mode
);
756 /* Like register_operand, but when in 64 bit mode also accept a sign
757 extend of a 32 bit register, since the value is known to be already
761 se_register_operand (op
, mode
)
763 enum machine_mode mode
;
767 && GET_CODE (op
) == SIGN_EXTEND
768 && GET_MODE (op
) == DImode
769 && GET_MODE (XEXP (op
, 0)) == SImode
770 && register_operand (XEXP (op
, 0), SImode
))
773 return register_operand (op
, mode
);
776 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
777 extend of a 32 bit register, since the value is known to be already
781 se_reg_or_0_operand (op
, mode
)
783 enum machine_mode mode
;
787 && GET_CODE (op
) == SIGN_EXTEND
788 && GET_MODE (op
) == DImode
789 && GET_MODE (XEXP (op
, 0)) == SImode
790 && register_operand (XEXP (op
, 0), SImode
))
793 return reg_or_0_operand (op
, mode
);
796 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
797 extend of a 32 bit register, since the value is known to be already
801 se_uns_arith_operand (op
, mode
)
803 enum machine_mode mode
;
807 && GET_CODE (op
) == SIGN_EXTEND
808 && GET_MODE (op
) == DImode
809 && GET_MODE (XEXP (op
, 0)) == SImode
810 && register_operand (XEXP (op
, 0), SImode
))
813 return uns_arith_operand (op
, mode
);
816 /* Like arith_operand, but when in 64 bit mode also accept a sign
817 extend of a 32 bit register, since the value is known to be already
821 se_arith_operand (op
, mode
)
823 enum machine_mode mode
;
827 && GET_CODE (op
) == SIGN_EXTEND
828 && GET_MODE (op
) == DImode
829 && GET_MODE (XEXP (op
, 0)) == SImode
830 && register_operand (XEXP (op
, 0), SImode
))
833 return arith_operand (op
, mode
);
836 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
837 extend of a 32 bit register, since the value is known to be already
841 se_nonmemory_operand (op
, mode
)
843 enum machine_mode mode
;
847 && GET_CODE (op
) == SIGN_EXTEND
848 && GET_MODE (op
) == DImode
849 && GET_MODE (XEXP (op
, 0)) == SImode
850 && register_operand (XEXP (op
, 0), SImode
))
853 return nonmemory_operand (op
, mode
);
856 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
857 sign extend of a 32 bit register, since the value is known to be
858 already sign extended. */
861 se_nonimmediate_operand (op
, mode
)
863 enum machine_mode mode
;
867 && GET_CODE (op
) == SIGN_EXTEND
868 && GET_MODE (op
) == DImode
869 && GET_MODE (XEXP (op
, 0)) == SImode
870 && register_operand (XEXP (op
, 0), SImode
))
873 return nonimmediate_operand (op
, mode
);
876 /* Return true if we split the address into high and low parts. */
878 /* ??? We should also handle reg+array somewhere. We get four
879 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
880 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
881 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
882 out of the address, then we have 4 instructions to combine. Perhaps
883 add a 3->2 define_split for combine. */
885 /* ??? We could also split a CONST_INT here if it is a large_int().
886 However, it doesn't seem to be very useful to have %hi(constant).
887 We would be better off by doing the masking ourselves and then putting
888 the explicit high part of the constant in the RTL. This will give better
889 optimization. Also, %hi(constant) needs assembler changes to work.
890 There is already a define_split that does this. */
893 mips_check_split (address
, mode
)
895 enum machine_mode mode
;
897 /* ??? This is the same check used in simple_memory_operand.
898 We use it here because LO_SUM is not offsettable. */
899 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
902 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
903 || (GET_CODE (address
) == CONST
904 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
905 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
906 || GET_CODE (address
) == LABEL_REF
)
912 /* Returns an operand string for the given instruction's delay slot,
913 after updating filled delay slot statistics.
915 We assume that operands[0] is the target register that is set.
917 In order to check the next insn, most of this functionality is moved
918 to FINAL_PRESCAN_INSN, and we just set the global variables that
921 /* ??? This function no longer does anything useful, because final_prescan_insn
922 now will never emit a nop. */
925 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
926 char *ret
; /* normal string to return */
927 enum delay_type type
; /* type of delay */
928 rtx operands
[]; /* operands to use */
929 rtx cur_insn
; /* current insn */
931 register rtx set_reg
;
932 register enum machine_mode mode
;
933 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
934 register int num_nops
;
936 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
939 else if (type
== DELAY_HILO
)
945 /* Make sure that we don't put nop's after labels. */
946 next_insn
= NEXT_INSN (cur_insn
);
947 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
948 next_insn
= NEXT_INSN (next_insn
);
950 dslots_load_total
+= num_nops
;
951 if (TARGET_DEBUG_F_MODE
953 || type
== DELAY_NONE
954 || operands
== (rtx
*)0
955 || cur_insn
== (rtx
)0
956 || next_insn
== (rtx
)0
957 || GET_CODE (next_insn
) == CODE_LABEL
958 || (set_reg
= operands
[0]) == (rtx
)0)
960 dslots_number_nops
= 0;
961 mips_load_reg
= (rtx
)0;
962 mips_load_reg2
= (rtx
)0;
963 mips_load_reg3
= (rtx
)0;
964 mips_load_reg4
= (rtx
)0;
968 set_reg
= operands
[0];
969 if (set_reg
== (rtx
)0)
972 while (GET_CODE (set_reg
) == SUBREG
)
973 set_reg
= SUBREG_REG (set_reg
);
975 mode
= GET_MODE (set_reg
);
976 dslots_number_nops
= num_nops
;
977 mips_load_reg
= set_reg
;
978 if (GET_MODE_SIZE (mode
)
979 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
980 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
984 if (type
== DELAY_HILO
)
986 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
987 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
999 /* Determine whether a memory reference takes one (based off of the GP pointer),
1000 two (normal), or three (label + reg) instructions, and bump the appropriate
1001 counter for -mstats. */
1004 mips_count_memory_refs (op
, num
)
1010 rtx addr
, plus0
, plus1
;
1011 enum rtx_code code0
, code1
;
1014 if (TARGET_DEBUG_B_MODE
)
1016 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1020 /* Skip MEM if passed, otherwise handle movsi of address. */
1021 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1023 /* Loop, going through the address RTL */
1027 switch (GET_CODE (addr
))
1038 plus0
= XEXP (addr
, 0);
1039 plus1
= XEXP (addr
, 1);
1040 code0
= GET_CODE (plus0
);
1041 code1
= GET_CODE (plus1
);
1051 if (code0
== CONST_INT
)
1066 if (code1
== CONST_INT
)
1073 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1080 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1090 n_words
= 2; /* always 2 words */
1094 addr
= XEXP (addr
, 0);
1099 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1108 n_words
+= additional
;
1112 num_refs
[n_words
-1] += num
;
1116 /* Return RTL for the offset from the current function to the
1120 embedded_pic_offset (x
)
1123 if (embedded_pic_fnaddr_rtx
== NULL
)
1127 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1129 /* Output code at function start to initialize the pseudo-reg. */
1130 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1131 inline functions, because it is called after RTL for the function
1132 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1133 does not get copied, and ends up not matching the rest of the RTL.
1134 This solution works, but means that we get unnecessary code to
1135 initialize this value every time a function is inlined into another
1138 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
1139 XEXP (DECL_RTL (current_function_decl
), 0)));
1140 seq
= gen_sequence ();
1142 push_topmost_sequence ();
1143 emit_insn_after (seq
, get_insns ());
1144 pop_topmost_sequence ();
1147 return gen_rtx (CONST
, Pmode
,
1148 gen_rtx (MINUS
, Pmode
, x
,
1149 XEXP (DECL_RTL (current_function_decl
), 0)));
1152 /* Return the appropriate instructions to move one operand to another. */
1155 mips_move_1word (operands
, insn
, unsignedp
)
1161 rtx op0
= operands
[0];
1162 rtx op1
= operands
[1];
1163 enum rtx_code code0
= GET_CODE (op0
);
1164 enum rtx_code code1
= GET_CODE (op1
);
1165 enum machine_mode mode
= GET_MODE (op0
);
1166 int subreg_word0
= 0;
1167 int subreg_word1
= 0;
1168 enum delay_type delay
= DELAY_NONE
;
1170 while (code0
== SUBREG
)
1172 subreg_word0
+= SUBREG_WORD (op0
);
1173 op0
= SUBREG_REG (op0
);
1174 code0
= GET_CODE (op0
);
1177 while (code1
== SUBREG
)
1179 subreg_word1
+= SUBREG_WORD (op1
);
1180 op1
= SUBREG_REG (op1
);
1181 code1
= GET_CODE (op1
);
1184 /* For our purposes, a condition code mode is the same as SImode. */
1190 int regno0
= REGNO (op0
) + subreg_word0
;
1194 int regno1
= REGNO (op1
) + subreg_word1
;
1196 /* Just in case, don't do anything for assigning a register
1197 to itself, unless we are filling a delay slot. */
1198 if (regno0
== regno1
&& set_nomacro
== 0)
1201 else if (GP_REG_P (regno0
))
1203 if (GP_REG_P (regno1
))
1204 ret
= "move\t%0,%1";
1206 else if (MD_REG_P (regno1
))
1209 if (regno1
!= HILO_REGNUM
)
1215 else if (ST_REG_P (regno1
) && mips_isa
>= 4)
1216 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
1221 if (FP_REG_P (regno1
))
1222 ret
= "mfc1\t%0,%1";
1224 else if (regno1
== FPSW_REGNUM
&& mips_isa
< 4)
1225 ret
= "cfc1\t%0,$31";
1229 else if (FP_REG_P (regno0
))
1231 if (GP_REG_P (regno1
))
1234 ret
= "mtc1\t%1,%0";
1237 if (FP_REG_P (regno1
))
1238 ret
= "mov.s\t%0,%1";
1241 else if (MD_REG_P (regno0
))
1243 if (GP_REG_P (regno1
))
1246 if (regno0
!= HILO_REGNUM
)
1251 else if (regno0
== FPSW_REGNUM
&& mips_isa
< 4)
1253 if (GP_REG_P (regno1
))
1256 ret
= "ctc1\t%0,$31";
1261 else if (code1
== MEM
)
1266 mips_count_memory_refs (op1
, 1);
1268 if (GP_REG_P (regno0
))
1270 /* For loads, use the mode of the memory item, instead of the
1271 target, so zero/sign extend can use this code as well. */
1272 switch (GET_MODE (op1
))
1281 ret
= ((unsignedp
&& TARGET_64BIT
)
1286 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1289 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1294 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1297 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1299 int i
= strlen (ret
);
1300 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1303 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1304 ret
= volatile_buffer
;
1308 else if (code1
== CONST_INT
1309 || (code1
== CONST_DOUBLE
1310 && GET_MODE (op1
) == VOIDmode
))
1312 if (code1
== CONST_DOUBLE
)
1314 /* This can happen when storing constants into long long
1315 bitfields. Just store the least significant word of
1317 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1320 if (INTVAL (op1
) == 0)
1322 if (GP_REG_P (regno0
))
1323 ret
= "move\t%0,%z1";
1325 else if (FP_REG_P (regno0
))
1328 ret
= "mtc1\t%z1,%0";
1331 else if (MD_REG_P (regno0
))
1338 else if (GP_REG_P (regno0
))
1339 /* Don't use X format, because that will give out of range
1340 numbers for 64 bit host and 32 bit target. */
1341 ret
= "li\t%0,%1\t\t\t# %X1";
1344 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1346 if (op1
== CONST0_RTX (SFmode
))
1348 if (GP_REG_P (regno0
))
1349 ret
= "move\t%0,%.";
1351 else if (FP_REG_P (regno0
))
1354 ret
= "mtc1\t%.,%0";
1361 ret
= "li.s\t%0,%1";
1365 else if (code1
== LABEL_REF
)
1368 mips_count_memory_refs (op1
, 1);
1373 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1375 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1377 rtx offset
= const0_rtx
;
1379 if (GET_CODE (op1
) == CONST
)
1380 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1382 if (GET_CODE (op1
) == SYMBOL_REF
)
1384 operands
[2] = HALF_PIC_PTR (op1
);
1387 mips_count_memory_refs (operands
[2], 1);
1389 if (INTVAL (offset
) == 0)
1392 ret
= (unsignedp
&& TARGET_64BIT
1398 dslots_load_total
++;
1399 operands
[3] = offset
;
1400 if (unsignedp
&& TARGET_64BIT
)
1401 ret
= (SMALL_INT (offset
))
1402 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1403 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1405 ret
= (SMALL_INT (offset
))
1406 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1407 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1414 mips_count_memory_refs (op1
, 1);
1420 else if (code1
== PLUS
)
1422 rtx add_op0
= XEXP (op1
, 0);
1423 rtx add_op1
= XEXP (op1
, 1);
1425 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1427 add_op0
= XEXP (op1
, 1); /* reverse operands */
1428 add_op1
= XEXP (op1
, 0);
1431 operands
[2] = add_op0
;
1432 operands
[3] = add_op1
;
1433 ret
= "add%:\t%0,%2,%3";
1436 else if (code1
== HIGH
)
1438 operands
[1] = XEXP (op1
, 0);
1439 ret
= "lui\t%0,%%hi(%1)";
1443 else if (code0
== MEM
)
1446 mips_count_memory_refs (op0
, 1);
1450 int regno1
= REGNO (op1
) + subreg_word1
;
1452 if (GP_REG_P (regno1
))
1457 case SFmode
: ret
= "sw\t%1,%0"; break;
1458 case SImode
: ret
= "sw\t%1,%0"; break;
1459 case HImode
: ret
= "sh\t%1,%0"; break;
1460 case QImode
: ret
= "sb\t%1,%0"; break;
1464 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1468 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1473 case SFmode
: ret
= "sw\t%z1,%0"; break;
1474 case SImode
: ret
= "sw\t%z1,%0"; break;
1475 case HImode
: ret
= "sh\t%z1,%0"; break;
1476 case QImode
: ret
= "sb\t%z1,%0"; break;
1480 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1485 case SFmode
: ret
= "sw\t%.,%0"; break;
1486 case SImode
: ret
= "sw\t%.,%0"; break;
1487 case HImode
: ret
= "sh\t%.,%0"; break;
1488 case QImode
: ret
= "sb\t%.,%0"; break;
1492 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1494 int i
= strlen (ret
);
1495 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1498 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1499 ret
= volatile_buffer
;
1503 if (ret
== (char *)0)
1505 abort_with_insn (insn
, "Bad move");
1509 if (delay
!= DELAY_NONE
)
1510 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1516 /* Return the appropriate instructions to move 2 words */
1519 mips_move_2words (operands
, insn
)
1524 rtx op0
= operands
[0];
1525 rtx op1
= operands
[1];
1526 enum rtx_code code0
= GET_CODE (operands
[0]);
1527 enum rtx_code code1
= GET_CODE (operands
[1]);
1528 int subreg_word0
= 0;
1529 int subreg_word1
= 0;
1530 enum delay_type delay
= DELAY_NONE
;
1532 while (code0
== SUBREG
)
1534 subreg_word0
+= SUBREG_WORD (op0
);
1535 op0
= SUBREG_REG (op0
);
1536 code0
= GET_CODE (op0
);
1539 if (code1
== SIGN_EXTEND
)
1541 op1
= XEXP (op1
, 0);
1542 code1
= GET_CODE (op1
);
1545 while (code1
== SUBREG
)
1547 subreg_word1
+= SUBREG_WORD (op1
);
1548 op1
= SUBREG_REG (op1
);
1549 code1
= GET_CODE (op1
);
1553 if (GET_CODE (operands
[1]) == SIGN_EXTEND
1555 && code1
!= CONST_INT
1556 /* The following three can happen as the result of a questionable
1558 && code1
!= LABEL_REF
1559 && code1
!= SYMBOL_REF
1565 int regno0
= REGNO (op0
) + subreg_word0
;
1569 int regno1
= REGNO (op1
) + subreg_word1
;
1571 /* Just in case, don't do anything for assigning a register
1572 to itself, unless we are filling a delay slot. */
1573 if (regno0
== regno1
&& set_nomacro
== 0)
1576 else if (FP_REG_P (regno0
))
1578 if (FP_REG_P (regno1
))
1579 ret
= "mov.d\t%0,%1";
1587 abort_with_insn (insn
, "Bad move");
1588 #ifdef TARGET_FP_CALL_32
1589 if (FP_CALL_GP_REG_P (regno1
))
1590 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1593 ret
= "dmtc1\t%1,%0";
1596 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1600 else if (FP_REG_P (regno1
))
1606 abort_with_insn (insn
, "Bad move");
1607 #ifdef TARGET_FP_CALL_32
1608 if (FP_CALL_GP_REG_P (regno0
))
1609 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1612 ret
= "dmfc1\t%0,%1";
1615 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1618 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1623 if (regno0
!= HILO_REGNUM
)
1625 else if (regno1
== 0)
1626 ret
= "mtlo\t%.\n\tmthi\t%.";
1629 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1632 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1637 if (regno1
!= HILO_REGNUM
)
1641 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1644 else if (TARGET_64BIT
)
1645 ret
= "move\t%0,%1";
1647 else if (regno0
!= (regno1
+1))
1648 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1651 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1654 else if (code1
== CONST_DOUBLE
)
1656 /* Move zero from $0 unless !TARGET_64BIT and recipient
1657 is 64-bit fp reg, in which case generate a constant. */
1658 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1659 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1661 if (GET_MODE (op1
) == DFmode
)
1664 #ifdef TARGET_FP_CALL_32
1665 if (FP_CALL_GP_REG_P (regno0
))
1667 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1669 split_double (op1
, operands
+ 2, operands
+ 3);
1670 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1673 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1677 ret
= "li.d\t%0,%1";
1680 else if (TARGET_64BIT
)
1685 split_double (op1
, operands
+ 2, operands
+ 3);
1686 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1692 if (GP_REG_P (regno0
))
1694 #ifdef TARGET_FP_CALL_32
1695 && ! FP_CALL_GP_REG_P (regno0
)
1699 : "move\t%0,%.\n\tmove\t%D0,%.";
1701 else if (FP_REG_P (regno0
))
1704 ret
= (TARGET_64BIT
)
1706 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1711 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1713 if (GP_REG_P (regno0
))
1714 ret
= (TARGET_64BIT
)
1716 : "move\t%0,%.\n\tmove\t%D0,%.";
1718 else if (FP_REG_P (regno0
))
1721 ret
= (TARGET_64BIT
)
1725 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1727 else if (MD_REG_P (regno0
))
1730 if (regno0
!= HILO_REGNUM
)
1733 ret
= "mtlo\t%.\n\tmthi\t%.";
1737 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1741 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1742 ret
= "li\t%0,%1\t\t# %X1";
1743 else if (HOST_BITS_PER_WIDE_INT
< 64)
1744 /* We can't use 'X' for negative numbers, because then we won't
1745 get the right value for the upper 32 bits. */
1746 ret
= ((INTVAL (op1
) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1747 : "dli\t%0,%X1\t\t# %1");
1749 /* We must use 'X', because otherwise LONG_MIN will print as
1750 a number that the assembler won't accept. */
1751 ret
= "dli\t%0,%X1\t\t# %1";
1753 else if (HOST_BITS_PER_WIDE_INT
< 64)
1755 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1756 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1760 /* We use multiple shifts here, to avoid warnings about out
1761 of range shifts on 32 bit hosts. */
1762 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
1763 operands
[1] = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
1764 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1768 else if (code1
== MEM
)
1773 mips_count_memory_refs (op1
, 2);
1775 if (FP_REG_P (regno0
))
1778 else if (TARGET_64BIT
)
1780 #ifdef TARGET_FP_CALL_32
1781 if (FP_CALL_GP_REG_P (regno0
))
1783 if (offsettable_address_p (FALSE
, SImode
, op1
))
1784 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1786 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1793 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1795 operands
[2] = adj_offsettable_operand (op1
, 4);
1796 if (reg_mentioned_p (op0
, op1
))
1797 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1799 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1802 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1804 int i
= strlen (ret
);
1805 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1808 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1809 ret
= volatile_buffer
;
1813 else if (code1
== LABEL_REF
1814 || code1
== SYMBOL_REF
1818 mips_count_memory_refs (op1
, 2);
1820 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1821 /* We deliberately remove the 'a' from '%1', so that we don't
1822 have to add SIGN_EXTEND support to print_operand_address.
1823 print_operand will just call print_operand_address in this
1824 case, so there is no problem. */
1827 ret
= "dla\t%0,%a1";
1831 else if (code0
== MEM
)
1835 int regno1
= REGNO (op1
) + subreg_word1
;
1837 if (FP_REG_P (regno1
))
1840 else if (TARGET_64BIT
)
1842 #ifdef TARGET_FP_CALL_32
1843 if (FP_CALL_GP_REG_P (regno1
))
1844 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1850 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1852 operands
[2] = adj_offsettable_operand (op0
, 4);
1853 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1857 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1858 || (code1
== CONST_DOUBLE
1859 && op1
== CONST0_RTX (GET_MODE (op1
))))
1861 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1867 operands
[2] = adj_offsettable_operand (op0
, 4);
1868 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1873 mips_count_memory_refs (op0
, 2);
1875 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1877 int i
= strlen (ret
);
1878 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1881 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1882 ret
= volatile_buffer
;
1886 if (ret
== (char *)0)
1888 abort_with_insn (insn
, "Bad move");
1892 if (delay
!= DELAY_NONE
)
1893 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1899 /* Provide the costs of an addressing mode that contains ADDR.
1900 If ADDR is not a valid address, its cost is irrelevant. */
1903 mips_address_cost (addr
)
1906 switch (GET_CODE (addr
))
1919 rtx offset
= const0_rtx
;
1920 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1921 if (GET_CODE (addr
) == LABEL_REF
)
1924 if (GET_CODE (addr
) != SYMBOL_REF
)
1927 if (! SMALL_INT (offset
))
1933 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1937 register rtx plus0
= XEXP (addr
, 0);
1938 register rtx plus1
= XEXP (addr
, 1);
1940 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1942 plus0
= XEXP (addr
, 1);
1943 plus1
= XEXP (addr
, 0);
1946 if (GET_CODE (plus0
) != REG
)
1949 switch (GET_CODE (plus1
))
1955 return (SMALL_INT (plus1
) ? 1 : 2);
1962 return mips_address_cost (plus1
) + 1;
1970 /* Return true if X is an address which needs a temporary register when
1971 reloaded while generating PIC code. */
1974 pic_address_needs_scratch (x
)
1977 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1978 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1979 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1980 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1981 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1987 /* Make normal rtx_code into something we can index from an array */
1989 static enum internal_test
1990 map_test_to_internal_test (test_code
)
1991 enum rtx_code test_code
;
1993 enum internal_test test
= ITEST_MAX
;
1998 case EQ
: test
= ITEST_EQ
; break;
1999 case NE
: test
= ITEST_NE
; break;
2000 case GT
: test
= ITEST_GT
; break;
2001 case GE
: test
= ITEST_GE
; break;
2002 case LT
: test
= ITEST_LT
; break;
2003 case LE
: test
= ITEST_LE
; break;
2004 case GTU
: test
= ITEST_GTU
; break;
2005 case GEU
: test
= ITEST_GEU
; break;
2006 case LTU
: test
= ITEST_LTU
; break;
2007 case LEU
: test
= ITEST_LEU
; break;
2014 /* Generate the code to compare two integer values. The return value is:
2015 (reg:SI xx) The pseudo register the comparison is in
2016 (rtx)0 No register, generate a simple branch.
2018 ??? This is called with result nonzero by the Scond patterns in
2019 mips.md. These patterns are called with a target in the mode of
2020 the Scond instruction pattern. Since this must be a constant, we
2021 must use SImode. This means that if RESULT is non-zero, it will
2022 always be an SImode register, even if TARGET_64BIT is true. We
2023 cope with this by calling convert_move rather than emit_move_insn.
2024 This will sometimes lead to an unnecessary extension of the result;
2036 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
2037 enum rtx_code test_code
; /* relational test (EQ, etc) */
2038 rtx result
; /* result to store comp. or 0 if branch */
2039 rtx cmp0
; /* first operand to compare */
2040 rtx cmp1
; /* second operand to compare */
2041 int *p_invert
; /* NULL or ptr to hold whether branch needs */
2042 /* to reverse its test */
2045 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
2046 int const_low
; /* low bound of constant we can accept */
2047 int const_high
; /* high bound of constant we can accept */
2048 int const_add
; /* constant to add (convert LE -> LT) */
2049 int reverse_regs
; /* reverse registers in test */
2050 int invert_const
; /* != 0 if invert value if cmp1 is constant */
2051 int invert_reg
; /* != 0 if invert value if cmp1 is register */
2052 int unsignedp
; /* != 0 for unsigned comparisons. */
2055 static struct cmp_info info
[ (int)ITEST_MAX
] = {
2057 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2058 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2059 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2060 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2061 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2062 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2063 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2064 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2065 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2066 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2069 enum internal_test test
;
2070 enum machine_mode mode
;
2071 struct cmp_info
*p_info
;
2078 test
= map_test_to_internal_test (test_code
);
2079 if (test
== ITEST_MAX
)
2082 p_info
= &info
[ (int)test
];
2083 eqne_p
= (p_info
->test_code
== XOR
);
2085 mode
= GET_MODE (cmp0
);
2086 if (mode
== VOIDmode
)
2087 mode
= GET_MODE (cmp1
);
2089 /* Eliminate simple branches */
2090 branch_p
= (result
== (rtx
)0);
2093 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
2095 /* Comparisons against zero are simple branches */
2096 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2099 /* Test for beq/bne. */
2104 /* allocate a pseudo to calculate the value in. */
2105 result
= gen_reg_rtx (mode
);
2108 /* Make sure we can handle any constants given to us. */
2109 if (GET_CODE (cmp0
) == CONST_INT
)
2110 cmp0
= force_reg (mode
, cmp0
);
2112 if (GET_CODE (cmp1
) == CONST_INT
)
2114 HOST_WIDE_INT value
= INTVAL (cmp1
);
2115 if (value
< p_info
->const_low
2116 || value
> p_info
->const_high
2117 /* ??? Why? And why wasn't the similar code below modified too? */
2119 && HOST_BITS_PER_WIDE_INT
< 64
2120 && p_info
->const_add
!= 0
2121 && ((p_info
->unsignedp
2122 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
2124 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
2125 != (p_info
->const_add
> 0))))
2126 cmp1
= force_reg (mode
, cmp1
);
2129 /* See if we need to invert the result. */
2130 invert
= (GET_CODE (cmp1
) == CONST_INT
)
2131 ? p_info
->invert_const
2132 : p_info
->invert_reg
;
2134 if (p_invert
!= (int *)0)
2140 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2141 Comparison between two registers, may involve switching operands. */
2142 if (GET_CODE (cmp1
) == CONST_INT
)
2144 if (p_info
->const_add
!= 0)
2146 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
2147 /* If modification of cmp1 caused overflow,
2148 we would get the wrong answer if we follow the usual path;
2149 thus, x > 0xffffffffU would turn into x > 0U. */
2150 if ((p_info
->unsignedp
2151 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
2152 : new > INTVAL (cmp1
))
2153 != (p_info
->const_add
> 0))
2155 /* This test is always true, but if INVERT is true then
2156 the result of the test needs to be inverted so 0 should
2157 be returned instead. */
2158 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
2162 cmp1
= GEN_INT (new);
2165 else if (p_info
->reverse_regs
)
2172 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2176 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
2177 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
2180 if (test
== ITEST_NE
)
2182 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
2186 else if (test
== ITEST_EQ
)
2188 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
2189 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
2194 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
2200 /* Emit the common code for doing conditional branches.
2201 operand[0] is the label to jump to.
2202 The comparison operands are saved away by cmp{si,di,sf,df}. */
2205 gen_conditional_branch (operands
, test_code
)
2207 enum rtx_code test_code
;
2209 enum cmp_type type
= branch_type
;
2210 rtx cmp0
= branch_cmp
[0];
2211 rtx cmp1
= branch_cmp
[1];
2212 enum machine_mode mode
;
2220 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
2224 mode
= type
== CMP_SI
? SImode
: DImode
;
2226 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
2233 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2235 /* We don't want to build a comparison against a non-zero
2237 cmp1
= force_reg (mode
, cmp1
);
2244 reg
= gen_rtx (REG
, CCmode
, FPSW_REGNUM
);
2246 reg
= gen_reg_rtx (CCmode
);
2248 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2249 0 in the instruction built below. The MIPS FPU handles
2250 inequality testing by testing for equality and looking for a
2252 emit_insn (gen_rtx (SET
, VOIDmode
,
2254 gen_rtx (test_code
== NE
? EQ
: test_code
,
2255 CCmode
, cmp0
, cmp1
)));
2257 test_code
= test_code
== NE
? EQ
: NE
;
2265 /* Generate the branch. */
2267 label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
2276 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
2278 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2279 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
2284 /* Emit the common code for conditional moves. OPERANDS is the array
2285 of operands passed to the conditional move defined_expand. */
2288 gen_conditional_move (operands
)
2291 rtx op0
= branch_cmp
[0];
2292 rtx op1
= branch_cmp
[1];
2293 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
2294 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
2295 enum rtx_code move_code
= NE
;
2296 enum machine_mode op_mode
= GET_MODE (operands
[0]);
2297 enum machine_mode cmp_mode
;
2300 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
2319 op0
= force_reg (mode
, branch_cmp
[1]);
2320 op1
= branch_cmp
[0];
2324 op0
= force_reg (mode
, branch_cmp
[1]);
2325 op1
= branch_cmp
[0];
2336 op0
= force_reg (mode
, branch_cmp
[1]);
2337 op1
= branch_cmp
[0];
2341 op0
= force_reg (mode
, branch_cmp
[1]);
2342 op1
= branch_cmp
[0];
2358 if (mode
== SImode
|| mode
== DImode
)
2360 else if (mode
== SFmode
|| mode
== DFmode
)
2365 cmp_reg
= gen_reg_rtx (cmp_mode
);
2366 emit_insn (gen_rtx (SET
, cmp_mode
,
2368 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
2369 emit_insn (gen_rtx (SET
, op_mode
,
2371 gen_rtx (IF_THEN_ELSE
, op_mode
,
2372 gen_rtx (move_code
, VOIDmode
,
2374 CONST0_RTX (SImode
)),
2379 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2385 temp<last> = src[MAX_MOVE_REGS-1];
2389 dest[MAX_MOVE_REGS-1] = temp<last>;
2390 src += MAX_MOVE_REGS;
2391 dest += MAX_MOVE_REGS;
2392 } while (src != final);
2394 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2395 registers are needed.
2397 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2398 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2399 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2401 #define MAX_MOVE_REGS 4
2402 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2405 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
2406 rtx dest_reg
; /* register holding destination address */
2407 rtx src_reg
; /* register holding source address */
2408 int bytes
; /* # bytes to move */
2409 int align
; /* alignment */
2410 rtx orig_dest
; /* original dest for change_address */
2411 rtx orig_src
; /* original source for making a reg note */
2413 rtx dest_mem
= change_address (orig_dest
, BLKmode
, dest_reg
);
2414 rtx src_mem
= change_address (orig_src
, BLKmode
, src_reg
);
2415 rtx align_rtx
= GEN_INT (align
);
2421 if (bytes
< 2*MAX_MOVE_BYTES
)
2424 leftover
= bytes
% MAX_MOVE_BYTES
;
2427 label
= gen_label_rtx ();
2428 final_src
= gen_reg_rtx (Pmode
);
2429 bytes_rtx
= GEN_INT (bytes
);
2435 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2436 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2440 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2441 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2447 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2449 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2454 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2455 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2458 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2459 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2460 emit_insn (gen_cmpdi (src_reg
, final_src
));
2464 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2465 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2466 emit_insn (gen_cmpsi (src_reg
, final_src
));
2468 emit_jump_insn (gen_bne (label
));
2471 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2476 /* Use a library function to move some bytes. */
2479 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2484 /* We want to pass the size as Pmode, which will normally be SImode
2485 but will be DImode if we are using 64 bit longs and pointers. */
2486 if (GET_MODE (bytes_rtx
) != VOIDmode
2487 && GET_MODE (bytes_rtx
) != Pmode
)
2488 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2490 #ifdef TARGET_MEM_FUNCTIONS
2491 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2495 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2496 TREE_UNSIGNED (sizetype
)),
2497 TYPE_MODE (sizetype
));
2499 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2503 convert_to_mode (TYPE_MODE (integer_type_node
),
2505 TREE_UNSIGNED (integer_type_node
)),
2506 TYPE_MODE (integer_type_node
));
2511 /* Expand string/block move operations.
2513 operands[0] is the pointer to the destination.
2514 operands[1] is the pointer to the source.
2515 operands[2] is the number of bytes to move.
2516 operands[3] is the alignment. */
2519 expand_block_move (operands
)
2522 rtx bytes_rtx
= operands
[2];
2523 rtx align_rtx
= operands
[3];
2524 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2525 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2526 int align
= INTVAL (align_rtx
);
2527 rtx orig_src
= operands
[1];
2528 rtx orig_dest
= operands
[0];
2532 if (constp
&& bytes
<= 0)
2535 if (align
> UNITS_PER_WORD
)
2536 align
= UNITS_PER_WORD
;
2538 /* Move the address into scratch registers. */
2539 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2540 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2543 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2545 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2546 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2548 change_address (orig_src
, BLKmode
,
2550 bytes_rtx
, align_rtx
));
2552 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2553 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
2555 else if (constp
&& optimize
)
2557 /* If the alignment is not word aligned, generate a test at
2558 runtime, to see whether things wound up aligned, and we
2559 can use the faster lw/sw instead ulw/usw. */
2561 rtx temp
= gen_reg_rtx (Pmode
);
2562 rtx aligned_label
= gen_label_rtx ();
2563 rtx join_label
= gen_label_rtx ();
2564 int leftover
= bytes
% MAX_MOVE_BYTES
;
2570 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2571 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2572 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2576 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2577 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2578 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2580 emit_jump_insn (gen_beq (aligned_label
));
2582 /* Unaligned loop. */
2583 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
2584 emit_jump_insn (gen_jump (join_label
));
2588 emit_label (aligned_label
);
2589 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
2591 emit_label (join_label
);
2593 /* Bytes at the end of the loop. */
2595 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2597 change_address (orig_src
, BLKmode
,
2604 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2608 /* Emit load/stores for a small constant block_move.
2610 operands[0] is the memory address of the destination.
2611 operands[1] is the memory address of the source.
2612 operands[2] is the number of bytes to move.
2613 operands[3] is the alignment.
2614 operands[4] is a temp register.
2615 operands[5] is a temp register.
2617 operands[3+num_regs] is the last temp register.
2619 The block move type can be one of the following:
2620 BLOCK_MOVE_NORMAL Do all of the block move.
2621 BLOCK_MOVE_NOT_LAST Do all but the last store.
2622 BLOCK_MOVE_LAST Do just the last store. */
2625 output_block_move (insn
, operands
, num_regs
, move_type
)
2629 enum block_move_type move_type
;
2631 rtx dest_reg
= XEXP (operands
[0], 0);
2632 rtx src_reg
= XEXP (operands
[1], 0);
2633 int bytes
= INTVAL (operands
[2]);
2634 int align
= INTVAL (operands
[3]);
2637 int use_lwl_lwr
= FALSE
;
2638 int last_operand
= num_regs
+4;
2644 char *load
; /* load insn without nop */
2645 char *load_nop
; /* load insn with trailing nop */
2646 char *store
; /* store insn */
2647 char *final
; /* if last_store used: NULL or swr */
2648 char *last_store
; /* last store instruction */
2649 int offset
; /* current offset */
2650 enum machine_mode mode
; /* mode to use on (MEM) */
2653 /* Detect a bug in GCC, where it can give us a register
2654 the same as one of the addressing registers and reduce
2655 the number of registers available. */
2657 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2660 if (!reg_mentioned_p (operands
[i
], operands
[0])
2661 && !reg_mentioned_p (operands
[i
], operands
[1]))
2663 xoperands
[safe_regs
++] = operands
[i
];
2666 if (safe_regs
< last_operand
)
2668 xoperands
[0] = operands
[0];
2669 xoperands
[1] = operands
[1];
2670 xoperands
[2] = operands
[2];
2671 xoperands
[3] = operands
[3];
2672 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2675 /* If we are given global or static addresses, and we would be
2676 emitting a few instructions, try to save time by using a
2677 temporary register for the pointer. */
2678 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
2679 an ldl/ldr instruction pair. We play it safe, and always move
2680 constant addresses into registers when generating N32/N64 code, just
2681 in case we might emit an unaligned load instruction. */
2682 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
2683 || mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
2685 if (CONSTANT_P (src_reg
))
2688 mips_count_memory_refs (operands
[1], 1);
2690 src_reg
= operands
[ 3 + num_regs
-- ];
2691 if (move_type
!= BLOCK_MOVE_LAST
)
2693 xoperands
[1] = operands
[1];
2694 xoperands
[0] = src_reg
;
2695 if (Pmode
== DImode
)
2696 output_asm_insn ("dla\t%0,%1", xoperands
);
2698 output_asm_insn ("la\t%0,%1", xoperands
);
2702 if (CONSTANT_P (dest_reg
))
2705 mips_count_memory_refs (operands
[0], 1);
2707 dest_reg
= operands
[ 3 + num_regs
-- ];
2708 if (move_type
!= BLOCK_MOVE_LAST
)
2710 xoperands
[1] = operands
[0];
2711 xoperands
[0] = dest_reg
;
2712 if (Pmode
== DImode
)
2713 output_asm_insn ("dla\t%0,%1", xoperands
);
2715 output_asm_insn ("la\t%0,%1", xoperands
);
2720 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2721 are not offsettable, however, offsettable_address_p says they are
2722 offsettable. I think this is a bug in offsettable_address_p.
2723 For expediency, we fix this by just loading the address into a register
2724 if we happen to get one. */
2726 if (GET_CODE (src_reg
) == LO_SUM
)
2728 src_reg
= operands
[ 3 + num_regs
-- ];
2729 if (move_type
!= BLOCK_MOVE_LAST
)
2731 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
2732 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2733 xoperands
[0] = src_reg
;
2734 if (Pmode
== DImode
)
2735 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2737 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2741 if (GET_CODE (dest_reg
) == LO_SUM
)
2743 dest_reg
= operands
[ 3 + num_regs
-- ];
2744 if (move_type
!= BLOCK_MOVE_LAST
)
2746 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
2747 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
2748 xoperands
[0] = dest_reg
;
2749 if (Pmode
== DImode
)
2750 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2752 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2756 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2757 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2759 else if (num_regs
< 1)
2760 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2764 load_store
[num
].offset
= offset
;
2766 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2768 load_store
[num
].load
= "ld\t%0,%1";
2769 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2770 load_store
[num
].store
= "sd\t%0,%1";
2771 load_store
[num
].last_store
= "sd\t%0,%1";
2772 load_store
[num
].final
= (char *)0;
2773 load_store
[num
].mode
= DImode
;
2778 else if (TARGET_64BIT
&& bytes
>= 8)
2780 if (BYTES_BIG_ENDIAN
)
2782 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2783 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2784 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2785 load_store
[num
].last_store
= "sdr\t%0,%2";
2786 load_store
[num
].final
= "sdl\t%0,%1";
2790 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2791 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2792 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2793 load_store
[num
].last_store
= "sdr\t%0,%1";
2794 load_store
[num
].final
= "sdl\t%0,%2";
2796 load_store
[num
].mode
= DImode
;
2802 else if (bytes
>= 4 && align
>= 4)
2804 load_store
[num
].load
= "lw\t%0,%1";
2805 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2806 load_store
[num
].store
= "sw\t%0,%1";
2807 load_store
[num
].last_store
= "sw\t%0,%1";
2808 load_store
[num
].final
= (char *)0;
2809 load_store
[num
].mode
= SImode
;
2814 else if (bytes
>= 4)
2816 if (BYTES_BIG_ENDIAN
)
2818 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2819 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2820 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2821 load_store
[num
].last_store
= "swr\t%0,%2";
2822 load_store
[num
].final
= "swl\t%0,%1";
2826 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2827 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2828 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2829 load_store
[num
].last_store
= "swr\t%0,%1";
2830 load_store
[num
].final
= "swl\t%0,%2";
2832 load_store
[num
].mode
= SImode
;
2838 else if (bytes
>= 2 && align
>= 2)
2840 load_store
[num
].load
= "lh\t%0,%1";
2841 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2842 load_store
[num
].store
= "sh\t%0,%1";
2843 load_store
[num
].last_store
= "sh\t%0,%1";
2844 load_store
[num
].final
= (char *)0;
2845 load_store
[num
].mode
= HImode
;
2852 load_store
[num
].load
= "lb\t%0,%1";
2853 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2854 load_store
[num
].store
= "sb\t%0,%1";
2855 load_store
[num
].last_store
= "sb\t%0,%1";
2856 load_store
[num
].final
= (char *)0;
2857 load_store
[num
].mode
= QImode
;
2862 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2864 dslots_load_total
++;
2865 dslots_load_filled
++;
2867 if (CONSTANT_P (src_reg
))
2868 mips_count_memory_refs (src_reg
, 1);
2870 if (CONSTANT_P (dest_reg
))
2871 mips_count_memory_refs (dest_reg
, 1);
2874 /* Emit load/stores now if we have run out of registers or are
2875 at the end of the move. */
2877 if (++num
== num_regs
|| bytes
== 0)
2879 /* If only load/store, we need a NOP after the load. */
2882 load_store
[0].load
= load_store
[0].load_nop
;
2883 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2884 dslots_load_filled
--;
2887 if (move_type
!= BLOCK_MOVE_LAST
)
2889 for (i
= 0; i
< num
; i
++)
2896 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2897 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2899 offset
= load_store
[i
].offset
;
2900 xoperands
[0] = operands
[i
+4];
2901 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2902 plus_constant (src_reg
, offset
));
2907 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2908 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2909 plus_constant (src_reg
,
2914 output_asm_insn (load_store
[i
].load
, xoperands
);
2918 for (i
= 0; i
< num
; i
++)
2920 int last_p
= (i
== num
-1 && bytes
== 0);
2921 int offset
= load_store
[i
].offset
;
2923 xoperands
[0] = operands
[i
+4];
2924 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2925 plus_constant (dest_reg
, offset
));
2931 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2932 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2933 plus_constant (dest_reg
,
2938 if (move_type
== BLOCK_MOVE_NORMAL
)
2939 output_asm_insn (load_store
[i
].store
, xoperands
);
2941 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2944 output_asm_insn (load_store
[i
].store
, xoperands
);
2946 else if (load_store
[i
].final
!= (char *)0)
2947 output_asm_insn (load_store
[i
].final
, xoperands
);
2951 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2954 num
= 0; /* reset load_store */
2955 use_lwl_lwr
= FALSE
;
2963 /* Argument support functions. */
2965 /* Initialize CUMULATIVE_ARGS for a function. */
2968 init_cumulative_args (cum
, fntype
, libname
)
2969 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2970 tree fntype
; /* tree ptr for function decl */
2971 rtx libname
; /* SYMBOL_REF of library name or 0 */
2973 static CUMULATIVE_ARGS zero_cum
;
2974 tree param
, next_param
;
2976 if (TARGET_DEBUG_E_MODE
)
2978 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2980 fputc ('\n', stderr
);
2984 tree ret_type
= TREE_TYPE (fntype
);
2985 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2986 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2987 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2993 /* Determine if this function has variable arguments. This is
2994 indicated by the last argument being 'void_type_mode' if there
2995 are no variable arguments. The standard MIPS calling sequence
2996 passes all arguments in the general purpose registers in this
2999 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
3003 next_param
= TREE_CHAIN (param
);
3004 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
3005 cum
->gp_reg_found
= 1;
3009 /* Advance the argument to the next argument position. */
3012 function_arg_advance (cum
, mode
, type
, named
)
3013 CUMULATIVE_ARGS
*cum
; /* current arg information */
3014 enum machine_mode mode
; /* current arg mode */
3015 tree type
; /* type of the argument or 0 if lib support */
3016 int named
; /* whether or not the argument was named */
3018 if (TARGET_DEBUG_E_MODE
)
3020 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
3021 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3031 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3032 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3034 cum
->gp_reg_found
= 1;
3035 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
3040 cum
->gp_reg_found
= 1;
3041 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3046 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3047 cum
->fp_arg_words
++;
3053 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3054 cum
->fp_arg_words
+= (TARGET_64BIT
? 1 : 2);
3056 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3060 cum
->gp_reg_found
= 1;
3061 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3067 cum
->gp_reg_found
= 1;
3073 /* Return an RTL expression containing the register for the given mode,
3074 or 0 if the argument is to be passed on the stack. */
3077 function_arg (cum
, mode
, type
, named
)
3078 CUMULATIVE_ARGS
*cum
; /* current arg information */
3079 enum machine_mode mode
; /* current arg mode */
3080 tree type
; /* type of the argument or 0 if lib support */
3081 int named
; /* != 0 for normal args, == 0 for ... args */
3086 int *arg_words
= &cum
->arg_words
;
3087 int struct_p
= ((type
!= (tree
)0)
3088 && (TREE_CODE (type
) == RECORD_TYPE
3089 || TREE_CODE (type
) == UNION_TYPE
));
3091 if (TARGET_DEBUG_E_MODE
)
3093 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
3094 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3097 cum
->last_arg_fp
= 0;
3101 if (mips_abi
== ABI_32
)
3103 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
3104 regbase
= GP_ARG_FIRST
;
3107 regbase
= FP_ARG_FIRST
;
3108 /* If the first arg was a float in a floating point register,
3109 then set bias to align this float arg properly. */
3110 if (cum
->arg_words
== 1)
3114 else if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3117 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3118 cum
->last_arg_fp
= 1;
3119 arg_words
= &cum
->fp_arg_words
;
3120 regbase
= FP_ARG_FIRST
;
3123 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3129 if (mips_abi
== ABI_EABI
3130 && ! TARGET_SOFT_FLOAT
3131 && ! TARGET_SINGLE_FLOAT
)
3132 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3134 cum
->arg_words
+= cum
->arg_words
& 1;
3136 if (mips_abi
== ABI_32
)
3137 regbase
= ((cum
->gp_reg_found
3138 || TARGET_SOFT_FLOAT
3139 || TARGET_SINGLE_FLOAT
3140 || cum
->arg_number
>= 2)
3143 else if (mips_abi
== ABI_EABI
3144 && ! TARGET_SOFT_FLOAT
3145 && ! TARGET_SINGLE_FLOAT
)
3147 cum
->last_arg_fp
= 1;
3148 arg_words
= &cum
->fp_arg_words
;
3149 regbase
= FP_ARG_FIRST
;
3152 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3153 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3157 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3158 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3161 /* Drops through. */
3163 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
3164 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3165 cum
->arg_words
+= (cum
->arg_words
& 1);
3166 regbase
= GP_ARG_FIRST
;
3173 regbase
= GP_ARG_FIRST
;
3178 cum
->arg_words
+= (cum
->arg_words
& 1);
3179 regbase
= GP_ARG_FIRST
;
3182 if (*arg_words
>= MAX_ARGS_IN_REGISTERS
)
3184 if (TARGET_DEBUG_E_MODE
)
3185 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3194 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3195 || mips_abi
== ABI_EABI
|| ! named
)
3196 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3199 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3200 structure contains a double in its entirety, then that 64 bit
3201 chunk is passed in a floating point register. */
3204 /* First check to see if there is any such field. */
3205 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3206 if (TREE_CODE (field
) == FIELD_DECL
3207 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3208 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3209 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3210 % BITS_PER_WORD
== 0))
3213 /* If the whole struct fits a DFmode register,
3214 we don't need the PARALLEL. */
3215 if (! field
|| mode
== DFmode
)
3216 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3219 /* Now handle the special case by returning a PARALLEL
3220 indicating where each 64 bit chunk goes. */
3226 /* ??? If this is a packed structure, then the last hunk won't
3229 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3230 if (chunks
+ *arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3231 chunks
= MAX_ARGS_IN_REGISTERS
- *arg_words
- bias
;
3233 /* assign_parms checks the mode of ENTRY_PARM, so we must
3234 use the actual mode here. */
3235 ret
= gen_rtx (PARALLEL
, mode
, rtvec_alloc (chunks
));
3238 regno
= regbase
+ *arg_words
+ bias
;
3239 field
= TYPE_FIELDS (type
);
3240 for (i
= 0; i
< chunks
; i
++)
3244 for (; field
; field
= TREE_CHAIN (field
))
3245 if (TREE_CODE (field
) == FIELD_DECL
3246 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3251 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3252 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3253 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3254 reg
= gen_rtx (REG
, DFmode
,
3255 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3257 reg
= gen_rtx (REG
, word_mode
, regno
);
3259 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
3260 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3268 if (TARGET_DEBUG_E_MODE
)
3269 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ *arg_words
+ bias
],
3270 struct_p
? ", [struct]" : "");
3272 /* The following is a hack in order to pass 1 byte structures
3273 the same way that the MIPS compiler does (namely by passing
3274 the structure in the high byte or half word of the register).
3275 This also makes varargs work. If we have such a structure,
3276 we save the adjustment RTL, and the call define expands will
3277 emit them. For the VOIDmode argument (argument after the
3278 last real argument), pass back a parallel vector holding each
3279 of the adjustments. */
3281 /* ??? function_arg can be called more than once for each argument.
3282 As a result, we compute more adjustments than we need here.
3283 See the CUMULATIVE_ARGS definition in mips.h. */
3285 /* ??? This scheme requires everything smaller than the word size to
3286 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3287 that would mean every int needs to be shifted left, which is very
3288 inefficient. Let's not carry this compatibility to the 64 bit
3289 calling convention for now. */
3291 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3292 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3294 rtx amount
= GEN_INT (BITS_PER_WORD
3295 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3296 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ *arg_words
+ bias
);
3298 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
3300 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
3304 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
3305 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3312 function_arg_partial_nregs (cum
, mode
, type
, named
)
3313 CUMULATIVE_ARGS
*cum
; /* current arg information */
3314 enum machine_mode mode
; /* current arg mode */
3315 tree type
; /* type of the argument or 0 if lib support */
3316 int named
; /* != 0 for normal args, == 0 for ... args */
3318 if ((mode
== BLKmode
3319 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3320 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3321 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
3322 && mips_abi
!= ABI_EABI
)
3325 if (mode
== BLKmode
)
3326 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3329 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3331 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3332 return 0; /* structure fits in registers */
3334 if (TARGET_DEBUG_E_MODE
)
3335 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3336 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3338 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3341 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3343 && mips_abi
!= ABI_EABI
)
3345 if (TARGET_DEBUG_E_MODE
)
3346 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3354 /* Abort after printing out a specific insn. */
3357 abort_with_insn (insn
, reason
)
3366 /* Write a message to stderr (for use in macros expanded in files that do not
3367 include stdio.h). */
3373 fprintf (stderr
, s
, s1
, s2
);
3383 fprintf (stderr
, "compiling '%s' in '%s'\n",
3384 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3385 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3388 #endif /* SIGINFO */
3391 /* Set up the threshold for data to go into the small data area, instead
3392 of the normal data area, and detect any conflicts in the switches. */
3397 register int i
, start
;
3399 register enum machine_mode mode
;
3401 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3403 if (mips_section_threshold
<= 0)
3404 target_flags
&= ~MASK_GPOPT
;
3406 target_flags
|= MASK_GPOPT
;
3408 /* Get the architectural level. */
3409 if (mips_isa_string
== (char *)0)
3411 #ifdef MIPS_ISA_DEFAULT
3412 mips_isa
= MIPS_ISA_DEFAULT
;
3418 else if (isdigit (*mips_isa_string
))
3420 mips_isa
= atoi (mips_isa_string
);
3421 if (mips_isa
< 1 || mips_isa
> 4)
3423 error ("-mips%d not supported", mips_isa
);
3430 error ("bad value (%s) for -mips switch", mips_isa_string
);
3434 #ifdef MIPS_ABI_DEFAULT
3435 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3436 if (mips_abi_string
== (char *) 0)
3437 mips_abi
= MIPS_ABI_DEFAULT
;
3438 else if (! strcmp (mips_abi_string
, "32")
3439 || ! strcmp (mips_abi_string
, "o32"))
3441 else if (! strcmp (mips_abi_string
, "n32"))
3443 else if (! strcmp (mips_abi_string
, "64")
3444 || ! strcmp (mips_abi_string
, "n64"))
3446 else if (! strcmp (mips_abi_string
, "eabi"))
3447 mips_abi
= ABI_EABI
;
3449 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3451 /* A specified ISA defaults the ABI if it was not specified. */
3452 if (mips_abi_string
== 0 && mips_isa_string
&& mips_abi
!= ABI_EABI
)
3459 /* A specified ABI defaults the ISA if it was not specified. */
3460 else if (mips_isa_string
== 0 && mips_abi_string
&& mips_abi
!= ABI_EABI
)
3462 if (mips_abi
== ABI_32
)
3464 else if (mips_abi
== ABI_N32
)
3469 /* If both ABI and ISA were specified, check for conflicts. */
3470 else if (mips_isa_string
&& mips_abi_string
)
3472 if ((mips_isa
<= 2 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3473 || (mips_isa
>= 3 && mips_abi
== ABI_32
))
3474 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
3477 /* Override TARGET_DEFAULT if necessary. */
3478 if (mips_abi
== ABI_32
)
3479 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
3481 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. Likewise
3482 for the SGI Irix6 N64 ABI. */
3483 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
)
3484 || mips_abi
== ABI_64
)
3485 target_flags
|= MASK_LONG64
;
3487 /* ??? This doesn't work yet, so don't let people try to use it. */
3488 if (mips_abi
== ABI_32
)
3489 error ("The -mabi=32 support does not work yet.");
3491 if (mips_abi_string
)
3492 error ("This target does not support the -mabi switch.");
3495 #ifdef MIPS_CPU_STRING_DEFAULT
3496 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3497 greater than that supported by the default processor, then the user gets
3498 an error. Normally, the compiler will just default to the base level cpu
3499 for the indicated isa. */
3500 if (mips_cpu_string
== (char *)0)
3501 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3504 /* Identify the processor type */
3505 if (mips_cpu_string
== (char *)0
3506 || !strcmp (mips_cpu_string
, "default")
3507 || !strcmp (mips_cpu_string
, "DEFAULT"))
3512 mips_cpu_string
= "3000";
3513 mips_cpu
= PROCESSOR_R3000
;
3516 mips_cpu_string
= "6000";
3517 mips_cpu
= PROCESSOR_R6000
;
3520 mips_cpu_string
= "4000";
3521 mips_cpu
= PROCESSOR_R4000
;
3524 mips_cpu_string
= "8000";
3525 mips_cpu
= PROCESSOR_R8000
;
3532 char *p
= mips_cpu_string
;
3535 /* We need to cope with the various "vr" prefixes for the NEC 4300
3536 and 4100 processors. */
3537 if (*p
== 'v' || *p
== 'V')
3542 if (*p
== 'r' || *p
== 'R')
3545 /* Since there is no difference between a R2000 and R3000 in
3546 terms of the scheduler, we collapse them into just an R3000. */
3548 mips_cpu
= PROCESSOR_DEFAULT
;
3552 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3553 mips_cpu
= PROCESSOR_R3000
;
3557 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3558 mips_cpu
= PROCESSOR_R3000
;
3559 else if (!strcmp (p
, "3900"))
3560 mips_cpu
= PROCESSOR_R3900
;
3564 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3565 mips_cpu
= PROCESSOR_R4000
;
3566 /* The vr4100 is a non-FP ISA III processor with some extra
3568 else if (!strcmp (p
, "4100")) {
3569 mips_cpu
= PROCESSOR_R4100
;
3570 target_flags
|= MASK_SOFT_FLOAT
;
3572 /* The vr4300 is a standard ISA III processor, but with a different
3574 else if (!strcmp (p
, "4300"))
3575 mips_cpu
= PROCESSOR_R4300
;
3576 /* The r4400 is exactly the same as the r4000 from the compiler's
3578 else if (!strcmp (p
, "4400"))
3579 mips_cpu
= PROCESSOR_R4000
;
3580 else if (!strcmp (p
, "4600"))
3581 mips_cpu
= PROCESSOR_R4600
;
3582 else if (!strcmp (p
, "4650"))
3583 mips_cpu
= PROCESSOR_R4650
;
3587 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
3588 mips_cpu
= PROCESSOR_R5000
;
3592 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3593 mips_cpu
= PROCESSOR_R6000
;
3597 if (!strcmp (p
, "8000"))
3598 mips_cpu
= PROCESSOR_R8000
;
3602 if (!strcmp (p
, "orion"))
3603 mips_cpu
= PROCESSOR_R4600
;
3608 && mips_cpu
!= PROCESSOR_R4300
3609 && mips_cpu
!= PROCESSOR_R4100
3610 && mips_cpu
!= PROCESSOR_R5000
)
3611 mips_cpu
= PROCESSOR_DEFAULT
;
3613 if (mips_cpu
== PROCESSOR_DEFAULT
)
3615 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3616 mips_cpu_string
= "default";
3620 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3621 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3622 || ((mips_cpu
== PROCESSOR_R4000
3623 || mips_cpu
== PROCESSOR_R4100
3624 || mips_cpu
== PROCESSOR_R4300
3625 || mips_cpu
== PROCESSOR_R4600
3626 || mips_cpu
== PROCESSOR_R4650
)
3628 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3630 /* make sure sizes of ints/longs/etc. are ok */
3634 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3636 else if (TARGET_LONG64
)
3637 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3639 else if (TARGET_FLOAT64
)
3640 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3642 else if (TARGET_64BIT
)
3643 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3646 if (mips_abi
!= ABI_32
)
3647 flag_pcc_struct_return
= 0;
3649 /* Tell halfpic.c that we have half-pic code if we do. */
3650 if (TARGET_HALF_PIC
)
3653 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3654 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3655 /* ??? -non_shared turns off pic code generation, but this is not
3657 if (TARGET_ABICALLS
)
3659 mips_abicalls
= MIPS_ABICALLS_YES
;
3661 if (mips_section_threshold
> 0)
3662 warning ("-G is incompatible with PIC code which is the default");
3665 mips_abicalls
= MIPS_ABICALLS_NO
;
3667 /* -membedded-pic is a form of PIC code suitable for embedded
3668 systems. All calls are made using PC relative addressing, and
3669 all data is addressed using the $gp register. This requires gas,
3670 which does most of the work, and GNU ld, which automatically
3671 expands PC relative calls which are out of range into a longer
3672 instruction sequence. All gcc really does differently is
3673 generate a different sequence for a switch. */
3674 if (TARGET_EMBEDDED_PIC
)
3677 if (TARGET_ABICALLS
)
3678 warning ("-membedded-pic and -mabicalls are incompatible");
3680 warning ("-G and -membedded-pic are incompatible");
3681 /* Setting mips_section_threshold is not required, because gas
3682 will force everything to be GP addressable anyhow, but
3683 setting it will cause gcc to make better estimates of the
3684 number of instructions required to access a particular data
3686 mips_section_threshold
= 0x7fffffff;
3689 /* This optimization requires a linker that can support a R_MIPS_LO16
3690 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
3691 GNU ld has this support, but not all other MIPS linkers do, so we enable
3692 this optimization only if the user requests it, or if GNU ld is the
3693 standard linker for this configuration. */
3694 /* ??? This does not work when target addresses are DImode.
3695 This is because we are missing DImode high/lo_sum patterns. */
3696 if (TARGET_GAS
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
3698 mips_split_addresses
= 1;
3700 mips_split_addresses
= 0;
3702 /* -mrnames says to use the MIPS software convention for register
3703 names instead of the hardware names (ie, $a0 instead of $4).
3704 We do this by switching the names in mips_reg_names, which the
3705 reg_names points into via the REGISTER_NAMES macro. */
3707 if (TARGET_NAME_REGS
)
3708 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3710 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3711 is currently being compiled. */
3713 if (getenv ("GCC_SIGINFO") != (char *)0)
3715 struct sigaction action
;
3716 action
.sa_handler
= siginfo
;
3718 action
.sa_flags
= SA_RESTART
;
3719 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3724 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3725 /* If -mstats and -quiet, make stderr line buffered. */
3726 if (quiet_flag
&& TARGET_STATS
)
3727 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3731 /* Initialize the high and low values for legitimate floating point
3732 constants. Rather than trying to get the accuracy down to the
3733 last bit, just use approximate ranges. */
3734 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3735 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3736 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3737 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3739 mips_print_operand_punct
['?'] = TRUE
;
3740 mips_print_operand_punct
['#'] = TRUE
;
3741 mips_print_operand_punct
['&'] = TRUE
;
3742 mips_print_operand_punct
['!'] = TRUE
;
3743 mips_print_operand_punct
['*'] = TRUE
;
3744 mips_print_operand_punct
['@'] = TRUE
;
3745 mips_print_operand_punct
['.'] = TRUE
;
3746 mips_print_operand_punct
['('] = TRUE
;
3747 mips_print_operand_punct
[')'] = TRUE
;
3748 mips_print_operand_punct
['['] = TRUE
;
3749 mips_print_operand_punct
[']'] = TRUE
;
3750 mips_print_operand_punct
['<'] = TRUE
;
3751 mips_print_operand_punct
['>'] = TRUE
;
3752 mips_print_operand_punct
['{'] = TRUE
;
3753 mips_print_operand_punct
['}'] = TRUE
;
3754 mips_print_operand_punct
['^'] = TRUE
;
3756 mips_char_to_class
['d'] = GR_REGS
;
3757 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3758 mips_char_to_class
['h'] = HI_REG
;
3759 mips_char_to_class
['l'] = LO_REG
;
3760 mips_char_to_class
['a'] = HILO_REG
;
3761 mips_char_to_class
['x'] = MD_REGS
;
3762 mips_char_to_class
['b'] = ALL_REGS
;
3763 mips_char_to_class
['y'] = GR_REGS
;
3764 mips_char_to_class
['z'] = ST_REGS
;
3766 /* Set up array to map GCC register number to debug register number.
3767 Ignore the special purpose register numbers. */
3769 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3770 mips_dbx_regno
[i
] = -1;
3772 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3773 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3774 mips_dbx_regno
[i
] = i
+ start
;
3776 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3777 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3778 mips_dbx_regno
[i
] = i
+ start
;
3780 /* Set up array giving whether a given register can hold a given mode.
3781 At present, restrict ints from being in FP registers, because reload
3782 is a little enthusiastic about storing extra values in FP registers,
3783 and this is not good for things like OS kernels. Also, due to the
3784 mandatory delay, it is as fast to load from cached memory as to move
3785 from the FP register. */
3787 for (mode
= VOIDmode
;
3788 mode
!= MAX_MACHINE_MODE
;
3789 mode
= (enum machine_mode
)((int)mode
+ 1))
3791 register int size
= GET_MODE_SIZE (mode
);
3792 register enum mode_class
class = GET_MODE_CLASS (mode
);
3794 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3801 temp
= (regno
== FPSW_REGNUM
);
3803 temp
= (ST_REG_P (regno
)
3805 || FP_REG_P (regno
));
3808 else if (GP_REG_P (regno
))
3809 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3811 else if (FP_REG_P (regno
))
3812 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3813 && (class == MODE_FLOAT
3814 || class == MODE_COMPLEX_FLOAT
3815 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3816 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3818 else if (MD_REG_P (regno
))
3819 temp
= (class == MODE_INT
3820 && (size
<= UNITS_PER_WORD
3821 || (regno
== MD_REG_FIRST
&& size
== 2 * UNITS_PER_WORD
)));
3826 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3833 * The MIPS debug format wants all automatic variables and arguments
3834 * to be in terms of the virtual frame pointer (stack pointer before
3835 * any adjustment in the function), while the MIPS 3.0 linker wants
3836 * the frame pointer to be the stack pointer after the initial
3837 * adjustment. So, we do the adjustment here. The arg pointer (which
3838 * is eliminated) points to the virtual frame pointer, while the frame
3839 * pointer (which may be eliminated) points to the stack pointer after
3840 * the initial adjustments.
3844 mips_debugger_offset (addr
, offset
)
3848 rtx offset2
= const0_rtx
;
3849 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3852 offset
= INTVAL (offset2
);
3854 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3856 int frame_size
= (!current_frame_info
.initialized
)
3857 ? compute_frame_size (get_frame_size ())
3858 : current_frame_info
.total_size
;
3860 offset
= offset
- frame_size
;
3862 /* sdbout_parms does not want this to crash for unrecognized cases. */
3864 else if (reg
!= arg_pointer_rtx
)
3865 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3872 /* A C compound statement to output to stdio stream STREAM the
3873 assembler syntax for an instruction operand X. X is an RTL
3876 CODE is a value that can be used to specify one of several ways
3877 of printing the operand. It is used when identical operands
3878 must be printed differently depending on the context. CODE
3879 comes from the `%' specification that was used to request
3880 printing of the operand. If the specification was just `%DIGIT'
3881 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3882 is the ASCII code for LTR.
3884 If X is a register, this macro should print the register's name.
3885 The names can be found in an array `reg_names' whose type is
3886 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3888 When the machine description has a specification `%PUNCT' (a `%'
3889 followed by a punctuation character), this macro is called with
3890 a null pointer for X and the punctuation character for CODE.
3892 The MIPS specific codes are:
3894 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3895 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3896 'd' output integer constant in decimal,
3897 'z' if the operand is 0, use $0 instead of normal operand.
3898 'D' print second register of double-word register operand.
3899 'L' print low-order register of double-word register operand.
3900 'M' print high-order register of double-word register operand.
3901 'C' print part of opcode for a branch condition.
3902 'N' print part of opcode for a branch condition, inverted.
3903 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3904 'B' print 'z' for EQ, 'n' for NE
3905 'b' print 'n' for EQ, 'z' for NE
3906 'T' print 'f' for EQ, 't' for NE
3907 't' print 't' for EQ, 'f' for NE
3908 'Z' print register and a comma, but print nothing for $fcc0
3909 '(' Turn on .set noreorder
3910 ')' Turn on .set reorder
3911 '[' Turn on .set noat
3913 '<' Turn on .set nomacro
3914 '>' Turn on .set macro
3915 '{' Turn on .set volatile (not GAS)
3916 '}' Turn on .set novolatile (not GAS)
3917 '&' Turn on .set noreorder if filling delay slots
3918 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3919 '!' Turn on .set nomacro if filling delay slots
3920 '#' Print nop if in a .set noreorder section.
3921 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3922 '@' Print the name of the assembler temporary register (at or $1).
3923 '.' Print the name of the register with a hard-wired zero (zero or $0).
3924 '^' Print the name of the pic call-through register (t9 or $25). */
3927 print_operand (file
, op
, letter
)
3928 FILE *file
; /* file to write to */
3929 rtx op
; /* operand to print */
3930 int letter
; /* %<letter> or 0 */
3932 register enum rtx_code code
;
3934 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3939 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3943 if (mips_branch_likely
)
3948 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3952 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3956 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3960 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3961 fputs (".set\tnoreorder\n\t", file
);
3965 if (final_sequence
!= 0)
3967 if (set_noreorder
++ == 0)
3968 fputs (".set\tnoreorder\n\t", file
);
3970 if (set_nomacro
++ == 0)
3971 fputs (".set\tnomacro\n\t", file
);
3976 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3977 fputs ("\n\t.set\tnomacro", file
);
3981 if (set_noreorder
!= 0)
3982 fputs ("\n\tnop", file
);
3984 else if (TARGET_STATS
)
3985 fputs ("\n\t#nop", file
);
3990 if (set_noreorder
++ == 0)
3991 fputs (".set\tnoreorder\n\t", file
);
3995 if (set_noreorder
== 0)
3996 error ("internal error: %%) found without a %%( in assembler pattern");
3998 else if (--set_noreorder
== 0)
3999 fputs ("\n\t.set\treorder", file
);
4004 if (set_noat
++ == 0)
4005 fputs (".set\tnoat\n\t", file
);
4010 error ("internal error: %%] found without a %%[ in assembler pattern");
4012 else if (--set_noat
== 0)
4013 fputs ("\n\t.set\tat", file
);
4018 if (set_nomacro
++ == 0)
4019 fputs (".set\tnomacro\n\t", file
);
4023 if (set_nomacro
== 0)
4024 error ("internal error: %%> found without a %%< in assembler pattern");
4026 else if (--set_nomacro
== 0)
4027 fputs ("\n\t.set\tmacro", file
);
4032 if (set_volatile
++ == 0)
4033 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
4037 if (set_volatile
== 0)
4038 error ("internal error: %%} found without a %%{ in assembler pattern");
4040 else if (--set_volatile
== 0)
4041 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
4050 error ("PRINT_OPERAND null pointer");
4054 code
= GET_CODE (op
);
4056 if (code
== SIGN_EXTEND
)
4059 code
= GET_CODE (op
);
4065 case EQ
: fputs ("eq", file
); break;
4066 case NE
: fputs ("ne", file
); break;
4067 case GT
: fputs ("gt", file
); break;
4068 case GE
: fputs ("ge", file
); break;
4069 case LT
: fputs ("lt", file
); break;
4070 case LE
: fputs ("le", file
); break;
4071 case GTU
: fputs ("gtu", file
); break;
4072 case GEU
: fputs ("geu", file
); break;
4073 case LTU
: fputs ("ltu", file
); break;
4074 case LEU
: fputs ("leu", file
); break;
4077 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
4080 else if (letter
== 'N')
4083 case EQ
: fputs ("ne", file
); break;
4084 case NE
: fputs ("eq", file
); break;
4085 case GT
: fputs ("le", file
); break;
4086 case GE
: fputs ("lt", file
); break;
4087 case LT
: fputs ("ge", file
); break;
4088 case LE
: fputs ("gt", file
); break;
4089 case GTU
: fputs ("leu", file
); break;
4090 case GEU
: fputs ("ltu", file
); break;
4091 case LTU
: fputs ("geu", file
); break;
4092 case LEU
: fputs ("gtu", file
); break;
4095 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
4098 else if (letter
== 'S')
4102 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
4103 assemble_name (file
, buffer
);
4106 else if (letter
== 'Z')
4108 register int regnum
;
4112 regnum
= REGNO (op
);
4113 if (! ST_REG_P (regnum
))
4115 if (regnum
!= ST_REG_FIRST
)
4116 fprintf (file
, "%s,", reg_names
[regnum
]);
4119 else if (code
== REG
|| code
== SUBREG
)
4121 register int regnum
;
4124 regnum
= REGNO (op
);
4126 regnum
= true_regnum (op
);
4128 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
4129 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
4133 fprintf (file
, "%s", reg_names
[regnum
]);
4136 else if (code
== MEM
)
4137 output_address (XEXP (op
, 0));
4139 else if (code
== CONST_DOUBLE
4140 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
4145 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
4146 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
4150 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
4151 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
4153 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4154 && HOST_BITS_PER_WIDE_INT
== 32)
4155 fprintf (file
, "0x%08x", INTVAL(op
));
4157 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4158 && HOST_BITS_PER_WIDE_INT
== 64)
4159 fprintf (file
, "0x%016lx", INTVAL(op
));
4161 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
4162 fprintf (file
, "%d", (INTVAL(op
)));
4164 else if (letter
== 'z'
4165 && (GET_CODE (op
) == CONST_INT
)
4166 && INTVAL (op
) == 0)
4167 fputs (reg_names
[GP_REG_FIRST
], file
);
4169 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
4170 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
4172 else if (letter
== 'B')
4173 fputs (code
== EQ
? "z" : "n", file
);
4174 else if (letter
== 'b')
4175 fputs (code
== EQ
? "n" : "z", file
);
4176 else if (letter
== 'T')
4177 fputs (code
== EQ
? "f" : "t", file
);
4178 else if (letter
== 't')
4179 fputs (code
== EQ
? "t" : "f", file
);
4182 output_addr_const (file
, op
);
4186 /* A C compound statement to output to stdio stream STREAM the
4187 assembler syntax for an instruction operand that is a memory
4188 reference whose address is ADDR. ADDR is an RTL expression.
4190 On some machines, the syntax for a symbolic address depends on
4191 the section that the address refers to. On these machines,
4192 define the macro `ENCODE_SECTION_INFO' to store the information
4193 into the `symbol_ref', and then check for it here. */
4196 print_operand_address (file
, addr
)
4201 error ("PRINT_OPERAND_ADDRESS, null pointer");
4204 switch (GET_CODE (addr
))
4207 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4211 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
4212 abort_with_insn (addr
, "Arg pointer not eliminated.");
4214 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
4219 register rtx arg0
= XEXP (addr
, 0);
4220 register rtx arg1
= XEXP (addr
, 1);
4222 if (! mips_split_addresses
)
4223 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4225 if (GET_CODE (arg0
) != REG
)
4226 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4228 fprintf (file
, "%%lo(");
4229 print_operand_address (file
, arg1
);
4230 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
4236 register rtx reg
= (rtx
)0;
4237 register rtx offset
= (rtx
)0;
4238 register rtx arg0
= XEXP (addr
, 0);
4239 register rtx arg1
= XEXP (addr
, 1);
4241 if (GET_CODE (arg0
) == REG
)
4245 if (GET_CODE (offset
) == REG
)
4246 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
4248 else if (GET_CODE (arg1
) == REG
)
4253 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
4255 output_addr_const (file
, addr
);
4259 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
4261 if (!CONSTANT_P (offset
))
4262 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4264 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
4265 abort_with_insn (addr
, "Arg pointer not eliminated.");
4267 output_addr_const (file
, offset
);
4268 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
4276 output_addr_const (file
, addr
);
4282 /* If optimizing for the global pointer, keep track of all of
4283 the externs, so that at the end of the file, we can emit
4284 the appropriate .extern declaration for them, before writing
4285 out the text section. We assume that all names passed to
4286 us are in the permanent obstack, so that they will be valid
4287 at the end of the compilation.
4289 If we have -G 0, or the extern size is unknown, or the object is in
4290 a user specified section that is not .sbss/.sdata, don't bother
4291 emitting the .externs. In the case of user specified sections this
4292 behaviour is required as otherwise GAS will think the object lives in
4296 mips_output_external (file
, decl
, name
)
4301 register struct extern_list
*p
;
4306 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
4307 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0)
4308 && (((section_name
= DECL_SECTION_NAME (decl
)) == NULL
)
4309 || strcmp (TREE_STRING_POINTER (section_name
), ".sbss") == 0
4310 || strcmp (TREE_STRING_POINTER (section_name
), ".sdata") == 0))
4312 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4313 p
->next
= extern_head
;
4319 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4320 if (TREE_CODE (decl
) == FUNCTION_DECL
4321 /* ??? Don't include alloca, since gcc will always expand it
4322 inline. If we don't do this, the C++ library fails to build. */
4323 && strcmp (name
, "alloca")
4324 /* ??? Don't include __builtin_next_arg, because then gcc will not
4325 bootstrap under Irix 5.1. */
4326 && strcmp (name
, "__builtin_next_arg"))
4328 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4329 p
->next
= extern_head
;
4339 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4341 mips_output_external_libcall (file
, name
)
4345 register struct extern_list
*p
;
4347 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4348 p
->next
= extern_head
;
4358 /* Compute a string to use as a temporary file name. */
4360 /* On MSDOS, write temp files in current dir
4361 because there's no place else we can expect to use. */
4364 #define P_tmpdir "./"
4372 char *base
= getenv ("TMPDIR");
4375 if (base
== (char *)0)
4378 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
4382 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
4388 len
= strlen (base
);
4389 /* temp_filename is global, so we must use malloc, not alloca. */
4390 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
4391 strcpy (temp_filename
, base
);
4392 if (len
> 0 && temp_filename
[len
-1] != '/')
4393 temp_filename
[len
++] = '/';
4395 strcpy (temp_filename
+ len
, "ctXXXXXX");
4396 mktemp (temp_filename
);
4398 stream
= fopen (temp_filename
, "w+");
4400 pfatal_with_name (temp_filename
);
4403 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4404 it. Otherwise, we delete it now, so that it will be gone even if the
4405 compiler happens to crash. */
4406 unlink (temp_filename
);
4412 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4413 for .file's that start within a function. If we are smuggling stabs, try to
4414 put out a MIPS ECOFF file and a stab. */
4417 mips_output_filename (stream
, name
)
4421 static int first_time
= TRUE
;
4422 char ltext_label_name
[100];
4428 current_function_file
= name
;
4429 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4430 /* This tells mips-tfile that stabs will follow. */
4431 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4432 fprintf (stream
, "\t#@stabs\n");
4435 else if (write_symbols
== DBX_DEBUG
)
4437 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4438 fprintf (stream
, "%s ", ASM_STABS_OP
);
4439 output_quoted_string (stream
, name
);
4440 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4443 else if (name
!= current_function_file
4444 && strcmp (name
, current_function_file
) != 0)
4446 if (inside_function
&& !TARGET_GAS
)
4448 if (!file_in_function_warning
)
4450 file_in_function_warning
= TRUE
;
4451 ignore_line_number
= TRUE
;
4452 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4458 current_function_file
= name
;
4459 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4465 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4466 as well as a .loc, since it is possible that MIPS ECOFF might not be
4467 able to represent the location for inlines that come from a different
4471 mips_output_lineno (stream
, line
)
4475 if (write_symbols
== DBX_DEBUG
)
4478 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4479 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4480 LOCAL_LABEL_PREFIX
, sym_lineno
);
4485 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4486 (ignore_line_number
) ? "#" : "",
4487 num_source_filenames
, line
);
4489 LABEL_AFTER_LOC (stream
);
4494 /* If defined, a C statement to be executed just prior to the
4495 output of assembler code for INSN, to modify the extracted
4496 operands so they will be output differently.
4498 Here the argument OPVEC is the vector containing the operands
4499 extracted from INSN, and NOPERANDS is the number of elements of
4500 the vector which contain meaningful data for this insn. The
4501 contents of this vector are what will be used to convert the
4502 insn template into assembler code, so you can change the
4503 assembler output by changing the contents of the vector.
4505 We use it to check if the current insn needs a nop in front of it
4506 because of load delays, and also to update the delay slot
4509 /* ??? There is no real need for this function, because it never actually
4510 emits a NOP anymore. */
4513 final_prescan_insn (insn
, opvec
, noperands
)
4518 if (dslots_number_nops
> 0)
4520 rtx pattern
= PATTERN (insn
);
4521 int length
= get_attr_length (insn
);
4523 /* Do we need to emit a NOP? */
4525 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4526 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4527 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4528 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4529 fputs ("\t#nop\n", asm_out_file
);
4532 dslots_load_filled
++;
4534 while (--dslots_number_nops
> 0)
4535 fputs ("\t#nop\n", asm_out_file
);
4537 mips_load_reg
= (rtx
)0;
4538 mips_load_reg2
= (rtx
)0;
4539 mips_load_reg3
= (rtx
)0;
4540 mips_load_reg4
= (rtx
)0;
4545 enum rtx_code code
= GET_CODE (insn
);
4546 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4547 dslots_jump_total
++;
4552 /* Output at beginning of assembler file.
4553 If we are optimizing to use the global pointer, create a temporary
4554 file to hold all of the text stuff, and write it out to the end.
4555 This is needed because the MIPS assembler is evidently one pass,
4556 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4557 declaration when the code is processed, it generates a two
4558 instruction sequence. */
4561 mips_asm_file_start (stream
)
4564 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4566 /* Versions of the MIPS assembler before 2.20 generate errors
4567 if a branch inside of a .set noreorder section jumps to a
4568 label outside of the .set noreorder section. Revision 2.20
4569 just set nobopt silently rather than fixing the bug. */
4571 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4572 fprintf (stream
, "\t.set\tnobopt\n");
4574 /* Generate the pseudo ops that System V.4 wants. */
4575 #ifndef ABICALLS_ASM_OP
4576 #define ABICALLS_ASM_OP ".abicalls"
4578 if (TARGET_ABICALLS
)
4579 /* ??? but do not want this (or want pic0) if -non-shared? */
4580 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4582 /* Start a section, so that the first .popsection directive is guaranteed
4583 to have a previously defined section to pop back to. */
4584 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
4585 fprintf (stream
, "\t.section\t.text\n");
4587 /* This code exists so that we can put all externs before all symbol
4588 references. This is necessary for the MIPS assembler's global pointer
4589 optimizations to work. */
4590 if (TARGET_FILE_SWITCHING
)
4592 asm_out_data_file
= stream
;
4593 asm_out_text_file
= make_temp_file ();
4596 asm_out_data_file
= asm_out_text_file
= stream
;
4598 if (flag_verbose_asm
)
4599 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4601 mips_section_threshold
, mips_cpu_string
, mips_isa
);
4605 /* If we are optimizing the global pointer, emit the text section now
4606 and any small externs which did not have .comm, etc that are
4607 needed. Also, give a warning if the data area is more than 32K and
4608 -pic because 3 instructions are needed to reference the data
4612 mips_asm_file_end (file
)
4617 struct extern_list
*p
;
4621 HALF_PIC_FINISH (file
);
4627 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4629 name_tree
= get_identifier (p
->name
);
4631 /* Positively ensure only one .extern for any given symbol. */
4632 if (! TREE_ASM_WRITTEN (name_tree
))
4634 TREE_ASM_WRITTEN (name_tree
) = 1;
4635 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4637 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4641 fputs ("\t.extern\t", file
);
4642 assemble_name (file
, p
->name
);
4643 fprintf (file
, ", %d\n", p
->size
);
4649 if (TARGET_FILE_SWITCHING
)
4651 fprintf (file
, "\n\t.text\n");
4652 rewind (asm_out_text_file
);
4653 if (ferror (asm_out_text_file
))
4654 fatal_io_error (temp_filename
);
4656 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4657 if (fwrite (buffer
, 1, len
, file
) != len
)
4658 pfatal_with_name (asm_file_name
);
4661 pfatal_with_name (temp_filename
);
4663 if (fclose (asm_out_text_file
) != 0)
4664 pfatal_with_name (temp_filename
);
4667 unlink (temp_filename
);
4673 /* Emit either a label, .comm, or .lcomm directive, and mark
4674 that the symbol is used, so that we don't emit an .extern
4675 for it in mips_asm_file_end. */
4678 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4685 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4686 assemble_name (stream
, name
);
4687 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4691 tree name_tree
= get_identifier (name
);
4692 TREE_ASM_WRITTEN (name_tree
) = 1;
4697 /* Output a double precision value to the assembler. If both the
4698 host and target are IEEE, emit the values in hex. */
4701 mips_output_double (stream
, value
)
4703 REAL_VALUE_TYPE value
;
4705 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4707 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4709 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4710 value_long
[0], value
, value_long
[1]);
4712 fprintf (stream
, "\t.double\t%.20g\n", value
);
4717 /* Output a single precision value to the assembler. If both the
4718 host and target are IEEE, emit the values in hex. */
4721 mips_output_float (stream
, value
)
4723 REAL_VALUE_TYPE value
;
4725 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4727 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4729 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4731 fprintf (stream
, "\t.float\t%.12g\n", value
);
4736 /* Return the bytes needed to compute the frame pointer from the current
4739 Mips stack frames look like:
4741 Before call After call
4742 +-----------------------+ +-----------------------+
4745 | caller's temps. | | caller's temps. |
4747 +-----------------------+ +-----------------------+
4749 | arguments on stack. | | arguments on stack. |
4751 +-----------------------+ +-----------------------+
4752 | 4 words to save | | 4 words to save |
4753 | arguments passed | | arguments passed |
4754 | in registers, even | | in registers, even |
4755 SP->| if not passed. | VFP->| if not passed. |
4756 +-----------------------+ +-----------------------+
4758 | fp register save |
4760 +-----------------------+
4762 | gp register save |
4764 +-----------------------+
4768 +-----------------------+
4770 | alloca allocations |
4772 +-----------------------+
4774 | GP save for V.4 abi |
4776 +-----------------------+
4778 | arguments on stack |
4780 +-----------------------+
4782 | arguments passed |
4783 | in registers, even |
4784 low SP->| if not passed. |
4785 memory +-----------------------+
4790 compute_frame_size (size
)
4791 int size
; /* # of var. bytes allocated */
4794 long total_size
; /* # bytes that the entire frame takes up */
4795 long var_size
; /* # bytes that variables take up */
4796 long args_size
; /* # bytes that outgoing arguments take up */
4797 long extra_size
; /* # extra bytes */
4798 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4799 long gp_reg_size
; /* # bytes needed to store gp regs */
4800 long fp_reg_size
; /* # bytes needed to store fp regs */
4801 long mask
; /* mask of saved gp registers */
4802 long fmask
; /* mask of saved fp registers */
4803 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4804 long fp_bits
; /* bitmask to use for each fp register */
4810 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4811 var_size
= MIPS_STACK_ALIGN (size
);
4812 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4814 /* The MIPS 3.0 linker does not like functions that dynamically
4815 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4816 looks like we are trying to create a second frame pointer to the
4817 function, so allocate some stack space to make it happy. */
4819 if (args_size
== 0 && current_function_calls_alloca
)
4820 args_size
= 4*UNITS_PER_WORD
;
4822 total_size
= var_size
+ args_size
+ extra_size
;
4824 /* Calculate space needed for gp registers. */
4825 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4827 if (MUST_SAVE_REGISTER (regno
))
4829 gp_reg_size
+= UNITS_PER_WORD
;
4830 mask
|= 1L << (regno
- GP_REG_FIRST
);
4834 /* Calculate space needed for fp registers. */
4835 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4846 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4848 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4850 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4851 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4855 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4856 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4858 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4859 for leaf routines (total_size == extra_size) to save the gp reg.
4860 The gp reg is callee saved in the 64 bit ABI, so all routines must
4861 save the gp reg. This is not a leaf routine if -p, because of the
4863 if (total_size
== extra_size
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_EABI
)
4865 total_size
= extra_size
= 0;
4866 else if (TARGET_ABICALLS
)
4868 /* Add the context-pointer to the saved registers. */
4869 gp_reg_size
+= UNITS_PER_WORD
;
4870 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4871 total_size
-= gp_reg_rounded
;
4872 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4873 total_size
+= gp_reg_rounded
;
4876 /* Add in space reserved on the stack by the callee for storing arguments
4877 passed in registers. */
4878 if (mips_abi
!= ABI_32
)
4879 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4881 /* Save other computed information. */
4882 current_frame_info
.total_size
= total_size
;
4883 current_frame_info
.var_size
= var_size
;
4884 current_frame_info
.args_size
= args_size
;
4885 current_frame_info
.extra_size
= extra_size
;
4886 current_frame_info
.gp_reg_size
= gp_reg_size
;
4887 current_frame_info
.fp_reg_size
= fp_reg_size
;
4888 current_frame_info
.mask
= mask
;
4889 current_frame_info
.fmask
= fmask
;
4890 current_frame_info
.initialized
= reload_completed
;
4891 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4892 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4896 unsigned long offset
= (args_size
+ extra_size
+ var_size
4897 + gp_reg_size
- UNITS_PER_WORD
);
4898 current_frame_info
.gp_sp_offset
= offset
;
4899 current_frame_info
.gp_save_offset
= offset
- total_size
;
4903 current_frame_info
.gp_sp_offset
= 0;
4904 current_frame_info
.gp_save_offset
= 0;
4910 unsigned long offset
= (args_size
+ extra_size
+ var_size
4911 + gp_reg_rounded
+ fp_reg_size
4912 - fp_inc
* UNITS_PER_FPREG
);
4913 current_frame_info
.fp_sp_offset
= offset
;
4914 current_frame_info
.fp_save_offset
= offset
- total_size
;
4918 current_frame_info
.fp_sp_offset
= 0;
4919 current_frame_info
.fp_save_offset
= 0;
4922 /* Ok, we're done. */
4927 /* Common code to emit the insns (or to write the instructions to a file)
4928 to save/restore registers.
4930 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4931 is not modified within save_restore_insns. */
4933 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4936 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4937 int store_p
; /* true if this is prologue */
4938 rtx large_reg
; /* register holding large offset constant or NULL */
4939 long large_offset
; /* large constant offset value */
4940 FILE *file
; /* file to write instructions to instead of making RTL */
4942 long mask
= current_frame_info
.mask
;
4943 long fmask
= current_frame_info
.fmask
;
4952 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4955 if (mask
== 0 && fmask
== 0)
4958 /* Save registers starting from high to low. The debuggers prefer
4959 at least the return register be stored at func+4, and also it
4960 allows us not to need a nop in the epilog if at least one
4961 register is reloaded in addition to return address. */
4963 /* Save GP registers if needed. */
4966 /* Pick which pointer to use as a base register. For small
4967 frames, just use the stack pointer. Otherwise, use a
4968 temporary register. Save 2 cycles if the save area is near
4969 the end of a large frame, by reusing the constant created in
4970 the prologue/epilogue to adjust the stack frame. */
4972 gp_offset
= current_frame_info
.gp_sp_offset
;
4973 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
4975 if (gp_offset
< 0 || end_offset
< 0)
4976 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4977 gp_offset
, end_offset
);
4979 else if (gp_offset
< 32768)
4981 base_reg_rtx
= stack_pointer_rtx
;
4985 else if (large_reg
!= (rtx
)0
4986 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
4987 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4989 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4990 base_offset
= large_offset
;
4991 if (file
== (FILE *)0)
4994 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4996 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4998 RTX_FRAME_RELATED_P (insn
) = 1;
5001 fprintf (file
, "\t%s\t%s,%s,%s\n",
5002 TARGET_LONG64
? "daddu" : "addu",
5003 reg_names
[MIPS_TEMP2_REGNUM
],
5004 reg_names
[REGNO (large_reg
)],
5005 reg_names
[STACK_POINTER_REGNUM
]);
5010 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5011 base_offset
= gp_offset
;
5012 if (file
== (FILE *)0)
5014 rtx gp_offset_rtx
= GEN_INT (gp_offset
);
5016 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5017 bit, so make sure that we don't emit anything that can be
5019 /* ??? There is no DImode ori immediate pattern, so we can only
5020 do this for 32 bit code. */
5021 if (large_int (gp_offset_rtx
)
5022 && GET_MODE (base_reg_rtx
) == SImode
)
5024 insn
= emit_move_insn (base_reg_rtx
,
5025 GEN_INT (gp_offset
& 0xffff0000));
5027 RTX_FRAME_RELATED_P (insn
) = 1;
5028 insn
= emit_insn (gen_iorsi3 (base_reg_rtx
, base_reg_rtx
,
5029 GEN_INT (gp_offset
& 0x0000ffff)));
5031 RTX_FRAME_RELATED_P (insn
) = 1;
5035 insn
= emit_move_insn (base_reg_rtx
, gp_offset_rtx
);
5037 RTX_FRAME_RELATED_P (insn
) = 1;
5041 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5043 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5045 RTX_FRAME_RELATED_P (insn
) = 1;
5048 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5049 reg_names
[MIPS_TEMP2_REGNUM
],
5052 TARGET_LONG64
? "daddu" : "addu",
5053 reg_names
[MIPS_TEMP2_REGNUM
],
5054 reg_names
[MIPS_TEMP2_REGNUM
],
5055 reg_names
[STACK_POINTER_REGNUM
]);
5058 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
5060 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
5062 if (file
== (FILE *)0)
5064 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
5065 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
5066 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5067 GEN_INT (gp_offset
- base_offset
)));
5071 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5072 RTX_FRAME_RELATED_P (insn
) = 1;
5074 else if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
5075 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5076 emit_move_insn (reg_rtx
, mem_rtx
);
5080 if (store_p
|| !TARGET_ABICALLS
|| mips_abi
!= ABI_32
5081 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5082 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5084 ? (store_p
) ? "sd" : "ld"
5085 : (store_p
) ? "sw" : "lw"),
5087 gp_offset
- base_offset
,
5088 reg_names
[REGNO(base_reg_rtx
)]);
5091 gp_offset
-= UNITS_PER_WORD
;
5097 base_reg_rtx
= (rtx
)0; /* Make sure these are initialized */
5101 /* Save floating point registers if needed. */
5104 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
5105 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
5107 /* Pick which pointer to use as a base register. */
5108 fp_offset
= current_frame_info
.fp_sp_offset
;
5109 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
5111 if (fp_offset
< 0 || end_offset
< 0)
5112 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5113 fp_offset
, end_offset
);
5115 else if (fp_offset
< 32768)
5117 base_reg_rtx
= stack_pointer_rtx
;
5121 else if (base_reg_rtx
!= (rtx
)0
5122 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
5123 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
5125 ; /* already set up for gp registers above */
5128 else if (large_reg
!= (rtx
)0
5129 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
5130 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5132 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5133 base_offset
= large_offset
;
5134 if (file
== (FILE *)0)
5137 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5139 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5141 RTX_FRAME_RELATED_P (insn
) = 1;
5144 fprintf (file
, "\t%s\t%s,%s,%s\n",
5145 TARGET_LONG64
? "daddu" : "addu",
5146 reg_names
[MIPS_TEMP2_REGNUM
],
5147 reg_names
[REGNO (large_reg
)],
5148 reg_names
[STACK_POINTER_REGNUM
]);
5153 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5154 base_offset
= fp_offset
;
5155 if (file
== (FILE *)0)
5157 rtx fp_offset_rtx
= GEN_INT (fp_offset
);
5159 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5160 bit, so make sure that we don't emit anything that can be
5162 /* ??? There is no DImode ori immediate pattern, so we can only
5163 do this for 32 bit code. */
5164 if (large_int (fp_offset_rtx
)
5165 && GET_MODE (base_reg_rtx
) == SImode
)
5167 insn
= emit_move_insn (base_reg_rtx
,
5168 GEN_INT (fp_offset
& 0xffff0000));
5170 RTX_FRAME_RELATED_P (insn
) = 1;
5171 insn
= emit_insn (gen_iorsi3 (base_reg_rtx
, base_reg_rtx
,
5172 GEN_INT (fp_offset
& 0x0000ffff)));
5174 RTX_FRAME_RELATED_P (insn
) = 1;
5178 insn
= emit_move_insn (base_reg_rtx
, fp_offset_rtx
);
5180 RTX_FRAME_RELATED_P (insn
) = 1;
5184 RTX_FRAME_RELATED_P (insn
) = 1;
5186 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5188 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5190 RTX_FRAME_RELATED_P (insn
) = 1;
5193 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5194 reg_names
[MIPS_TEMP2_REGNUM
],
5197 TARGET_LONG64
? "daddu" : "addu",
5198 reg_names
[MIPS_TEMP2_REGNUM
],
5199 reg_names
[MIPS_TEMP2_REGNUM
],
5200 reg_names
[STACK_POINTER_REGNUM
]);
5203 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
5205 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
5207 if (file
== (FILE *)0)
5209 enum machine_mode sz
=
5210 TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5211 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
5212 rtx mem_rtx
= gen_rtx (MEM
, sz
,
5213 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5214 GEN_INT (fp_offset
- base_offset
)));
5218 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5219 RTX_FRAME_RELATED_P (insn
) = 1;
5222 emit_move_insn (reg_rtx
, mem_rtx
);
5225 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5226 (TARGET_SINGLE_FLOAT
5227 ? ((store_p
) ? "s.s" : "l.s")
5228 : ((store_p
) ? "s.d" : "l.d")),
5230 fp_offset
- base_offset
,
5231 reg_names
[REGNO(base_reg_rtx
)]);
5234 fp_offset
-= fp_size
;
5241 /* Set up the stack and frame (if desired) for the function. */
5244 function_prologue (file
, size
)
5249 long tsize
= current_frame_info
.total_size
;
5251 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
5253 #ifdef SDB_DEBUGGING_INFO
5254 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5255 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
5258 inside_function
= 1;
5260 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5261 /* Get the function name the same way that toplev.c does before calling
5262 assemble_start_function. This is needed so that the name used here
5263 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5264 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5266 if (!flag_inhibit_size_directive
)
5268 fputs ("\t.ent\t", file
);
5269 assemble_name (file
, fnname
);
5273 assemble_name (file
, fnname
);
5274 fputs (":\n", file
);
5277 if (!flag_inhibit_size_directive
)
5279 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5280 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
5282 reg_names
[31 + GP_REG_FIRST
],
5283 current_frame_info
.var_size
,
5284 current_frame_info
.num_gp
,
5285 current_frame_info
.num_fp
,
5286 current_function_outgoing_args_size
,
5287 current_frame_info
.extra_size
);
5289 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5290 current_frame_info
.mask
,
5291 current_frame_info
.gp_save_offset
,
5292 current_frame_info
.fmask
,
5293 current_frame_info
.fp_save_offset
);
5296 if (TARGET_ABICALLS
&& mips_abi
== ABI_32
)
5298 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5300 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5301 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
5304 fprintf (file
, "\t%s\t%s,%s,%d\n",
5305 (TARGET_LONG64
? "dsubu" : "subu"),
5306 sp_str
, sp_str
, tsize
);
5307 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
5310 if (dwarf2out_do_frame ())
5311 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, tsize
);
5316 /* Expand the prologue into a bunch of separate insns. */
5319 mips_expand_prologue ()
5323 rtx tmp_rtx
= (rtx
)0;
5324 char *arg_name
= (char *)0;
5325 tree fndecl
= current_function_decl
;
5326 tree fntype
= TREE_TYPE (fndecl
);
5327 tree fnargs
= DECL_ARGUMENTS (fndecl
);
5332 CUMULATIVE_ARGS args_so_far
;
5334 /* If struct value address is treated as the first argument, make it so. */
5335 if (aggregate_value_p (DECL_RESULT (fndecl
))
5336 && ! current_function_returns_pcc_struct
5337 && struct_value_incoming_rtx
== 0)
5339 tree type
= build_pointer_type (fntype
);
5340 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
5341 DECL_ARG_TYPE (function_result_decl
) = type
;
5342 TREE_CHAIN (function_result_decl
) = fnargs
;
5343 fnargs
= function_result_decl
;
5346 /* Determine the last argument, and get its name. */
5348 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0, 0);
5349 regno
= GP_ARG_FIRST
;
5351 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
5353 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
5354 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
5357 if (TREE_ADDRESSABLE (passed_type
))
5359 passed_type
= build_pointer_type (passed_type
);
5360 passed_mode
= Pmode
;
5363 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
5369 /* passed in a register, so will get homed automatically */
5370 if (GET_MODE (entry_parm
) == BLKmode
)
5371 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
5373 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
5375 regno
= REGNO (entry_parm
) + words
- 1;
5379 regno
= GP_ARG_LAST
+1;
5383 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
5385 next_arg
= TREE_CHAIN (cur_arg
);
5386 if (next_arg
== (tree
)0)
5388 if (DECL_NAME (cur_arg
))
5389 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
5395 /* In order to pass small structures by value in registers
5396 compatibly with the MIPS compiler, we need to shift the value
5397 into the high part of the register. Function_arg has encoded a
5398 PARALLEL rtx, holding a vector of adjustments to be made as the
5399 next_arg_reg variable, so we split up the insns, and emit them
5402 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
5403 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
5405 rtvec adjust
= XVEC (next_arg_reg
, 0);
5406 int num
= GET_NUM_ELEM (adjust
);
5408 for (i
= 0; i
< num
; i
++)
5410 rtx pattern
= RTVEC_ELT (adjust
, i
);
5411 if (GET_CODE (pattern
) != SET
5412 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
5413 abort_with_insn (pattern
, "Insn is not a shift");
5415 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
5416 emit_insn (pattern
);
5420 tsize
= compute_frame_size (get_frame_size ());
5422 /* If this function is a varargs function, store any registers that
5423 would normally hold arguments ($4 - $7) on the stack. */
5424 if (mips_abi
== ABI_32
5425 && ((TYPE_ARG_TYPES (fntype
) != 0
5426 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
5427 || (arg_name
!= (char *)0
5428 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
5429 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0)))))
5431 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5432 rtx ptr
= stack_pointer_rtx
;
5434 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5435 if (TARGET_ABICALLS
)
5438 for (; regno
<= GP_ARG_LAST
; regno
++)
5441 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
5442 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
5443 gen_rtx (REG
, word_mode
, regno
));
5444 offset
+= UNITS_PER_WORD
;
5450 rtx tsize_rtx
= GEN_INT (tsize
);
5452 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5453 if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
)
5459 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5461 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5462 bit, so make sure that we don't emit anything that can be
5464 /* ??? There is no DImode ori immediate pattern, so we can only
5465 do this for 32 bit code. */
5466 if (large_int (tsize_rtx
) && GET_MODE (tmp_rtx
) == SImode
)
5468 insn
= emit_move_insn (tmp_rtx
,
5469 GEN_INT (tsize
& 0xffff0000));
5470 RTX_FRAME_RELATED_P (insn
) = 1;
5471 insn
= emit_insn (gen_iorsi3 (tmp_rtx
, tmp_rtx
,
5472 GEN_INT (tsize
& 0x0000ffff)));
5473 RTX_FRAME_RELATED_P (insn
) = 1;
5477 insn
= emit_move_insn (tmp_rtx
, tsize_rtx
);
5478 RTX_FRAME_RELATED_P (insn
) = 1;
5481 tsize_rtx
= tmp_rtx
;
5485 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5488 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5491 RTX_FRAME_RELATED_P (insn
) = 1;
5494 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5496 if (frame_pointer_needed
)
5501 insn
= emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
5503 insn
= emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
5505 RTX_FRAME_RELATED_P (insn
) = 1;
5508 if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
)
5509 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0),
5510 gen_rtx (REG
, DImode
, 25)));
5513 /* If we are profiling, make sure no instructions are scheduled before
5514 the call to mcount. */
5516 if (profile_flag
|| profile_block_flag
)
5517 emit_insn (gen_blockage ());
5521 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5523 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5524 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5527 function_epilogue (file
, size
)
5533 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5534 /* Get the function name the same way that toplev.c does before calling
5535 assemble_start_function. This is needed so that the name used here
5536 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5537 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5539 if (!flag_inhibit_size_directive
)
5541 fputs ("\t.end\t", file
);
5542 assemble_name (file
, fnname
);
5549 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5550 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5551 int num_regs
= num_gp_regs
+ num_fp_regs
;
5552 char *name
= fnname
;
5557 dslots_load_total
+= num_regs
;
5560 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5562 (frame_pointer_needed
) ? 'y' : 'n',
5563 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5564 (current_function_calls_alloca
) ? 'y' : 'n',
5565 (current_function_calls_setjmp
) ? 'y' : 'n',
5566 (long)current_frame_info
.total_size
,
5567 (long)current_function_outgoing_args_size
,
5568 num_gp_regs
, num_fp_regs
,
5569 dslots_load_total
, dslots_load_filled
,
5570 dslots_jump_total
, dslots_jump_filled
,
5571 num_refs
[0], num_refs
[1], num_refs
[2]);
5573 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5575 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5576 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5579 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5581 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5582 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5585 fputc ('\n', stderr
);
5588 /* Reset state info for each function. */
5589 inside_function
= FALSE
;
5590 ignore_line_number
= FALSE
;
5591 dslots_load_total
= 0;
5592 dslots_jump_total
= 0;
5593 dslots_load_filled
= 0;
5594 dslots_jump_filled
= 0;
5598 mips_load_reg
= (rtx
)0;
5599 mips_load_reg2
= (rtx
)0;
5600 current_frame_info
= zero_frame_info
;
5602 /* Restore the output file if optimizing the GP (optimizing the GP causes
5603 the text to be diverted to a tempfile, so that data decls come before
5604 references to the data). */
5607 asm_out_file
= asm_out_data_file
;
5611 /* Expand the epilogue into a bunch of separate insns. */
5614 mips_expand_epilogue ()
5616 long tsize
= current_frame_info
.total_size
;
5617 rtx tsize_rtx
= GEN_INT (tsize
);
5618 rtx tmp_rtx
= (rtx
)0;
5620 if (mips_can_use_return_insn ())
5622 emit_insn (gen_return ());
5628 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5629 emit_move_insn (tmp_rtx
, tsize_rtx
);
5630 tsize_rtx
= tmp_rtx
;
5635 if (frame_pointer_needed
)
5637 emit_insn (gen_blockage ());
5639 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5641 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5643 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
5644 are going to restore it, then we must emit a blockage insn to
5645 prevent the scheduler from moving the restore out of the epilogue. */
5646 else if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
5647 && (current_frame_info
.mask
5648 & (1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))))
5649 emit_insn (gen_blockage ());
5651 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5653 emit_insn (gen_blockage ());
5655 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5658 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5662 emit_jump_insn (gen_return_internal ());
5666 /* Return true if this function is known to have a null epilogue.
5667 This allows the optimizer to omit jumps to jumps if no stack
5671 mips_can_use_return_insn ()
5673 if (!reload_completed
)
5676 if (regs_ever_live
[31] || profile_flag
)
5679 if (current_frame_info
.initialized
)
5680 return current_frame_info
.total_size
== 0;
5682 return (compute_frame_size (get_frame_size ())) == 0;
5685 /* Choose the section to use for the constant rtx expression X that has
5688 mips_select_rtx_section (mode
, x
)
5689 enum machine_mode mode
;
5692 if (TARGET_EMBEDDED_DATA
)
5694 /* For embedded applications, always put constants in read-only data,
5695 in order to reduce RAM usage. */
5696 READONLY_DATA_SECTION ();
5700 /* For hosted applications, always put constants in small data if
5701 possible, as this gives the best performance. */
5703 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5704 && mips_section_threshold
> 0)
5705 SMALL_DATA_SECTION ();
5707 READONLY_DATA_SECTION ();
5711 /* Choose the section to use for DECL. RELOC is true if its value contains
5712 any relocatable expression. */
5714 mips_select_section (decl
, reloc
)
5718 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5720 if (TARGET_EMBEDDED_PIC
5721 && TREE_CODE (decl
) == STRING_CST
5722 && !flag_writable_strings
)
5724 /* For embedded position independent code, put constant strings
5725 in the text section, because the data section is limited to
5730 else if (TARGET_EMBEDDED_DATA
)
5732 /* For embedded applications, always put an object in read-only data
5733 if possible, in order to reduce RAM usage. */
5735 if (((TREE_CODE (decl
) == VAR_DECL
5736 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5737 && DECL_INITIAL (decl
)
5738 && (DECL_INITIAL (decl
) == error_mark_node
5739 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5740 /* Deal with calls from output_constant_def_contents. */
5741 || (TREE_CODE (decl
) != VAR_DECL
5742 && (TREE_CODE (decl
) != STRING_CST
5743 || !flag_writable_strings
)))
5744 && ! (flag_pic
&& reloc
))
5745 READONLY_DATA_SECTION ();
5746 else if (size
> 0 && size
<= mips_section_threshold
)
5747 SMALL_DATA_SECTION ();
5753 /* For hosted applications, always put an object in small data if
5754 possible, as this gives the best performance. */
5756 if (size
> 0 && size
<= mips_section_threshold
)
5757 SMALL_DATA_SECTION ();
5758 else if (((TREE_CODE (decl
) == VAR_DECL
5759 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5760 && DECL_INITIAL (decl
)
5761 && (DECL_INITIAL (decl
) == error_mark_node
5762 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5763 /* Deal with calls from output_constant_def_contents. */
5764 || (TREE_CODE (decl
) != VAR_DECL
5765 && (TREE_CODE (decl
) != STRING_CST
5766 || !flag_writable_strings
)))
5767 && ! (flag_pic
&& reloc
))
5768 READONLY_DATA_SECTION ();
5774 #ifdef MIPS_ABI_DEFAULT
5775 /* Support functions for the 64 bit ABI. */
5777 /* Return register to use for a function return value with VALTYPE for function
5781 mips_function_value (valtype
, func
)
5785 int reg
= GP_RETURN
;
5786 enum machine_mode mode
= TYPE_MODE (valtype
);
5787 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5789 /* ??? How should we return complex float? */
5790 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5792 if (TARGET_SINGLE_FLOAT
5793 && (mclass
== MODE_FLOAT
5794 ? GET_MODE_SIZE (mode
) > 4
5795 : GET_MODE_SIZE (mode
) / 2 > 4))
5800 else if (TREE_CODE (valtype
) == RECORD_TYPE
5801 && mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
5803 /* A struct with only one or two floating point fields is returned in
5804 the floating point registers. */
5805 tree field
, fields
[2];
5808 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5809 field
= TREE_CHAIN (field
))
5811 if (TREE_CODE (field
) != FIELD_DECL
)
5813 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5816 fields
[i
++] = field
;
5819 /* Must check i, so that we reject structures with no elements. */
5824 /* The structure has DImode, but we don't allow DImode values
5825 in FP registers, so we use a PARALLEL even though it isn't
5826 strictly necessary. */
5827 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
5829 return gen_rtx (PARALLEL
, mode
,
5831 gen_rtx (EXPR_LIST
, VOIDmode
,
5832 gen_rtx (REG
, field_mode
, FP_RETURN
),
5837 enum machine_mode first_mode
5838 = TYPE_MODE (TREE_TYPE (fields
[0]));
5839 enum machine_mode second_mode
5840 = TYPE_MODE (TREE_TYPE (fields
[1]));
5842 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
5844 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
5846 return gen_rtx (PARALLEL
, mode
,
5848 gen_rtx (EXPR_LIST
, VOIDmode
,
5849 gen_rtx (REG
, first_mode
, FP_RETURN
),
5850 GEN_INT (first_offset
/ BITS_PER_UNIT
)),
5851 gen_rtx (EXPR_LIST
, VOIDmode
,
5852 gen_rtx (REG
, second_mode
, FP_RETURN
+ 2),
5853 GEN_INT (second_offset
/ BITS_PER_UNIT
))));
5858 return gen_rtx (REG
, mode
, reg
);
5861 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
5862 nonzero when an argument must be passed by reference. */
5865 function_arg_pass_by_reference (cum
, mode
, type
, named
)
5866 CUMULATIVE_ARGS
*cum
;
5867 enum machine_mode mode
;
5873 if (mips_abi
!= ABI_EABI
)
5876 /* ??? How should SCmode be handled? */
5877 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
5880 size
= int_size_in_bytes (type
);
5881 return size
== -1 || size
> UNITS_PER_WORD
;
5886 /* This function returns the register class required for a secondary
5887 register when copying between one of the registers in CLASS, and X,
5888 using MODE. If IN_P is nonzero, the copy is going from X to the
5889 register, otherwise the register is the source. A return value of
5890 NO_REGS means that no secondary register is required. */
5893 mips_secondary_reload_class (class, mode
, x
, in_p
)
5894 enum reg_class
class;
5895 enum machine_mode mode
;
5901 if (GET_CODE (x
) == SIGN_EXTEND
)
5907 /* We may be called with reg_renumber NULL from regclass.
5908 ??? This is probably a bug. */
5910 regno
= true_regnum (x
);
5913 while (GET_CODE (x
) == SUBREG
)
5915 off
+= SUBREG_WORD (x
);
5918 if (GET_CODE (x
) == REG
)
5919 regno
= REGNO (x
) + off
;
5922 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5923 regno
= true_regnum (x
);
5925 /* We always require a general register when copying anything to
5926 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
5927 to a general register, or when copying from register 0. */
5928 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
5932 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5936 if (regno
== HILO_REGNUM
)
5940 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5945 /* Copying from HI or LO to anywhere other than a general register
5946 requires a general register. */
5947 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
5949 if (GP_REG_P (regno
))
5953 if (MD_REG_P (regno
))
5955 if (class == GR_REGS
)
5960 /* We can only copy a value to a condition code register from a
5961 floating point register, and even then we require a scratch
5962 floating point register. We can only copy a value out of a
5963 condition code register into a general register. */
5964 if (class == ST_REGS
)
5968 if (GP_REG_P (regno
))
5972 if (ST_REG_P (regno
))
5976 if (class == GR_REGS
)