| blob | fcce3455c3c95f07a3b6b2d2f780b0de5a1ced44 |
1 /* Definitions of target machine for GNU compiler. Sun 68000/68020 version.
2 Copyright (C) 1987, 88, 93-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Note that some other tm.h files include this one and then override
23 many of the definitions that relate to assembler syntax. */
26 /* Names to predefine in the preprocessor for this target machine. */
28 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
30 /* Print subsidiary information on the compiler version in use. */
31 #ifdef MOTOROLA
33 #else
35 #endif
37 /* Define SUPPORT_SUN_FPA to include support for generating code for
38 the Sun Floating Point Accelerator, an optional product for Sun 3
39 machines. By default, it is not defined. Avoid defining it unless
40 you need to output code for the Sun3+FPA architecture, as it has the
41 effect of slowing down the register set operations in hard-reg-set.h
42 (total number of registers will exceed number of bits in a long,
43 if defined, causing the set operations to expand to loops).
44 SUPPORT_SUN_FPA is typically defined in sun3.h. */
46 /* Run-time compilation parameters selecting different hardware subsets. */
50 /* Macros used in the machine description to test the flags. */
52 /* Compile for a 68020 (not a 68000 or 68010). */
53 #define MASK_68020 1
54 #define TARGET_68020 (target_flags & MASK_68020)
56 /* Compile 68881 insns for floating point (not library calls). */
57 #define MASK_68881 2
58 #define TARGET_68881 (target_flags & MASK_68881)
60 /* Compile using 68020 bitfield insns. */
61 #define MASK_BITFIELD 4
62 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
64 /* Compile using rtd insn calling sequence.
65 This will not work unless you use prototypes at least
66 for all functions that can take varying numbers of args. */
67 #define MASK_RTD 8
68 #define TARGET_RTD (target_flags & MASK_RTD)
70 /* Compile passing first two args in regs 0 and 1.
71 This exists only to test compiler features that will
72 be needed for RISC chips. It is not usable
73 and is not intended to be usable on this cpu. */
74 #define MASK_REGPARM 16
75 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
77 /* Compile with 16-bit `int'. */
78 #define MASK_SHORT 32
79 #define TARGET_SHORT (target_flags & MASK_SHORT)
81 /* Compile with special insns for Sun FPA. */
82 #define MASK_FPA 64
83 #define TARGET_FPA (target_flags & MASK_FPA)
85 /* Compile (actually, link) for Sun SKY board. */
86 #define MASK_SKY 128
87 #define TARGET_SKY (target_flags & MASK_SKY)
89 /* Optimize for 68040, but still allow execution on 68020
90 (-m68020-40 or -m68040).
91 The 68040 will execute all 68030 and 68881/2 instructions, but some
92 of them must be emulated in software by the OS. When TARGET_68040 is
93 turned on, these instructions won't be used. This code will still
94 run on a 68030 and 68881/2. */
95 #define MASK_68040 256
96 #define TARGET_68040 (target_flags & MASK_68040)
98 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
99 #define MASK_68040_ONLY 512
100 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
102 /* Optimize for 68060, but still allow execution on 68020
103 (-m68020-60 or -m68060).
104 The 68060 will execute all 68030 and 68881/2 instructions, but some
105 of them must be emulated in software by the OS. When TARGET_68060 is
106 turned on, these instructions won't be used. This code will still
107 run on a 68030 and 68881/2. */
108 #define MASK_68060 1024
109 #define TARGET_68060 (target_flags & MASK_68060)
111 /* Compile for mcf5200 */
112 #define MASK_5200 2048
113 #define TARGET_5200 (target_flags & MASK_5200)
115 /* Align ints to a word boundary. This breaks compatibility with the
116 published ABI's for structures containing ints, but produces faster
117 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
118 It's required for coldfire cpus without a misalignment module. */
119 #define MASK_ALIGN_INT 4096
120 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
122 /* Compile for a CPU32 */
123 /* A 68020 without bitfields is a good heuristic for a CPU32 */
124 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
126 /* Macro to define tables used to set the flags.
127 This is a list in braces of pairs in braces,
128 each pair being { "NAME", VALUE }
129 where VALUE is the bits to set or minus the bits to clear.
130 An empty string NAME is used to identify the default VALUE. */
132 #define TARGET_SWITCHES \
138 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
140 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
164 |MASK_68040_ONLY|MASK_68040)}, \
167 |MASK_68040_ONLY|MASK_68060)}, \
173 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
175 |MASK_BITFIELD)}, \
178 |MASK_BITFIELD)}, \
182 SUBTARGET_SWITCHES \
184 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
186 /* This macro is similar to `TARGET_SWITCHES' but defines names of
187 command options that have values. Its definition is an
188 initializer with a subgrouping for each command option.
190 Each subgrouping contains a string constant, that defines the
191 fixed part of the option name, and the address of a variable. The
192 variable, type `char *', is set to the variable part of the given
193 option if the fixed part matches. The actual option name is made
194 by appending `-m' to the specified name. */
195 #define TARGET_OPTIONS \
199 SUBTARGET_OPTIONS \
200 }
202 /* Sometimes certain combinations of command options do not make
203 sense on a particular target machine. You can define a macro
204 `OVERRIDE_OPTIONS' to take account of this. This macro, if
205 defined, is executed once just after all the command options have
206 been parsed.
208 Don't use this macro to turn on various extra optimizations for
209 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
211 #define OVERRIDE_OPTIONS \
212 { \
213 override_options(); \
214 if (! TARGET_68020 && flag_pic == 2) \
216 SUBTARGET_OVERRIDE_OPTIONS; \
217 }
219 /* These are meant to be redefined in the host dependent files */
220 #define SUBTARGET_SWITCHES
221 #define SUBTARGET_OPTIONS
222 #define SUBTARGET_OVERRIDE_OPTIONS
223 \f
224 /* target machine storage layout */
226 /* Define for XFmode extended real floating point support.
227 This will automatically cause REAL_ARITHMETIC to be defined. */
228 #define LONG_DOUBLE_TYPE_SIZE 96
230 /* Define if you don't want extended real, but do want to use the
231 software floating point emulator for REAL_ARITHMETIC and
232 decimal <-> binary conversion. */
233 /* #define REAL_ARITHMETIC */
235 /* Define this if most significant bit is lowest numbered
236 in instructions that operate on numbered bit-fields.
237 This is true for 68020 insns such as bfins and bfexts.
238 We make it true always by avoiding using the single-bit insns
239 except in special cases with constant bit numbers. */
240 #define BITS_BIG_ENDIAN 1
242 /* Define this if most significant byte of a word is the lowest numbered. */
243 /* That is true on the 68000. */
244 #define BYTES_BIG_ENDIAN 1
246 /* Define this if most significant word of a multiword number is the lowest
247 numbered. */
248 /* For 68000 we can decide arbitrarily
249 since there are no machine instructions for them.
250 So let's be consistent. */
251 #define WORDS_BIG_ENDIAN 1
253 /* number of bits in an addressable storage unit */
254 #define BITS_PER_UNIT 8
256 /* Width in bits of a "word", which is the contents of a machine register.
257 Note that this is not necessarily the width of data type `int';
258 if using 16-bit ints on a 68000, this would still be 32.
259 But on a machine with 16-bit registers, this would be 16. */
260 #define BITS_PER_WORD 32
262 /* Width of a word, in units (bytes). */
263 #define UNITS_PER_WORD 4
265 /* Width in bits of a pointer.
266 See also the macro `Pmode' defined below. */
267 #define POINTER_SIZE 32
269 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
270 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
272 /* Boundary (in *bits*) on which stack pointer should be aligned. */
273 #define STACK_BOUNDARY 16
275 /* Allocation boundary (in *bits*) for the code of a function. */
276 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
278 /* Alignment of field after `int : 0' in a structure. */
279 #define EMPTY_FIELD_BOUNDARY 16
281 /* No data type wants to be aligned rounder than this.
282 Most published ABIs say that ints should be aligned on 16 bit
283 boundaries, but cpus with 32 bit busses get better performance
284 aligned on 32 bit boundaries. Coldfires without a misalignment
285 module require 32 bit alignment. */
286 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
288 /* Set this nonzero if move instructions will actually fail to work
289 when given unaligned data. */
290 #define STRICT_ALIGNMENT 1
292 /* Maximum power of 2 that code can be aligned to. */
295 /* Align loop starts for optimal branching. */
296 #define ASM_OUTPUT_LOOP_ALIGN(FILE) ASM_OUTPUT_ALIGN ((FILE), m68k_align_loops)
298 /* This is how to align an instruction for optimal branching. */
299 #define ASM_OUTPUT_ALIGN_CODE(FILE) ASM_OUTPUT_ALIGN ((FILE), m68k_align_jumps)
301 #define SELECT_RTX_SECTION(MODE, X) \
302 { \
303 if (!flag_pic) \
304 readonly_data_section(); \
305 else if (LEGITIMATE_PIC_OPERAND_P (X)) \
306 readonly_data_section(); \
307 else \
308 data_section(); \
309 }
311 /* Define number of bits in most basic integer type.
312 (If undefined, default is BITS_PER_WORD). */
314 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
316 /* Define these to avoid dependence on meaning of `int'.
317 Note that WCHAR_TYPE_SIZE is used in cexp.y,
318 where TARGET_SHORT is not available. */
321 #define WCHAR_TYPE_SIZE 32
322 \f
323 /* Standard register usage. */
325 /* Number of actual hardware registers.
326 The hardware registers are assigned numbers for the compiler
327 from 0 to just below FIRST_PSEUDO_REGISTER.
328 All registers that the compiler knows about must be given numbers,
329 even those that are not normally considered general registers.
330 For the 68000, we give the data registers numbers 0-7,
331 the address registers numbers 010-017,
332 and the 68881 floating point registers numbers 020-027. */
333 #ifndef SUPPORT_SUN_FPA
334 #define FIRST_PSEUDO_REGISTER 24
335 #else
336 #define FIRST_PSEUDO_REGISTER 56
337 #endif
339 /* This defines the register which is used to hold the offset table for PIC. */
340 #define PIC_OFFSET_TABLE_REGNUM 13
342 /* Used to output a (use pic_offset_table_rtx) so that we
343 always save/restore a5 in functions that use PIC relocation
344 at *any* time during the compilation process. */
345 #define FINALIZE_PIC finalize_pic()
347 #ifndef SUPPORT_SUN_FPA
349 /* 1 for registers that have pervasive standard uses
350 and are not available for the register allocator.
351 On the 68000, only the stack pointer is such. */
353 #define FIXED_REGISTERS \
355 0, 0, 0, 0, 0, 0, 0, 0, \
356 \
358 0, 0, 0, 0, 0, 0, 0, 1, \
359 \
360 /* Floating point registers \
362 0, 0, 0, 0, 0, 0, 0, 0 }
364 /* 1 for registers not available across function calls.
365 These must include the FIXED_REGISTERS and also any
366 registers that can be used without being saved.
367 The latter must include the registers where values are returned
368 and the register where structure-value addresses are passed.
369 Aside from that, you can include as many other registers as you like. */
370 #define CALL_USED_REGISTERS \
371 {1, 1, 0, 0, 0, 0, 0, 0, \
372 1, 1, 0, 0, 0, 0, 0, 1, \
373 1, 1, 0, 0, 0, 0, 0, 0 }
377 /* 1 for registers that have pervasive standard uses
378 and are not available for the register allocator.
379 On the 68000, only the stack pointer is such. */
381 /* fpa0 is also reserved so that it can be used to move data back and
382 forth between high fpa regs and everything else. */
384 #define FIXED_REGISTERS \
386 0, 0, 0, 0, 0, 0, 0, 0, \
387 \
389 0, 0, 0, 0, 0, 0, 0, 1, \
390 \
391 /* Floating point registers \
393 0, 0, 0, 0, 0, 0, 0, 0, \
394 \
396 1, 0, 0, 0, 0, 0, 0, 0, \
397 0, 0, 0, 0, 0, 0, 0, 0, \
398 0, 0, 0, 0, 0, 0, 0, 0, \
399 0, 0, 0, 0, 0, 0, 0, 0 }
401 /* 1 for registers not available across function calls.
402 These must include the FIXED_REGISTERS and also any
403 registers that can be used without being saved.
404 The latter must include the registers where values are returned
405 and the register where structure-value addresses are passed.
406 Aside from that, you can include as many other registers as you like. */
407 #define CALL_USED_REGISTERS \
408 {1, 1, 0, 0, 0, 0, 0, 0, \
409 1, 1, 0, 0, 0, 0, 0, 1, \
410 1, 1, 0, 0, 0, 0, 0, 0, \
412 1, 1, 1, 1, 0, 0, 0, 0, \
413 0, 0, 0, 0, 0, 0, 0, 0, \
414 0, 0, 0, 0, 0, 0, 0, 0, \
415 0, 0, 0, 0, 0, 0, 0, 0 }
420 /* Make sure everything's fine if we *don't* have a given processor.
421 This assumes that putting a register in fixed_regs will keep the
422 compiler's mitts completely off it. We don't bother to zero it out
423 of register classes. If neither TARGET_FPA or TARGET_68881 is set,
424 the compiler won't touch since no instructions that use these
425 registers will be valid. */
427 #ifdef SUPPORT_SUN_FPA
429 #define CONDITIONAL_REGISTER_USAGE \
430 { \
431 int i; \
432 HARD_REG_SET x; \
433 if (!TARGET_FPA) \
434 { \
435 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
436 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
437 if (TEST_HARD_REG_BIT (x, i)) \
438 fixed_regs[i] = call_used_regs[i] = 1; \
439 } \
440 if (TARGET_FPA) \
441 { \
442 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
443 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
444 if (TEST_HARD_REG_BIT (x, i)) \
445 fixed_regs[i] = call_used_regs[i] = 1; \
446 } \
447 }
451 /* Return number of consecutive hard regs needed starting at reg REGNO
452 to hold something of mode MODE.
453 This is ordinarily the length in words of a value of mode MODE
454 but can be less for certain modes in special long registers.
456 On the 68000, ordinary registers hold 32 bits worth;
457 for the 68881 registers, a single register is always enough for
458 anything that can be stored in them at all. */
459 #define HARD_REGNO_NREGS(REGNO, MODE) \
460 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
461 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
463 #ifndef SUPPORT_SUN_FPA
465 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
466 On the 68000, the cpu registers can hold any mode but the 68881 registers
467 can hold only SFmode or DFmode. The 68881 registers can't hold anything
468 if 68881 use is disabled. */
470 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
471 (((REGNO) < 16 \
472 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8)) \
473 || ((REGNO) < 24 \
474 && TARGET_68881 \
475 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
476 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)))
480 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
481 On the 68000, the cpu registers can hold any mode but the 68881 registers
482 can hold only SFmode or DFmode. And the 68881 registers can't hold anything
483 if 68881 use is disabled. However, the Sun FPA register can
484 (apparently) hold whatever you feel like putting in them.
485 If using the fpa, don't put a double in d7/a0. */
487 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
488 (((REGNO) < 16 \
489 && !(TARGET_FPA \
490 && GET_MODE_CLASS ((MODE)) != MODE_INT \
491 && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
492 && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \
493 && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \
494 || ((REGNO) < 24 \
495 ? TARGET_68881 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
496 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
497 : ((REGNO) < 56 ? TARGET_FPA : 0)))
501 /* Value is 1 if it is a good idea to tie two pseudo registers
502 when one has mode MODE1 and one has mode MODE2.
503 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
504 for any hard reg, then this must be 0 for correct output. */
505 #define MODES_TIEABLE_P(MODE1, MODE2) \
506 (! TARGET_68881 \
507 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
508 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
509 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
510 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
512 /* Specify the registers used for certain standard purposes.
513 The values of these macros are register numbers. */
515 /* m68000 pc isn't overloaded on a register. */
516 /* #define PC_REGNUM */
518 /* Register to use for pushing function arguments. */
519 #define STACK_POINTER_REGNUM 15
521 /* Base register for access to local variables of the function. */
522 #define FRAME_POINTER_REGNUM 14
524 /* Value should be nonzero if functions must have frame pointers.
525 Zero means the frame pointer need not be set up (and parms
526 may be accessed via the stack pointer) in functions that seem suitable.
527 This is computed in `reload', in reload1.c. */
528 #define FRAME_POINTER_REQUIRED 0
530 /* Base register for access to arguments of the function. */
531 #define ARG_POINTER_REGNUM 14
533 /* Register in which static-chain is passed to a function. */
534 #define STATIC_CHAIN_REGNUM 8
536 /* Register in which address to store a structure value
537 is passed to a function. */
538 #define STRUCT_VALUE_REGNUM 9
539 \f
540 /* Define the classes of registers for register constraints in the
541 machine description. Also define ranges of constants.
543 One of the classes must always be named ALL_REGS and include all hard regs.
544 If there is more than one class, another class must be named NO_REGS
545 and contain no registers.
547 The name GENERAL_REGS must be the name of a class (or an alias for
548 another name such as ALL_REGS). This is the class of registers
549 that is allowed by "g" or "r" in a register constraint.
550 Also, registers outside this class are allocated only when
551 instructions express preferences for them.
553 The classes must be numbered in nondecreasing order; that is,
554 a larger-numbered class must never be contained completely
555 in a smaller-numbered class.
557 For any two classes, it is very desirable that there be another
558 class that represents their union. */
560 /* The 68000 has three kinds of registers, so eight classes would be
561 a complete set. One of them is not needed. */
563 #ifndef SUPPORT_SUN_FPA
570 LIM_REG_CLASSES };
572 #define N_REG_CLASSES (int) LIM_REG_CLASSES
574 /* Give names of register classes as strings for dump file. */
576 #define REG_CLASS_NAMES \
582 /* Define which registers fit in which classes.
583 This is an initializer for a vector of HARD_REG_SET
584 of length N_REG_CLASSES. */
586 #define REG_CLASS_CONTENTS \
587 { \
596 }
598 /* The same information, inverted:
599 Return the class number of the smallest class containing
600 reg number REGNO. This could be a conditional expression
601 or could index an array. */
603 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
607 /*
608 * Notes on final choices:
609 *
610 * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
611 * else.
612 * 2) Removed all unions that involve address registers with
613 * floating point registers (left in unions of address and data with
614 * floating point).
615 * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
616 * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
617 * 4) Left in everything else.
618 */
623 LIM_REG_CLASSES };
625 #define N_REG_CLASSES (int) LIM_REG_CLASSES
627 /* Give names of register classes as strings for dump file. */
629 #define REG_CLASS_NAMES \
635 /* Define which registers fit in which classes.
636 This is an initializer for a vector of HARD_REG_SET
637 of length N_REG_CLASSES. */
639 #define REG_CLASS_CONTENTS \
640 { \
655 }
657 /* The same information, inverted:
658 Return the class number of the smallest class containing
659 reg number REGNO. This could be a conditional expression
660 or could index an array. */
663 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
667 /* The class value for index registers, and the one for base regs. */
669 #define INDEX_REG_CLASS GENERAL_REGS
670 #define BASE_REG_CLASS ADDR_REGS
672 /* Get reg_class from a letter such as appears in the machine description.
673 We do a trick here to modify the effective constraints on the
674 machine description; we zorch the constraint letters that aren't
675 appropriate for a specific target. This allows us to guarantee
676 that a specific kind of register will not be used for a given target
677 without fiddling with the register classes above. */
679 #ifndef SUPPORT_SUN_FPA
681 #define REG_CLASS_FROM_LETTER(C) \
685 NO_REGS) : \
686 NO_REGS)))
690 #define REG_CLASS_FROM_LETTER(C) \
694 NO_REGS) : \
696 NO_REGS) : \
698 NO_REGS) : \
699 NO_REGS)))))
703 /* The letters I, J, K, L and M in a register constraint string
704 can be used to stand for particular ranges of immediate operands.
705 This macro defines what the ranges are.
706 C is the letter, and VALUE is a constant value.
707 Return 1 if VALUE is in the range specified by C.
709 For the 68000, `I' is used for the range 1 to 8
710 allowed as immediate shift counts and in addq.
711 `J' is used for the range of signed numbers that fit in 16 bits.
712 `K' is for numbers that moveq can't handle.
713 `L' is for range -8 to -1, range of values that can be added with subq.
714 `M' is for numbers that moveq+notb can't handle.
715 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
716 'O' is for 16 (for rotate using swap).
717 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
719 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
729 /*
730 * A small bit of explanation:
731 * "G" defines all of the floating constants that are *NOT* 68881
732 * constants. this is so 68881 constants get reloaded and the
733 * fpmovecr is used. "H" defines *only* the class of constants that
734 * the fpa can use, because these can be gotten at in any fpa
735 * instruction and there is no need to force reloads.
736 */
737 #ifndef SUPPORT_SUN_FPA
738 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
741 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
746 /* A C expression that defines the optional machine-dependent constraint
747 letters that can be used to segregate specific types of operands,
748 usually memory references, for the target machine. It should return 1 if
749 VALUE corresponds to the operand type represented by the constraint letter
750 C. If C is not defined as an extra constraint, the value returned should
751 be 0 regardless of VALUE. */
753 /* For the m68k, `Q' means address register indirect addressing mode. */
755 #define EXTRA_CONSTRAINT(OP, C) \
757 0 )
759 /* Given an rtx X being reloaded into a reg required to be
760 in class CLASS, return the class of reg to actually use.
761 In general this is just CLASS; but on some machines
762 in some cases it is preferable to use a more restrictive class.
763 On the 68000 series, use a data reg if possible when the
764 value is a constant in the range where moveq could be used
765 and we ensure that QImodes are reloaded into data regs.
766 Also, if a floating constant needs reloading, put it in memory.
767 Don't do this for !G constants, since all patterns in the md file
768 expect them to be loaded into a register via fpmovecr. See above. */
770 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
771 ((GET_CODE (X) == CONST_INT \
772 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
773 && (CLASS) != ADDR_REGS) \
774 ? DATA_REGS \
775 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
776 ? DATA_REGS \
777 : (GET_CODE (X) == CONST_DOUBLE \
778 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
780 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
781 ? FP_REGS : NO_REGS) \
782 : (CLASS))
784 /* Force QImode output reloads from subregs to be allocated to data regs,
785 since QImode stores from address regs are not supported. We make the
786 assumption that if the class is not ADDR_REGS, then it must be a superset
787 of DATA_REGS. */
789 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
790 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
791 ? DATA_REGS \
792 : (CLASS))
794 /* Return the maximum number of consecutive registers
795 needed to represent mode MODE in a register of class CLASS. */
796 /* On the 68000, this is the size of MODE in words,
797 except in the FP regs, where a single reg is always enough. */
798 #ifndef SUPPORT_SUN_FPA
800 #define CLASS_MAX_NREGS(CLASS, MODE) \
801 ((CLASS) == FP_REGS ? 1 \
802 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
804 /* Moves between fp regs and other regs are two insns. */
805 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
806 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
807 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
808 ? 4 : 2)
812 #define CLASS_MAX_NREGS(CLASS, MODE) \
813 ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
814 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
816 /* Moves between fp regs and other regs are two insns. */
817 /* Likewise for high fpa regs and other regs. */
818 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
819 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
820 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
821 || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \
822 || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \
823 ? 4 : 2)
826 \f
827 /* Stack layout; function entry, exit and calling. */
829 /* Define this if pushing a word on the stack
830 makes the stack pointer a smaller address. */
831 #define STACK_GROWS_DOWNWARD
833 /* Nonzero if we need to generate stack-probe insns.
834 On most systems they are not needed.
835 When they are needed, define this as the stack offset to probe at. */
836 #define NEED_PROBE 0
838 /* Define this if the nominal address of the stack frame
839 is at the high-address end of the local variables;
840 that is, each additional local variable allocated
841 goes at a more negative offset in the frame. */
842 #define FRAME_GROWS_DOWNWARD
844 /* Offset within stack frame to start allocating local variables at.
845 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
846 first local allocated. Otherwise, it is the offset to the BEGINNING
847 of the first local allocated. */
848 #define STARTING_FRAME_OFFSET 0
850 /* If we generate an insn to push BYTES bytes,
851 this says how many the stack pointer really advances by.
852 On the 68000, sp@- in a byte insn really pushes a word.
853 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
854 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
856 /* Offset of first parameter from the argument pointer register value. */
857 #define FIRST_PARM_OFFSET(FNDECL) 8
859 /* Value is the number of byte of arguments automatically
860 popped when returning from a subroutine call.
861 FUNDECL is the declaration node of the function (as a tree),
862 FUNTYPE is the data type of the function (as a tree),
863 or for a library call it is an identifier node for the subroutine name.
864 SIZE is the number of bytes of arguments passed on the stack.
866 On the 68000, the RTS insn cannot pop anything.
867 On the 68010, the RTD insn may be used to pop them if the number
868 of args is fixed, but if the number is variable then the caller
869 must pop them all. RTD can't be used for library calls now
870 because the library is compiled with the Unix compiler.
871 Use of RTD is a selectable option, since it is incompatible with
872 standard Unix calling sequences. If the option is not selected,
873 the caller must always pop the args. */
875 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
876 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
877 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
878 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
879 == void_type_node))) \
880 ? (SIZE) : 0)
882 /* Define how to find the value returned by a function.
883 VALTYPE is the data type of the value (as a tree).
884 If the precise function being called is known, FUNC is its FUNCTION_DECL;
885 otherwise, FUNC is 0. */
887 /* On the 68000 the return value is in D0 regardless. */
889 #define FUNCTION_VALUE(VALTYPE, FUNC) \
890 gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
892 /* Define how to find the value returned by a library function
893 assuming the value has mode MODE. */
895 /* On the 68000 the return value is in D0 regardless. */
897 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
899 /* 1 if N is a possible register number for a function value.
900 On the 68000, d0 is the only register thus used. */
902 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
904 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
905 more than one register. */
907 #define NEEDS_UNTYPED_CALL 0
909 /* Define this if PCC uses the nonreentrant convention for returning
910 structure and union values. */
912 #define PCC_STATIC_STRUCT_RETURN
914 /* 1 if N is a possible register number for function argument passing.
915 On the 68000, no registers are used in this way. */
917 #define FUNCTION_ARG_REGNO_P(N) 0
918 \f
919 /* Define a data type for recording info about an argument list
920 during the scan of that argument list. This data type should
921 hold all necessary information about the function itself
922 and about the args processed so far, enough to enable macros
923 such as FUNCTION_ARG to determine where the next arg should go.
925 On the m68k, this is a single integer, which is a number of bytes
926 of arguments scanned so far. */
928 #define CUMULATIVE_ARGS int
930 /* Initialize a variable CUM of type CUMULATIVE_ARGS
931 for a call to a function whose data type is FNTYPE.
932 For a library call, FNTYPE is 0.
934 On the m68k, the offset starts at 0. */
936 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
937 ((CUM) = 0)
939 /* Update the data in CUM to advance over an argument
940 of mode MODE and data type TYPE.
941 (TYPE is null for libcalls where that information may not be available.) */
943 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
944 ((CUM) += ((MODE) != BLKmode \
945 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
946 : (int_size_in_bytes (TYPE) + 3) & ~3))
948 /* Define where to put the arguments to a function.
949 Value is zero to push the argument on the stack,
950 or a hard register in which to store the argument.
952 MODE is the argument's machine mode.
953 TYPE is the data type of the argument (as a tree).
954 This is null for libcalls where that information may
955 not be available.
956 CUM is a variable of type CUMULATIVE_ARGS which gives info about
957 the preceding args and about the function being called.
958 NAMED is nonzero if this argument is a named parameter
959 (otherwise it is an extra parameter matching an ellipsis). */
961 /* On the 68000 all args are pushed, except if -mregparm is specified
962 then the first two words of arguments are passed in d0, d1.
963 *NOTE* -mregparm does not work.
964 It exists only to test register calling conventions. */
966 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
967 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
969 /* For an arg passed partly in registers and partly in memory,
970 this is the number of registers used.
971 For args passed entirely in registers or entirely in memory, zero. */
973 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
974 ((TARGET_REGPARM && (CUM) < 8 \
975 && 8 < ((CUM) + ((MODE) == BLKmode \
976 ? int_size_in_bytes (TYPE) \
977 : GET_MODE_SIZE (MODE)))) \
978 ? 2 - (CUM) / 4 : 0)
980 /* Generate the assembly code for function entry. */
981 #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE)
983 /* Output assembler code to FILE to increment profiler label # LABELNO
984 for profiling a function entry. */
986 #define FUNCTION_PROFILER(FILE, LABELNO) \
989 /* Output assembler code to FILE to initialize this source file's
990 basic block profiling info, if that has not already been done. */
992 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
993 do \
994 { \
995 switch (profile_block_flag) \
996 { \
997 case 2: \
998 asm_fprintf (FILE, "\tpea %d\n\tpea %LLPBX0\n\tjsr %U__bb_init_trace_func\n\taddql %I8,%Rsp\n", \
999 (BLOCK_OR_LABEL)); \
1000 break; \
1001 \
1002 default: \
1003 asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \
1004 (BLOCK_OR_LABEL), (BLOCK_OR_LABEL)); \
1005 break; \
1006 } \
1007 } \
1008 while(0)
1010 /* Output assembler code to FILE to increment the counter for
1011 the BLOCKNO'th basic block in this source file. */
1013 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1014 do \
1015 { \
1016 switch (profile_block_flag) \
1017 { \
1018 case 2: \
1019 asm_fprintf (FILE, "\tmovel %Ra1,%Rsp@-\n\tlea ___bb,%Ra1\n\tmovel %I%d,%Ra1@(0)\n\tmovel %I%LLPBX0,%Ra1@(4)\n\tmovel %Rsp@+,%Ra1\n\tjsr %U__bb_trace_func\n", \
1020 BLOCKNO); \
1021 break; \
1022 \
1023 default: \
1025 break; \
1026 } \
1027 } \
1028 while(0)
1030 /* Output assembler code to FILE to indicate return from
1031 a function during basic block profiling. */
1033 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1036 /* Save all registers which may be clobbered by a function call.
1037 MACHINE_STATE_SAVE and MACHINE_STATE_RESTORE are target-code macros,
1038 used in libgcc2.c. They may not refer to TARGET_* macros !!! */
1039 #if defined (__mc68010__) || defined(mc68010) \
1040 || defined(__mc68020__) || defined(mc68020) \
1041 || defined(__mc68030__) || defined(mc68030) \
1042 || defined(__mc68040__) || defined(mc68040) \
1043 || defined(__mc68332__) || defined(mc68332)
1044 #define MACHINE_STATE_m68010_up
1045 #endif
1047 #ifdef MOTOROLA
1048 #if defined(__mcf5200__)
1049 #define MACHINE_STATE_SAVE(id) \
1050 { \
1055 }
1057 #if defined(MACHINE_STATE_m68010_up)
1058 #ifdef __HPUX_ASM__
1059 /* HPUX assembler does not accept %ccr. */
1060 #define MACHINE_STATE_SAVE(id) \
1061 { \
1064 }
1066 #define MACHINE_STATE_SAVE(id) \
1067 { \
1070 }
1073 #define MACHINE_STATE_SAVE(id) \
1074 { \
1077 }
1081 #if defined(__mcf5200__)
1082 #define MACHINE_STATE_SAVE(id) \
1083 { \
1088 }
1090 #if defined(MACHINE_STATE_m68010_up)
1091 #define MACHINE_STATE_SAVE(id) \
1092 { \
1095 }
1097 #define MACHINE_STATE_SAVE(id) \
1098 { \
1101 }
1106 /* Restore all registers saved by MACHINE_STATE_SAVE. */
1108 #ifdef MOTOROLA
1109 #if defined(__mcf5200__)
1110 #define MACHINE_STATE_RESTORE(id) \
1111 { \
1116 }
1118 #ifdef __HPUX_ASM__
1119 /* HPUX assembler does not accept %ccr. */
1120 #define MACHINE_STATE_RESTORE(id) \
1121 { \
1124 }
1126 #define MACHINE_STATE_RESTORE(id) \
1127 { \
1130 }
1134 #if defined(__mcf5200__)
1135 #define MACHINE_STATE_RESTORE(id) \
1136 { \
1141 }
1143 #define MACHINE_STATE_RESTORE(id) \
1144 { \
1147 }
1151 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1152 the stack pointer does not matter. The value is tested only in
1153 functions that have frame pointers.
1154 No definition is equivalent to always zero. */
1156 #define EXIT_IGNORE_STACK 1
1158 /* Generate the assembly code for function exit. */
1159 #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE)
1161 /* This is a hook for other tm files to change. */
1162 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
1164 /* Determine if the epilogue should be output as RTL.
1165 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1166 #define USE_RETURN_INSN use_return_insn ()
1168 /* Store in the variable DEPTH the initial difference between the
1169 frame pointer reg contents and the stack pointer reg contents,
1170 as of the start of the function body. This depends on the layout
1171 of the fixed parts of the stack frame and on how registers are saved.
1173 On the 68k, if we have a frame, we must add one word to its length
1174 to allow for the place that a6 is stored when we do have a frame pointer.
1175 Otherwise, we would need to compute the offset from the frame pointer
1176 of a local variable as a function of frame_pointer_needed, which
1177 is hard. */
1179 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1180 { int regno; \
1181 int offset = -4; \
1182 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
1183 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1184 offset += 12; \
1185 for (regno = 0; regno < 16; regno++) \
1186 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1187 offset += 4; \
1188 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
1189 + (get_frame_size () == 0 ? 0 : 4)); \
1190 }
1192 /* Output assembler code for a block containing the constant parts
1193 of a trampoline, leaving space for the variable parts. */
1195 /* On the 68k, the trampoline looks like this:
1196 movl #STATIC,a0
1197 jmp FUNCTION
1199 WARNING: Targets that may run on 68040+ cpus must arrange for
1200 the instruction cache to be flushed. Previous incarnations of
1201 the m68k trampoline code attempted to get around this by either
1202 using an out-of-line transfer function or pc-relative data, but
1203 the fact remains that the code to jump to the transfer function
1204 or the code to load the pc-relative data needs to be flushed
1205 just as much as the "variable" portion of the trampoline.
1206 Recognizing that a cache flush is going to be required anyway,
1207 dispense with such notions and build a smaller trampoline. */
1209 /* Since more instructions are required to move a template into
1210 place than to create it on the spot, don't use a template. */
1212 /* Length in units of the trampoline for entering a nested function. */
1214 #define TRAMPOLINE_SIZE 12
1216 /* Alignment required for a trampoline in bits. */
1218 #define TRAMPOLINE_ALIGNMENT 16
1220 /* Targets redefine this to invoke code to either flush the cache,
1221 or enable stack execution (or both). */
1223 #ifndef FINALIZE_TRAMPOLINE
1224 #define FINALIZE_TRAMPOLINE(TRAMP)
1225 #endif
1227 /* Emit RTL insns to initialize the variable parts of a trampoline.
1228 FNADDR is an RTX for the address of the function's pure code.
1229 CXT is an RTX for the static chain value for the function.
1231 We generate a two-instructions program at address TRAMP :
1232 movea.l &CXT,%a0
1233 jmp FNADDR */
1235 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1236 { \
1237 emit_move_insn (gen_rtx (MEM, HImode, TRAMP), GEN_INT(0x207C)); \
1238 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), CXT); \
1239 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 6)), \
1240 GEN_INT(0x4EF9)); \
1241 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), FNADDR); \
1242 FINALIZE_TRAMPOLINE(TRAMP); \
1243 }
1245 /* This is the library routine that is used
1246 to transfer control from the trampoline
1247 to the actual nested function.
1248 It is defined for backward compatibility,
1249 for linking with object code that used the old
1250 trampoline definition. */
1252 /* A colon is used with no explicit operands
1253 to cause the template string to be scanned for %-constructs. */
1254 /* The function name __transfer_from_trampoline is not actually used.
1255 The function definition just permits use of "asm with operands"
1256 (though the operand list is empty). */
1257 #define TRANSFER_FROM_TRAMPOLINE \
1258 void \
1259 __transfer_from_trampoline () \
1260 { \
1267 }
1268 \f
1269 /* Addressing modes, and classification of registers for them. */
1271 #define HAVE_POST_INCREMENT
1272 /* #define HAVE_POST_DECREMENT */
1274 #define HAVE_PRE_DECREMENT
1275 /* #define HAVE_PRE_INCREMENT */
1277 /* Macros to check register numbers against specific register classes. */
1279 /* These assume that REGNO is a hard or pseudo reg number.
1280 They give nonzero only if REGNO is a hard reg of the suitable class
1281 or a pseudo reg currently allocated to a suitable hard reg.
1282 Since they use reg_renumber, they are safe only once reg_renumber
1283 has been allocated, which happens in local-alloc.c. */
1285 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1286 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1287 #define REGNO_OK_FOR_BASE_P(REGNO) \
1288 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1289 #define REGNO_OK_FOR_DATA_P(REGNO) \
1290 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1291 #define REGNO_OK_FOR_FP_P(REGNO) \
1292 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1293 #ifdef SUPPORT_SUN_FPA
1294 #define REGNO_OK_FOR_FPA_P(REGNO) \
1295 (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
1296 #endif
1298 /* Now macros that check whether X is a register and also,
1299 strictly, whether it is in a specified class.
1301 These macros are specific to the 68000, and may be used only
1302 in code for printing assembler insns and in conditions for
1303 define_optimization. */
1305 /* 1 if X is a data register. */
1307 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1309 /* 1 if X is an fp register. */
1311 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1313 /* 1 if X is an address register */
1315 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1317 #ifdef SUPPORT_SUN_FPA
1318 /* 1 if X is a register in the Sun FPA. */
1319 #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
1320 #else
1321 /* Answer must be no if we don't have an FPA. */
1322 #define FPA_REG_P(X) 0
1323 #endif
1324 \f
1325 /* Maximum number of registers that can appear in a valid memory address. */
1327 #define MAX_REGS_PER_ADDRESS 2
1329 /* Recognize any constant value that is a valid address. */
1331 #define CONSTANT_ADDRESS_P(X) \
1332 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1333 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1334 || GET_CODE (X) == HIGH)
1336 /* Nonzero if the constant value X is a legitimate general operand.
1337 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1339 #define LEGITIMATE_CONSTANT_P(X) 1
1341 /* Nonzero if the constant value X is a legitimate general operand
1342 when generating PIC code. It is given that flag_pic is on and
1343 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1345 #define LEGITIMATE_PIC_OPERAND_P(X) \
1346 ((! symbolic_operand (X, VOIDmode) \
1347 && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X) \
1348 && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM \
1349 && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), \
1350 VOIDmode))) \
1351 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)))
1353 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1354 and check its validity for a certain class.
1355 We have two alternate definitions for each of them.
1356 The usual definition accepts all pseudo regs; the other rejects
1357 them unless they have been allocated suitable hard regs.
1358 The symbol REG_OK_STRICT causes the latter definition to be used.
1360 Most source files want to accept pseudo regs in the hope that
1361 they will get allocated to the class that the insn wants them to be in.
1362 Source files for reload pass need to be strict.
1363 After reload, it makes no difference, since pseudo regs have
1364 been eliminated by then. */
1366 #ifndef REG_OK_STRICT
1368 /* Nonzero if X is a hard reg that can be used as an index
1369 or if it is a pseudo reg. */
1370 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1371 /* Nonzero if X is a hard reg that can be used as a base reg
1372 or if it is a pseudo reg. */
1373 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1375 #else
1377 /* Nonzero if X is a hard reg that can be used as an index. */
1378 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1379 /* Nonzero if X is a hard reg that can be used as a base reg. */
1380 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1382 #endif
1383 \f
1384 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1385 that is a valid memory address for an instruction.
1386 The MODE argument is the machine mode for the MEM expression
1387 that wants to use this address.
1389 When generating PIC, an address involving a SYMBOL_REF is legitimate
1390 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1391 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1392 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1394 Likewise for a LABEL_REF when generating PIC.
1396 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1398 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1399 also makes function inlining work when inline functions are called with
1400 arguments that are SUBREGs. */
1402 #define LEGITIMATE_BASE_REG_P(X) \
1403 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1404 || (GET_CODE (X) == SUBREG \
1405 && GET_CODE (SUBREG_REG (X)) == REG \
1406 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1408 #define INDIRECTABLE_1_ADDRESS_P(X) \
1409 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1410 || LEGITIMATE_BASE_REG_P (X) \
1411 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1412 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1413 || (GET_CODE (X) == PLUS \
1414 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1415 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1416 && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000) \
1417 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1418 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1419 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1420 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) \
1422 #if 0
1423 /* This should replace the last two (non-pic) lines
1424 except that Sun's assembler does not seem to handle such operands. */
1428 #endif
1431 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1432 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1434 /* Only labels on dispatch tables are valid for indexing from. */
1435 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1436 { rtx temp; \
1437 if (GET_CODE (X) == LABEL_REF \
1438 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1439 && GET_CODE (temp) == JUMP_INSN \
1440 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1441 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1442 goto ADDR; \
1443 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1445 #define GO_IF_INDEXING(X, ADDR) \
1446 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1447 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1448 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1449 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1451 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1452 { GO_IF_INDEXING (X, ADDR); \
1453 if (GET_CODE (X) == PLUS) \
1454 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1455 && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \
1456 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1457 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1458 && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \
1459 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1461 #define LEGITIMATE_INDEX_REG_P(X) \
1462 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1463 || (GET_CODE (X) == SIGN_EXTEND \
1464 && GET_CODE (XEXP (X, 0)) == REG \
1465 && GET_MODE (XEXP (X, 0)) == HImode \
1466 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1467 || (GET_CODE (X) == SUBREG \
1468 && GET_CODE (SUBREG_REG (X)) == REG \
1469 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1471 #define LEGITIMATE_INDEX_P(X) \
1472 (LEGITIMATE_INDEX_REG_P (X) \
1473 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1474 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1475 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1476 && (INTVAL (XEXP (X, 1)) == 2 \
1477 || INTVAL (XEXP (X, 1)) == 4 \
1478 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1480 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1481 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1482 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1483 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1484 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1485 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1486 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1487 goto ADDR; }
1489 /* Don't call memory_address_noforce for the address to fetch
1490 the switch offset. This address is ok as it stands (see above),
1491 but memory_address_noforce would alter it. */
1492 #define PIC_CASE_VECTOR_ADDRESS(index) index
1493 \f
1494 /* Try machine-dependent ways of modifying an illegitimate address
1495 to be legitimate. If we find one, return the new, valid address.
1496 This macro is used in only one place: `memory_address' in explow.c.
1498 OLDX is the address as it was before break_out_memory_refs was called.
1499 In some cases it is useful to look at this to decide what needs to be done.
1501 MODE and WIN are passed so that this macro can use
1502 GO_IF_LEGITIMATE_ADDRESS.
1504 It is always safe for this macro to do nothing. It exists to recognize
1505 opportunities to optimize the output.
1507 For the 68000, we handle X+REG by loading X into a register R and
1508 using R+REG. R will go in an address reg and indexing will be used.
1509 However, if REG is a broken-out memory address or multiplication,
1510 nothing needs to be done because REG can certainly go in an address reg. */
1512 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1513 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1514 { register int ch = (X) != (OLDX); \
1515 if (GET_CODE (X) == PLUS) \
1516 { int copied = 0; \
1517 if (GET_CODE (XEXP (X, 0)) == MULT) \
1518 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1519 if (GET_CODE (XEXP (X, 1)) == MULT) \
1520 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1521 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1522 && GET_CODE (XEXP (X, 0)) == REG) \
1523 goto WIN; \
1524 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1525 if (GET_CODE (XEXP (X, 0)) == REG \
1526 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1527 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1528 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1529 { register rtx temp = gen_reg_rtx (Pmode); \
1530 register rtx val = force_operand (XEXP (X, 1), 0); \
1531 emit_move_insn (temp, val); \
1532 COPY_ONCE (X); \
1533 XEXP (X, 1) = temp; \
1534 goto WIN; } \
1535 else if (GET_CODE (XEXP (X, 1)) == REG \
1536 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1537 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1538 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1539 { register rtx temp = gen_reg_rtx (Pmode); \
1540 register rtx val = force_operand (XEXP (X, 0), 0); \
1541 emit_move_insn (temp, val); \
1542 COPY_ONCE (X); \
1543 XEXP (X, 0) = temp; \
1544 goto WIN; }}}
1546 /* Go to LABEL if ADDR (a legitimate address expression)
1547 has an effect that depends on the machine mode it is used for.
1548 On the 68000, only predecrement and postincrement address depend thus
1549 (the amount of decrement or increment being the length of the operand). */
1551 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1552 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1553 \f
1554 /* Specify the machine mode that this machine uses
1555 for the index in the tablejump instruction. */
1556 #define CASE_VECTOR_MODE HImode
1558 /* Define this if the tablejump instruction expects the table
1559 to contain offsets from the address of the table.
1560 Do not define this if the table should contain absolute addresses. */
1561 #define CASE_VECTOR_PC_RELATIVE
1563 /* Specify the tree operation to be used to convert reals to integers. */
1564 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1566 /* This is the kind of divide that is easiest to do in the general case. */
1567 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1569 /* Define this as 1 if `char' should by default be signed; else as 0. */
1570 #define DEFAULT_SIGNED_CHAR 1
1572 /* Don't cse the address of the function being compiled. */
1573 #define NO_RECURSIVE_FUNCTION_CSE
1575 /* Max number of bytes we can move from memory to memory
1576 in one reasonably fast instruction. */
1577 #define MOVE_MAX 4
1579 /* Define this if zero-extension is slow (more than one real instruction). */
1580 #define SLOW_ZERO_EXTEND
1582 /* Nonzero if access to memory by bytes is slow and undesirable. */
1583 #define SLOW_BYTE_ACCESS 0
1585 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1586 is done just by pretending it is already truncated. */
1587 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1589 /* We assume that the store-condition-codes instructions store 0 for false
1590 and some other value for true. This is the value stored for true. */
1592 #define STORE_FLAG_VALUE -1
1594 /* When a prototype says `char' or `short', really pass an `int'. */
1595 #define PROMOTE_PROTOTYPES
1597 /* Specify the machine mode that pointers have.
1598 After generation of rtl, the compiler makes no further distinction
1599 between pointers and any other objects of this machine mode. */
1600 #define Pmode SImode
1602 /* A function address in a call instruction
1603 is a byte address (for indexing purposes)
1604 so give the MEM rtx a byte's mode. */
1605 #define FUNCTION_MODE QImode
1607 /* Compute the cost of computing a constant rtl expression RTX
1608 whose rtx-code is CODE. The body of this macro is a portion
1609 of a switch statement. If the code is computed here,
1610 return it with a return statement. Otherwise, break from the switch. */
1612 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1613 case CONST_INT: \
1615 if (RTX == const0_rtx) return 0; \
1617 return const_int_cost(RTX); \
1618 case CONST: \
1619 case LABEL_REF: \
1620 case SYMBOL_REF: \
1621 return 3; \
1622 case CONST_DOUBLE: \
1623 return 5;
1625 /* Compute the cost of various arithmetic operations.
1626 These are vaguely right for a 68020. */
1627 /* The costs for long multiply have been adjusted to
1628 work properly in synth_mult on the 68020,
1629 relative to an average of the time for add and the time for shift,
1630 taking away a little more because sometimes move insns are needed. */
1631 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1632 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
1633 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
1634 #define DIVW_COST (TARGET_68020 ? 27 : 12)
1636 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1637 case PLUS: \
1639 if (GET_MODE (X) == SImode \
1640 && GET_CODE (XEXP (X, 1)) == REG \
1641 && GET_CODE (XEXP (X, 0)) == MULT \
1642 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1643 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1644 && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \
1645 || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \
1646 || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \
1648 break; \
1649 case ASHIFT: \
1650 case ASHIFTRT: \
1651 case LSHIFTRT: \
1652 if (TARGET_68060) \
1653 return COSTS_N_INSNS(1); \
1654 if (! TARGET_68020) \
1655 { \
1656 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1657 { \
1658 if (INTVAL (XEXP (X, 1)) < 16) \
1659 return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \
1660 else \
1662 return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \
1663 } \
1665 } \
1667 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1668 && (INTVAL (XEXP (X, 1)) == 16)) \
1670 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1671 && !(INTVAL (XEXP (X, 1)) > 0 \
1672 && INTVAL (XEXP (X, 1)) <= 8)) \
1674 break; \
1675 case MULT: \
1676 if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \
1677 || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \
1678 && GET_MODE (X) == SImode) \
1679 return COSTS_N_INSNS (MULW_COST); \
1680 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1681 return COSTS_N_INSNS (MULW_COST); \
1682 else \
1683 return COSTS_N_INSNS (MULL_COST); \
1684 case DIV: \
1685 case UDIV: \
1686 case MOD: \
1687 case UMOD: \
1688 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1691 \f
1692 /* Tell final.c how to eliminate redundant test instructions. */
1694 /* Here we define machine-dependent flags and fields in cc_status
1695 (see `conditions.h'). */
1697 /* Set if the cc value is actually in the 68881, so a floating point
1698 conditional branch must be output. */
1699 #define CC_IN_68881 04000
1701 /* Store in cc_status the expressions that the condition codes will
1702 describe after execution of an instruction whose pattern is EXP.
1703 Do not alter them if the instruction would not alter the cc's. */
1705 /* On the 68000, all the insns to store in an address register fail to
1706 set the cc's. However, in some cases these instructions can make it
1707 possibly invalid to use the saved cc's. In those cases we clear out
1708 some or all of the saved cc's so they won't be used. */
1710 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1712 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1713 { if (cc_prev_status.flags & CC_IN_68881) \
1714 return FLOAT; \
1715 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1716 return NO_OV; \
1717 return NORMAL; }
1718 \f
1719 /* Control the assembler format that we output. */
1721 /* Output at beginning of assembler file. */
1723 #define ASM_FILE_START(FILE) \
1726 /* Output to assembler file text saying following lines
1727 may contain character constants, extra white space, comments, etc. */
1731 /* Output to assembler file text saying following lines
1732 no longer contain unusual constructs. */
1736 /* Output before read-only data. */
1740 /* Output before writable data. */
1744 /* Here are four prefixes that are used by asm_fprintf to
1745 facilitate customization for alternate assembler syntaxes.
1746 Machines with no likelihood of an alternate syntax need not
1747 define these and need not use asm_fprintf. */
1749 /* The prefix for register names. Note that REGISTER_NAMES
1750 is supposed to include this prefix. */
1754 /* The prefix for local labels. You should be able to define this as
1755 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1756 without having to make any other changes to account for the specific
1757 definition. Note it is a string literal, not interpreted by printf
1758 and friends. */
1762 /* The prefix to add to user-visible assembler symbols. */
1766 /* The prefix for immediate operands. */
1770 /* How to refer to registers in assembler output.
1771 This sequence is indexed by compiler's hard-register-number (see above). */
1773 #ifndef SUPPORT_SUN_FPA
1775 #define REGISTER_NAMES \
1782 #define REGISTER_NAMES \
1793 /* How to renumber registers for dbx and gdb.
1794 On the Sun-3, the floating point registers have numbers
1795 18 to 25, not 16 to 23 as they do in the compiler. */
1797 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1799 /* Before the prologue, RA is at 0(%sp). */
1800 #define INCOMING_RETURN_ADDR_RTX \
1801 gen_rtx (MEM, VOIDmode, gen_rtx (REG, VOIDmode, STACK_POINTER_REGNUM))
1803 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1804 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1805 Instead use the identity mapping. */
1806 #define DWARF_FRAME_REGNUM(REG) REG
1808 /* Before the prologue, the top of the frame is at 4(%sp). */
1809 #define INCOMING_FRAME_SP_OFFSET 4
1811 /* This is how to output the definition of a user-level label named NAME,
1812 such as the label on a static function or variable NAME. */
1814 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1817 /* This is how to output a command to make the user-level label named NAME
1818 defined for reference from other files. */
1821 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1823 assemble_name (FILE, NAME); \
1826 /* This is how to output a reference to a user-level label named NAME.
1827 `assemble_name' uses this. */
1829 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1832 /* This is how to output an internal numbered label where
1833 PREFIX is the class of label and NUM is the number within the class. */
1835 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1838 /* This is how to store into the string LABEL
1839 the symbol_ref name of an internal numbered label where
1840 PREFIX is the class of label and NUM is the number within the class.
1841 This is suitable for output with `assemble_name'. */
1843 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1846 /* This is how to output a `long double' extended real constant. */
1848 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1849 do { long l[3]; \
1850 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1851 if (sizeof (int) == sizeof (long)) \
1853 else \
1855 } while (0)
1857 /* This is how to output an assembler line defining a `double' constant. */
1859 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1860 do { char dstr[30]; \
1863 } while (0)
1865 /* This is how to output an assembler line defining a `float' constant. */
1867 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1868 do { long l; \
1869 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1870 if (sizeof (int) == sizeof (long)) \
1872 else \
1874 } while (0)
1876 /* This is how to output an assembler line defining an `int' constant. */
1878 #define ASM_OUTPUT_INT(FILE,VALUE) \
1880 output_addr_const (FILE, (VALUE)), \
1883 /* Likewise for `char' and `short' constants. */
1885 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1887 output_addr_const (FILE, (VALUE)), \
1890 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1892 output_addr_const (FILE, (VALUE)), \
1895 /* This is how to output an assembler line for a numeric constant byte. */
1897 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1900 /* This is how to output an insn to push a register on the stack.
1901 It need not be very fast code. */
1903 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1906 /* This is how to output an insn to pop a register from the stack.
1907 It need not be very fast code. */
1909 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1912 /* This is how to output an element of a case-vector that is absolute.
1913 (The 68000 does not use such vectors,
1914 but we must define this macro anyway.) */
1916 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1919 /* This is how to output an element of a case-vector that is relative. */
1921 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1924 /* This is how to output an assembler line
1925 that says to advance the location counter
1926 to a multiple of 2**LOG bytes. */
1928 /* We don't have a way to align to more than a two-byte boundary, so do the
1929 best we can and don't complain. */
1930 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1931 if ((LOG) >= 1) \
1934 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1937 /* This says how to output an assembler line
1938 to define a global common symbol. */
1940 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1942 assemble_name ((FILE), (NAME)), \
1945 /* This says how to output an assembler line
1946 to define a local common symbol. */
1948 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1950 assemble_name ((FILE), (NAME)), \
1953 /* Store in OUTPUT a string (made with alloca) containing
1954 an assembler-name for a local static variable named NAME.
1955 LABELNO is an integer which is different for each call. */
1957 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1958 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1961 /* Define the parentheses used to group arithmetic operations
1962 in assembler code. */
1967 /* Define results of standard character escape sequences. */
1968 #define TARGET_BELL 007
1969 #define TARGET_BS 010
1970 #define TARGET_TAB 011
1971 #define TARGET_NEWLINE 012
1972 #define TARGET_VT 013
1973 #define TARGET_FF 014
1974 #define TARGET_CR 015
1976 /* Output a float value (represented as a C double) as an immediate operand.
1977 This macro is a 68k-specific macro. */
1979 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1980 do { \
1982 { \
1983 char dstr[30]; \
1986 } \
1987 else \
1988 { \
1989 long l; \
1990 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1991 if (sizeof (int) == sizeof (long)) \
1993 else \
1995 } \
1996 } while (0)
1998 /* Output a double value (represented as a C double) as an immediate operand.
1999 This macro is a 68k-specific macro. */
2000 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
2001 do { char dstr[30]; \
2004 } while (0)
2006 /* Note, long double immediate operands are not actually
2007 generated by m68k.md. */
2008 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
2009 do { char dstr[30]; \
2012 } while (0)
2014 /* Print operand X (an rtx) in assembler syntax to file FILE.
2015 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2016 For `%' followed by punctuation, CODE is the punctuation and X is null.
2018 On the 68000, we use several CODE characters:
2019 '.' for dot needed in Motorola-style opcode names.
2020 '-' for an operand pushing on the stack:
2021 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2022 '+' for an operand pushing on the stack:
2023 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2024 '@' for a reference to the top word on the stack:
2025 sp@, (sp) or (%sp) depending on the style of syntax.
2026 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2027 but & in SGS syntax).
2028 '!' for the fpcr register (used in some float-to-fixed conversions).
2029 '$' for the letter `s' in an op code, but only on the 68040.
2030 '&' for the letter `d' in an op code, but only on the 68040.
2031 '/' for register prefix needed by longlong.h.
2033 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2034 'd' to force memory addressing to be absolute, not relative.
2035 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2036 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2037 than directly). Second part of 'y' below.
2038 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2039 or print pair of registers as rx:ry.
2040 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2041 CONST_DOUBLE's as SunFPA constant RAM registers if
2042 possible, so it should not be used except for the SunFPA. */
2044 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2049 /* A C compound statement to output to stdio stream STREAM the
2050 assembler syntax for an instruction operand X. X is an RTL
2051 expression.
2053 CODE is a value that can be used to specify one of several ways
2054 of printing the operand. It is used when identical operands
2055 must be printed differently depending on the context. CODE
2056 comes from the `%' specification that was used to request
2057 printing of the operand. If the specification was just `%DIGIT'
2058 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2059 is the ASCII code for LTR.
2061 If X is a register, this macro should print the register's name.
2062 The names can be found in an array `reg_names' whose type is
2063 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2065 When the machine description has a specification `%PUNCT' (a `%'
2066 followed by a punctuation character), this macro is called with
2067 a null pointer for X and the punctuation character for CODE.
2069 See m68k.c for the m68k specific codes. */
2071 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2073 /* A C compound statement to output to stdio stream STREAM the
2074 assembler syntax for an instruction operand that is a memory
2075 reference whose address is ADDR. ADDR is an RTL expression.
2077 On some machines, the syntax for a symbolic address depends on
2078 the section that the address refers to. On these machines,
2079 define the macro `ENCODE_SECTION_INFO' to store the information
2080 into the `symbol_ref', and then check for it here. */
2082 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2085 /* Definitions for generating bytecode */
2087 /* Just so it's known this target is supported by the bytecode generator.
2088 If this define isn't found anywhere in the target config files, then
2089 dummy stubs are supplied by bytecode.h, and any attempt to use
2090 -fbytecode will result in an error message. */
2092 #define TARGET_SUPPORTS_BYTECODE
2094 /* Minimal segment alignment within sections is 8 units. */
2095 #define MACHINE_SEG_ALIGN 3
2097 /* Integer alignment is two units. */
2098 #define INT_ALIGN 2
2100 /* Pointer alignment is eight units. */
2101 #define PTR_ALIGN 3
2103 /* Global symbols begin with `_' */
2104 #define NAMES_HAVE_UNDERSCORES
2106 /* BC_xxx below are similar to their ASM_xxx counterparts above. */
2107 #define BC_GLOBALIZE_LABEL(FP, NAME) bc_globalize_label(NAME)
2109 #define BC_OUTPUT_COMMON(FP, NAME, SIZE, ROUNDED) \
2110 do { bc_emit_common(NAME, ROUNDED); bc_globalize_label(NAME); } while (0)
2112 #define BC_OUTPUT_BSS(FP, NAME, SIZE, ROUNDED) \
2113 do { bc_data (); bc_emit_labeldef(NAME); bc_emit_skip (SIZE); } while (0)
2115 #define BC_OUTPUT_LOCAL(FP, NAME, SIZE, ROUNDED) \
2116 bc_emit_common(NAME, ROUNDED)
2118 #define BC_OUTPUT_ALIGN(FP, ALIGN) bc_align(ALIGN)
2120 #define BC_OUTPUT_LABEL(FP, NAME) bc_emit_labeldef(NAME)
2122 #define BC_OUTPUT_SKIP(FP, SIZE) bc_emit_skip(SIZE)
2124 #define BC_OUTPUT_LABELREF(FP, NAME) \
2125 do { \
2126 char *foo = (char *) xmalloc(strlen(NAME) + 2); \
2128 strcat(foo, NAME); \
2129 bc_emit_labelref (foo); \
2130 free (foo); \
2131 } while (0)
2133 #define BC_OUTPUT_FLOAT(FP, VAL) \
2134 do { \
2135 float F = VAL; \
2136 bc_emit ((char *) &F, sizeof F); \
2137 } while (0)
2139 #define BC_OUTPUT_DOUBLE(FP, VAL) \
2140 do { \
2141 double D = VAL; \
2142 bc_emit ((char *) &D, sizeof D); \
2143 } while (0)
2145 #define BC_OUTPUT_BYTE(FP, VAL) \
2146 do { \
2147 char C = VAL; \
2148 bc_emit (&C, 1); \
2149 } while (0)
2152 #define BC_OUTPUT_FILE ASM_OUTPUT_FILE
2153 #define BC_OUTPUT_ASCII ASM_OUTPUT_ASCII
2154 #define BC_OUTPUT_IDENT ASM_OUTPUT_IDENT
2156 /* Same as XSTR, but for bytecode */
2157 #define BCXSTR(RTX) ((RTX)->bc_label)
2160 /* Flush bytecode buffer onto file */
2161 #define BC_WRITE_FILE(FP) \
2162 { \
2164 bc_seg_write (bc_text_seg, FP); \
2166 bc_seg_write (bc_data_seg, FP); \
2168 }
2170 /* Write one symbol */
2171 #define BC_WRITE_SEGSYM(SEGSYM, FP) \
2172 { \
2173 prsym (FP, (SEGSYM)->sym->name); \
2175 }
2178 /* Write one reloc entry */
2179 #define BC_WRITE_RELOC_ENTRY(SEGRELOC, FP, OFFSET) \
2180 { \
2182 prsym (FP, (SEGRELOC)->sym->name); \
2184 }
2186 /* Start new line of bytecodes */
2187 #define BC_START_BYTECODE_LINE(FP) \
2188 { \
2190 }
2192 /* Write one bytecode */
2193 #define BC_WRITE_BYTECODE(SEP, VAL, FP) \
2194 { \
2196 }
2198 /* Write one bytecode RTL entry */
2199 #define BC_WRITE_RTL(R, FP) \
2200 { \
2202 }
2205 /* Emit function entry trampoline */
2206 #define BC_EMIT_TRAMPOLINE(TRAMPSEG, CALLINFO) \
2207 { \
2208 short insn; \
2209 \
2212 seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \
2213 seg_refsym (TRAMPSEG, CALLINFO, 0); \
2214 \
2217 seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \
2220 seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \
2222 seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \
2223 }
2227 #if 0
2228 #define VALIDATE_STACK() if (stack_depth < 0) abort ();
2229 #else
2230 #if 0
2231 #define VALIDATE_STACK() \
2233 #endif
2234 #endif
2236 /* Define functions defined in aux-output.c and used in templates. */
2255 /* Variables in m68k.c */
2264 \f
2265 /*
2266 Local variables:
2267 version-control: t
2268 End:
2269 */