| blob | b0ce7cd9d4345c866d5cf59389a4a4c0c22a86d0 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
60 /* Not really meaningful values, but at least something. */
61 #ifndef SIMULTANEOUS_PREFETCHES
62 #define SIMULTANEOUS_PREFETCHES 3
63 #endif
64 #ifndef PREFETCH_BLOCK
65 #define PREFETCH_BLOCK 32
66 #endif
67 #ifndef HAVE_prefetch
68 #define HAVE_prefetch 0
69 #define CODE_FOR_prefetch 0
70 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
71 #endif
73 /* Give up the prefetch optimizations once we exceed a given threshhold.
74 It is unlikely that we would be able to optimize something in a loop
75 with so many detected prefetches. */
76 #define MAX_PREFETCHES 100
77 /* The number of prefetch blocks that are beneficial to fetch at once before
78 a loop with a known (and low) iteration count. */
79 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
80 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
81 since it is likely that the data are already in the cache. */
82 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
84 /* Parameterize some prefetch heuristics so they can be turned on and off
85 easily for performance testing on new architecures. These can be
86 defined in target-dependent files. */
88 /* Prefetch is worthwhile only when loads/stores are dense. */
89 #ifndef PREFETCH_ONLY_DENSE_MEM
90 #define PREFETCH_ONLY_DENSE_MEM 1
91 #endif
93 /* Define what we mean by "dense" loads and stores; This value divided by 256
94 is the minimum percentage of memory references that worth prefetching. */
95 #ifndef PREFETCH_DENSE_MEM
96 #define PREFETCH_DENSE_MEM 220
97 #endif
99 /* Do not prefetch for a loop whose iteration count is known to be low. */
100 #ifndef PREFETCH_NO_LOW_LOOPCNT
101 #define PREFETCH_NO_LOW_LOOPCNT 1
102 #endif
104 /* Define what we mean by a "low" iteration count. */
105 #ifndef PREFETCH_LOW_LOOPCNT
106 #define PREFETCH_LOW_LOOPCNT 32
107 #endif
109 /* Do not prefetch for a loop that contains a function call; such a loop is
110 probably not an internal loop. */
111 #ifndef PREFETCH_NO_CALL
112 #define PREFETCH_NO_CALL 1
113 #endif
115 /* Do not prefetch accesses with an extreme stride. */
116 #ifndef PREFETCH_NO_EXTREME_STRIDE
117 #define PREFETCH_NO_EXTREME_STRIDE 1
118 #endif
120 /* Define what we mean by an "extreme" stride. */
121 #ifndef PREFETCH_EXTREME_STRIDE
122 #define PREFETCH_EXTREME_STRIDE 4096
123 #endif
125 /* Define a limit to how far apart indices can be and still be merged
126 into a single prefetch. */
127 #ifndef PREFETCH_EXTREME_DIFFERENCE
128 #define PREFETCH_EXTREME_DIFFERENCE 4096
129 #endif
131 /* Issue prefetch instructions before the loop to fetch data to be used
132 in the first few loop iterations. */
133 #ifndef PREFETCH_BEFORE_LOOP
134 #define PREFETCH_BEFORE_LOOP 1
135 #endif
137 /* Do not handle reversed order prefetches (negative stride). */
138 #ifndef PREFETCH_NO_REVERSE_ORDER
139 #define PREFETCH_NO_REVERSE_ORDER 1
140 #endif
142 /* Prefetch even if the GIV is in conditional code. */
143 #ifndef PREFETCH_CONDITIONAL
144 #define PREFETCH_CONDITIONAL 1
145 #endif
147 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
148 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
150 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
151 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
152 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
154 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
155 ((REGNO) < FIRST_PSEUDO_REGISTER \
156 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
159 /* Vector mapping INSN_UIDs to luids.
160 The luids are like uids but increase monotonically always.
161 We use them to see whether a jump comes from outside a given loop. */
165 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
166 number the insn is contained in. */
170 /* 1 + largest uid of any insn. */
174 /* Number of loops detected in current function. Used as index to the
175 next few tables. */
179 /* Bound on pseudo register number before loop optimization.
180 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
183 /* The value to pass to the next call of reg_scan_update. */
185 \f
186 /* During the analysis of a loop, a chain of `struct movable's
187 is made to record all the movable insns found.
188 Then the entire chain can be scanned to decide which to move. */
190 struct movable
191 {
196 of any registers used within the LIBCALL. */
198 that must be moved with this one. */
201 may be adjusted when matching movables
202 that load the same value are found. */
204 including other movables that force this
205 or match this one. */
209 /* If PARTIAL is 1, GLOBAL means something different:
210 that the reg is live outside the range from where it is set
211 to the following label. */
215 In particular, moving it does not make it
216 invariant. */
218 load SRC, rather than copying INSN. */
220 first insn of a consecutive sets group. */
223 that we should avoid changing when clearing
224 the rest of the reg. */
228 };
233 /* Forward declarations. */
248 #if 0
250 #endif
280 rtx *));
363 {
364 rtx r1;
365 rtx r2;
369 {
370 rtx match;
371 rtx replacement;
372 rtx insn;
375 /* Nonzero iff INSN is between START and END, inclusive. */
376 #define INSN_IN_RANGE_P(INSN, START, END) \
377 (INSN_UID (INSN) < max_uid_for_loop \
378 && INSN_LUID (INSN) >= INSN_LUID (START) \
379 && INSN_LUID (INSN) <= INSN_LUID (END))
381 /* Indirect_jump_in_function is computed once per function. */
389 rtx));
390 \f
391 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
392 copy the value of the strength reduced giv to its original register. */
395 /* Cost of using a register, to normalize the benefits of a giv. */
398 void
400 {
406 }
407 \f
408 /* Compute the mapping from uids to luids.
409 LUIDs are numbers assigned to insns, like uids,
410 except that luids increase monotonically through the code.
411 Start at insn START and stop just before END. Assign LUIDs
412 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
413 static int
417 {
419 rtx insn;
422 {
425 /* Don't assign luids to line-number NOTEs, so that the distance in
426 luids between two insns is not affected by -g. */
430 else
431 /* Give a line number note the same luid as preceding insn. */
433 }
435 }
436 \f
437 /* Entry point of this file. Perform loop optimization
438 on the current function. F is the first insn of the function
439 and DUMPFILE is a stream for output of a trace of actions taken
440 (or 0 if none should be output). */
442 void
444 /* f is the first instruction of a chain of insns for one function */
445 rtx f;
448 {
449 rtx insn;
464 /* Count the number of loops. */
468 {
471 max_loop_num++;
472 }
474 /* Don't waste time if no loops. */
480 /* Get size to use for tables indexed by uids.
481 Leave some space for labels allocated by find_and_verify_loops. */
488 /* Allocate storage for array of loops. */
492 /* Find and process each loop.
493 First, find them, and record them in order of their beginnings. */
496 /* Allocate and initialize auxiliary loop information. */
501 /* Now find all register lifetimes. This must be done after
502 find_and_verify_loops, because it might reorder the insns in the
503 function. */
506 /* This must occur after reg_scan so that registers created by gcse
507 will have entries in the register tables.
509 We could have added a call to reg_scan after gcse_main in toplev.c,
510 but moving this call to init_alias_analysis is more efficient. */
513 /* See if we went too far. Note that get_max_uid already returns
514 one more that the maximum uid of all insn. */
517 /* Now reset it to the actual size we need. See above. */
520 /* find_and_verify_loops has already called compute_luids, but it
521 might have rearranged code afterwards, so we need to recompute
522 the luids now. */
525 /* Don't leave gaps in uid_luid for insns that have been
526 deleted. It is possible that the first or last insn
527 using some register has been deleted by cross-jumping.
528 Make sure that uid_luid for that former insn's uid
529 points to the general area where that insn used to be. */
531 {
535 }
540 /* Determine if the function has indirect jump. On some systems
541 this prevents low overhead loop instructions from being used. */
544 /* Now scan the loops, last ones first, since this means inner ones are done
545 before outer ones. */
547 {
552 }
556 /* Clean up. */
561 }
562 \f
563 /* Returns the next insn, in execution order, after INSN. START and
564 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
565 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
566 insn-stream; it is used with loops that are entered near the
567 bottom. */
569 static rtx
572 rtx insn;
573 {
577 {
579 /* Go to the top of the loop, and continue there. */
581 else
582 /* We're done. */
584 }
587 /* We're done. */
591 }
593 /* Optimize one loop described by LOOP. */
595 /* ??? Could also move memory writes out of loops if the destination address
596 is invariant, the source is invariant, the memory write is not volatile,
597 and if we can prove that no read inside the loop can read this address
598 before the write occurs. If there is a read of this address after the
599 write, then we can also mark the memory read as invariant. */
601 static void
605 {
611 rtx p;
612 /* 1 if we are scanning insns that could be executed zero times. */
614 /* 1 if we are scanning insns that might never be executed
615 due to a subroutine call which might exit before they are reached. */
617 /* Number of insns in the loop. */
621 /* The SET from an insn, if it is the only SET in the insn. */
623 /* Chain describing insns movable in current loop. */
625 /* Ratio of extra register life span we can justify
626 for saving an instruction. More if loop doesn't call subroutines
627 since in that case saving an insn makes more difference
628 and more registers are available. */
630 /* Nonzero if we are scanning instructions in a sub-loop. */
639 /* Determine whether this loop starts with a jump down to a test at
640 the end. This will occur for a small number of loops with a test
641 that is too complex to duplicate in front of the loop.
643 We search for the first insn or label in the loop, skipping NOTEs.
644 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
645 (because we might have a loop executed only once that contains a
646 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
647 (in case we have a degenerate loop).
649 Note that if we mistakenly think that a loop is entered at the top
650 when, in fact, it is entered at the exit test, the only effect will be
651 slightly poorer optimization. Making the opposite error can generate
652 incorrect code. Since very few loops now start with a jump to the
653 exit test, the code here to detect that case is very conservative. */
656 p != loop_end
662 ;
666 /* If loop end is the end of the current function, then emit a
667 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
668 note insn. This is the position we use when sinking insns out of
669 the loop. */
672 else
675 /* Set up variables describing this loop. */
679 /* If loop has a jump before the first label,
680 the true entry is the target of that jump.
681 Start scan from there.
682 But record in LOOP->TOP the place where the end-test jumps
683 back to so we can scan that after the end of the loop. */
685 /* Loop entry must be unconditional jump (and not a RETURN) */
688 /* Check to see whether the jump actually
689 jumps out of the loop (meaning it's no loop).
690 This case can happen for things like
691 do {..} while (0). If this label was generated previously
692 by loop, we can't tell anything about it and have to reject
693 the loop. */
695 {
698 }
700 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
701 as required by loop_reg_used_before_p. So skip such loops. (This
702 test may never be true, but it's best to play it safe.)
704 Also, skip loops where we do not start scanning at a label. This
705 test also rejects loops starting with a JUMP_INSN that failed the
706 test above. */
710 {
715 }
717 /* Allocate extra space for REGs that might be created by load_mems.
718 We allocate a little extra slop as well, in the hopes that we
719 won't have to reallocate the regs array. */
724 {
730 }
732 /* Scan through the loop finding insns that are safe to move.
733 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
734 this reg will be considered invariant for subsequent insns.
735 We consider whether subsequent insns use the reg
736 in deciding whether it is worth actually moving.
738 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
739 and therefore it is possible that the insns we are scanning
740 would never be executed. At such times, we must make sure
741 that it is safe to execute the insn once instead of zero times.
742 When MAYBE_NEVER is 0, all insns will be executed at least once
743 so that is not a problem. */
748 {
750 in_libcall--;
752 {
755 in_libcall++;
759 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
761 #endif
763 {
770 /* Figure out what to use as a source of this insn. If a
771 REG_EQUIV note is given or if a REG_EQUAL note with a
772 constant operand is specified, use it as the source and
773 mark that we should move this insn by calling
774 emit_move_insn rather that duplicating the insn.
776 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
777 note is present. */
781 else
782 {
787 {
789 /* A libcall block can use regs that don't appear in
790 the equivalent expression. To move the libcall,
791 we must move those regs too. */
793 }
794 }
796 /* For parallels, add any possible uses to the depencies, as
797 we can't move the insn without resolving them first. */
799 {
801 {
804 dependencies
806 dependencies);
807 }
808 }
810 /* Don't try to optimize a register that was made
811 by loop-optimization for an inner loop.
812 We don't know its life-span, so we can't compute
813 the benefit. */
815 ;
817 than the one where it is set (meaning that
818 something after this point in the loop might
819 depend on its value before the set). */
821 /* And the set is not guaranteed to be executed once
822 the loop starts, or the value before the set is
823 needed before the set occurs...
825 ??? Note we have quadratic behavior here, mitigated
826 by the fact that the previous test will often fail for
827 large loops. Rather than re-scanning the entire loop
828 each time for register usage, we should build tables
829 of the register usage and use them here instead. */
830 && (maybe_never
832 /* It is unsafe to move the set.
834 This code used to consider it OK to move a set of a variable
835 which was not created by the user and not used in an exit
836 test.
837 That behavior is incorrect and was removed. */
838 ;
841 || (tem2
844 || (tem1
845 = consec_sets_invariant_p
848 p)))
849 /* If the insn can cause a trap (such as divide by zero),
850 can't move it unless it's guaranteed to be executed
851 once loop is entered. Even a function call might
852 prevent the trap insn from being reached
853 (since it might exit!) */
856 {
860 /* A potential lossage is where we have a case where two insns
861 can be combined as long as they are both in the loop, but
862 we move one of them outside the loop. For large loops,
863 this can lose. The most common case of this is the address
864 of a function being called.
866 Therefore, if this register is marked as being used
867 exactly once if we are in a loop with calls
868 (a "large loop"), see if we can replace the usage of
869 this register with the source of this SET. If we can,
870 delete this insn.
872 Don't do this if P has a REG_RETVAL note or if we have
873 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
885 && (! SMALL_REGISTER_CLASSES
889 /* This test is not redundant; SET_SRC (set) might be
890 a call-clobbered register and the life of REGNO
891 might span a call. */
898 {
899 /* Replace any usage in a REG_EQUAL note. Must copy
900 the new source, so that we don't get rtx sharing
901 between the SET_SOURCE and REG_NOTES of insn p. */
903 = (replace_rtx
909 i++)
912 }
921 m->consec
931 /* Set M->cond if either loop_invariant_p
932 or consec_sets_invariant_p returned 2
933 (only conditionally invariant). */
943 /* Add M to the end of the chain MOVABLES. */
947 {
948 /* It is possible for the first instruction to have a
949 REG_EQUAL note but a non-invariant SET_SRC, so we must
950 remember the status of the first instruction in case
951 the last instruction doesn't have a REG_EQUAL note. */
954 /* Skip this insn, not checking REG_LIBCALL notes. */
956 /* Skip the consecutive insns, if there are any. */
958 /* Back up to the last insn of the consecutive group. */
961 /* We must now reset m->move_insn, m->is_equiv, and
962 possibly m->set_src to correspond to the effects of
963 all the insns. */
967 else
968 {
972 else
975 }
976 m->is_equiv
978 }
979 }
980 /* If this register is always set within a STRICT_LOW_PART
981 or set to zero, then its high bytes are constant.
982 So clear them outside the loop and within the loop
983 just load the low bytes.
984 We must check that the machine has an instruction to do so.
985 Also, if the value loaded into the register
986 depends on the same register, this cannot be done. */
996 {
999 {
1013 /* If the insn may not be executed on some cycles,
1014 we can't clear the whole reg; clear just high part.
1015 Not even if the reg is used only within this loop.
1016 Consider this:
1017 while (1)
1018 while (s != t) {
1019 if (foo ()) x = *s;
1020 use (x);
1021 }
1022 Clearing x before the inner loop could clobber a value
1023 being saved from the last time around the outer loop.
1024 However, if the reg is not used outside this loop
1025 and all uses of the register are in the same
1026 basic block as the store, there is no problem.
1028 If this insn was made by loop, we don't know its
1029 INSN_LUID and hence must make a conservative
1030 assumption. */
1033 || (labels_in_range_p
1037 else
1046 i++)
1048 /* Add M to the end of the chain MOVABLES. */
1050 }
1051 }
1052 }
1053 }
1054 /* Past a call insn, we get to insns which might not be executed
1055 because the call might exit. This matters for insns that trap.
1056 Constant and pure call insns always return, so they don't count. */
1059 /* Past a label or a jump, we get to insns for which we
1060 can't count on whether or how many times they will be
1061 executed during each iteration. Therefore, we can
1062 only move out sets of trivial variables
1063 (those not used after the loop). */
1064 /* Similar code appears twice in strength_reduce. */
1066 /* If we enter the loop in the middle, and scan around to the
1067 beginning, don't set maybe_never for that. This must be an
1068 unconditional jump, otherwise the code at the top of the
1069 loop might never be executed. Unconditional jumps are
1070 followed by a barrier then the loop_end. */
1076 {
1077 /* At the virtual top of a converted loop, insns are again known to
1078 be executed: logically, the loop begins here even though the exit
1079 code has been duplicated. */
1083 loop_depth++;
1085 loop_depth--;
1086 }
1087 }
1089 /* If one movable subsumes another, ignore that other. */
1093 /* For each movable insn, see if the reg that it loads
1094 leads when it dies right into another conditionally movable insn.
1095 If so, record that the second insn "forces" the first one,
1096 since the second can be moved only if the first is. */
1100 /* See if there are multiple movable insns that load the same value.
1101 If there are, make all but the first point at the first one
1102 through the `match' field, and add the priorities of them
1103 all together as the priority of the first. */
1107 /* Now consider each movable insn to decide whether it is worth moving.
1108 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1110 Generally this increases code size, so do not move moveables when
1111 optimizing for code size. */
1114 {
1117 /* Recalculate regs->array if move_movables has created new
1118 registers. */
1120 {
1126 ;
1131 }
1132 }
1134 /* Now candidates that still are negative are those not moved.
1135 Change regs->array[I].set_in_loop to indicate that those are not actually
1136 invariant. */
1141 /* Now that we've moved some things out of the loop, we might be able to
1142 hoist even more memory references. */
1145 /* Recalculate regs->array if load_mems has created new registers. */
1153 ;
1160 {
1162 /* Ensure our label doesn't go away. */
1173 }
1176 /* The movable information is required for strength reduction. */
1182 }
1183 \f
1184 /* Add elements to *OUTPUT to record all the pseudo-regs
1185 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1187 void
1191 {
1199 {
1217 }
1221 {
1225 {
1234 }
1235 }
1236 }
1237 \f
1238 /* Check what regs are referred to in the libcall block ending with INSN,
1239 aside from those mentioned in the equivalent value.
1240 If there are none, return 0.
1241 If there are one or more, return an EXPR_LIST containing all of them. */
1243 rtx
1246 {
1251 /* First, find all the regs used in the libcall block
1252 that are not mentioned as inputs to the result. */
1255 {
1260 }
1263 }
1264 \f
1265 /* Return 1 if all uses of REG
1266 are between INSN and the end of the basic block. */
1268 static int
1271 {
1273 rtx p;
1278 /* Search this basic block for the already recorded last use of the reg. */
1280 {
1282 {
1288 /* Ordinary insn: if this is the last use, we win. */
1294 /* Jump insn: if this is the last use, we win. */
1297 /* Otherwise, it's the end of the basic block, so we lose. */
1302 /* It's the end of the basic block, so we lose. */
1307 }
1308 }
1310 /* The "last use" that was recorded can't be found after the first
1311 use. This can happen when the last use was deleted while
1312 processing an inner loop, this inner loop was then completely
1313 unrolled, and the outer loop is always exited after the inner loop,
1314 so that everything after the first use becomes a single basic block. */
1316 }
1317 \f
1318 /* Compute the benefit of eliminating the insns in the block whose
1319 last insn is LAST. This may be a group of insns used to compute a
1320 value directly or can contain a library call. */
1322 static int
1324 rtx last;
1325 {
1326 rtx insn;
1331 {
1334 routine. */
1338 benefit++;
1339 }
1342 }
1343 \f
1344 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1346 static rtx
1348 rtx insn;
1350 {
1352 {
1353 rtx temp;
1355 /* If first insn of libcall sequence, skip to end. */
1356 /* Do this at start of loop, since INSN is guaranteed to
1357 be an insn here. */
1362 do
1365 }
1368 }
1370 /* Ignore any movable whose insn falls within a libcall
1371 which is part of another movable.
1372 We make use of the fact that the movable for the libcall value
1373 was made later and so appears later on the chain. */
1375 static void
1378 {
1382 {
1383 /* Is this a movable for the value of a libcall? */
1386 {
1387 rtx insn;
1388 /* Check for earlier movables inside that range,
1389 and mark them invalid. We cannot use LUIDs here because
1390 insns created by loop.c for prior loops don't have LUIDs.
1391 Rather than reject all such insns from movables, we just
1392 explicitly check each insn in the libcall (since invariant
1393 libcalls aren't that common). */
1398 }
1399 }
1400 }
1402 /* For each movable insn, see if the reg that it loads
1403 leads when it dies right into another conditionally movable insn.
1404 If so, record that the second insn "forces" the first one,
1405 since the second can be moved only if the first is. */
1407 static void
1410 {
1414 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1416 {
1419 /* ??? Could this be a bug? What if CSE caused the
1420 register of M1 to be used after this insn?
1421 Since CSE does not update regno_last_uid,
1422 this insn M->insn might not be where it dies.
1423 But very likely this doesn't matter; what matters is
1424 that M's reg is computed from M1's reg. */
1429 /* If m->consec, m->set_src isn't valid. */
1433 /* Increase the priority of the moving the first insn
1434 since it permits the second to be moved as well. */
1436 {
1440 }
1441 }
1442 }
1443 \f
1444 /* Find invariant expressions that are equal and can be combined into
1445 one register. */
1447 static void
1451 {
1456 /* Regs that are set more than once are not allowed to match
1457 or be matched. I'm no longer sure why not. */
1458 /* Only pseudo registers are allowed to match or be matched,
1459 since move_movables does not validate the change. */
1460 /* Perhaps testing m->consec_sets would be more appropriate here? */
1466 {
1473 /* We want later insns to match the first one. Don't make the first
1474 one match any later ones. So start this loop at m->next. */
1479 /* A reg used outside the loop mustn't be eliminated. */
1481 /* A reg used for zero-extending mustn't be eliminated. */
1484 ||
1485 (
1486 /* Can combine regs with different modes loaded from the
1487 same constant only if the modes are the same or
1488 if both are integer modes with M wider or the same
1489 width as M1. The check for integer is redundant, but
1490 safe, since the only case of differing destination
1491 modes with equal sources is when both sources are
1492 VOIDmode, i.e., CONST_INT. */
1498 /* See if the source of M1 says it matches M. */
1505 {
1511 }
1512 }
1514 /* Now combine the regs used for zero-extension.
1515 This can be done for those not marked `global'
1516 provided their lives don't overlap. */
1520 {
1523 /* Combine all the registers for extension from mode MODE.
1524 Don't combine any that are used outside this loop. */
1528 {
1535 {
1536 /* First one: don't check for overlap, just record it. */
1539 }
1541 /* Make sure they extend to the same mode.
1542 (Almost always true.) */
1546 /* We already have one: check for overlap with those
1547 already combined together. */
1554 /* No overlap: we can combine this with the others. */
1560 overlap:
1561 ;
1562 }
1563 }
1565 /* Clean up. */
1567 }
1569 /* Returns the number of movable instructions in LOOP that were not
1570 moved outside the loop. */
1572 static int
1575 {
1584 }
1586 \f
1587 /* Return 1 if regs X and Y will become the same if moved. */
1589 static int
1593 {
1610 }
1612 /* Return 1 if X and Y are identical-looking rtx's.
1613 This is the Lisp function EQUAL for rtx arguments.
1615 If two registers are matching movables or a movable register and an
1616 equivalent constant, consider them equal. */
1618 static int
1623 {
1637 /* If we have a register and a constant, they may sometimes be
1638 equal. */
1641 {
1646 }
1649 {
1654 }
1656 /* Otherwise, rtx's of different codes cannot be equal. */
1660 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1661 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1666 /* These three types of rtx's can be compared nonrecursively. */
1675 /* Compare the elements. If any pair of corresponding elements
1676 fail to match, return 0 for the whole things. */
1680 {
1682 {
1694 /* Two vectors must have the same length. */
1698 /* And the corresponding elements must match. */
1717 /* These are just backpointers, so they don't matter. */
1723 /* It is believed that rtx's at this level will never
1724 contain anything but integers and other rtx's,
1725 except for within LABEL_REFs and SYMBOL_REFs. */
1728 }
1729 }
1731 }
1732 \f
1733 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1734 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1735 references is incremented once for each added note. */
1737 static void
1739 rtx x;
1740 rtx insns;
1741 {
1745 rtx insn;
1748 {
1749 /* This code used to ignore labels that referred to dispatch tables to
1750 avoid flow generating (slighly) worse code.
1752 We no longer ignore such label references (see LABEL_REF handling in
1753 mark_jump_label for additional information). */
1756 {
1761 }
1762 }
1766 {
1772 }
1773 }
1774 \f
1775 /* Scan MOVABLES, and move the insns that deserve to be moved.
1776 If two matching movables are combined, replace one reg with the
1777 other throughout. */
1779 static void
1785 {
1790 rtx p;
1793 /* Map of pseudo-register replacements to handle combining
1794 when we move several insns that load the same value
1795 into different pseudo-registers. */
1800 {
1801 /* Describe this movable insn. */
1804 {
1825 }
1827 /* Ignore the insn if it's already done (it matched something else).
1828 Otherwise, see if it is now safe to move. */
1840 {
1842 rtx p;
1845 /* We have an insn that is safe to move.
1846 Compute its desirability. */
1857 /* An insn MUST be moved if we already moved something else
1858 which is safe only if this one is moved too: that is,
1859 if already_moved[REGNO] is nonzero. */
1861 /* An insn is desirable to move if the new lifetime of the
1862 register is no more than THRESHOLD times the old lifetime.
1863 If it's not desirable, it means the loop is so big
1864 that moving won't speed things up much,
1865 and it is liable to make register usage worse. */
1867 /* It is also desirable to move if it can be moved at no
1868 extra cost because something else was already moved. */
1871 || flag_move_all_movables
1876 {
1881 /* Now move the insns that set the reg. */
1884 {
1887 /* Find the end of this chain of matching regs.
1888 Thus, we load each reg in the chain from that one reg.
1889 And that reg is loaded with 0 directly,
1890 since it has ->match == 0. */
1896 /* Mark the moved, invariant reg as being allowed to
1897 share a hard reg with the other matching invariant. */
1901 regs_may_share
1904 regs_may_share));
1912 }
1913 /* If we are to re-generate the item being moved with a
1914 new move insn, first delete what we have and then emit
1915 the move insn before the loop. */
1917 {
1921 {
1922 /* If this is the first insn of a library call sequence,
1923 something is very wrong. */
1928 /* If this is the last insn of a libcall sequence, then
1929 delete every insn in the sequence except the last.
1930 The last insn is handled in the normal manner. */
1933 {
1937 }
1942 /* simplify_giv_expr expects that it can walk the insns
1943 at m->insn forwards and see this old sequence we are
1944 tossing here. delete_insn does preserve the next
1945 pointers, but when we skip over a NOTE we must fix
1946 it up. Otherwise that code walks into the non-deleted
1947 insn stream. */
1950 }
1968 /* The more regs we move, the less we like moving them. */
1970 }
1971 else
1972 {
1974 {
1977 /* If first insn of libcall sequence, skip to end. */
1978 /* Do this at start of loop, since p is guaranteed to
1979 be an insn here. */
1984 /* If last insn of libcall sequence, move all
1985 insns except the last before the loop. The last
1986 insn is handled in the normal manner. */
1989 {
1997 {
1998 rtx body;
1999 rtx n;
2000 rtx next;
2007 /* Find the next insn after TEMP,
2008 not counting USE or NOTE insns. */
2016 /* If that is the call, this may be the insn
2017 that loads the function address.
2019 Extract the function address from the insn
2020 that loads it into a register.
2021 If this insn was cse'd, we get incorrect code.
2023 So emit a new move insn that copies the
2024 function address into the register that the
2025 call insn will use. flow.c will delete any
2026 redundant stores that we have created. */
2031 NULL_RTX)))
2032 {
2038 }
2039 /* We have the call insn.
2040 If it uses the register we suspect it might,
2041 load it with the correct address directly. */
2046 gen_move_insn
2050 {
2052 /* Because the USAGE information potentially
2053 contains objects other than hard registers
2054 we need to copy it. */
2058 }
2059 else
2068 }
2071 }
2073 {
2074 /* P sets REG to zero; but we should clear only
2075 the bits that are not covered by the mode
2076 m->savemode. */
2078 rtx sequence;
2079 rtx tem;
2082 tem = expand_simple_binop
2095 }
2097 {
2099 /* Because the USAGE information potentially
2100 contains objects other than hard registers
2101 we need to copy it. */
2105 }
2107 {
2108 rtx seq;
2109 /* The SET_SRC might not be invariant, so we must
2110 use the REG_EQUAL note. */
2122 }
2123 else
2127 {
2131 /* If there is a REG_EQUAL note present whose value
2132 is not loop invariant, then delete it, since it
2133 may cause problems with later optimization passes.
2134 It is possible for cse to create such notes
2135 like this as a result of record_jump_cond. */
2140 }
2149 /* If library call, now fix the REG_NOTES that contain
2150 insn pointers, namely REG_LIBCALL on FIRST
2151 and REG_RETVAL on I1. */
2153 {
2157 }
2163 /* simplify_giv_expr expects that it can walk the insns
2164 at m->insn forwards and see this old sequence we are
2165 tossing here. delete_insn does preserve the next
2166 pointers, but when we skip over a NOTE we must fix
2167 it up. Otherwise that code walks into the non-deleted
2168 insn stream. */
2171 }
2173 /* The more regs we move, the less we like moving them. */
2175 }
2177 /* Any other movable that loads the same register
2178 MUST be moved. */
2181 /* This reg has been moved out of one loop. */
2184 /* The reg set here is now invariant. */
2186 {
2190 }
2194 /* Change the length-of-life info for the register
2195 to say it lives at least the full length of this loop.
2196 This will help guide optimizations in outer loops. */
2199 /* This is the old insn before all the moved insns.
2200 We can't use the moved insn because it is out of range
2201 in uid_luid. Only the old insns have luids. */
2206 /* Combine with this moved insn any other matching movables. */
2211 {
2212 rtx temp;
2214 /* Schedule the reg loaded by M1
2215 for replacement so that shares the reg of M.
2216 If the modes differ (only possible in restricted
2217 circumstances, make a SUBREG.
2219 Note this assumes that the target dependent files
2220 treat REG and SUBREG equally, including within
2221 GO_IF_LEGITIMATE_ADDRESS and in all the
2222 predicates since we never verify that replacing the
2223 original register with a SUBREG results in a
2224 recognizable insn. */
2227 else
2232 /* Get rid of the matching insn
2233 and prevent further processing of it. */
2236 /* if library call, delete all insns. */
2238 NULL_RTX)))
2240 else
2243 /* Any other movable that loads the same register
2244 MUST be moved. */
2247 /* The reg merged here is now invariant,
2248 if the reg it matches is invariant. */
2250 {
2254 i++)
2256 }
2257 }
2258 }
2261 }
2267 }
2272 /* Go through all the instructions in the loop, making
2273 all the register substitutions scheduled in REG_MAP. */
2277 {
2281 }
2283 /* Clean up. */
2286 }
2289 static void
2293 {
2296 else
2299 }
2302 static void
2305 {
2310 {
2313 }
2314 }
2315 \f
2316 #if 0
2317 /* Scan X and replace the address of any MEM in it with ADDR.
2318 REG is the address that MEM should have before the replacement. */
2320 static void
2323 {
2332 {
2344 /* Short cut for very common case. */
2349 /* Short cut for very common case. */
2354 /* If this MEM uses a reg other than the one we expected,
2355 something is wrong. */
2363 }
2367 {
2371 {
2375 }
2376 }
2377 }
2378 #endif
2379 \f
2380 /* Return the number of memory refs to addresses that vary
2381 in the rtx X. */
2383 static int
2386 rtx x;
2387 {
2398 {
2415 }
2420 {
2424 {
2428 }
2429 }
2431 }
2432 \f
2433 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2434 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2435 `unknown_address_altered', `unknown_constant_address_altered', and
2436 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2437 list `store_mems' in LOOP. */
2439 static void
2442 {
2444 rtx insn;
2448 /* The label after END. Jumping here is just like falling off the
2449 end of the loop. We use next_nonnote_insn instead of next_label
2450 as a hedge against the (pathological) case where some actual insn
2451 might end up between the two. */
2470 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2475 {
2477 {
2480 }
2481 }
2485 {
2487 {
2490 {
2492 /* Count number of loops contained in this one. */
2494 }
2501 {
2504 }
2514 {
2518 {
2523 {
2526 }
2527 else
2528 {
2531 }
2533 do
2534 {
2536 {
2538 {
2539 /* Something tricky. */
2542 }
2545 {
2546 /* A jump outside the current loop. */
2549 }
2550 }
2554 }
2556 }
2557 else
2558 {
2559 /* A return, or something tricky. */
2561 }
2562 }
2563 /* FALLTHRU */
2584 }
2585 }
2587 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2589 anywhere. */
2591 /* We don't want loads for MEMs moved to a location before the
2592 one at which their stack memory becomes allocated. (Note
2593 that this is not a problem for malloc, etc., since those
2594 require actual function calls. */
2595 && ! current_function_calls_alloca
2596 /* There are ways to leave the loop other than falling off the
2597 end. */
2603 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2604 that loop_invariant_p and load_mems can use true_dependence
2605 to determine what is really clobbered. */
2607 {
2610 loop_info->store_mems
2612 }
2614 {
2618 loop_info->store_mems
2620 }
2621 }
2622 \f
2623 /* Invalidate all loops containing LABEL. */
2625 static void
2627 rtx label;
2628 {
2632 }
2634 /* Scan the function looking for loops. Record the start and end of each loop.
2635 Also mark as invalid loops any loops that contain a setjmp or are branched
2636 to from outside the loop. */
2638 static void
2640 rtx f;
2642 {
2643 rtx insn;
2644 rtx label;
2654 /* If there are jumps to undefined labels,
2655 treat them as jumps out of any/all loops.
2656 This also avoids writing past end of tables when there are no loops. */
2659 /* Find boundaries of loops, mark which loops are contained within
2660 loops, and invalidate loops that have setjmp. */
2665 {
2668 {
2672 num_loops++;
2696 }
2700 {
2701 /* In this case, we must invalidate our current loop and any
2702 enclosing loop. */
2704 {
2710 }
2711 }
2713 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2714 enclosing loop, but this doesn't matter. */
2716 }
2718 /* Any loop containing a label used in an initializer must be invalidated,
2719 because it can be jumped into from anywhere. */
2723 /* Any loop containing a label used for an exception handler must be
2724 invalidated, because it can be jumped into from anywhere. */
2727 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2728 loop that it is not contained within, that loop is marked invalid.
2729 If any INSN or CALL_INSN uses a label's address, then the loop containing
2730 that label is marked invalid, because it could be jumped into from
2731 anywhere.
2733 Also look for blocks of code ending in an unconditional branch that
2734 exits the loop. If such a block is surrounded by a conditional
2735 branch around the block, move the block elsewhere (see below) and
2736 invert the jump to point to the code block. This may eliminate a
2737 label in our loop and will simplify processing by both us and a
2738 possible second cse pass. */
2742 {
2746 {
2750 }
2757 /* See if this is an unconditional branch outside the loop. */
2765 {
2766 rtx p;
2772 /* Go backwards until we reach the start of the loop, a label,
2773 or a JUMP_INSN. */
2780 ;
2782 /* Check for the case where we have a jump to an inner nested
2783 loop, and do not perform the optimization in that case. */
2786 {
2789 {
2794 }
2795 }
2797 /* Make sure that the target of P is within the current loop. */
2803 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2804 we have a block of code to try to move.
2806 We look backward and then forward from the target of INSN
2807 to find a BARRIER at the same loop depth as the target.
2808 If we find such a BARRIER, we make a new label for the start
2809 of the block, invert the jump in P and point it to that label,
2810 and move the block of code to the spot we found. */
2815 /* Just ignore jumps to labels that were never emitted.
2816 These always indicate compilation errors. */
2820 /* If it's not safe to move the sequence, then we
2821 mustn't try. */
2824 {
2825 rtx target
2829 rtx tmp;
2831 /* Search for possible garbage past the conditional jumps
2832 and look for the last barrier. */
2840 /* Don't move things inside a tablejump. */
2853 /* Don't move things inside a tablejump. */
2864 {
2868 /* Ensure our label doesn't go away. */
2871 /* Verify that uid_loop is large enough and that
2872 we can invert P. */
2874 {
2877 /* If no suitable BARRIER was found, create a suitable
2878 one before TARGET. Since TARGET is a fall through
2879 path, we'll need to insert a jump around our block
2880 and add a BARRIER before TARGET.
2882 This creates an extra unconditional jump outside
2883 the loop. However, the benefits of removing rarely
2884 executed instructions from inside the loop usually
2885 outweighs the cost of the extra unconditional jump
2886 outside the loop. */
2888 {
2889 rtx temp;
2896 }
2898 /* Include the BARRIER after INSN and copy the
2899 block after LOC. */
2904 /* All those insns are now in TARGET_LOOP. */
2910 /* The label jumped to by INSN is no longer a loop
2911 exit. Unless INSN does not have a label (e.g.,
2912 it is a RETURN insn), search loop->exit_labels
2913 to find its label_ref, and remove it. Also turn
2914 off LABEL_OUTSIDE_LOOP_P bit. */
2916 {
2918 r;
2921 {
2925 else
2928 }
2934 /* If we didn't find it, then something is
2935 wrong. */
2938 }
2940 /* P is now a jump outside the loop, so it must be put
2941 in loop->exit_labels, and marked as such.
2942 The easiest way to do this is to just call
2943 mark_loop_jump again for P. */
2946 /* If INSN now jumps to the insn after it,
2947 delete INSN. */
2952 }
2954 /* Continue the loop after where the conditional
2955 branch used to jump, since the only branch insn
2956 in the block (if it still remains) is an inter-loop
2957 branch and hence needs no processing. */
2963 /* This loop will be continued with NEXT_INSN (insn). */
2965 }
2966 }
2967 }
2968 }
2969 }
2971 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2972 loops it is contained in, mark the target loop invalid.
2974 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2976 static void
2978 rtx x;
2980 {
2986 {
2998 /* There could be a label reference in here. */
3010 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3022 /* Link together all labels that branch outside the loop. This
3023 is used by final_[bg]iv_value and the loop unrolling code. Also
3024 mark this LABEL_REF so we know that this branch should predict
3025 false. */
3027 /* A check to make sure the label is not in an inner nested loop,
3028 since this does not count as a loop exit. */
3030 {
3035 }
3036 else
3040 {
3049 }
3051 /* If this is inside a loop, but not in the current loop or one enclosed
3052 by it, it invalidates at least one loop. */
3057 /* We must invalidate every nested loop containing the target of this
3058 label, except those that also contain the jump insn. */
3061 {
3062 /* Stop when we reach a loop that also contains the jump insn. */
3067 /* If we get here, we know we need to invalidate a loop. */
3074 }
3078 /* If this is not setting pc, ignore. */
3100 /* Strictly speaking this is not a jump into the loop, only a possible
3101 jump out of the loop. However, we have no way to link the destination
3102 of this jump onto the list of exit labels. To be safe we mark this
3103 loop and any containing loops as invalid. */
3105 {
3107 {
3113 }
3114 }
3116 }
3117 }
3118 \f
3119 /* Return nonzero if there is a label in the range from
3120 insn INSN to and including the insn whose luid is END
3121 INSN must have an assigned luid (i.e., it must not have
3122 been previously created by loop.c). */
3124 static int
3126 rtx insn;
3128 {
3130 {
3134 }
3137 }
3139 /* Record that a memory reference X is being set. */
3141 static void
3143 rtx x;
3144 rtx y ATTRIBUTE_UNUSED;
3146 {
3152 /* Count number of memory writes.
3153 This affects heuristics in strength_reduce. */
3156 /* BLKmode MEM means all memory is clobbered. */
3158 {
3161 else
3165 }
3169 }
3171 /* X is a value modified by an INSN that references a biv inside a loop
3172 exit test (ie, X is somehow related to the value of the biv). If X
3173 is a pseudo that is used more than once, then the biv is (effectively)
3174 used more than once. DATA is a pointer to a loop_regs structure. */
3176 static void
3178 rtx x;
3179 rtx y ATTRIBUTE_UNUSED;
3181 {
3196 /* If we do not have usage information, or if we know the register
3197 is used more than once, note that fact for check_dbra_loop. */
3202 }
3203 \f
3204 /* Return nonzero if the rtx X is invariant over the current loop.
3206 The value is 2 if we refer to something only conditionally invariant.
3208 A memory ref is invariant if it is not volatile and does not conflict
3209 with anything stored in `loop_info->store_mems'. */
3211 int
3214 rtx x;
3215 {
3222 rtx mem_list_entry;
3228 {
3236 /* A LABEL_REF is normally invariant, however, if we are unrolling
3237 loops, and this label is inside the loop, then it isn't invariant.
3238 This is because each unrolled copy of the loop body will have
3239 a copy of this label. If this was invariant, then an insn loading
3240 the address of this label into a register might get moved outside
3241 the loop, and then each loop body would end up using the same label.
3243 We don't know the loop bounds here though, so just fail for all
3244 labels. */
3247 else
3256 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3257 since the reg might be set by initialization within the loop. */
3268 /* Out-of-range regs can occur when we are called from unrolling.
3269 These have always been created by the unroller and are set in
3270 the loop, hence are never invariant. */
3281 /* Volatile memory references must be rejected. Do this before
3282 checking for read-only items, so that volatile read-only items
3283 will be rejected also. */
3287 /* See if there is any dependence between a store and this load. */
3290 {
3296 }
3298 /* It's not invalidated by a store in memory
3299 but we must still verify the address is invariant. */
3303 /* Don't mess with insns declared volatile. */
3310 }
3314 {
3316 {
3322 }
3324 {
3327 {
3333 }
3335 }
3336 }
3339 }
3340 \f
3341 /* Return nonzero if all the insns in the loop that set REG
3342 are INSN and the immediately following insns,
3343 and if each of those insns sets REG in an invariant way
3344 (not counting uses of REG in them).
3346 The value is 2 if some of these insns are only conditionally invariant.
3348 We assume that INSN itself is the first set of REG
3349 and that its source is invariant. */
3351 static int
3356 {
3360 rtx temp;
3361 /* Number of sets we have to insist on finding after INSN. */
3367 /* If N_SETS hit the limit, we can't rely on its value. */
3374 {
3376 rtx set;
3381 /* If library call, skip to end of it. */
3390 {
3395 {
3396 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3397 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3398 notes are OK. */
3404 }
3405 }
3407 count--;
3409 {
3412 }
3413 }
3416 /* If loop_invariant_p ever returned 2, we return 2. */
3418 }
3420 #if 0
3421 /* I don't think this condition is sufficient to allow INSN
3422 to be moved, so we no longer test it. */
3424 /* Return 1 if all insns in the basic block of INSN and following INSN
3425 that set REG are invariant according to TABLE. */
3427 static int
3431 {
3436 {
3445 {
3448 }
3449 }
3450 }
3452 \f
3453 /* Look at all uses (not sets) of registers in X. For each, if it is
3454 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3455 a different insn, set USAGE[REGNO] to const0_rtx. */
3457 static void
3460 rtx insn;
3461 rtx x;
3462 {
3474 {
3475 /* Don't count SET_DEST if it is a REG; otherwise count things
3476 in SET_DEST because if a register is partially modified, it won't
3477 show up as a potential movable so we don't care how USAGE is set
3478 for it. */
3482 }
3483 else
3485 {
3491 }
3492 }
3493 \f
3494 /* Count and record any set in X which is contained in INSN. Update
3495 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3496 in X. */
3498 static void
3503 {
3505 /* Don't move a reg that has an explicit clobber.
3506 It's not worth the pain to try to do it correctly. */
3510 {
3518 {
3522 {
3523 /* If this is the first setting of this reg
3524 in current basic block, and it was set before,
3525 it must be set in two basic blocks, so it cannot
3526 be moved out of the loop. */
3530 /* If this is not first setting in current basic block,
3531 see if reg was used in between previous one and this.
3532 If so, neither one can be moved. */
3539 }
3540 }
3541 }
3542 }
3543 \f
3544 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3545 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3546 contained in insn INSN is used by any insn that precedes INSN in
3547 cyclic order starting from the loop entry point.
3549 We don't want to use INSN_LUID here because if we restrict INSN to those
3550 that have a valid INSN_LUID, it means we cannot move an invariant out
3551 from an inner loop past two loops. */
3553 static int
3557 {
3559 rtx p;
3561 /* Scan forward checking for register usage. If we hit INSN, we
3562 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3564 {
3570 }
3573 }
3574 \f
3576 /* Information we collect about arrays that we might want to prefetch. */
3577 struct prefetch_info
3578 {
3582 index. */
3583 HOST_WIDE_INT index;
3585 iteration. */
3587 prefetch area in one iteration. */
3589 This is set only for loops with known
3590 iteration counts and is 0xffffffff
3591 otherwise. */
3595 };
3597 /* Data used by check_store function. */
3598 struct check_store_data
3599 {
3600 rtx mem_address;
3602 };
3608 /* Set mem_write when mem_address is found. Used as callback to
3609 note_stores. */
3610 static void
3614 {
3619 }
3620 \f
3621 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3622 important to get some addresses combined. Later more sophisticated
3623 transformations can be added when necesary.
3625 ??? Same trick with swapping operand is done at several other places.
3626 It can be nice to develop some common way to handle this. */
3628 static int
3631 {
3645 {
3650 }
3651 /* Compare the elements. If any pair of corresponding elements fails to
3652 match, return 0 for the whole thing. */
3656 {
3658 {
3670 /* Two vectors must have the same length. */
3674 /* And the corresponding elements must match. */
3692 /* These are just backpointers, so they don't matter. */
3698 /* It is believed that rtx's at this level will never
3699 contain anything but integers and other rtx's,
3700 except for within LABEL_REFs and SYMBOL_REFs. */
3703 }
3704 }
3706 }
3707 \f
3708 /* Remove constant addition value from the expression X (when present)
3709 and return it. */
3711 static HOST_WIDE_INT
3714 {
3718 /* Avoid clobbering a shared CONST expression. */
3720 {
3724 {
3727 }
3729 }
3732 {
3735 }
3737 /* For plus expression recurse on ourself. */
3739 {
3743 /* In case our parameter was constant, remove extra zero from the
3744 expression. */
3749 }
3752 }
3754 /* Attempt to identify accesses to arrays that are most likely to cause cache
3755 misses, and emit prefetch instructions a few prefetch blocks forward.
3757 To detect the arrays we use the GIV information that was collected by the
3758 strength reduction pass.
3760 The prefetch instructions are generated after the GIV information is done
3761 and before the strength reduction process. The new GIVs are injected into
3762 the strength reduction tables, so the prefetch addresses are optimized as
3763 well.
3765 GIVs are split into base address, stride, and constant addition values.
3766 GIVs with the same address, stride and close addition values are combined
3767 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3768 for write instructions can be used for the block we write to, on machines
3769 that support write prefetches.
3771 Several heuristics are used to determine when to prefetch. They are
3772 controlled by defined symbols that can be overridden for each target. */
3774 static void
3777 {
3793 /* Consider only loops w/o calls. When a call is done, the loop is probably
3794 slow enough to read the memory. */
3796 {
3801 }
3803 /* Don't prefetch in loops known to have few iterations. */
3807 {
3812 }
3814 /* Search all induction variables and pick those interesting for the prefetch
3815 machinery. */
3817 {
3823 /* Expect all BIVs to be executed in each iteration. This makes our
3824 analysis more conservative. */
3826 {
3827 /* Discard non-constant additions that we can't handle well yet, and
3828 BIVs that are executed multiple times; such BIVs ought to be
3829 handled in the nested loop. We accept not_every_iteration BIVs,
3830 since these only result in larger strides and make our
3831 heuristics more conservative. */
3833 {
3835 {
3841 }
3843 }
3846 {
3848 {
3854 }
3856 }
3860 }
3866 {
3867 rtx address;
3868 rtx temp;
3877 /* See whether an induction variable is interesting to us and if
3878 not, report the reason. */
3882 /* We are interested only in constant stride memory references
3883 in order to be able to compute density easily. */
3887 else
3888 {
3891 {
3894 }
3896 /* On some targets, reversed order prefetches are not
3897 worthwhile. */
3901 /* Prefetch of accesses with an extreme stride might not be
3902 worthwhile, either. */
3907 /* Ignore GIVs with varying add values; we can't predict the
3908 value for the next iteration. */
3912 /* Ignore GIVs in the nested loops; they ought to have been
3913 handled already. */
3916 }
3919 {
3925 }
3927 /* Determine the pointer to the basic array we are examining. It is
3928 the sum of the BIV's initial value and the GIV's add_val. */
3938 /* When the GIV is not always executed, we might be better off by
3939 not dirtying the cache pages. */
3942 else
3943 {
3948 }
3950 /* Attempt to find another prefetch to the same array and see if we
3951 can merge this one. */
3955 {
3956 /* In case both access same array (same location
3957 just with small difference in constant indexes), merge
3958 the prefetches. Just do the later and the earlier will
3959 get prefetched from previous iteration.
3960 The artificial threshold should not be too small,
3961 but also not bigger than small portion of memory usually
3962 traversed by single loop. */
3965 {
3974 }
3978 {
3983 }
3984 }
3986 /* Merging failed. */
3988 {
3996 num_prefetches++;
3998 {
4003 }
4004 }
4005 }
4006 }
4009 {
4012 /* Attempt to calculate the total number of bytes fetched by all
4013 iterations of the loop. Avoid overflow. */
4018 else
4023 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4028 {
4033 }
4034 else
4035 {
4041 }
4042 else
4045 /* Find how many prefetch instructions we'll use within the loop. */
4047 {
4053 }
4054 }
4056 /* Determine how many iterations ahead to prefetch within the loop, based
4057 on how many prefetches we currently expect to do within the loop. */
4059 {
4061 {
4067 }
4068 }
4069 /* We'll also use AHEAD to determine how many prefetch instructions to
4070 emit before a loop, so don't leave it zero. */
4075 {
4076 /* Update if we've decided not to prefetch anything within the loop. */
4080 /* Find how many prefetch instructions we'll use before the loop. */
4082 {
4090 }
4093 {
4115 }
4116 }
4119 {
4120 /* Record that this loop uses prefetch instructions. */
4124 {
4129 }
4130 }
4133 {
4137 {
4139 rtx insn;
4143 rtx seq;
4145 /* We can save some effort by offsetting the address on
4146 architectures with offsettable memory references. */
4149 else
4150 {
4156 }
4159 /* Make sure the address operand is valid for prefetch. */
4169 /* Check all insns emitted and record the new GIV
4170 information. */
4173 {
4178 }
4179 }
4182 {
4183 /* Emit insns before the loop to fetch the first cache lines or,
4184 if we're not prefetching within the loop, everything we expect
4185 to need. */
4187 {
4195 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4196 non-constant INIT_VAL to have the same mode as REG, which
4197 in this case we know to be Pmode. */
4205 loop_start);
4206 }
4207 }
4208 }
4211 }
4212 \f
4213 /* A "basic induction variable" or biv is a pseudo reg that is set
4214 (within this loop) only by incrementing or decrementing it. */
4215 /* A "general induction variable" or giv is a pseudo reg whose
4216 value is a linear function of a biv. */
4218 /* Bivs are recognized by `basic_induction_var';
4219 Givs by `general_induction_var'. */
4221 /* Communication with routines called via `note_stores'. */
4225 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4229 /* ??? Unfinished optimizations, and possible future optimizations,
4230 for the strength reduction code. */
4232 /* ??? The interaction of biv elimination, and recognition of 'constant'
4233 bivs, may cause problems. */
4235 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4236 performance problems.
4238 Perhaps don't eliminate things that can be combined with an addressing
4239 mode. Find all givs that have the same biv, mult_val, and add_val;
4240 then for each giv, check to see if its only use dies in a following
4241 memory address. If so, generate a new memory address and check to see
4242 if it is valid. If it is valid, then store the modified memory address,
4243 otherwise, mark the giv as not done so that it will get its own iv. */
4245 /* ??? Could try to optimize branches when it is known that a biv is always
4246 positive. */
4248 /* ??? When replace a biv in a compare insn, we should replace with closest
4249 giv so that an optimized branch can still be recognized by the combiner,
4250 e.g. the VAX acb insn. */
4252 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4253 was rerun in loop_optimize whenever a register was added or moved.
4254 Also, some of the optimizations could be a little less conservative. */
4255 \f
4256 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4257 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4258 callback.
4260 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4261 least once for every loop iteration except for the last one.
4263 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4264 loop iteration.
4265 */
4266 void
4269 loop_insn_callback fncall;
4270 {
4275 rtx p;
4277 /* If loop_scan_start points to the loop exit test, we have to be wary of
4278 subversive use of gotos inside expression statements. */
4282 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4286 {
4289 /* Past CODE_LABEL, we get to insns that may be executed multiple
4290 times. The only way we can be sure that they can't is if every
4291 jump insn between here and the end of the loop either
4292 returns, exits the loop, is a jump to a location that is still
4293 behind the label, or is a jump to the loop start. */
4296 {
4302 {
4307 {
4310 else
4314 }
4322 {
4325 }
4326 }
4327 }
4329 /* Past a jump, we get to insns for which we can't count
4330 on whether they will be executed during each iteration. */
4331 /* This code appears twice in strength_reduce. There is also similar
4332 code in scan_loop. */
4334 /* If we enter the loop in the middle, and scan around to the
4335 beginning, don't set not_every_iteration for that.
4336 This can be any kind of jump, since we want to know if insns
4337 will be executed if the loop is executed. */
4342 {
4345 /* If this is a jump outside the loop, then it also doesn't
4346 matter. Check to see if the target of this branch is on the
4347 loop->exits_labels list. */
4355 }
4358 {
4359 /* At the virtual top of a converted loop, insns are again known to
4360 be executed each iteration: logically, the loop begins here
4361 even though the exit code has been duplicated.
4363 Insns are also again known to be executed each iteration at
4364 the LOOP_CONT note. */
4370 loop_depth++;
4372 loop_depth--;
4373 }
4375 /* Note if we pass a loop latch. If we do, then we can not clear
4376 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4377 a loop since a jump before the last CODE_LABEL may have started
4378 a new loop iteration.
4380 Note that LOOP_TOP is only set for rotated loops and we need
4381 this check for all loops, so compare against the CODE_LABEL
4382 which immediately follows LOOP_START. */
4387 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4388 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4389 or not an insn is known to be executed each iteration of the
4390 loop, whether or not any iterations are known to occur.
4392 Therefore, if we have just passed a label and have no more labels
4393 between here and the test insn of the loop, and we have not passed
4394 a jump to the top of the loop, then we know these insns will be
4395 executed each iteration. */
4398 && !past_loop_latch
4403 }
4404 }
4405 \f
4406 static void
4409 {
4412 /* Temporary list pointers for traversing ivs->list. */
4419 /* Scan ivs->list to remove all regs that proved not to be bivs.
4420 Make a sanity check against regs->n_times_set. */
4422 {
4424 /* Above happens if register modified by subreg, etc. */
4425 /* Make sure it is not recognized as a basic induction var: */
4427 /* If never incremented, it is invariant that we decided not to
4428 move. So leave it alone. */
4430 {
4441 }
4442 else
4443 {
4448 }
4449 }
4450 }
4453 /* Determine how BIVS are initialized by looking through pre-header
4454 extended basic block. */
4455 static void
4458 {
4460 /* Temporary list pointers for traversing ivs->list. */
4463 rtx p;
4465 /* Find initial value for each biv by searching backwards from loop_start,
4466 halting at first label. Also record any test condition. */
4470 {
4471 rtx test;
4481 /* Record any test of a biv that branches around the loop if no store
4482 between it and the start of loop. We only care about tests with
4483 constants and registers and only certain of those. */
4493 {
4494 /* If an NE test, we have an initial value! */
4496 {
4500 }
4501 else
4503 }
4504 }
4505 }
4508 /* Look at the each biv and see if we can say anything better about its
4509 initial value from any initializing insns set up above. (This is done
4510 in two passes to avoid missing SETs in a PARALLEL.) */
4511 static void
4514 {
4516 /* Temporary list pointers for traversing ivs->list. */
4521 {
4522 rtx src;
4523 rtx note;
4528 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4529 is a constant, use the value of that. */
4535 else
4548 {
4552 {
4555 }
4556 }
4557 /* If we can't make it a giv,
4558 let biv keep initial value of "itself". */
4561 }
4562 }
4565 /* Search the loop for general induction variables. */
4567 static void
4570 {
4572 }
4575 /* For each giv for which we still don't know whether or not it is
4576 replaceable, check to see if it is replaceable because its final value
4577 can be calculated. */
4579 static void
4582 {
4587 {
4593 }
4594 }
4597 /* Return nonzero if it is possible to eliminate the biv BL provided
4598 all givs are reduced. This is possible if either the reg is not
4599 used outside the loop, or we can compute what its final value will
4600 be. */
4602 static int
4608 {
4609 /* For architectures with a decrement_and_branch_until_zero insn,
4610 don't do this if we put a REG_NONNEG note on the endtest for this
4611 biv. */
4613 #ifdef HAVE_decrement_and_branch_until_zero
4615 {
4620 }
4621 #endif
4623 /* Check that biv is used outside loop or if it has a final value.
4624 Compare against bl->init_insn rather than loop->start. We aren't
4625 concerned with any uses of the biv between init_insn and
4626 loop->start since these won't be affected by the value of the biv
4627 elsewhere in the function, so long as init_insn doesn't use the
4628 biv itself. */
4639 {
4647 }
4649 }
4652 /* Reduce each giv of BL that we have decided to reduce. */
4654 static void
4658 {
4662 {
4665 {
4668 /* If the code for derived givs immediately below has already
4669 allocated a new_reg, we must keep it. */
4673 #ifdef AUTO_INC_DEC
4674 /* If the target has auto-increment addressing modes, and
4675 this is an address giv, then try to put the increment
4676 immediately after its use, so that flow can create an
4677 auto-increment addressing mode. */
4680 /* We don't handle reversed biv's because bl->biv->insn
4681 does not have a valid INSN_LUID. */
4685 {
4686 /* If other giv's have been combined with this one, then
4687 this will work only if all uses of the other giv's occur
4688 before this giv's insn. This is difficult to check.
4690 We simplify this by looking for the common case where
4691 there is one DEST_REG giv, and this giv's insn is the
4692 last use of the dest_reg of that DEST_REG giv. If the
4693 increment occurs after the address giv, then we can
4694 perform the optimization. (Otherwise, the increment
4695 would have to go before other_giv, and we would not be
4696 able to combine it with the address giv to get an
4697 auto-inc address.) */
4699 {
4704 {
4707 else
4709 }
4716 }
4717 /* Check for case where increment is before the address
4718 giv. Do this test in "loop order". */
4727 else
4730 #ifdef HAVE_cc0
4731 {
4732 rtx prev;
4734 /* We can't put an insn immediately after one setting
4735 cc0, or immediately before one using cc0. */
4742 }
4743 #endif
4747 }
4748 #endif
4750 /* For each place where the biv is incremented, add an insn
4751 to increment the new, reduced reg for the giv. */
4753 {
4754 rtx insert_before;
4760 else
4768 /* A multiply is acceptable here
4769 since this is presumed to be seldom executed. */
4773 }
4775 /* Add code at loop start to initialize giv's reduced reg. */
4780 }
4781 }
4782 }
4785 /* Check for givs whose first use is their definition and whose
4786 last use is the definition of another giv. If so, it is likely
4787 dead and should not be used to derive another giv nor to
4788 eliminate a biv. */
4790 static void
4794 {
4798 {
4805 {
4811 }
4812 }
4813 }
4816 static void
4821 {
4825 {
4832 /* Update expression if this was combined, in case other giv was
4833 replaced. */
4838 /* See if this register is known to be a pointer to something. If
4839 so, see if we can find the alignment. First see if there is a
4840 destination register that is a pointer. If so, this shares the
4841 alignment too. Next see if we can deduce anything from the
4842 computational information. If not, and this is a DEST_ADDR
4843 giv, at least we know that it's a pointer, though we don't know
4844 the alignment. */
4852 {
4861 }
4865 {
4873 }
4878 /* Store reduced reg as the address in the memref where we found
4879 this giv. */
4882 {
4884 }
4885 else
4886 {
4888 rtx note;
4890 /* Not replaceable; emit an insn to set the original giv reg from
4891 the reduced giv, same as above. */
4896 /* The original insn may have a REG_EQUAL note. This note is
4897 now incorrect and may result in invalid substitutions later.
4898 The original insn is dead, but may be part of a libcall
4899 sequence, which doesn't seem worth the bother of handling. */
4903 }
4905 /* When a loop is reversed, givs which depend on the reversed
4906 biv, and which are live outside the loop, must be set to their
4907 correct final value. This insn is only needed if the giv is
4908 not replaceable. The correct final value is the same as the
4909 value that the giv starts the reversed loop with. */
4920 {
4925 }
4926 }
4927 }
4930 static int
4935 rtx test_reg;
4936 {
4945 /* Reduce benefit if not replaceable, since we will insert a
4946 move-insn to replace the insn that calculates this giv. Don't do
4947 this unless the giv is a user variable, since it will often be
4948 marked non-replaceable because of the duplication of the exit
4949 code outside the loop. In such a case, the copies we insert are
4950 dead and will be deleted. So they don't have a cost. Similar
4951 situations exist. */
4952 /* ??? The new final_[bg]iv_value code does a much better job of
4953 finding replaceable giv's, and hence this code may no longer be
4954 necessary. */
4959 /* Decrease the benefit to count the add-insns that we will insert
4960 to increment the reduced reg for the giv. ??? This can
4961 overestimate the run-time cost of the additional insns, e.g. if
4962 there are multiple basic blocks that increment the biv, but only
4963 one of these blocks is executed during each iteration. There is
4964 no good way to detect cases like this with the current structure
4965 of the loop optimizer. This code is more accurate for
4966 determining code size than run-time benefits. */
4969 /* Decide whether to strength-reduce this giv or to leave the code
4970 unchanged (recompute it from the biv each time it is used). This
4971 decision can be made independently for each giv. */
4973 #ifdef AUTO_INC_DEC
4974 /* Attempt to guess whether autoincrement will handle some of the
4975 new add insns; if so, increase BENEFIT (undo the subtraction of
4976 add_cost that was done above). */
4978 /* Increasing the benefit is risky, since this is only a guess.
4979 Avoid increasing register pressure in cases where there would
4980 be no other benefit from reducing this giv. */
4983 {
4998 }
4999 #endif
5002 }
5005 /* Free IV structures for LOOP. */
5007 static void
5010 {
5017 {
5023 {
5026 }
5028 {
5031 }
5035 }
5036 }
5039 /* Perform strength reduction and induction variable elimination.
5041 Pseudo registers created during this function will be beyond the
5042 last valid index in several tables including
5043 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5044 problem here, because the added registers cannot be givs outside of
5045 their loop, and hence will never be reconsidered. But scan_loop
5046 must check regnos to make sure they are in bounds. */
5048 static void
5052 {
5056 rtx p;
5057 /* Temporary list pointer for traversing ivs->list. */
5059 /* Ratio of extra register life span we can justify
5060 for saving an instruction. More if loop doesn't call subroutines
5061 since in that case saving an insn makes more difference
5062 and more registers are available. */
5063 /* ??? could set this to last value of threshold in move_movables */
5065 /* Map of pseudo-register replacements. */
5077 /* Find all BIVs in loop. */
5080 /* Exit if there are no bivs. */
5082 {
5083 /* Can still unroll the loop anyways, but indicate that there is no
5084 strength reduction info available. */
5090 }
5092 /* Determine how BIVS are initialized by looking through pre-header
5093 extended basic block. */
5096 /* Look at the each biv and see if we can say anything better about its
5097 initial value from any initializing insns set up above. */
5100 /* Search the loop for general induction variables. */
5103 /* Try to calculate and save the number of loop iterations. This is
5104 set to zero if the actual number can not be calculated. This must
5105 be called after all giv's have been identified, since otherwise it may
5106 fail if the iteration variable is a giv. */
5109 #ifdef HAVE_prefetch
5112 #endif
5114 /* Now for each giv for which we still don't know whether or not it is
5115 replaceable, check to see if it is replaceable because its final value
5116 can be calculated. This must be done after loop_iterations is called,
5117 so that final_giv_value will work correctly. */
5120 /* Try to prove that the loop counter variable (if any) is always
5121 nonnegative; if so, record that fact with a REG_NONNEG note
5122 so that "decrement and branch until zero" insn can be used. */
5125 /* Create reg_map to hold substitutions for replaceable giv regs.
5126 Some givs might have been made from biv increments, so look at
5127 ivs->reg_iv_type for a suitable size. */
5131 /* Examine each iv class for feasibility of strength reduction/induction
5132 variable elimination. */
5135 {
5139 /* Test whether it will be possible to eliminate this biv
5140 provided all givs are reduced. */
5143 /* This will be true at the end, if all givs which depend on this
5144 biv have been strength reduced.
5145 We can't (currently) eliminate the biv unless this is so. */
5148 /* Check each extension dependent giv in this class to see if its
5149 root biv is safe from wrapping in the interior mode. */
5152 /* Combine all giv's for this iv_class. */
5156 {
5164 /* If an insn is not to be strength reduced, then set its ignore
5165 flag, and clear bl->all_reduced. */
5167 /* A giv that depends on a reversed biv must be reduced if it is
5168 used after the loop exit, otherwise, it would have the wrong
5169 value after the loop exit. To make it simple, just reduce all
5170 of such giv's whether or not we know they are used after the loop
5171 exit. */
5176 {
5184 }
5185 else
5186 {
5187 /* Check that we can increment the reduced giv without a
5188 multiply insn. If not, reject it. */
5193 {
5201 }
5202 }
5203 }
5205 /* Check for givs whose first use is their definition and whose
5206 last use is the definition of another giv. If so, it is likely
5207 dead and should not be used to derive another giv nor to
5208 eliminate a biv. */
5211 /* Reduce each giv that we decided to reduce. */
5214 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5215 as not reduced.
5217 For each giv register that can be reduced now: if replaceable,
5218 substitute reduced reg wherever the old giv occurs;
5219 else add new move insn "giv_reg = reduced_reg". */
5222 /* All the givs based on the biv bl have been reduced if they
5223 merit it. */
5225 /* For each giv not marked as maybe dead that has been combined with a
5226 second giv, clear any "maybe dead" mark on that second giv.
5227 v->new_reg will either be or refer to the register of the giv it
5228 combined with.
5230 Doing this clearing avoids problems in biv elimination where
5231 a giv's new_reg is a complex value that can't be put in the
5232 insn but the giv combined with (with a reg as new_reg) is
5233 marked maybe_dead. Since the register will be used in either
5234 case, we'd prefer it be used from the simpler giv. */
5240 /* Try to eliminate the biv, if it is a candidate.
5241 This won't work if ! bl->all_reduced,
5242 since the givs we planned to use might not have been reduced.
5244 We have to be careful that we didn't initially think we could
5245 eliminate this biv because of a giv that we now think may be
5246 dead and shouldn't be used as a biv replacement.
5248 Also, there is the possibility that we may have a giv that looks
5249 like it can be used to eliminate a biv, but the resulting insn
5250 isn't valid. This can happen, for example, on the 88k, where a
5251 JUMP_INSN can compare a register only with zero. Attempts to
5252 replace it with a compare with a constant will fail.
5254 Note that in cases where this call fails, we may have replaced some
5255 of the occurrences of the biv with a giv, but no harm was done in
5256 doing so in the rare cases where it can occur. */
5260 {
5261 /* ?? If we created a new test to bypass the loop entirely,
5262 or otherwise drop straight in, based on this test, then
5263 we might want to rewrite it also. This way some later
5264 pass has more hope of removing the initialization of this
5265 biv entirely. */
5267 /* If final_value != 0, then the biv may be used after loop end
5268 and we must emit an insn to set it just in case.
5270 Reversed bivs already have an insn after the loop setting their
5271 value, so we don't need another one. We can't calculate the
5272 proper final value for such a biv here anyways. */
5281 }
5282 /* See above note wrt final_value. But since we couldn't eliminate
5283 the biv, we must set the value after the loop instead of before. */
5287 }
5289 /* Go through all the instructions in the loop, making all the
5290 register substitutions scheduled in REG_MAP. */
5295 {
5299 }
5302 {
5303 /* When we completely unroll a loop we will likely not need the increment
5304 of the loop BIV and we will not need the conditional branch at the
5305 end of the loop. */
5308 #ifdef HAVE_cc0
5309 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5310 need the comparison before the conditional branch at the end of the
5311 loop. */
5313 #endif
5315 /* We'll need one copy for each loop iteration. */
5318 /* A little slop to account for the ability to remove initialization
5319 code, better CSE, and other secondary benefits of completely
5320 unrolling some loops. */
5323 /* Clamp the value. */
5326 }
5328 /* Unroll loops from within strength reduction so that we can use the
5329 induction variable information that strength_reduce has already
5330 collected. Always unroll loops that would be as small or smaller
5331 unrolled than when rolled. */
5338 #ifdef HAVE_doloop_end
5343 /* In case number of iterations is known, drop branch prediction note
5344 in the branch. Do that only in second loop pass, as loop unrolling
5345 may change the number of iterations performed. */
5347 {
5348 unsigned HOST_WIDE_INT n
5353 }
5361 }
5362 \f
5363 /*Record all basic induction variables calculated in the insn. */
5364 static rtx
5367 rtx p;
5370 {
5372 rtx set;
5373 rtx dest_reg;
5374 rtx inc_val;
5375 rtx mult_val;
5381 {
5386 {
5391 {
5392 /* It is a possible basic induction variable.
5393 Create and initialize an induction structure for it. */
5401 }
5404 }
5405 }
5407 }
5408 \f
5409 /* Record all givs calculated in the insn.
5410 A register is a giv if: it is only set once, it is a function of a
5411 biv and a constant (or invariant), and it is not a biv. */
5412 static rtx
5415 rtx p;
5418 {
5421 rtx set;
5422 /* Look for a general induction variable in a register. */
5427 {
5428 rtx src_reg;
5429 rtx dest_reg;
5430 rtx add_val;
5431 rtx mult_val;
5432 rtx ext_val;
5435 rtx last_consec_insn;
5444 /* Equivalent expression is a giv. */
5449 /* Don't try to handle any regs made by loop optimization.
5450 We have nothing on them in regno_first_uid, etc. */
5452 /* Don't recognize a BASIC_INDUCT_VAR here. */
5454 /* This must be the only place where the register is set. */
5456 /* or all sets must be consecutive and make a giv. */
5461 {
5465 /* If this is a library call, increase benefit. */
5469 /* Skip the consecutive insns, if there are any. */
5477 }
5478 }
5480 #ifndef DONT_REDUCE_ADDR
5481 /* Look for givs which are memory addresses. */
5482 /* This resulted in worse code on a VAX 8600. I wonder if it
5483 still does. */
5486 maybe_multiple);
5487 #endif
5489 /* Update the status of whether giv can derive other givs. This can
5490 change when we pass a label or an insn that updates a biv. */
5495 }
5496 \f
5497 /* Return 1 if X is a valid source for an initial value (or as value being
5498 compared against in an initial test).
5500 X must be either a register or constant and must not be clobbered between
5501 the current insn and the start of the loop.
5503 INSN is the insn containing X. */
5505 static int
5507 rtx x;
5508 rtx insn;
5510 rtx loop_start;
5511 {
5515 /* Only consider pseudos we know about initialized in insns whose luids
5516 we know. */
5521 /* Don't use call-clobbered registers across a call which clobbers it. On
5522 some machines, don't use any hard registers at all. */
5524 && (SMALL_REGISTER_CLASSES
5528 /* Don't use registers that have been clobbered before the start of the
5529 loop. */
5534 }
5535 \f
5536 /* Scan X for memory refs and check each memory address
5537 as a possible giv. INSN is the insn whose pattern X comes from.
5538 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5539 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5540 more thanonce in each loop iteration. */
5542 static void
5545 rtx x;
5546 rtx insn;
5548 {
5558 {
5574 {
5575 rtx src_reg;
5576 rtx add_val;
5577 rtx mult_val;
5578 rtx ext_val;
5581 /* This code used to disable creating GIVs with mult_val == 1 and
5582 add_val == 0. However, this leads to lost optimizations when
5583 it comes time to combine a set of related DEST_ADDR GIVs, since
5584 this one would not be seen. */
5589 {
5590 /* Found one; record it. */
5599 }
5600 }
5605 }
5607 /* Recursively scan the subexpressions for other mem refs. */
5613 maybe_multiple);
5617 maybe_multiple);
5618 }
5619 \f
5620 /* Fill in the data about one biv update.
5621 V is the `struct induction' in which we record the biv. (It is
5622 allocated by the caller, with alloca.)
5623 INSN is the insn that sets it.
5624 DEST_REG is the biv's reg.
5626 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5627 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5628 being set to INC_VAL.
5630 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5631 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5632 can be executed more than once per iteration. If MAYBE_MULTIPLE
5633 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5634 executed exactly once per iteration. */
5636 static void
5641 rtx insn;
5642 rtx dest_reg;
5643 rtx inc_val;
5644 rtx mult_val;
5648 {
5664 /* Add this to the reg's iv_class, creating a class
5665 if this is the first incrementation of the reg. */
5669 {
5670 /* Create and initialize new iv_class. */
5680 /* Set initial value to the reg itself. */
5683 /* We haven't seen the initializing insn yet */
5693 /* Add this class to ivs->list. */
5697 /* Put it in the array of biv register classes. */
5699 }
5701 /* Update IV_CLASS entry for this biv. */
5710 }
5711 \f
5712 /* Fill in the data about one giv.
5713 V is the `struct induction' in which we record the giv. (It is
5714 allocated by the caller, with alloca.)
5715 INSN is the insn that sets it.
5716 BENEFIT estimates the savings from deleting this insn.
5717 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5718 into a register or is used as a memory address.
5720 SRC_REG is the biv reg which the giv is computed from.
5721 DEST_REG is the giv's reg (if the giv is stored in a reg).
5722 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5723 LOCATION points to the place where this giv's value appears in INSN. */
5725 static void
5730 rtx insn;
5731 rtx src_reg;
5732 rtx dest_reg;
5738 {
5743 rtx temp;
5745 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5746 undo the MULT canonicalization that we performed earlier. */
5776 /* The v->always_computable field is used in update_giv_derive, to
5777 determine whether a giv can be used to derive another giv. For a
5778 DEST_REG giv, INSN computes a new value for the giv, so its value
5779 isn't computable if INSN insn't executed every iteration.
5780 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5781 it does not compute a new value. Hence the value is always computable
5782 regardless of whether INSN is executed each iteration. */
5786 else
5792 {
5795 }
5797 {
5802 /* If the lifetime is zero, it means that this register is
5803 really a dead store. So mark this as a giv that can be
5804 ignored. This will not prevent the biv from being eliminated. */
5810 }
5812 /* Add the giv to the class of givs computed from one biv. */
5816 {
5819 /* Don't count DEST_ADDR. This is supposed to count the number of
5820 insns that calculate givs. */
5824 }
5825 else
5826 /* Fatal error, biv missing for this giv? */
5830 {
5833 }
5834 else
5835 {
5836 /* The giv can be replaced outright by the reduced register only if all
5837 of the following conditions are true:
5838 - the insn that sets the giv is always executed on any iteration
5839 on which the giv is used at all
5840 (there are two ways to deduce this:
5841 either the insn is executed on every iteration,
5842 or all uses follow that insn in the same basic block),
5843 - the giv is not used outside the loop
5844 - no assignments to the biv occur during the giv's lifetime. */
5847 /* Previous line always fails if INSN was moved by loop opt. */
5850 && (! not_every_iteration
5852 {
5853 /* Now check that there are no assignments to the biv within the
5854 giv's lifetime. This requires two separate checks. */
5856 /* Check each biv update, and fail if any are between the first
5857 and last use of the giv.
5859 If this loop contains an inner loop that was unrolled, then
5860 the insn modifying the biv may have been emitted by the loop
5861 unrolling code, and hence does not have a valid luid. Just
5862 mark the biv as not replaceable in this case. It is not very
5863 useful as a biv, because it is used in two different loops.
5864 It is very unlikely that we would be able to optimize the giv
5865 using this biv anyways. */
5870 {
5876 {
5880 }
5881 }
5883 /* If there are any backwards branches that go from after the
5884 biv update to before it, then this giv is not replaceable. */
5888 {
5892 }
5893 }
5894 else
5895 {
5896 /* May still be replaceable, we don't have enough info here to
5897 decide. */
5900 }
5901 }
5903 /* Record whether the add_val contains a const_int, for later use by
5904 combine_givs. */
5905 {
5910 ;
5914 {
5916 {
5921 else
5923 }
5926 }
5927 }
5931 }
5933 /* All this does is determine whether a giv can be made replaceable because
5934 its final value can be calculated. This code can not be part of record_giv
5935 above, because final_giv_value requires that the number of loop iterations
5936 be known, and that can not be accurately calculated until after all givs
5937 have been identified. */
5939 static void
5943 {
5946 /* DEST_ADDR givs will never reach here, because they are always marked
5947 replaceable above in record_giv. */
5949 /* The giv can be replaced outright by the reduced register only if all
5950 of the following conditions are true:
5951 - the insn that sets the giv is always executed on any iteration
5952 on which the giv is used at all
5953 (there are two ways to deduce this:
5954 either the insn is executed on every iteration,
5955 or all uses follow that insn in the same basic block),
5956 - its final value can be calculated (this condition is different
5957 than the one above in record_giv)
5958 - it's not used before the it's set
5959 - no assignments to the biv occur during the giv's lifetime. */
5961 #if 0
5962 /* This is only called now when replaceable is known to be false. */
5963 /* Clear replaceable, so that it won't confuse final_giv_value. */
5965 #endif
5970 {
5973 rtx last_giv_use;
5978 /* When trying to determine whether or not a biv increment occurs
5979 during the lifetime of the giv, we can ignore uses of the variable
5980 outside the loop because final_value is true. Hence we can not
5981 use regno_last_uid and regno_first_uid as above in record_giv. */
5983 /* Search the loop to determine whether any assignments to the
5984 biv occur during the giv's lifetime. Start with the insn
5985 that sets the giv, and search around the loop until we come
5986 back to that insn again.
5988 Also fail if there is a jump within the giv's lifetime that jumps
5989 to somewhere outside the lifetime but still within the loop. This
5990 catches spaghetti code where the execution order is not linear, and
5991 hence the above test fails. Here we assume that the giv lifetime
5992 does not extend from one iteration of the loop to the next, so as
5993 to make the test easier. Since the lifetime isn't known yet,
5994 this requires two loops. See also record_giv above. */
5999 {
6002 {
6005 }
6011 {
6012 /* It is possible for the BIV increment to use the GIV if we
6013 have a cycle. Thus we must be sure to check each insn for
6014 both BIV and GIV uses, and we must check for BIV uses
6015 first. */
6022 {
6024 {
6028 }
6030 }
6031 }
6032 }
6034 /* Now that the lifetime of the giv is known, check for branches
6035 from within the lifetime to outside the lifetime if it is still
6036 replaceable. */
6039 {
6042 {
6055 {
6064 }
6065 }
6066 }
6068 /* If it is replaceable, then save the final value. */
6071 }
6076 }
6077 \f
6078 /* Update the status of whether a giv can derive other givs.
6080 We need to do something special if there is or may be an update to the biv
6081 between the time the giv is defined and the time it is used to derive
6082 another giv.
6084 In addition, a giv that is only conditionally set is not allowed to
6085 derive another giv once a label has been passed.
6087 The cases we look at are when a label or an update to a biv is passed. */
6089 static void
6092 rtx p;
6093 {
6097 rtx tem;
6100 /* Search all IV classes, then all bivs, and finally all givs.
6102 There are three cases we are concerned with. First we have the situation
6103 of a giv that is only updated conditionally. In that case, it may not
6104 derive any givs after a label is passed.
6106 The second case is when a biv update occurs, or may occur, after the
6107 definition of a giv. For certain biv updates (see below) that are
6108 known to occur between the giv definition and use, we can adjust the
6109 giv definition. For others, or when the biv update is conditional,
6110 we must prevent the giv from deriving any other givs. There are two
6111 sub-cases within this case.
6113 If this is a label, we are concerned with any biv update that is done
6114 conditionally, since it may be done after the giv is defined followed by
6115 a branch here (actually, we need to pass both a jump and a label, but
6116 this extra tracking doesn't seem worth it).
6118 If this is a jump, we are concerned about any biv update that may be
6119 executed multiple times. We are actually only concerned about
6120 backward jumps, but it is probably not worth performing the test
6121 on the jump again here.
6123 If this is a biv update, we must adjust the giv status to show that a
6124 subsequent biv update was performed. If this adjustment cannot be done,
6125 the giv cannot derive further givs. */
6131 {
6133 {
6134 /* If cant_derive is already true, there is no point in
6135 checking all of these conditions again. */
6139 /* If this giv is conditionally set and we have passed a label,
6140 it cannot derive anything. */
6144 /* Skip givs that have mult_val == 0, since
6145 they are really invariants. Also skip those that are
6146 replaceable, since we know their lifetime doesn't contain
6147 any biv update. */
6151 /* The only way we can allow this giv to derive another
6152 is if this is a biv increment and we can form the product
6153 of biv->add_val and giv->mult_val. In this case, we will
6154 be able to compute a compensation. */
6156 {
6157 rtx ext_val_dummy;
6168 tem = simplify_giv_expr
6175 else
6177 }
6181 }
6182 }
6183 }
6184 \f
6185 /* Check whether an insn is an increment legitimate for a basic induction var.
6186 X is the source of insn P, or a part of it.
6187 MODE is the mode in which X should be interpreted.
6189 DEST_REG is the putative biv, also the destination of the insn.
6190 We accept patterns of these forms:
6191 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6192 REG = INVARIANT + REG
6194 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6195 store the additive term into *INC_VAL, and store the place where
6196 we found the additive term into *LOCATION.
6198 If X is an assignment of an invariant into DEST_REG, we set
6199 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6201 We also want to detect a BIV when it corresponds to a variable
6202 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6203 of the variable may be a PLUS that adds a SUBREG of that variable to
6204 an invariant and then sign- or zero-extends the result of the PLUS
6205 into the variable.
6207 Most GIVs in such cases will be in the promoted mode, since that is the
6208 probably the natural computation mode (and almost certainly the mode
6209 used for addresses) on the machine. So we view the pseudo-reg containing
6210 the variable as the BIV, as if it were simply incremented.
6212 Note that treating the entire pseudo as a BIV will result in making
6213 simple increments to any GIVs based on it. However, if the variable
6214 overflows in its declared mode but not its promoted mode, the result will
6215 be incorrect. This is acceptable if the variable is signed, since
6216 overflows in such cases are undefined, but not if it is unsigned, since
6217 those overflows are defined. So we only check for SIGN_EXTEND and
6218 not ZERO_EXTEND.
6220 If we cannot find a biv, we return 0. */
6222 static int
6225 rtx x;
6227 rtx dest_reg;
6228 rtx p;
6232 {
6240 {
6246 {
6248 }
6253 {
6255 }
6256 else
6269 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6270 handle addition of promoted variables.
6271 ??? The comment at the start of this function is wrong: promoted
6272 variable increments don't look like it says they do. */
6278 /* If this register is assigned in a previous insn, look at its
6279 source, but don't go outside the loop or past a label. */
6281 /* If this sets a register to itself, we would repeat any previous
6282 biv increment if we applied this strategy blindly. */
6288 {
6289 rtx dest;
6290 do
6291 {
6293 }
6322 }
6323 /* Fall through. */
6325 /* Can accept constant setting of biv only when inside inner most loop.
6326 Otherwise, a biv of an inner loop may be incorrectly recognized
6327 as a biv of the outer loop,
6328 causing code to be moved INTO the inner loop. */
6335 /* convert_modes aborts if we try to convert to or from CCmode, so just
6336 exclude that case. It is very unlikely that a condition code value
6337 would be a useful iterator anyways. convert_modes aborts if we try to
6338 convert a float mode to non-float or vice versa too. */
6342 {
6343 /* Possible bug here? Perhaps we don't know the mode of X. */
6347 }
6348 else
6356 /* Similar, since this can be a sign extension. */
6361 ;
6375 location);
6380 }
6381 }
6382 \f
6383 /* A general induction variable (giv) is any quantity that is a linear
6384 function of a basic induction variable,
6385 i.e. giv = biv * mult_val + add_val.
6386 The coefficients can be any loop invariant quantity.
6387 A giv need not be computed directly from the biv;
6388 it can be computed by way of other givs. */
6390 /* Determine whether X computes a giv.
6391 If it does, return a nonzero value
6392 which is the benefit from eliminating the computation of X;
6393 set *SRC_REG to the register of the biv that it is computed from;
6394 set *ADD_VAL and *MULT_VAL to the coefficients,
6395 such that the value of X is biv * mult + add; */
6397 static int
6401 rtx x;
6409 {
6413 /* If this is an invariant, forget it, it isn't a giv. */
6424 {
6427 /* Since this is now an invariant and wasn't before, it must be a giv
6428 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6429 with. */
6436 /* This is equivalent to a BIV. */
6443 /* Either (plus (biv) (invar)) or
6444 (plus (mult (biv) (invar_1)) (invar_2)). */
6446 {
6449 }
6450 else
6451 {
6454 }
6459 /* ADD_VAL is zero. */
6467 }
6469 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6470 unless they are CONST_INT). */
6478 else
6481 /* Always return true if this is a giv so it will be detected as such,
6482 even if the benefit is zero or negative. This allows elimination
6483 of bivs that might otherwise not be eliminated. */
6485 }
6486 \f
6487 /* Given an expression, X, try to form it as a linear function of a biv.
6488 We will canonicalize it to be of the form
6489 (plus (mult (BIV) (invar_1))
6490 (invar_2))
6491 with possible degeneracies.
6493 The invariant expressions must each be of a form that can be used as a
6494 machine operand. We surround then with a USE rtx (a hack, but localized
6495 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6496 routine; it is the caller's responsibility to strip them.
6498 If no such canonicalization is possible (i.e., two biv's are used or an
6499 expression that is neither invariant nor a biv or giv), this routine
6500 returns 0.
6502 For a nonzero return, the result will have a code of CONST_INT, USE,
6503 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6505 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6510 static rtx
6513 rtx x;
6516 {
6521 rtx tem;
6523 /* If this is not an integer mode, or if we cannot do arithmetic in this
6524 mode, this can't be a giv. */
6531 {
6538 /* Put constant last, CONST_INT last if both constant. */
6546 /* Handle addition of zero, then addition of an invariant. */
6551 {
6554 /* Adding two invariants must result in an invariant, so enclose
6555 addition operation inside a USE and return it. */
6565 else
6574 /* biv + invar or mult + invar. Return sum. */
6578 /* (a + invar_1) + invar_2. Associate. */
6579 return
6585 arg1)),
6590 }
6592 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6593 MULT to reduce cases. */
6599 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6600 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6601 Recurse to associate the second PLUS. */
6606 return
6614 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6630 /* Handle "a - b" as "a + b * (-1)". */
6636 constm1_rtx)),
6645 /* Put constant last, CONST_INT last if both constant. */
6650 /* If second argument is not now constant, not giv. */
6654 /* Handle multiply by 0 or 1. */
6662 {
6664 /* biv * invar. Done. */
6668 /* Product of two constants. */
6672 /* invar * invar is a giv, but attempt to simplify it somehow. */
6678 {
6679 /* (invar_0 * invar_1) * invar_2. Associate. */
6686 arg1)),
6688 }
6689 /* Porpagate the MULT expressions to the intermost nodes. */
6691 {
6692 /* (invar_0 + invar_1) * invar_2. Distribute. */
6698 arg1),
6702 arg1)),
6704 }
6708 /* (a * invar_1) * invar_2. Associate. */
6714 arg1)),
6718 /* (a + invar_1) * invar_2. Distribute. */
6723 arg1),
6726 arg1)),
6731 }
6734 /* Shift by constant is multiply by power of two. */
6738 return
6747 /* "-a" is "a * (-1)" */
6753 /* "~a" is "-a - 1". Silly, but easy. */
6757 const1_rtx),
6761 /* Already in proper form for invariant. */
6767 /* Conditionally recognize extensions of simple IVs. After we've
6768 computed loop traversal counts and verified the range of the
6769 source IV, we'll reevaluate this as a GIV. */
6771 {
6774 {
6777 }
6778 }
6782 /* If this is a new register, we can't deal with it. */
6786 /* Check for biv or giv. */
6788 {
6792 {
6795 /* Form expression from giv and add benefit. Ensure this giv
6796 can derive another and subtract any needed adjustment if so. */
6798 /* Increasing the benefit here is risky. The only case in which it
6799 is arguably correct is if this is the only use of V. In other
6800 cases, this will artificially inflate the benefit of the current
6801 giv, and lead to suboptimal code. Thus, it is disabled, since
6802 potentially not reducing an only marginally beneficial giv is
6803 less harmful than reducing many givs that are not really
6804 beneficial. */
6805 {
6809 }
6822 {
6825 }
6826 else
6827 {
6830 }
6832 }
6835 do_default:
6836 /* If it isn't an induction variable, and it is invariant, we
6837 may be able to simplify things further by looking through
6838 the bits we just moved outside the loop. */
6840 {
6846 {
6847 /* Ok, we found a match. Substitute and simplify. */
6849 /* If we match another movable, we must use that, as
6850 this one is going away. */
6855 /* If consec is nonzero, this is a member of a group of
6856 instructions that were moved together. We handle this
6857 case only to the point of seeking to the last insn and
6858 looking for a REG_EQUAL. Fail if we don't find one. */
6860 {
6863 do
6864 {
6866 }
6872 }
6873 else
6874 {
6878 }
6881 {
6882 /* What we are most interested in is pointer
6883 arithmetic on invariants -- only take
6884 patterns we may be able to do something with. */
6890 {
6892 benefit);
6895 }
6900 {
6905 }
6906 }
6908 }
6909 }
6911 }
6913 /* Fall through to general case. */
6915 /* If invariant, return as USE (unless CONST_INT).
6916 Otherwise, not giv. */
6921 {
6930 }
6931 else
6933 }
6934 }
6936 /* This routine folds invariants such that there is only ever one
6937 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6939 static rtx
6942 {
6948 {
6951 }
6954 {
6957 }
6958 else
6959 {
6962 }
6963 }
6965 static rtx
6969 {
6971 {
6975 else
6978 }
6981 else
6984 }
6985 \f
6986 /* Help detect a giv that is calculated by several consecutive insns;
6987 for example,
6988 giv = biv * M
6989 giv = giv + A
6990 The caller has already identified the first insn P as having a giv as dest;
6991 we check that all other insns that set the same register follow
6992 immediately after P, that they alter nothing else,
6993 and that the result of the last is still a giv.
6995 The value is 0 if the reg set in P is not really a giv.
6996 Otherwise, the value is the amount gained by eliminating
6997 all the consecutive insns that compute the value.
6999 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7000 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7002 The coefficients of the ultimate giv value are stored in
7003 *MULT_VAL and *ADD_VAL. */
7005 static int
7010 rtx p;
7011 rtx src_reg;
7012 rtx dest_reg;
7017 {
7023 rtx temp;
7024 rtx set;
7026 /* Indicate that this is a giv so that we can update the value produced in
7027 each insn of the multi-insn sequence.
7029 This induction structure will be used only by the call to
7030 general_induction_var below, so we can allocate it on our stack.
7031 If this is a giv, our caller will replace the induct var entry with
7032 a new induction structure. */
7053 {
7057 /* If libcall, skip to end of call sequence. */
7068 /* Giv created by equivalent expression. */
7074 {
7078 count--;
7082 }
7084 {
7085 /* Allow insns that set something other than this giv to a
7086 constant. Such insns are needed on machines which cannot
7087 include long constants and should not disqualify a giv. */
7096 }
7097 }
7102 }
7103 \f
7104 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7105 represented by G1. If no such expression can be found, or it is clear that
7106 it cannot possibly be a valid address, 0 is returned.
7108 To perform the computation, we note that
7109 G1 = x * v + a and
7110 G2 = y * v + b
7111 where `v' is the biv.
7113 So G2 = (y/b) * G1 + (b - a*y/x).
7115 Note that MULT = y/x.
7117 Update: A and B are now allowed to be additive expressions such that
7118 B contains all variables in A. That is, computing B-A will not require
7119 subtracting variables. */
7121 static rtx
7124 {
7125 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7130 /* If MULT is not 1, we cannot handle A with non-constants, since we
7131 would then be required to subtract multiples of the registers in A.
7132 This is theoretically possible, and may even apply to some Fortran
7133 constructs, but it is a lot of work and we do not attempt it here. */
7138 /* In general these structures are sorted top to bottom (down the PLUS
7139 chain), but not left to right across the PLUS. If B is a higher
7140 order giv than A, we can strip one level and recurse. If A is higher
7141 order, we'll eventually bail out, but won't know that until the end.
7142 If they are the same, we'll strip one level around this loop. */
7145 {
7157 /* We matched: remove one reg completely. */
7160 /* An alternate match. */
7163 /* An alternate match. */
7165 else
7166 {
7167 /* Indicates an extra register in B. Strip one level from B and
7168 recurse, hoping B was the higher order expression. */
7173 }
7174 }
7176 /* Here we are at the last level of A, go through the cases hoping to
7177 get rid of everything but a constant. */
7180 {
7193 }
7195 {
7197 }
7199 {
7204 }
7206 {
7211 else
7213 }
7218 }
7220 rtx
7223 {
7226 /* The value that G1 will be multiplied by must be a constant integer. Also,
7227 the only chance we have of getting a valid address is if b*c/a (see above
7228 for notation) is also an integer. */
7231 {
7236 }
7239 else
7240 {
7241 /* ??? Find out if the one is a multiple of the other? */
7243 }
7247 {
7248 /* Failed. If we've got a multiplication factor between G1 and G2,
7249 scale G1's addend and try again. */
7251 {
7255 {
7256 HOST_WIDE_INT m;
7260 }
7261 else
7262 {
7264 mult);
7265 }
7268 }
7269 }
7273 /* Form simplified final result. */
7278 else
7283 else
7284 {
7287 {
7291 }
7294 }
7295 }
7296 \f
7297 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7298 represented by G1. This indicates that G2 should be combined with G1 and
7299 that G2 can use (either directly or via an address expression) a register
7300 used to represent G1. */
7302 static rtx
7305 {
7308 /* With the introduction of ext dependent givs, we must care for modes.
7309 G2 must not use a wider mode than G1. */
7319 /* If these givs are identical, they can be combined. We use the results
7320 of express_from because the addends are not in a canonical form, so
7321 rtx_equal_p is a weaker test. */
7322 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7323 combination to be the other way round. */
7326 {
7328 }
7330 /* If G2 can be expressed as a function of G1 and that function is valid
7331 as an address and no more expensive than using a register for G2,
7332 the expression of G2 in terms of G1 can be used. */
7336 /* ??? Looses, especially with -fforce-addr, where *g2->location
7337 will always be a register, and so anything more complicated
7338 gets discarded. */
7339 #if 0
7340 #ifdef ADDRESS_COST
7342 #else
7344 #endif
7345 #endif
7346 )
7347 {
7349 }
7352 }
7353 \f
7354 /* Check each extension dependent giv in this class to see if its
7355 root biv is safe from wrapping in the interior mode, which would
7356 make the giv illegal. */
7358 static void
7362 {
7365 HOST_WIDE_INT start_val;
7371 /* Make sure the iteration data is available. We must have
7372 constants in order to be certain of no overflow. */
7373 /* ??? An unknown iteration count with an increment of +-1
7374 combined with friendly exit tests of against an invariant
7375 value is also ameanable to optimization. Not implemented. */
7381 /* Make sure the host can represent the arithmetic. */
7383 {
7385 HOST_WIDE_INT s_end_val;
7397 /* Check for host arithmatic overflow. */
7399 {
7401 HOST_WIDE_INT s_max;
7408 /* Check zero extension of biv ok. */
7410 /* Check for host arithmatic overflow. */
7411 && (neg_incr
7414 /* Check for target arithmetic overflow. */
7415 && (neg_incr
7418 {
7420 }
7422 /* Check sign extension of biv ok. */
7423 /* ??? While it is true that overflow with signed and pointer
7424 arithmetic is undefined, I fear too many programmers don't
7425 keep this fact in mind -- myself included on occasion.
7426 So leave alone with the signed overflow optimizations. */
7428 /* Check for host arithmatic overflow. */
7429 && (neg_incr
7432 /* Check for target arithmetic overflow. */
7433 && (neg_incr
7436 {
7438 }
7439 }
7440 }
7442 /* Invalidate givs that fail the tests. */
7445 {
7450 {
7459 /* We don't know whether this value is being used as either
7460 signed or unsigned, so to safely truncate we must satisfy
7461 both. The initial check here verifies the BIV itself;
7462 once that is successful we may check its range wrt the
7463 derived GIV. */
7465 {
7469 /* We know from the above that both endpoints are nonnegative,
7470 and that there is no wrapping. Verify that both endpoints
7471 are within the (signed) range of the outer mode. */
7474 }
7479 }
7482 {
7484 {
7488 }
7489 }
7490 else
7491 {
7493 {
7498 else
7499 {
7504 else
7506 }
7511 }
7514 }
7515 }
7516 }
7518 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7520 rtx
7523 rtx value;
7524 {
7530 /* Recall that check_ext_dependent_givs verified that the known bounds
7531 of a biv did not overflow or wrap with respect to the extension for
7532 the giv. Therefore, constants need no additional adjustment. */
7536 /* Otherwise, we must adjust the value to compensate for the
7537 differing modes of the biv and the giv. */
7539 }
7540 \f
7541 struct combine_givs_stats
7542 {
7545 };
7547 static int
7551 {
7558 /* Stabilize the sort. */
7562 }
7564 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7565 any other. If so, point SAME to the giv combined with and set NEW_REG to
7566 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7567 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7569 static void
7573 {
7574 /* Additional benefit to add for being combined multiple times. */
7582 /* Count givs, because bl->giv_count is incorrect here. */
7586 giv_count++;
7588 giv_array
7599 {
7601 rtx single_use;
7606 /* If a DEST_REG GIV is used only once, do not allow it to combine
7607 with anything, for in doing so we will gain nothing that cannot
7608 be had by simply letting the GIV with which we would have combined
7609 to be reduced on its own. The losage shows up in particular with
7610 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7611 be seen elsewhere as well. */
7618 /* Add an additional weight for zero addends. */
7623 {
7624 rtx this_combine;
7629 {
7632 }
7633 }
7635 }
7637 /* Iterate, combining until we can't. */
7638 restart:
7642 {
7645 {
7651 }
7653 }
7656 {
7662 /* If it has already been combined, skip. */
7667 {
7670 /* If it has already been combined, skip. */
7672 {
7677 /* For destination, we now may replace by mem expression instead
7678 of register. This changes the costs considerably, so add the
7679 compensation. */
7689 /* ??? The new final_[bg]iv_value code does a much better job
7690 of finding replaceable giv's, and hence this code may no
7691 longer be necessary. */
7695 /* To help optimize the next set of combinations, remove
7696 this giv from the benefits of other potential mates. */
7698 {
7702 }
7709 }
7710 }
7712 /* To help optimize the next set of combinations, remove
7713 this giv from the benefits of other potential mates. */
7715 {
7717 {
7721 }
7725 /* We've finished with this giv, and everything it touched.
7726 Restart the combination so that proper weights for the
7727 rest of the givs are properly taken into account. */
7728 /* ??? Ideally we would compact the arrays at this point, so
7729 as to not cover old ground. But sanely compacting
7730 can_combine is tricky. */
7732 }
7733 }
7735 /* Clean up. */
7738 }
7739 \f
7740 /* Generate sequence for REG = B * M + A. */
7742 static rtx
7748 {
7749 rtx seq;
7750 rtx result;
7753 /* Use unsigned arithmetic. */
7761 }
7764 /* Update registers created in insn sequence SEQ. */
7766 static void
7769 rtx seq;
7770 {
7771 rtx insn;
7773 /* Update register info for alias analysis. */
7779 {
7782 {
7789 }
7790 }
7794 }
7797 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7799 void
7806 basic_block before_bb;
7807 rtx before_insn;
7808 {
7809 rtx seq;
7812 {
7815 }
7817 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7820 /* Increase the lifetime of any invariants moved further in code. */
7827 /* It is possible that the expansion created lots of new registers.
7828 Iterate over the sequence we just created and record them all. */
7830 }
7833 /* Emit insns in loop pre-header to set REG = B * M + A. */
7835 void
7842 {
7843 rtx seq;
7845 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7848 /* Increase the lifetime of any invariants moved further in code.
7849 ???? Is this really necessary? */
7856 /* It is possible that the expansion created lots of new registers.
7857 Iterate over the sequence we just created and record them all. */
7859 }
7862 /* Emit insns after loop to set REG = B * M + A. */
7864 void
7871 {
7872 rtx seq;
7874 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7879 /* It is possible that the expansion created lots of new registers.
7880 Iterate over the sequence we just created and record them all. */
7882 }
7886 /* Similar to gen_add_mult, but compute cost rather than generating
7887 sequence. */
7889 static int
7895 {
7905 {
7910 }
7913 }
7914 \f
7915 /* Test whether A * B can be computed without
7916 an actual multiply insn. Value is 1 if so.
7918 ??? This function stinks because it generates a ton of wasted RTL
7919 ??? and as a result fragments GC memory to no end. There are other
7920 ??? places in the compiler which are invoked a lot and do the same
7921 ??? thing, generate wasted RTL just to see if something is possible. */
7923 static int
7925 rtx a;
7926 rtx b;
7927 {
7928 rtx tmp;
7931 /* If only one is constant, make it B. */
7935 /* If first constant, both constant, so don't need multiply. */
7939 /* If second not constant, neither is constant, so would need multiply. */
7943 /* One operand is constant, so might not need multiply insn. Generate the
7944 code for the multiply and see if a call or multiply, or long sequence
7945 of insns is generated. */
7954 {
7957 {
7967 {
7970 }
7973 }
7974 }
7984 }
7985 \f
7986 /* Check to see if loop can be terminated by a "decrement and branch until
7987 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7988 Also try reversing an increment loop to a decrement loop
7989 to see if the optimization can be performed.
7990 Value is nonzero if optimization was performed. */
7992 /* This is useful even if the architecture doesn't have such an insn,
7993 because it might change a loops which increments from 0 to n to a loop
7994 which decrements from n to 0. A loop that decrements to zero is usually
7995 faster than one that increments from zero. */
7997 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7998 such as approx_final_value, biv_total_increment, loop_iterations, and
7999 final_[bg]iv_value. */
8001 static int
8005 {
8010 rtx reg;
8011 rtx jump_label;
8012 rtx final_value;
8013 rtx start_value;
8014 rtx new_add_val;
8015 rtx comparison;
8016 rtx before_comparison;
8017 rtx p;
8018 rtx jump;
8019 rtx first_compare;
8024 /* If last insn is a conditional branch, and the insn before tests a
8025 register value, try to optimize it. Otherwise, we can't do anything. */
8034 /* Try to compute whether the compare/branch at the loop end is one or
8035 two instructions. */
8041 else
8044 {
8045 /* If more than one condition is present to control the loop, then
8046 do not proceed, as this function does not know how to rewrite
8047 loop tests with more than one condition.
8049 Look backwards from the first insn in the last comparison
8050 sequence and see if we've got another comparison sequence. */
8052 rtx jump1;
8056 }
8058 /* Check all of the bivs to see if the compare uses one of them.
8059 Skip biv's set more than once because we can't guarantee that
8060 it will be zero on the last iteration. Also skip if the biv is
8061 used between its update and the test insn. */
8064 {
8069 first_compare))
8071 }
8076 /* Look for the case where the basic induction variable is always
8077 nonnegative, and equals zero on the last iteration.
8078 In this case, add a reg_note REG_NONNEG, which allows the
8079 m68k DBRA instruction to be used. */
8087 {
8088 /* Initial value must be greater than 0,
8089 init_val % -dec_value == 0 to ensure that it equals zero on
8090 the last iteration */
8096 {
8097 /* register always nonnegative, add REG_NOTE to branch */
8105 }
8107 /* If the decrement is 1 and the value was tested as >= 0 before
8108 the loop, then we can safely optimize. */
8110 {
8123 {
8131 }
8132 }
8133 }
8136 {
8137 /* Try to change inc to dec, so can apply above optimization. */
8138 /* Can do this if:
8139 all registers modified are induction variables or invariant,
8140 all memory references have non-overlapping addresses
8141 (obviously true if only one write)
8142 allow 2 insns for the compare/jump at the end of the loop. */
8143 /* Also, we must avoid any instructions which use both the reversed
8144 biv and another biv. Such instructions will fail if the loop is
8145 reversed. We meet this condition by requiring that either
8146 no_use_except_counting is true, or else that there is only
8147 one biv. */
8149 /* 1 if the iteration var is used only to count iterations. */
8151 /* 1 if the loop has no memory store, or it has a single memory store
8152 which is reversible. */
8158 {
8162 /* If there are no givs for this biv, and the only exit is the
8163 fall through at the end of the loop, then
8164 see if perhaps there are no uses except to count. */
8168 {
8173 /* An insn that sets the biv is okay. */
8174 ;
8178 {
8179 /* If either of these insns uses the biv and sets a pseudo
8180 that has more than one usage, then the biv has uses
8181 other than counting since it's used to derive a value
8182 that is used more than one time. */
8184 regs);
8186 {
8189 }
8190 }
8192 {
8195 }
8196 }
8198 /* A biv has uses besides counting if it is used to set
8199 another biv. */
8203 {
8206 }
8207 }
8210 /* No need to worry about MEMs. */
8211 ;
8213 {
8218 /* If the loop has a single store, and the destination address is
8219 invariant, then we can't reverse the loop, because this address
8220 might then have the wrong value at loop exit.
8221 This would work if the source was invariant also, however, in that
8222 case, the insn should have been moved out of the loop. */
8225 {
8228 /* If we could prove that each of the memory locations
8229 written to was different, then we could reverse the
8230 store -- but we don't presently have any way of
8231 knowing that. */
8234 /* If the store depends on a register that is set after the
8235 store, it depends on the initial value, and is thus not
8236 reversible. */
8238 {
8245 }
8246 }
8247 }
8248 else
8251 /* This code only acts for innermost loops. Also it simplifies
8252 the memory address check by only reversing loops with
8253 zero or one memory access.
8254 Two memory accesses could involve parts of the same array,
8255 and that can't be reversed.
8256 If the biv is used only for counting, than we don't need to worry
8257 about all these things. */
8263 && reversible_mem_store
8268 {
8269 rtx tem;
8271 /* Loop can be reversed. */
8275 /* Now check other conditions:
8277 The increment must be a constant, as must the initial value,
8278 and the comparison code must be LT.
8280 This test can probably be improved since +/- 1 in the constant
8281 can be obtained by changing LT to LE and vice versa; this is
8282 confusing. */
8285 /* for constants, LE gets turned into LT */
8289 {
8300 comparison_const_width
8302 else
8303 comparison_const_width
8307 comparison_sign_mask
8310 /* If the comparison value is not a loop invariant, then we
8311 can not reverse this loop.
8313 ??? If the insns which initialize the comparison value as
8314 a whole compute an invariant result, then we could move
8315 them out of the loop and proceed with loop reversal. */
8323 /* Normalize the initial value if it is an integer and
8324 has no other use except as a counter. This will allow
8325 a few more loops to be reversed. */
8329 {
8331 /* The code below requires comparison_val to be a multiple
8332 of add_val in order to do the loop reversal, so
8333 round up comparison_val to a multiple of add_val.
8334 Since comparison_value is constant, we know that the
8335 current comparison code is LT. */
8337 comparison_val
8339 /* We postpone overflow checks for COMPARISON_VAL here;
8340 even if there is an overflow, we might still be able to
8341 reverse the loop, if converting the loop exit test to
8342 NE is possible. */
8344 }
8346 /* First check if we can do a vanilla loop reversal. */
8348 /* If we have a decrement_and_branch_on_count,
8349 prefer the NE test, since this will allow that
8350 instruction to be generated. Note that we must
8351 use a vanilla loop reversal if the biv is used to
8352 calculate a giv or has a non-counting use. */
8353 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8354 && defined (HAVE_decrement_and_branch_on_count)
8358 #endif
8360 /* Now do postponed overflow checks on COMPARISON_VAL. */
8363 {
8364 /* Register will always be nonnegative, with value
8365 0 on last iteration */
8369 }
8373 {
8376 }
8377 else
8383 /* If the initial value is not zero, or if the comparison
8384 value is not an exact multiple of the increment, then we
8385 can not reverse this loop. */
8388 {
8391 }
8392 else
8393 {
8396 }
8400 /* Reset these in case we normalized the initial value
8401 and comparison value above. */
8404 {
8406 final_value
8408 }
8411 /* Save some info needed to produce the new insns. */
8416 /* Set start_value; if this is not a CONST_INT, we need
8417 to generate a SUB.
8418 Initialize biv to start_value before loop start.
8419 The old initializing insn will be deleted as a
8420 dead store by flow.c. */
8423 {
8426 }
8428 {
8436 start_value
8442 }
8444 {
8447 initial_value);
8451 start_value
8454 }
8455 else
8456 /* We could handle the other cases too, but it'll be
8457 better to have a testcase first. */
8460 /* We may not have a single insn which can increment a reg, so
8461 create a sequence to hold all the insns from expand_inc. */
8470 /* Update biv info to reflect its new status. */
8475 /* Update loop info. */
8484 /* Inc LABEL_NUSES so that delete_insn will
8485 not delete the label. */
8488 /* Emit an insn after the end of the loop to set the biv's
8489 proper exit value if it is used anywhere outside the loop. */
8495 /* Delete compare/branch at end of loop. */
8500 /* Add new compare/branch insn at end of loop. */
8512 ;
8518 {
8520 {
8521 /* Increment of LABEL_NUSES done above. */
8522 /* Register is now always nonnegative,
8523 so add REG_NONNEG note to the branch. */
8526 }
8528 }
8530 /* No insn may reference both the reversed and another biv or it
8531 will fail (see comment near the top of the loop reversal
8532 code).
8533 Earlier on, we have verified that the biv has no use except
8534 counting, or it is the only biv in this function.
8535 However, the code that computes no_use_except_counting does
8536 not verify reg notes. It's possible to have an insn that
8537 references another biv, and has a REG_EQUAL note with an
8538 expression based on the reversed biv. To avoid this case,
8539 remove all REG_EQUAL notes based on the reversed biv
8540 here. */
8543 {
8546 /* If this is a set of a GIV based on the reversed biv, any
8547 REG_EQUAL notes should still be correct. */
8554 {
8559 else
8561 }
8562 }
8564 /* Mark that this biv has been reversed. Each giv which depends
8565 on this biv, and which is also live past the end of the loop
8566 will have to be fixed up. */
8571 {
8575 else
8577 }
8580 }
8581 }
8582 }
8585 }
8586 \f
8587 /* Verify whether the biv BL appears to be eliminable,
8588 based on the insns in the loop that refer to it.
8590 If ELIMINATE_P is nonzero, actually do the elimination.
8592 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8593 determine whether invariant insns should be placed inside or at the
8594 start of the loop. */
8596 static int
8602 {
8605 rtx p;
8607 /* Scan all insns in the loop, stopping if we find one that uses the
8608 biv in a way that we cannot eliminate. */
8611 {
8615 rtx note;
8617 /* If this is a libcall that sets a giv, skip ahead to its end. */
8619 {
8623 {
8628 {
8635 }
8636 }
8637 }
8639 /* Closely examine the insn if the biv is mentioned. */
8644 {
8650 }
8652 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8657 }
8660 {
8665 }
8668 }
8669 \f
8670 /* INSN and REFERENCE are instructions in the same insn chain.
8671 Return nonzero if INSN is first. */
8673 int
8676 {
8680 {
8681 /* Start with test for not first so that INSN == REFERENCE yields not
8682 first. */
8688 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8689 previous insn, hence the <= comparison below does not work if
8690 P is a note. */
8701 }
8702 }
8704 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8705 the offset that we have to take into account due to auto-increment /
8706 div derivation is zero. */
8707 static int
8710 rtx insn;
8711 {
8712 /* If the giv V had the auto-inc address optimization applied
8713 to it, and INSN occurs between the giv insn and the biv
8714 insn, then we'd have to adjust the value used here.
8715 This is rare, so we don't bother to make this possible. */
8724 }
8726 /* If BL appears in X (part of the pattern of INSN), see if we can
8727 eliminate its use. If so, return 1. If not, return 0.
8729 If BIV does not appear in X, return 1.
8731 If ELIMINATE_P is nonzero, actually do the elimination.
8732 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8733 Depending on how many items have been moved out of the loop, it
8734 will either be before INSN (when WHERE_INSN is nonzero) or at the
8735 start of the loop (when WHERE_INSN is zero). */
8737 static int
8743 basic_block where_bb;
8744 rtx where_insn;
8745 {
8751 #ifdef HAVE_cc0
8753 #endif
8759 {
8761 /* If we haven't already been able to do something with this BIV,
8762 we can't eliminate it. */
8768 /* If this sets the BIV, it is not a problem. */
8772 /* If this is an insn that defines a giv, it is also ok because
8773 it will go away when the giv is reduced. */
8778 #ifdef HAVE_cc0
8780 {
8781 /* Can replace with any giv that was reduced and
8782 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8783 Require a constant for MULT_VAL, so we know it's nonzero.
8784 ??? We disable this optimization to avoid potential
8785 overflows. */
8793 {
8800 /* If the giv has the opposite direction of change,
8801 then reverse the comparison. */
8805 else
8808 /* We can probably test that giv's reduced reg. */
8811 }
8813 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8814 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8815 Require a constant for MULT_VAL, so we know it's nonzero.
8816 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8817 overflow problem. */
8829 {
8836 /* If the giv has the opposite direction of change,
8837 then reverse the comparison. */
8841 else
8845 /* Replace biv with the giv's reduced register. */
8850 /* Insn doesn't support that constant or invariant. Copy it
8851 into a register (it will be a loop invariant.) */
8858 /* Substitute the new register for its invariant value in
8859 the compare expression. */
8863 }
8864 }
8865 #endif
8872 /* See if either argument is the biv. */
8877 else
8881 {
8882 /* First try to replace with any giv that has constant positive
8883 mult_val and constant add_val. We might be able to support
8884 negative mult_val, but it seems complex to do it in general. */
8896 {
8900 /* Don't eliminate if the linear combination that makes up
8901 the giv overflows when it is applied to ARG. */
8903 {
8904 rtx add_val;
8908 else
8914 }
8919 /* Replace biv with the giv's reduced reg. */
8922 /* If all constants are actually constant integers and
8923 the derived constant can be directly placed in the COMPARE,
8924 do so. */
8927 {
8930 }
8931 else
8932 {
8933 /* Otherwise, load it into a register. */
8938 }
8944 }
8946 /* Look for giv with positive constant mult_val and nonconst add_val.
8947 Insert insns to calculate new compare value.
8948 ??? Turn this off due to possible overflow. */
8956 {
8957 rtx tem;
8967 /* Replace biv with giv's reduced register. */
8971 /* Compute value to compare against. */
8975 /* Use it in this insn. */
8979 }
8980 }
8982 {
8984 {
8985 /* Look for giv with constant positive mult_val and nonconst
8986 add_val. Insert insns to compute new compare value.
8987 ??? Turn this off due to possible overflow. */
8994 {
8995 rtx tem;
9005 /* Replace biv with giv's reduced register. */
9009 /* Compute value to compare against. */
9016 }
9017 }
9019 /* This code has problems. Basically, you can't know when
9020 seeing if we will eliminate BL, whether a particular giv
9021 of ARG will be reduced. If it isn't going to be reduced,
9022 we can't eliminate BL. We can try forcing it to be reduced,
9023 but that can generate poor code.
9025 The problem is that the benefit of reducing TV, below should
9026 be increased if BL can actually be eliminated, but this means
9027 we might have to do a topological sort of the order in which
9028 we try to process biv. It doesn't seem worthwhile to do
9029 this sort of thing now. */
9031 #if 0
9032 /* Otherwise the reg compared with had better be a biv. */
9037 /* Look for a pair of givs, one for each biv,
9038 with identical coefficients. */
9040 {
9052 {
9059 /* Replace biv with its giv's reduced reg. */
9061 /* Replace other operand with the other giv's
9062 reduced reg. */
9065 }
9066 }
9067 #endif
9068 }
9070 /* If we get here, the biv can't be eliminated. */
9074 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9075 biv is used in it, since it will be replaced. */
9083 }
9085 /* See if any subexpression fails elimination. */
9088 {
9090 {
9103 }
9104 }
9107 }
9108 \f
9109 /* Return nonzero if the last use of REG
9110 is in an insn following INSN in the same basic block. */
9112 static int
9114 rtx reg;
9115 rtx insn;
9116 {
9117 rtx n;
9121 {
9124 }
9126 }
9127 \f
9128 /* Called via `note_stores' to record the initial value of a biv. Here we
9129 just record the location of the set and process it later. */
9131 static void
9133 rtx dest;
9134 rtx set;
9136 {
9147 /* If this is the first set found, record it. */
9149 {
9152 }
9153 }
9154 \f
9155 /* If any of the registers in X are "old" and currently have a last use earlier
9156 than INSN, update them to have a last use of INSN. Their actual last use
9157 will be the previous insn but it will not have a valid uid_luid so we can't
9158 use it. X must be a source expression only. */
9160 static void
9162 rtx x;
9163 rtx insn;
9164 {
9165 /* Check for the case where INSN does not have a valid luid. In this case,
9166 there is no need to modify the regno_last_uid, as this can only happen
9167 when code is inserted after the loop_end to set a pseudo's final value,
9168 and hence this insn will never be the last use of x.
9169 ???? This comment is not correct. See for example loop_givs_reduce.
9170 This may insert an insn before another new insn. */
9174 {
9176 }
9177 else
9178 {
9182 {
9188 }
9189 }
9190 }
9191 \f
9192 /* Given an insn INSN and condition COND, return the condition in a
9193 canonical form to simplify testing by callers. Specifically:
9195 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9196 (2) Both operands will be machine operands; (cc0) will have been replaced.
9197 (3) If an operand is a constant, it will be the second operand.
9198 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9199 for GE, GEU, and LEU.
9201 If the condition cannot be understood, or is an inequality floating-point
9202 comparison which needs to be reversed, 0 will be returned.
9204 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9206 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9207 insn used in locating the condition was found. If a replacement test
9208 of the condition is desired, it should be placed in front of that
9209 insn and we will be sure that the inputs are still valid.
9211 If WANT_REG is nonzero, we wish the condition to be relative to that
9212 register, if possible. Therefore, do not canonicalize the condition
9213 further. */
9215 rtx
9217 rtx insn;
9218 rtx cond;
9221 rtx want_reg;
9222 {
9225 rtx set;
9226 rtx tem;
9244 /* If we are comparing a register with zero, see if the register is set
9245 in the previous insn to a COMPARE or a comparison operation. Perform
9246 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9247 in cse.c */
9252 {
9253 /* Set nonzero when we find something of interest. */
9256 #ifdef HAVE_cc0
9257 /* If comparison with cc0, import actual comparison from compare
9258 insn. */
9260 {
9271 }
9272 #endif
9274 /* If this is a COMPARE, pick up the two things being compared. */
9276 {
9280 }
9284 /* Go back to the previous insn. Stop if it is not an INSN. We also
9285 stop if it isn't a single set or if it has a REG_INC note because
9286 we don't want to bother dealing with it. */
9300 /* If this is setting OP0, get what it sets it to if it looks
9301 relevant. */
9303 {
9305 #ifdef FLOAT_STORE_FLAG_VALUE
9306 REAL_VALUE_TYPE fsfv;
9307 #endif
9309 /* ??? We may not combine comparisons done in a CCmode with
9310 comparisons not done in a CCmode. This is to aid targets
9311 like Alpha that have an IEEE compliant EQ instruction, and
9312 a non-IEEE compliant BEQ instruction. The use of CCmode is
9313 actually artificial, simply to prevent the combination, but
9314 should not affect other platforms.
9316 However, we must allow VOIDmode comparisons to match either
9317 CCmode or non-CCmode comparison, because some ports have
9318 modeless comparisons inside branch patterns.
9320 ??? This mode check should perhaps look more like the mode check
9321 in simplify_comparison in combine. */
9329 && (STORE_FLAG_VALUE
9332 #ifdef FLOAT_STORE_FLAG_VALUE
9337 #endif
9338 ))
9349 && (STORE_FLAG_VALUE
9352 #ifdef FLOAT_STORE_FLAG_VALUE
9357 #endif
9358 ))
9364 {
9367 }
9368 else
9370 }
9373 /* If this sets OP0, but not directly, we have to give up. */
9377 {
9381 {
9386 }
9391 }
9392 }
9394 /* If constant is first, put it last. */
9398 /* If OP0 is the result of a comparison, we weren't able to find what
9399 was really being compared, so fail. */
9403 /* Canonicalize any ordered comparison with integers involving equality
9404 if we can do computations in the relevant mode and we do not
9405 overflow. */
9410 {
9413 unsigned HOST_WIDE_INT max_val
9417 {
9423 /* When cross-compiling, const_val might be sign-extended from
9424 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9444 }
9445 }
9447 #ifdef HAVE_cc0
9448 /* Never return CC0; return zero instead. */
9451 #endif
9454 }
9456 /* Given a jump insn JUMP, return the condition that will cause it to branch
9457 to its JUMP_LABEL. If the condition cannot be understood, or is an
9458 inequality floating-point comparison which needs to be reversed, 0 will
9459 be returned.
9461 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9462 insn used in locating the condition was found. If a replacement test
9463 of the condition is desired, it should be placed in front of that
9464 insn and we will be sure that the inputs are still valid. */
9466 rtx
9468 rtx jump;
9470 {
9471 rtx cond;
9473 rtx set;
9475 /* If this is not a standard conditional jump, we can't parse it. */
9483 /* If this branches to JUMP_LABEL when the condition is false, reverse
9484 the condition. */
9485 reverse
9490 }
9492 /* Similar to above routine, except that we also put an invariant last
9493 unless both operands are invariants. */
9495 rtx
9498 rtx x;
9499 {
9509 }
9511 /* Scan the function and determine whether it has indirect (computed) jumps.
9513 This is taken mostly from flow.c; similar code exists elsewhere
9514 in the compiler. It may be useful to put this into rtlanal.c. */
9515 static int
9517 rtx start;
9518 {
9519 rtx insn;
9526 }
9528 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9529 documentation for LOOP_MEMS for the definition of `appropriate'.
9530 This function is called from prescan_loop via for_each_rtx. */
9532 static int
9536 {
9545 {
9550 /* We're not interested in MEMs that are only clobbered. */
9554 /* We're not interested in the MEM associated with a
9555 CONST_DOUBLE, so there's no need to traverse into this. */
9559 /* We're not interested in any MEMs that only appear in notes. */
9563 /* This is not a MEM. */
9565 }
9567 /* See if we've already seen this MEM. */
9570 {
9572 /* The modes of the two memory accesses are different. If
9573 this happens, something tricky is going on, and we just
9574 don't optimize accesses to this MEM. */
9578 }
9580 /* Resize the array, if necessary. */
9582 {
9585 else
9591 }
9593 /* Actually insert the MEM. */
9595 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9596 because we can't put it in a register. We still store it in the
9597 table, though, so that if we see the same address later, but in a
9598 non-BLK mode, we'll not think we can optimize it at that point. */
9604 }
9607 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9609 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9610 register that is modified by an insn between FROM and TO. If the
9611 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9612 more, stop incrementing it, to avoid overflow.
9614 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9615 register I is used, if it is only used once. Otherwise, it is set
9616 to 0 (for no uses) or const0_rtx for more than one use. This
9617 parameter may be zero, in which case this processing is not done.
9619 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9620 optimize register I. */
9622 static void
9626 {
9629 /* last_set[n] is nonzero iff reg n has been set in the current
9630 basic block. In that case, it is the insn that last set reg n. */
9632 rtx insn;
9638 /* Grow the regs array if not allocated or too small. */
9640 {
9646 /* Zero the new elements. */
9649 }
9651 /* Clear previously scanned fields but do not clear n_times_set. */
9653 {
9657 }
9661 /* Scan the loop, recording register usage. */
9664 {
9666 {
9667 /* Record registers that have exactly one use. */
9670 /* Include uses in REG_EQUAL notes. */
9678 {
9682 last_set);
9683 }
9684 }
9689 /* Invalidate all registers used for function argument passing.
9690 We check rtx_varies_p for the same reason as below, to allow
9691 optimizing PIC calculations. */
9693 {
9694 rtx link;
9696 link;
9698 {
9705 }
9706 }
9707 }
9709 /* Invalidate all hard registers clobbered by calls. With one exception:
9710 a call-clobbered PIC register is still function-invariant for our
9711 purposes, since we can hoist any PIC calculations out of the loop.
9712 Thus the call to rtx_varies_p. */
9717 {
9720 }
9722 #ifdef AVOID_CCMODE_COPIES
9723 /* Don't try to move insns which set CC registers if we should not
9724 create CCmode register copies. */
9728 #endif
9730 /* Set regs->array[I].n_times_set for the new registers. */
9735 }
9737 /* Returns the number of real INSNs in the LOOP. */
9739 static int
9742 {
9744 rtx insn;
9752 }
9754 /* Move MEMs into registers for the duration of the loop. */
9756 static void
9759 {
9766 rtx end_label;
9767 /* Nonzero if the next instruction may never be executed. */
9774 /* We cannot use next_label here because it skips over normal insns. */
9779 /* Check to see if it's possible that some instructions in the loop are
9780 never executed. Also check if there is a goto out of the loop other
9781 than right after the end of the loop. */
9785 {
9789 /* If we enter the loop in the middle, and scan
9790 around to the beginning, don't set maybe_never
9791 for that. This must be an unconditional jump,
9792 otherwise the code at the top of the loop might
9793 never be executed. Unconditional jumps are
9794 followed a by barrier then loop end. */
9799 {
9800 /* If this is a jump outside of the loop but not right
9801 after the end of the loop, we would have to emit new fixup
9802 sequences for each such label. */
9804 JUMP_INSN is executed, we must be conservative. */
9813 /* Something complicated. */
9815 else
9816 /* If there are any more instructions in the loop, they
9817 might not be reached. */
9819 }
9822 }
9824 /* Find start of the extended basic block that enters the loop. */
9828 ;
9833 /* Build table of mems that get set to constant values before the
9834 loop. */
9838 /* Actually move the MEMs. */
9840 {
9841 regset_head load_copies;
9842 regset_head store_copies;
9844 rtx reg;
9846 rtx mem_list_entry;
9850 /* There's no telling whether or not MEM is modified. */
9853 /* Go through the MEMs written to in the loop to see if this
9854 one is aliased by one of them. */
9857 {
9862 {
9863 /* MEM is indeed aliased by this store. */
9866 }
9868 }
9874 /* If this MEM is written to, we must be sure that there
9875 are no reads from another MEM that aliases this one. */
9877 {
9881 {
9885 VOIDmode,
9887 rtx_varies_p))
9888 {
9889 /* It's not safe to hoist loop_info->mems[i] out of
9890 the loop because writes to it might not be
9891 seen by reads from loop_info->mems[j]. */
9894 }
9895 }
9896 }
9899 /* We can't access the MEM outside the loop; it might
9900 cause a trap that wouldn't have happened otherwise. */
9904 /* We thought we were going to lift this MEM out of the
9905 loop, but later discovered that we could not. */
9911 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9912 order to keep scan_loop from moving stores to this MEM
9913 out of the loop just because this REG is neither a
9914 user-variable nor used in the loop test. */
9919 /* Now, replace all references to the MEM with the
9920 corresponding pseudos. */
9925 {
9927 {
9928 rtx set;
9932 /* See if this copies the mem into a register that isn't
9933 modified afterwards. We'll try to do copy propagation
9934 a little further on. */
9936 /* @@@ This test is _way_ too conservative. */
9937 && ! maybe_never
9945 /* See if this copies the mem from a register that isn't
9946 modified afterwards. We'll try to remove the
9947 redundant copy later on by doing a little register
9948 renaming and copy propagation. This will help
9949 to untangle things for the BIV detection code. */
9951 && ! maybe_never
9959 /* If this is a call which uses / clobbers this memory
9960 location, we must not change the interface here. */
9964 {
9968 }
9969 else
9970 /* Replace the memory reference with the shadow register. */
9973 }
9978 }
9983 /* We couldn't replace all occurrences of the MEM. */
9985 else
9986 {
9987 /* Load the memory immediately before LOOP->START, which is
9988 the NOTE_LOOP_BEG. */
9990 rtx set;
9996 {
10000 {
10004 /* Extending hard register lifetimes causes crash
10005 on SRC targets. Doing so on non-SRC is
10006 probably also not good idea, since we most
10007 probably have pseudoregister equivalence as
10008 well. */
10011 }
10012 /* Use the constant equivalence if that is cheap enough. */
10018 {
10021 }
10023 /* If best_equiv is nonzero, we know that MEM is set to a
10024 constant or register before the loop. We will use this
10025 knowledge to initialize the shadow register with that
10026 constant or reg rather than by loading from MEM. */
10029 }
10034 {
10037 {
10040 }
10041 }
10047 {
10049 {
10052 }
10054 /* Store the memory immediately after END, which is
10055 the NOTE_LOOP_END. */
10058 }
10061 {
10066 }
10068 /* Attempt a bit of copy propagation. This helps untangle the
10069 data flow, and enables {basic,general}_induction_var to find
10070 more bivs/givs. */
10071 EXECUTE_IF_SET_IN_REG_SET
10073 {
10075 });
10078 EXECUTE_IF_SET_IN_REG_SET
10080 {
10082 });
10084 }
10085 }
10088 {
10089 /* Now, we need to replace all references to the previous exit
10090 label with the new one. */
10091 rtx_pair rr;
10096 {
10099 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
10100 field. This is not handled by for_each_rtx because it doesn't
10101 handle unprinted ('0') fields. We need to update JUMP_LABEL
10102 because the immediately following unroll pass will use it.
10103 replace_label would not work anyways, because that only handles
10104 LABEL_REFs. */
10107 }
10108 }
10111 }
10113 /* For communication between note_reg_stored and its caller. */
10114 struct note_reg_stored_arg
10115 {
10117 rtx reg;
10118 };
10120 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10121 is equal to ARG. */
10122 static void
10126 {
10130 }
10132 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10133 There must be exactly one insn that sets this pseudo; it will be
10134 deleted if all replacements succeed and we can prove that the register
10135 is not used after the loop. */
10137 static void
10140 rtx replacement;
10142 {
10143 /* This is the reg that we are copying from. */
10146 rtx insn;
10147 /* These help keep track of whether we replaced all uses of the reg. */
10154 {
10155 rtx set;
10157 /* Only substitute within one extended basic block from the initializing
10158 insn. */
10165 /* Is this the initializing insn? */
10170 {
10177 }
10179 /* Only substitute after seeing the initializing insn. */
10181 {
10188 /* Stop replacing when REPLACEMENT is modified. */
10193 {
10196 /* It is possible that we've turned previously valid REG_EQUAL to
10197 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10198 REPLACEMENT is modified, we get different meaning. */
10202 }
10203 }
10204 }
10208 {
10212 {
10213 rtx first;
10214 rtx retval_note;
10216 /* Assume we're just deleting INIT_INSN. */
10218 /* Look for REG_RETVAL note. If we're deleting the end of
10219 the libcall sequence, the whole sequence can go. */
10221 /* If we found a REG_RETVAL note, find the first instruction
10222 in the sequence. */
10226 /* Delete the instructions. */
10228 }
10231 }
10232 }
10234 /* Replace all the instructions from FIRST up to and including LAST
10235 with NOTE_INSN_DELETED notes. */
10237 static void
10239 rtx first;
10240 rtx last;
10241 {
10243 {
10249 /* If this was the LAST instructions we're supposed to delete,
10250 we're done. */
10255 }
10256 }
10258 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10259 loop LOOP if the order of the sets of these registers can be
10260 swapped. There must be exactly one insn within the loop that sets
10261 this pseudo followed immediately by a move insn that sets
10262 REPLACEMENT with REGNO. */
10263 static void
10266 rtx replacement;
10268 {
10269 rtx insn;
10278 {
10279 /* Search for the insn that copies REGNO to NEW_REGNO? */
10287 }
10290 {
10291 rtx prev_insn;
10292 rtx prev_set;
10294 /* Some DEF-USE info would come in handy here to make this
10295 function more general. For now, just check the previous insn
10296 which is the most likely candidate for setting REGNO. */
10304 {
10305 /* We have:
10306 (set (reg regno) (expr))
10307 (set (reg new_regno) (reg regno))
10309 so try converting this to:
10310 (set (reg new_regno) (expr))
10311 (set (reg regno) (reg new_regno))
10313 The former construct is often generated when a global
10314 variable used for an induction variable is shadowed by a
10315 register (NEW_REGNO). The latter construct improves the
10316 chances of GIV replacement and BIV elimination. */
10326 {
10333 /* Update first use of REGNO. */
10337 /* Now perform copy propagation to hopefully
10338 remove all uses of REGNO within the loop. */
10340 }
10341 }
10342 }
10343 }
10345 /* Replace MEM with its associated pseudo register. This function is
10346 called from load_mems via for_each_rtx. DATA is actually a pointer
10347 to a structure describing the instruction currently being scanned
10348 and the MEM we are currently replacing. */
10350 static int
10354 {
10362 {
10367 /* We're not interested in the MEM associated with a
10368 CONST_DOUBLE, so there's no need to traverse into one. */
10372 /* This is not a MEM. */
10374 }
10377 /* This is not the MEM we are currently replacing. */
10380 /* Actually replace the MEM. */
10384 }
10386 static void
10388 rtx insn;
10389 rtx mem;
10390 rtx reg;
10391 {
10392 loop_replace_args args;
10399 }
10401 /* Replace one register with another. Called through for_each_rtx; PX points
10402 to the rtx being scanned. DATA is actually a pointer to
10403 a structure of arguments. */
10405 static int
10409 {
10420 }
10422 static void
10424 rtx insn;
10425 rtx reg;
10426 rtx replacement;
10427 {
10428 loop_replace_args args;
10435 }
10437 /* Replace occurrences of the old exit label for the loop with the new
10438 one. DATA is an rtx_pair containing the old and new labels,
10439 respectively. */
10441 static int
10445 {
10464 }
10465 \f
10466 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10467 (ignored in the interim). */
10469 static rtx
10472 basic_block where_bb ATTRIBUTE_UNUSED;
10473 rtx where_insn;
10474 rtx pattern;
10475 {
10477 }
10480 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10481 in basic block WHERE_BB (ignored in the interim) within the loop
10482 otherwise hoist PATTERN into the loop pre-header. */
10484 rtx
10487 basic_block where_bb ATTRIBUTE_UNUSED;
10488 rtx where_insn;
10489 rtx pattern;
10490 {
10494 }
10497 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10498 WHERE_BB (ignored in the interim) within the loop. */
10500 static rtx
10503 basic_block where_bb ATTRIBUTE_UNUSED;
10504 rtx where_insn;
10505 rtx pattern;
10506 {
10508 }
10511 /* Hoist insn for PATTERN into the loop pre-header. */
10513 rtx
10516 rtx pattern;
10517 {
10519 }
10522 /* Hoist call insn for PATTERN into the loop pre-header. */
10524 static rtx
10527 rtx pattern;
10528 {
10530 }
10533 /* Sink insn for PATTERN after the loop end. */
10535 rtx
10538 rtx pattern;
10539 {
10541 }
10543 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10544 and constant. Emit sequence of intructions to load it into REG */
10545 static rtx
10548 {
10549 rtx seq;
10557 }
10559 /* If the loop has multiple exits, emit insn for PATTERN before the
10560 loop to ensure that it will always be executed no matter how the
10561 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10562 since this is slightly more efficient. */
10564 static rtx
10567 rtx pattern;
10568 {
10571 else
10573 }
10574 \f
10575 static void
10580 {
10588 iv_num++;
10593 {
10596 }
10597 }
10600 static void
10605 {
10607 rtx incr;
10618 {
10621 }
10623 {
10626 }
10630 {
10634 }
10637 {
10641 }
10643 /* List the increments. */
10645 {
10649 }
10651 /* List the givs. */
10653 {
10658 else
10661 }
10662 }
10665 static void
10670 {
10681 {
10685 }
10688 }
10691 static void
10696 {
10703 else
10719 {
10721 {
10733 }
10734 }
10745 {
10749 }
10752 }
10755 void
10758 {
10760 }
10763 void
10766 {
10768 }
10771 void
10774 {
10776 }
10779 void
10782 {
10784 }
10787 #define LOOP_BLOCK_NUM_1(INSN) \
10788 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10790 /* The notes do not have an assigned block, so look at the next insn. */
10791 #define LOOP_BLOCK_NUM(INSN) \
10792 ((INSN) ? (GET_CODE (INSN) == NOTE \
10793 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10794 : LOOP_BLOCK_NUM_1 (INSN)) \
10795 : -1)
10797 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10799 static void
10804 {
10805 rtx label;
10810 /* Print diagnostics to compare our concept of a loop with
10811 what the loop notes say. */
10826 {
10846 {
10849 {
10852 }
10853 }
10856 /* This can happen when a marked loop appears as two nested loops,
10857 say from while (a || b) {}. The inner loop won't match
10858 the loop markers but the outer one will. */
10861 }
10862 }
10864 /* Call this function from the debugger to dump LOOP. */
10866 void
10869 {
10871 }
10873 /* Call this function from the debugger to dump LOOPS. */
10875 void
10878 {
10880 }