1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_special_predicate "cc_register"
22 (and (match_code "reg")
23 (and (match_test "REGNO (op) == CC_REGNUM")
24 (ior (match_test "mode == GET_MODE (op)")
25 (match_test "mode == VOIDmode
26 && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
29 (define_predicate "aarch64_call_insn_operand"
30 (ior (match_code "symbol_ref")
31 (match_operand 0 "register_operand")))
33 ;; Return true if OP a (const_int 0) operand.
34 (define_predicate "const0_operand"
35 (and (match_code "const_int")
36 (match_test "op == CONST0_RTX (mode)")))
38 (define_predicate "aarch64_ccmp_immediate"
39 (and (match_code "const_int")
40 (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
42 (define_predicate "aarch64_ccmp_operand"
43 (ior (match_operand 0 "register_operand")
44 (match_operand 0 "aarch64_ccmp_immediate")))
46 (define_predicate "aarch64_simd_register"
47 (and (match_code "reg")
48 (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
49 (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
51 (define_predicate "aarch64_reg_or_zero"
52 (and (match_code "reg,subreg,const_int")
53 (ior (match_operand 0 "register_operand")
54 (match_test "op == const0_rtx"))))
56 (define_predicate "aarch64_reg_or_fp_zero"
57 (and (match_code "reg,subreg,const_double")
58 (ior (match_operand 0 "register_operand")
59 (match_test "aarch64_float_const_zero_rtx_p (op)"))))
61 (define_predicate "aarch64_reg_zero_or_m1_or_1"
62 (and (match_code "reg,subreg,const_int")
63 (ior (match_operand 0 "register_operand")
64 (ior (match_test "op == const0_rtx")
65 (ior (match_test "op == constm1_rtx")
66 (match_test "op == const1_rtx"))))))
68 (define_predicate "aarch64_fp_compare_operand"
69 (ior (match_operand 0 "register_operand")
70 (and (match_code "const_double")
71 (match_test "aarch64_float_const_zero_rtx_p (op)"))))
73 (define_predicate "aarch64_fp_pow2"
74 (and (match_code "const_double")
75 (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
77 (define_predicate "aarch64_fp_vec_pow2"
78 (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
80 (define_predicate "aarch64_plus_immediate"
81 (and (match_code "const_int")
82 (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
83 (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
85 (define_predicate "aarch64_plus_operand"
86 (ior (match_operand 0 "register_operand")
87 (match_operand 0 "aarch64_plus_immediate")))
89 (define_predicate "aarch64_pluslong_immediate"
90 (and (match_code "const_int")
91 (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
93 (define_predicate "aarch64_pluslong_strict_immedate"
94 (and (match_operand 0 "aarch64_pluslong_immediate")
95 (not (match_operand 0 "aarch64_plus_immediate"))))
97 (define_predicate "aarch64_pluslong_operand"
98 (ior (match_operand 0 "register_operand")
99 (match_operand 0 "aarch64_pluslong_immediate")))
101 (define_predicate "aarch64_logical_immediate"
102 (and (match_code "const_int")
103 (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
105 (define_predicate "aarch64_logical_operand"
106 (ior (match_operand 0 "register_operand")
107 (match_operand 0 "aarch64_logical_immediate")))
109 (define_predicate "aarch64_shift_imm_si"
110 (and (match_code "const_int")
111 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
113 (define_predicate "aarch64_shift_imm_di"
114 (and (match_code "const_int")
115 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
117 (define_predicate "aarch64_shift_imm64_di"
118 (and (match_code "const_int")
119 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
121 (define_predicate "aarch64_reg_or_shift_imm_si"
122 (ior (match_operand 0 "register_operand")
123 (match_operand 0 "aarch64_shift_imm_si")))
125 (define_predicate "aarch64_reg_or_shift_imm_di"
126 (ior (match_operand 0 "register_operand")
127 (match_operand 0 "aarch64_shift_imm_di")))
129 ;; The imm3 field is a 3-bit field that only accepts immediates in the
131 (define_predicate "aarch64_imm3"
132 (and (match_code "const_int")
133 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
135 ;; An immediate that fits into 24 bits.
136 (define_predicate "aarch64_imm24"
137 (and (match_code "const_int")
138 (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
140 (define_predicate "aarch64_pwr_imm3"
141 (and (match_code "const_int")
142 (match_test "INTVAL (op) != 0
143 && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
145 (define_predicate "aarch64_pwr_2_si"
146 (and (match_code "const_int")
147 (match_test "INTVAL (op) != 0
148 && (unsigned) exact_log2 (INTVAL (op)) < 32")))
150 (define_predicate "aarch64_pwr_2_di"
151 (and (match_code "const_int")
152 (match_test "INTVAL (op) != 0
153 && (unsigned) exact_log2 (INTVAL (op)) < 64")))
155 (define_predicate "aarch64_mem_pair_offset"
156 (and (match_code "const_int")
157 (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
159 (define_predicate "aarch64_mem_pair_operand"
160 (and (match_code "mem")
161 (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
164 (define_predicate "aarch64_valid_symref"
165 (match_code "const, symbol_ref, label_ref")
167 return (aarch64_classify_symbolic_expression (op)
168 != SYMBOL_FORCE_TO_MEM);
171 (define_predicate "aarch64_tls_ie_symref"
172 (match_code "const, symbol_ref, label_ref")
174 switch (GET_CODE (op))
178 if (GET_CODE (op) != PLUS
179 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
180 || GET_CODE (XEXP (op, 1)) != CONST_INT)
186 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
193 (define_predicate "aarch64_tls_le_symref"
194 (match_code "const, symbol_ref, label_ref")
196 switch (GET_CODE (op))
200 if (GET_CODE (op) != PLUS
201 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
202 || GET_CODE (XEXP (op, 1)) != CONST_INT)
208 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
215 (define_predicate "aarch64_mov_operand"
216 (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high")
217 (ior (match_operand 0 "register_operand")
218 (ior (match_operand 0 "memory_operand")
219 (match_test "aarch64_mov_operand_p (op, mode)")))))
221 (define_predicate "aarch64_movti_operand"
222 (and (match_code "reg,subreg,mem,const_int")
223 (ior (match_operand 0 "register_operand")
224 (ior (match_operand 0 "memory_operand")
225 (match_operand 0 "const_int_operand")))))
227 (define_predicate "aarch64_reg_or_imm"
228 (and (match_code "reg,subreg,const_int")
229 (ior (match_operand 0 "register_operand")
230 (match_operand 0 "const_int_operand"))))
232 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
233 (define_special_predicate "aarch64_comparison_operator"
234 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
235 ordered,unlt,unle,unge,ungt"))
237 ;; Same as aarch64_comparison_operator but don't ignore the mode.
238 ;; RTL SET operations require their operands source and destination have
239 ;; the same modes, so we can't ignore the modes there. See PR target/69161.
240 (define_predicate "aarch64_comparison_operator_mode"
241 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
242 ordered,unlt,unle,unge,ungt"))
244 (define_special_predicate "aarch64_comparison_operation"
245 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
246 ordered,unlt,unle,unge,ungt")
248 if (XEXP (op, 1) != const0_rtx)
250 rtx op0 = XEXP (op, 0);
251 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
253 return aarch64_get_condition_code (op) >= 0;
256 (define_special_predicate "aarch64_carry_operation"
257 (match_code "ne,geu")
259 if (XEXP (op, 1) != const0_rtx)
261 machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
262 rtx op0 = XEXP (op, 0);
263 return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
266 (define_special_predicate "aarch64_borrow_operation"
267 (match_code "eq,ltu")
269 if (XEXP (op, 1) != const0_rtx)
271 machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
272 rtx op0 = XEXP (op, 0);
273 return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
276 ;; True if the operand is memory reference suitable for a load/store exclusive.
277 (define_predicate "aarch64_sync_memory_operand"
278 (and (match_operand 0 "memory_operand")
279 (match_code "reg" "0")))
281 ;; Predicates for parallel expanders based on mode.
282 (define_special_predicate "vect_par_cnst_hi_half"
283 (match_code "parallel")
285 return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
288 (define_special_predicate "vect_par_cnst_lo_half"
289 (match_code "parallel")
291 return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
294 (define_special_predicate "aarch64_simd_lshift_imm"
295 (match_code "const_vector")
297 return aarch64_simd_shift_imm_p (op, mode, true);
300 (define_special_predicate "aarch64_simd_rshift_imm"
301 (match_code "const_vector")
303 return aarch64_simd_shift_imm_p (op, mode, false);
306 (define_predicate "aarch64_simd_reg_or_zero"
307 (and (match_code "reg,subreg,const_int,const_double,const_vector")
308 (ior (match_operand 0 "register_operand")
309 (ior (match_test "op == const0_rtx")
310 (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
312 (define_predicate "aarch64_simd_struct_operand"
313 (and (match_code "mem")
314 (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
316 ;; Like general_operand but allow only valid SIMD addressing modes.
317 (define_predicate "aarch64_simd_general_operand"
318 (and (match_operand 0 "general_operand")
319 (match_test "!MEM_P (op)
320 || GET_CODE (XEXP (op, 0)) == POST_INC
321 || GET_CODE (XEXP (op, 0)) == REG")))
323 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
324 (define_predicate "aarch64_simd_nonimmediate_operand"
325 (and (match_operand 0 "nonimmediate_operand")
326 (match_test "!MEM_P (op)
327 || GET_CODE (XEXP (op, 0)) == POST_INC
328 || GET_CODE (XEXP (op, 0)) == REG")))
330 (define_special_predicate "aarch64_simd_imm_zero"
331 (match_code "const_vector")
333 return aarch64_simd_imm_zero_p (op, mode);
336 (define_special_predicate "aarch64_simd_imm_minus_one"
337 (match_code "const_vector")
339 return aarch64_const_vec_all_same_int_p (op, -1);
342 ;; Predicates used by the various SIMD shift operations. These
343 ;; fall in to 3 categories.
344 ;; Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
345 ;; Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
346 ;; Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
347 (define_predicate "aarch64_simd_shift_imm_qi"
348 (and (match_code "const_int")
349 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
351 (define_predicate "aarch64_simd_shift_imm_hi"
352 (and (match_code "const_int")
353 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
355 (define_predicate "aarch64_simd_shift_imm_si"
356 (and (match_code "const_int")
357 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
359 (define_predicate "aarch64_simd_shift_imm_di"
360 (and (match_code "const_int")
361 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
363 (define_predicate "aarch64_simd_shift_imm_offset_qi"
364 (and (match_code "const_int")
365 (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
367 (define_predicate "aarch64_simd_shift_imm_offset_hi"
368 (and (match_code "const_int")
369 (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
371 (define_predicate "aarch64_simd_shift_imm_offset_si"
372 (and (match_code "const_int")
373 (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
375 (define_predicate "aarch64_simd_shift_imm_offset_di"
376 (and (match_code "const_int")
377 (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
379 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
380 (and (match_code "const_int")
381 (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
383 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
384 (and (match_code "const_int")
385 (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
387 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
388 (and (match_code "const_int")
389 (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
391 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
392 (and (match_code "const_int")
393 (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
395 (define_predicate "aarch64_constant_pool_symref"
396 (and (match_code "symbol_ref")
397 (match_test "CONSTANT_POOL_ADDRESS_P (op)")))