| blob | 4432cae6b8ddc84b00219eae884720af69dc376f |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define INCLUDE_STRING
70 /* This file should be included last. */
73 /* Defined for convenience. */
74 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
76 /* Classifies an address.
78 ADDRESS_REG_IMM
79 A simple base register plus immediate offset.
81 ADDRESS_REG_WB
82 A base register indexed by immediate offset with writeback.
84 ADDRESS_REG_REG
85 A base register indexed by (optionally scaled) register.
87 ADDRESS_REG_UXTW
88 A base register indexed by (optionally scaled) zero-extended register.
90 ADDRESS_REG_SXTW
91 A base register indexed by (optionally scaled) sign-extended register.
93 ADDRESS_LO_SUM
94 A LO_SUM rtx with a base register and "LO12" symbol relocation.
96 ADDRESS_SYMBOLIC:
97 A constant symbolic address, in pc-relative literal pool. */
100 ADDRESS_REG_IMM,
101 ADDRESS_REG_WB,
102 ADDRESS_REG_REG,
103 ADDRESS_REG_UXTW,
104 ADDRESS_REG_SXTW,
105 ADDRESS_LO_SUM,
106 ADDRESS_SYMBOLIC
107 };
111 rtx base;
112 rtx offset;
115 };
117 struct simd_immediate_info
118 {
119 rtx value;
124 };
126 /* The current code model. */
129 #ifdef HAVE_AS_TLS
130 #undef TARGET_HAVE_TLS
131 #define TARGET_HAVE_TLS 1
132 #endif
136 const_tree,
147 const_tree type,
151 /* Major revision number of the ARM Architecture implemented by the target. */
154 /* The processor for which instructions should be scheduled. */
157 /* Mask to specify which instruction scheduling options should be used. */
160 /* Global flag for PC relative loads. */
163 /* Support for command line parsing of boolean flags in the tuning
164 structures. */
165 struct aarch64_flag_desc
166 {
169 };
171 #define AARCH64_FUSION_PAIR(name, internal_name) \
172 { name, AARCH64_FUSE_##internal_name },
174 {
179 };
181 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
182 { name, AARCH64_EXTRA_TUNE_##internal_name },
184 {
189 };
191 /* Tuning parameters. */
194 {
195 {
200 },
207 };
210 {
211 {
216 },
223 };
226 {
227 {
232 },
239 };
242 {
243 {
248 },
255 };
258 {
259 {
264 },
271 };
274 {
275 {
280 },
287 };
290 {
292 /* Avoid the use of slow int<->fp moves for spilling by setting
293 their cost higher than memmov_cost. */
297 };
300 {
302 /* Avoid the use of slow int<->fp moves for spilling by setting
303 their cost higher than memmov_cost. */
307 };
310 {
312 /* Avoid the use of slow int<->fp moves for spilling by setting
313 their cost higher than memmov_cost. */
317 };
320 {
322 /* Avoid the use of slow int<->fp moves for spilling by setting
323 their cost higher than memmov_cost (actual, 4 and 9). */
327 };
330 {
335 };
338 {
340 /* Avoid the use of slow int<->fp moves for spilling by setting
341 their cost higher than memmov_cost. */
345 };
348 {
350 /* Avoid the use of int<->fp moves for spilling. */
354 };
357 {
359 /* Avoid the use of int<->fp moves for spilling. */
363 };
365 /* Generic costs for vector insn classes. */
367 {
381 };
383 /* ThunderX costs for vector insn classes. */
385 {
399 };
401 /* Generic costs for vector insn classes. */
403 {
417 };
420 {
434 };
436 /* Generic costs for vector insn classes. */
438 {
452 };
454 /* Costs for vector insn classes for Vulcan. */
456 {
470 };
472 /* Generic costs for branch instructions. */
474 {
477 };
479 /* Branch costs for Cortex-A57. */
481 {
484 };
486 /* Branch costs for Vulcan. */
488 {
491 };
493 /* Generic approximation modes. */
495 {
498 AARCH64_APPROX_NONE /* recip_sqrt */
499 };
501 /* Approximation modes for Exynos M1. */
503 {
506 AARCH64_APPROX_ALL /* recip_sqrt */
507 };
509 /* Approximation modes for X-Gene 1. */
511 {
514 AARCH64_APPROX_ALL /* recip_sqrt */
515 };
518 {
540 };
543 {
566 };
569 {
592 };
595 {
618 };
621 {
644 };
647 {
670 };
673 {
695 };
698 {
720 };
723 {
745 };
748 {
771 };
774 {
796 };
798 /* Support for fine-grained override of the tuning structures. */
799 struct aarch64_tuning_override_function
800 {
803 };
808 static const struct aarch64_tuning_override_function
809 aarch64_tuning_override_functions[] =
810 {
814 };
816 /* A processor implementing AArch64. */
817 struct processor
818 {
826 };
828 /* Architectures implementing AArch64. */
830 {
831 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
832 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
835 };
837 /* Processor cores implementing AArch64. */
839 {
840 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
841 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
842 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
843 FLAGS, &COSTS##_tunings},
848 };
851 /* Target specification. These are populated by the -march, -mtune, -mcpu
852 handling code or by target attributes. */
857 /* The current tuning set. */
860 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
862 /* An ISA extension in the co-processor and main instruction set space. */
863 struct aarch64_option_extension
864 {
868 };
871 {
875 }
876 aarch64_cc;
878 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
880 /* The condition codes of the processor, and the inverse function. */
882 {
885 };
887 /* Generate code to enable conditional branches in functions over 1 MiB. */
891 {
908 }
910 void
912 {
916 else
918 }
920 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
921 The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have
922 the same cost even if ALL_REGS has a much larger cost. ALL_REGS is also
923 used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory
924 cost (in this case the best class is the lowest cost one). Using ALL_REGS
925 irrespectively of its cost results in bad allocations with many redundant
926 int<->FP moves which are expensive on various cores.
927 To avoid this we don't allow ALL_REGS as the allocno class, but force a
928 decision between FP_REGS and GENERAL_REGS. We use the allocno class if it
929 isn't ALL_REGS. Similarly, use the best class if it isn't ALL_REGS.
930 Otherwise set the allocno class depending on the mode.
931 The result of this is that it is no longer inefficient to have a higher
932 memory move cost than the register move cost.
933 */
935 static reg_class_t
937 reg_class_t best_class)
938 {
949 }
951 static unsigned int
953 {
957 }
959 static int
962 {
970 }
972 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
973 unsigned
975 {
983 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
984 equivalent DWARF register. */
986 }
988 /* Return TRUE if MODE is any of the large INT modes. */
989 static bool
991 {
993 }
995 /* Return TRUE if MODE is any of the vector modes. */
996 static bool
998 {
1001 }
1003 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
1004 static bool
1007 {
1015 }
1017 /* Implement HARD_REGNO_NREGS. */
1019 int
1021 {
1023 {
1029 }
1031 }
1033 /* Implement HARD_REGNO_MODE_OK. */
1035 int
1037 {
1042 /* The purpose of comparing with ptr_mode is to support the
1043 global register variable associated with the stack pointer
1044 register via the syntax of asm ("wsp") in ILP32. */
1054 {
1056 return
1058 else
1060 }
1063 }
1065 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
1066 machine_mode
1068 machine_mode mode)
1069 {
1070 /* Handle modes that fit within single registers. */
1072 {
1075 else
1077 }
1078 /* Fall back to generic for multi-reg and very large modes. */
1079 else
1081 }
1083 /* Return true if calls to DECL should be treated as
1084 long-calls (ie called via a register). */
1085 static bool
1087 {
1089 }
1091 /* Return true if calls to symbol-ref SYM should be treated as
1092 long-calls (ie called via a register). */
1093 bool
1095 {
1097 }
1099 /* Return true if calls to symbol-ref SYM should not go through
1100 plt stubs. */
1102 bool
1104 {
1108 && decl
1109 && (!flag_plt
1115 }
1117 /* Return true if the offsets to a zero/sign-extract operation
1118 represent an expression that matches an extend operation. The
1119 operands represent the paramters from
1121 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
1122 bool
1124 rtx extract_imm)
1125 {
1142 }
1144 /* Emit an insn that's a simple single-set. Both the operands must be
1145 known to be valid. */
1148 {
1150 }
1152 /* X and Y are two things to compare using CODE. Emit the compare insn and
1153 return the rtx for register 0 in the proper mode. */
1154 rtx
1156 {
1162 }
1164 /* Build the SYMBOL_REF for __tls_get_addr. */
1168 rtx
1170 {
1174 }
1176 /* Return the TLS model to use for ADDR. */
1178 static enum tls_model
1180 {
1185 {
1189 }
1194 }
1196 /* We'll allow lo_sum's in addresses in our legitimate addresses
1197 so that combine would take care of combining addresses where
1198 necessary, but for generation purposes, we'll generate the address
1199 as :
1200 RTL Absolute
1201 tmp = hi (symbol_ref); adrp x1, foo
1202 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
1203 nop
1205 PIC TLS
1206 adrp x1, :got:foo adrp tmp, :tlsgd:foo
1207 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
1208 bl __tls_get_addr
1209 nop
1211 Load TLS symbol, depending on TLS mechanism and TLS access model.
1213 Global Dynamic - Traditional TLS:
1214 adrp tmp, :tlsgd:imm
1215 add dest, tmp, #:tlsgd_lo12:imm
1216 bl __tls_get_addr
1218 Global Dynamic - TLS Descriptors:
1219 adrp dest, :tlsdesc:imm
1220 ldr tmp, [dest, #:tlsdesc_lo12:imm]
1221 add dest, dest, #:tlsdesc_lo12:imm
1222 blr tmp
1223 mrs tp, tpidr_el0
1224 add dest, dest, tp
1226 Initial Exec:
1227 mrs tp, tpidr_el0
1228 adrp tmp, :gottprel:imm
1229 ldr dest, [tmp, #:gottprel_lo12:imm]
1230 add dest, dest, tp
1232 Local Exec:
1233 mrs tp, tpidr_el0
1234 add t0, tp, #:tprel_hi12:imm, lsl #12
1235 add t0, t0, #:tprel_lo12_nc:imm
1236 */
1238 static void
1241 {
1243 {
1245 {
1246 /* In ILP32, the mode of dest can be either SImode or DImode. */
1258 }
1265 {
1268 rtx insn;
1269 rtx mem;
1271 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
1272 here before rtl expand. Tree IVOPT will generate rtl pattern to
1273 decide rtx costs, in which case pic_offset_table_rtx is not
1274 initialized. For that case no need to generate the first adrp
1275 instruction as the final cost for global variable access is
1276 one instruction. */
1278 {
1279 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
1280 using the page base as GOT base, the first page may be wasted,
1281 in the worst scenario, there is only 28K space for GOT).
1283 The generate instruction sequence for accessing global variable
1284 is:
1286 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
1288 Only one instruction needed. But we must initialize
1289 pic_offset_table_rtx properly. We generate initialize insn for
1290 every global access, and allow CSE to remove all redundant.
1292 The final instruction sequences will look like the following
1293 for multiply global variables access.
1295 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
1297 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
1298 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
1299 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
1300 ... */
1309 }
1312 {
1315 else
1319 }
1320 else
1321 {
1326 }
1328 /* The operand is expected to be MEM. Whenever the related insn
1329 pattern changed, above code which calculate mem should be
1330 updated. */
1336 }
1339 {
1340 /* In ILP32, the mode of dest can be either SImode or DImode,
1341 while the got entry is always of SImode size. The mode of
1342 dest depends on how dest is used: if dest is assigned to a
1343 pointer (e.g. in the memory), it has SImode; it may have
1344 DImode if dest is dereferenced to access the memeory.
1345 This is why we have to handle three different ldr_got_small
1346 patterns here (two patterns for ILP32). */
1348 rtx insn;
1349 rtx mem;
1358 {
1361 else
1365 }
1366 else
1367 {
1372 }
1379 }
1382 {
1390 else
1398 }
1401 {
1404 rtx tp;
1408 /* In ILP32, the got entry is always of SImode size. Unlike
1409 small GOT, the dest is fixed at reg 0. */
1412 else
1422 }
1425 {
1426 /* In ILP32, the mode of dest can be either SImode or DImode,
1427 while the got entry is always of SImode size. The mode of
1428 dest depends on how dest is used: if dest is assigned to a
1429 pointer (e.g. in the memory), it has SImode; it may have
1430 DImode if dest is dereferenced to access the memeory.
1431 This is why we have to handle three different tlsie_small
1432 patterns here (two patterns for ILP32). */
1438 {
1441 else
1442 {
1445 }
1446 }
1447 else
1448 {
1451 }
1456 }
1462 {
1470 {
1493 }
1497 }
1504 {
1509 {
1512 else
1513 {
1516 }
1517 }
1518 else
1519 {
1522 }
1526 }
1530 }
1531 }
1533 /* Emit a move from SRC to DEST. Assume that the move expanders can
1534 handle all moves if !can_create_pseudo_p (). The distinction is
1535 important because, unlike emit_move_insn, the move expanders know
1536 how to force Pmode objects into the constant pool even when the
1537 constant pool address is not itself legitimate. */
1538 static rtx
1540 {
1544 }
1546 /* Split a 128-bit move operation into two 64-bit move operations,
1547 taking care to handle partial overlap of register to register
1548 copies. Special cases are needed when moving between GP regs and
1549 FP regs. SRC can be a register, constant or memory; DST a register
1550 or memory. If either operand is memory it must not have any side
1551 effects. */
1552 void
1554 {
1565 {
1569 /* Handle FP <-> GP regs. */
1571 {
1576 {
1579 }
1580 else
1581 {
1584 }
1586 }
1588 {
1593 {
1596 }
1597 else
1598 {
1601 }
1603 }
1604 }
1611 /* At most one pairing may overlap. */
1613 {
1616 }
1617 else
1618 {
1621 }
1622 }
1624 bool
1626 {
1629 }
1631 /* Split a complex SIMD combine. */
1633 void
1635 {
1642 {
1646 {
1670 }
1674 }
1675 }
1677 /* Split a complex SIMD move. */
1679 void
1681 {
1688 {
1694 {
1718 }
1722 }
1723 }
1725 bool
1728 {
1732 }
1735 static rtx
1737 {
1740 else
1741 {
1744 }
1745 }
1748 static rtx
1750 {
1752 {
1753 rtx high;
1754 /* Load the full offset into a register. This
1755 might be improvable in the future. */
1761 }
1763 }
1765 static int
1767 machine_mode mode)
1768 {
1777 {
1781 }
1784 {
1786 {
1791 else
1794 }
1796 }
1798 /* Remaining cases are all for DImode. */
1807 {
1808 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1809 For a 64-bit bitmask try whether changing 16 bits to all ones or
1810 zeroes creates a valid bitmask. To check any repeated bitmask,
1811 try using 16 bits from the other 32-bit half of val. */
1814 {
1825 }
1827 {
1829 {
1833 }
1835 }
1836 }
1838 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1839 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1840 otherwise skip zero bits. */
1852 {
1858 num_insns ++;
1859 }
1862 }
1865 void
1867 {
1872 /* Check on what type of symbol it is. */
1876 {
1880 /* If we have (const (plus symbol offset)), separate out the offset
1881 before we start classifying the symbol. */
1886 {
1890 {
1896 }
1901 /* If we aren't generating PC relative literals, then
1902 we need to expand the literal pool access carefully.
1903 This is something that needs to be done in a number
1904 of places, so could well live as a separate function. */
1906 {
1911 }
1928 {
1934 }
1935 /* FALLTHRU */
1948 }
1949 }
1952 {
1955 else
1956 {
1960 }
1963 }
1966 }
1968 /* Add DELTA to REGNUM in mode MODE. SCRATCHREG can be used to hold a
1969 temporary value if necessary. FRAME_RELATED_P should be true if
1970 the RTX_FRAME_RELATED flag should be set and CFA adjustments added
1971 to the generated instructions. If SCRATCHREG is known to hold
1972 abs (delta), EMIT_MOVE_IMM can be set to false to avoid emitting the
1973 immediate again.
1975 Since this function may be used to adjust the stack pointer, we must
1976 ensure that it cannot cause transient stack deallocation (for example
1977 by first incrementing SP and then decrementing when adjusting by a
1978 large immediate). */
1980 static void
1984 {
1992 /* Single instruction adjustment. */
1994 {
1998 }
2000 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits.
2001 Only do this if mdelta is not a 16-bit move as adjusting using a move
2002 is better. */
2004 {
2013 }
2015 /* Emit a move immediate if required and an addition/subtraction. */
2022 {
2026 }
2027 }
2031 HOST_WIDE_INT delta)
2032 {
2034 }
2038 {
2041 }
2045 {
2048 }
2050 static bool
2052 tree exp ATTRIBUTE_UNUSED)
2053 {
2054 /* Currently, always true. */
2056 }
2058 /* Implement TARGET_PASS_BY_REFERENCE. */
2060 static bool
2062 machine_mode mode,
2063 const_tree type,
2065 {
2066 HOST_WIDE_INT size;
2067 machine_mode dummymode;
2070 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
2074 /* Aggregates are passed by reference based on their size. */
2076 {
2078 }
2080 /* Variable sized arguments are always returned by reference. */
2084 /* Can this be a candidate to be passed in fp/simd register(s)? */
2087 NULL))
2090 /* Arguments which are variable sized or larger than 2 registers are
2091 passed by reference unless they are a homogenous floating point
2092 aggregate. */
2094 }
2096 /* Return TRUE if VALTYPE is padded to its least significant bits. */
2097 static bool
2099 {
2100 machine_mode dummy_mode;
2103 /* Never happens in little-endian mode. */
2107 /* Only composite types smaller than or equal to 16 bytes can
2108 be potentially returned in registers. */
2114 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
2115 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
2116 is always passed/returned in the least significant bits of fp/simd
2117 register(s). */
2123 }
2125 /* Implement TARGET_FUNCTION_VALUE.
2126 Define how to find the value returned by a function. */
2128 static rtx
2131 {
2132 machine_mode mode;
2135 machine_mode ag_mode;
2142 {
2146 {
2149 }
2150 }
2154 {
2156 {
2159 }
2160 else
2161 {
2163 rtx par;
2167 {
2172 }
2174 }
2175 }
2176 else
2178 }
2180 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
2181 Return true if REGNO is the number of a hard register in which the values
2182 of called function may come back. */
2184 static bool
2186 {
2187 /* Maximum of 16 bytes can be returned in the general registers. Examples
2188 of 16-byte return values are: 128-bit integers and 16-byte small
2189 structures (excluding homogeneous floating-point aggregates). */
2193 /* Up to four fp/simd registers can return a function value, e.g. a
2194 homogeneous floating-point aggregate having four members. */
2199 }
2201 /* Implement TARGET_RETURN_IN_MEMORY.
2203 If the type T of the result of a function is such that
2204 void func (T arg)
2205 would require that arg be passed as a value in a register (or set of
2206 registers) according to the parameter passing rules, then the result
2207 is returned in the same registers as would be used for such an
2208 argument. */
2210 static bool
2212 {
2213 HOST_WIDE_INT size;
2214 machine_mode ag_mode;
2220 /* Simple scalar types always returned in registers. */
2224 type,
2227 NULL))
2230 /* Types larger than 2 registers returned in memory. */
2233 }
2235 static bool
2238 {
2241 type,
2243 nregs,
2244 NULL);
2245 }
2247 /* Given MODE and TYPE of a function argument, return the alignment in
2248 bits. The idea is to suppress any stronger alignment requested by
2249 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
2250 This is a helper function for local use only. */
2252 static unsigned int
2254 {
2274 }
2276 /* Layout a function argument according to the AAPCS64 rules. The rule
2277 numbers refer to the rule numbers in the AAPCS64. */
2279 static void
2281 const_tree type,
2283 {
2287 HOST_WIDE_INT size;
2289 /* We need to do this once per argument. */
2295 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
2296 size
2298 UNITS_PER_WORD);
2302 mode,
2303 type,
2306 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
2307 The following code thus handles passing by SIMD/FP registers first. */
2311 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
2312 and homogenous short-vector aggregates (HVA). */
2314 {
2319 {
2322 {
2325 }
2326 else
2327 {
2328 rtx par;
2332 {
2335 tmp = gen_rtx_EXPR_LIST
2339 }
2341 }
2343 }
2344 else
2345 {
2346 /* C.3 NSRN is set to 8. */
2349 }
2350 }
2355 /* C6 - C9. though the sign and zero extension semantics are
2356 handled elsewhere. This is the case where the argument fits
2357 entirely general registers. */
2359 {
2364 /* C.8 if the argument has an alignment of 16 then the NGRN is
2365 rounded up to the next even number. */
2367 {
2370 }
2371 /* NREGS can be 0 when e.g. an empty structure is to be passed.
2372 A reg is still generated for it, but the caller should be smart
2373 enough not to use it. */
2375 {
2377 }
2378 else
2379 {
2380 rtx par;
2385 {
2390 }
2392 }
2396 }
2398 /* C.11 */
2401 /* The argument is passed on stack; record the needed number of words for
2402 this argument and align the total size if necessary. */
2403 on_stack:
2409 }
2411 /* Implement TARGET_FUNCTION_ARG. */
2413 static rtx
2416 {
2425 }
2427 void
2429 const_tree fntype ATTRIBUTE_UNUSED,
2430 rtx libname ATTRIBUTE_UNUSED,
2431 const_tree fndecl ATTRIBUTE_UNUSED,
2433 {
2447 {
2454 }
2456 }
2458 static void
2460 machine_mode mode,
2461 const_tree type,
2463 {
2466 {
2476 }
2477 }
2479 bool
2481 {
2484 }
2486 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2487 PARM_BOUNDARY bits of alignment, but will be given anything up
2488 to STACK_BOUNDARY bits if the type requires it. This makes sure
2489 that both before and after the layout of each argument, the Next
2490 Stacked Argument Address (NSAA) will have a minimum alignment of
2491 8 bytes. */
2493 static unsigned int
2495 {
2503 }
2505 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2507 Return true if an argument passed on the stack should be padded upwards,
2508 i.e. if the least-significant byte of the stack slot has useful data.
2510 Small aggregate types are placed in the lowest memory address.
2512 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2514 bool
2516 {
2517 /* On little-endian targets, the least significant byte of every stack
2518 argument is passed at the lowest byte address of the stack slot. */
2522 /* Otherwise, integral, floating-point and pointer types are padded downward:
2523 the least significant byte of a stack argument is passed at the highest
2524 byte address of the stack slot. */
2531 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2533 }
2535 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2537 It specifies padding for the last (may also be the only)
2538 element of a block move between registers and memory. If
2539 assuming the block is in the memory, padding upward means that
2540 the last element is padded after its highest significant byte,
2541 while in downward padding, the last element is padded at the
2542 its least significant byte side.
2544 Small aggregates and small complex types are always padded
2545 upwards.
2547 We don't need to worry about homogeneous floating-point or
2548 short-vector aggregates; their move is not affected by the
2549 padding direction determined here. Regardless of endianness,
2550 each element of such an aggregate is put in the least
2551 significant bits of a fp/simd register.
2553 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2554 register has useful data, and return the opposite if the most
2555 significant byte does. */
2557 bool
2560 {
2562 /* Small composite types are always padded upward. */
2564 {
2569 }
2571 /* Otherwise, use the default padding. */
2573 }
2575 static machine_mode
2577 {
2579 }
2581 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
2583 /* We use the 12-bit shifted immediate arithmetic instructions so values
2584 must be multiple of (1 << 12), i.e. 4096. */
2585 #define ARITH_FACTOR 4096
2587 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
2588 #error Cannot use simple address calculation for stack probing
2589 #endif
2591 /* The pair of scratch registers used for stack probing. */
2592 #define PROBE_STACK_FIRST_REG 9
2593 #define PROBE_STACK_SECOND_REG 10
2595 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
2596 inclusive. These are offsets from the current stack pointer. */
2598 static void
2600 {
2603 /* See the same assertion on PROBE_INTERVAL above. */
2606 /* See if we have a constant small number of probes to generate. If so,
2607 that's the easy case. */
2609 {
2616 }
2618 /* The run-time loop is made up of 8 insns in the generic case while the
2619 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
2621 {
2626 stack_pointer_rtx,
2630 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
2631 it exceeds SIZE. If only two probes are needed, this will not
2632 generate any code. Then probe at FIRST + SIZE. */
2634 {
2638 }
2642 {
2647 }
2648 else
2650 }
2652 /* Otherwise, do the same as above, but in a loop. Note that we must be
2653 extra careful with variables wrapping around because we might be at
2654 the very top (or the very bottom) of the address space and we have
2655 to be able to handle this case properly; in particular, we use an
2656 equality test for the loop condition. */
2657 else
2658 {
2661 /* Step 1: round SIZE to the previous multiple of the interval. */
2666 /* Step 2: compute initial and final value of the loop counter. */
2668 /* TEST_ADDR = SP + FIRST. */
2672 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
2678 /* Step 3: the loop
2680 do
2681 {
2682 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
2683 probe at TEST_ADDR
2684 }
2685 while (TEST_ADDR != LAST_ADDR)
2687 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
2688 until it is equal to ROUNDED_SIZE. */
2692 else
2696 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
2697 that SIZE is equal to ROUNDED_SIZE. */
2700 {
2704 {
2709 }
2710 else
2712 }
2713 }
2715 /* Make sure nothing is scheduled before we are done. */
2717 }
2719 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
2720 absolute addresses. */
2724 {
2731 /* Loop. */
2734 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
2739 /* Probe at TEST_ADDR. */
2742 /* Test if TEST_ADDR == LAST_ADDR. */
2746 /* Branch. */
2752 }
2754 static bool
2756 {
2757 /* In aarch64_override_options_after_change
2758 flag_omit_leaf_frame_pointer turns off the frame pointer by
2759 default. Turn it back on now if we've not got a leaf
2760 function. */
2765 /* Force a frame pointer for EH returns so the return address is at FP+8. */
2770 }
2772 /* Mark the registers that need to be saved by the callee and calculate
2773 the size of the callee-saved registers area and frame record (both FP
2774 and LR may be omitted). */
2775 static void
2777 {
2784 #define SLOT_NOT_REQUIRED (-2)
2785 #define SLOT_REQUIRED (-1)
2790 /* First mark all the registers that really need to be saved... */
2797 /* ... that includes the eh data registers (if needed)... */
2803 /* ... and any callee saved register that dataflow says is live. */
2813 {
2816 }
2819 {
2820 /* FP and LR are placed in the linkage record. */
2826 }
2828 /* Now assign stack slots for them. */
2831 {
2838 }
2846 {
2847 /* If there is an alignment gap between integer and fp callee-saves,
2848 allocate the last fp register to it if possible. */
2850 {
2853 }
2862 }
2868 HOST_WIDE_INT varargs_and_saved_regs_size
2895 {
2896 /* Simple, small frame with no outgoing arguments:
2897 stp reg1, reg2, [sp, -frame_size]!
2898 stp reg3, reg4, [sp, 16] */
2900 }
2905 {
2906 /* Frame with small outgoing arguments:
2907 sub sp, sp, frame_size
2908 stp reg1, reg2, [sp, outgoing_args_size]
2909 stp reg3, reg4, [sp, outgoing_args_size + 16] */
2913 }
2915 {
2916 /* Frame with large outgoing arguments but a small local area:
2917 stp reg1, reg2, [sp, -hard_fp_offset]!
2918 stp reg3, reg4, [sp, 16]
2919 sub sp, sp, outgoing_args_size */
2923 }
2926 {
2927 /* Frame with large local area and outgoing arguments (this pushes the
2928 callee-saves first, followed by the locals and outgoing area):
2929 stp reg1, reg2, [sp, -varargs_and_saved_regs_size]!
2930 stp reg3, reg4, [sp, 16]
2931 sub sp, sp, frame_size - varargs_and_saved_regs_size */
2937 }
2938 else
2939 {
2940 /* Frame with large local area and outgoing arguments using frame pointer:
2941 sub sp, sp, hard_fp_offset
2942 stp x29, x30, [sp, 0]
2943 add x29, sp, 0
2944 stp reg3, reg4, [sp, 16]
2945 sub sp, sp, outgoing_args_size */
2949 }
2952 }
2954 /* Return true if the register REGNO is saved on entry to
2955 the current function. */
2957 static bool
2959 {
2961 }
2963 /* Return the next register up from REGNO up to LIMIT for the callee
2964 to save. */
2966 static unsigned
2968 {
2970 regno ++;
2972 }
2974 /* Push the register number REGNO of mode MODE to the stack with write-back
2975 adjusting the stack by ADJUSTMENT. */
2977 static void
2979 HOST_WIDE_INT adjustment)
2980 {
2991 }
2993 /* Generate and return an instruction to store the pair of registers
2994 REG and REG2 of mode MODE to location BASE with write-back adjusting
2995 the stack location BASE by ADJUSTMENT. */
2997 static rtx
2999 HOST_WIDE_INT adjustment)
3000 {
3002 {
3013 }
3014 }
3016 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
3017 stack pointer by ADJUSTMENT. */
3019 static void
3021 {
3036 }
3038 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
3039 adjusting it by ADJUSTMENT afterwards. */
3041 static rtx
3043 HOST_WIDE_INT adjustment)
3044 {
3046 {
3055 }
3056 }
3058 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
3059 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
3060 into CFI_OPS. */
3062 static void
3065 {
3072 {
3076 }
3077 else
3078 {
3083 }
3084 }
3086 /* Generate and return a store pair instruction of mode MODE to store
3087 register REG1 to MEM1 and register REG2 to MEM2. */
3089 static rtx
3091 rtx reg2)
3092 {
3094 {
3103 }
3104 }
3106 /* Generate and regurn a load pair isntruction of mode MODE to load register
3107 REG1 from MEM1 and register REG2 from MEM2. */
3109 static rtx
3111 rtx mem2)
3112 {
3114 {
3123 }
3124 }
3126 /* Emit code to save the callee-saved registers from register number START
3127 to LIMIT to the stack at the location starting at offset START_OFFSET,
3128 skipping any write-back candidates if SKIP_WB is true. */
3130 static void
3133 {
3143 {
3145 HOST_WIDE_INT offset;
3158 offset));
3167 {
3169 rtx mem2;
3173 offset));
3175 reg2));
3177 /* The first part of a frame-related parallel insn is
3178 always assumed to be relevant to the frame
3179 calculations; subsequent parts, are only
3180 frame-related if explicitly marked. */
3183 }
3184 else
3188 }
3189 }
3191 /* Emit code to restore the callee registers of mode MODE from register
3192 number START up to and including LIMIT. Restore from the stack offset
3193 START_OFFSET, skipping any write-back candidates if SKIP_WB is true.
3194 Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */
3196 static void
3200 {
3206 HOST_WIDE_INT offset;
3211 {
3232 {
3234 rtx mem2;
3242 }
3243 else
3246 }
3247 }
3251 HOST_WIDE_INT offset)
3252 {
3254 }
3258 {
3262 }
3264 bool
3266 {
3270 }
3272 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
3274 static sbitmap
3276 {
3282 /* The registers we need saved to the frame. */
3285 {
3290 /* Check that we can access the stack slot of the register with one
3291 direct load with no adjustments needed. */
3294 }
3296 /* Don't mess with the hard frame pointer. */
3302 /* If aarch64_layout_frame has chosen registers to store/restore with
3303 writeback don't interfere with them to avoid having to output explicit
3304 stack adjustment instructions. */
3314 }
3316 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
3318 static sbitmap
3320 {
3328 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
3337 }
3339 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
3340 Nothing to do for aarch64. */
3342 static void
3344 {
3345 }
3347 /* Return the next set bit in BMP from START onwards. Return the total number
3348 of bits in BMP if no set bit is found at or after START. */
3350 static unsigned int
3352 {
3363 }
3365 /* Do the work for aarch64_emit_prologue_components and
3366 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
3367 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
3368 for these components or the epilogue sequence. That is, it determines
3369 whether we should emit stores or loads and what kind of CFA notes to attach
3370 to the insns. Otherwise the logic for the two sequences is very
3371 similar. */
3373 static void
3375 {
3377 ? HARD_FRAME_POINTER_REGNUM
3385 {
3386 /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
3387 so DFmode for the vector registers is enough. */
3399 /* No more registers to handle after REGNO.
3400 Emit a single save/restore and exit. */
3402 {
3407 else
3410 }
3413 /* The next register is not of the same class or its offset is not
3414 mergeable with the current one into a pair. */
3419 {
3424 else
3429 }
3431 /* REGNO2 can be saved/restored in a pair with REGNO. */
3443 else
3448 {
3451 }
3452 else
3453 {
3456 }
3459 }
3460 }
3462 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
3464 static void
3466 {
3468 }
3470 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
3472 static void
3474 {
3476 }
3478 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
3480 static void
3482 {
3486 }
3488 /* AArch64 stack frames generated by this compiler look like:
3490 +-------------------------------+
3491 | |
3492 | incoming stack arguments |
3493 | |
3494 +-------------------------------+
3495 | | <-- incoming stack pointer (aligned)
3496 | callee-allocated save area |
3497 | for register varargs |
3498 | |
3499 +-------------------------------+
3500 | local variables | <-- frame_pointer_rtx
3501 | |
3502 +-------------------------------+
3503 | padding0 | \
3504 +-------------------------------+ |
3505 | callee-saved registers | | frame.saved_regs_size
3506 +-------------------------------+ |
3507 | LR' | |
3508 +-------------------------------+ |
3509 | FP' | / <- hard_frame_pointer_rtx (aligned)
3510 +-------------------------------+
3511 | dynamic allocation |
3512 +-------------------------------+
3513 | padding |
3514 +-------------------------------+
3515 | outgoing stack arguments | <-- arg_pointer
3516 | |
3517 +-------------------------------+
3518 | | <-- stack_pointer_rtx (aligned)
3520 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
3521 but leave frame_pointer_rtx and hard_frame_pointer_rtx
3522 unchanged. */
3524 /* Generate the prologue instructions for entry into a function.
3525 Establish the stack frame by decreasing the stack pointer with a
3526 properly calculated size and, if necessary, create a frame record
3527 filled with the values of LR and previous frame pointer. The
3528 current FP is also set up if it is in use. */
3530 void
3532 {
3548 {
3550 {
3554 }
3557 }
3565 {
3570 stack_pointer_rtx,
3574 }
3581 }
3583 /* Return TRUE if we can use a simple_return insn.
3585 This function checks whether the callee saved stack is empty, which
3586 means no restore actions are need. The pro_and_epilogue will use
3587 this to check whether shrink-wrapping opt is feasible. */
3589 bool
3591 {
3601 }
3603 /* Generate the epilogue instructions for returning from a function.
3604 This is almost exactly the reverse of the prolog sequence, except
3605 that we need to insert barriers to avoid scheduling loads that read
3606 from a deallocated stack, and we optimize the unwind records by
3607 emitting them all together if possible. */
3608 void
3610 {
3622 /* We need to add memory barrier to prevent read from deallocated stack. */
3626 /* Emit a barrier to prevent loads from a deallocated stack. */
3629 {
3632 }
3634 /* Restore the stack pointer from the frame pointer if it may not
3635 be the same as the stack pointer. */
3637 {
3639 hard_frame_pointer_rtx,
3641 /* If writeback is used when restoring callee-saves, the CFA
3642 is restored on the instruction doing the writeback. */
3644 }
3645 else
3660 {
3661 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
3667 }
3672 {
3673 /* Emit delayed restores and reset the CFA to be SP. */
3678 }
3680 /* Stack adjustment for exception handler. */
3682 {
3683 /* We need to unwind the stack by the offset computed by
3684 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
3685 to be SP; letting the CFA move during this adjustment
3686 is just as correct as retaining the CFA from the body
3687 of the function. Therefore, do nothing special. */
3689 }
3694 }
3696 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
3697 normally or return to a previous frame after unwinding.
3699 An EH return uses a single shared return sequence. The epilogue is
3700 exactly like a normal epilogue except that it has an extra input
3701 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
3702 that must be applied after the frame has been destroyed. An extra label
3703 is inserted before the epilogue which initializes this register to zero,
3704 and this is the entry point for a normal return.
3706 An actual EH return updates the return address, initializes the stack
3707 adjustment and jumps directly into the epilogue (bypassing the zeroing
3708 of the adjustment). Since the return address is typically saved on the
3709 stack when a function makes a call, the saved LR must be updated outside
3710 the epilogue.
3712 This poses problems as the store is generated well before the epilogue,
3713 so the offset of LR is not known yet. Also optimizations will remove the
3714 store as it appears dead, even after the epilogue is generated (as the
3715 base or offset for loading LR is different in many cases).
3717 To avoid these problems this implementation forces the frame pointer
3718 in eh_return functions so that the location of LR is fixed and known early.
3719 It also marks the store volatile, so no optimization is permitted to
3720 remove the store. */
3721 rtx
3723 {
3727 /* Mark the store volatile, so no optimization is permitted to remove it. */
3730 }
3732 /* Output code to add DELTA to the first argument, and then jump
3733 to FUNCTION. Used for C++ multiple inheritance. */
3734 static void
3736 HOST_WIDE_INT delta,
3737 HOST_WIDE_INT vcall_offset,
3738 tree function)
3739 {
3740 /* The this pointer is always in x0. Note that this differs from
3741 Arm where the this pointer maybe bumped to r1 if r0 is required
3742 to return a pointer to an aggregate. On AArch64 a result value
3743 pointer will be in x8. */
3753 else
3754 {
3763 {
3767 else
3769 }
3773 else
3780 else
3781 {
3783 Pmode);
3785 }
3789 else
3795 }
3797 /* Generate a tail call to the target function. */
3799 {
3802 }
3814 /* Stop pretending to be a post-reload pass. */
3816 }
3818 static bool
3820 {
3825 {
3829 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3830 TLS offsets, not real symbol references. */
3833 }
3835 }
3838 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3839 a left shift of 0 or 12 bits. */
3840 bool
3842 {
3845 );
3846 }
3849 /* Return true if val is an immediate that can be loaded into a
3850 register by a MOVZ instruction. */
3851 static bool
3853 {
3855 {
3859 }
3860 else
3861 {
3862 /* Ignore sign extension. */
3864 }
3867 }
3869 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3872 {
3878 };
3881 /* Return true if val is a valid bitmask immediate. */
3883 bool
3885 {
3889 /* Check for a single sequence of one bits and return quickly if so.
3890 The special cases of all ones and all zeroes returns false. */
3897 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3901 /* Invert if the immediate doesn't start with a zero bit - this means we
3902 only need to search for sequences of one bits. */
3906 /* Find the first set bit and set tmp to val with the first sequence of one
3907 bits removed. Return success if there is a single sequence of ones. */
3914 /* Find the next set bit and compute the difference in bit position. */
3919 /* Check the bit position difference is a power of 2, and that the first
3920 sequence of one bits fits within 'bits' bits. */
3924 /* Check the sequence of one bits is repeated 64/bits times. */
3926 }
3928 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
3929 Assumed precondition: VAL_IN Is not zero. */
3931 unsigned HOST_WIDE_INT
3933 {
3940 }
3942 /* Create constant where bits outside of lowest bit set to highest bit set
3943 are set to 1. */
3945 unsigned HOST_WIDE_INT
3947 {
3949 }
3951 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
3953 bool
3955 {
3965 }
3967 /* Return true if val is an immediate that can be loaded into a
3968 register in a single instruction. */
3969 bool
3971 {
3975 }
3977 static bool
3979 {
3987 {
3991 else
3992 /* Avoid generating a 64-bit relocation in ILP32; leave
3993 to aarch64_expand_mov_immediate to handle it properly. */
3995 }
3998 }
4000 /* Implement TARGET_CASE_VALUES_THRESHOLD.
4001 The expansion for a table switch is quite expensive due to the number
4002 of instructions, the table lookup and hard to predict indirect jump.
4003 When optimizing for speed, and -O3 enabled, use the per-core tuning if
4004 set, otherwise use tables for > 16 cases as a tradeoff between size and
4005 performance. When optimizing for size, use the default setting. */
4007 static unsigned int
4009 {
4010 /* Use the specified limit for the number of cases before using jump
4011 tables at higher optimization levels. */
4015 else
4017 }
4019 /* Return true if register REGNO is a valid index register.
4020 STRICT_P is true if REG_OK_STRICT is in effect. */
4022 bool
4024 {
4026 {
4034 }
4036 }
4038 /* Return true if register REGNO is a valid base register for mode MODE.
4039 STRICT_P is true if REG_OK_STRICT is in effect. */
4041 bool
4043 {
4045 {
4053 }
4055 /* The fake registers will be eliminated to either the stack or
4056 hard frame pointer, both of which are usually valid base registers.
4057 Reload deals with the cases where the eliminated form isn't valid. */
4062 }
4064 /* Return true if X is a valid base register for mode MODE.
4065 STRICT_P is true if REG_OK_STRICT is in effect. */
4067 static bool
4069 {
4074 }
4076 /* Return true if address offset is a valid index. If it is, fill in INFO
4077 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
4079 static bool
4082 {
4084 rtx index;
4087 /* (reg:P) */
4090 {
4094 }
4095 /* (sign_extend:DI (reg:SI)) */
4100 {
4105 }
4106 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
4113 {
4118 }
4119 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
4126 {
4131 }
4132 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
4139 {
4147 }
4148 /* (and:DI (mult:DI (reg:DI) (const_int scale))
4149 (const_int 0xffffffff<<shift)) */
4156 {
4162 }
4163 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
4170 {
4178 }
4179 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
4180 (const_int 0xffffffff<<shift)) */
4187 {
4193 }
4194 /* (mult:P (reg:P) (const_int scale)) */
4199 {
4203 }
4204 /* (ashift:P (reg:P) (const_int shift)) */
4209 {
4213 }
4214 else
4225 {
4230 }
4233 }
4235 /* Return true if MODE is one of the modes for which we
4236 support LDP/STP operations. */
4238 static bool
4240 {
4245 }
4247 /* Return true if REGNO is a virtual pointer register, or an eliminable
4248 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
4249 include stack_pointer or hard_frame_pointer. */
4250 static bool
4252 {
4257 }
4259 /* Return true if X is a valid address for machine mode MODE. If it is,
4260 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
4261 effect. OUTER_CODE is PARALLEL for a load/store pair. */
4263 static bool
4267 {
4271 /* On BE, we use load/store pair for all large int mode load/stores.
4272 TI/TFmode may also use a load/store pair. */
4276 || (BYTES_BIG_ENDIAN
4280 !load_store_pair_p
4284 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
4285 REG addressing. */
4291 {
4307 {
4313 }
4318 {
4325 /* TImode and TFmode values are allowed in both pairs of X
4326 registers and individual Q registers. The available
4327 address modes are:
4328 X,X: 7-bit signed scaled offset
4329 Q: 9-bit signed offset
4330 We conservatively require an offset representable in either mode.
4331 When performing the check for pairs of X registers i.e. LDP/STP
4332 pass down DImode since that is the natural size of the LDP/STP
4333 instruction memory accesses. */
4339 /* A 7bit offset check because OImode will emit a ldp/stp
4340 instruction (only big endian will get here).
4341 For ldp/stp instructions, the offset is scaled for the size of a
4342 single element of the pair. */
4346 /* Three 9/12 bit offsets checks because CImode will emit three
4347 ldr/str instructions (only big endian will get here). */
4354 /* Two 7bit offsets checks because XImode will emit two ldp/stp
4355 instructions (only big endian will get here). */
4364 else
4367 }
4370 {
4371 /* Look for base + (scaled/extended) index register. */
4374 {
4377 }
4380 {
4383 }
4384 }
4405 {
4406 HOST_WIDE_INT offset;
4410 /* TImode and TFmode values are allowed in both pairs of X
4411 registers and individual Q registers. The available
4412 address modes are:
4413 X,X: 7-bit signed scaled offset
4414 Q: 9-bit signed offset
4415 We conservatively require an offset representable in either mode.
4416 */
4424 else
4426 }
4432 /* load literal: pc-relative constant pool entry. Only supported
4433 for SI mode or larger. */
4437 {
4445 }
4454 {
4459 {
4460 /* The symbol and offset must be aligned to the access size. */
4467 {
4471 }
4477 else
4486 }
4487 }
4492 }
4493 }
4495 bool
4497 {
4498 rtx offset;
4502 }
4504 /* Classify the base of symbolic expression X. */
4506 enum aarch64_symbol_type
4508 {
4509 rtx offset;
4513 }
4516 /* Return TRUE if X is a legitimate address for accessing memory in
4517 mode MODE. */
4518 static bool
4520 {
4524 }
4526 /* Return TRUE if X is a legitimate address for accessing memory in
4527 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
4528 pair operation. */
4529 bool
4532 {
4536 }
4538 /* Split an out-of-range address displacement into a base and offset.
4539 Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
4540 to increase opportunities for sharing the base address of different sizes.
4541 For unaligned accesses and TI/TF mode use the signed 9-bit range. */
4542 static bool
4544 {
4555 }
4557 /* Return TRUE if rtx X is immediate constant 0.0 */
4558 bool
4560 {
4567 }
4569 /* Return the fixed registers used for condition codes. */
4571 static bool
4573 {
4577 }
4579 /* Emit call insn with PAT and do aarch64-specific handling. */
4581 void
4583 {
4589 }
4591 machine_mode
4593 {
4594 /* All floating point compares return CCFP if it is an equality
4595 comparison, and CCFPE otherwise. */
4597 {
4599 {
4620 }
4621 }
4623 /* Equality comparisons of short modes against zero can be performed
4624 using the TST instruction with the appropriate bitmask. */
4630 /* Similarly, comparisons of zero_extends from shorter modes can
4631 be performed using an ANDS with an immediate mask. */
4647 /* A compare with a shifted operand. Because of canonicalization,
4648 the comparison will have to be swapped when we emit the assembly
4649 code. */
4657 /* Similarly for a negated operand, but we can only do this for
4658 equalities. */
4665 /* A test for unsigned overflow. */
4672 /* For everything else, return CCmode. */
4674 }
4676 static int
4679 int
4681 {
4688 }
4690 static int
4692 {
4694 {
4698 {
4712 }
4717 {
4729 }
4734 {
4746 }
4751 {
4757 }
4762 {
4766 }
4771 {
4775 }
4780 }
4783 }
4785 bool
4787 HOST_WIDE_INT minval,
4788 HOST_WIDE_INT maxval)
4789 {
4790 HOST_WIDE_INT firstval;
4807 }
4809 bool
4811 {
4813 }
4816 /* N Z C V. */
4817 #define AARCH64_CC_V 1
4818 #define AARCH64_CC_C (1 << 1)
4819 #define AARCH64_CC_Z (1 << 2)
4820 #define AARCH64_CC_N (1 << 3)
4822 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
4824 {
4841 };
4843 static void
4845 {
4847 {
4848 /* An integer or symbol address without a preceding # sign. */
4851 {
4863 {
4866 }
4867 /* Fall through. */
4871 }
4875 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4876 {
4881 {
4884 }
4887 {
4900 }
4901 }
4905 {
4908 /* Print N such that 2^N == X. */
4910 {
4913 }
4916 }
4920 /* Print the number of non-zero bits in X (a const_int). */
4922 {
4925 }
4931 /* Print the higher numbered register of a pair (TImode) of regs. */
4933 {
4936 }
4943 {
4945 /* Print a condition (eq, ne, etc) or its inverse. */
4947 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
4949 {
4953 }
4956 {
4959 }
4966 }
4974 /* Print a scalar FP/SIMD register name. */
4976 {
4977 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4979 }
4987 /* Print the first FP/SIMD register name in a list. */
4989 {
4990 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4992 }
4997 /* Print a scalar FP/SIMD register name + 1. */
4999 {
5000 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
5002 }
5007 /* Print bottom 16 bits of integer constant in hex. */
5009 {
5012 }
5018 /* Print a general register name or the zero register (32-bit or
5019 64-bit). */
5022 {
5025 }
5028 {
5031 }
5034 {
5037 }
5039 /* Fall through */
5042 /* Print a normal operand, if it's a general register, then we
5043 assume DImode. */
5045 {
5048 }
5051 {
5072 {
5075 HOST_WIDE_INT_MIN,
5076 HOST_WIDE_INT_MAX));
5078 }
5080 {
5082 }
5083 else
5088 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
5089 be getting CONST_DOUBLEs holding integers. */
5092 {
5095 }
5097 {
5098 #define buf_size 20
5106 #undef buf_size
5107 }
5113 }
5121 {
5148 }
5154 {
5189 }
5196 {
5202 }
5207 {
5208 HOST_WIDE_INT cond_code;
5209 /* Print nzcv. */
5212 {
5215 }
5220 }
5226 }
5227 }
5229 static void
5231 {
5236 {
5240 else
5249 else
5258 else
5267 else
5274 {
5301 }
5312 }
5315 }
5317 bool
5319 {
5326 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
5327 referencing instruction, but they are constant offsets, not
5328 symbols. */
5334 {
5336 {
5342 }
5345 }
5348 }
5350 /* Implement REGNO_REG_CLASS. */
5352 enum reg_class
5354 {
5369 }
5371 static rtx
5373 {
5374 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
5375 where mask is selected by alignment and size of the offset.
5376 We try to pick as large a range for the offset as possible to
5377 maximize the chance of a CSE. However, for aligned addresses
5378 we limit the range to 4k so that structures with different sized
5379 elements are likely to use the same base. We need to be careful
5380 not to split a CONST for some forms of address expression, otherwise
5381 it will generate sub-optimal code. */
5384 {
5390 {
5394 /* Force any scaling into a temp for CSE. */
5398 /* Let the pointer register be in op0. */
5402 /* If the pointer is virtual or frame related, then we know that
5403 virtual register instantiation or register elimination is going
5404 to apply a second constant. We want the two constants folded
5405 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
5407 {
5411 }
5413 /* Otherwise, in order to encourage CSE (and thence loop strength
5414 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
5418 }
5420 /* Does it look like we'll need a 16-byte load/store-pair operation? */
5421 HOST_WIDE_INT base_offset;
5424 /* For offsets aren't a multiple of the access size, the limit is
5425 -256...255. */
5427 {
5430 /* BLKmode typically uses LDP of X-registers. */
5433 }
5434 /* Small negative offsets are supported. */
5439 /* Use 12-bit offset by access size. */
5440 else
5444 {
5448 }
5449 }
5452 }
5454 /* Return the reload icode required for a constant pool in mode. */
5455 static enum insn_code
5457 {
5459 {
5495 }
5498 }
5499 static reg_class_t
5501 reg_class_t rclass,
5502 machine_mode mode,
5504 {
5506 /* If we have to disable direct literal pool loads and stores because the
5507 function is too big, then we need a scratch register. */
5512 {
5515 }
5517 /* Without the TARGET_SIMD instructions we cannot move a Q register
5518 to a Q register directly. We need a scratch. */
5522 {
5528 }
5530 /* A TFmode or TImode memory access should be handled via an FP_REGS
5531 because AArch64 has richer addressing modes for LDR/STR instructions
5532 than LDP/STP instructions. */
5541 }
5543 static bool
5545 {
5546 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
5547 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
5550 {
5562 }
5563 else
5564 {
5565 /* If we decided that we didn't need a leaf frame pointer but then used
5566 LR in the function, then we'll want a frame pointer after all, so
5567 prevent this elimination to ensure a frame pointer is used. */
5569 && flag_omit_leaf_frame_pointer
5572 }
5575 }
5577 HOST_WIDE_INT
5579 {
5583 {
5590 }
5593 {
5597 }
5600 }
5602 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
5603 previous frame. */
5605 rtx
5607 {
5611 }
5614 static void
5616 {
5618 {
5621 }
5622 else
5623 {
5626 }
5631 }
5633 static void
5635 {
5639 /* Don't need to copy the trailing D-words, we fill those in below. */
5651 /* XXX We should really define a "clear_cache" pattern and use
5652 gen_clear_cache(). */
5657 ptr_mode);
5658 }
5660 static unsigned char
5662 {
5664 {
5671 return
5683 }
5685 }
5687 static reg_class_t
5689 {
5694 {
5700 }
5702 /* If it's an integer immediate that MOVI can't handle, then
5703 FP_REGS is not an option, so we return NO_REGS instead. */
5708 /* Register eliminiation can result in a request for
5709 SP+constant->FP_REGS. We cannot support such operations which
5710 use SP as source and an FP_REG as destination, so reject out
5711 right now. */
5713 {
5716 /* Look through a possible SUBREG introduced by ILP32. */
5722 POINTER_REGS));
5724 }
5727 }
5729 void
5731 {
5733 }
5735 static void
5737 {
5740 else
5741 {
5749 }
5750 }
5752 static void
5754 {
5757 else
5758 {
5766 }
5767 }
5771 {
5777 {
5778 {
5781 },
5782 {
5785 },
5786 {
5789 },
5790 /* We assume that DImode is only generated when not optimizing and
5791 that we don't really need 64-bit address offsets. That would
5792 imply an object file with 8GB of code in a single function! */
5793 {
5796 }
5797 };
5805 /* Need to implement table size reduction, by chaning the code below. */
5815 }
5818 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5819 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5820 operator. */
5822 int
5824 {
5826 {
5829 {
5833 }
5834 }
5836 }
5838 /* Constant pools are per function only when PC relative
5839 literal loads are true or we are in the large memory
5840 model. */
5844 {
5847 }
5849 static bool
5851 {
5852 /* Fixme:: In an ideal world this would work similar
5853 to the logic in aarch64_select_rtx_section but this
5854 breaks bootstrap in gcc go. For now we workaround
5855 this by returning false here. */
5857 }
5859 /* Select appropriate section for constants depending
5860 on where we place literal pools. */
5864 rtx x,
5866 {
5871 }
5873 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
5874 void
5876 HOST_WIDE_INT offset)
5877 {
5878 /* When using per-function literal pools, we must ensure that any code
5879 section is aligned to the minimal instruction length, lest we get
5880 errors from the assembler re "unaligned instructions". */
5883 }
5885 /* Costs. */
5887 /* Helper function for rtx cost calculation. Strip a shift expression
5888 from X. Returns the inner operand if successful, or the original
5889 expression on failure. */
5890 static rtx
5892 {
5895 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5896 we can convert both to ROR during final output. */
5911 }
5913 /* Helper function for rtx cost calculation. Strip an extend
5914 expression from X. Returns the inner operand if successful, or the
5915 original expression on failure. We deal with a number of possible
5916 canonicalization variations here. */
5917 static rtx
5919 {
5922 /* Zero and sign extraction of a widened value. */
5930 /* It can also be represented (for zero-extend) as an AND with an
5931 immediate. */
5940 /* Now handle extended register, as this may also have an optional
5941 left shift by 1..4. */
5955 }
5957 /* Return true iff CODE is a shift supported in combination
5958 with arithmetic instructions. */
5960 static bool
5962 {
5964 }
5966 /* Helper function for rtx cost calculation. Calculate the cost of
5967 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5968 Return the calculated cost of the expression, recursing manually in to
5969 operands where needed. */
5971 static int
5973 {
5989 /* Integer multiply/fma. */
5991 {
5992 /* The multiply will be canonicalized as a shift, cost it as such. */
5996 {
6000 {
6002 {
6004 /* ARITH + shift-by-register. */
6007 /* ARITH + extended register. We don't have a cost field
6008 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
6010 else
6011 /* ARITH + shift-by-immediate. */
6013 }
6014 else
6015 /* LSL (immediate). */
6018 }
6019 /* Strip extends as we will have costed them in the case above. */
6026 }
6028 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
6029 compound and let the below cases handle it. After all, MNEG is a
6030 special-case alias of MSUB. */
6032 {
6035 }
6037 /* Integer multiplies or FMAs have zero/sign extending variants. */
6042 {
6047 {
6049 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
6051 else
6052 /* MUL/SMULL/UMULL. */
6054 }
6057 }
6059 /* This is either an integer multiply or a MADD. In both cases
6060 we want to recurse and cost the operands. */
6065 {
6067 /* MADD/MSUB. */
6069 else
6070 /* MUL. */
6072 }
6075 }
6076 else
6077 {
6079 {
6080 /* Floating-point FMA/FMUL can also support negations of the
6081 operands, unless the rounding mode is upward or downward in
6082 which case FNMUL is different than FMUL with operand negation. */
6086 {
6091 }
6094 /* FMADD/FNMADD/FNMSUB/FMSUB. */
6096 else
6097 /* FMUL/FNMUL. */
6099 }
6104 }
6105 }
6107 static int
6109 machine_mode mode,
6110 addr_space_t as ATTRIBUTE_UNUSED,
6112 {
6120 {
6122 {
6123 /* This is a CONST or SYMBOL ref which will be split
6124 in a different way depending on the code model in use.
6125 Cost it through the generic infrastructure. */
6127 /* Divide through by the cost of one instruction to
6128 bring it to the same units as the address costs. */
6130 /* The cost is then the cost of preparing the address,
6131 followed by an immediate (possibly 0) offset. */
6133 }
6134 else
6135 {
6136 /* This is most likely a jump table from a case
6137 statement. */
6139 }
6140 }
6143 {
6155 else
6174 }
6178 {
6179 /* For the sake of calculating the cost of the shifted register
6180 component, we can treat same sized modes in the same way. */
6182 {
6195 /* We can't tell, or this is a 128-bit vector. */
6199 }
6200 }
6203 }
6205 /* Return the cost of a branch. If SPEED_P is true then the compiler is
6206 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
6207 to be taken. */
6209 int
6211 {
6212 /* When optimizing for speed, use the cost of unpredictable branches. */
6218 else
6220 }
6222 /* Return true if the RTX X in mode MODE is a zero or sign extract
6223 usable in an ADD or SUB (extended register) instruction. */
6224 static bool
6226 {
6227 /* Catch add with a sign extract.
6228 This is add_<optab><mode>_multp2. */
6231 {
6242 op1))
6243 {
6245 }
6246 }
6247 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
6248 No shift. */
6254 }
6256 static bool
6258 {
6260 {
6272 }
6273 }
6275 /* Return true iff X is an rtx that will match an extr instruction
6276 i.e. as described in the *extr<mode>5_insn family of patterns.
6277 OP0 and OP1 will be set to the operands of the shifts involved
6278 on success and will be NULL_RTX otherwise. */
6280 static bool
6282 {
6297 {
6298 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
6310 {
6314 }
6315 }
6318 }
6320 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
6321 storing it in *COST. Result is true if the total cost of the operation
6322 has now been calculated. */
6323 static bool
6325 {
6326 rtx inner;
6327 rtx comparator;
6331 {
6335 }
6336 else
6337 {
6341 }
6344 {
6345 /* Conditional branch. */
6348 else
6349 {
6351 {
6353 {
6354 /* TBZ/TBNZ/CBZ/CBNZ. */
6356 /* TBZ/TBNZ. */
6359 else
6360 /* CBZ/CBNZ. */
6364 }
6365 }
6367 {
6368 /* TBZ/TBNZ. */
6371 }
6372 }
6373 }
6375 {
6376 /* CCMP. */
6378 {
6379 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
6383 {
6390 else
6392 }
6394 }
6396 /* It's a conditional operation based on the status flags,
6397 so it must be some flavor of CSEL. */
6399 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
6405 {
6406 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
6409 }
6414 }
6416 /* We don't know what this is, cost all operands. */
6418 }
6420 /* Check whether X is a bitfield operation of the form shift + extend that
6421 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
6422 operand to which the bitfield operation is applied. Otherwise return
6423 NULL_RTX. */
6425 static rtx
6427 {
6441 {
6459 }
6462 }
6464 /* Return true if the mask and a shift amount from an RTX of the form
6465 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
6466 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
6468 bool
6470 {
6475 }
6477 /* Calculate the cost of calculating X, storing it in *COST. Result
6478 is true if the total cost of the operation has now been calculated. */
6479 static bool
6482 {
6488 /* By default, assume that everything has equivalent cost to the
6489 cheapest instruction. Any additional costs are applied as a delta
6490 above this default. */
6494 {
6496 /* The cost depends entirely on the operands to SET. */
6502 {
6505 {
6519 }
6528 /* Fall through. */
6530 /* The cost is one per vector-register copied. */
6532 {
6536 }
6537 /* const0_rtx is in general free, but we will use an
6538 instruction to set a register to 0. */
6540 {
6541 /* The cost is 1 per register copied. */
6545 }
6546 else
6547 /* Cost is just the cost of the RHS of the set. */
6553 /* Bit-field insertion. Strip any redundant widening of
6554 the RHS to meet the width of the target. */
6565 {
6566 /* MOV immediate is assumed to always be cheap. */
6568 }
6569 else
6570 {
6571 /* BFM. */
6575 }
6580 /* We can't make sense of this, assume default cost. */
6583 }
6587 /* If an instruction can incorporate a constant within the
6588 instruction, the instruction's expression avoids calling
6589 rtx_cost() on the constant. If rtx_cost() is called on a
6590 constant, then it is usually because the constant must be
6591 moved into a register by one or more instructions.
6593 The exception is constant 0, which can be expressed
6594 as XZR/WZR and is therefore free. The exception to this is
6595 if we have (set (reg) (const0_rtx)) in which case we must cost
6596 the move. However, we can catch that when we cost the SET, so
6597 we don't need to consider that here. */
6600 else
6601 {
6602 /* To an approximation, building any other constant is
6603 proportionally expensive to the number of instructions
6604 required to build that constant. This is true whether we
6605 are compiling for SPEED or otherwise. */
6608 }
6613 {
6614 /* mov[df,sf]_aarch64. */
6616 /* FMOV (scalar immediate). */
6619 {
6620 /* This will be a load from memory. */
6623 else
6625 }
6626 else
6627 /* Otherwise this is +0.0. We get this using MOVI d0, #0
6628 or MOV v0.s[0], wzr - neither of which are modeled by the
6629 cost tables. Just use the default cost. */
6630 {
6631 }
6632 }
6638 {
6639 /* For loads we want the base cost of a load, plus an
6640 approximation for the additional cost of the addressing
6641 mode. */
6655 }
6663 {
6665 {
6666 /* FNEG. */
6668 }
6670 }
6673 {
6676 {
6677 /* CSETM. */
6680 }
6682 /* Cost this as SUB wzr, X. */
6686 }
6689 {
6690 /* Support (neg(fma...)) as a single instruction only if
6691 sign of zeros is unimportant. This matches the decision
6692 making in aarch64.md. */
6694 {
6695 /* FNMADD. */
6698 }
6700 {
6701 /* FNMUL. */
6704 }
6706 /* FNEG. */
6709 }
6716 {
6719 else
6721 }
6731 {
6735 }
6738 {
6739 /* TODO: A write to the CC flags possibly costs extra, this
6740 needs encoding in the cost tables. */
6743 /* ANDS. */
6745 {
6748 }
6751 {
6752 /* ADDS (and CMN alias). */
6755 }
6758 {
6759 /* SUBS. */
6762 }
6767 {
6768 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
6769 Handle it here directly rather than going to cost_logic
6770 since we know the immediate generated for the TST is valid
6771 so we can avoid creating an intermediate rtx for it only
6772 for costing purposes. */
6779 }
6782 {
6783 /* CMN. */
6790 }
6792 /* CMP.
6794 Compare can freely swap the order of operands, and
6795 canonicalization puts the more complex operation first.
6796 But the integer MINUS logic expects the shift/extend
6797 operation in op1. */
6800 {
6803 }
6805 }
6808 {
6809 /* FCMP. */
6814 {
6816 /* FCMP supports constant 0.0 for no extra cost. */
6818 }
6820 }
6823 {
6824 /* Vector compare. */
6829 {
6830 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6831 cost. */
6833 }
6835 }
6839 {
6843 cost_minus:
6846 /* Detect valid immediates. */
6852 {
6854 /* SUB(S) (immediate). */
6857 }
6859 /* Look for SUB (extended register). */
6861 {
6869 }
6873 /* Cost this as an FMA-alike operation. */
6877 {
6880 speed);
6882 }
6887 {
6889 {
6890 /* Vector SUB. */
6892 }
6894 {
6895 /* SUB(S). */
6897 }
6899 {
6900 /* FSUB. */
6902 }
6903 }
6905 }
6908 {
6909 rtx new_op0;
6914 cost_plus:
6917 {
6918 /* CSINC. */
6922 }
6927 {
6931 /* ADD (immediate). */
6934 }
6938 /* Look for ADD (extended register). */
6940 {
6948 }
6950 /* Strip any extend, leave shifts behind as we will
6951 cost them through mult_cost. */
6956 {
6958 speed);
6960 }
6965 {
6967 {
6968 /* Vector ADD. */
6970 }
6972 {
6973 /* ADD. */
6975 }
6977 {
6978 /* FADD. */
6980 }
6981 }
6983 }
6989 {
6992 else
6994 }
6999 {
7003 {
7006 else
7008 }
7010 }
7013 {
7020 }
7021 /* Fall through. */
7024 cost_logic:
7029 {
7033 }
7041 {
7042 /* This is a UBFM/SBFM. */
7047 }
7050 {
7052 {
7053 /* We have a mask + shift version of a UBFIZ
7054 i.e. the *andim_ashift<mode>_bfiz pattern. */
7058 {
7065 }
7067 {
7068 /* We possibly get the immediate for free, this is not
7069 modelled. */
7075 }
7076 }
7077 else
7078 {
7081 /* Handle ORN, EON, or BIC. */
7087 /* If we had a shift on op0 then this is a logical-shift-
7088 by-register/immediate operation. Otherwise, this is just
7089 a logical operation. */
7091 {
7093 {
7094 /* Shift by immediate. */
7097 else
7099 }
7100 else
7102 }
7104 /* In both cases we want to cost both operands. */
7109 }
7110 }
7118 {
7119 /* Vector NOT. */
7122 }
7124 /* MVN-shifted-reg. */
7126 {
7133 }
7134 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
7135 Handle the second form here taking care that 'a' in the above can
7136 be a shift. */
7138 {
7147 {
7150 else
7152 }
7155 }
7156 /* MVN. */
7165 /* If a value is written in SI mode, then zero extended to DI
7166 mode, the operation will in general be free as a write to
7167 a 'w' register implicitly zeroes the upper bits of an 'x'
7168 register. However, if this is
7170 (set (reg) (zero_extend (reg)))
7172 we must cost the explicit register move. */
7176 {
7179 /* If OP_COST is non-zero, then the cost of the zero extend
7180 is effectively the cost of the inner operation. Otherwise
7181 we have a MOV instruction and we take the cost from the MOV
7182 itself. This is true independently of whether we are
7183 optimizing for space or time. */
7188 }
7190 {
7191 /* All loads can zero extend to any size for free. */
7194 }
7198 {
7203 }
7206 {
7208 {
7209 /* UMOV. */
7211 }
7212 else
7213 {
7214 /* We generate an AND instead of UXTB/UXTH. */
7216 }
7217 }
7222 {
7223 /* LDRSH. */
7225 {
7232 }
7234 }
7238 {
7243 }
7246 {
7249 else
7251 }
7259 {
7261 {
7263 {
7264 /* Vector shift (immediate). */
7266 }
7267 else
7268 {
7269 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
7270 aliases. */
7272 }
7273 }
7275 /* We can incorporate zero/sign extend for free. */
7282 }
7283 else
7284 {
7286 {
7288 {
7289 /* Vector shift (register). */
7291 }
7292 else
7293 {
7294 /* LSLV. */
7296 }
7297 }
7299 }
7309 {
7310 /* ASR (immediate) and friends. */
7312 {
7315 else
7317 }
7321 }
7322 else
7323 {
7325 /* ASR (register) and friends. */
7327 {
7330 else
7332 }
7334 }
7340 {
7341 /* LDR. */
7344 }
7347 {
7348 /* ADRP, followed by ADD. */
7352 }
7355 {
7356 /* ADR. */
7359 }
7362 {
7363 /* One extra load instruction, after accessing the GOT. */
7367 }
7372 /* ADRP/ADD (immediate). */
7379 /* UBFX/SBFX. */
7381 {
7384 else
7386 }
7388 /* We can trust that the immediates used will be correct (there
7389 are no by-register forms), so we need only cost op0. */
7395 /* aarch64_rtx_mult_cost always handles recursion to its
7396 operands. */
7400 /* We can expand signed mod by power of 2 using a NEGS, two parallel
7401 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
7402 an unconditional negate. This case should only ever be reached through
7403 the set_smod_pow2_cheap check in expmed.c. */
7407 {
7408 /* We expand to 4 instructions. Reset the baseline. */
7416 }
7418 /* Fall-through. */
7421 {
7433 }
7440 {
7444 /* There is no integer SQRT, so only DIV and UDIV can get
7445 here. */
7447 else
7449 }
7475 {
7478 else
7480 }
7482 /* FMSUB, FNMADD, and FNMSUB are free. */
7489 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
7490 and the by-element operand as operand 0. */
7494 /* Catch vector-by-element operations. The by-element operand can
7495 either be (vec_duplicate (vec_select (x))) or just
7496 (vec_select (x)), depending on whether we are multiplying by
7497 a vector or a scalar.
7499 Canonicalization is not very good in these cases, FMA4 will put the
7500 by-element operand as operand 0, FNMA4 will have it as operand 1. */
7511 /* If the remaining parameters are not registers,
7512 get the cost to put them into registers. */
7526 {
7528 {
7529 /*Vector truncate. */
7531 }
7532 else
7534 }
7539 {
7541 {
7542 /*Vector conversion. */
7544 }
7545 else
7547 }
7553 /* Strip the rounding part. They will all be implemented
7554 by the fcvt* family of instructions anyway. */
7556 {
7565 }
7568 {
7571 else
7573 }
7575 /* We can combine fmul by a power of 2 followed by a fcvt into a single
7576 fixed-point fcvt. */
7581 {
7585 }
7592 {
7593 /* ABS (vector). */
7596 }
7598 {
7601 /* FABD, which is analogous to FADD. */
7603 {
7610 }
7611 /* Simple FABS is analogous to FNEG. */
7614 }
7615 else
7616 {
7617 /* Integer ABS will either be split to
7618 two arithmetic instructions, or will be an ABS
7619 (scalar), which we don't model. */
7623 }
7629 {
7632 else
7633 {
7634 /* FMAXNM/FMINNM/FMAX/FMIN.
7635 TODO: This may not be accurate for all implementations, but
7636 we do not model this in the cost tables. */
7638 }
7639 }
7643 /* The floating point round to integer frint* instructions. */
7645 {
7650 }
7653 {
7658 }
7663 /* Decompose <su>muldi3_highpart. */
7665 mode == DImode
7666 /* (lshiftrt:TI */
7669 /* (mult:TI */
7671 /* (ANY_EXTEND:TI (reg:DI))
7672 (ANY_EXTEND:TI (reg:DI))) */
7679 /* (const_int 64) */
7682 {
7683 /* UMULH/SMULH. */
7691 }
7693 /* Fall through. */
7696 }
7704 }
7706 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
7707 calculated for X. This cost is stored in *COST. Returns true
7708 if the total cost of X was calculated. */
7709 static bool
7712 {
7717 {
7722 }
7725 }
7727 static int
7730 {
7736 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
7743 /* Moving between GPR and stack cost is the same as GP2GP. */
7748 /* To/From the stack register, we move via the gprs. */
7754 {
7755 /* 128-bit operations on general registers require 2 instructions. */
7763 /* When AdvSIMD instructions are disabled it is not possible to move
7764 a 128-bit value directly between Q registers. This is handled in
7765 secondary reload. A general register is used as a scratch to move
7766 the upper DI value and the lower DI value is moved directly,
7767 hence the cost is the sum of three moves. */
7772 }
7782 }
7784 static int
7786 reg_class_t rclass ATTRIBUTE_UNUSED,
7788 {
7790 }
7792 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
7793 to optimize 1.0/sqrt. */
7795 static bool
7797 {
7799 && flag_unsafe_math_optimizations
7803 }
7805 /* Function to decide when to use the approximate reciprocal square root
7806 builtin. */
7808 static tree
7810 {
7816 }
7820 /* Select reciprocal square root initial estimate insn depending on machine
7821 mode. */
7823 static rsqrte_type
7825 {
7827 {
7834 }
7835 }
7839 /* Select reciprocal square root series step insn depending on machine mode. */
7841 static rsqrts_type
7843 {
7845 {
7852 }
7853 }
7855 /* Emit instruction sequence to compute either the approximate square root
7856 or its approximate reciprocal, depending on the flag RECP, and return
7857 whether the sequence was emitted or not. */
7859 bool
7861 {
7867 machine_mode mmsk = mode_for_vector
7871 && (flag_mlow_precision_sqrt
7875 && (flag_mrecip_low_precision_sqrt
7880 || flag_trapping_math
7881 || !flag_unsafe_math_optimizations
7888 /* When calculating the approximate square root, compare the argument with
7889 0.0 and create a mask. */
7893 /* Estimate the approximate reciprocal square root. */
7897 /* Iterate over the series twice for SF and thrice for DF. */
7900 /* Optionally iterate over the series once less for faster performance
7901 while sacrificing the accuracy. */
7904 iterations--;
7906 /* Iterate over the series to calculate the approximate reciprocal square
7907 root. */
7910 {
7918 }
7921 {
7922 /* Qualify the approximate reciprocal square root when the argument is
7923 0.0 by squashing the intermediary result to 0.0. */
7929 /* Calculate the approximate square root. */
7931 }
7933 /* Finalize the approximation. */
7937 }
7941 /* Select reciprocal initial estimate insn depending on machine mode. */
7943 static recpe_type
7945 {
7947 {
7954 }
7955 }
7959 /* Select reciprocal series step insn depending on machine mode. */
7961 static recps_type
7963 {
7965 {
7972 }
7973 }
7975 /* Emit the instruction sequence to compute the approximation for the division
7976 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
7978 bool
7980 {
7991 || flag_trapping_math
7992 || !flag_unsafe_math_optimizations
7997 /* Estimate the approximate reciprocal. */
8001 /* Iterate over the series twice for SF and thrice for DF. */
8004 /* Optionally iterate over the series once less for faster performance,
8005 while sacrificing the accuracy. */
8007 iterations--;
8009 /* Iterate over the series to calculate the approximate reciprocal. */
8012 {
8017 }
8020 {
8021 /* As the approximate reciprocal of DEN is already calculated, only
8022 calculate the approximate division when NUM is not 1.0. */
8025 }
8027 /* Finalize the approximation. */
8030 }
8032 /* Return the number of instructions that can be issued per cycle. */
8033 static int
8035 {
8037 }
8039 static int
8041 {
8045 }
8048 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
8049 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
8050 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
8052 static int
8055 {
8057 }
8060 /* Vectorizer cost model target hooks. */
8062 /* Implement targetm.vectorize.builtin_vectorization_cost. */
8063 static int
8065 tree vectype,
8067 {
8071 {
8120 }
8121 }
8123 /* Implement targetm.vectorize.add_stmt_cost. */
8124 static unsigned
8128 {
8133 {
8138 /* Statements in an inner loop relative to the loop being
8139 vectorized are weighted more heavily. The value here is
8140 arbitrary and could potentially be improved with analysis. */
8146 }
8149 }
8153 /* Parse the TO_PARSE string and put the architecture struct that it
8154 selects into RES and the architectural features into ISA_FLAGS.
8155 Return an aarch64_parse_opt_result describing the parse result.
8156 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
8158 static enum aarch64_parse_opt_result
8161 {
8173 else
8180 /* Loop through the list of supported ARCHes to find a match. */
8182 {
8184 {
8188 {
8189 /* TO_PARSE string contains at least one extension. */
8190 enum aarch64_parse_opt_result ext_res
8195 }
8196 /* Extension parsing was successful. Confirm the result
8197 arch and ISA flags. */
8201 }
8202 }
8204 /* ARCH name not found in list. */
8206 }
8208 /* Parse the TO_PARSE string and put the result tuning in RES and the
8209 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
8210 describing the parse result. If there is an error parsing, RES and
8211 ISA_FLAGS are left unchanged. */
8213 static enum aarch64_parse_opt_result
8216 {
8228 else
8235 /* Loop through the list of supported CPUs to find a match. */
8237 {
8239 {
8244 {
8245 /* TO_PARSE string contains at least one extension. */
8246 enum aarch64_parse_opt_result ext_res
8251 }
8252 /* Extension parsing was successfull. Confirm the result
8253 cpu and ISA flags. */
8257 }
8258 }
8260 /* CPU name not found in list. */
8262 }
8264 /* Parse the TO_PARSE string and put the cpu it selects into RES.
8265 Return an aarch64_parse_opt_result describing the parse result.
8266 If the parsing fails the RES does not change. */
8268 static enum aarch64_parse_opt_result
8270 {
8276 /* Loop through the list of supported CPUs to find a match. */
8278 {
8280 {
8283 }
8284 }
8286 /* CPU name not found in list. */
8288 }
8290 /* Parse TOKEN, which has length LENGTH to see if it is an option
8291 described in FLAG. If it is, return the index bit for that fusion type.
8292 If not, error (printing OPTION_NAME) and return zero. */
8294 static unsigned int
8299 {
8301 {
8305 }
8309 }
8311 /* Parse OPTION which is a comma-separated list of flags to enable.
8312 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
8313 default state we inherit from the CPU tuning structures. OPTION_NAME
8314 gives the top-level option we are parsing in the -moverride string,
8315 for use in error messages. */
8317 static unsigned int
8322 {
8329 {
8332 token_length,
8333 flags,
8334 option_name);
8335 /* If we find "none" (or, for simplicity's sake, an error) anywhere
8336 in the token stream, reset the supported operations. So:
8338 adrp+add.cmp+branch.none.adrp+add
8340 would have the result of turning on only adrp+add fusion. */
8346 }
8348 /* We ended with a comma, print something. */
8350 {
8353 }
8355 /* We still have one more token to parse. */
8358 token_length,
8359 flags,
8360 option_name);
8366 }
8368 /* Support for overriding instruction fusion. */
8370 static void
8373 {
8375 aarch64_fusible_pairs,
8378 }
8380 /* Support for overriding other tuning flags. */
8382 static void
8385 {
8386 tune->extra_tuning_flags
8388 aarch64_tuning_flags,
8391 }
8393 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
8394 we understand. If it is, extract the option string and handoff to
8395 the appropriate function. */
8397 void
8401 {
8407 {
8410 }
8412 /* Get the length of the option name. */
8414 /* Skip the '=' to get to the option string. */
8415 option_part++;
8418 {
8420 {
8423 }
8424 }
8428 }
8430 /* A checking mechanism for the implementation of the tls size. */
8432 static void
8434 {
8439 {
8441 /* Both the default and maximum TLS size allowed under tiny is 1M which
8442 needs two instructions to address, so we clamp the size to 24. */
8447 /* The maximum TLS size allowed under small is 4G. */
8452 /* The maximum TLS size allowed under large is 16E.
8453 FIXME: 16E should be 64bit, we only support 48bit offset now. */
8459 }
8462 }
8464 /* Parse STRING looking for options in the format:
8465 string :: option:string
8466 option :: name=substring
8467 name :: {a-z}
8468 substring :: defined by option. */
8470 static void
8473 {
8484 {
8486 /* Make this substring look like a string. */
8490 }
8492 /* One last option to parse. */
8495 }
8498 static void
8500 {
8501 /* The logic here is that if we are disabling all frame pointer generation
8502 then we do not need to disable leaf frame pointer generation as a
8503 separate operation. But if we are *only* disabling leaf frame pointer
8504 generation then we set flag_omit_frame_pointer to true, but in
8505 aarch64_frame_pointer_required we return false only for leaf functions.
8507 PR 70044: We have to be careful about being called multiple times for the
8508 same function. Once we have decided to set flag_omit_frame_pointer just
8509 so that we can omit leaf frame pointers, we must then not interpret a
8510 second call as meaning that all frame pointer generation should be
8511 omitted. We do this by setting flag_omit_frame_pointer to a special,
8512 non-zero value. */
8521 /* If not optimizing for size, set the default
8522 alignment to what the target wants. */
8524 {
8531 }
8533 /* We default to no pc-relative literal loads. */
8537 /* If -mpc-relative-literal-loads is set on the command line, this
8538 implies that the user asked for PC relative literal loads. */
8542 /* This is PR70113. When building the Linux kernel with
8543 CONFIG_ARM64_ERRATUM_843419, support for relocations
8544 R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADR_PREL_PG_HI21_NC is
8545 removed from the kernel to avoid loading objects with possibly
8546 offending sequences. Without -mpc-relative-literal-loads we would
8547 generate such relocations, preventing the kernel build from
8548 succeeding. */
8553 /* In the tiny memory model it makes no sense to disallow PC relative
8554 literal pool loads. */
8559 /* When enabling the lower precision Newton series for the square root, also
8560 enable it for the reciprocal square root, since the latter is an
8561 intermediary step for the former. */
8564 }
8566 /* 'Unpack' up the internal tuning structs and update the options
8567 in OPTS. The caller must have set up selected_tune and selected_arch
8568 as all the other target-specific codegen decisions are
8569 derived from them. */
8571 void
8573 {
8576 /* Make a copy of the tuning parameters attached to the core, which
8577 we may later overwrite. */
8585 /* This target defaults to strict volatile bitfields. */
8594 {
8606 }
8608 /* We don't mind passing in global_options_set here as we don't use
8609 the *options_set structs anyway. */
8611 queue_depth,
8615 /* Set the L1 cache line size. */
8623 }
8625 /* Print a hint with a suggestion for a core or architecture name that
8626 most closely resembles what the user passed in STR. ARCH is true if
8627 the user is asking for an architecture name. ARCH is false if the user
8628 is asking for a core name. */
8630 static void
8632 {
8643 }
8645 /* Print a hint with a suggestion for a core name that most closely resembles
8646 what the user passed in STR. */
8650 {
8652 }
8654 /* Print a hint with a suggestion for an architecture name that most closely
8655 resembles what the user passed in STR. */
8659 {
8661 }
8663 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
8664 specified in STR and throw errors if appropriate. Put the results if
8665 they are valid in RES and ISA_FLAGS. Return whether the option is
8666 valid. */
8668 static bool
8671 {
8672 enum aarch64_parse_opt_result parse_res
8679 {
8692 }
8695 }
8697 /* Validate a command-line -march option. Parse the arch and extensions
8698 (if any) specified in STR and throw errors if appropriate. Put the
8699 results, if they are valid, in RES and ISA_FLAGS. Return whether the
8700 option is valid. */
8702 static bool
8705 {
8706 enum aarch64_parse_opt_result parse_res
8713 {
8726 }
8729 }
8731 /* Validate a command-line -mtune option. Parse the cpu
8732 specified in STR and throw errors if appropriate. Put the
8733 result, if it is valid, in RES. Return whether the option is
8734 valid. */
8736 static bool
8738 {
8739 enum aarch64_parse_opt_result parse_res
8746 {
8756 }
8758 }
8760 /* Return the CPU corresponding to the enum CPU.
8761 If it doesn't specify a cpu, return the default. */
8765 {
8769 /* The & 0x3f is to extract the bottom 6 bits that encode the
8770 default cpu as selected by the --with-cpu GCC configure option
8771 in config.gcc.
8772 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
8773 flags mechanism should be reworked to make it more sane. */
8775 }
8777 /* Return the architecture corresponding to the enum ARCH.
8778 If it doesn't specify a valid architecture, return the default. */
8782 {
8789 }
8791 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
8792 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
8793 tuning structs. In particular it must set selected_tune and
8794 aarch64_isa_flags that define the available ISA features and tuning
8795 decisions. It must also set selected_arch as this will be used to
8796 output the .arch asm tags for each function. */
8798 static void
8800 {
8813 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
8814 If either of -march or -mtune is given, they override their
8815 respective component of -mcpu. */
8827 /* If the user did not specify a processor, choose the default
8828 one for them. This will be the CPU set during configuration using
8829 --with-cpu, otherwise it is "generic". */
8831 {
8833 {
8837 }
8838 else
8839 {
8840 /* Get default configure-time CPU. */
8843 }
8847 }
8848 /* If both -mcpu and -march are specified check that they are architecturally
8849 compatible, warn if they're not and prefer the -march ISA flags. */
8851 {
8853 {
8857 }
8862 }
8863 else
8864 {
8865 /* -mcpu but no -march. */
8872 }
8874 /* Set the arch as well as we will need it when outputing
8875 the .arch directive in assembly. */
8877 {
8880 }
8885 #ifndef HAVE_AS_MABI_OPTION
8886 /* The compiler may have been configured with 2.23.* binutils, which does
8887 not have support for ILP32. */
8890 #endif
8892 /* Make sure we properly set up the explicit options. */
8903 /* Save these options as the default ones in case we push and pop them later
8904 while processing functions with potential target attributes. */
8905 target_option_default_node = target_option_current_node
8907 }
8909 /* Implement targetm.override_options_after_change. */
8911 static void
8913 {
8915 }
8919 {
8923 }
8925 void
8927 {
8929 }
8931 /* A checking mechanism for the implementation of the various code models. */
8932 static void
8934 {
8936 {
8938 {
8943 #ifdef HAVE_AS_SMALL_PIC_RELOCS
8945 ? AARCH64_CMODEL_SMALL_PIC
8947 #else
8949 #endif
8957 }
8958 }
8959 else
8961 }
8963 /* Implement TARGET_OPTION_SAVE. */
8965 static void
8967 {
8969 }
8971 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
8972 using the information saved in PTR. */
8974 static void
8976 {
8984 }
8986 /* Implement TARGET_OPTION_PRINT. */
8988 static void
8990 {
9001 }
9005 void
9007 {
9009 }
9011 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9012 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
9013 make sure optab availability predicates are recomputed when necessary. */
9015 void
9017 {
9022 else
9024 }
9026 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
9027 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
9028 of the function, if such exists. This function may be called multiple
9029 times on a single function so use aarch64_previous_fndecl to avoid
9030 setting up identical state. */
9032 static void
9034 {
9038 tree old_tree = (aarch64_previous_fndecl
9044 /* If current function has no attributes but the previous one did,
9045 use the default node. */
9049 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
9050 the default have been handled by aarch64_save_restore_target_globals from
9051 aarch64_pragma_target_parse. */
9057 /* First set the target options. */
9061 }
9063 /* Enum describing the various ways we can handle attributes.
9064 In many cases we can reuse the generic option handling machinery. */
9066 enum aarch64_attr_opt_type
9067 {
9071 aarch64_attr_custom /* Attribute requires a custom handling function. */
9072 };
9074 /* All the information needed to handle a target attribute.
9075 NAME is the name of the attribute.
9076 ATTR_TYPE specifies the type of behavior of the attribute as described
9077 in the definition of enum aarch64_attr_opt_type.
9078 ALLOW_NEG is true if the attribute supports a "no-" form.
9079 HANDLER is the function that takes the attribute string and whether
9080 it is a pragma or attribute and handles the option. It is needed only
9081 when the ATTR_TYPE is aarch64_attr_custom.
9082 OPT_NUM is the enum specifying the option that the attribute modifies.
9083 This is needed for attributes that mirror the behavior of a command-line
9084 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
9085 aarch64_attr_enum. */
9087 struct aarch64_attribute_info
9088 {
9094 };
9096 /* Handle the ARCH_STR argument to the arch= target attribute.
9097 PRAGMA_OR_ATTR is used in potential error messages. */
9099 static bool
9101 {
9103 enum aarch64_parse_opt_result parse_res
9107 {
9112 }
9115 {
9129 }
9132 }
9134 /* Handle the argument CPU_STR to the cpu= target attribute.
9135 PRAGMA_OR_ATTR is used in potential error messages. */
9137 static bool
9139 {
9141 enum aarch64_parse_opt_result parse_res
9145 {
9153 }
9156 {
9170 }
9173 }
9175 /* Handle the argument STR to the tune= target attribute.
9176 PRAGMA_OR_ATTR is used in potential error messages. */
9178 static bool
9180 {
9182 enum aarch64_parse_opt_result parse_res
9186 {
9191 }
9194 {
9201 }
9204 }
9206 /* Parse an architecture extensions target attribute string specified in STR.
9207 For example "+fp+nosimd". Show any errors if needed. Return TRUE
9208 if successful. Update aarch64_isa_flags to reflect the ISA features
9209 modified.
9210 PRAGMA_OR_ATTR is used in potential error messages. */
9212 static bool
9214 {
9218 /* We allow "+nothing" in the beginning to clear out all architectural
9219 features if the user wants to handpick specific features. */
9221 {
9224 }
9229 {
9232 }
9235 {
9248 }
9251 }
9253 /* The target attributes that we support. On top of these we also support just
9254 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
9255 handled explicitly in aarch64_process_one_target_attr. */
9258 {
9260 OPT_mgeneral_regs_only },
9262 OPT_mfix_cortex_a53_835769 },
9264 OPT_mfix_cortex_a53_843419 },
9268 OPT_momit_leaf_frame_pointer },
9271 OPT_march_ },
9274 OPT_mtune_ },
9276 };
9278 /* Parse ARG_STR which contains the definition of one target attribute.
9279 Show appropriate errors if any or return true if the attribute is valid.
9280 PRAGMA_OR_ATTR holds the string to use in error messages about whether
9281 we're processing a target attribute or pragma. */
9283 static bool
9285 {
9291 {
9294 }
9299 /* Skip leading whitespace. */
9301 str_to_check++;
9303 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
9304 It is easier to detect and handle it explicitly here rather than going
9305 through the machinery for the rest of the target attributes in this
9306 function. */
9311 {
9314 }
9317 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
9318 and point ARG to "foo". */
9320 {
9322 arg++;
9323 }
9327 {
9328 /* If the names don't match up, or the user has given an argument
9329 to an attribute that doesn't accept one, or didn't give an argument
9330 to an attribute that expects one, fail to match. */
9339 {
9343 }
9345 /* If the name matches but the attribute does not allow "no-" versions
9346 then we can't match. */
9348 {
9352 }
9355 {
9356 /* Has a custom handler registered.
9357 For example, cpu=, arch=, tune=. */
9364 /* Either set or unset a boolean option. */
9366 {
9374 }
9375 /* Set or unset a bit in the target_flags. aarch64_handle_option
9376 should know what mask to apply given the option number. */
9378 {
9380 /* We only need to specify the option number.
9381 aarch64_handle_option will know which mask to apply. */
9387 }
9388 /* Use the option setting machinery to set an option to an enum. */
9390 {
9397 {
9400 global_dc);
9401 }
9402 else
9403 {
9406 }
9408 }
9411 }
9412 }
9414 /* If we reached here we either have found an attribute and validated
9415 it or didn't match any. If we matched an attribute but its arguments
9416 were malformed we will have returned false already. */
9418 }
9420 /* Count how many times the character C appears in
9421 NULL-terminated string STR. */
9423 static unsigned int
9425 {
9428 {
9430 res++;
9432 str++;
9433 }
9436 }
9438 /* Parse the tree in ARGS that contains the target attribute information
9439 and update the global target options space. PRAGMA_OR_ATTR is a string
9440 to be used in error messages, specifying whether this is processing
9441 a target attribute or a target pragma. */
9443 bool
9445 {
9447 {
9448 do
9449 {
9452 {
9455 }
9460 }
9461 /* We expect to find a string to parse. */
9469 {
9472 }
9474 /* Used to catch empty spaces between commas i.e.
9475 attribute ((target ("attr1,,attr2"))). */
9478 /* Handle multiple target attributes separated by ','. */
9483 {
9484 num_attrs++;
9486 {
9489 }
9492 }
9495 {
9499 }
9502 }
9504 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
9505 process attribute ((target ("..."))). */
9507 static bool
9509 {
9512 tree old_optimize;
9516 /* If what we're processing is the current pragma string then the
9517 target option node is already stored in target_option_current_node
9518 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
9519 having to re-parse the string. This is especially useful to keep
9520 arm_neon.h compile times down since that header contains a lot
9521 of intrinsics enclosed in pragmas. */
9523 {
9526 }
9532 /* If the function changed the optimization levels as well as setting
9533 target options, start with the optimizations specified. */
9538 /* Save the current target options to restore at the end. */
9541 /* If fndecl already has some target attributes applied to it, unpack
9542 them so that we add this attribute on top of them, rather than
9543 overwriting them. */
9545 {
9551 }
9552 else
9559 /* Set up any additional state. */
9561 {
9563 /* Initialize SIMD builtins if we haven't already.
9564 Set current_target_pragma to NULL for the duration so that
9565 the builtin initialization code doesn't try to tag the functions
9566 being built with the attributes specified by any current pragma, thus
9567 going into an infinite recursion. */
9569 {
9574 }
9576 }
9577 else
9583 {
9588 }
9596 }
9598 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
9599 tri-bool options (yes, no, don't care) and the default value is
9600 DEF, determine whether to reject inlining. */
9602 static bool
9605 {
9606 /* If the callee doesn't care, always allow inlining. */
9610 /* If the caller doesn't care, always allow inlining. */
9614 /* Otherwise, allow inlining if either the callee and caller values
9615 agree, or if the callee is using the default value. */
9617 }
9619 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
9620 to inline CALLEE into CALLER based on target-specific info.
9621 Make sure that the caller and callee have compatible architectural
9622 features. Then go through the other possible target attributes
9623 and see if they can block inlining. Try not to reject always_inline
9624 callees unless they are incompatible architecturally. */
9626 static bool
9628 {
9632 /* If callee has no option attributes, then it is ok to inline. */
9643 /* Callee's ISA flags should be a subset of the caller's. */
9648 /* Allow non-strict aligned functions inlining into strict
9649 aligned ones. */
9659 /* If the architectural features match up and the callee is always_inline
9660 then the other attributes don't matter. */
9672 /* Honour explicit requests to workaround errata. */
9685 /* If the user explicitly specified -momit-leaf-frame-pointer for the
9686 caller and calle and they don't match up, reject inlining. */
9693 /* If the callee has specific tuning overrides, respect them. */
9698 /* If the user specified tuning override strings for the
9699 caller and callee and they don't match up, reject inlining.
9700 We just do a string compare here, we don't analyze the meaning
9701 of the string, as it would be too costly for little gain. */
9709 }
9711 /* Return true if SYMBOL_REF X binds locally. */
9713 static bool
9715 {
9719 }
9721 /* Return true if SYMBOL_REF X is thread local */
9722 static bool
9724 {
9732 }
9734 /* Classify a TLS symbol into one of the TLS kinds. */
9735 enum aarch64_symbol_type
9737 {
9741 {
9748 {
9754 }
9765 else
9774 }
9775 }
9777 /* Return the method that should be used to access SYMBOL_REF or
9778 LABEL_REF X. */
9780 enum aarch64_symbol_type
9782 {
9784 {
9786 {
9801 }
9802 }
9805 {
9810 {
9812 /* When we retrieve symbol + offset address, we have to make sure
9813 the offset does not cause overflow of the final address. But
9814 we have no way of knowing the address of symbol at compile time
9815 so we can't accurately say if the distance between the PC and
9816 symbol + offset is outside the addressible range of +/-1M in the
9817 TINY code model. So we rely on images not being greater than
9818 1M and cap the offset at 1M and anything beyond 1M will have to
9819 be loaded using an alternative mechanism. Furthermore if the
9820 symbol is a weak reference to something that isn't known to
9821 resolve to a symbol in this module, then force to memory. */
9829 /* Same reasoning as the tiny code model, but the offset cap here is
9830 4G. */
9851 /* This is alright even in PIC code as the constant
9852 pool reference is always PC relative and within
9853 the same translation unit. */
9856 else
9861 }
9862 }
9864 /* By default push everything into the constant pool. */
9866 }
9868 bool
9870 {
9872 }
9874 bool
9876 {
9884 }
9886 /* Return true if X holds either a quarter-precision or
9887 floating-point +0.0 constant. */
9888 static bool
9890 {
9897 /* We only handle moving 0.0 to a TFmode register. */
9902 }
9904 static bool
9906 {
9907 /* Do not allow vector struct mode constants. We could support
9908 0 and -1 easily, but they need support in aarch64-simd.md. */
9912 /* This could probably go away because
9913 we now decompose CONST_INTs according to expand_mov_immediate. */
9924 }
9926 rtx
9928 {
9934 /* Can return in any reg. */
9937 }
9939 /* On AAPCS systems, this is the "struct __va_list". */
9942 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
9943 Return the type to use as __builtin_va_list.
9945 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
9947 struct __va_list
9948 {
9949 void *__stack;
9950 void *__gr_top;
9951 void *__vr_top;
9952 int __gr_offs;
9953 int __vr_offs;
9954 }; */
9956 static tree
9958 {
9959 tree va_list_name;
9962 /* Create the type. */
9964 /* Give it the required name. */
9966 TYPE_DECL,
9968 va_list_type);
9973 /* Create the fields. */
9976 ptr_type_node);
9979 ptr_type_node);
9982 ptr_type_node);
9985 integer_type_node);
9988 integer_type_node);
9990 /* Tell tree-stdarg pass about our internal offset fields.
9991 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
9992 purpose to identify whether the code is updating va_list internal
9993 offset fields through irregular way. */
10015 /* Compute its layout. */
10019 }
10021 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
10022 static void
10024 {
10028 tree t;
10042 {
10045 }
10054 NULL_TREE);
10056 NULL_TREE);
10058 NULL_TREE);
10060 NULL_TREE);
10062 NULL_TREE);
10064 /* Emit code to initialize STACK, which points to the next varargs stack
10065 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
10066 by named arguments. STACK is 8-byte aligned. */
10073 /* Emit code to initialize GRTOP, the top of the GR save area.
10074 virtual_incoming_args_rtx should have been 16 byte aligned. */
10079 /* Emit code to initialize VRTOP, the top of the VR save area.
10080 This address is gr_save_area_bytes below GRTOP, rounded
10081 down to the next 16-byte boundary. */
10091 /* Emit code to initialize GROFF, the offset from GRTOP of the
10092 next GPR argument. */
10097 /* Likewise emit code to initialize VROFF, the offset from FTOP
10098 of the next VR argument. */
10102 }
10104 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
10106 static tree
10109 {
10110 tree addr;
10116 machine_mode mode;
10143 type,
10147 {
10148 /* TYPE passed in fp/simd registers. */
10160 {
10163 }
10166 {
10168 }
10169 }
10170 else
10171 {
10172 /* TYPE passed in general registers. */
10185 {
10187 }
10188 }
10190 /* Get a local temporary for the field value. */
10193 /* Emit code to branch if off >= 0. */
10199 {
10200 /* Emit: offs = (offs + 15) & -16. */
10206 }
10207 else
10210 /* Update ap.__[g|v]r_offs */
10215 /* String up. */
10219 /* [cond2] if (ap.__[g|v]r_offs > 0) */
10224 /* String up: make sure the assignment happens before the use. */
10228 /* Prepare the trees handling the argument that is passed on the stack;
10229 the top level node will store in ON_STACK. */
10232 {
10233 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
10241 }
10242 else
10244 /* Advance ap.__stack */
10252 /* String up roundup and advance. */
10255 /* String up with arg */
10257 /* Big-endianness related address adjustment. */
10260 {
10264 }
10269 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
10279 {
10280 /* type ha; // treat as "struct {ftype field[n];}"
10281 ... [computing offs]
10282 for (i = 0; i <nregs; ++i, offs += 16)
10283 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
10284 return ha; */
10288 /* Declare a local variable. */
10292 /* Establish the base type. */
10294 {
10313 {
10317 }
10321 }
10323 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
10331 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
10333 {
10343 }
10347 }
10357 }
10359 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
10361 static void
10365 {
10367 CUMULATIVE_ARGS local_cum;
10371 /* The caller has advanced CUM up to, but not beyond, the last named
10372 argument. Advance a local copy of CUM past the last "real" named
10373 argument, to find out how many registers are left over. */
10377 /* Found out how many registers we need to save.
10378 Honor tree-stdvar analysis results. */
10387 {
10390 }
10393 {
10395 {
10398 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
10406 }
10408 {
10409 /* We can't use move_block_from_reg, because it will use
10410 the wrong mode, storing D regs only. */
10414 /* Set OFF to the offset from virtual_incoming_args_rtx of
10415 the first vector register. The VR save area lies below
10416 the GR one, and is aligned to 16 bytes. */
10423 {
10431 }
10432 }
10433 }
10435 /* We don't save the size into *PRETEND_SIZE because we want to avoid
10436 any complication of having crtl->args.pretend_args_size changed. */
10441 }
10443 static void
10445 {
10448 {
10450 {
10453 }
10454 }
10455 }
10457 /* Walk down the type tree of TYPE counting consecutive base elements.
10458 If *MODEP is VOIDmode, then set it to the first valid floating point
10459 type. If a non-floating point type is found, or if a floating point
10460 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
10461 otherwise return the count in the sub-tree. */
10462 static int
10464 {
10465 machine_mode mode;
10466 HOST_WIDE_INT size;
10469 {
10499 /* Use V2SImode and V4SImode as representatives of all 64-bit
10500 and 128-bit vector types. */
10503 {
10512 }
10517 /* Vector modes are considered to be opaque: two vectors are
10518 equivalent for the purposes of being homogeneous aggregates
10519 if they are the same size. */
10526 {
10530 /* Can't handle incomplete types nor sizes that are not
10531 fixed. */
10538 || !index
10549 /* There must be no padding. */
10554 }
10557 {
10560 tree field;
10562 /* Can't handle incomplete types nor sizes that are not
10563 fixed. */
10569 {
10577 }
10579 /* There must be no padding. */
10584 }
10588 {
10589 /* These aren't very interesting except in a degenerate case. */
10592 tree field;
10594 /* Can't handle incomplete types nor sizes that are not
10595 fixed. */
10601 {
10609 }
10611 /* There must be no padding. */
10616 }
10620 }
10623 }
10625 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
10626 type as described in AAPCS64 \S 4.1.2.
10628 See the comment above aarch64_composite_type_p for the notes on MODE. */
10630 static bool
10632 machine_mode mode)
10633 {
10643 }
10645 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
10646 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
10647 array types. The C99 floating-point complex types are also considered
10648 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
10649 types, which are GCC extensions and out of the scope of AAPCS64, are
10650 treated as composite types here as well.
10652 Note that MODE itself is not sufficient in determining whether a type
10653 is such a composite type or not. This is because
10654 stor-layout.c:compute_record_mode may have already changed the MODE
10655 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
10656 structure with only one field may have its MODE set to the mode of the
10657 field. Also an integer mode whose size matches the size of the
10658 RECORD_TYPE type may be used to substitute the original mode
10659 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
10660 solely relied on. */
10662 static bool
10664 machine_mode mode)
10665 {
10678 }
10680 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
10681 shall be passed or returned in simd/fp register(s) (providing these
10682 parameter passing registers are available).
10684 Upon successful return, *COUNT returns the number of needed registers,
10685 *BASE_MODE returns the mode of the individual register and when IS_HAF
10686 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
10687 floating-point aggregate or a homogeneous short-vector aggregate. */
10689 static bool
10691 const_tree type,
10695 {
10703 {
10706 }
10708 {
10712 }
10714 {
10718 {
10721 }
10722 else
10724 }
10725 else
10730 }
10732 /* Implement TARGET_STRUCT_VALUE_RTX. */
10734 static rtx
10737 {
10739 }
10741 /* Implements target hook vector_mode_supported_p. */
10742 static bool
10744 {
10756 }
10758 /* Return appropriate SIMD container
10759 for MODE within a vector of WIDTH bits. */
10760 static machine_mode
10762 {
10765 {
10768 {
10783 }
10784 else
10786 {
10797 }
10798 }
10800 }
10802 /* Return 128-bit container as the preferred SIMD mode for MODE. */
10803 static machine_mode
10805 {
10807 }
10809 /* Return the bitmask of possible vector sizes for the vectorizer
10810 to iterate over. */
10811 static unsigned int
10813 {
10815 }
10817 /* Implement TARGET_MANGLE_TYPE. */
10821 {
10822 /* The AArch64 ABI documents say that "__va_list" has to be
10823 managled as if it is in the "std" namespace. */
10827 /* Half-precision float. */
10831 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
10832 builtin types. */
10836 /* Use the default mangling. */
10838 }
10841 /* Return true if the rtx_insn contains a MEM RTX somewhere
10842 in it. */
10844 static bool
10846 {
10853 }
10855 /* Find the first rtx_insn before insn that will generate an assembly
10856 instruction. */
10860 {
10864 do
10865 {
10867 }
10871 }
10873 static bool
10875 {
10877 /* A number of these may be AArch32 only. */
10882 };
10885 {
10888 }
10891 }
10893 /* Check if there is a register dependency between a load and the insn
10894 for which we hold recog_data. */
10896 static bool
10898 {
10899 rtx load_reg;
10909 {
10915 }
10917 }
10920 /* When working around the Cortex-A53 erratum 835769,
10921 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10922 instruction and has a preceding memory instruction such that a NOP
10923 should be inserted between them. */
10925 bool
10927 {
10930 rtx body;
10943 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
10944 Restore recog state to INSN to avoid state corruption. */
10952 /* If the previous insn is a memory op and there is no dependency between
10953 it and the DImode madd, emit a NOP between them. If body is NULL then we
10954 have a complex memory operation, probably a load/store pair.
10955 Be conservative for now and emit a NOP. */
10962 }
10965 /* Implement FINAL_PRESCAN_INSN. */
10967 void
10969 {
10972 }
10975 /* Return the equivalent letter for size. */
10976 static char
10978 {
10980 {
10986 }
10987 }
10989 /* Return true iff x is a uniform vector of floating-point
10990 constants, and the constant can be represented in
10991 quarter-precision form. Note, as aarch64_float_const_representable
10992 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
10993 static bool
10995 {
10996 rtx elt;
11000 }
11002 /* Return true for valid and false for invalid. */
11003 bool
11006 {
11007 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
11008 matches = 1; \
11009 for (i = 0; i < idx; i += (STRIDE)) \
11010 if (!(TEST)) \
11011 matches = 0; \
11012 if (matches) \
11013 { \
11014 immtype = (CLASS); \
11015 elsize = (ELSIZE); \
11016 eshift = (SHIFT); \
11017 emvn = (NEG); \
11018 break; \
11019 }
11029 {
11035 {
11040 }
11043 }
11045 /* Splat vector constant out into a byte vector. */
11047 {
11048 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
11049 it must be laid out in the vector register in reverse order. */
11057 {
11060 }
11062 }
11064 /* Sanity check. */
11067 do
11068 {
11117 }
11124 {
11134 /* Un-invert bytes of recognized vector, if necessary. */
11140 {
11141 /* FIXME: Broken on 32-bit H_W_I hosts. */
11150 }
11151 else
11152 {
11156 /* Construct 'abcdefgh' because the assembler cannot handle
11157 generic constants. */
11162 }
11163 }
11166 #undef CHECK
11167 }
11169 /* Check of immediate shift constants are within range. */
11170 bool
11172 {
11176 else
11178 }
11180 /* Return true if X is a uniform vector where all elements
11181 are either the floating-point constant 0.0 or the
11182 integer constant 0. */
11183 bool
11185 {
11187 }
11190 /* Return the bitmask CONST_INT to select the bits required by a zero extract
11191 operation of width WIDTH at bit position POS. */
11193 rtx
11195 {
11199 unsigned HOST_WIDE_INT mask
11202 }
11204 bool
11206 {
11211 {
11216 }
11219 }
11221 bool
11223 {
11236 }
11238 /* Return a const_int vector of VAL. */
11239 rtx
11241 {
11252 }
11254 /* Check OP is a legal scalar immediate for the MOVI instruction. */
11256 bool
11258 {
11259 machine_mode vmode;
11265 }
11267 /* Construct and return a PARALLEL RTX vector with elements numbering the
11268 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
11269 the vector - from the perspective of the architecture. This does not
11270 line up with GCC's perspective on lane numbers, so we end up with
11271 different masks depending on our target endian-ness. The diagram
11272 below may help. We must draw the distinction when building masks
11273 which select one half of the vector. An instruction selecting
11274 architectural low-lanes for a big-endian target, must be described using
11275 a mask selecting GCC high-lanes.
11277 Big-Endian Little-Endian
11279 GCC 0 1 2 3 3 2 1 0
11280 | x | x | x | x | | x | x | x | x |
11281 Architecture 3 2 1 0 3 2 1 0
11283 Low Mask: { 2, 3 } { 0, 1 }
11284 High Mask: { 0, 1 } { 2, 3 }
11285 */
11287 rtx
11289 {
11295 rtx t1;
11300 else
11308 }
11310 /* Check OP for validity as a PARALLEL RTX vector with elements
11311 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
11312 from the perspective of the architecture. See the diagram above
11313 aarch64_simd_vect_par_cnst_half for more details. */
11315 bool
11318 {
11331 {
11338 }
11340 }
11342 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
11343 HIGH (exclusive). */
11344 void
11346 const_tree exp)
11347 {
11348 HOST_WIDE_INT lane;
11353 {
11356 else
11358 }
11359 }
11361 /* Return TRUE if OP is a valid vector addressing mode. */
11362 bool
11364 {
11367 }
11369 /* Emit a register copy from operand to operand, taking care not to
11370 early-clobber source registers in the process.
11372 COUNT is the number of components into which the copy needs to be
11373 decomposed. */
11374 void
11377 {
11387 else
11391 }
11393 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
11394 one of VSTRUCT modes: OI, CI, or XI. */
11395 int
11397 {
11399 }
11401 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
11402 alignment of a vector to 128 bits. */
11403 static HOST_WIDE_INT
11405 {
11408 }
11410 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
11411 static bool
11413 {
11417 /* We guarantee alignment for vectors up to 128-bits. */
11422 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
11424 }
11426 /* Return true if the vector misalignment factor is supported by the
11427 target. */
11428 static bool
11432 {
11434 {
11435 /* Return if movmisalign pattern is not supported for this mode. */
11440 {
11441 /* Misalignment factor is unknown at compile time but we know
11442 it's word aligned. */
11444 {
11449 }
11451 }
11452 }
11454 is_packed);
11455 }
11457 /* If VALS is a vector constant that can be loaded into a register
11458 using DUP, generate instructions to do so and return an RTX to
11459 assign to the register. Otherwise return NULL_RTX. */
11460 static rtx
11462 {
11465 rtx x;
11470 /* We can load this constant by using DUP and a constant in a
11471 single ARM register. This will be cheaper than a vector
11472 load. */
11475 }
11478 /* Generate code to load VALS, which is a PARALLEL containing only
11479 constants (for vec_init) or CONST_VECTOR, efficiently into a
11480 register. Returns an RTX to copy into the register, or NULL_RTX
11481 for a PARALLEL that can not be converted into a CONST_VECTOR. */
11482 static rtx
11484 {
11486 rtx const_dup;
11495 {
11496 /* A CONST_VECTOR must contain only CONST_INTs and
11497 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
11498 Only store valid constants in a CONST_VECTOR. */
11500 {
11503 n_const++;
11504 }
11507 }
11508 else
11513 /* Load using MOVI/MVNI. */
11516 /* Loaded using DUP. */
11519 /* Load from constant pool. We can not take advantage of single-cycle
11520 LD1 because we need a PC-relative addressing mode. */
11522 else
11523 /* A PARALLEL containing something not valid inside CONST_VECTOR.
11524 We can not construct an initializer. */
11526 }
11528 /* Expand a vector initialisation sequence, such that TARGET is
11529 initialised to contain VALS. */
11531 void
11533 {
11536 /* The number of vector elements. */
11538 /* The number of vector elements which are not constant. */
11541 /* The first element of vals. */
11545 /* Count the number of variable elements to initialise. */
11547 {
11551 else
11555 }
11557 /* No variable elements, hand off to aarch64_simd_make_constant which knows
11558 how best to handle this. */
11560 {
11563 {
11566 }
11567 }
11569 /* Splat a single non-constant element if we can. */
11571 {
11575 }
11577 /* Initialise a vector which is part-variable. We want to first try
11578 to build those lanes which are constant in the most efficient way we
11579 can. */
11581 {
11584 /* Load constant part of vector. We really don't care what goes into the
11585 parts we will overwrite, but we're more likely to be able to load the
11586 constant efficiently if it has fewer, larger, repeating parts
11587 (see aarch64_simd_valid_immediate). */
11589 {
11595 {
11596 /* Look in the copied vector, as more elements are const. */
11599 {
11602 }
11603 }
11605 }
11607 }
11609 /* Insert the variable lanes directly. */
11615 {
11621 }
11622 }
11624 static unsigned HOST_WIDE_INT
11626 {
11627 return
11628 (!SHIFT_COUNT_TRUNCATED
11631 }
11633 /* Select a format to encode pointers in exception handling data. */
11634 int
11636 {
11639 {
11645 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
11646 for everything. */
11650 /* No assumptions here. 8-byte relocs required. */
11653 }
11655 }
11657 /* The last .arch and .tune assembly strings that we printed. */
11661 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
11662 by the function fndecl. */
11664 void
11666 tree fndecl)
11667 {
11673 else
11684 /* Only update the assembler .arch string if it is distinct from the last
11685 such string we printed. */
11688 {
11691 }
11693 /* Print the cpu name we're tuning for in the comments, might be
11694 useful to readers of the generated asm. Do it only when it changes
11695 from function to function and verbose assembly is requested. */
11700 {
11704 }
11706 /* Don't forget the type directive for ELF. */
11709 }
11711 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
11713 static void
11715 {
11732 }
11734 /* Emit load exclusive. */
11736 static void
11739 {
11743 {
11750 }
11753 }
11755 /* Emit store exclusive. */
11757 static void
11760 {
11764 {
11771 }
11774 }
11776 /* Mark the previous jump instruction as unlikely. */
11778 static void
11780 {
11785 }
11787 /* Expand a compare and swap pattern. */
11789 void
11791 {
11796 gen_cas_fn gen;
11798 {
11799 gen_aarch64_compare_and_swapqi,
11800 gen_aarch64_compare_and_swaphi,
11801 gen_aarch64_compare_and_swapsi,
11802 gen_aarch64_compare_and_swapdi
11803 };
11805 {
11806 gen_aarch64_compare_and_swapqi_lse,
11807 gen_aarch64_compare_and_swaphi_lse,
11808 gen_aarch64_compare_and_swapsi_lse,
11809 gen_aarch64_compare_and_swapdi_lse
11810 };
11823 /* Normally the succ memory model must be stronger than fail, but in the
11824 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
11825 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
11832 {
11835 /* For short modes, we're going to perform the comparison in SImode,
11836 so do the zero-extension now. */
11840 /* Fall through. */
11844 /* Force the value into a register if needed. */
11851 }
11854 {
11861 }
11864 else
11875 }
11877 /* Test whether the target supports using a atomic load-operate instruction.
11878 CODE is the operation and AFTER is TRUE if the data in memory after the
11879 operation should be returned and FALSE if the data before the operation
11880 should be returned. Returns FALSE if the operation isn't supported by the
11881 architecture. */
11883 bool
11885 {
11890 {
11900 }
11901 }
11903 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
11904 sequence implementing an atomic operation. */
11906 static void
11908 {
11915 {
11917 }
11918 }
11920 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
11921 for the data in memory. EXPECTED is the value expected to be in memory.
11922 DESIRED is the value to store to memory. MEM is the memory location. MODEL
11923 is the memory ordering to use. */
11925 void
11928 rtx model)
11929 {
11931 machine_mode mode;
11936 {
11943 }
11945 /* Move the expected value into the CAS destination register. */
11948 /* Emit the CAS. */
11951 /* Compare the expected value with the value loaded by the CAS, to establish
11952 whether the swap was made. */
11954 }
11956 /* Split a compare and swap pattern. */
11958 void
11960 {
11962 machine_mode mode;
11967 rtx model_rtx;
11981 {
11984 }
11987 /* The initial load can be relaxed for a __sync operation since a final
11988 barrier will be emitted to stop code hoisting. */
11992 else
12004 {
12009 }
12010 else
12011 {
12015 }
12019 /* Emit any final barrier needed for a __sync operation. */
12022 }
12024 /* Emit a BIC instruction. */
12026 static void
12028 {
12033 {
12038 }
12041 }
12043 /* Emit an atomic swap. */
12045 static void
12048 {
12052 {
12059 }
12062 }
12064 /* Operations supported by aarch64_emit_atomic_load_op. */
12066 enum aarch64_atomic_load_op_code
12067 {
12071 AARCH64_LDOP_BIC /* A & ~B */
12072 };
12074 /* Emit an atomic load-operate. */
12076 static void
12080 {
12083 {
12084 gen_aarch64_atomic_loadaddqi,
12085 gen_aarch64_atomic_loadaddhi,
12086 gen_aarch64_atomic_loadaddsi,
12087 gen_aarch64_atomic_loadadddi
12088 };
12090 {
12091 gen_aarch64_atomic_loadeorqi,
12092 gen_aarch64_atomic_loadeorhi,
12093 gen_aarch64_atomic_loadeorsi,
12094 gen_aarch64_atomic_loadeordi
12095 };
12097 {
12098 gen_aarch64_atomic_loadsetqi,
12099 gen_aarch64_atomic_loadsethi,
12100 gen_aarch64_atomic_loadsetsi,
12101 gen_aarch64_atomic_loadsetdi
12102 };
12104 {
12105 gen_aarch64_atomic_loadclrqi,
12106 gen_aarch64_atomic_loadclrhi,
12107 gen_aarch64_atomic_loadclrsi,
12108 gen_aarch64_atomic_loadclrdi
12109 };
12110 aarch64_atomic_load_op_fn gen;
12114 {
12121 }
12124 {
12131 }
12134 }
12136 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
12137 location to store the data read from memory. OUT_RESULT is the location to
12138 store the result of the operation. MEM is the memory location to read and
12139 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
12140 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
12141 be NULL. */
12143 void
12146 {
12150 aarch64_atomic_load_op_code ldop_code;
12151 rtx src;
12152 rtx x;
12160 /* Make sure the value is in a register, putting it into a destination
12161 register if it needs to be manipulated. */
12164 {
12167 }
12168 else
12172 /* Preprocess the data for the operation as necessary. If the operation is
12173 a SET then emit a swap instruction and finish. */
12175 {
12181 /* Negate the value and treat it as a PLUS. */
12182 {
12183 rtx neg_src;
12185 /* Resize the value if necessary. */
12194 }
12195 /* Fall-through. */
12209 {
12210 rtx not_src;
12212 /* Resize the value if necessary. */
12221 }
12226 /* The operation can't be done with atomic instructions. */
12228 }
12232 /* If necessary, calculate the data in memory after the update by redoing the
12233 operation from values in registers. */
12238 {
12242 }
12247 {
12263 }
12268 }
12270 /* Split an atomic operation. */
12272 void
12275 {
12281 rtx x;
12283 /* Split the atomic operation into a sequence. */
12291 else
12295 /* The initial load can be relaxed for a __sync operation since a final
12296 barrier will be emitted to stop code hoisting. */
12300 else
12304 {
12318 {
12321 }
12322 /* Fall through. */
12328 }
12338 /* Emit any final barrier needed for a __sync operation. */
12341 }
12343 static void
12345 {
12346 /* Half-precision float operations. The compiler handles all operations
12347 with NULL libfuncs by converting to SFmode. */
12349 /* Conversions. */
12353 /* Arithmetic. */
12360 /* Comparisons. */
12368 }
12370 /* Target hook for c_mode_for_suffix. */
12371 static machine_mode
12373 {
12378 }
12380 /* We can only represent floating point constants which will fit in
12381 "quarter-precision" values. These values are characterised by
12382 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
12383 by:
12385 (-1)^s * (n/16) * 2^r
12387 Where:
12388 's' is the sign bit.
12389 'n' is an integer in the range 16 <= n <= 31.
12390 'r' is an integer in the range -3 <= r <= 4. */
12392 /* Return true iff X can be represented by a quarter-precision
12393 floating point immediate operand X. Note, we cannot represent 0.0. */
12394 bool
12396 {
12397 /* This represents our current view of how many bits
12398 make up the mantissa. */
12408 /* We don't support HFmode constants yet. */
12414 /* We cannot represent infinities, NaNs or +/-zero. We won't
12415 know if we have +zero until we analyse the mantissa, but we
12416 can reject the other invalid values. */
12421 /* Extract exponent. */
12425 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12426 highest (sign) bit, with a fixed binary point at bit point_pos.
12427 m1 holds the low part of the mantissa, m2 the high part.
12428 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
12429 bits for the mantissa, this can fail (low bits will be lost). */
12433 /* If the low part of the mantissa has bits set we cannot represent
12434 the value. */
12437 /* We have rejected the lower HOST_WIDE_INT, so update our
12438 understanding of how many bits lie in the mantissa and
12439 look only at the high HOST_WIDE_INT. */
12443 /* We can only represent values with a mantissa of the form 1.xxxx. */
12448 /* Having filtered unrepresentable values, we may now remove all
12449 but the highest 5 bits. */
12452 /* We cannot represent the value 0.0, so reject it. This is handled
12453 elsewhere. */
12457 /* Then, as bit 4 is always set, we can mask it off, leaving
12458 the mantissa in the range [0, 15]. */
12462 /* GCC internally does not use IEEE754-like encoding (where normalized
12463 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
12464 Our mantissa values are shifted 4 places to the left relative to
12465 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
12466 by 5 places to correct for GCC's representation. */
12470 }
12474 machine_mode mode,
12476 {
12486 /* This will return true to show const_vector is legal for use as either
12487 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
12488 also update INFO to show how the immediate should be generated. */
12497 {
12499 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
12500 move immediate path. */
12503 else
12504 {
12513 else
12517 }
12518 }
12531 else
12535 }
12539 machine_mode mode)
12540 {
12541 machine_mode vmode;
12547 }
12549 /* Split operands into moves from op[1] + op[2] into op[0]. */
12551 void
12553 {
12564 {
12565 /* No-op move. Can't split to nothing; emit something. */
12568 }
12570 /* Preserve register attributes for variable tracking. */
12575 /* Special case of reversed high/low parts. */
12578 {
12582 }
12584 {
12585 /* Try to avoid unnecessary moves if part of the result
12586 is in the right place already. */
12591 }
12592 else
12593 {
12598 }
12599 }
12601 /* vec_perm support. */
12603 #define MAX_VECT_LEN 16
12605 struct expand_vec_perm_d
12606 {
12609 machine_mode vmode;
12613 };
12615 /* Generate a variable permutation. */
12617 static void
12619 {
12630 {
12632 {
12633 /* Expand the argument to a V16QI mode by duplicating it. */
12637 }
12638 else
12639 {
12641 }
12642 }
12643 else
12644 {
12645 rtx pair;
12648 {
12652 }
12653 else
12654 {
12658 }
12659 }
12660 }
12662 void
12664 {
12668 rtx mask;
12670 /* The TBL instruction does not use a modulo index, so we must take care
12671 of that ourselves. */
12676 /* For big-endian, we also need to reverse the index within the vector
12677 (but not which vector). */
12679 {
12680 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
12685 }
12687 }
12689 /* Recognize patterns suitable for the TRN instructions. */
12690 static bool
12692 {
12701 /* Note that these are little-endian tests.
12702 We correct for big-endian later. */
12707 else
12712 {
12717 }
12719 /* Success! */
12726 {
12729 }
12733 {
12735 {
12750 }
12751 }
12752 else
12753 {
12755 {
12770 }
12771 }
12775 }
12777 /* Recognize patterns suitable for the UZP instructions. */
12778 static bool
12780 {
12789 /* Note that these are little-endian tests.
12790 We correct for big-endian later. */
12795 else
12800 {
12804 }
12806 /* Success! */
12813 {
12816 }
12820 {
12822 {
12837 }
12838 }
12839 else
12840 {
12842 {
12857 }
12858 }
12862 }
12864 /* Recognize patterns suitable for the ZIP instructions. */
12865 static bool
12867 {
12876 /* Note that these are little-endian tests.
12877 We correct for big-endian later. */
12880 /* Do Nothing. */
12881 ;
12884 else
12889 {
12896 }
12898 /* Success! */
12905 {
12908 }
12912 {
12914 {
12929 }
12930 }
12931 else
12932 {
12934 {
12949 }
12950 }
12954 }
12956 /* Recognize patterns for the EXT insn. */
12958 static bool
12960 {
12963 rtx offset;
12967 /* Check if the extracted indices are increasing by one. */
12969 {
12972 {
12973 /* We'll pass the same vector in twice, so allow indices to wrap. */
12975 }
12978 }
12981 {
12996 }
12998 /* Success! */
13002 /* The case where (location == 0) is a no-op for both big- and little-endian,
13003 and is removed by the mid-end at optimization levels -O1 and higher. */
13006 {
13007 /* After setup, we want the high elements of the first vector (stored
13008 at the LSB end of the register), and the low elements of the second
13009 vector (stored at the MSB end of the register). So swap. */
13011 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
13013 }
13018 }
13020 /* Recognize patterns for the REV insns. */
13022 static bool
13024 {
13033 {
13036 {
13041 }
13045 {
13052 }
13056 {
13069 }
13073 }
13077 {
13078 /* This is guaranteed to be true as the value of diff
13079 is 7, 3, 1 and we should have enough elements in the
13080 queue to generate this. Getting a vector mask with a
13081 value of diff other than these values implies that
13082 something is wrong by the time we get here. */
13086 }
13088 /* Success! */
13094 }
13096 static bool
13098 {
13101 rtx in0;
13104 rtx lane;
13108 {
13111 }
13113 /* The generic preparation in aarch64_expand_vec_perm_const_1
13114 swaps the operand order and the permute indices if it finds
13115 d->perm[0] to be in the second operand. Thus, we can always
13116 use d->op0 and need not do any extra arithmetic to get the
13117 correct lane number. */
13122 {
13137 }
13141 }
13143 static bool
13145 {
13153 /* Generic code will try constant permutation twice. Once with the
13154 original mode and again with the elements lowered to QImode.
13155 So wait and don't do the selector expansion ourselves. */
13160 {
13163 /* If big-endian and two vectors we end up with a weird mixed-endian
13164 mode on NEON. Reverse the index within each word but not the word
13165 itself. */
13168 }
13174 }
13176 static bool
13178 {
13179 /* The pattern matching functions above are written to look for a small
13180 number to begin the sequence (0, 1, N/2). If we begin with an index
13181 from the second operand, we can swap the operands. */
13183 {
13191 }
13194 {
13208 }
13210 }
13212 /* Expand a vec_perm_const pattern. */
13214 bool
13216 {
13230 {
13235 }
13238 {
13247 /* The elements of PERM do not suggest that only the first operand
13248 is used, but both operands are identical. Allow easier matching
13249 of the permutation by folding the permutation into the single
13250 input vector. */
13251 /* Fall Through. */
13263 }
13266 }
13268 static bool
13271 {
13281 /* Calculate whether all elements are in one vector. */
13283 {
13287 }
13289 /* If all elements are from the second vector, reindex as if from the
13290 first vector. */
13295 /* Check whether the mask can be applied to a single vector. */
13308 }
13310 rtx
13312 {
13313 /* We have to reverse each vector because we dont have
13314 a permuted load that can reverse-load according to ABI rules. */
13315 rtx mask;
13329 }
13331 /* Implement MODES_TIEABLE_P. In principle we should always return true.
13332 However due to issues with register allocation it is preferable to avoid
13333 tieing integer scalar and FP scalar modes. Executing integer operations
13334 in general registers is better than treating them as scalar vector
13335 operations. This reduces latency and avoids redundant int<->FP moves.
13336 So tie modes if they are either the same class, or vector modes with
13337 other vector modes, vector structs or any scalar mode.
13338 */
13340 bool
13342 {
13346 /* We specifically want to allow elements of "structure" modes to
13347 be tieable to the structure. This more general condition allows
13348 other rarer situations too. */
13352 /* Also allow any scalar modes with vectors. */
13358 }
13360 /* Return a new RTX holding the result of moving POINTER forward by
13361 AMOUNT bytes. */
13363 static rtx
13365 {
13370 }
13372 /* Return a new RTX holding the result of moving POINTER forward by the
13373 size of the mode it points to. */
13375 static rtx
13377 {
13381 }
13383 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
13384 MODE bytes. */
13386 static void
13388 machine_mode mode)
13389 {
13392 /* "Cast" the pointers to the correct mode. */
13395 /* Emit the memcpy. */
13398 /* Move the pointers forward. */
13401 }
13403 /* Expand movmem, as if from a __builtin_memcpy. Return true if
13404 we succeed, otherwise return false. */
13406 bool
13408 {
13412 rtx base;
13415 /* When optimizing for size, give a better estimate of the length of a
13416 memcpy call, but use the default otherwise. */
13419 /* We can't do anything smart if the amount to copy is not constant. */
13425 /* Try to keep the number of instructions low. For cases below 16 bytes we
13426 need to make at most two moves. For cases above 16 bytes it will be one
13427 move for each 16 byte chunk, then at most two additional moves. */
13437 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
13438 1-byte chunk. */
13440 {
13442 {
13445 }
13451 }
13453 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
13454 4-byte chunk, partially overlapping with the previously copied chunk. */
13456 {
13460 {
13466 }
13468 }
13470 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
13471 them, then (if applicable) an 8-byte chunk. */
13473 {
13475 {
13478 }
13479 else
13480 {
13483 }
13484 }
13486 /* Finish the final bytes of the copy. We can always do this in one
13487 instruction. We either copy the exact amount we need, or partially
13488 overlap with the previous chunk we copied and copy 8-bytes. */
13497 else
13498 {
13500 {
13504 }
13505 else
13506 {
13512 }
13513 }
13516 }
13518 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
13519 SImode stores. Handle the case when the constant has identical
13520 bottom and top halves. This is beneficial when the two stores can be
13521 merged into an STP and we avoid synthesising potentially expensive
13522 immediates twice. Return true if such a split is possible. */
13524 bool
13526 {
13535 unsigned int orig_cost
13537 unsigned int lo_cost
13540 /* We want to transform:
13541 MOV x1, 49370
13542 MOVK x1, 0x140, lsl 16
13543 MOVK x1, 0xc0da, lsl 32
13544 MOVK x1, 0x140, lsl 48
13545 STR x1, [x0]
13546 into:
13547 MOV w1, 49370
13548 MOVK w1, 0x140, lsl 16
13549 STP w1, w1, [x0]
13550 So we want to perform this only when we save two instructions
13551 or more. When optimizing for size, however, accept any code size
13552 savings we can. */
13567 /* Don't emit an explicit store pair as this may not be always profitable.
13568 Let the sched-fusion logic decide whether to merge them. */
13573 }
13575 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
13577 static unsigned HOST_WIDE_INT
13579 {
13581 }
13583 static bool
13588 {
13589 /* STORE_BY_PIECES can be used when copying a constant string, but
13590 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
13591 For now we always fail this and let the move_by_pieces code copy
13592 the string from read-only memory. */
13597 }
13599 static rtx
13602 {
13606 insn_code icode;
13617 {
13645 }
13650 {
13653 }
13662 {
13665 }
13671 }
13673 static rtx
13676 {
13680 insn_code icode;
13692 {
13720 }
13725 {
13728 }
13736 {
13741 }
13752 {
13755 }
13761 }
13763 #undef TARGET_GEN_CCMP_FIRST
13764 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
13766 #undef TARGET_GEN_CCMP_NEXT
13767 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
13769 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
13770 instruction fusion of some sort. */
13772 static bool
13774 {
13776 }
13779 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
13780 should be kept together during scheduling. */
13782 static bool
13784 {
13785 rtx set_dest;
13788 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
13795 {
13796 /* We are trying to match:
13797 prev (mov) == (set (reg r0) (const_int imm16))
13798 curr (movk) == (set (zero_extract (reg r0)
13799 (const_int 16)
13800 (const_int 16))
13801 (const_int imm16_1)) */
13813 {
13815 }
13816 }
13819 {
13821 /* We're trying to match:
13822 prev (adrp) == (set (reg r1)
13823 (high (symbol_ref ("SYM"))))
13824 curr (add) == (set (reg r0)
13825 (lo_sum (reg r1)
13826 (symbol_ref ("SYM"))))
13827 Note that r0 need not necessarily be the same as r1, especially
13828 during pre-regalloc scheduling. */
13832 {
13840 }
13841 }
13844 {
13846 /* We're trying to match:
13847 prev (movk) == (set (zero_extract (reg r0)
13848 (const_int 16)
13849 (const_int 32))
13850 (const_int imm16_1))
13851 curr (movk) == (set (zero_extract (reg r0)
13852 (const_int 16)
13853 (const_int 48))
13854 (const_int imm16_2)) */
13870 }
13872 {
13873 /* We're trying to match:
13874 prev (adrp) == (set (reg r0)
13875 (high (symbol_ref ("SYM"))))
13876 curr (ldr) == (set (reg r1)
13877 (mem (lo_sum (reg r0)
13878 (symbol_ref ("SYM")))))
13879 or
13880 curr (ldr) == (set (reg r1)
13881 (zero_extend (mem
13882 (lo_sum (reg r0)
13883 (symbol_ref ("SYM")))))) */
13886 {
13899 }
13900 }
13908 {
13911 /* FIXME: this misses some which is considered simple arthematic
13912 instructions for ThunderX. Simple shifts are missed here. */
13918 }
13921 }
13923 /* Return true iff the instruction fusion described by OP is enabled. */
13925 bool
13927 {
13929 }
13931 /* If MEM is in the form of [base+offset], extract the two parts
13932 of address and set to BASE and OFFSET, otherwise return false
13933 after clearing BASE and OFFSET. */
13935 bool
13937 {
13938 rtx addr;
13945 {
13949 }
13953 {
13957 }
13963 }
13965 /* Types for scheduling fusion. */
13966 enum sched_fusion_type
13967 {
13969 SCHED_FUSION_LD_SIGN_EXTEND,
13970 SCHED_FUSION_LD_ZERO_EXTEND,
13971 SCHED_FUSION_LD,
13972 SCHED_FUSION_ST,
13973 SCHED_FUSION_NUM
13974 };
13976 /* If INSN is a load or store of address in the form of [base+offset],
13977 extract the two parts and set to BASE and OFFSET. Return scheduling
13978 fusion type this INSN is. */
13980 static enum sched_fusion_type
13982 {
14000 {
14005 }
14007 {
14012 }
14017 {
14020 }
14021 else
14028 }
14030 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
14032 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
14033 and PRI are only calculated for these instructions. For other instruction,
14034 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
14035 type instruction fusion can be added by returning different priorities.
14037 It's important that irrelevant instructions get the largest FUSION_PRI. */
14039 static void
14042 {
14052 {
14056 }
14058 /* Set FUSION_PRI according to fusion type and base register. */
14061 /* Calculate PRI. */
14064 /* INSN with smaller offset goes first. */
14068 else
14073 }
14075 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
14076 Adjust priority of sha1h instructions so they are scheduled before
14077 other SHA1 instructions. */
14079 static int
14081 {
14085 {
14090 }
14093 }
14095 /* Given OPERANDS of consecutive load/store, check if we can merge
14096 them into ldp/stp. LOAD is true if they are load instructions.
14097 MODE is the mode of memory operands. */
14099 bool
14102 {
14108 {
14116 }
14117 else
14118 {
14123 }
14125 /* The mems cannot be volatile. */
14129 /* If we have SImode and slow unaligned ldp,
14130 check the alignment to be at least 8 byte. */
14134 && !optimize_size
14138 /* Check if the addresses are in the form of [base+offset]. */
14146 /* Check if the bases are same. */
14153 /* Check if the offsets are consecutive. */
14157 /* Check if the addresses are clobbered by load. */
14159 {
14163 /* In increasing order, the last load can clobber the address. */
14166 }
14170 else
14175 else
14178 /* Check if the registers are of same class. */
14183 }
14185 /* Given OPERANDS of consecutive load/store, check if we can merge
14186 them into ldp/stp by adjusting the offset. LOAD is true if they
14187 are load instructions. MODE is the mode of memory operands.
14189 Given below consecutive stores:
14191 str w1, [xb, 0x100]
14192 str w1, [xb, 0x104]
14193 str w1, [xb, 0x108]
14194 str w1, [xb, 0x10c]
14196 Though the offsets are out of the range supported by stp, we can
14197 still pair them after adjusting the offset, like:
14199 add scratch, xb, 0x100
14200 stp w1, w1, [scratch]
14201 stp w1, w1, [scratch, 0x8]
14203 The peephole patterns detecting this opportunity should guarantee
14204 the scratch register is avaliable. */
14206 bool
14209 {
14216 {
14229 }
14230 else
14231 {
14240 }
14241 /* Skip if memory operand is by itslef valid for ldp/stp. */
14245 /* The mems cannot be volatile. */
14250 /* Check if the addresses are in the form of [base+offset]. */
14264 /* Check if the bases are same. */
14275 /* Check if the offsets are consecutive. */
14284 /* Check if the addresses are clobbered by load. */
14286 {
14292 /* In increasing order, the last load can clobber the address. */
14295 }
14297 /* If we have SImode and slow unaligned ldp,
14298 check the alignment to be at least 8 byte. */
14302 && !optimize_size
14308 else
14313 else
14318 else
14323 else
14326 /* Check if the registers are of same class. */
14331 }
14333 /* Given OPERANDS of consecutive load/store, this function pairs them
14334 into ldp/stp after adjusting the offset. It depends on the fact
14335 that addresses of load/store instructions are in increasing order.
14336 MODE is the mode of memory operands. CODE is the rtl operator
14337 which should be applied to all memory operands, it's SIGN_EXTEND,
14338 ZERO_EXTEND or UNKNOWN. */
14340 bool
14343 {
14349 {
14354 }
14355 else
14356 {
14362 }
14367 /* Adjust offset thus it can fit in ldp/stp instruction. */
14375 /* Further adjust to make sure all offsets are OK. */
14377 {
14380 }
14382 /* Make sure the adjustment can be done with ADD/SUB instructions. */
14387 {
14390 }
14392 /* Create new memory references. */
14396 /* Check if the adjusted address is OK for ldp/stp. */
14415 {
14420 }
14422 {
14427 }
14430 {
14435 }
14436 else
14437 {
14442 }
14444 /* Emit adjusting instruction. */
14446 /* Emit ldp/stp instructions. */
14454 }
14456 /* Return 1 if pseudo register should be created and used to hold
14457 GOT address for PIC code. */
14459 bool
14461 {
14463 }
14465 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
14467 static int
14469 {
14471 {
14478 }
14481 }
14484 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
14485 return the log2 of that value. Otherwise return -1. */
14487 int
14489 {
14504 }
14506 /* If X is a vector of equal CONST_DOUBLE values and that value is
14507 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
14509 int
14511 {
14527 }
14529 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
14530 to float.
14532 __fp16 always promotes through this hook.
14533 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
14534 through the generic excess precision logic rather than here. */
14536 static tree
14538 {
14544 }
14546 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
14548 static bool
14550 optimization_type opt_type)
14551 {
14553 {
14559 }
14560 }
14562 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
14563 if MODE is HFmode, and punt to the generic implementation otherwise. */
14565 static bool
14567 {
14571 }
14573 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
14574 if MODE is HFmode, and punt to the generic implementation otherwise. */
14576 static bool
14578 {
14582 }
14584 /* Set the value of FLT_EVAL_METHOD.
14585 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
14587 0: evaluate all operations and constants, whose semantic type has at
14588 most the range and precision of type float, to the range and
14589 precision of float; evaluate all other operations and constants to
14590 the range and precision of the semantic type;
14592 N, where _FloatN is a supported interchange floating type
14593 evaluate all operations and constants, whose semantic type has at
14594 most the range and precision of _FloatN type, to the range and
14595 precision of the _FloatN type; evaluate all other operations and
14596 constants to the range and precision of the semantic type;
14598 If we have the ARMv8.2-A extensions then we support _Float16 in native
14599 precision, so we should set this to 16. Otherwise, we support the type,
14600 but want to evaluate expressions in float precision, so set this to
14601 0. */
14603 static enum flt_eval_method
14605 {
14607 {
14610 /* We can calculate either in 16-bit range and precision or
14611 32-bit range and precision. Make that decision based on whether
14612 we have native support for the ARMv8.2-A 16-bit floating-point
14613 instructions or not. */
14615 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
14621 }
14623 }
14625 /* Target-specific selftests. */
14627 #if CHECKING_P
14631 /* Selftest for the RTL loader.
14632 Verify that the RTL loader copes with a dump from
14633 print_rtx_function. This is essentially just a test that class
14634 function_reader can handle a real dump, but it also verifies
14635 that lookup_reg_by_dump_name correctly handles hard regs.
14636 The presence of hard reg names in the dump means that the test is
14637 target-specific, hence it is in this file. */
14639 static void
14641 {
14653 /* Verify crtl->return_rtx. */
14657 }
14659 /* Run all target-specific selftests. */
14661 static void
14663 {
14665 }
14671 #undef TARGET_ADDRESS_COST
14672 #define TARGET_ADDRESS_COST aarch64_address_cost
14674 /* This hook will determines whether unnamed bitfields affect the alignment
14675 of the containing structure. The hook returns true if the structure
14676 should inherit the alignment requirements of an unnamed bitfield's
14677 type. */
14678 #undef TARGET_ALIGN_ANON_BITFIELD
14679 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
14681 #undef TARGET_ASM_ALIGNED_DI_OP
14684 #undef TARGET_ASM_ALIGNED_HI_OP
14687 #undef TARGET_ASM_ALIGNED_SI_OP
14690 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14691 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
14692 hook_bool_const_tree_hwi_hwi_const_tree_true
14694 #undef TARGET_ASM_FILE_START
14695 #define TARGET_ASM_FILE_START aarch64_start_file
14697 #undef TARGET_ASM_OUTPUT_MI_THUNK
14698 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
14700 #undef TARGET_ASM_SELECT_RTX_SECTION
14701 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
14703 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14704 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
14706 #undef TARGET_BUILD_BUILTIN_VA_LIST
14707 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
14709 #undef TARGET_CALLEE_COPIES
14710 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
14712 #undef TARGET_CAN_ELIMINATE
14713 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
14715 #undef TARGET_CAN_INLINE_P
14716 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
14718 #undef TARGET_CANNOT_FORCE_CONST_MEM
14719 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
14721 #undef TARGET_CASE_VALUES_THRESHOLD
14722 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
14724 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14725 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
14727 /* Only the least significant bit is used for initialization guard
14728 variables. */
14729 #undef TARGET_CXX_GUARD_MASK_BIT
14730 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
14732 #undef TARGET_C_MODE_FOR_SUFFIX
14733 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
14735 #ifdef TARGET_BIG_ENDIAN_DEFAULT
14736 #undef TARGET_DEFAULT_TARGET_FLAGS
14737 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
14738 #endif
14740 #undef TARGET_CLASS_MAX_NREGS
14741 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
14743 #undef TARGET_BUILTIN_DECL
14744 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
14746 #undef TARGET_BUILTIN_RECIPROCAL
14747 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
14749 #undef TARGET_C_EXCESS_PRECISION
14750 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
14752 #undef TARGET_EXPAND_BUILTIN
14753 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
14755 #undef TARGET_EXPAND_BUILTIN_VA_START
14756 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
14758 #undef TARGET_FOLD_BUILTIN
14759 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
14761 #undef TARGET_FUNCTION_ARG
14762 #define TARGET_FUNCTION_ARG aarch64_function_arg
14764 #undef TARGET_FUNCTION_ARG_ADVANCE
14765 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
14767 #undef TARGET_FUNCTION_ARG_BOUNDARY
14768 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
14770 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14771 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
14773 #undef TARGET_FUNCTION_VALUE
14774 #define TARGET_FUNCTION_VALUE aarch64_function_value
14776 #undef TARGET_FUNCTION_VALUE_REGNO_P
14777 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
14779 #undef TARGET_FRAME_POINTER_REQUIRED
14780 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
14782 #undef TARGET_GIMPLE_FOLD_BUILTIN
14783 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
14785 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14786 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
14788 #undef TARGET_INIT_BUILTINS
14789 #define TARGET_INIT_BUILTINS aarch64_init_builtins
14791 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
14792 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
14793 aarch64_ira_change_pseudo_allocno_class
14795 #undef TARGET_LEGITIMATE_ADDRESS_P
14796 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
14798 #undef TARGET_LEGITIMATE_CONSTANT_P
14799 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
14801 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
14802 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
14803 aarch64_legitimize_address_displacement
14805 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14806 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
14808 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
14809 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
14810 aarch64_libgcc_floating_mode_supported_p
14812 #undef TARGET_MANGLE_TYPE
14813 #define TARGET_MANGLE_TYPE aarch64_mangle_type
14815 #undef TARGET_MEMORY_MOVE_COST
14816 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
14818 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
14819 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
14821 #undef TARGET_MUST_PASS_IN_STACK
14822 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14824 /* This target hook should return true if accesses to volatile bitfields
14825 should use the narrowest mode possible. It should return false if these
14826 accesses should use the bitfield container type. */
14827 #undef TARGET_NARROW_VOLATILE_BITFIELD
14828 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
14830 #undef TARGET_OPTION_OVERRIDE
14831 #define TARGET_OPTION_OVERRIDE aarch64_override_options
14833 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
14834 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
14835 aarch64_override_options_after_change
14837 #undef TARGET_OPTION_SAVE
14838 #define TARGET_OPTION_SAVE aarch64_option_save
14840 #undef TARGET_OPTION_RESTORE
14841 #define TARGET_OPTION_RESTORE aarch64_option_restore
14843 #undef TARGET_OPTION_PRINT
14844 #define TARGET_OPTION_PRINT aarch64_option_print
14846 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14847 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
14849 #undef TARGET_SET_CURRENT_FUNCTION
14850 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
14852 #undef TARGET_PASS_BY_REFERENCE
14853 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
14855 #undef TARGET_PREFERRED_RELOAD_CLASS
14856 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
14858 #undef TARGET_SCHED_REASSOCIATION_WIDTH
14859 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
14861 #undef TARGET_PROMOTED_TYPE
14862 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
14864 #undef TARGET_SECONDARY_RELOAD
14865 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
14867 #undef TARGET_SHIFT_TRUNCATION_MASK
14868 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
14870 #undef TARGET_SETUP_INCOMING_VARARGS
14871 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
14873 #undef TARGET_STRUCT_VALUE_RTX
14874 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
14876 #undef TARGET_REGISTER_MOVE_COST
14877 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
14879 #undef TARGET_RETURN_IN_MEMORY
14880 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
14882 #undef TARGET_RETURN_IN_MSB
14883 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
14885 #undef TARGET_RTX_COSTS
14886 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
14888 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14889 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
14891 #undef TARGET_SCHED_ISSUE_RATE
14892 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
14894 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14895 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14896 aarch64_sched_first_cycle_multipass_dfa_lookahead
14898 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
14899 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
14900 aarch64_first_cycle_multipass_dfa_lookahead_guard
14902 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
14903 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
14904 aarch64_get_separate_components
14906 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
14907 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
14908 aarch64_components_for_bb
14910 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
14911 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
14912 aarch64_disqualify_components
14914 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
14915 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
14916 aarch64_emit_prologue_components
14918 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
14919 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
14920 aarch64_emit_epilogue_components
14922 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
14923 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
14924 aarch64_set_handled_components
14926 #undef TARGET_TRAMPOLINE_INIT
14927 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
14929 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14930 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
14932 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14933 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
14935 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
14936 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
14937 aarch64_builtin_support_vector_misalignment
14939 #undef TARGET_ARRAY_MODE_SUPPORTED_P
14940 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
14942 #undef TARGET_VECTORIZE_ADD_STMT_COST
14943 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
14945 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
14946 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
14947 aarch64_builtin_vectorization_cost
14949 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
14950 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
14952 #undef TARGET_VECTORIZE_BUILTINS
14953 #define TARGET_VECTORIZE_BUILTINS
14955 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
14956 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
14957 aarch64_builtin_vectorized_function
14959 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
14960 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
14961 aarch64_autovectorize_vector_sizes
14963 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
14964 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
14965 aarch64_atomic_assign_expand_fenv
14967 /* Section anchor support. */
14969 #undef TARGET_MIN_ANCHOR_OFFSET
14970 #define TARGET_MIN_ANCHOR_OFFSET -256
14972 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
14973 byte offset; we can do much more for larger data types, but have no way
14974 to determine the size of the access. We assume accesses are aligned. */
14975 #undef TARGET_MAX_ANCHOR_OFFSET
14976 #define TARGET_MAX_ANCHOR_OFFSET 4095
14978 #undef TARGET_VECTOR_ALIGNMENT
14979 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
14981 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
14982 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
14983 aarch64_simd_vector_alignment_reachable
14985 /* vec_perm support. */
14987 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
14988 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
14989 aarch64_vectorize_vec_perm_const_ok
14991 #undef TARGET_INIT_LIBFUNCS
14992 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
14994 #undef TARGET_FIXED_CONDITION_CODE_REGS
14995 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
14997 #undef TARGET_FLAGS_REGNUM
14998 #define TARGET_FLAGS_REGNUM CC_REGNUM
15000 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
15001 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
15003 #undef TARGET_ASAN_SHADOW_OFFSET
15004 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
15006 #undef TARGET_LEGITIMIZE_ADDRESS
15007 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
15009 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
15010 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
15011 aarch64_use_by_pieces_infrastructure_p
15013 #undef TARGET_CAN_USE_DOLOOP_P
15014 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
15016 #undef TARGET_SCHED_ADJUST_PRIORITY
15017 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
15019 #undef TARGET_SCHED_MACRO_FUSION_P
15020 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
15022 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
15023 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
15025 #undef TARGET_SCHED_FUSION_PRIORITY
15026 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
15028 #undef TARGET_UNSPEC_MAY_TRAP_P
15029 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
15031 #undef TARGET_USE_PSEUDO_PIC_REG
15032 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
15034 #undef TARGET_PRINT_OPERAND
15035 #define TARGET_PRINT_OPERAND aarch64_print_operand
15037 #undef TARGET_PRINT_OPERAND_ADDRESS
15038 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
15040 #undef TARGET_OPTAB_SUPPORTED_P
15041 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
15043 #undef TARGET_OMIT_STRUCT_RETURN_REG
15044 #define TARGET_OMIT_STRUCT_RETURN_REG true
15046 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
15047 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
15048 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
15050 #if CHECKING_P
15051 #undef TARGET_RUN_TARGET_SELFTESTS
15052 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests