1 /* Check that the SH specific sh_treg_combine RTL optimization pass works as
2 expected. On SH2A the expected insns are slightly different, see
4 /* { dg-do compile } */
5 /* { dg-options "-O2" } */
6 /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
7 /* { dg-final { scan-assembler-times "tst" 7 } } */
8 /* { dg-final { scan-assembler-times "movt" 2 } } */
9 /* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
10 /* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
11 /* { dg-final { scan-assembler-times "cmp/gt" 2 } } */
12 /* { dg-final { scan-assembler-not "not\t" } } */
15 /* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi
16 SH2A: 1x tst, 1x nott, 2x cmp/eq, 1x cmp/hi */
18 blk_oversized_queue_0 (int* q
)
25 int __attribute__ ((noinline
))
26 get_request_0 (int* q
, int rw
)
28 if (blk_oversized_queue_0 (q
))
30 if ((rw
== 1) || (rw
== 0))
38 /* 1x tst, 1x cmp/gt, 1x cmp/hi
39 On SH2A mem loads/stores have a wrong length of 4 bytes and thus will
40 not be placed in a delay slot. This introduces an extra cmp/gt insn. */
42 blk_oversized_queue_1 (int* q
)
49 int __attribute__ ((noinline
))
50 get_request_1 (int* q
, int rw
)
52 if (blk_oversized_queue_1 (q
))
54 if ((rw
== 1) || (rw
== 0))
62 /* 1x tst, 1x cmp/gt, 1x cmp/hi, 1x cmp/hi */
64 blk_oversized_queue_2 (int* q
)
71 int __attribute__ ((noinline
))
72 get_request_2 (int* q
, int rw
)
74 if (blk_oversized_queue_2 (q
))
76 if ((rw
== 1) || (rw
== 0))
84 /* 3x tst, 1x movt, 1x cmp/hi, 1x not */
86 blk_oversized_queue_5 (int* q
)
93 int __attribute__ ((noinline
))
94 get_request_5 (int* q
, int rw
)
96 if (blk_oversized_queue_5 (q
))
98 if ((rw
== 1) || (rw
== 0))