| blob | 2e0e67be222c09c2e52c33602ee2853ca531bd95 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
332 {
336 }
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
348 /* Allocate a link. */
352 {
360 }
362 /* Incremented for each basic block. */
366 /* Reset to label_tick for each extended basic block in scanning order. */
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
379 in a loop. */
383 \f
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
389 struct undo
390 {
395 };
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
403 struct undobuf
404 {
408 };
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
418 machine_mode,
422 machine_mode,
496 \f
498 /* It is not safe to use ordinary gen_lowpart in combine.
499 See comments in gen_lowpart_for_combine. */
500 #undef RTL_HOOKS_GEN_LOWPART
501 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
503 /* Our implementation of gen_lowpart never emits a new pseudo. */
504 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
505 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
507 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
508 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
510 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
511 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
513 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
514 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
518 \f
519 /* Convenience wrapper for the canonicalize_comparison target hook.
520 Target hooks cannot use enum rtx_code. */
524 {
528 }
530 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
531 PATTERN can not be split. Otherwise, it returns an insn sequence.
532 This is a wrapper around split_insns which ensures that the
533 reg_stat vector is made larger if the splitter creates a new
534 register. */
538 {
547 }
549 /* This is used by find_single_use to locate an rtx in LOC that
550 contains exactly one use of DEST, which is typically either a REG
551 or CC0. It returns a pointer to the innermost rtx expression
552 containing DEST. Appearances of DEST that are being used to
553 totally replace it are not counted. */
557 {
566 {
570 CASE_CONST_ANY:
575 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
576 of a REG that occupies all of the REG, the insn uses DEST if
577 it is mentioned in the destination or the source. Otherwise, we
578 need just check the source. */
598 }
600 /* If it wasn't one of the common cases above, check each expression and
601 vector of this code. Look for a unique usage of DEST. */
605 {
607 {
612 else
618 /* Duplicate usage. */
620 }
622 {
626 {
632 else
639 }
640 }
641 }
644 }
647 /* See if DEST, produced in INSN, is used only a single time in the
648 sequel. If so, return a pointer to the innermost rtx expression in which
649 it is used.
651 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
653 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
654 care about REG_DEAD notes or LOG_LINKS.
656 Otherwise, we find the single use by finding an insn that has a
657 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
658 only referenced once in that insn, we know that it must be the first
659 and last insn referencing DEST. */
663 {
664 basic_block bb;
670 {
680 }
690 {
696 {
701 }
702 }
705 }
706 \f
707 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
708 insn. The substitution can be undone by undo_all. If INTO is already
709 set to NEWVAL, do not record this change. Because computing NEWVAL might
710 also call SUBST, we have to compute it before we put anything into
711 the undo table. */
713 static void
715 {
722 /* We'd like to catch as many invalid transformations here as
723 possible. Unfortunately, there are way too many mode changes
724 that are perfectly valid, so we'd waste too much effort for
725 little gain doing the checks here. Focus on catching invalid
726 transformations involving integer constants. */
729 {
730 /* Sanity check that we're replacing oldval with a CONST_INT
731 that is a valid sign-extension for the original mode. */
735 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
736 CONST_INT is not valid, because after the replacement, the
737 original mode would be gone. Unfortunately, we can't tell
738 when do_SUBST is called to replace the operand thereof, so we
739 perform this test on oldval instead, checking whether an
740 invalid replacement took place before we got here. */
745 }
749 else
758 }
760 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
762 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
763 for the value of a HOST_WIDE_INT value (including CONST_INT) is
764 not safe. */
766 static void
768 {
777 else
786 }
788 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
790 /* Similar to SUBST, but just substitute the mode. This is used when
791 changing the mode of a pseudo-register, so that any other
792 references to the entry in the regno_reg_rtx array will change as
793 well. */
795 static void
797 {
806 else
815 }
817 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
819 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
821 static void
823 {
832 else
841 }
843 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
844 \f
845 /* Subroutine of try_combine. Determine whether the replacement patterns
846 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
847 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
848 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
849 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
850 of all the instructions can be estimated and the replacements are more
851 expensive than the original sequence. */
853 static bool
856 {
861 /* Lookup the original insn_rtx_costs. */
866 {
869 {
873 }
874 else
875 {
879 }
880 }
881 else
882 {
885 }
887 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
888 correct that. */
893 /* Calculate the replacement insn_rtx_costs. */
896 {
900 }
901 else
902 {
905 }
908 {
914 {
917 }
918 else
920 }
922 /* Disallow this combination if both new_cost and old_cost are greater than
923 zero, and new_cost is greater than old cost. */
927 {
946 else
948 }
953 /* Update the uid_insn_cost array with the replacement costs. */
957 {
961 }
964 }
967 /* Delete any insns that copy a register to itself. */
969 static void
971 {
973 basic_block bb;
976 {
978 {
981 {
986 }
987 }
988 }
989 }
991 \f
992 /* Return false if we do not want to (or cannot) combine DEF. */
993 static bool
995 {
996 /* Do not consider if it is pre/post modification in MEM. */
1002 /* Do not combine frame pointer adjustments. */
1005 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1013 }
1015 /* Return false if we do not want to (or cannot) combine USE. */
1016 static bool
1018 {
1019 /* Do not consider the usage of the stack pointer by function call. */
1024 }
1026 /* Fill in log links field for all insns. */
1028 static void
1030 {
1031 basic_block bb;
1038 /* Pass through each block from the end, recording the uses of each
1039 register and establishing log links when def is encountered.
1040 Note that we do not clear next_use array in order to save time,
1041 so we have to test whether the use is in the same basic block as def.
1043 There are a few cases below when we do not consider the definition or
1044 usage -- these are taken from original flow.c did. Don't ask me why it is
1045 done this way; I don't know and if it works, I don't want to know. */
1048 {
1050 {
1054 /* Log links are created only once. */
1058 {
1074 /* flow.c claimed:
1076 We don't build a LOG_LINK for hard registers contained
1077 in ASM_OPERANDs. If these registers get replaced,
1078 we might wind up changing the semantics of the insn,
1079 even if reload can make what appear to be valid
1080 assignments later. */
1085 /* Don't add duplicate links between instructions. */
1094 }
1099 }
1100 }
1103 }
1105 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1106 true if we found a LOG_LINK that proves that A feeds B. This only works
1107 if there are no instructions between A and B which could have a link
1108 depending on A, since in that case we would not record a link for B.
1109 We also check the implicit dependency created by a cc0 setter/user
1110 pair. */
1112 static bool
1114 {
1122 }
1123 \f
1124 /* Main entry point for combiner. F is the first insn of the function.
1125 NREGS is the first unused pseudo-reg number.
1127 Return nonzero if the combiner has turned an indirect jump
1128 instruction into a direct jump. */
1129 static int
1131 {
1136 basic_block last_bb;
1156 /* Allocate array for insn info. */
1164 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1165 problems when, for example, we have j <<= 1 in a loop. */
1170 /* Scan all SETs and see if we can deduce anything about what
1171 bits are known to be zero for some registers and how many copies
1172 of the sign bit are known to exist for those registers.
1174 Also set any known values so that we can use it while searching
1175 for what bits are known to be set. */
1178 /* Allow the entry block and the first block to fall into the same EBB.
1179 Conceptually the incoming promotions are assigned to the entry block. */
1184 {
1189 label_tick++;
1197 {
1198 rtx links;
1204 insn);
1211 insn);
1213 /* Record the current insn_rtx_cost of this instruction. */
1216 optimize_this_for_speed_p);
1218 {
1221 }
1222 }
1223 }
1227 /* Now scan all the insns in forward order. */
1235 {
1241 label_tick++;
1251 {
1265 /* See if we know about function return values before this
1266 insn based upon SUBREG flags. */
1269 /* See if we can find hardregs and subreg of pseudos in
1270 narrower modes. This could help turning TRUNCATEs
1271 into SUBREGs. */
1274 /* Try this insn with each insn it links back to. */
1280 {
1283 }
1285 /* Try each sequence of three linked insns ending with this one. */
1289 {
1292 /* If the linked insn has been replaced by a note, then there
1293 is no point in pursuing this chain any further. */
1301 {
1304 }
1305 }
1307 /* Try to combine a jump insn that uses CC0
1308 with a preceding insn that sets CC0, and maybe with its
1309 logical predecessor as well.
1310 This is how we make decrement-and-branch insns.
1311 We need this special code because data flow connections
1312 via CC0 do not get entered in LOG_LINKS. */
1319 {
1330 }
1332 /* Do the same for an insn that explicitly references CC0. */
1339 {
1350 }
1352 /* Finally, see if any of the insns that this insn links to
1353 explicitly references CC0. If so, try this insn, that insn,
1354 and its predecessor if it sets CC0. */
1356 {
1368 }
1370 /* Try combining an insn with two different insns whose results it
1371 uses. */
1381 {
1384 }
1386 /* Try four-instruction combinations. */
1389 {
1393 /* If the linked insn has been replaced by a note, then there
1394 is no point in pursuing this chain any further. */
1399 {
1403 /* I0 -> I1 -> I2 -> I3. */
1409 {
1412 }
1413 /* I0, I1 -> I2, I2 -> I3. */
1420 {
1423 }
1424 }
1427 {
1431 /* I0 -> I2; I1, I2 -> I3. */
1437 {
1440 }
1441 /* I0 -> I1; I1, I2 -> I3. */
1447 {
1450 }
1451 }
1452 }
1454 /* Try this insn with each REG_EQUAL note it links back to. */
1456 {
1462 /* Avoid using a register that may already been marked
1463 dead by an earlier instruction. */
1471 {
1472 /* Temporarily replace the set's source with the
1473 contents of the REG_EQUAL note. The insn will
1474 be deleted or recognized by try_combine. */
1485 last_combined_insn);
1488 {
1491 }
1494 }
1495 }
1500 retry:
1501 ;
1502 }
1503 }
1510 /* Clean up. */
1516 {
1519 {
1522 }
1524 }
1534 /* Make recognizer allow volatile MEMs again. */
1538 }
1540 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1542 static void
1544 {
1550 }
1551 \f
1552 /* Set up any promoted values for incoming argument registers. */
1554 static void
1556 {
1557 tree arg;
1562 {
1567 /* Only continue if the incoming argument is in a register. */
1571 /* Determine, if possible, whether all call sites of the current
1572 function lie within the current compilation unit. (This does
1573 take into account the exporting of a function via taking its
1574 address, and so forth.) */
1577 /* The mode and signedness of the argument before any promotions happen
1578 (equal to the mode of the pseudo holding it at that stage). */
1582 /* The mode and signedness of the argument after any source language and
1583 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1587 /* The mode and signedness of the argument as it is actually passed,
1588 see assign_parm_setup_reg in function.c. */
1592 /* The mode of the register in which the argument is being passed. */
1595 /* Eliminate sign extensions in the callee when:
1596 (a) A mode promotion has occurred; */
1599 /* (b) The mode of the register is the same as the mode of
1600 the argument as it is passed; */
1603 /* (c) There's no language level extension; */
1605 ;
1606 /* (c.1) All callers are from the current compilation unit. If that's
1607 the case we don't have to rely on an ABI, we only have to know
1608 what we're generating right now, and we know that we will do the
1609 mode1 to mode2 promotion with the given sign. */
1612 /* (c.2) The combination of the two promotions is useful. This is
1613 true when the signs match, or if the first promotion is unsigned.
1614 In the later case, (sign_extend (zero_extend x)) is the same as
1615 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1621 /* Record that the value was promoted from mode1 to mode3,
1622 so that any sign extension at the head of the current
1623 function may be eliminated. */
1627 }
1628 }
1630 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1631 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1632 because some machines (maybe most) will actually do the sign-extension and
1633 this is the conservative approach.
1635 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1636 kludge. */
1638 static rtx
1640 {
1641 scalar_int_mode int_mode;
1650 }
1652 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1653 and SET. */
1655 static void
1657 rtx x)
1658 {
1668 {
1672 }
1674 /* Don't call nonzero_bits if it cannot change anything. */
1676 {
1681 }
1683 /* Don't call num_sign_bit_copies if it cannot change anything. */
1685 {
1688 {
1692 }
1695 }
1696 }
1698 /* Called via note_stores. If X is a pseudo that is narrower than
1699 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1701 If we are setting only a portion of X and we can't figure out what
1702 portion, assume all bits will be used since we don't know what will
1703 be happening.
1705 Similarly, set how many bits of X are known to be copies of the sign bit
1706 at all locations in the function. This is the smallest number implied
1707 by any set of X. */
1709 static void
1711 {
1713 scalar_int_mode mode;
1717 /* If this register is undefined at the start of the file, we can't
1718 say what its contents were. */
1719 && ! REGNO_REG_SET_P
1723 {
1727 {
1731 }
1733 /* If this register is being initialized using itself, and the
1734 register is uninitialized in this basic block, and there are
1735 no LOG_LINKS which set the register, then part of the
1736 register is uninitialized. In that case we can't assume
1737 anything about the number of nonzero bits.
1739 ??? We could do better if we checked this in
1740 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1741 could avoid making assumptions about the insn which initially
1742 sets the register, while still using the information in other
1743 insns. We would have to be careful to check every insn
1744 involved in the combination. */
1750 {
1757 {
1761 }
1762 }
1764 /* If this is a complex assignment, see if we can convert it into a
1765 simple assignment. */
1768 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1769 set what we know about X. */
1775 else
1776 {
1779 }
1780 }
1781 }
1782 \f
1783 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1784 optionally insns that were previously combined into I3 or that will be
1785 combined into the merger of INSN and I3. The order is PRED, PRED2,
1786 INSN, SUCC, SUCC2, I3.
1788 Return 0 if the combination is not allowed for any reason.
1790 If the combination is allowed, *PDEST will be set to the single
1791 destination of INSN and *PSRC to the single source, and this function
1792 will return 1. */
1794 static int
1798 {
1803 rtx link;
1808 {
1810 {
1815 }
1820 }
1824 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1825 or a PARALLEL consisting of such a SET and CLOBBERs.
1827 If INSN has CLOBBER parallel parts, ignore them for our processing.
1828 By definition, these happen during the execution of the insn. When it
1829 is merged with another insn, all bets are off. If they are, in fact,
1830 needed and aren't also supplied in I3, they may be added by
1831 recog_for_combine. Otherwise, it won't match.
1833 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1834 note.
1836 Get the source and destination of INSN. If more than one, can't
1837 combine. */
1843 {
1845 {
1849 {
1850 /* This is important to combine floating point insns
1851 for the SH4 port. */
1853 /* Combining an isolated USE doesn't make sense.
1854 We depend here on combinable_i3pat to reject them. */
1855 /* The code below this loop only verifies that the inputs of
1856 the SET in INSN do not change. We call reg_set_between_p
1857 to verify that the REG in the USE does not change between
1858 I3 and INSN.
1859 If the USE in INSN was for a pseudo register, the matching
1860 insn pattern will likely match any register; combining this
1861 with any other USE would only be safe if we knew that the
1862 used registers have identical values, or if there was
1863 something to tell them apart, e.g. different modes. For
1864 now, we forgo such complicated tests and simply disallow
1865 combining of USES of pseudo registers with any other USE. */
1868 {
1873 do
1874 {
1884 }
1886 }
1889 /* We can ignore CLOBBERs. */
1894 /* Ignore SETs whose result isn't used but not those that
1895 have side-effects. */
1901 /* If we have already found a SET, this is a second one and
1902 so we cannot combine with this insn. */
1910 /* Anything else means we can't combine. */
1912 }
1913 }
1916 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1917 so don't do anything with it. */
1920 }
1921 else
1927 /* The simplification in expand_field_assignment may call back to
1928 get_last_value, so set safe guard here. */
1934 /* Do not eliminate user-specified register if it is in an
1935 asm input because we may break the register asm usage defined
1936 in GCC manual if allow to do so.
1937 Be aware that this may cover more cases than we expect but this
1938 should be harmless. */
1943 /* Don't eliminate a store in the stack pointer. */
1945 /* Don't combine with an insn that sets a register to itself if it has
1946 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1948 /* Can't merge an ASM_OPERANDS. */
1950 /* Can't merge a function call. */
1952 /* Don't eliminate a function call argument. */
1958 /* Don't substitute into an incremented register. */
1962 /* Don't substitute into a non-local goto, this confuses CFG. */
1964 /* Make sure that DEST is not used after INSN but before SUCC, or
1965 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1966 || (!all_adjacent
1967 && ((succ2
1971 || (succ
1972 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1973 that case SUCC is not in the insn stream, so use SUCC2
1974 instead for this test. */
1976 succ2
1979 /* Make sure that the value that is to be substituted for the register
1980 does not use any registers whose values alter in between. However,
1981 If the insns are adjacent, a use can't cross a set even though we
1982 think it might (this can happen for a sequence of insns each setting
1983 the same destination; last_set of that register might point to
1984 a NOTE). If INSN has a REG_EQUIV note, the register is always
1985 equivalent to the memory so the substitution is valid even if there
1986 are intervening stores. Also, don't move a volatile asm or
1987 UNSPEC_VOLATILE across any other insns. */
1988 || (! all_adjacent
1994 /* Don't combine across a CALL_INSN, because that would possibly
1995 change whether the life span of some REGs crosses calls or not,
1996 and it is a pain to update that information.
1997 Exception: if source is a constant, moving it later can't hurt.
1998 Accept that as a special case. */
2002 /* DEST must either be a REG or CC0. */
2004 {
2005 /* If register alignment is being enforced for multi-word items in all
2006 cases except for parameters, it is possible to have a register copy
2007 insn referencing a hard register that is not allowed to contain the
2008 mode being copied and which would not be valid as an operand of most
2009 insns. Eliminate this problem by not combining with such an insn.
2011 Also, on some machines we don't want to extend the life of a hard
2012 register. */
2017 /* Don't extend the life of a hard register unless it is
2018 user variable (if we have few registers) or it can't
2019 fit into the desired register (meaning something special
2020 is going on).
2021 Also avoid substituting a return register into I3, because
2022 reload can't handle a conflict with constraints of other
2023 inputs. */
2027 }
2035 {
2038 /* If the clobber represents an earlyclobber operand, we must not
2039 substitute an expression containing the clobbered register.
2040 As we do not analyze the constraint strings here, we have to
2041 make the conservative assumption. However, if the register is
2042 a fixed hard reg, the clobber cannot represent any operand;
2043 we leave it up to the machine description to either accept or
2044 reject use-and-clobber patterns. */
2050 }
2052 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2053 or not), reject, unless nothing volatile comes between it and I3 */
2056 {
2057 /* Make sure neither succ nor succ2 contains a volatile reference. */
2062 /* We'll check insns between INSN and I3 below. */
2063 }
2065 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2066 to be an explicit register variable, and was chosen for a reason. */
2072 /* If INSN contains volatile references (specifically volatile MEMs),
2073 we cannot combine across any other volatile references.
2074 Even if INSN doesn't contain volatile references, any intervening
2075 volatile insn might affect machine state. */
2078 ? volatile_refs_p
2085 /* If INSN contains an autoincrement or autodecrement, make sure that
2086 register is not used between there and I3, and not already used in
2087 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2088 Also insist that I3 not be a jump; if it were one
2089 and the incremented register were spilled, we would lose. */
2107 /* Don't combine an insn that follows a CC0-setting insn.
2108 An insn that uses CC0 must not be separated from the one that sets it.
2109 We do, however, allow I2 to follow a CC0-setting insn if that insn
2110 is passed as I1; in that case it will be deleted also.
2111 We also allow combining in this case if all the insns are adjacent
2112 because that would leave the two CC0 insns adjacent as well.
2113 It would be more logical to test whether CC0 occurs inside I1 or I2,
2114 but that would be much slower, and this ought to be equivalent. */
2117 {
2122 }
2124 /* If we get here, we have passed all the tests and the combination is
2125 to be allowed. */
2131 }
2132 \f
2133 /* LOC is the location within I3 that contains its pattern or the component
2134 of a PARALLEL of the pattern. We validate that it is valid for combining.
2136 One problem is if I3 modifies its output, as opposed to replacing it
2137 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2138 doing so would produce an insn that is not equivalent to the original insns.
2140 Consider:
2142 (set (reg:DI 101) (reg:DI 100))
2143 (set (subreg:SI (reg:DI 101) 0) <foo>)
2145 This is NOT equivalent to:
2147 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2148 (set (reg:DI 101) (reg:DI 100))])
2150 Not only does this modify 100 (in which case it might still be valid
2151 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2153 We can also run into a problem if I2 sets a register that I1
2154 uses and I1 gets directly substituted into I3 (not via I2). In that
2155 case, we would be getting the wrong value of I2DEST into I3, so we
2156 must reject the combination. This case occurs when I2 and I1 both
2157 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2158 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2159 of a SET must prevent combination from occurring. The same situation
2160 can occur for I0, in which case I0_NOT_IN_SRC is set.
2162 Before doing the above check, we first try to expand a field assignment
2163 into a set of logical operations.
2165 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2166 we place a register that is both set and used within I3. If more than one
2167 such register is detected, we fail.
2169 Return 1 if the combination is valid, zero otherwise. */
2171 static int
2174 {
2178 {
2183 rtx subdest;
2190 /* Check for the case where I3 modifies its output, as discussed
2191 above. We don't want to prevent pseudos from being combined
2192 into the address of a MEM, so only prevent the combination if
2193 i1 or i2 set the same MEM. */
2203 /* This is the same test done in can_combine_p except we can't test
2204 all_adjacent; we don't have to, since this instruction will stay
2205 in place, thus we are not considering increasing the lifetime of
2206 INNER_DEST.
2208 Also, if this insn sets a function argument, combining it with
2209 something that might need a spill could clobber a previous
2210 function argument; the all_adjacent test in can_combine_p also
2211 checks this; here, we do a more specific test for this case. */
2221 /* If DEST is used in I3, it is being killed in this insn, so
2222 record that for later. We have to consider paradoxical
2223 subregs here, since they kill the whole register, but we
2224 ignore partial subregs, STRICT_LOW_PART, etc.
2225 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2226 STACK_POINTER_REGNUM, since these are always considered to be
2227 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2237 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2243 {
2248 }
2249 }
2252 {
2259 }
2262 }
2263 \f
2264 /* Return 1 if X is an arithmetic expression that contains a multiplication
2265 and division. We don't count multiplications by powers of two here. */
2267 static int
2269 {
2271 {
2287 }
2288 }
2289 \f
2290 /* Determine whether INSN can be used in a combination. Return nonzero if
2291 not. This is used in try_combine to detect early some cases where we
2292 can't perform combinations. */
2294 static int
2296 {
2297 rtx set;
2300 /* If this isn't really an insn, we can't do anything.
2301 This can occur when flow deletes an insn that it has merged into an
2302 auto-increment address. */
2306 /* Never combine loads and stores involving hard regs that are likely
2307 to be spilled. The register allocator can usually handle such
2308 reg-reg moves by tying. If we allow the combiner to make
2309 substitutions of likely-spilled regs, reload might die.
2310 As an exception, we allow combinations involving fixed regs; these are
2311 not available to the register allocator so there's no risk involved. */
2332 }
2334 struct likely_spilled_retval_info
2335 {
2338 };
2340 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2341 hard registers that are known to be written to / clobbered in full. */
2342 static void
2344 {
2361 else
2364 }
2366 /* Return nonzero iff part of the return value is live during INSN, and
2367 it is likely spilled. This can happen when more than one insn is needed
2368 to copy the return value, e.g. when we consider to combine into the
2369 second copy insn for a complex value. */
2371 static int
2373 {
2375 rtx reg;
2378 /* We assume here that no machine mode needs more than
2379 32 hard registers when the value overlaps with a register
2380 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2395 /* Disregard parts of the return value that are set later. */
2404 /* Check if any of the (probably) live return value registers is
2405 likely spilled. */
2406 nregs --;
2407 do
2408 {
2414 }
2416 /* Adjust INSN after we made a change to its destination.
2418 Changing the destination can invalidate notes that say something about
2419 the results of the insn and a LOG_LINK pointing to the insn. */
2421 static void
2423 {
2424 /* For notes, be conservative and simply remove them. */
2427 /* The new insn will have a destination that was previously the destination
2428 of an insn just above it. Call distribute_links to make a LOG_LINK from
2429 the next use of that destination. */
2445 }
2447 /* Return TRUE if combine can reuse reg X in mode MODE.
2448 ADDED_SETS is nonzero if the original set is still required. */
2449 static bool
2451 {
2458 /* Allow hard registers if the new mode is legal, and occupies no more
2459 registers than the old mode. */
2464 /* Or a pseudo that is only used once. */
2467 && !added_sets
2469 }
2472 /* Check whether X, the destination of a set, refers to part of
2473 the register specified by REG. */
2475 static bool
2477 {
2478 /* Check that reg is an integer mode register. */
2489 }
2491 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2492 Note that the INSN should be deleted *after* removing dead edges, so
2493 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2494 but not for a (set (pc) (label_ref FOO)). */
2496 static void
2498 {
2506 {
2511 /* Remove barriers from the footer if there are any. */
2514 {
2517 else
2521 }
2524 }
2525 }
2527 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2528 by an arbitrary number of CLOBBERs. */
2529 static bool
2531 {
2550 }
2552 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2553 CLOBBERs), can be split into individual SETs in that order, without
2554 changing semantics. */
2555 static bool
2557 {
2565 {
2574 }
2577 }
2579 /* Try to combine the insns I0, I1 and I2 into I3.
2580 Here I0, I1 and I2 appear earlier than I3.
2581 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2582 I3.
2584 If we are combining more than two insns and the resulting insn is not
2585 recognized, try splitting it into two insns. If that happens, I2 and I3
2586 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2587 Otherwise, I0, I1 and I2 are pseudo-deleted.
2589 Return 0 if the combination does not work. Then nothing is changed.
2590 If we did the combination, return the insn at which combine should
2591 resume scanning.
2593 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2594 new direct jump instruction.
2596 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2597 been I3 passed to an earlier try_combine within the same basic
2598 block. */
2603 {
2604 /* New patterns for I3 and I2, respectively. */
2608 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2609 dead. */
2611 /* Total number of SETs to put into I3. */
2613 /* Nonzero if I2's or I1's body now appears in I3. */
2615 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2617 /* Contains I3 if the destination of I3 is used in its source, which means
2618 that the old life of I3 is being killed. If that usage is placed into
2619 I2 and not in I3, a REG_DEAD note must be made. */
2621 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2623 /* Copy of SET_SRC of I1 and I0, if needed. */
2625 /* Set if I2DEST was reused as a scratch register. */
2627 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2629 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2634 /* Notes that must be added to REG_NOTES in I3 and I2. */
2636 /* Notes that we substituted I3 into I2 instead of the normal case. */
2638 /* Notes that I1, I2 or I3 is a MULT operation. */
2645 rtx temp_expr;
2648 rtx new_other_notes;
2651 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2652 never be). */
2656 /* Only try four-insn combinations when there's high likelihood of
2657 success. Look for simple insns, such as loads of constants or
2658 binary operations involving a constant. */
2660 {
2670 {
2673 rtx src;
2678 {
2681 }
2683 ngood++;
2686 nshift++;
2687 }
2689 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2690 are likely manipulating its value. Ideally we'll be able to combine
2691 all four insns into a bitfield insertion of some kind.
2693 Note the source in I0 might be inside a sign/zero extension and the
2694 memory modes in I0 and I3 might be different. So extract the address
2695 from the destination of I3 and search for it in the source of I0.
2697 In the event that there's a match but the source/dest do not actually
2698 refer to the same memory, the worst that happens is we try some
2699 combinations that we wouldn't have otherwise. */
2701 /* Ensure the source of SET0 is a MEM, possibly buried inside
2702 an extension. */
2708 /* Ensure the destination of SET3 is a MEM. */
2710 /* Would it be better to extract the base address for the MEM
2711 in SET3 and look for that? I don't have cases where it matters
2712 but I could envision such cases. */
2718 }
2720 /* Exit early if one of the insns involved can't be used for
2721 combinations. */
2732 combine_attempts++;
2735 /* Reset the hard register usage information. */
2739 {
2746 else
2749 }
2751 /* If multiple insns feed into one of I2 or I3, they can be in any
2752 order. To simplify the code below, reorder them in sequence. */
2762 /* First check for one important special case that the code below will
2763 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2764 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2765 we may be able to replace that destination with the destination of I3.
2766 This occurs in the common code where we compute both a quotient and
2767 remainder into a structure, in which case we want to do the computation
2768 directly into the structure to avoid register-register copies.
2770 Note that this case handles both multiple sets in I2 and also cases
2771 where I2 has a number of CLOBBERs inside the PARALLEL.
2773 We make very conservative checks below and only try to handle the
2774 most common cases of this. For example, we only handle the case
2775 where I2 and I3 are adjacent to avoid making difficult register
2776 usage tests. */
2784 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2785 below would need to check what is inside (and reg_overlap_mentioned_p
2786 doesn't support those codes anyway). Don't allow those destinations;
2787 the resulting insn isn't likely to be recognized anyway. */
2793 {
2796 /* Make sure that the destination of I3,
2797 which we are going to substitute into one output of I2,
2798 is not used within another output of I2. We must avoid making this:
2799 (parallel [(set (mem (reg 69)) ...)
2800 (set (reg 69) ...)])
2801 which is not well-defined as to order of actions.
2802 (Besides, reload can't handle output reloads for this.)
2804 The problem can also happen if the dest of I3 is a memory ref,
2805 if another dest in I2 is an indirect memory ref.
2807 Neither can this PARALLEL be an asm. We do not allow combining
2808 that usually (see can_combine_p), so do not here either. */
2811 {
2820 }
2826 {
2827 combine_merges++;
2837 /* Replace the dest in I2 with our dest and make the resulting
2838 insn the new pattern for I3. Then skip to where we validate
2839 the pattern. Everything was set up above. */
2844 }
2845 }
2847 /* If I2 is setting a pseudo to a constant and I3 is setting some
2848 sub-part of it to another constant, merge them by making a new
2849 constant. */
2856 {
2862 {
2865 {
2871 }
2872 }
2873 else
2874 {
2879 }
2882 {
2883 /* If this is the low part, we're done. */
2885 ;
2886 /* Handle the case where inner is twice the size of outer. */
2890 /* Otherwise give up for now. */
2891 else
2893 }
2896 {
2900 wide_int o
2905 combine_merges++;
2912 /* Replace the source in I2 with the new constant and make the
2913 resulting insn the new pattern for I3. Then skip to where we
2914 validate the pattern. Everything was set up above. */
2920 /* The dest of I3 has been replaced with the dest of I2. */
2923 }
2924 }
2926 /* If we have no I1 and I2 looks like:
2927 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2928 (set Y OP)])
2929 make up a dummy I1 that is
2930 (set Y OP)
2931 and change I2 to be
2932 (set (reg:CC X) (compare:CC Y (const_int 0)))
2934 (We can ignore any trailing CLOBBERs.)
2936 This undoes a previous combination and allows us to match a branch-and-
2937 decrement insn. */
2949 {
2950 /* We make I1 with the same INSN_UID as I2. This gives it
2951 the same DF_INSN_LUID for value tracking. Our fake I1 will
2952 never appear in the insn stream so giving it the same INSN_UID
2953 as I2 will not cause a problem. */
2966 }
2968 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2969 make those two SETs separate I1 and I2 insns, and make an I0 that is
2970 the original I1. */
2976 {
2977 /* If there is no I1, there is no I0 either. */
2980 /* We make I1 with the same INSN_UID as I2. This gives it
2981 the same DF_INSN_LUID for value tracking. Our fake I1 will
2982 never appear in the insn stream so giving it the same INSN_UID
2983 as I2 will not cause a problem. */
2991 }
2993 /* Verify that I2 and I1 are valid for combining. */
2999 {
3002 }
3004 /* Record whether I2DEST is used in I2SRC and similarly for the other
3005 cases. Knowing this will help in register status updating below. */
3016 /* For the earlier insns, determine which of the subsequent ones they
3017 feed. */
3024 /* Ensure that I3's pattern can be the destination of combines. */
3030 {
3033 }
3035 /* See if any of the insns is a MULT operation. Unless one is, we will
3036 reject a combination that is, since it must be slower. Be conservative
3037 here. */
3045 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3046 We used to do this EXCEPT in one case: I3 has a post-inc in an
3047 output operand. However, that exception can give rise to insns like
3048 mov r3,(r3)+
3049 which is a famous insn on the PDP-11 where the value of r3 used as the
3050 source was model-dependent. Avoid this sort of thing. */
3052 #if 0
3058 /* It's not the exception. */
3059 #endif
3061 {
3062 rtx link;
3068 {
3071 }
3072 }
3074 /* See if the SETs in I1 or I2 need to be kept around in the merged
3075 instruction: whenever the value set there is still needed past I3.
3076 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3078 For the SET in I1, we have two cases: if I1 and I2 independently feed
3079 into I3, the set in I1 needs to be kept around unless I1DEST dies
3080 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3081 in I1 needs to be kept around unless I1DEST dies or is set in either
3082 I2 or I3. The same considerations apply to I0. */
3089 else
3097 else
3100 /* We are about to copy insns for the case where they need to be kept
3101 around. Check that they can be copied in the merged instruction. */
3107 {
3110 }
3112 /* If the set in I2 needs to be kept around, we must make a copy of
3113 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3114 PATTERN (I2), we are only substituting for the original I1DEST, not into
3115 an already-substituted copy. This also prevents making self-referential
3116 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3117 I2DEST. */
3120 {
3123 else
3125 }
3128 {
3131 else
3133 }
3136 {
3139 else
3141 }
3143 combine_merges++;
3145 /* Substitute in the latest insn for the regs set by the earlier ones. */
3151 /* Many machines that don't use CC0 have insns that can both perform an
3152 arithmetic operation and set the condition code. These operations will
3153 be represented as a PARALLEL with the first element of the vector
3154 being a COMPARE of an arithmetic operation with the constant zero.
3155 The second element of the vector will set some pseudo to the result
3156 of the same arithmetic operation. If we simplify the COMPARE, we won't
3157 match such a pattern and so will generate an extra insn. Here we test
3158 for this case, where both the comparison and the operation result are
3159 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3160 I2SRC. Later we will make the PARALLEL that contains I2. */
3166 {
3167 rtx newpat_dest;
3173 scalar_int_mode mode;
3182 {
3188 }
3190 /* Do the rest only if op1 is const0_rtx, which may be the
3191 result of simplification. */
3193 {
3194 /* If a single use of the CC is found, prepare to modify it
3195 when SELECT_CC_MODE returns a new CC-class mode, or when
3196 the above simplify_compare_const() returned a new comparison
3197 operator. undobuf.other_insn is assigned the CC use insn
3198 when modifying it. */
3200 {
3201 #ifdef SELECT_CC_MODE
3202 machine_mode new_mode
3207 {
3212 else
3213 {
3216 }
3217 }
3218 #endif
3219 /* Cases for modifying the CC-using comparison. */
3221 /* ??? Do we need to verify the zero rtx? */
3223 {
3224 /* Replace cc_use_loc with entire new RTX. */
3229 }
3231 {
3232 /* Just replace the CC reg with a new mode. */
3235 }
3236 }
3238 /* Now we modify the current newpat:
3239 First, SET_DEST(newpat) is updated if the CC mode has been
3240 altered. For targets without SELECT_CC_MODE, this should be
3241 optimized away. */
3244 /* This is always done to propagate i2src into newpat. */
3247 /* Create new version of i2pat if needed; the below PARALLEL
3248 creation needs this to work correctly. */
3252 }
3253 }
3256 {
3257 /* It is possible that the source of I2 or I1 may be performing
3258 an unneeded operation, such as a ZERO_EXTEND of something
3259 that is known to have the high part zero. Handle that case
3260 by letting subst look at the inner insns.
3262 Another way to do this would be to have a function that tries
3263 to simplify a single insn instead of merging two or more
3264 insns. We don't do this because of the potential of infinite
3265 loops and because of the potential extra memory required.
3266 However, doing it the way we are is a bit of a kludge and
3267 doesn't catch all cases.
3269 But only do this if -fexpensive-optimizations since it slows
3270 things down and doesn't usually win.
3272 This is not done in the COMPARE case above because the
3273 unmodified I2PAT is used in the PARALLEL and so a pattern
3274 with a modified I2SRC would not match. */
3277 {
3278 /* Pass pc_rtx so no substitutions are done, just
3279 simplifications. */
3281 {
3284 }
3288 }
3293 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3294 copy of I2SRC each time we substitute it, in order to avoid creating
3295 self-referential RTL when we will be substituting I1SRC for I1DEST
3296 later. Likewise if I0 feeds into I2, either directly or indirectly
3297 through I1, and I0DEST is in I0SRC. */
3304 /* Record whether I2's body now appears within I3's body. */
3306 }
3308 /* If we already got a failure, don't try to do more. Otherwise, try to
3309 substitute I1 if we have it. */
3312 {
3313 /* Check that an autoincrement side-effect on I1 has not been lost.
3314 This happens if I1DEST is mentioned in I2 and dies there, and
3315 has disappeared from the new pattern. */
3317 && i1_feeds_i2_n
3320 /* Before we can do this substitution, we must redo the test done
3321 above (see detailed comments there) that ensures I1DEST isn't
3322 mentioned in any SETs in NEWPAT that are field assignments. */
3325 {
3328 }
3333 /* If the following substitution will modify I1SRC, make a copy of it
3334 for the case where it is substituted for I1DEST in I2PAT later. */
3338 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3339 copy of I1SRC each time we substitute it, in order to avoid creating
3340 self-referential RTL when we will be substituting I0SRC for I0DEST
3341 later. */
3346 /* Record whether I1's body now appears within I3's body. */
3348 }
3350 /* Likewise for I0 if we have it. */
3353 {
3360 {
3363 }
3365 /* If the following substitution will modify I0SRC, make a copy of it
3366 for the case where it is substituted for I0DEST in I1PAT later. */
3369 /* And a copy for I0DEST in I2PAT substitution. */
3378 }
3380 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3381 to count all the ways that I2SRC and I1SRC can be used. */
3392 /* Fail if we tried to make a new register. */
3394 /* Fail if we couldn't do something and have a CLOBBER. */
3396 /* Fail if this new pattern is a MULT and we didn't have one before
3397 at the outer level. */
3400 {
3403 }
3405 /* If the actions of the earlier insns must be kept
3406 in addition to substituting them into the latest one,
3407 we must make a new PARALLEL for the latest insn
3408 to hold additional the SETs. */
3411 {
3413 combine_extras++;
3416 {
3422 }
3423 else
3424 {
3429 }
3435 {
3441 }
3443 {
3452 }
3453 }
3455 validate_replacement:
3457 /* Note which hard regs this insn has as inputs. */
3460 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3461 consider splitting this pattern, we might need these clobbers. */
3464 {
3470 }
3472 /* We have recognized nothing yet. */
3475 /* See if this is a PARALLEL of two SETs where one SET's destination is
3476 a register that is unused and this isn't marked as an instruction that
3477 might trap in an EH region. In that case, we just need the other SET.
3478 We prefer this over the PARALLEL.
3480 This can occur when simplifying a divmod insn. We *must* test for this
3481 case here because the code below that splits two independent SETs doesn't
3482 handle this case correctly when it updates the register status.
3484 It's pointless doing this if we originally had two sets, one from
3485 i3, and one from i2. Combining then splitting the parallel results
3486 in the original i2 again plus an invalid insn (which we delete).
3487 The net effect is only to move instructions around, which makes
3488 debug info less accurate. */
3493 {
3504 {
3507 }
3516 {
3522 }
3526 }
3528 /* Is the result of combination a valid instruction? */
3532 /* If we were combining three insns and the result is a simple SET
3533 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3534 insns. There are two ways to do this. It can be split using a
3535 machine-specific method (like when you have an addition of a large
3536 constant) or by combine in the function find_split_point. */
3540 {
3544 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3545 use I2DEST as a scratch register will help. In the latter case,
3546 convert I2DEST to the mode of the source of NEWPAT if we can. */
3550 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3551 inputs of NEWPAT. */
3553 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3554 possible to try that as a scratch reg. This would require adding
3555 more code to make it work though. */
3558 {
3561 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3562 (temporarily, until we are committed to this instruction
3563 combination) does not work: for example, any call to nonzero_bits
3564 on the register (from a splitter in the MD file, for example)
3565 will get the old information, which is invalid.
3567 Since nowadays we can create registers during combine just fine,
3568 we should just create a new one here, not reuse i2dest. */
3570 /* First try to split using the original register as a
3571 scratch register. */
3575 i2dest)));
3578 /* If that didn't work, try changing the mode of I2DEST if
3579 we can. */
3584 {
3586 rtx ni2dest;
3590 else
3591 {
3594 }
3596 parallel = (gen_rtx_PARALLEL
3600 ni2dest))));
3605 {
3613 }
3614 }
3617 }
3619 /* If recog_for_combine has discarded clobbers, try to use them
3620 again for the split. */
3622 {
3625 }
3628 {
3633 }
3637 {
3647 /* If I2 or I3 has multiple SETs, we won't know how to track
3648 register status, so don't use these insns. If I2's destination
3649 is used between I2 and I3, we also can't use these insns. */
3659 /* It is possible that both insns now set the destination of I3.
3660 If so, we must show an extra use of it. */
3663 {
3682 }
3683 }
3685 /* If we can split it and use I2DEST, go ahead and see if that
3686 helps things be recognized. Verify that none of the registers
3687 are set between I2 and I3. */
3691 /* We need I2DEST in the proper mode. If it is a hard register
3692 or the only use of a pseudo, we can change its mode.
3693 Make sure we don't change a hard register to have a mode that
3694 isn't valid for it, or change the number of registers. */
3701 /* We can't overwrite I2DEST if its value is still used by
3702 NEWPAT. */
3704 {
3713 /* *SPLIT may be part of I2SRC, so make sure we have the
3714 original expression around for later debug processing.
3715 We should not need I2SRC any more in other cases. */
3718 else
3721 /* Get NEWDEST as a register in the proper mode. We have already
3722 validated that we can do this. */
3724 {
3727 else
3728 {
3731 }
3732 }
3734 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3735 an ASHIFT. This can occur if it was inside a PLUS and hence
3736 appeared to be a memory address. This is a kludge. */
3741 {
3744 /* Update split_code because we may not have a multiply
3745 anymore. */
3747 }
3749 /* Similarly for (plus (mult FOO (const_int pow2))). */
3755 {
3759 /* Update split_code because we may not have a multiply
3760 anymore. */
3762 }
3764 #ifdef INSN_SCHEDULING
3765 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3766 be written as a ZERO_EXTEND. */
3768 {
3769 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3770 what it really is. */
3775 else
3778 }
3779 #endif
3781 /* Attempt to split binary operators using arithmetic identities. */
3785 {
3792 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3794 {
3799 }
3800 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3807 {
3813 /* Split both "((X op Y) op X) op Y" and
3814 "((X op Y) op Y) op X" as "T op T" where T is
3815 "X op Y". */
3818 {
3823 }
3824 /* Split "((X op X) op Y) op Y)" as "T op T" where
3825 T is "X op Y". */
3827 {
3833 }
3834 }
3835 }
3838 {
3841 }
3845 /* recog_for_combine might have added CLOBBERs to newi2pat.
3846 Make sure NEWPAT does not depend on the clobbered regs. */
3850 {
3853 {
3856 }
3857 }
3859 /* If the split point was a MULT and we didn't have one before,
3860 don't use one now. */
3863 }
3864 }
3866 /* Check for a case where we loaded from memory in a narrow mode and
3867 then sign extended it, but we need both registers. In that case,
3868 we have a PARALLEL with both loads from the same memory location.
3869 We can split this into a load from memory followed by a register-register
3870 copy. This saves at least one insn, more if register allocation can
3871 eliminate the copy.
3873 We cannot do this if the destination of the first assignment is a
3874 condition code register or cc0. We eliminate this case by making sure
3875 the SET_DEST and SET_SRC have the same mode.
3877 We cannot do this if the destination of the second assignment is
3878 a register that we have already assumed is zero-extended. Similarly
3879 for a SUBREG of such a register. */
3914 {
3915 rtx ni2dest;
3929 }
3931 /* Similarly, check for a case where we have a PARALLEL of two independent
3932 SETs but we started with three insns. In this case, we can do the sets
3933 as two separate insns. This case occurs when some SET allows two
3934 other insns to combine, but the destination of that SET is still live.
3936 Also do this if we started with two insns and (at least) one of the
3937 resulting sets is a noop; this noop will be deleted later. */
3956 {
3960 /* Normally, it doesn't matter which of the two is done first,
3961 but the one that references cc0 can't be the second, and
3962 one which uses any regs/memory set in between i2 and i3 can't
3963 be first. The PARALLEL might also have been pre-existing in i3,
3964 so we need to make sure that we won't wrongly hoist a SET to i2
3965 that would conflict with a death note present in there. */
3973 /* If I3 is a jump, ensure that set0 is a jump so that
3974 we do not create invalid RTL. */
3976 )
3977 {
3980 }
3988 /* If I3 is a jump, ensure that set1 is a jump so that
3989 we do not create invalid RTL. */
3991 )
3992 {
3995 }
3996 else
3997 {
4000 }
4005 {
4006 /* recog_for_combine might have added CLOBBERs to newi2pat.
4007 Make sure NEWPAT does not depend on the clobbered regs. */
4009 {
4012 {
4015 {
4018 }
4019 }
4020 }
4023 }
4024 }
4026 /* If it still isn't recognized, fail and change things back the way they
4027 were. */
4029 /* Is the result a reasonable ASM_OPERANDS? */
4031 {
4034 }
4036 /* If we had to change another insn, make sure it is valid also. */
4038 {
4046 {
4049 }
4050 }
4052 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4053 they are adjacent to each other or not. */
4055 {
4059 {
4062 }
4063 }
4065 /* Only allow this combination if insn_rtx_costs reports that the
4066 replacement instructions are cheaper than the originals. */
4068 {
4071 }
4074 {
4079 {
4084 /* Temporarily revert mode back. */
4088 {
4089 /* If we used i2dest as a scratch register with a
4090 different mode, substitute it for the original
4091 i2src while its original mode is temporarily
4092 restored, and then clear i2scratch so that we don't
4093 do it again later. */
4095 this_basic_block);
4097 /* Put back the new mode. */
4099 }
4100 else
4101 {
4106 {
4109 }
4110 else
4111 {
4118 }
4120 /* We're dealing with a reg that changed mode but not
4121 meaning, so we want to turn it into a subreg for
4122 the new mode. However, because of REG sharing and
4123 because its mode had already changed, we have to do
4124 it in two steps. First, replace any debug uses of
4125 reg, with its original mode temporarily restored,
4126 with this copy we have created; then, replace the
4127 copy with the SUBREG of the original shared reg,
4128 once again changed to the new mode. */
4130 this_basic_block);
4134 this_basic_block);
4135 }
4136 }
4137 }
4139 /* If we will be able to accept this, we have made a
4140 change to the destination of I3. This requires us to
4141 do a few adjustments. */
4144 {
4147 }
4149 /* We now know that we can do this combination. Merge the insns and
4150 update the status of registers and LOG_LINKS. */
4153 {
4158 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4159 ensure that they are still valid. Then add any non-duplicate
4160 notes added by recog_for_combine. */
4162 {
4171 /* Simply drop equal note since it may be no longer valid
4172 for other_insn. It may be possible to record that CC
4173 register is changed and only discard those notes, but
4174 in practice it's unnecessary complication and doesn't
4175 give any meaningful improvement.
4177 See PR78559. */
4181 }
4185 NULL_RTX);
4186 }
4189 {
4192 rtx ni2dest;
4194 /* I3 now uses what used to be its destination and which is now
4195 I2's destination. This requires us to do a few adjustments. */
4199 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4200 so we still will.
4202 However, some later insn might be using I2's dest and have
4203 a LOG_LINK pointing at I3. We must remove this link.
4204 The simplest way to remove the link is to point it at I1,
4205 which we know will be a NOTE. */
4207 /* newi2pat is usually a SET here; however, recog_for_combine might
4208 have added some clobbers. */
4211 else
4218 {
4221 {
4227 }
4228 }
4229 }
4231 {
4236 /* Compute which registers we expect to eliminate. newi2pat may be setting
4237 either i3dest or i2dest, so we must check it. */
4240 || !i2dest_killed
4242 /* For i1, we need to compute both local elimination and global
4243 elimination information with respect to newi2pat because i1dest
4244 may be the same as i3dest, in which case newi2pat may be setting
4245 i1dest. Global information is used when distributing REG_DEAD
4246 note for i2 and i3, in which case it does matter if newi2pat sets
4247 i1dest or not.
4249 Local information is used when distributing REG_DEAD note for i1,
4250 in which case it doesn't matter if newi2pat sets i1dest or not.
4251 See PR62151, if we have four insns combination:
4252 i0: r0 <- i0src
4253 i1: r1 <- i1src (using r0)
4254 REG_DEAD (r0)
4255 i2: r0 <- i2src (using r1)
4256 i3: r3 <- i3src (using r0)
4257 ix: using r0
4258 From i1's point of view, r0 is eliminated, no matter if it is set
4259 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4260 should be discarded.
4262 Note local information only affects cases in forms like "I1->I2->I3",
4263 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4264 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4265 i0dest anyway. */
4267 || !i1dest_killed
4272 /* Same case as i1. */
4279 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4280 clear them. */
4288 /* Ensure that we do not have something that should not be shared but
4289 occurs multiple times in the new insns. Check this by first
4290 resetting all the `used' flags and then copying anything is shared. */
4314 {
4317 {
4319 {
4320 /* I2SRC must still be meaningful at this point. Some
4321 splitting operations can invalidate I2SRC, but those
4322 operations do not apply to calls. */
4326 }
4333 }
4334 }
4339 /* We had one special case above where I2 had more than one set and
4340 we replaced a destination of one of those sets with the destination
4341 of I3. In that case, we have to update LOG_LINKS of insns later
4342 in this basic block. Note that this (expensive) case is rare.
4344 Also, in this case, we must pretend that all REG_NOTEs for I2
4345 actually came from I3, so that REG_UNUSED notes from I2 will be
4346 properly handled. */
4349 {
4358 temp_insn
4368 {
4373 }
4374 else
4377 }
4385 {
4388 this_basic_block);
4391 }
4392 else
4393 {
4396 this_basic_block);
4398 }
4401 {
4406 this_basic_block);
4408 }
4411 {
4416 this_basic_block);
4418 }
4420 /* Get death notes for everything that is now used in either I3 or
4421 I2 and used to die in a previous insn. If we built two new
4422 patterns, move from I1 to I2 then I2 to I3 so that we get the
4423 proper movement on registers that I2 modifies. */
4429 else
4435 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4452 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4453 know these are REG_UNUSED and want them to go to the desired insn,
4454 so we always pass it as i3. */
4458 NULL_RTX);
4462 NULL_RTX);
4464 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4465 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4466 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4467 in that case, it might delete I2. Similarly for I2 and I1.
4468 Show an additional death due to the REG_DEAD note we make here. If
4469 we discard it in distribute_notes, we will decrement it again. */
4472 {
4477 else
4480 }
4483 {
4488 else
4491 }
4494 {
4499 else
4502 }
4505 {
4510 else
4513 }
4521 {
4526 /* The insn that used to set this register doesn't exist, and
4527 this life of the register may not exist either. See if one of
4528 I3's links points to an insn that sets I2DEST. If it does,
4529 that is now the last known value for I2DEST. If we don't update
4530 this and I2 set the register to a value that depended on its old
4531 contents, we will get confused. If this insn is used, thing
4532 will be set correctly in combine_instructions. */
4540 /* If the reg formerly set in I2 died only once and that was in I3,
4541 zero its use count so it won't make `reload' do any work. */
4544 && ! i2dest_in_i2src
4547 }
4550 {
4563 && ! i1dest_in_i1src
4566 }
4569 {
4582 && ! i0dest_in_i0src
4585 }
4587 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4588 been made to this insn. The order is important, because newi2pat
4589 can affect nonzero_bits of newpat. */
4593 }
4596 {
4598 {
4601 }
4603 }
4606 {
4608 {
4611 }
4613 }
4616 {
4618 {
4621 }
4623 }
4626 {
4628 {
4631 }
4633 }
4636 {
4638 {
4641 }
4643 }
4645 /* Set new_direct_jump_p if a new return or simple jump instruction
4646 has been created. Adjust the CFG accordingly. */
4648 {
4652 }
4657 {
4660 }
4664 {
4670 }
4675 {
4681 }
4683 /* A noop might also need cleaning up of CFG, if it comes from the
4684 simplification of a jump. */
4689 {
4692 }
4699 {
4702 }
4704 combine_successes++;
4711 else
4713 }
4714 \f
4715 /* Get a marker for undoing to the current state. */
4719 {
4721 }
4723 /* Undo the modifications up to the marker. */
4725 static void
4727 {
4731 {
4736 {
4751 }
4755 }
4758 }
4760 /* Undo all the modifications recorded in undobuf. */
4762 static void
4764 {
4766 }
4768 /* We've committed to accepting the changes we made. Move all
4769 of the undos to the free list. */
4771 static void
4773 {
4777 {
4781 }
4783 }
4784 \f
4785 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4786 where we have an arithmetic expression and return that point. LOC will
4787 be inside INSN.
4789 try_combine will call this function to see if an insn can be split into
4790 two insns. */
4794 {
4804 /* First special-case some codes. */
4806 {
4808 #ifdef INSN_SCHEDULING
4809 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4810 point. */
4813 #endif
4817 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4818 using LO_SUM and HIGH. */
4821 {
4829 }
4831 /* If we have a PLUS whose second operand is a constant and the
4832 address is not valid, perhaps will can split it up using
4833 the machine-specific way to split large constants. We use
4834 the first pseudo-reg (one of the virtual regs) as a placeholder;
4835 it will not remain in the result. */
4840 {
4843 subst_insn);
4845 /* This should have produced two insns, each of which sets our
4846 placeholder. If the source of the second is a valid address,
4847 we can make put both sources together and make a split point
4848 in the middle. */
4861 && memory_address_addr_space_p
4864 {
4868 /* Replace the placeholder in SRC2 with SRC1. If we can
4869 find where in SRC2 it was placed, that can become our
4870 split point and we can replace this address with SRC2.
4871 Just try two obvious places. */
4882 {
4885 }
4886 }
4888 /* If that didn't work, perhaps the first operand is complex and
4889 needs to be computed separately, so make a split point there.
4890 This will occur on machines that just support REG + CONST
4891 and have a constant moved through some previous computation. */
4897 }
4899 /* If we have a PLUS whose first operand is complex, try computing it
4900 separately by making a split there. */
4911 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4912 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4913 we need to put the operand into a register. So split at that
4914 point. */
4924 /* See if we can split SET_SRC as it stands. */
4929 /* See if we can split SET_DEST as it stands. */
4934 /* See if this is a bitfield assignment with everything constant. If
4935 so, this is an IOR of an AND, so split it into that. */
4947 {
4952 unsigned HOST_WIDE_INT mask
4954 rtx or_mask;
4963 else
4964 {
4970 or_mask));
4971 }
4978 }
4980 /* Otherwise, see if this is an operation that we can split into two.
4981 If so, try to split that. */
4985 {
4987 /* If we are AND'ing with a large constant that is only a single
4988 bit and the result is only being used in a context where we
4989 need to know if it is zero or nonzero, replace it with a bit
4990 extraction. This will avoid the large constant, which might
4991 have taken more than one insn to make. If the constant were
4992 not a valid argument to the AND but took only one insn to make,
4993 this is no worse, but if it took more than one insn, it will
4994 be better. */
5004 {
5009 {
5012 }
5013 }
5017 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5018 is known to be on, this can be converted into a NEG of a shift. */
5024 {
5036 }
5042 /* We can't optimize if either mode is a partial integer
5043 mode as we don't know how many bits are significant
5044 in those modes. */
5060 {
5068 }
5073 }
5078 {
5079 /* For unsigned, we have a choice of a shift followed by an
5080 AND or two shifts. Use two shifts for field sizes where the
5081 constant might be too large. We assume here that we can
5082 always at least get 8-bit constants in an AND insn, which is
5083 true for every current RISC. */
5086 {
5087 unsigned HOST_WIDE_INT mask
5091 gen_rtx_LSHIFTRT
5099 }
5100 else
5101 {
5103 gen_rtx_fmt_ee
5114 }
5115 }
5117 /* See if this is a simple operation with a constant as the second
5118 operand. It might be that this constant is out of range and hence
5119 could be used as a split point. */
5127 /* Finally, see if this is a simple operation with its first operand
5128 not in a register. The operation might require this operand in a
5129 register, so return it as a split point. We can always do this
5130 because if the first operand were another operation, we would have
5131 already found it as a split point. */
5140 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5141 it is better to write this as (not (ior A B)) so we can split it.
5142 Similarly for IOR. */
5144 {
5152 }
5154 /* Many RISC machines have a large set of logical insns. If the
5155 second operand is a NOT, put it first so we will try to split the
5156 other operand first. */
5158 {
5162 }
5167 /* Canonicalization can produce (minus A (mult B C)), where C is a
5168 constant. It may be better to try splitting (plus (mult B -C) A)
5169 instead if this isn't a multiply by a power of two. */
5173 {
5181 mode)),
5184 }
5186 /* Split at a multiply-accumulate instruction. However if this is
5187 the SET_SRC, we likely do not have such an instruction and it's
5188 worthless to try this split. */
5197 }
5199 /* Otherwise, select our actions depending on our rtx class. */
5201 {
5207 /* fall through */
5215 /* fall through */
5217 /* Some machines have (and (shift ...) ...) insns. If X is not
5218 an AND, but XEXP (X, 0) is, use it as our split point. */
5228 /* Otherwise, we don't have a split point. */
5230 }
5231 }
5232 \f
5233 /* Throughout X, replace FROM with TO, and return the result.
5234 The result is TO if X is FROM;
5235 otherwise the result is X, but its contents may have been modified.
5236 If they were modified, a record was made in undobuf so that
5237 undo_all will (among other things) return X to its original state.
5239 If the number of changes necessary is too much to record to undo,
5240 the excess changes are not made, so the result is invalid.
5241 The changes already made can still be undone.
5242 undobuf.num_undo is incremented for such changes, so by testing that
5243 the caller can tell whether the result is valid.
5245 `n_occurrences' is incremented each time FROM is replaced.
5247 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5249 IN_COND is nonzero if we are at the top level of a condition.
5251 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5252 by copying if `n_occurrences' is nonzero. */
5254 static rtx
5256 {
5261 rtx new_rtx;
5263 /* Two expressions are equal if they are identical copies of a shared
5264 RTX or if they are both registers with the same register number
5265 and mode. */
5267 #define COMBINE_RTX_EQUAL_P(X,Y) \
5268 ((X) == (Y) \
5269 || (REG_P (X) && REG_P (Y) \
5270 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5272 /* Do not substitute into clobbers of regs -- this will never result in
5273 valid RTL. */
5278 {
5279 n_occurrences++;
5281 }
5283 /* If X and FROM are the same register but different modes, they
5284 will not have been seen as equal above. However, the log links code
5285 will make a LOG_LINKS entry for that case. If we do nothing, we
5286 will try to rerecognize our original insn and, when it succeeds,
5287 we will delete the feeding insn, which is incorrect.
5289 So force this insn not to match in this (rare) case. */
5294 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5295 of which may contain things that can be combined. */
5299 /* It is possible to have a subexpression appear twice in the insn.
5300 Suppose that FROM is a register that appears within TO.
5301 Then, after that subexpression has been scanned once by `subst',
5302 the second time it is scanned, TO may be found. If we were
5303 to scan TO here, we would find FROM within it and create a
5304 self-referent rtl structure which is completely wrong. */
5308 /* Parallel asm_operands need special attention because all of the
5309 inputs are shared across the arms. Furthermore, unsharing the
5310 rtl results in recognition failures. Failure to handle this case
5311 specially can result in circular rtl.
5313 Solve this by doing a normal pass across the first entry of the
5314 parallel, and only processing the SET_DESTs of the subsequent
5315 entries. Ug. */
5320 {
5323 /* If this substitution failed, this whole thing fails. */
5331 {
5337 {
5340 /* If this substitution failed, this whole thing fails. */
5346 }
5347 }
5348 }
5349 else
5350 {
5354 /* We don't need to process a SET_DEST that is a register, CC0,
5355 or PC, so set up to skip this common case. All other cases
5356 where we want to suppress replacing something inside a
5357 SET_SRC are handled via the IN_DEST operand. */
5364 /* Trying to simplify the operands of a widening MULT is not likely
5365 to create RTL matching a machine insn. */
5377 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5378 constant. */
5383 {
5385 {
5388 {
5390 {
5393 n_occurrences++;
5394 }
5395 else
5396 {
5398 unique_copy);
5400 /* If this substitution failed, this whole thing
5401 fails. */
5405 }
5408 }
5409 }
5411 {
5412 /* If this is a register being set, ignore it. */
5419 ;
5422 {
5423 /* In general, don't install a subreg involving two
5424 modes not tieable. It can worsen register
5425 allocation, and can even make invalid reload
5426 insns, since the reg inside may need to be copied
5427 from in the outside mode, and that may be invalid
5428 if it is an fp reg copied in integer mode.
5430 We allow two exceptions to this: It is valid if
5431 it is inside another SUBREG and the mode of that
5432 SUBREG and the mode of the inside of TO is
5433 tieable and it is valid if X is a SET that copies
5434 FROM to CC0. */
5442 && (!HAVE_cc0
5457 n_occurrences++;
5458 }
5459 else
5460 /* If we are in a SET_DEST, suppress most cases unless we
5461 have gone inside a MEM, in which case we want to
5462 simplify the address. We assume here that things that
5463 are actually part of the destination have their inner
5464 parts in the first expression. This is true for SUBREG,
5465 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5466 things aside from REG and MEM that should appear in a
5467 SET_DEST. */
5469 (((in_dest
5475 unique_copy);
5477 /* If we found that we will have to reject this combination,
5478 indicate that by returning the CLOBBER ourselves, rather than
5479 an expression containing it. This will speed things up as
5480 well as prevent accidents where two CLOBBERs are considered
5481 to be equal, thus producing an incorrect simplification. */
5487 {
5495 }
5498 {
5502 }
5503 else
5505 }
5506 }
5507 }
5509 /* Check if we are loading something from the constant pool via float
5510 extension; in this case we would undo compress_float_constant
5511 optimization and degenerate constant load to an immediate value. */
5515 {
5519 }
5521 /* Try to simplify X. If the simplification changed the code, it is likely
5522 that further simplification will help, so loop, but limit the number
5523 of repetitions that will be performed. */
5526 {
5527 /* If X is sufficiently simple, don't bother trying to do anything
5528 with it. */
5537 /* We no longer know the original mode of operand 0 since we
5538 have changed the form of X) */
5540 }
5543 }
5544 \f
5545 /* If X is a commutative operation whose operands are not in the canonical
5546 order, use substitutions to swap them. */
5548 static void
5550 {
5553 {
5557 }
5558 }
5560 /* Simplify X, a piece of RTL. We just operate on the expression at the
5561 outer level; call `subst' to simplify recursively. Return the new
5562 expression.
5564 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5565 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5566 of a condition. */
5568 static rtx
5571 {
5574 scalar_int_mode int_mode;
5575 rtx temp;
5578 /* If this is a commutative operation, put a constant last and a complex
5579 expression first. We don't need to do this for comparisons here. */
5582 /* Try to fold this expression in case we have constants that weren't
5583 present before. */
5586 {
5594 {
5597 {
5601 }
5604 }
5617 }
5620 {
5625 }
5627 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5628 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5629 things. Check for cases where both arms are testing the same
5630 condition.
5632 Don't do anything if all operands are very simple. */
5645 {
5650 /* If everything is a comparison, what we have is highly unlikely
5651 to be simpler, so don't use it. */
5654 {
5661 /* Simplify the alternative arms; this may collapse the true and
5662 false arms to store-flag values. Be careful to use copy_rtx
5663 here since true_rtx or false_rtx might share RTL with x as a
5664 result of the if_then_else_cond call above. */
5668 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5669 is unlikely to be simpler. */
5672 {
5675 /* Restarting if we generate a store-flag expression will cause
5676 us to loop. Just drop through in this case. */
5678 /* If the result values are STORE_FLAG_VALUE and zero, we can
5679 just make the comparison operation. */
5690 /* Likewise, we can make the negate of a comparison operation
5691 if the result values are - STORE_FLAG_VALUE and zero. */
5699 mode);
5710 mode);
5711 else
5714 mode,
5715 VOIDmode,
5716 cond,
5717 cop1),
5722 }
5723 }
5724 }
5726 /* First see if we can apply the inverse distributive law. */
5729 {
5733 }
5735 /* If CODE is an associative operation not otherwise handled, see if we
5736 can associate some operands. This can win if they are constants or
5737 if they are logically related (i.e. (a & b) & a). */
5743 {
5745 {
5749 rtx inner;
5751 /* Make sure we pass the constant operand if any as the second
5752 one if this is a commutative operation. */
5760 /* For commutative operations, try the other pair if that one
5761 didn't simplify. */
5763 {
5768 }
5772 }
5773 }
5775 /* A little bit of algebraic simplification here. */
5777 {
5779 /* Ensure that our address has any ASHIFTs converted to MULT in case
5780 address-recognizing predicates are called later. */
5789 /* See if this can be moved to simplify_subreg. */
5792 /* Don't call gen_lowpart if the inner mode
5793 is VOIDmode and we cannot simplify it, as SUBREG without
5794 inner mode is invalid. */
5801 {
5802 rtx temp;
5808 /* If op is known to have all lower bits zero, the result is zero. */
5821 }
5823 /* Don't change the mode of the MEM if that would change the meaning
5824 of the address. */
5831 /* Note that we cannot do any narrowing for non-constants since
5832 we might have been counting on using the fact that some bits were
5833 zero. We now do this in the SET. */
5840 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5841 replaced by (lshiftrt X C). This will convert
5842 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5850 /* If X has only a single bit that might be nonzero, say, bit I, convert
5851 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5852 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5853 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5854 or a SUBREG of one since we'd be making the expression more
5855 complex if it was just a register. */
5862 {
5863 rtx temp1 = simplify_shift_const
5869 /* If all we did was surround TEMP with the two shifts, we
5870 haven't improved anything, so don't use it. Otherwise,
5871 we are better off with TEMP1. */
5876 }
5880 /* We can't handle truncation to a partial integer mode here
5881 because we don't know the real bitsize of the partial
5882 integer mode. */
5891 /* We can truncate a constant value and return it. */
5895 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5896 whose value is a comparison can be replaced with a subreg if
5897 STORE_FLAG_VALUE permits. */
5906 /* (const (const X)) can become (const X). Do it this way rather than
5907 returning the inner CONST since CONST can be shared with a
5908 REG_EQUAL note. */
5914 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5915 can add in an offset. find_split_point will split this address up
5916 again if it doesn't match. */
5923 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5924 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5925 bit-field and can be replaced by either a sign_extend or a
5926 sign_extract. The `and' may be a zero_extend and the two
5927 <c>, -<c> constants may be reversed. */
5943 return simplify_shift_const
5950 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5951 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5952 the bitsize of the mode - 1. This allows simplification of
5953 "a = (b & 8) == 0;" */
5960 return simplify_shift_const
5964 const1_rtx),
5968 /* If we are adding two things that have no bits in common, convert
5969 the addition into an IOR. This will often be further simplified,
5970 for example in cases like ((a & 1) + (a & 2)), which can
5971 become a & 3. */
5976 {
5977 /* Try to simplify the expression further. */
5981 /* If we could, great. If not, do not go ahead with the IOR
5982 replacement, since PLUS appears in many special purpose
5983 address arithmetic instructions. */
5991 }
5993 /* Canonicalize x + x into x << 1. */
6002 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6003 (and <foo> (const_int pow2-1)) */
6014 /* If we have (mult (plus A B) C), apply the distributive law and then
6015 the inverse distributive law to see if things simplify. This
6016 occurs mostly in addresses, often when unrolling loops. */
6019 {
6023 }
6025 /* Try simplify a*(b/c) as (a*b)/c. */
6028 {
6034 }
6038 /* If this is a divide by a power of two, treat it as a shift if
6039 its first operand is a shift. */
6059 /* If the first operand is a condition code, we can't do anything
6060 with it. */
6064 {
6072 /* Simplify our comparison, if possible. */
6075 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6076 if only the low-order bit is possibly nonzero in X (such as when
6077 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6078 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6079 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6080 (plus X 1).
6082 Remove any ZERO_EXTRACT we made when thinking this was a
6083 comparison. It may now be simpler to use, e.g., an AND. If a
6084 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6085 the call to make_compound_operation in the SET case.
6087 Don't apply these optimizations if the caller would
6088 prefer a comparison rather than a value.
6089 E.g., for the condition in an IF_THEN_ELSE most targets need
6090 an explicit comparison. */
6093 ;
6111 {
6115 int_mode);
6116 }
6124 {
6128 const1_rtx);
6129 }
6138 {
6141 }
6143 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6144 those above. */
6146 ;
6163 {
6167 int_mode);
6168 }
6177 {
6181 int_mode);
6182 }
6184 /* If X is 0/1, (eq X 0) is X-1. */
6191 {
6194 }
6196 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6197 one bit that might be nonzero, we can convert (ne x 0) to
6198 (ashift x c) where C puts the bit in the sign bit. Remove any
6199 AND with STORE_FLAG_VALUE when we are done, since we are only
6200 going to test the sign bit. */
6208 {
6214 else
6216 }
6218 /* If the code changed, return a whole new comparison.
6219 We also need to avoid using SUBST in cases where
6220 simplify_comparison has widened a comparison with a CONST_INT,
6221 since in that case the wider CONST_INT may fail the sanity
6222 checks in do_SUBST. */
6229 /* Otherwise, keep this operation, but maybe change its operands.
6230 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6233 }
6243 /* If we are processing SET_DEST, we are done. */
6261 /* If this is a shift by a constant amount, simplify it. */
6269 (HOST_WIDE_INT_1U
6277 }
6280 }
6281 \f
6282 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6284 static rtx
6286 {
6293 rtx temp;
6296 rtx reversed;
6299 /* Simplify storing of the truth value. */
6304 /* Also when the truth value has to be reversed. */
6310 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6311 in it is being compared against certain values. Get the true and false
6312 comparisons and see if that says anything about the value of each arm. */
6318 {
6319 HOST_WIDE_INT nzb;
6325 /* If FALSE_CODE is EQ, swap the codes and arms. */
6328 {
6331 }
6333 scalar_int_mode from_mode;
6335 {
6336 /* If we are comparing against zero and the expression being
6337 tested has only a single bit that might be nonzero, that is
6338 its value when it is not equal to zero. Similarly if it is
6339 known to be -1 or 0. */
6343 {
6346 }
6351 {
6354 }
6355 }
6357 /* Now simplify an arm if we know the value of the register in the
6358 branch and it is used in the arm. Be careful due to the potential
6359 of locally-shared RTL. */
6376 }
6378 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6379 reversed, do so to avoid needing two sets of patterns for
6380 subtract-and-branch insns. Similarly if we have a constant in the true
6381 arm, the false arm is the same as the first operand of the comparison, or
6382 the false arm is more complicated than the true arm. */
6395 {
6404 /* It is possible that the conditional has been simplified out. */
6407 }
6409 /* If the two arms are identical, we don't need the comparison. */
6414 /* Convert a == b ? b : a to "a". */
6426 /* Look for cases where we have (abs x) or (neg (abs X)). */
6429 && comparison_p
6436 {
6442 return
6445 mode);
6448 }
6450 /* Look for MIN or MAX. */
6453 && comparison_p
6458 {
6473 }
6475 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6476 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6477 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6478 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6479 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6480 neither 1 or -1, but it isn't worth checking for. */
6483 && comparison_p
6486 {
6502 /* If an identity-zero op is commutative, check whether there
6503 would be a match if we swapped the operands. */
6524 {
6528 }
6541 {
6545 }
6562 {
6566 }
6579 {
6583 }
6586 {
6592 const_true_rtx));
6600 }
6601 }
6603 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6604 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6605 negation of a single bit, we can convert this operation to a shift. We
6606 can actually do this more generally, but it doesn't seem worth it. */
6618 return
6622 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6623 non-zero bit in A is C1. */
6631 {
6637 }
6640 }
6641 \f
6642 /* Simplify X, a SET expression. Return the new expression. */
6644 static rtx
6646 {
6649 machine_mode mode
6653 scalar_int_mode int_mode;
6655 /* (set (pc) (return)) gets written as (return). */
6659 /* Now that we know for sure which bits of SRC we are using, see if we can
6660 simplify the expression for the object knowing that we only need the
6661 low-order bits. */
6664 {
6667 }
6669 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6670 the comparison result and try to simplify it unless we already have used
6671 undobuf.other_insn. */
6679 {
6688 {
6691 {
6694 }
6695 }
6696 else
6704 {
6708 }
6709 else
6710 {
6715 /* Attempt to simplify CC user. */
6717 {
6721 }
6723 /* Convert X into a no-op move. */
6727 }
6729 /* Simplify our comparison, if possible. */
6732 #ifdef SELECT_CC_MODE
6733 /* If this machine has CC modes other than CCmode, check to see if we
6734 need to use a different CC mode here. */
6743 else
6746 /* If the mode changed, we have to change SET_DEST, the mode in the
6747 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6748 a hard register, just build new versions with the proper mode. If it
6749 is a pseudo, we lose unless it is only time we set the pseudo, in
6750 which case we can safely change its mode. */
6752 {
6754 {
6756 rtx new_dest;
6760 else
6761 {
6764 }
6771 }
6772 }
6775 /* If the code changed, we have to build a new comparison in
6776 undobuf.other_insn. */
6778 {
6787 /* If the only change we made was to change an EQ into an NE or
6788 vice versa, OP0 has only one bit that might be nonzero, and OP1
6789 is zero, check if changing the user of the condition code will
6790 produce a valid insn. If it won't, we can keep the original code
6791 in that insn by surrounding our operation with an XOR. */
6798 {
6803 {
6810 }
6811 }
6812 }
6817 /* Don't generate a compare of a CC with 0, just use that CC. */
6819 {
6822 }
6823 /* Otherwise, if we didn't previously have the same COMPARE we
6824 want, create it from scratch. */
6827 {
6830 }
6831 }
6832 else
6833 {
6834 /* Get SET_SRC in a form where we have placed back any
6835 compound expressions. Then do the checks below. */
6838 }
6840 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6841 and X being a REG or (subreg (reg)), we may be able to convert this to
6842 (set (subreg:m2 x) (op)).
6844 We can always do this if M1 is narrower than M2 because that means that
6845 we only care about the low bits of the result.
6847 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6848 perform a narrower operation than requested since the high-order bits will
6849 be undefined. On machine where it is defined, this transformation is safe
6850 as long as M1 and M2 have the same number of words. */
6859 #ifdef CANNOT_CHANGE_MODE_CLASS
6864 #endif
6868 {
6871 dest));
6875 }
6877 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6878 in SRC. */
6884 {
6888 /* Here we make sure that we don't have a sign bit on. */
6891 {
6894 }
6895 }
6897 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6898 would require a paradoxical subreg. Replace the subreg with a
6899 zero_extend to avoid the reload that would otherwise be required. */
6905 {
6910 }
6912 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6913 are comparing an item known to be 0 or -1 against 0, use a logical
6914 operation instead. Check for one of the arms being an IOR of the other
6915 arm with some value. We compute three terms to be IOR'ed together. In
6916 practice, at most two will be nonzero. Then we do the IOR's. */
6924 && (!HAVE_conditional_move
6929 {
6954 int_mode),
6955 false_rtx);
6961 term3));
6964 }
6966 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6967 whole thing fail. */
6972 else
6973 /* Convert this into a field assignment operation, if possible. */
6975 }
6976 \f
6977 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6978 result. */
6980 static rtx
6982 {
6985 scalar_int_mode mode;
6988 {
6990 /* We can call simplify_and_const_int only if we don't lose
6991 any (sign) bits when converting INTVAL (op1) to
6992 "unsigned HOST_WIDE_INT". */
6997 {
7004 }
7006 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7007 apply the distributive law and then the inverse distributive
7008 law to see if things simplify. */
7010 {
7014 }
7016 {
7020 }
7024 /* If we have (ior (and A B) C), apply the distributive law and then
7025 the inverse distributive law to see if things simplify. */
7028 {
7032 }
7035 {
7039 }
7044 }
7047 }
7048 \f
7049 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7050 operations" because they can be replaced with two more basic operations.
7051 ZERO_EXTEND is also considered "compound" because it can be replaced with
7052 an AND operation, which is simpler, though only one operation.
7054 The function expand_compound_operation is called with an rtx expression
7055 and will convert it to the appropriate shifts and AND operations,
7056 simplifying at each stage.
7058 The function make_compound_operation is called to convert an expression
7059 consisting of shifts and ANDs into the equivalent compound expression.
7060 It is the inverse of this function, loosely speaking. */
7062 static rtx
7064 {
7068 rtx tem;
7069 scalar_int_mode inner_mode;
7072 {
7075 /* FALLTHRU */
7077 /* We can't necessarily use a const_int for a multiword mode;
7078 it depends on implicitly extending the value.
7079 Since we don't know the right way to extend it,
7080 we can't tell whether the implicit way is right.
7082 Even for a mode that is no wider than a const_int,
7083 we can't win, because we need to sign extend one of its bits through
7084 the rest of it, and we don't know which bit. */
7088 /* Reject modes that aren't scalar integers because turning vector
7089 or complex modes into shifts causes problems. */
7093 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7094 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7095 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7096 reloaded. If not for that, MEM's would very rarely be safe.
7098 Reject modes bigger than a word, because we might not be able
7099 to reference a two-register group starting with an arbitrary register
7100 (and currently gen_lowpart might crash for a SUBREG). */
7106 /* If the inner object has VOIDmode (the only way this can happen
7107 is if it is an ASM_OPERANDS), we can't do anything since we don't
7108 know how much masking to do. */
7117 /* fall through */
7120 /* If the operand is a CLOBBER, just return it. */
7128 /* Reject modes that aren't scalar integers because turning vector
7129 or complex modes into shifts causes problems. */
7136 /* This should stay within the object being extracted, fail otherwise. */
7147 }
7149 /* We've rejected non-scalar operations by now. */
7152 /* Convert sign extension to zero extension, if we know that the high
7153 bit is not set, as this is easier to optimize. It will be converted
7154 back to cheaper alternative in make_extraction. */
7160 {
7164 /* Make sure this is a profitable operation. */
7171 else
7173 }
7175 /* We can optimize some special cases of ZERO_EXTEND. */
7177 {
7178 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7179 know that the last value didn't have any inappropriate bits
7180 set. */
7188 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7197 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7198 is a comparison and STORE_FLAG_VALUE permits. This is like
7199 the first case, but it works even when MODE is larger
7200 than HOST_WIDE_INT. */
7208 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7217 }
7219 /* If we reach here, we want to return a pair of shifts. The inner
7220 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7221 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7222 logical depending on the value of UNSIGNEDP.
7224 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7225 converted into an AND of a shift.
7227 We must check for the case where the left shift would have a negative
7228 count. This can happen in a case like (x >> 31) & 255 on machines
7229 that can't shift by a constant. On those machines, we would first
7230 combine the shift with the AND to produce a variable-position
7231 extraction. Then the constant of 31 would be substituted in
7232 to produce such a position. */
7236 {
7244 }
7249 pos),
7251 else
7252 /* Any other cases we can't handle. */
7255 /* If we couldn't do this for some reason, return the original
7256 expression. */
7261 }
7262 \f
7263 /* X is a SET which contains an assignment of one object into
7264 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7265 or certain SUBREGS). If possible, convert it into a series of
7266 logical operations.
7268 We half-heartedly support variable positions, but do not at all
7269 support variable lengths. */
7271 static const_rtx
7273 {
7274 rtx inner;
7278 scalar_int_mode compute_mode;
7280 /* Loop until we find something we can't simplify. */
7282 {
7285 {
7289 }
7292 {
7297 /* A constant position should stay within the width of INNER. */
7303 {
7311 /* If position is ADJUST - X, new position is X. */
7313 else
7314 {
7319 pos);
7320 }
7321 }
7322 }
7324 /* A SUBREG between two modes that occupy the same numbers of words
7325 can be done by moving the SUBREG to the source. */
7327 /* We need SUBREGs to compute nonzero_bits properly. */
7328 && nonzero_sign_valid
7333 {
7335 gen_lowpart
7339 }
7340 else
7346 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7348 {
7349 /* Don't do anything for vector or complex integral types. */
7353 /* Try to find an integral mode to pun with. */
7359 }
7361 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7365 /* Don't try to compute in too wide unsupported modes. */
7369 /* Now compute the equivalent expression. Make a copy of INNER
7370 for the SET_DEST in case it is a MEM into which we will substitute;
7371 we don't want shared RTL in that case. */
7373 compute_mode);
7377 compute_mode,
7379 compute_mode),
7380 inner);
7385 mask),
7386 pos);
7391 }
7394 }
7395 \f
7396 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7397 it is an RTX that represents the (variable) starting position; otherwise,
7398 POS is the (constant) starting bit position. Both are counted from the LSB.
7400 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7402 IN_DEST is nonzero if this is a reference in the destination of a SET.
7403 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7404 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7405 be used.
7407 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7408 ZERO_EXTRACT should be built even for bits starting at bit 0.
7410 MODE is the desired mode of the result (if IN_DEST == 0).
7412 The result is an RTX for the extraction or NULL_RTX if the target
7413 can't handle it. */
7415 static rtx
7419 {
7420 /* This mode describes the size of the storage area
7421 to fetch the overall value from. Within that, we
7422 ignore the POS lowest bits, etc. */
7424 machine_mode inner_mode;
7425 machine_mode wanted_inner_mode;
7431 HOST_WIDE_INT orig_pos;
7437 {
7438 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7439 consider just the QI as the memory to extract from.
7440 The subreg adds or removes high bits; its mode is
7441 irrelevant to the meaning of this extraction,
7442 since POS and LEN count from the lsb. */
7446 }
7451 {
7452 /* We're extracting the least significant bits of an rtx
7453 (ashift X (const_int C)), where LEN > C. Extract the
7454 least significant (LEN - C) bits of X, giving an rtx
7455 whose mode is MODE, then shift it left C times. */
7461 }
7467 /* See if this can be done without an extraction. We never can if the
7468 width of the field is not the same as that of some integer mode. For
7469 registers, we can only avoid the extraction if the position is at the
7470 low-order bit and this is either not in the destination or we have the
7471 appropriate STRICT_LOW_PART operation available.
7473 For MEM, we can avoid an extract if the field starts on an appropriate
7474 boundary and we can change the mode of the memory reference. */
7476 scalar_int_mode tmode;
7485 && (! in_dest
7489 && (pos
7492 /* We can't do this if we are widening INNER_MODE (it
7493 may not be aligned, for one thing). */
7499 {
7500 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7501 field. If the original and current mode are the same, we need not
7502 adjust the offset. Otherwise, we do if bytes big endian.
7504 If INNER is not a MEM, get a piece consisting of just the field
7505 of interest (in this case POS % BITS_PER_WORD must be 0). */
7508 {
7509 HOST_WIDE_INT offset;
7511 /* POS counts from lsb, but make OFFSET count in memory order. */
7514 else
7518 }
7520 {
7522 {
7523 /* We can't call gen_lowpart in a DEST since we
7524 always want a SUBREG (see below) and it would sometimes
7525 return a new hard register. */
7527 {
7528 unsigned int offset
7531 /* Avoid creating invalid subregs, for example when
7532 simplifying (x>>32)&255. */
7537 }
7538 else
7540 }
7541 else
7543 }
7544 else
7546 len >= HOST_BITS_PER_WIDE_INT
7547 ? HOST_WIDE_INT_M1U
7550 /* If this extraction is going into the destination of a SET,
7551 make a STRICT_LOW_PART unless we made a MEM. */
7566 /* If we know that no extraneous bits are set, and that the high
7567 bit is not set, convert the extraction to the cheaper of
7568 sign and zero extension, that are equivalent in these cases. */
7574 {
7578 /* Prefer ZERO_EXTENSION, since it gives more information to
7579 backends. */
7584 }
7586 /* Otherwise, sign- or zero-extend unless we already are in the
7587 proper mode. */
7591 }
7593 /* Unless this is a COMPARE or we have a funny memory reference,
7594 don't do anything with zero-extending field extracts starting at
7595 the low-order bit since they are simple AND operations. */
7600 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7601 if the position is not a constant and the length is not 1. In all
7602 other cases, we would only be going outside our object in cases when
7603 an original shift would have been undefined. */
7612 /* If INNER is not from memory, we want it to have the mode of a register
7613 extraction pattern's structure operand, or word_mode if there is no
7614 such pattern. The same applies to extraction_mode and pos_mode
7615 and their respective operands.
7617 For memory, assume that the desired extraction_mode and pos_mode
7618 are the same as for a register operation, since at present we don't
7619 have named patterns for aligned memory structures. */
7623 {
7627 }
7629 /* Never narrow an object, since that might not be safe. */
7637 else
7638 {
7639 /* Be careful not to go beyond the extracted object and maintain the
7640 natural alignment of the memory. */
7645 }
7650 {
7651 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7652 BITS_BIG_ENDIAN style. If position is constant, compute new
7653 position. Otherwise, build subtraction.
7654 Note that POS is relative to the mode of the original argument.
7655 If it's a MEM we need to recompute POS relative to that.
7656 However, if we're extracting from (or inserting into) a register,
7657 we want to recompute POS relative to wanted_inner_mode. */
7664 else
7665 pos_rtx
7668 pos_rtx);
7669 /* POS may be less than 0 now, but we check for that below.
7670 Note that it can only be less than 0 if !MEM_P (inner). */
7671 }
7673 /* If INNER has a wider mode, and this is a constant extraction, try to
7674 make it smaller and adjust the byte to point to the byte containing
7675 the value. */
7678 && ! pos_rtx
7683 {
7686 /* The computations below will be correct if the machine is big
7687 endian in both bits and bytes or little endian in bits and bytes.
7688 If it is mixed, we must adjust. */
7690 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7691 adjust OFFSET to compensate. */
7696 /* We can now move to the desired byte. */
7707 }
7709 /* If INNER is not memory, get it into the proper mode. If we are changing
7710 its mode, POS must be a constant and smaller than the size of the new
7711 mode. */
7713 {
7714 /* On the LHS, don't create paradoxical subregs implicitely truncating
7715 the register unless TRULY_NOOP_TRUNCATION. */
7718 wanted_inner_mode))
7730 pos_rtx
7732 ? HOST_WIDE_INT_M1U
7736 }
7738 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7739 have to zero extend. Otherwise, we can just use a SUBREG.
7741 We dealt with constant rtxes earlier, so pos_rtx cannot
7742 have VOIDmode at this point. */
7746 {
7750 /* If we know that no extraneous bits are set, and that the high
7751 bit is not set, convert extraction to cheaper one - either
7752 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7753 cases. */
7761 {
7765 /* Prefer ZERO_EXTENSION, since it gives more information to
7766 backends. */
7770 }
7772 }
7774 /* Make POS_RTX unless we already have it and it is correct. If we don't
7775 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7776 be a CONST_INT. */
7783 /* Make the required operation. See if we can use existing rtx. */
7790 }
7791 \f
7792 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7793 with any other operations in X. Return X without that shift if so. */
7795 static rtx
7797 {
7800 rtx tem;
7803 {
7805 /* This is the shift itself. If it is wide enough, we will return
7806 either the value being shifted if the shift count is equal to
7807 COUNT or a shift for the difference. */
7821 /* If we can safely shift this constant and we find the inner shift,
7822 make a new operation. */
7827 {
7831 }
7836 }
7839 }
7840 \f
7841 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7842 level of the expression and MODE is its mode. IN_CODE is as for
7843 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7844 that should be used when recursing on operands of *X_PTR.
7846 There are two possible actions:
7848 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7849 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7851 - Return a new rtx, which the caller returns directly. */
7853 static rtx
7857 {
7865 rtx tem;
7866 scalar_int_mode inner_mode;
7870 {
7873 }
7875 /* Process depending on the code of this operation. If NEW is set
7876 nonzero, it will be returned. */
7879 {
7881 /* Convert shifts by constants into multiplications if inside
7882 an address. */
7886 {
7892 {
7895 }
7898 }
7907 {
7911 }
7914 {
7918 mode));
7920 }
7921 else
7922 {
7925 }
7935 {
7939 }
7942 {
7946 mode));
7948 }
7949 else
7950 {
7954 }
7957 /* If the second operand is not a constant, we can't do anything
7958 with it. */
7962 /* If the constant is a power of two minus one and the first operand
7963 is a logical right shift, make an extraction. */
7966 {
7970 }
7972 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7979 {
7986 /* If we narrowed the mode when dropping the subreg, then we lose. */
7990 /* If that didn't give anything, see if the AND simplifies on
7991 its own. */
7993 {
7997 }
7998 }
7999 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8005 {
8006 /* Apply the distributive law, and then try to make extractions. */
8013 }
8015 /* If we are have (and (rotate X C) M) and C is larger than the number
8016 of bits in M, this is an extraction. */
8022 {
8028 }
8030 /* On machines without logical shifts, if the operand of the AND is
8031 a logical shift and our mask turns off all the propagated sign
8032 bits, we can replace the logical shift with an arithmetic shift. */
8040 {
8047 make_compound_operation
8050 }
8052 /* If the constant is one less than a power of two, this might be
8053 representable by an extraction even if no shift is present.
8054 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8055 we are in a COMPARE. */
8059 next_code),
8062 /* If we are in a comparison and this is an AND with a power of two,
8063 convert this into the appropriate bit extract. */
8069 next_code),
8072 /* If the one operand is a paradoxical subreg of a register or memory and
8073 the constant (limited to the smaller mode) has only zero bits where
8074 the sub expression has known zero bits, this can be expressed as
8075 a zero_extend. */
8077 {
8078 rtx sub;
8084 {
8088 /* original AND constant with all the known zero bits set */
8091 {
8096 }
8097 }
8098 }
8103 /* If the sign bit is known to be zero, replace this with an
8104 arithmetic shift. */
8109 {
8112 next_code),
8115 }
8117 /* fall through */
8123 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8124 this is a SIGN_EXTRACT. */
8131 {
8138 }
8140 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8141 If so, try to merge the shifts into a SIGN_EXTEND. We could
8142 also do this for some cases of SIGN_EXTRACT, but it doesn't
8143 seem worth the effort; the case checked for occurs on Alpha. */
8160 /* Call ourselves recursively on the inner expression. If we are
8161 narrowing the object and it has a different RTL code from
8162 what it originally did, do this SUBREG as a force_to_mode. */
8163 {
8167 /* If the SUBREG is masking of a logical right shift,
8168 make an extraction. */
8175 {
8184 }
8186 /* If in_code is COMPARE, it isn't always safe to pass it through
8187 to the recursive make_compound_operation call. */
8191 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8192 is (const_int 0), rather than
8193 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8194 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8195 for non-equality comparisons against 0 is not equivalent
8196 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8206 simplified
8214 {
8215 rtx newer
8218 /* If we have something other than a SUBREG, we might have
8219 done an expansion, so rerun ourselves. */
8223 /* force_to_mode can expand compounds. If it just re-expanded the
8224 compound, use gen_lowpart to convert to the desired mode. */
8226 /* Likewise if it re-expanded the compound only partially.
8227 This happens for SUBREG of ZERO_EXTRACT if they extract
8228 the same number of bits. */
8237 }
8241 }
8246 }
8252 }
8254 /* Look at the expression rooted at X. Look for expressions
8255 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8256 Form these expressions.
8258 Return the new rtx, usually just X.
8260 Also, for machines like the VAX that don't have logical shift insns,
8261 try to convert logical to arithmetic shift operations in cases where
8262 they are equivalent. This undoes the canonicalizations to logical
8263 shifts done elsewhere.
8265 We try, as much as possible, to re-use rtl expressions to save memory.
8267 IN_CODE says what kind of expression we are processing. Normally, it is
8268 SET. In a memory address it is MEM. When processing the arguments of
8269 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8270 precisely it is an equality comparison against zero. */
8272 rtx
8274 {
8281 /* Select the code to be used in recursive calls. Once we are inside an
8282 address, we stay there. If we have a comparison, set to COMPARE,
8283 but once inside, go back to our default of SET. */
8290 scalar_int_mode mode;
8292 {
8298 }
8300 /* Now recursively process each operand of this operation. We need to
8301 handle ZERO_EXTEND specially so that we don't lose track of the
8302 inner mode. */
8304 {
8312 }
8317 {
8320 }
8323 {
8326 }
8330 }
8331 \f
8332 /* Given M see if it is a value that would select a field of bits
8333 within an item, but not the entire word. Return -1 if not.
8334 Otherwise, return the starting position of the field, where 0 is the
8335 low-order bit.
8337 *PLEN is set to the length of the field. */
8339 static int
8341 {
8342 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8347 /* Now shift off the low-order zero bits and see if we have a
8348 power of two minus 1. */
8356 }
8357 \f
8358 /* If X refers to a register that equals REG in value, replace these
8359 references with REG. */
8360 static rtx
8362 {
8370 {
8403 /* FALLTHRU */
8407 {
8411 else
8413 }
8415 /* fall through */
8422 {
8425 {
8427 {
8430 }
8432 }
8433 }
8435 {
8438 {
8441 {
8443 {
8446 }
8448 }
8449 }
8450 }
8453 }
8456 }
8458 /* Return X converted to MODE. If the value is already truncated to
8459 MODE we can just return a subreg even though in the general case we
8460 would need an explicit truncation. */
8462 static rtx
8464 {
8469 {
8470 /* Bit-cast X into an integer mode. */
8475 }
8478 }
8480 /* See if X can be simplified knowing that we will only refer to it in
8481 MODE and will only refer to those bits that are nonzero in MASK.
8482 If other bits are being computed or if masking operations are done
8483 that select a superset of the bits in MASK, they can sometimes be
8484 ignored.
8486 Return a possibly simplified expression, but always convert X to
8487 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8489 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8490 are all off in X. This is used when X will be complemented, by either
8491 NOT, NEG, or XOR. */
8493 static rtx
8496 {
8499 machine_mode op_mode;
8502 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8503 code below will do the wrong thing since the mode of such an
8504 expression is VOIDmode.
8506 Also do nothing if X is a CLOBBER; this can happen if X was
8507 the return value from a call to gen_lowpart. */
8511 /* We want to perform the operation in its present mode unless we know
8512 that the operation is valid in MODE, in which case we do the operation
8513 in MODE. */
8518 /* It is not valid to do a right-shift in a narrower mode
8519 than the one it came in with. */
8524 /* Truncate MASK to fit OP_MODE. */
8528 /* Determine what bits of X are guaranteed to be (non)zero. */
8531 /* If none of the bits in X are needed, return a zero. */
8535 /* If X is a CONST_INT, return a new one. Do this here since the
8536 test below will fail. */
8538 {
8541 else
8542 {
8545 }
8546 }
8548 /* If X is narrower than MODE and we want all the bits in X's mode, just
8549 get X in the proper mode. */
8554 /* We can ignore the effect of a SUBREG if it narrows the mode or
8555 if the constant masks to zero all the bits the mode doesn't have. */
8568 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8569 integer too. */
8575 }
8577 /* Subroutine of force_to_mode that handles cases in which both X and
8578 the result are scalar integers. MODE is the mode of the result,
8579 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8580 is preferred for simplified versions of X. The other arguments
8581 are as for force_to_mode. */
8583 static rtx
8587 {
8593 /* When we have an arithmetic operation, or a shift whose count we
8594 do not know, we need to assume that all bits up to the highest-order
8595 bit in MASK will be needed. This is how we form such a mask. */
8598 else
8603 {
8605 /* If X is a (clobber (const_int)), return it since we know we are
8606 generating something that won't match. */
8619 /* Similarly for a truncate. */
8623 /* If this is an AND with a constant, convert it into an AND
8624 whose constant is the AND of that constant with MASK. If it
8625 remains an AND of MASK, delete it since it is redundant. */
8628 {
8633 /* If X is still an AND, see if it is an AND with a mask that
8634 is just some low-order bits. If so, and it is MASK, we don't
8635 need it. */
8641 /* If it remains an AND, try making another AND with the bits
8642 in the mode mask that aren't in MASK turned on. If the
8643 constant in the AND is wide enough, this might make a
8644 cheaper constant. */
8649 {
8650 unsigned HOST_WIDE_INT cval
8652 rtx y;
8659 }
8662 }
8667 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8668 low-order bits (as in an alignment operation) and FOO is already
8669 aligned to that boundary, mask C1 to that boundary as well.
8670 This may eliminate that PLUS and, later, the AND. */
8672 {
8676 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8677 number, sign extend it. */
8690 }
8692 /* fall through */
8695 /* Substituting into the operands of a widening MULT is not likely to
8696 create RTL matching a machine insn. */
8706 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8707 most significant bit in MASK since carries from those bits will
8708 affect the bits we are interested in. */
8713 /* If X is (minus C Y) where C's least set bit is larger than any bit
8714 in the mask, then we may replace with (neg Y). */
8717 {
8720 }
8722 /* Similarly, if C contains every bit in the fuller_mask, then we may
8723 replace with (not Y). */
8726 {
8729 }
8736 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8737 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8738 operation which may be a bitfield extraction. Ensure that the
8739 constant we form is not wider than the mode of X. */
8751 {
8754 xmode);
8760 }
8762 binop:
8763 /* For most binary operations, just propagate into the operation and
8764 change the mode if we have an operation of that mode. */
8769 /* If we ended up truncating both operands, truncate the result of the
8770 operation instead. */
8773 {
8776 }
8782 {
8785 }
8789 /* For left shifts, do the same, but just for the first operand.
8790 However, we cannot do anything with shifts where we cannot
8791 guarantee that the counts are smaller than the size of the mode
8792 because such a count will have a different meaning in a
8793 wider mode. */
8803 /* If the shift count is a constant and we can do arithmetic in
8804 the mode of the shift, refine which bits we need. Otherwise, use the
8805 conservative form of the mask. */
8811 else
8819 {
8822 }
8826 /* Here we can only do something if the shift count is a constant,
8827 this shift constant is valid for the host, and we can do arithmetic
8828 in OP_MODE. */
8834 {
8838 /* Select the mask of the bits we need for the shift operand. */
8841 /* We can only change the mode of the shift if we can do arithmetic
8842 in the mode of the shift and INNER_MASK is no wider than the
8843 width of X's mode. */
8850 {
8853 }
8854 }
8856 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8857 shift and AND produces only copies of the sign bit (C2 is one less
8858 than a power of two), we can do this with just a shift. */
8862 /* The shift puts one of the sign bit copies in the least significant
8863 bit. */
8868 /* Number of bits left after the shift must be more than the mask
8869 needs. */
8872 /* Must be more sign bit copies than the mask needs. */
8882 /* If we are just looking for the sign bit, we don't need this shift at
8883 all, even if it has a variable count. */
8887 /* If this is a shift by a constant, get a mask that contains those bits
8888 that are not copies of the sign bit. We then have two cases: If
8889 MASK only includes those bits, this can be a logical shift, which may
8890 allow simplifications. If MASK is a single-bit field not within
8891 those bits, we are requesting a copy of the sign bit and hence can
8892 shift the sign bit to the appropriate location. */
8896 {
8900 /* If the considered data is wider than HOST_WIDE_INT, we can't
8901 represent a mask for all its bits in a single scalar.
8902 But we only care about the lower bits, so calculate these. */
8905 {
8908 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8909 is the number of bits a full-width mask would have set.
8910 We need only shift if these are fewer than nonzero can
8911 hold. If not, we must keep all bits set in nonzero. */
8916 + HOST_BITS_PER_WIDE_INT
8918 }
8919 else
8920 {
8923 }
8926 {
8931 }
8934 {
8935 x = simplify_shift_const
8941 }
8942 }
8944 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8945 even if the shift count isn't a constant. */
8949 shiftrt:
8951 /* If this is a zero- or sign-extension operation that just affects bits
8952 we don't care about, remove it. Be sure the call above returned
8953 something that is still a shift. */
8963 next_select);
8969 /* If the shift count is constant and we can do computations
8970 in the mode of X, compute where the bits we care about are.
8971 Otherwise, we can't do anything. Don't change the mode of
8972 the shift or propagate MODE into the shift, though. */
8975 {
8984 }
8988 /* If we just want the low-order bit, the NEG isn't needed since it
8989 won't change the low-order bit. */
8993 /* We need any bits less significant than the most significant bit in
8994 MASK since carries from those bits will affect the bits we are
8995 interested in. */
9000 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9001 same as the XOR case above. Ensure that the constant we form is not
9002 wider than the mode of X. */
9010 {
9017 }
9019 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9020 use the full mask inside the NOT. */
9023 unop:
9026 next_select));
9028 {
9031 }
9035 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9036 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9037 which is equal to STORE_FLAG_VALUE. */
9049 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9050 written in a narrower mode. We play it safe and do not do so. */
9066 }
9068 /* Ensure we return a value of the proper mode. */
9070 }
9071 \f
9072 /* Return nonzero if X is an expression that has one of two values depending on
9073 whether some other value is zero or nonzero. In that case, we return the
9074 value that is being tested, *PTRUE is set to the value if the rtx being
9075 returned has a nonzero value, and *PFALSE is set to the other alternative.
9077 If we return zero, we set *PTRUE and *PFALSE to X. */
9079 static rtx
9081 {
9086 scalar_int_mode int_mode;
9088 /* If we are comparing a value against zero, we are done. */
9091 {
9095 }
9097 /* If this is a unary operation whose operand has one of two values, apply
9098 our opcode to compute those values. */
9101 {
9106 }
9108 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9109 make can't possibly match and would suppress other optimizations. */
9111 ;
9113 /* If this is a binary operation, see if either side has only one of two
9114 values. If either one does or if both do and they are conditional on
9115 the same value, compute the new true and false values. */
9117 {
9125 {
9126 /* Try to enable a simplification by undoing work done by
9127 if_then_else_cond if it converted a REG into something more
9128 complex. */
9130 {
9133 }
9134 else
9135 {
9138 }
9139 }
9143 {
9144 /* If if_then_else_cond returned zero, then true/false are the
9145 same rtl. We must copy one of them to prevent invalid rtl
9146 sharing. */
9153 {
9158 }
9159 else
9160 {
9163 }
9166 }
9168 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9169 operands is zero when the other is nonzero, and vice-versa,
9170 and STORE_FLAG_VALUE is 1 or -1. */
9176 {
9193 {
9200 const_true_rtx);
9202 }
9203 }
9205 /* Similarly for MULT, AND and UMIN, except that for these the result
9206 is always zero. */
9210 {
9224 {
9227 }
9228 }
9229 }
9232 {
9233 /* If we have IF_THEN_ELSE already, extract the condition and
9234 canonicalize it if it is NE or EQ. */
9240 {
9243 }
9244 else
9246 }
9248 /* If X is a SUBREG, we can narrow both the true and false values
9249 if the inner expression, if there is a condition. */
9253 {
9259 {
9263 }
9264 }
9266 /* If X is a constant, this isn't special and will cause confusions
9267 if we treat it as such. Likewise if it is equivalent to a constant. */
9270 ;
9272 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9273 will be least confusing to the rest of the compiler. */
9275 {
9278 }
9280 /* If X is known to be either 0 or -1, those are the true and
9281 false values when testing X. */
9286 {
9289 }
9291 /* Likewise for 0 or a single bit. */
9294 {
9297 }
9299 /* Otherwise fail; show no condition with true and false values the same. */
9302 }
9303 \f
9304 /* Return the value of expression X given the fact that condition COND
9305 is known to be true when applied to REG as its first operand and VAL
9306 as its second. X is known to not be shared and so can be modified in
9307 place.
9309 We only handle the simplest cases, and specifically those cases that
9310 arise with IF_THEN_ELSE expressions. */
9312 static rtx
9314 {
9322 /* If either operand of the condition is a floating point value,
9323 then we have to avoid collapsing an EQ comparison. */
9333 /* If X is (abs REG) and we know something about REG's relationship
9334 with zero, we may be able to simplify this. */
9338 {
9347 }
9349 /* The only other cases we handle are MIN, MAX, and comparisons if the
9350 operands are the same as REG and VAL. */
9353 {
9355 {
9358 }
9361 {
9363 {
9371 else
9373 }
9376 {
9379 /* Do not reverse the condition when it is NE or EQ.
9380 This is because we cannot conclude anything about
9381 the value of 'SMAX (x, y)' when x is not equal to y,
9382 but we can when x equals y. */
9388 {
9399 }
9400 }
9401 }
9402 }
9404 {
9409 {
9410 /* We must simplify subreg here, before we lose track of the
9411 original inner_mode. */
9416 else
9418 }
9421 }
9422 /* We don't have to handle SIGN_EXTEND here, because even in the
9423 case of replacing something with a modeless CONST_INT, a
9424 CONST_INT is already (supposed to be) a valid sign extension for
9425 its narrower mode, which implies it's already properly
9426 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9427 story is different. */
9429 {
9434 {
9435 /* We must simplify the zero_extend here, before we lose
9436 track of the original inner_mode. */
9441 else
9443 }
9446 }
9450 {
9457 }
9460 }
9461 \f
9462 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9463 assignment as a field assignment. */
9465 static int
9467 {
9469 {
9474 /* For big endian, adjust the memory offset. */
9479 else
9481 }
9489 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9490 Note that all SUBREGs of MEM are paradoxical; otherwise they
9491 would have been rewritten. */
9504 /* We used to see if get_last_value of X and Y were the same but that's
9505 not correct. In one direction, we'll cause the assignment to have
9506 the wrong destination and in the case, we'll import a register into this
9507 insn that might have already have been dead. So fail if none of the
9508 above cases are true. */
9510 }
9511 \f
9512 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9513 Return that assignment if so.
9515 We only handle the most common cases. */
9517 static rtx
9519 {
9522 rtx assign;
9524 HOST_WIDE_INT c1;
9525 HOST_WIDE_INT pos;
9527 rtx other;
9529 /* All the rules in this function are specific to scalar integers. */
9530 scalar_int_mode mode;
9534 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9535 a clear of a one-bit field. We will have changed it to
9536 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9537 for a SUBREG. */
9543 {
9549 }
9559 {
9566 }
9568 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9569 one-bit field. */
9573 {
9579 }
9581 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9582 SRC is an AND with all bits of that field set, then we can discard
9583 the AND. */
9588 {
9595 else
9598 /* Complete overlap. We can remove the source AND. */
9602 /* Partial overlap. We can reduce the source AND. */
9604 {
9608 }
9609 }
9611 /* The other case we handle is assignments into a constant-position
9612 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9613 a mask that has all one bits except for a group of zero bits and
9614 OTHER is known to have zeros where C1 has ones, this is such an
9615 assignment. Compute the position and length from C1. Shift OTHER
9616 to the appropriate position, force it to the required mode, and
9617 make the extraction. Check for the AND in both operands. */
9619 /* One or more SUBREGs might obscure the constant-position field
9620 assignment. The first one we are likely to encounter is an outer
9621 narrowing SUBREG, which we can just strip for the purposes of
9622 identifying the constant-field assignment. */
9639 /* The second SUBREG that might get in the way is a paradoxical
9640 SUBREG around the first operand of the AND. We want to
9641 pretend the operand is as wide as the destination here. We
9642 do this by adjusting the MEM to wider mode for the sole
9643 purpose of the call to rtx_equal_for_field_assignment_p. Also
9644 note this trick only works for MEMs. */
9656 /* The second SUBREG that might get in the way is a paradoxical
9657 SUBREG around the first operand of the AND. We want to
9658 pretend the operand is as wide as the destination here. We
9659 do this by adjusting the MEM to wider mode for the sole
9660 purpose of the call to rtx_equal_for_field_assignment_p. Also
9661 note this trick only works for MEMs. */
9669 else
9683 /* The mode to use for the source is the mode of the assignment, or of
9684 what is inside a possible STRICT_LOW_PART. */
9688 /* Shift OTHER right POS places and make it the source, restricting it
9689 to the proper length and mode. */
9693 dest);
9695 len >= HOST_BITS_PER_WIDE_INT
9696 ? HOST_WIDE_INT_M1U
9700 /* If SRC is masked by an AND that does not make a difference in
9701 the value being stored, strip it. */
9712 }
9713 \f
9714 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9715 if so. */
9717 static rtx
9719 {
9723 rtx tem;
9725 /* Distributivity is not true for floating point as it can change the
9726 value. So we don't do it unless -funsafe-math-optimizations. */
9731 /* The outer operation can only be one of the following: */
9739 /* If either operand is a primitive we can't do anything, so get out
9740 fast. */
9750 /* See if the inner and outer operations distribute. */
9752 {
9757 /* These all distribute except over PLUS. */
9768 /* This is also a multiply, so it distributes over everything. */
9771 /* This used to handle SUBREG, but this turned out to be counter-
9772 productive, since (subreg (op ...)) usually is not handled by
9773 insn patterns, and this "optimization" therefore transformed
9774 recognizable patterns into unrecognizable ones. Therefore the
9775 SUBREG case was removed from here.
9777 It is possible that distributing SUBREG over arithmetic operations
9778 leads to an intermediate result than can then be optimized further,
9779 e.g. by moving the outer SUBREG to the other side of a SET as done
9780 in simplify_set. This seems to have been the original intent of
9781 handling SUBREGs here.
9783 However, with current GCC this does not appear to actually happen,
9784 at least on major platforms. If some case is found where removing
9785 the SUBREG case here prevents follow-on optimizations, distributing
9786 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9790 }
9792 /* Set LHS and RHS to the inner operands (A and B in the example
9793 above) and set OTHER to the common operand (C in the example).
9794 There is only one way to do this unless the inner operation is
9795 commutative. */
9807 else
9810 /* Form the new inner operation, seeing if it simplifies first. */
9813 /* There is one exception to the general way of distributing:
9814 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9816 {
9819 }
9821 /* We may be able to continuing distributing the result, so call
9822 ourselves recursively on the inner operation before forming the
9823 outer operation, which we return. */
9826 }
9828 /* See if X is of the form (* (+ A B) C), and if so convert to
9829 (+ (* A C) (* B C)) and try to simplify.
9831 Most of the time, this results in no change. However, if some of
9832 the operands are the same or inverses of each other, simplifications
9833 will result.
9835 For example, (and (ior A B) (not B)) can occur as the result of
9836 expanding a bit field assignment. When we apply the distributive
9837 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9838 which then simplifies to (and (A (not B))).
9840 Note that no checks happen on the validity of applying the inverse
9841 distributive law. This is pointless since we can do it in the
9842 few places where this routine is called.
9844 N is the index of the term that is decomposed (the arithmetic operation,
9845 i.e. (+ A B) in the first example above). !N is the index of the term that
9846 is distributed, i.e. of C in the first example above. */
9847 static rtx
9849 {
9850 machine_mode mode;
9854 /* Distributivity is not true for floating point as it can change the
9855 value. So we don't do it unless -funsafe-math-optimizations. */
9872 /* Special case (and (xor B C) (not A)), which is equivalent to
9873 (xor (ior A B) (ior A C)) */
9875 {
9878 }
9881 {
9882 /* Distribute the second term. */
9885 }
9886 else
9887 {
9888 /* Distribute the first term. */
9891 }
9901 }
9902 \f
9903 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9904 in MODE. Return an equivalent form, if different from (and VAROP
9905 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9907 static rtx
9910 {
9913 rtx orig_varop;
9921 /* Simplify VAROP knowing that we will be only looking at some of the
9922 bits in it.
9924 Note by passing in CONSTOP, we guarantee that the bits not set in
9925 CONSTOP are not significant and will never be examined. We must
9926 ensure that is the case by explicitly masking out those bits
9927 before returning. */
9930 /* If VAROP is a CLOBBER, we will fail so return it. */
9934 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9935 to VAROP and return the new constant. */
9939 /* See what bits may be nonzero in VAROP. Unlike the general case of
9940 a call to nonzero_bits, here we don't care about bits outside
9941 MODE. */
9945 /* Turn off all bits in the constant that are known to already be zero.
9946 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9947 which is tested below. */
9951 /* If we don't have any bits left, return zero. */
9955 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9956 a power of two, we can replace this with an ASHIFT. */
9961 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9962 or XOR, then try to apply the distributive law. This may eliminate
9963 operations if either branch can be simplified because of the AND.
9964 It may also make some cases more complex, but those cases probably
9965 won't match a pattern either with or without this. */
9968 return
9969 gen_lowpart
9971 apply_distributive_law
9976 constop),
9980 constop))));
9982 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9983 the AND and see if one of the operands simplifies to zero. If so, we
9984 may eliminate it. */
9988 {
9997 }
9999 /* Make a SUBREG if necessary. If we can't make it, fail. */
10004 /* If we are only masking insignificant bits, return VAROP. */
10011 /* Otherwise, return an AND. */
10013 }
10016 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10017 in MODE.
10019 Return an equivalent form, if different from X. Otherwise, return X. If
10020 X is zero, we are to always construct the equivalent form. */
10022 static rtx
10025 {
10036 }
10037 \f
10038 /* Given a REG, X, compute which bits in X can be nonzero.
10039 We don't care about bits outside of those defined in MODE.
10041 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10042 a shift, AND, or zero_extract, we can do better. */
10044 static rtx
10046 const_rtx known_x ATTRIBUTE_UNUSED,
10047 machine_mode known_mode ATTRIBUTE_UNUSED,
10050 {
10051 rtx tem;
10054 /* If X is a register whose nonzero bits value is current, use it.
10055 Otherwise, if X is a register whose value we can find, use that
10056 value. Otherwise, use the previously-computed global nonzero bits
10057 for this register. */
10071 && !REGNO_REG_SET_P
10074 {
10075 /* Note that, even if the precision of last_set_mode is lower than that
10076 of mode, record_value_for_reg invoked nonzero_bits on the register
10077 with nonzero_bits_mode (because last_set_mode is necessarily integral
10078 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10079 are all valid, hence in mode too since nonzero_bits_mode is defined
10080 to the largest HWI_COMPUTABLE_MODE_P mode. */
10083 }
10087 {
10093 }
10096 {
10100 /* We don't know anything about the upper bits. */
10104 }
10107 }
10109 /* Return the number of bits at the high-order end of X that are known to
10110 be equal to the sign bit. X will be used in mode MODE; if MODE is
10111 VOIDmode, X will be used in its own mode. The returned value will always
10112 be between 1 and the number of bits in MODE. */
10114 static rtx
10116 const_rtx known_x ATTRIBUTE_UNUSED,
10117 machine_mode known_mode
10118 ATTRIBUTE_UNUSED,
10121 {
10122 rtx tem;
10135 && !REGNO_REG_SET_P
10138 {
10141 }
10152 }
10153 \f
10154 /* Return the number of "extended" bits there are in X, when interpreted
10155 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10156 unsigned quantities, this is the number of high-order zero bits.
10157 For signed quantities, this is the number of copies of the sign bit
10158 minus 1. In both case, this function returns the number of "spare"
10159 bits. For example, if two quantities for which this function returns
10160 at least 1 are added, the addition is known not to overflow.
10162 This function will always return 0 unless called during combine, which
10163 implies that it must be called from a define_split. */
10165 unsigned int
10167 {
10171 scalar_int_mode int_mode;
10179 }
10181 /* This function is called from `simplify_shift_const' to merge two
10182 outer operations. Specifically, we have already found that we need
10183 to perform operation *POP0 with constant *PCONST0 at the outermost
10184 position. We would now like to also perform OP1 with constant CONST1
10185 (with *POP0 being done last).
10187 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10188 the resulting operation. *PCOMP_P is set to 1 if we would need to
10189 complement the innermost operand, otherwise it is unchanged.
10191 MODE is the mode in which the operation will be done. No bits outside
10192 the width of this mode matter. It is assumed that the width of this mode
10193 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10195 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10196 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10197 result is simply *PCONST0.
10199 If the resulting operation cannot be expressed as one operation, we
10200 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10202 static int
10203 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10204 {
10211 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10215 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10216 if OP0 is SET. */
10225 {
10227 {
10245 }
10246 }
10248 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10252 /* If the two constants aren't the same, we can't do anything. The
10253 remaining six cases can all be done. */
10257 else
10259 {
10262 /* (a & b) | b == b */
10265 /* (a ^ b) | b == a | b */
10266 {;}
10271 /* (a & b) ^ b == (~a) & b */
10274 /* (a | b) ^ b == a & ~b */
10280 /* (a | b) & b == b */
10283 /* (a ^ b) & b) == (~a) & b */
10288 }
10290 /* Check for NO-OP cases. */
10303 /* ??? Slightly redundant with the above mask, but not entirely.
10304 Moving this above means we'd have to sign-extend the mode mask
10305 for the final test. */
10310 }
10311 \f
10312 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10313 the shift in. The original shift operation CODE is performed on OP in
10314 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10315 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10316 result of the shift is subject to operation OUTER_CODE with operand
10317 OUTER_CONST. */
10319 static machine_mode
10323 {
10326 /* In general we can't perform in wider mode for right shift and rotate. */
10328 {
10330 /* We can still widen if the bits brought in from the left are identical
10331 to the sign bit of ORIG_MODE. */
10339 /* Similarly here but with zero bits. */
10344 /* We can also widen if the bits brought in will be masked off. This
10345 operation is performed in ORIG_MODE. */
10347 {
10353 }
10354 /* fall through */
10364 }
10365 }
10367 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10368 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10369 if we cannot simplify it. Otherwise, return a simplified value.
10371 The shift is normally computed in the widest mode we find in VAROP, as
10372 long as it isn't a different number of words than RESULT_MODE. Exceptions
10373 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10375 static rtx
10378 {
10383 machine_mode shift_mode;
10385 unsigned int mode_words
10387 /* We form (outer_op (code varop count) (outer_const)). */
10393 /* Make sure and truncate the "natural" shift on the way in. We don't
10394 want to do this inside the loop as it makes it more difficult to
10395 combine shifts. */
10399 /* If we were given an invalid count, don't do anything except exactly
10400 what was requested. */
10407 /* Unless one of the branches of the `if' in this loop does a `continue',
10408 we will `break' the loop after the `if'. */
10411 {
10412 /* If we have an operand of (clobber (const_int 0)), fail. */
10416 /* Convert ROTATERT to ROTATE. */
10418 {
10422 }
10426 {
10427 /* We only change the modes of scalar shifts. */
10433 }
10435 scalar_int_mode shift_unit_mode
10438 /* Handle cases where the count is greater than the size of the mode
10439 minus 1. For ASHIFT, use the size minus one as the count (this can
10440 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10441 take the count modulo the size. For other shifts, the result is
10442 zero.
10444 Since these shifts are being produced by the compiler by combining
10445 multiple operations, each of which are defined, we know what the
10446 result is supposed to be. */
10449 {
10454 else
10455 {
10456 /* We can't simply return zero because there may be an
10457 outer op. */
10461 }
10462 }
10464 /* If we discovered we had to complement VAROP, leave. Making a NOT
10465 here would cause an infinite loop. */
10470 {
10471 /* An arithmetic right shift of a quantity known to be -1 or 0
10472 is a no-op. */
10476 {
10479 }
10481 /* If we are doing an arithmetic right shift and discarding all but
10482 the sign bit copies, this is equivalent to doing a shift by the
10483 bitsize minus one. Convert it into that shift because it will
10484 often allow other simplifications. */
10491 /* We simplify the tests below and elsewhere by converting
10492 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10493 `make_compound_operation' will convert it to an ASHIFTRT for
10494 those machines (such as VAX) that don't have an LSHIFTRT. */
10499 shift_unit_mode)))
10511 }
10514 {
10521 {
10524 }
10528 /* The following rules apply only to scalars. */
10533 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10534 minus the width of a smaller mode, we can do this with a
10535 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10542 {
10551 }
10555 /* The following rules apply only to scalars. */
10561 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10562 the same number of words as what we've seen so far. Then store
10563 the widest mode in MODE. */
10569 == mode_words
10571 {
10576 }
10580 /* Some machines use MULT instead of ASHIFT because MULT
10581 is cheaper. But it is still better on those machines to
10582 merge two shifts into one. */
10585 {
10586 varop
10592 }
10596 /* Similar, for when divides are cheaper. */
10599 {
10600 varop
10606 }
10610 /* If we are extracting just the sign bit of an arithmetic
10611 right shift, that shift is not needed. However, the sign
10612 bit of a wider mode may be different from what would be
10613 interpreted as the sign bit in a narrower mode, so, if
10614 the result is narrower, don't discard the shift. */
10619 {
10622 }
10624 /* fall through */
10629 /* The following rules apply only to scalars. */
10636 /* Here we have two nested shifts. The result is usually the
10637 AND of a new shift with a mask. We compute the result below. */
10643 {
10647 rtx mask_rtx;
10649 /* We have one common special case. We can't do any merging if
10650 the inner code is an ASHIFTRT of a smaller mode. However, if
10651 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10652 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10653 we can convert it to
10654 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10655 This simplifies certain SIGN_EXTEND operations. */
10659 {
10660 /* C3 has the low-order C1 bits zero. */
10672 }
10674 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10675 than C1 high-order bits equal to the sign bit, we can convert
10676 this to either an ASHIFT or an ASHIFTRT depending on the
10677 two counts.
10679 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10685 {
10689 {
10692 }
10695 }
10697 /* There are some cases we can't do. If CODE is ASHIFTRT,
10698 we can only do this if FIRST_CODE is also ASHIFTRT.
10700 We can't do the case when CODE is ROTATE and FIRST_CODE is
10701 ASHIFTRT.
10703 If the mode of this shift is not the mode of the outer shift,
10704 we can't do this if either shift is a right shift or ROTATE.
10706 Finally, we can't do any of these if the mode is too wide
10707 unless the codes are the same.
10709 Handle the case where the shift codes are the same
10710 first. */
10713 {
10722 }
10733 /* To compute the mask to apply after the shift, shift the
10734 nonzero bits of the inner shift the same way the
10735 outer shift will. */
10738 int_result_mode);
10740 mask_rtx
10744 /* Give up if we can't compute an outer operation to use. */
10752 /* If the shifts are in the same direction, we add the
10753 counts. Otherwise, we subtract them. */
10757 else
10760 /* If COUNT is positive, the new shift is usually CODE,
10761 except for the two exceptions below, in which case it is
10762 FIRST_CODE. If the count is negative, FIRST_CODE should
10763 always be used */
10773 }
10775 /* If we have (A << B << C) for any shift, we can convert this to
10776 (A << C << B). This wins if A is a constant. Only try this if
10777 B is not a constant. */
10782 {
10783 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10784 sure the result will be masked. See PR70222. */
10792 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10793 up outer sign extension (often left and right shift) is
10794 hardly more efficient than the original. See PR70429. */
10804 }
10808 /* The following rules apply only to scalars. */
10812 /* Make this fit the case below. */
10819 /* The following rules apply only to scalars. */
10825 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10826 with C the size of VAROP - 1 and the shift is logical if
10827 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10828 we have an (le X 0) operation. If we have an arithmetic shift
10829 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10830 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10838 {
10841 const0_rtx);
10847 }
10849 /* If we have (shift (logical)), move the logical to the outside
10850 to allow it to possibly combine with another logical and the
10851 shift to combine with another shift. This also canonicalizes to
10852 what a ZERO_EXTRACT looks like. Also, some machines have
10853 (and (shift)) insns. */
10856 /* We can't do this if we have (ashiftrt (xor)) and the
10857 constant has its sign bit set in shift_unit_mode with
10858 shift_unit_mode wider than result_mode. */
10862 shift_unit_mode))
10871 {
10874 }
10876 /* If we can't do that, try to simplify the shift in each arm of the
10877 logical expression, make a new logical expression, and apply
10878 the inverse distributive law. This also can't be done for
10879 (ashiftrt (xor)) where we've widened the shift and the constant
10880 changes the sign bit. */
10885 shift_unit_mode)))
10886 {
10898 }
10902 /* The following rules apply only to scalars. */
10907 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10908 says that the sign bit can be tested, FOO has mode MODE, C is
10909 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10910 that may be nonzero. */
10920 {
10924 }
10928 /* The following rules apply only to scalars. */
10933 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10934 than the number of bits in the mode is equivalent to A. */
10938 {
10942 }
10944 /* NEG commutes with ASHIFT since it is multiplication. Move the
10945 NEG outside to allow shifts to combine. */
10949 {
10952 }
10956 /* The following rules apply only to scalars. */
10961 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10962 is one less than the number of bits in the mode is
10963 equivalent to (xor A 1). */
10970 {
10974 }
10976 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10977 that might be nonzero in BAR are those being shifted out and those
10978 bits are known zero in FOO, we can replace the PLUS with FOO.
10979 Similarly in the other operand order. This code occurs when
10980 we are computing the size of a variable-size array. */
10987 {
10990 }
10998 {
11001 }
11003 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11014 {
11017 }
11019 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11020 signbit', and attempt to change the PLUS to an XOR and move it to
11021 the outer operation as is done above in the AND/IOR/XOR case
11022 leg for shift(logical). See details in logical handling above
11023 for reasoning in doing so. */
11035 {
11038 }
11043 /* The following rules apply only to scalars. */
11048 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11049 with C the size of VAROP - 1 and the shift is logical if
11050 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11051 we have a (gt X 0) operation. If the shift is arithmetic with
11052 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11053 we have a (neg (gt X 0)) operation. */
11062 {
11065 const0_rtx);
11071 }
11075 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11076 if the truncate does not affect the value. */
11083 {
11086 varop_inner
11089 GEN_INT
11094 }
11099 }
11102 }
11106 {
11107 /* We only change the modes of scalar shifts. */
11112 }
11114 /* We have now finished analyzing the shift. The result should be
11115 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11116 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11117 to the result of the shift. OUTER_CONST is the relevant constant,
11118 but we must turn off all bits turned off in the shift. */
11126 /* Make a SUBREG if necessary. If we can't make it, fail. */
11131 /* If we have an outer operation and we just made a shift, it is
11132 possible that we could have simplified the shift were it not
11133 for the outer operation. So try to do the simplification
11134 recursively. */
11138 else
11144 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11145 turn off all the bits that the shift would have turned off. */
11147 /* We only change the modes of scalar shifts. */
11151 /* Do the remainder of the processing in RESULT_MODE. */
11154 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11155 operation. */
11160 {
11170 {
11171 /* This means that we have determined that the result is
11172 equivalent to a constant. This should be rare. */
11175 }
11178 else
11181 }
11184 }
11186 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11187 The result of the shift is RESULT_MODE. If we cannot simplify it,
11188 return X or, if it is NULL, synthesize the expression with
11189 simplify_gen_binary. Otherwise, return a simplified value.
11191 The shift is normally computed in the widest mode we find in VAROP, as
11192 long as it isn't a different number of words than RESULT_MODE. Exceptions
11193 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11195 static rtx
11198 {
11208 }
11210 \f
11211 /* A subroutine of recog_for_combine. See there for arguments and
11212 return value. */
11214 static int
11216 {
11218 rtx pat_without_clobbers;
11226 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11227 we use to indicate that something didn't match. If we find such a
11228 thing, force rejection. */
11242 {
11245 else
11248 }
11250 /* If it isn't, there is the possibility that we previously had an insn
11251 that clobbered some register as a side effect, but the combined
11252 insn doesn't need to do that. So try once more without the clobbers
11253 unless this represents an ASM insn. */
11257 {
11262 {
11265 pos++;
11266 }
11276 {
11279 else
11282 }
11283 }
11290 /* Recognize all noop sets, these will be killed by followup pass. */
11294 /* If we had any clobbers to add, make a new pattern than contains
11295 them. Then check to make sure that all of them are dead. */
11297 {
11307 else
11314 {
11319 {
11323 }
11324 }
11326 }
11330 {
11338 /* Allow targets to reject combined insn. */
11340 {
11343 dump_file);
11345 /* Callers expect recog_for_combine to strip
11346 clobbers from the pattern on failure. */
11351 }
11356 }
11362 }
11364 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11365 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11366 Return whether anything was so changed. */
11368 static bool
11370 {
11376 {
11388 {
11397 else
11401 }
11407 {
11413 }
11418 {
11422 }
11423 else
11429 {
11432 }
11436 }
11443 scalar_int_mode mode;
11449 {
11463 else
11471 }
11474 }
11476 /* Like recog, but we receive the address of a pointer to a new pattern.
11477 We try to match the rtx that the pointer points to.
11478 If that fails, we may try to modify or replace the pattern,
11479 storing the replacement into the same pointer object.
11481 Modifications include deletion or addition of CLOBBERs. If the
11482 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11483 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11484 (and undo if that fails).
11486 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11487 the CLOBBERs are placed.
11489 The value is the final insn code from the pattern ultimately matched,
11490 or -1. */
11492 static int
11494 {
11506 {
11509 {
11513 }
11514 }
11517 {
11522 }
11525 }
11526 \f
11527 /* Like gen_lowpart_general but for use by combine. In combine it
11528 is not possible to create any new pseudoregs. However, it is
11529 safe to create invalid memory addresses, because combine will
11530 try to recognize them and all they will do is make the combine
11531 attempt fail.
11533 If for some reason this cannot do its job, an rtx
11534 (clobber (const_int 0)) is returned.
11535 An insn containing that will not be recognized. */
11537 static rtx
11539 {
11543 rtx result;
11548 /* We can only support MODE being wider than a word if X is a
11549 constant integer or has a mode the same size. */
11554 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11555 won't know what to do. So we will strip off the SUBREG here and
11556 process normally. */
11558 {
11561 /* For use in case we fall down into the address adjustments
11562 further below, we need to adjust the known mode and size of
11563 x; imode and isize, since we just adjusted x. */
11570 }
11578 {
11581 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11582 address. */
11587 /* If we want to refer to something bigger than the original memref,
11588 generate a paradoxical subreg instead. That will force a reload
11589 of the original memref X. */
11596 /* Adjust the address so that the address-after-the-data is
11597 unchanged. */
11602 }
11604 /* If X is a comparison operator, rewrite it in a new mode. This
11605 probably won't match, but may allow further simplifications. */
11609 /* If we couldn't simplify X any other way, just enclose it in a
11610 SUBREG. Normally, this SUBREG won't match, but some patterns may
11611 include an explicit SUBREG or we may simplify it further in combine. */
11612 else
11613 {
11614 rtx res;
11617 {
11622 }
11626 }
11628 fail:
11630 }
11631 \f
11632 /* Try to simplify a comparison between OP0 and a constant OP1,
11633 where CODE is the comparison code that will be tested, into a
11634 (CODE OP0 const0_rtx) form.
11636 The result is a possibly different comparison code to use.
11637 *POP1 may be updated. */
11639 static enum rtx_code
11642 {
11646 /* Get the constant we are comparing against and turn off all bits
11647 not on in our mode. */
11651 /* If we are comparing against a constant power of two and the value
11652 being compared can only have that single bit nonzero (e.g., it was
11653 `and'ed with that bit), we can replace this with a comparison
11654 with zero. */
11662 {
11665 }
11667 /* Similarly, if we are comparing a value known to be either -1 or
11668 0 with -1, change it to the opposite comparison against zero. */
11673 {
11676 }
11678 /* Do some canonicalizations based on the comparison code. We prefer
11679 comparisons against zero and then prefer equality comparisons.
11680 If we can reduce the size of a constant, we will do that too. */
11682 {
11684 /* < C is equivalent to <= (C - 1) */
11686 {
11689 /* ... fall through to LE case below. */
11691 }
11692 else
11696 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11698 {
11701 }
11703 /* If we are doing a <= 0 comparison on a value known to have
11704 a zero sign bit, we can replace this with == 0. */
11714 /* >= C is equivalent to > (C - 1). */
11716 {
11719 /* ... fall through to GT below. */
11721 }
11722 else
11726 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11728 {
11731 }
11733 /* If we are doing a > 0 comparison on a value known to have
11734 a zero sign bit, we can replace this with != 0. */
11744 /* < C is equivalent to <= (C - 1). */
11746 {
11749 /* ... fall through ... */
11750 }
11751 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11755 {
11759 }
11760 else
11764 /* unsigned <= 0 is equivalent to == 0 */
11767 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11771 {
11774 }
11778 /* >= C is equivalent to > (C - 1). */
11780 {
11783 /* ... fall through ... */
11784 }
11786 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11790 {
11794 }
11795 else
11799 /* unsigned > 0 is equivalent to != 0 */
11802 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11806 {
11809 }
11814 }
11818 }
11819 \f
11820 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11821 comparison code that will be tested.
11823 The result is a possibly different comparison code to use. *POP0 and
11824 *POP1 may be updated.
11826 It is possible that we might detect that a comparison is either always
11827 true or always false. However, we do not perform general constant
11828 folding in combine, so this knowledge isn't useful. Such tautologies
11829 should have been detected earlier. Hence we ignore all such cases. */
11831 static enum rtx_code
11833 {
11839 opt_scalar_int_mode tmode_iter;
11841 /* Try a few ways of applying the same transformation to both operands. */
11843 {
11844 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11845 so check specially. */
11864 {
11867 }
11869 /* If both operands are the same constant shift, see if we can ignore the
11870 shift. We can if the shift is a rotate or if the bits shifted out of
11871 this shift are known to be zero for both inputs and if the type of
11872 comparison is compatible with the shift. */
11885 {
11898 else
11900 }
11902 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11903 SUBREGs are of the same mode, and, in both cases, the AND would
11904 be redundant if the comparison was done in the narrower mode,
11905 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11906 and the operand's possibly nonzero bits are 0xffffff01; in that case
11907 if we only care about QImode, we don't need the AND). This case
11908 occurs if the output mode of an scc insn is not SImode and
11909 STORE_FLAG_VALUE == 1 (e.g., the 386).
11911 Similarly, check for a case where the AND's are ZERO_EXTEND
11912 operations from some narrower mode even though a SUBREG is not
11913 present. */
11918 {
11935 {
11939 /* The resulting comparison is always unsigned since we masked
11940 off the original sign bit. */
11944 }
11950 {
11956 }
11960 }
11962 /* If both operands are NOT, we can strip off the outer operation
11963 and adjust the comparison code for swapped operands; similarly for
11964 NEG, except that this must be an equality comparison. */
11970 else
11972 }
11974 /* If the first operand is a constant, swap the operands and adjust the
11975 comparison code appropriately, but don't do this if the second operand
11976 is already a constant integer. */
11978 {
11981 }
11983 /* We now enter a loop during which we will try to simplify the comparison.
11984 For the most part, we only are concerned with comparisons with zero,
11985 but some things may really be comparisons with zero but not start
11986 out looking that way. */
11989 {
11996 HOST_WIDE_INT const_op;
11998 /* We only want to handle integral modes. This catches VOIDmode,
11999 CCmode, and the floating-point modes. An exception is that we
12000 can handle VOIDmode if OP0 is a COMPARE or a comparison
12001 operation. */
12008 /* Try to simplify the compare to constant, possibly changing the
12009 comparison op, and/or changing op1 to zero. */
12013 /* Compute some predicates to simplify code below. */
12020 /* If this is a sign bit comparison and we can do arithmetic in
12021 MODE, say that we will only be needing the sign bit of OP0. */
12024 HOST_WIDE_INT_1U
12028 /* Now try cases based on the opcode of OP0. If none of the cases
12029 does a "continue", we exit this loop immediately after the
12030 switch. */
12033 {
12035 /* If we are extracting a single bit from a variable position in
12036 a constant that has only a single bit set and are comparing it
12037 with zero, we can convert this into an equality comparison
12038 between the position and the location of the single bit. */
12039 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12040 have already reduced the shift count modulo the word size. */
12046 {
12054 /* Result is nonzero iff shift count is equal to I. */
12057 }
12059 /* fall through */
12064 {
12067 }
12071 /* If testing for equality, we can take the NOT of the constant. */
12074 {
12078 }
12080 /* If just looking at the sign bit, reverse the sense of the
12081 comparison. */
12083 {
12087 }
12091 /* If testing for equality, we can take the NEG of the constant. */
12094 {
12098 }
12100 /* The remaining cases only apply to comparisons with zero. */
12104 /* When X is ABS or is known positive,
12105 (neg X) is < 0 if and only if X != 0. */
12113 {
12117 }
12119 /* If we have NEG of something whose two high-order bits are the
12120 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12122 {
12126 }
12130 /* If we are testing equality and our count is a constant, we
12131 can perform the inverse operation on our RHS. */
12135 {
12139 }
12141 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12142 a particular bit. Convert it to an AND of a constant of that
12143 bit. This will be converted into a ZERO_EXTRACT. */
12147 {
12149 (HOST_WIDE_INT_1U
12154 }
12156 /* Fall through. */
12159 /* ABS is ignorable inside an equality comparison with zero. */
12161 {
12164 }
12168 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12169 (compare FOO CONST) if CONST fits in FOO's mode and we
12170 are either testing inequality or have an unsigned
12171 comparison with ZERO_EXTEND or a signed comparison with
12172 SIGN_EXTEND. But don't do it if we don't have a compare
12173 insn of the given mode, since we'd have to revert it
12174 later on, and then we wouldn't know whether to sign- or
12175 zero-extend. */
12178 && ! unsigned_comparison_p
12182 {
12185 }
12189 /* Check for the case where we are comparing A - C1 with C2, that is
12191 (subreg:MODE (plus (A) (-C1))) op (C2)
12193 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12194 comparison in the wider mode. One of the following two conditions
12195 must be true in order for this to be valid:
12197 1. The mode extension results in the same bit pattern being added
12198 on both sides and the comparison is equality or unsigned. As
12199 C2 has been truncated to fit in MODE, the pattern can only be
12200 all 0s or all 1s.
12202 2. The mode extension results in the sign bit being copied on
12203 each side.
12205 The difficulty here is that we have predicates for A but not for
12206 (A - C1) so we need to check that C1 is within proper bounds so
12207 as to perturbate A as little as possible. */
12214 {
12223 /* (A - C1) zero-extends if it is positive and sign-extends
12224 if it is negative, C2 both zero- and sign-extends. */
12228 /* (A - C1) sign-extends if it is positive and 1-extends
12229 if it is negative, C2 both sign- and 1-extends. */
12236 /* (A - C1) always sign-extends, like C2. */
12240 {
12243 }
12244 }
12246 /* If the inner mode is narrower and we are extracting the low part,
12247 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12249 ;
12258 {
12259 /* Remove outer subregs that don't do anything. */
12264 {
12268 }
12270 }
12271 else
12274 /* FALLTHROUGH */
12284 {
12287 }
12291 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12292 this for equality comparisons due to pathological cases involving
12293 overflows. */
12297 {
12301 }
12303 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12306 {
12310 }
12314 /* We used to optimize signed comparisons against zero, but that
12315 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12316 arrive here as equality comparisons, or (GEU, LTU) are
12317 optimized away. No need to special-case them. */
12319 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12320 (eq B (minus A C)), whichever simplifies. We can only do
12321 this for equality comparisons due to pathological cases involving
12322 overflows. */
12326 {
12330 }
12335 {
12339 }
12341 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12342 of bits in X minus 1, is one iff X > 0. */
12347 {
12351 }
12355 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12356 if C is zero or B is a constant. */
12360 {
12364 }
12372 /* We can't do anything if OP0 is a condition code value, rather
12373 than an actual data value. */
12379 /* Get the two operands being compared. */
12382 else
12385 /* Check for the cases where we simply want the result of the
12386 earlier test or the opposite of that result. */
12390 {
12394 else
12398 {
12403 }
12404 }
12408 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12409 iff X <= 0. */
12413 {
12417 }
12421 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12422 will be converted to a ZERO_EXTRACT later. */
12426 {
12431 }
12433 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12434 zero and X is a comparison and C1 and C2 describe only bits set
12435 in STORE_FLAG_VALUE, we can compare with X. */
12443 {
12450 {
12453 }
12454 }
12456 /* If we are doing an equality comparison of an AND of a bit equal
12457 to the sign bit, replace this with a LT or GE comparison of
12458 the underlying value. */
12465 {
12469 }
12471 /* If this AND operation is really a ZERO_EXTEND from a narrower
12472 mode, the constant fits within that mode, and this is either an
12473 equality or unsigned comparison, try to do this comparison in
12474 the narrower mode.
12476 Note that in:
12478 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12479 -> (ne:DI (reg:SI 4) (const_int 0))
12481 unless TRULY_NOOP_TRUNCATION allows it or the register is
12482 known to hold a value of the required mode the
12483 transformation is invalid. */
12491 {
12494 }
12496 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12497 fits in both M1 and M2 and the SUBREG is either paradoxical
12498 or represents the low part, permute the SUBREG and the AND
12499 and try again. */
12502 {
12504 /* Require an integral mode, to avoid creating something like
12505 (AND:SF ...). */
12508 /* It is unsafe to commute the AND into the SUBREG if the
12509 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12510 not defined. As originally written the upper bits
12511 have a defined value due to the AND operation.
12512 However, if we commute the AND inside the SUBREG then
12513 they no longer have defined values and the meaning of
12514 the code has been changed.
12515 Also C1 should not change value in the smaller mode,
12516 see PR67028 (a positive C1 can become negative in the
12517 smaller mode, so that the AND does no longer mask the
12518 upper bits). */
12519 && ((WORD_REGISTER_OPERATIONS
12531 {
12537 }
12538 }
12540 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12544 {
12549 }
12551 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12552 (eq (and (lshiftrt X) 1) 0).
12553 Also handle the case where (not X) is expressed using xor. */
12557 {
12567 == HOST_WIDE_INT_1U
12569 {
12570 op0
12575 }
12576 }
12580 /* If we have (compare (ashift FOO N) (const_int C)) and
12581 the high order N bits of FOO (N+1 if an inequality comparison)
12582 are known to be zero, we can do this by comparing FOO with C
12583 shifted right N bits so long as the low-order N bits of C are
12584 zero. */
12596 {
12597 /* We must perform a logical shift, not an arithmetic one,
12598 as we want the top N bits of C to be zero. */
12605 }
12607 /* If we are doing a sign bit comparison, it means we are testing
12608 a particular bit. Convert it to the appropriate AND. */
12611 {
12613 (HOST_WIDE_INT_1U
12618 }
12620 /* If this an equality comparison with zero and we are shifting
12621 the low bit to the sign bit, we can convert this to an AND of the
12622 low-order bit. */
12626 {
12629 }
12633 /* If this is an equality comparison with zero, we can do this
12634 as a logical shift, which might be much simpler. */
12637 {
12642 }
12644 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12645 do the comparison in a narrower mode. */
12655 {
12658 }
12660 /* Likewise if OP0 is a PLUS of a sign extension with a
12661 constant, which is usually represented with the PLUS
12662 between the shifts. */
12674 {
12682 new_const);
12684 }
12686 /* FALLTHROUGH */
12688 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12689 the low order N bits of FOO are known to be zero, we can do this
12690 by comparing FOO with C shifted left N bits so long as no
12691 overflow occurs. Even if the low order N bits of FOO aren't known
12692 to be zero, if the comparison is >= or < we can use the same
12693 optimization and for > or <= by setting all the low
12694 order N bits in the comparison constant. */
12705 {
12706 unsigned HOST_WIDE_INT low_bits
12708 & ((HOST_WIDE_INT_1U
12711 {
12712 /* If the shift was logical, then we must make the condition
12713 unsigned. */
12722 const_op
12727 }
12728 }
12730 /* If we are using this shift to extract just the sign bit, we
12731 can replace this with an LT or GE comparison. */
12736 {
12740 }
12745 }
12748 }
12750 /* Now make any compound operations involved in this comparison. Then,
12751 check for an outmost SUBREG on OP0 that is not doing anything or is
12752 paradoxical. The latter transformation must only be performed when
12753 it is known that the "extra" bits will be the same in op0 and op1 or
12754 that they don't matter. There are three cases to consider:
12756 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12757 care bits and we can assume they have any convenient value. So
12758 making the transformation is safe.
12760 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12761 In this case the upper bits of op0 are undefined. We should not make
12762 the simplification in that case as we do not know the contents of
12763 those bits.
12765 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12766 In that case we know those bits are zeros or ones. We must also be
12767 sure that they are the same as the upper bits of op1.
12769 We can never remove a SUBREG for a non-equality comparison because
12770 the sign bit is in a different place in the underlying object. */
12783 {
12785 {
12786 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12787 implemented. */
12789 {
12792 }
12793 }
12797 {
12802 }
12803 }
12805 /* We now do the opposite procedure: Some machines don't have compare
12806 insns in all modes. If OP0's mode is an integer mode smaller than a
12807 word and we can't do a compare in that mode, see if there is a larger
12808 mode for which we can do the compare. There are a number of cases in
12809 which we can use the wider mode. */
12815 {
12820 {
12823 /* If this is a test for negative, we can make an explicit
12824 test of the sign bit. Test this first so we can use
12825 a paradoxical subreg to extend OP0. */
12829 {
12830 unsigned HOST_WIDE_INT sign
12837 }
12839 /* If the only nonzero bits in OP0 and OP1 are those in the
12840 narrower mode and this is an equality or unsigned comparison,
12841 we can use the wider mode. Similarly for sign-extended
12842 values, in which case it is true for all comparisons. */
12859 {
12860 /* If OP0 is an AND and we don't have an AND in MODE either,
12861 make a new AND in the proper mode. */
12869 else
12870 {
12872 {
12877 }
12878 else
12879 {
12884 }
12886 }
12887 }
12888 }
12889 }
12891 /* We may have changed the comparison operands. Re-canonicalize. */
12893 {
12896 }
12898 /* If this machine only supports a subset of valid comparisons, see if we
12899 can convert an unsupported one into a supported one. */
12906 }
12907 \f
12908 /* Utility function for record_value_for_reg. Count number of
12909 rtxs in X. */
12910 static int
12912 {
12919 {
12939 }
12950 }
12951 \f
12952 /* Utility function for following routine. Called when X is part of a value
12953 being stored into last_set_value. Sets last_set_table_tick
12954 for each register mentioned. Similar to mention_regs in cse.c */
12956 static void
12958 {
12964 {
12970 {
12973 }
12976 }
12980 {
12981 /* Check for identical subexpressions. If x contains
12982 identical subexpression we only have to traverse one of
12983 them. */
12985 {
12986 /* Note that at this point x1 has already been
12987 processed. */
12991 /* If x0 and x1 are identical then there is no need to
12992 process x0. */
12996 /* If x0 is identical to a subexpression of x1 then while
12997 processing x1, x0 has already been processed. Thus we
12998 are done with x. */
13003 /* If x1 is identical to a subexpression of x0 then we
13004 still have to process the rest of x0. */
13007 {
13010 }
13011 }
13014 }
13018 }
13020 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13021 are saying that the register is clobbered and we no longer know its
13022 value. If INSN is zero, don't update reg_stat[].last_set; this is
13023 only permitted with VALUE also zero and is used to invalidate the
13024 register. */
13026 static void
13028 {
13034 /* If VALUE contains REG and we have a previous value for REG, substitute
13035 the previous value. */
13037 {
13038 rtx tem;
13040 /* Set things up so get_last_value is allowed to see anything set up to
13041 our insn. */
13045 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13046 it isn't going to be useful and will take a lot of time to process,
13047 so just use the CLOBBER. */
13050 {
13056 {
13057 /* If there are two or more occurrences of REG in VALUE,
13058 prevent the value from growing too much. */
13061 }
13064 }
13065 }
13067 /* For each register modified, show we don't know its value, that
13068 we don't know about its bitwise content, that its value has been
13069 updated, and that we don't know the location of the death of the
13070 register. */
13072 {
13084 }
13086 /* Mark registers that are being referenced in this value. */
13090 /* Now update the status of each register being set.
13091 If someone is using this register in this block, set this register
13092 to invalid since we will get confused between the two lives in this
13093 basic block. This makes using this register always invalid. In cse, we
13094 scan the table to invalidate all entries using this register, but this
13095 is too much work for us. */
13098 {
13104 else
13106 }
13108 /* The value being assigned might refer to X (like in "x++;"). In that
13109 case, we must replace it with (clobber (const_int 0)) to prevent
13110 infinite loops. */
13113 {
13117 }
13119 /* For the main register being modified, update the value, the mode, the
13120 nonzero bits, and the number of sign bit copies. */
13125 {
13133 rsp->last_set_sign_bit_copies
13135 }
13136 }
13138 /* Called via note_stores from record_dead_and_set_regs to handle one
13139 SET or CLOBBER in an insn. DATA is the instruction in which the
13140 set is occurring. */
13142 static void
13144 {
13151 {
13155 }
13158 {
13159 /* If we are setting the whole register, we know its value. Otherwise
13160 show that we don't know the value. We can handle SUBREG in
13161 some cases. */
13172 else
13174 }
13176 /* Ignore pushes, they clobber nothing. */
13179 }
13181 /* Update the records of when each REG was most recently set or killed
13182 for the things done by INSN. This is the last thing done in processing
13183 INSN in the combiner loop.
13185 We update reg_stat[], in particular fields last_set, last_set_value,
13186 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13187 last_death, and also the similar information mem_last_set (which insn
13188 most recently modified memory) and last_call_luid (which insn was the
13189 most recent subroutine call). */
13191 static void
13193 {
13194 rtx link;
13198 {
13201 {
13206 {
13211 }
13212 }
13215 }
13218 {
13219 hard_reg_set_iterator hrsi;
13221 {
13233 }
13237 /* We can't combine into a call pattern. Remember, though, that
13238 the return value register is set at this LUID. We could
13239 still replace a register with the return value from the
13240 wrong subroutine call! */
13242 }
13243 else
13245 }
13247 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13248 register present in the SUBREG, so for each such SUBREG go back and
13249 adjust nonzero and sign bit information of the registers that are
13250 known to have some zero/sign bits set.
13252 This is needed because when combine blows the SUBREGs away, the
13253 information on zero/sign bits is lost and further combines can be
13254 missed because of that. */
13256 static void
13258 {
13260 rtx set;
13268 {
13277 {
13280 }
13284 {
13287 }
13290 {
13293 }
13294 else
13296 }
13297 }
13299 /* Check if X, a register, is known to contain a value already
13300 truncated to MODE. In this case we can use a subreg to refer to
13301 the truncated value even though in the generic case we would need
13302 an explicit truncation. */
13304 static bool
13306 {
13318 }
13320 /* If X is a hard reg or a subreg record the mode that the register is
13321 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13322 to turn a truncate into a subreg using this information. Return true
13323 if traversing X is complete. */
13325 static bool
13327 {
13328 machine_mode truncated_mode;
13332 {
13343 }
13344 /* ??? For hard-regs we now record everything. We might be able to
13345 optimize this using last_set_mode. */
13348 else
13356 {
13359 }
13362 }
13364 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13365 the modes they are used in. This can help truning TRUNCATEs into
13366 SUBREGs. */
13368 static void
13370 {
13375 }
13377 /* Scan X for promoted SUBREGs. For each one found,
13378 note what it implies to the registers used in it. */
13380 static void
13382 {
13387 else
13388 {
13394 {
13404 }
13405 }
13406 }
13407 \f
13408 /* Verify that all the registers and memory references mentioned in *LOC are
13409 still valid. *LOC was part of a value set in INSN when label_tick was
13410 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13411 the invalid references with (clobber (const_int 0)) and return 1. This
13412 replacement is useful because we often can get useful information about
13413 the form of a value (e.g., if it was produced by a shift that always
13414 produces -1 or 0) even though we don't know exactly what registers it
13415 was produced from. */
13417 static int
13419 {
13426 {
13432 {
13435 /* If this is a pseudo-register that was only set once and not
13436 live at the beginning of the function, it is always valid. */
13440 && (!REGNO_REG_SET_P
13442 regno)))
13444 {
13448 }
13449 }
13452 }
13453 /* If this is a memory reference, make sure that there were no stores after
13454 it that might have clobbered the value. We don't have alias info, so we
13455 assume any store invalidates it. Moreover, we only have local UIDs, so
13456 we also assume that there were stores in the intervening basic blocks. */
13459 {
13463 }
13466 {
13468 {
13469 /* Check for identical subexpressions. If x contains
13470 identical subexpression we only have to traverse one of
13471 them. */
13473 {
13474 /* Note that at this point x0 has already been checked
13475 and found valid. */
13479 /* If x0 and x1 are identical then x is also valid. */
13483 /* If x1 is identical to a subexpression of x0 then
13484 while checking x0, x1 has already been checked. Thus
13485 it is valid and so as x. */
13490 /* If x0 is identical to a subexpression of x1 then x is
13491 valid iff the rest of x1 is valid. */
13494 return
13498 }
13503 }
13509 }
13511 /* If we haven't found a reason for it to be invalid, it is valid. */
13513 }
13515 /* Get the last value assigned to X, if known. Some registers
13516 in the value may be replaced with (clobber (const_int 0)) if their value
13517 is known longer known reliably. */
13519 static rtx
13521 {
13523 rtx value;
13526 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13527 then convert it to the desired mode. If this is a paradoxical SUBREG,
13528 we cannot predict what values the "extra" bits might have. */
13542 /* If we don't have a value, or if it isn't for this basic block and
13543 it's either a hard register, set more than once, or it's a live
13544 at the beginning of the function, return 0.
13546 Because if it's not live at the beginning of the function then the reg
13547 is always set before being used (is never used without being set).
13548 And, if it's set only once, and it's always set before use, then all
13549 uses must have the same last value, even if it's not from this basic
13550 block. */
13557 || REGNO_REG_SET_P
13561 /* If the value was set in a later insn than the ones we are processing,
13562 we can't use it even if the register was only set once. */
13567 /* If fewer bits were set than what we are asked for now, we cannot use
13568 the value. */
13573 /* If the value has all its registers valid, return it. */
13577 /* Otherwise, make a copy and replace any invalid register with
13578 (clobber (const_int 0)). If that fails for some reason, return 0. */
13585 }
13586 \f
13587 /* Return nonzero if expression X refers to a REG or to memory
13588 that is set in an instruction more recent than FROM_LUID. */
13590 static int
13592 {
13598 {
13602 #ifdef PUSH_ROUNDING
13603 /* Don't allow uses of the stack pointer to be moved,
13604 because we don't know whether the move crosses a push insn. */
13607 #endif
13609 {
13615 }
13617 }
13625 {
13627 {
13632 }
13636 }
13638 }
13639 \f
13640 /* Define three variables used for communication between the following
13641 routines. */
13646 /* Function called via note_stores from reg_dead_at_p.
13648 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13649 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13651 static void
13653 {
13663 }
13665 /* Return nonzero if REG is known to be dead at INSN.
13667 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13668 referencing REG, it is dead. If we hit a SET referencing REG, it is
13669 live. Otherwise, see if it is live or dead at the start of the basic
13670 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13671 must be assumed to be always live. */
13673 static int
13675 {
13676 basic_block block;
13679 /* Set variables for reg_dead_at_p_1. */
13685 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13686 we allow the machine description to decide whether use-and-clobber
13687 patterns are OK. */
13689 {
13693 }
13695 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13696 beginning of basic block. */
13699 {
13701 {
13711 }
13717 }
13719 /* Look at live-in sets for the basic block that we were in. */
13725 }
13726 \f
13727 /* Note hard registers in X that are used. */
13729 static void
13731 {
13737 {
13741 CASE_CONST_ANY:
13746 /* CC0 must die in the insn after it is set, so we don't need to take
13747 special note of it here. */
13752 /* If we are clobbering a MEM, mark any hard registers inside the
13753 address as used. */
13760 /* A hard reg in a wide mode may really be multiple registers.
13761 If so, mark all of them just like the first. */
13763 {
13764 /* None of this applies to the stack, frame or arg pointers. */
13766 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13774 }
13778 {
13779 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13780 the address. */
13792 }
13797 }
13799 /* Recursively scan the operands of this expression. */
13801 {
13805 {
13809 {
13814 }
13815 }
13816 }
13817 }
13818 \f
13819 /* Remove register number REGNO from the dead registers list of INSN.
13821 Return the note used to record the death, if there was one. */
13823 rtx
13825 {
13832 }
13834 /* For each register (hardware or pseudo) used within expression X, if its
13835 death is in an instruction with luid between FROM_LUID (inclusive) and
13836 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13837 list headed by PNOTES.
13839 That said, don't move registers killed by maybe_kill_insn.
13841 This is done when X is being merged by combination into TO_INSN. These
13842 notes will then be distributed as needed. */
13844 static void
13847 {
13853 {
13857 /* Don't move the register if it gets killed in between from and to. */
13866 {
13869 /* It is possible for the call above to return 0. This can occur
13870 when last_death points to I2 or I1 that we combined with.
13871 In that case make a new note.
13873 We must also check for the case where X is a hard register
13874 and NOTE is a death note for a range of hard registers
13875 including X. In that case, we must put REG_DEAD notes for
13876 the remaining registers in place of NOTE. */
13881 {
13890 }
13892 /* If we didn't find any note, or if we found a REG_DEAD note that
13893 covers only part of the given reg, and we have a multi-reg hard
13894 register, then to be safe we must check for REG_DEAD notes
13895 for each register other than the first. They could have
13896 their own REG_DEAD notes lying around. */
13903 {
13910 else
13916 }
13919 {
13922 }
13923 else
13925 }
13928 }
13931 {
13936 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13937 that accesses one word of a multi-word item, some
13938 piece of everything register in the expression is used by
13939 this insn, so remove any old death. */
13940 /* ??? So why do we test for equality of the sizes? */
13949 {
13952 }
13954 /* If this is some other SUBREG, we know it replaces the entire
13955 value, so use that as the destination. */
13959 /* If this is a MEM, adjust deaths of anything used in the address.
13960 For a REG (the only other possibility), the entire value is
13961 being replaced so the old value is not used in this insn. */
13967 }
13976 {
13978 {
13983 }
13986 }
13987 }
13988 \f
13989 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13990 pattern of an insn. X must be a REG. */
13992 static int
13994 {
13998 {
14000 rtx target;
14007 else
14024 }
14032 }
14033 \f
14034 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14035 as appropriate. I3 and I2 are the insns resulting from the combination
14036 insns including FROM (I2 may be zero).
14038 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14039 not need REG_DEAD notes because they are being substituted for. This
14040 saves searching in the most common cases.
14042 Each note in the list is either ignored or placed on some insns, depending
14043 on the type of note. */
14045 static void
14048 {
14050 rtx tem_note;
14054 {
14059 {
14062 /* Doesn't matter much where we put this, as long as it's somewhere.
14063 It is preferable to keep these notes on branches, which is most
14064 likely to be i3. */
14071 else
14072 {
14075 }
14079 /* These notes must remain with the call or trapping instruction. */
14084 else
14085 {
14091 /* ??? Otherwise assume we've combined things such that we
14092 can now prove that the instructions can't trap. Drop the
14093 note in this case. */
14094 }
14098 /* ??? How to distribute between i3-i1. Assume i3 contains the
14099 entire adjustment. Assert i3 contains at least some adjust. */
14101 {
14103 /* fixup_args_size_notes looks at REG_NORETURN note,
14104 so ensure the note is placed there first. */
14106 {
14110 {
14116 }
14117 }
14119 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14120 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14123 && !ACCUMULATE_OUTGOING_ARGS
14125 }
14132 /* These notes must remain with the call. It should not be
14133 possible for both I2 and I3 to be a call. */
14136 else
14137 {
14140 }
14144 /* Any clobbers for i3 may still exist, and so we must process
14145 REG_UNUSED notes from that insn.
14147 Any clobbers from i2 or i1 can only exist if they were added by
14148 recog_for_combine. In that case, recog_for_combine created the
14149 necessary REG_UNUSED notes. Trying to keep any original
14150 REG_UNUSED notes from these insns can cause incorrect output
14151 if it is for the same register as the original i3 dest.
14152 In that case, we will notice that the register is set in i3,
14153 and then add a REG_UNUSED note for the destination of i3, which
14154 is wrong. However, it is possible to have REG_UNUSED notes from
14155 i2 or i1 for register which were both used and clobbered, so
14156 we keep notes from i2 or i1 if they will turn into REG_DEAD
14157 notes. */
14159 /* If this register is set or clobbered in I3, put the note there
14160 unless there is one already. */
14162 {
14170 }
14171 /* Otherwise, if this register is used by I3, then this register
14172 now dies here, so we must put a REG_DEAD note here unless there
14173 is one already. */
14179 {
14182 }
14188 /* These notes say something about results of an insn. We can
14189 only support them if they used to be on I3 in which case they
14190 remain on I3. Otherwise they are ignored.
14192 If the note refers to an expression that is not a constant, we
14193 must also ignore the note since we cannot tell whether the
14194 equivalence is still true. It might be possible to do
14195 slightly better than this (we only have a problem if I2DEST
14196 or I1DEST is present in the expression), but it doesn't
14197 seem worth the trouble. */
14205 /* These notes say something about how a register is used. They must
14206 be present on any use of the register in I2 or I3. */
14211 {
14214 else
14216 }
14221 /* This can show up in several ways -- either directly in the
14222 pattern, or hidden off in the constant pool with (or without?)
14223 a REG_EQUAL note. */
14224 /* ??? Ignore the without-reg_equal-note problem for now. */
14236 {
14239 else
14241 }
14243 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14244 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14245 there. */
14250 {
14257 }
14263 {
14271 }
14275 /* This note says something about the value of a register prior
14276 to the execution of an insn. It is too much trouble to see
14277 if the note is still correct in all situations. It is better
14278 to simply delete it. */
14282 /* If we replaced the right hand side of FROM_INSN with a
14283 REG_EQUAL note, the original use of the dying register
14284 will not have been combined into I3 and I2. In such cases,
14285 FROM_INSN is guaranteed to be the first of the combined
14286 instructions, so we simply need to search back before
14287 FROM_INSN for the previous use or set of this register,
14288 then alter the notes there appropriately.
14290 If the register is used as an input in I3, it dies there.
14291 Similarly for I2, if it is nonzero and adjacent to I3.
14293 If the register is not used as an input in either I3 or I2
14294 and it is not one of the registers we were supposed to eliminate,
14295 there are two possibilities. We might have a non-adjacent I2
14296 or we might have somehow eliminated an additional register
14297 from a computation. For example, we might have had A & B where
14298 we discover that B will always be zero. In this case we will
14299 eliminate the reference to A.
14301 In both cases, we must search to see if we can find a previous
14302 use of A and put the death note there. */
14308 else
14309 {
14320 && !(i2mod
14322 i2mod_old_rhs)))
14327 /* If the new I2 sets the same register that is marked dead
14328 in the note, we do not know where to put the note.
14329 Give up. */
14332 }
14335 {
14339 {
14341 {
14345 }
14347 /* If the register is being set at TEM_INSN, see if that is all
14348 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14349 into a REG_UNUSED note instead. Don't delete sets to
14350 global register vars. */
14354 {
14365 ;
14367 /* Verify that it was the set, and not a clobber that
14368 modified the register.
14370 CC0 targets must be careful to maintain setter/user
14371 pairs. If we cannot delete the setter due to side
14372 effects, mark the user with an UNUSED note instead
14373 of deleting it. */
14377 && (!HAVE_cc0
14381 {
14382 /* Move the notes and links of TEM_INSN elsewhere.
14383 This might delete other dead insns recursively.
14384 First set the pattern to something that won't use
14385 any register. */
14404 /* Delete the setter too. */
14406 {
14419 }
14420 }
14421 else
14422 {
14425 /* If there isn't already a REG_UNUSED note, put one
14426 here. Do not place a REG_DEAD note, even if
14427 the register is also used here; that would not
14428 match the algorithm used in lifetime analysis
14429 and can cause the consistency check in the
14430 scheduler to fail. */
14435 }
14436 }
14440 {
14443 /* If we are doing a 3->2 combination, and we have a
14444 register which formerly died in i3 and was not used
14445 by i2, which now no longer dies in i3 and is used in
14446 i2 but does not die in i2, and place is between i2
14447 and i3, then we may need to move a link from place to
14448 i2. */
14450 && from_insn
14453 {
14457 }
14459 }
14463 }
14465 }
14467 /* If the register is set or already dead at PLACE, we needn't do
14468 anything with this note if it is still a REG_DEAD note.
14469 We check here if it is set at all, not if is it totally replaced,
14470 which is what `dead_or_set_p' checks, so also check for it being
14471 set partially. */
14474 {
14480 {
14481 /* Unless the register previously died in PLACE, clear
14482 last_death. [I no longer understand why this is
14483 being done.] */
14487 }
14488 else
14491 /* If this is a death note for a hard reg that is occupying
14492 multiple registers, ensure that we are still using all
14493 parts of the object. If we find a piece of the object
14494 that is unused, we must arrange for an appropriate REG_DEAD
14495 note to be added for it. However, we can't just emit a USE
14496 and tag the note to it, since the register might actually
14497 be dead; so we recourse, and the recursive call then finds
14498 the previous insn that used this register. */
14501 {
14510 {
14513 }
14516 {
14517 /* Put only REG_DEAD notes for pieces that are
14518 not already dead or set. */
14522 {
14529 {
14531 NULL_RTX);
14535 NULL_RTX);
14536 }
14541 {
14543 {
14547 }
14551 {
14554 }
14555 }
14556 }
14559 }
14560 }
14561 }
14565 /* Any other notes should not be present at this point in the
14566 compilation. */
14568 }
14571 {
14574 }
14578 }
14579 }
14580 \f
14581 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14582 I3, I2, and I1 to new locations. This is also called to add a link
14583 pointing at I3 when I3's destination is changed. */
14585 static void
14587 {
14591 {
14598 /* If the insn that this link points to is a NOTE, ignore it. */
14607 {
14610 {
14626 }
14629 }
14630 else
14640 /* A LOG_LINK is defined as being placed on the first insn that uses
14641 a register and points to the insn that sets the register. Start
14642 searching at the next insn after the target of the link and stop
14643 when we reach a set of the register or the end of the basic block.
14645 Note that this correctly handles the link that used to point from
14646 I3 to I2. Also note that not much searching is typically done here
14647 since most links don't point very far away. */
14656 {
14660 }
14663 {
14666 }
14670 /* If we found a place to put the link, place it there unless there
14671 is already a link to the same insn as LINK at that point. */
14674 {
14682 {
14686 /* Set added_links_insn to the earliest insn we added a
14687 link to. */
14691 }
14692 }
14693 }
14694 }
14695 \f
14696 /* Check for any register or memory mentioned in EQUIV that is not
14697 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14698 of EXPR where some registers may have been replaced by constants. */
14700 static bool
14702 {
14705 {
14710 }
14712 }
14713 \f
14714 DEBUG_FUNCTION void
14716 {
14717 fprintf
14719 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14721 }
14723 void
14725 {
14726 fprintf
14728 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14730 }
14731 \f
14732 /* Try combining insns through substitution. */
14733 static unsigned int
14735 {
14745 rebuild_jump_labels_after_combine
14748 /* Combining insns may have turned an indirect jump into a
14749 direct jump. Rebuild the JUMP_LABEL fields of jumping
14750 instructions. */
14752 {
14759 }
14763 }
14768 {
14778 };
14781 {
14785 {}
14787 /* opt_pass methods: */
14790 {
14792 }
14798 rtl_opt_pass *
14800 {
14802 }