1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-flags.h"
33 #include "insn-codes.h"
38 #include "basic-block.h"
46 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
47 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
85 #ifndef REGISTER_MOVE_COST
86 #define REGISTER_MOVE_COST(x, y) 2
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx
*reg_last_reload_reg
;
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static char *reg_has_output_reload
;
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload
;
101 /* Element N is the constant value to which pseudo reg N is equivalent,
102 or zero if pseudo reg N is not equivalent to a constant.
103 find_reloads looks at this in order to replace pseudo reg N
104 with the constant it stands for. */
105 rtx
*reg_equiv_constant
;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx
*reg_equiv_memory_loc
;
113 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
114 This is used when the address is not valid as a memory address
115 (because its displacement is too big for the machine.) */
116 rtx
*reg_equiv_address
;
118 /* Element N is the memory slot to which pseudo reg N is equivalent,
119 or zero if pseudo reg N is not equivalent to a memory slot. */
122 /* Widest width in which each pseudo reg is referred to (via subreg). */
123 static int *reg_max_ref_width
;
125 /* Element N is the list of insns that initialized reg N from its equivalent
126 constant or memory slot. */
127 static rtx
*reg_equiv_init
;
129 /* Vector to remember old contents of reg_renumber before spilling. */
130 static short *reg_old_renumber
;
132 /* During reload_as_needed, element N contains the last pseudo regno reloaded
133 into hard register N. If that pseudo reg occupied more than one register,
134 reg_reloaded_contents points to that pseudo for each spill register in
135 use; all of these must remain set for an inheritance to occur. */
136 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
138 /* During reload_as_needed, element N contains the insn for which
139 hard register N was last used. Its contents are significant only
140 when reg_reloaded_valid is set for this register. */
141 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
143 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
144 static HARD_REG_SET reg_reloaded_valid
;
145 /* Indicate if the register was dead at the end of the reload.
146 This is only valid if reg_reloaded_contents is set and valid. */
147 static HARD_REG_SET reg_reloaded_dead
;
149 /* Number of spill-regs so far; number of valid elements of spill_regs. */
152 /* In parallel with spill_regs, contains REG rtx's for those regs.
153 Holds the last rtx used for any given reg, or 0 if it has never
154 been used for spilling yet. This rtx is reused, provided it has
156 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
158 /* In parallel with spill_regs, contains nonzero for a spill reg
159 that was stored after the last time it was used.
160 The precise value is the insn generated to do the store. */
161 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
163 /* This is the register that was stored with spill_reg_store. This is a
164 copy of reload_out / reload_out_reg when the value was stored; if
165 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
166 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
168 /* This table is the inverse mapping of spill_regs:
169 indexed by hard reg number,
170 it contains the position of that reg in spill_regs,
171 or -1 for something that is not in spill_regs.
173 ?!? This is no longer accurate. */
174 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
176 /* This reg set indicates registers that can't be used as spill registers for
177 the currently processed insn. These are the hard registers which are live
178 during the insn, but not allocated to pseudos, as well as fixed
180 static HARD_REG_SET bad_spill_regs
;
182 /* These are the hard registers that can't be used as spill register for any
183 insn. This includes registers used for user variables and registers that
184 we can't eliminate. A register that appears in this set also can't be used
185 to retry register allocation. */
186 static HARD_REG_SET bad_spill_regs_global
;
188 /* Describes order of use of registers for reloading
189 of spilled pseudo-registers. `n_spills' is the number of
190 elements that are actually valid; new ones are added at the end.
192 Both spill_regs and spill_reg_order are used on two occasions:
193 once during find_reload_regs, where they keep track of the spill registers
194 for a single insn, but also during reload_as_needed where they show all
195 the registers ever used by reload. For the latter case, the information
196 is calculated during finish_spills. */
197 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
199 /* This vector of reg sets indicates, for each pseudo, which hard registers
200 may not be used for retrying global allocation because the register was
201 formerly spilled from one of them. If we allowed reallocating a pseudo to
202 a register that it was already allocated to, reload might not
204 static HARD_REG_SET
*pseudo_previous_regs
;
206 /* This vector of reg sets indicates, for each pseudo, which hard
207 registers may not be used for retrying global allocation because they
208 are used as spill registers during one of the insns in which the
210 static HARD_REG_SET
*pseudo_forbidden_regs
;
212 /* All hard regs that have been used as spill registers for any insn are
213 marked in this set. */
214 static HARD_REG_SET used_spill_regs
;
216 /* Index of last register assigned as a spill register. We allocate in
217 a round-robin fashion. */
218 static int last_spill_reg
;
220 /* Nonzero if indirect addressing is supported on the machine; this means
221 that spilling (REG n) does not require reloading it into a register in
222 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
223 value indicates the level of indirect addressing supported, e.g., two
224 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
226 static char spill_indirect_levels
;
228 /* Nonzero if indirect addressing is supported when the innermost MEM is
229 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
230 which these are valid is the same as spill_indirect_levels, above. */
231 char indirect_symref_ok
;
233 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
234 char double_reg_address_ok
;
236 /* Record the stack slot for each spilled hard register. */
237 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
239 /* Width allocated so far for that stack slot. */
240 static int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
242 /* Record which pseudos needed to be spilled. */
243 static regset_head spilled_pseudos
;
245 /* Used for communication between order_regs_for_reload and count_pseudo.
246 Used to avoid counting one pseudo twice. */
247 static regset_head pseudos_counted
;
249 /* First uid used by insns created by reload in this function.
250 Used in find_equiv_reg. */
251 int reload_first_uid
;
253 /* Flag set by local-alloc or global-alloc if anything is live in
254 a call-clobbered reg across calls. */
255 int caller_save_needed
;
257 /* Set to 1 while reload_as_needed is operating.
258 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress
= 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
264 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
265 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
267 /* This obstack is used for allocation of rtl during register elimination.
268 The allocated storage can be freed once find_reloads has processed the
270 struct obstack reload_obstack
;
272 /* Points to the beginning of the reload_obstack. All insn_chain structures
273 are allocated first. */
274 char *reload_startobj
;
276 /* The point after all insn_chain structures. Used to quickly deallocate
277 memory allocated in copy_reloads during calculate_needs_all_insns. */
278 char *reload_firstobj
;
280 /* This points before all local rtl generated by register elimination.
281 Used to quickly free all memory after processing one insn. */
282 static char *reload_insn_firstobj
;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain
*reload_insn_chain
;
292 extern tree current_function_decl
;
294 extern union tree_node
*current_function_decl
;
297 /* List of all insns needing reloads. */
298 static struct insn_chain
*insns_need_reload
;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from
; /* Register number to be eliminated. */
308 int to
; /* Register number used as replacement. */
309 int initial_offset
; /* Initial difference between values. */
310 int can_eliminate
; /* Non-zero if this elimination can be done. */
311 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 int offset
; /* Current offset between the two regs. */
314 int previous_offset
; /* Offset at end of previous insn. */
315 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx
; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx
; /* REG rtx for the replacement. */
324 static struct elim_table
* reg_eliminate
= 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static struct elim_table_1
332 } reg_eliminate_1
[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
344 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If non-zero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset
;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable
;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants
;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the number of the label.
360 The first table is an array of flags that records whether we have yet
361 encountered a label and the second table is an array of arrays, one
362 entry in the latter array for each elimination. */
364 static char *offsets_known_at
;
365 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
367 /* Number of labels in the current function. */
369 static int num_labels
;
371 static void maybe_fix_stack_asms
PARAMS ((void));
372 static void copy_reloads
PARAMS ((struct insn_chain
*));
373 static void calculate_needs_all_insns
PARAMS ((int));
374 static int find_reg
PARAMS ((struct insn_chain
*, int,
376 static void find_reload_regs
PARAMS ((struct insn_chain
*, FILE *));
377 static void select_reload_regs
PARAMS ((FILE *));
378 static void delete_caller_save_insns
PARAMS ((void));
380 static void spill_failure
PARAMS ((rtx
, enum reg_class
));
381 static void count_spilled_pseudo
PARAMS ((int, int, int));
382 static void delete_dead_insn
PARAMS ((rtx
));
383 static void alter_reg
PARAMS ((int, int));
384 static void set_label_offsets
PARAMS ((rtx
, rtx
, int));
385 static void check_eliminable_occurrences
PARAMS ((rtx
));
386 static void elimination_effects
PARAMS ((rtx
, enum machine_mode
));
387 static int eliminate_regs_in_insn
PARAMS ((rtx
, int));
388 static void update_eliminable_offsets
PARAMS ((void));
389 static void mark_not_eliminable
PARAMS ((rtx
, rtx
, void *));
390 static void set_initial_elim_offsets
PARAMS ((void));
391 static void verify_initial_elim_offsets
PARAMS ((void));
392 static void set_initial_label_offsets
PARAMS ((void));
393 static void set_offsets_for_label
PARAMS ((rtx
));
394 static void init_elim_table
PARAMS ((void));
395 static void update_eliminables
PARAMS ((HARD_REG_SET
*));
396 static void spill_hard_reg
PARAMS ((int, FILE *, int));
397 static int finish_spills
PARAMS ((int, FILE *));
398 static void ior_hard_reg_set
PARAMS ((HARD_REG_SET
*, HARD_REG_SET
*));
399 static void scan_paradoxical_subregs
PARAMS ((rtx
));
400 static void count_pseudo
PARAMS ((int));
401 static void order_regs_for_reload
PARAMS ((struct insn_chain
*));
402 static void reload_as_needed
PARAMS ((int));
403 static void forget_old_reloads_1
PARAMS ((rtx
, rtx
, void *));
404 static int reload_reg_class_lower
PARAMS ((const PTR
, const PTR
));
405 static void mark_reload_reg_in_use
PARAMS ((int, int, enum reload_type
,
407 static void clear_reload_reg_in_use
PARAMS ((int, int, enum reload_type
,
409 static int reload_reg_free_p
PARAMS ((int, int, enum reload_type
));
410 static int reload_reg_free_for_value_p
PARAMS ((int, int, enum reload_type
,
411 rtx
, rtx
, int, int));
412 static int reload_reg_reaches_end_p
PARAMS ((int, int, enum reload_type
));
413 static int allocate_reload_reg
PARAMS ((struct insn_chain
*, int, int));
414 static void failed_reload
PARAMS ((rtx
, int));
415 static int set_reload_reg
PARAMS ((int, int));
416 static void choose_reload_regs_init
PARAMS ((struct insn_chain
*, rtx
*));
417 static void choose_reload_regs
PARAMS ((struct insn_chain
*));
418 static void merge_assigned_reloads
PARAMS ((rtx
));
419 static void emit_input_reload_insns
PARAMS ((struct insn_chain
*,
420 struct reload
*, rtx
, int));
421 static void emit_output_reload_insns
PARAMS ((struct insn_chain
*,
422 struct reload
*, int));
423 static void do_input_reload
PARAMS ((struct insn_chain
*,
424 struct reload
*, int));
425 static void do_output_reload
PARAMS ((struct insn_chain
*,
426 struct reload
*, int));
427 static void emit_reload_insns
PARAMS ((struct insn_chain
*));
428 static void delete_output_reload
PARAMS ((rtx
, int, int));
429 static void delete_address_reloads
PARAMS ((rtx
, rtx
));
430 static void delete_address_reloads_1
PARAMS ((rtx
, rtx
, rtx
));
431 static rtx inc_for_reload
PARAMS ((rtx
, rtx
, rtx
, int));
432 static int constraint_accepts_reg_p
PARAMS ((const char *, rtx
));
433 static void reload_cse_regs_1
PARAMS ((rtx
));
434 static int reload_cse_noop_set_p
PARAMS ((rtx
));
435 static int reload_cse_simplify_set
PARAMS ((rtx
, rtx
));
436 static int reload_cse_simplify_operands
PARAMS ((rtx
));
437 static void reload_combine
PARAMS ((void));
438 static void reload_combine_note_use
PARAMS ((rtx
*, rtx
));
439 static void reload_combine_note_store
PARAMS ((rtx
, rtx
, void *));
440 static void reload_cse_move2add
PARAMS ((rtx
));
441 static void move2add_note_store
PARAMS ((rtx
, rtx
, void *));
443 static void add_auto_inc_notes
PARAMS ((rtx
, rtx
));
445 static rtx gen_mode_int
PARAMS ((enum machine_mode
,
447 static void failed_reload
PARAMS ((rtx
, int));
448 static int set_reload_reg
PARAMS ((int, int));
449 extern void dump_needs
PARAMS ((struct insn_chain
*, FILE *));
451 /* Initialize the reload pass once per compilation. */
458 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
459 Set spill_indirect_levels to the number of levels such addressing is
460 permitted, zero if it is not permitted at all. */
463 = gen_rtx_MEM (Pmode
,
466 LAST_VIRTUAL_REGISTER
+ 1),
468 spill_indirect_levels
= 0;
470 while (memory_address_p (QImode
, tem
))
472 spill_indirect_levels
++;
473 tem
= gen_rtx_MEM (Pmode
, tem
);
476 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
478 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
479 indirect_symref_ok
= memory_address_p (QImode
, tem
);
481 /* See if reg+reg is a valid (and offsettable) address. */
483 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
485 tem
= gen_rtx_PLUS (Pmode
,
486 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
487 gen_rtx_REG (Pmode
, i
));
489 /* This way, we make sure that reg+reg is an offsettable address. */
490 tem
= plus_constant (tem
, 4);
492 if (memory_address_p (QImode
, tem
))
494 double_reg_address_ok
= 1;
499 /* Initialize obstack for our rtl allocation. */
500 gcc_obstack_init (&reload_obstack
);
501 reload_startobj
= (char *) obstack_alloc (&reload_obstack
, 0);
503 INIT_REG_SET (&spilled_pseudos
);
504 INIT_REG_SET (&pseudos_counted
);
507 /* List of insn chains that are currently unused. */
508 static struct insn_chain
*unused_insn_chains
= 0;
510 /* Allocate an empty insn_chain structure. */
514 struct insn_chain
*c
;
516 if (unused_insn_chains
== 0)
518 c
= (struct insn_chain
*)
519 obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
520 INIT_REG_SET (&c
->live_throughout
);
521 INIT_REG_SET (&c
->dead_or_set
);
525 c
= unused_insn_chains
;
526 unused_insn_chains
= c
->next
;
528 c
->is_caller_save_insn
= 0;
529 c
->need_operand_change
= 0;
535 /* Small utility function to set all regs in hard reg set TO which are
536 allocated to pseudos in regset FROM. */
538 compute_use_by_pseudos (to
, from
)
543 EXECUTE_IF_SET_IN_REG_SET
544 (from
, FIRST_PSEUDO_REGISTER
, regno
,
546 int r
= reg_renumber
[regno
];
550 /* reload_combine uses the information from
551 BASIC_BLOCK->global_live_at_start, which might still
552 contain registers that have not actually been allocated
553 since they have an equivalence. */
554 if (! reload_completed
)
559 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
561 SET_HARD_REG_BIT (*to
, r
+ nregs
);
566 /* Global variables used by reload and its subroutines. */
568 /* Set during calculate_needs if an insn needs register elimination. */
569 static int something_needs_elimination
;
570 /* Set during calculate_needs if an insn needs an operand changed. */
571 int something_needs_operands_changed
;
573 /* Nonzero means we couldn't get enough spill regs. */
576 /* Main entry point for the reload pass.
578 FIRST is the first insn of the function being compiled.
580 GLOBAL nonzero means we were called from global_alloc
581 and should attempt to reallocate any pseudoregs that we
582 displace from hard regs we will use for reloads.
583 If GLOBAL is zero, we do not have enough information to do that,
584 so any pseudo reg that is spilled must go to the stack.
586 DUMPFILE is the global-reg debugging dump file stream, or 0.
587 If it is nonzero, messages are written to it to describe
588 which registers are seized as reload regs, which pseudo regs
589 are spilled from them, and where the pseudo regs are reallocated to.
591 Return value is nonzero if reload failed
592 and we must not do any more for this function. */
595 reload (first
, global
, dumpfile
)
602 register struct elim_table
*ep
;
604 /* The two pointers used to track the true location of the memory used
605 for label offsets. */
606 char *real_known_ptr
= NULL_PTR
;
607 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
609 /* Make sure even insns with volatile mem refs are recognizable. */
614 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
616 /* Make sure that the last insn in the chain
617 is not something that needs reloading. */
618 emit_note (NULL_PTR
, NOTE_INSN_DELETED
);
620 /* Enable find_equiv_reg to distinguish insns made by reload. */
621 reload_first_uid
= get_max_uid ();
623 #ifdef SECONDARY_MEMORY_NEEDED
624 /* Initialize the secondary memory table. */
625 clear_secondary_mem ();
628 /* We don't have a stack slot for any spill reg yet. */
629 bzero ((char *) spill_stack_slot
, sizeof spill_stack_slot
);
630 bzero ((char *) spill_stack_slot_width
, sizeof spill_stack_slot_width
);
632 /* Initialize the save area information for caller-save, in case some
636 /* Compute which hard registers are now in use
637 as homes for pseudo registers.
638 This is done here rather than (eg) in global_alloc
639 because this point is reached even if not optimizing. */
640 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
643 /* A function that receives a nonlocal goto must save all call-saved
645 if (current_function_has_nonlocal_label
)
646 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
648 if (! call_used_regs
[i
] && ! fixed_regs
[i
])
649 regs_ever_live
[i
] = 1;
652 /* Find all the pseudo registers that didn't get hard regs
653 but do have known equivalent constants or memory slots.
654 These include parameters (known equivalent to parameter slots)
655 and cse'd or loop-moved constant memory addresses.
657 Record constant equivalents in reg_equiv_constant
658 so they will be substituted by find_reloads.
659 Record memory equivalents in reg_mem_equiv so they can
660 be substituted eventually by altering the REG-rtx's. */
662 reg_equiv_constant
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
663 reg_equiv_memory_loc
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
664 reg_equiv_mem
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
665 reg_equiv_init
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
666 reg_equiv_address
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
667 reg_max_ref_width
= (int *) xcalloc (max_regno
, sizeof (int));
668 reg_old_renumber
= (short *) xcalloc (max_regno
, sizeof (short));
669 bcopy ((PTR
) reg_renumber
, (PTR
) reg_old_renumber
, max_regno
* sizeof (short));
670 pseudo_forbidden_regs
671 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
673 = (HARD_REG_SET
*) xcalloc (max_regno
, sizeof (HARD_REG_SET
));
675 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
677 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
678 Also find all paradoxical subregs and find largest such for each pseudo.
679 On machines with small register classes, record hard registers that
680 are used for user variables. These can never be used for spills.
681 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
682 caller-saved registers must be marked live. */
684 num_eliminable_invariants
= 0;
685 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
687 rtx set
= single_set (insn
);
689 if (GET_CODE (insn
) == NOTE
&& CONST_CALL_P (insn
)
690 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
691 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
692 if (! call_used_regs
[i
])
693 regs_ever_live
[i
] = 1;
695 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
697 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
699 #ifdef LEGITIMATE_PIC_OPERAND_P
700 && (! function_invariant_p (XEXP (note
, 0))
702 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
706 rtx x
= XEXP (note
, 0);
707 i
= REGNO (SET_DEST (set
));
708 if (i
> LAST_VIRTUAL_REGISTER
)
710 if (GET_CODE (x
) == MEM
)
712 /* If the operand is a PLUS, the MEM may be shared,
713 so make sure we have an unshared copy here. */
714 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
717 reg_equiv_memory_loc
[i
] = x
;
719 else if (function_invariant_p (x
))
721 if (GET_CODE (x
) == PLUS
)
723 /* This is PLUS of frame pointer and a constant,
724 and might be shared. Unshare it. */
725 reg_equiv_constant
[i
] = copy_rtx (x
);
726 num_eliminable_invariants
++;
728 else if (x
== frame_pointer_rtx
729 || x
== arg_pointer_rtx
)
731 reg_equiv_constant
[i
] = x
;
732 num_eliminable_invariants
++;
734 else if (LEGITIMATE_CONSTANT_P (x
))
735 reg_equiv_constant
[i
] = x
;
737 reg_equiv_memory_loc
[i
]
738 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
743 /* If this register is being made equivalent to a MEM
744 and the MEM is not SET_SRC, the equivalencing insn
745 is one with the MEM as a SET_DEST and it occurs later.
746 So don't mark this insn now. */
747 if (GET_CODE (x
) != MEM
748 || rtx_equal_p (SET_SRC (set
), x
))
750 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[i
]);
755 /* If this insn is setting a MEM from a register equivalent to it,
756 this is the equivalencing insn. */
757 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
758 && GET_CODE (SET_SRC (set
)) == REG
759 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
760 && rtx_equal_p (SET_DEST (set
),
761 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
762 reg_equiv_init
[REGNO (SET_SRC (set
))]
763 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
764 reg_equiv_init
[REGNO (SET_SRC (set
))]);
766 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
767 scan_paradoxical_subregs (PATTERN (insn
));
772 num_labels
= max_label_num () - get_first_label_num ();
774 /* Allocate the tables used to store offset information at labels. */
775 /* We used to use alloca here, but the size of what it would try to
776 allocate would occasionally cause it to exceed the stack limit and
777 cause a core dump. */
778 real_known_ptr
= xmalloc (num_labels
);
780 = (int (*)[NUM_ELIMINABLE_REGS
])
781 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
783 offsets_known_at
= real_known_ptr
- get_first_label_num ();
785 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
787 /* Alter each pseudo-reg rtx to contain its hard reg number.
788 Assign stack slots to the pseudos that lack hard regs or equivalents.
789 Do not touch virtual registers. */
791 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
794 /* If we have some registers we think can be eliminated, scan all insns to
795 see if there is an insn that sets one of these registers to something
796 other than itself plus a constant. If so, the register cannot be
797 eliminated. Doing this scan here eliminates an extra pass through the
798 main reload loop in the most common case where register elimination
800 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
801 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
802 || GET_CODE (insn
) == CALL_INSN
)
803 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
805 maybe_fix_stack_asms ();
807 insns_need_reload
= 0;
808 something_needs_elimination
= 0;
810 /* Initialize to -1, which means take the first spill register. */
813 /* Spill any hard regs that we know we can't eliminate. */
814 CLEAR_HARD_REG_SET (used_spill_regs
);
815 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
816 if (! ep
->can_eliminate
)
817 spill_hard_reg (ep
->from
, dumpfile
, 1);
819 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
820 if (frame_pointer_needed
)
821 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, dumpfile
, 1);
823 finish_spills (global
, dumpfile
);
825 /* From now on, we may need to generate moves differently. We may also
826 allow modifications of insns which cause them to not be recognized.
827 Any such modifications will be cleaned up during reload itself. */
828 reload_in_progress
= 1;
830 /* This loop scans the entire function each go-round
831 and repeats until one repetition spills no additional hard regs. */
834 int something_changed
;
837 HOST_WIDE_INT starting_frame_size
;
839 /* Round size of stack frame to stack_alignment_needed. This must be done
840 here because the stack size may be a part of the offset computation
841 for register elimination, and there might have been new stack slots
842 created in the last iteration of this loop. */
843 if (cfun
->stack_alignment_needed
)
844 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
846 starting_frame_size
= get_frame_size ();
848 set_initial_elim_offsets ();
849 set_initial_label_offsets ();
851 /* For each pseudo register that has an equivalent location defined,
852 try to eliminate any eliminable registers (such as the frame pointer)
853 assuming initial offsets for the replacement register, which
856 If the resulting location is directly addressable, substitute
857 the MEM we just got directly for the old REG.
859 If it is not addressable but is a constant or the sum of a hard reg
860 and constant, it is probably not addressable because the constant is
861 out of range, in that case record the address; we will generate
862 hairy code to compute the address in a register each time it is
863 needed. Similarly if it is a hard register, but one that is not
864 valid as an address register.
866 If the location is not addressable, but does not have one of the
867 above forms, assign a stack slot. We have to do this to avoid the
868 potential of producing lots of reloads if, e.g., a location involves
869 a pseudo that didn't get a hard register and has an equivalent memory
870 location that also involves a pseudo that didn't get a hard register.
872 Perhaps at some point we will improve reload_when_needed handling
873 so this problem goes away. But that's very hairy. */
875 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
876 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
878 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
880 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
882 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
883 else if (CONSTANT_P (XEXP (x
, 0))
884 || (GET_CODE (XEXP (x
, 0)) == REG
885 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
886 || (GET_CODE (XEXP (x
, 0)) == PLUS
887 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
888 && (REGNO (XEXP (XEXP (x
, 0), 0))
889 < FIRST_PSEUDO_REGISTER
)
890 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
891 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
894 /* Make a new stack slot. Then indicate that something
895 changed so we go back and recompute offsets for
896 eliminable registers because the allocation of memory
897 below might change some offset. reg_equiv_{mem,address}
898 will be set up for this pseudo on the next pass around
900 reg_equiv_memory_loc
[i
] = 0;
901 reg_equiv_init
[i
] = 0;
906 if (caller_save_needed
)
909 /* If we allocated another stack slot, redo elimination bookkeeping. */
910 if (starting_frame_size
!= get_frame_size ())
913 if (caller_save_needed
)
915 save_call_clobbered_regs ();
916 /* That might have allocated new insn_chain structures. */
917 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
920 calculate_needs_all_insns (global
);
922 CLEAR_REG_SET (&spilled_pseudos
);
925 something_changed
= 0;
927 /* If we allocated any new memory locations, make another pass
928 since it might have changed elimination offsets. */
929 if (starting_frame_size
!= get_frame_size ())
930 something_changed
= 1;
933 HARD_REG_SET to_spill
;
934 CLEAR_HARD_REG_SET (to_spill
);
935 update_eliminables (&to_spill
);
936 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
937 if (TEST_HARD_REG_BIT (to_spill
, i
))
939 spill_hard_reg (i
, dumpfile
, 1);
942 /* Regardless of the state of spills, if we previously had
943 a register that we thought we could eliminate, but no can
944 not eliminate, we must run another pass.
946 Consider pseudos which have an entry in reg_equiv_* which
947 reference an eliminable register. We must make another pass
948 to update reg_equiv_* so that we do not substitute in the
949 old value from when we thought the elimination could be
951 something_changed
= 1;
955 select_reload_regs (dumpfile
);
959 if (insns_need_reload
!= 0 || did_spill
)
960 something_changed
|= finish_spills (global
, dumpfile
);
962 if (! something_changed
)
965 if (caller_save_needed
)
966 delete_caller_save_insns ();
968 obstack_free (&reload_obstack
, reload_firstobj
);
971 /* If global-alloc was run, notify it of any register eliminations we have
974 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
975 if (ep
->can_eliminate
)
976 mark_elimination (ep
->from
, ep
->to
);
978 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
979 If that insn didn't set the register (i.e., it copied the register to
980 memory), just delete that insn instead of the equivalencing insn plus
981 anything now dead. If we call delete_dead_insn on that insn, we may
982 delete the insn that actually sets the register if the register dies
983 there and that is incorrect. */
985 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
987 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
990 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
992 rtx equiv_insn
= XEXP (list
, 0);
993 if (GET_CODE (equiv_insn
) == NOTE
)
995 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
996 delete_dead_insn (equiv_insn
);
999 PUT_CODE (equiv_insn
, NOTE
);
1000 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1001 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1007 /* Use the reload registers where necessary
1008 by generating move instructions to move the must-be-register
1009 values into or out of the reload registers. */
1011 if (insns_need_reload
!= 0 || something_needs_elimination
1012 || something_needs_operands_changed
)
1014 int old_frame_size
= get_frame_size ();
1016 reload_as_needed (global
);
1018 if (old_frame_size
!= get_frame_size ())
1022 verify_initial_elim_offsets ();
1025 /* If we were able to eliminate the frame pointer, show that it is no
1026 longer live at the start of any basic block. If it ls live by
1027 virtue of being in a pseudo, that pseudo will be marked live
1028 and hence the frame pointer will be known to be live via that
1031 if (! frame_pointer_needed
)
1032 for (i
= 0; i
< n_basic_blocks
; i
++)
1033 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i
)->global_live_at_start
,
1034 HARD_FRAME_POINTER_REGNUM
);
1036 /* Come here (with failure set nonzero) if we can't get enough spill regs
1037 and we decide not to abort about it. */
1040 CLEAR_REG_SET (&spilled_pseudos
);
1041 reload_in_progress
= 0;
1043 /* Now eliminate all pseudo regs by modifying them into
1044 their equivalent memory references.
1045 The REG-rtx's for the pseudos are modified in place,
1046 so all insns that used to refer to them now refer to memory.
1048 For a reg that has a reg_equiv_address, all those insns
1049 were changed by reloading so that no insns refer to it any longer;
1050 but the DECL_RTL of a variable decl may refer to it,
1051 and if so this causes the debugging info to mention the variable. */
1053 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1058 int is_readonly
= 0;
1060 if (reg_equiv_memory_loc
[i
])
1062 in_struct
= MEM_IN_STRUCT_P (reg_equiv_memory_loc
[i
]);
1063 is_scalar
= MEM_SCALAR_P (reg_equiv_memory_loc
[i
]);
1064 is_readonly
= RTX_UNCHANGING_P (reg_equiv_memory_loc
[i
]);
1067 if (reg_equiv_mem
[i
])
1068 addr
= XEXP (reg_equiv_mem
[i
], 0);
1070 if (reg_equiv_address
[i
])
1071 addr
= reg_equiv_address
[i
];
1075 if (reg_renumber
[i
] < 0)
1077 rtx reg
= regno_reg_rtx
[i
];
1078 PUT_CODE (reg
, MEM
);
1079 XEXP (reg
, 0) = addr
;
1080 REG_USERVAR_P (reg
) = 0;
1081 RTX_UNCHANGING_P (reg
) = is_readonly
;
1082 MEM_IN_STRUCT_P (reg
) = in_struct
;
1083 MEM_SCALAR_P (reg
) = is_scalar
;
1084 /* We have no alias information about this newly created
1086 MEM_ALIAS_SET (reg
) = 0;
1088 else if (reg_equiv_mem
[i
])
1089 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1093 /* We must set reload_completed now since the cleanup_subreg_operands call
1094 below will re-recognize each insn and reload may have generated insns
1095 which are only valid during and after reload. */
1096 reload_completed
= 1;
1098 /* Make a pass over all the insns and delete all USEs which we inserted
1099 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1100 notes. Delete all CLOBBER insns that don't refer to the return value
1101 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1102 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1103 and regenerate REG_INC notes that may have been moved around. */
1105 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1106 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1110 if ((GET_CODE (PATTERN (insn
)) == USE
1111 && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1112 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1113 && (GET_CODE (XEXP (PATTERN (insn
), 0)) != REG
1114 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1116 PUT_CODE (insn
, NOTE
);
1117 NOTE_SOURCE_FILE (insn
) = 0;
1118 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1122 pnote
= ®_NOTES (insn
);
1125 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1126 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1127 || REG_NOTE_KIND (*pnote
) == REG_INC
1128 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1129 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1130 *pnote
= XEXP (*pnote
, 1);
1132 pnote
= &XEXP (*pnote
, 1);
1136 add_auto_inc_notes (insn
, PATTERN (insn
));
1139 /* And simplify (subreg (reg)) if it appears as an operand. */
1140 cleanup_subreg_operands (insn
);
1143 /* If we are doing stack checking, give a warning if this function's
1144 frame size is larger than we expect. */
1145 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1147 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1148 static int verbose_warned
= 0;
1150 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1151 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1152 size
+= UNITS_PER_WORD
;
1154 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1156 warning ("frame size too large for reliable stack checking");
1157 if (! verbose_warned
)
1159 warning ("try reducing the number of local variables");
1165 /* Indicate that we no longer have known memory locations or constants. */
1166 if (reg_equiv_constant
)
1167 free (reg_equiv_constant
);
1168 reg_equiv_constant
= 0;
1169 if (reg_equiv_memory_loc
)
1170 free (reg_equiv_memory_loc
);
1171 reg_equiv_memory_loc
= 0;
1174 free (real_known_ptr
);
1178 free (reg_equiv_mem
);
1179 free (reg_equiv_init
);
1180 free (reg_equiv_address
);
1181 free (reg_max_ref_width
);
1182 free (reg_old_renumber
);
1183 free (pseudo_previous_regs
);
1184 free (pseudo_forbidden_regs
);
1186 CLEAR_HARD_REG_SET (used_spill_regs
);
1187 for (i
= 0; i
< n_spills
; i
++)
1188 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1190 /* Free all the insn_chain structures at once. */
1191 obstack_free (&reload_obstack
, reload_startobj
);
1192 unused_insn_chains
= 0;
1197 /* Yet another special case. Unfortunately, reg-stack forces people to
1198 write incorrect clobbers in asm statements. These clobbers must not
1199 cause the register to appear in bad_spill_regs, otherwise we'll call
1200 fatal_insn later. We clear the corresponding regnos in the live
1201 register sets to avoid this.
1202 The whole thing is rather sick, I'm afraid. */
1204 maybe_fix_stack_asms ()
1207 const char *constraints
[MAX_RECOG_OPERANDS
];
1208 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1209 struct insn_chain
*chain
;
1211 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1214 HARD_REG_SET clobbered
, allowed
;
1217 if (GET_RTX_CLASS (GET_CODE (chain
->insn
)) != 'i'
1218 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1220 pat
= PATTERN (chain
->insn
);
1221 if (GET_CODE (pat
) != PARALLEL
)
1224 CLEAR_HARD_REG_SET (clobbered
);
1225 CLEAR_HARD_REG_SET (allowed
);
1227 /* First, make a mask of all stack regs that are clobbered. */
1228 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1230 rtx t
= XVECEXP (pat
, 0, i
);
1231 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1232 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1235 /* Get the operand values and constraints out of the insn. */
1236 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1237 constraints
, operand_mode
);
1239 /* For every operand, see what registers are allowed. */
1240 for (i
= 0; i
< noperands
; i
++)
1242 const char *p
= constraints
[i
];
1243 /* For every alternative, we compute the class of registers allowed
1244 for reloading in CLS, and merge its contents into the reg set
1246 int cls
= (int) NO_REGS
;
1252 if (c
== '\0' || c
== ',' || c
== '#')
1254 /* End of one alternative - mark the regs in the current
1255 class, and reset the class. */
1256 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1261 } while (c
!= '\0' && c
!= ',');
1269 case '=': case '+': case '*': case '%': case '?': case '!':
1270 case '0': case '1': case '2': case '3': case '4': case 'm':
1271 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1272 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1273 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1275 #ifdef EXTRA_CONSTRAINT
1276 case 'Q': case 'R': case 'S': case 'T': case 'U':
1281 cls
= (int) reg_class_subunion
[cls
][(int) BASE_REG_CLASS
];
1286 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1290 cls
= (int) reg_class_subunion
[cls
][(int) REG_CLASS_FROM_LETTER (c
)];
1295 /* Those of the registers which are clobbered, but allowed by the
1296 constraints, must be usable as reload registers. So clear them
1297 out of the life information. */
1298 AND_HARD_REG_SET (allowed
, clobbered
);
1299 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1300 if (TEST_HARD_REG_BIT (allowed
, i
))
1302 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1303 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1310 /* Copy the global variables n_reloads and rld into the corresponding elts
1313 copy_reloads (chain
)
1314 struct insn_chain
*chain
;
1316 chain
->n_reloads
= n_reloads
;
1318 = (struct reload
*) obstack_alloc (&reload_obstack
,
1319 n_reloads
* sizeof (struct reload
));
1320 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1321 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1324 /* Walk the chain of insns, and determine for each whether it needs reloads
1325 and/or eliminations. Build the corresponding insns_need_reload list, and
1326 set something_needs_elimination as appropriate. */
1328 calculate_needs_all_insns (global
)
1331 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1332 struct insn_chain
*chain
;
1334 something_needs_elimination
= 0;
1336 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1337 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1339 rtx insn
= chain
->insn
;
1341 /* Clear out the shortcuts. */
1342 chain
->n_reloads
= 0;
1343 chain
->need_elim
= 0;
1344 chain
->need_reload
= 0;
1345 chain
->need_operand_change
= 0;
1347 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1348 include REG_LABEL), we need to see what effects this has on the
1349 known offsets at labels. */
1351 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1352 || (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1353 && REG_NOTES (insn
) != 0))
1354 set_label_offsets (insn
, insn
, 0);
1356 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1358 rtx old_body
= PATTERN (insn
);
1359 int old_code
= INSN_CODE (insn
);
1360 rtx old_notes
= REG_NOTES (insn
);
1361 int did_elimination
= 0;
1362 int operands_changed
= 0;
1363 rtx set
= single_set (insn
);
1365 /* Skip insns that only set an equivalence. */
1366 if (set
&& GET_CODE (SET_DEST (set
)) == REG
1367 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1368 && reg_equiv_constant
[REGNO (SET_DEST (set
))])
1371 /* If needed, eliminate any eliminable registers. */
1372 if (num_eliminable
|| num_eliminable_invariants
)
1373 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1375 /* Analyze the instruction. */
1376 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1377 global
, spill_reg_order
);
1379 /* If a no-op set needs more than one reload, this is likely
1380 to be something that needs input address reloads. We
1381 can't get rid of this cleanly later, and it is of no use
1382 anyway, so discard it now.
1383 We only do this when expensive_optimizations is enabled,
1384 since this complements reload inheritance / output
1385 reload deletion, and it can make debugging harder. */
1386 if (flag_expensive_optimizations
&& n_reloads
> 1)
1388 rtx set
= single_set (insn
);
1390 && SET_SRC (set
) == SET_DEST (set
)
1391 && GET_CODE (SET_SRC (set
)) == REG
1392 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1394 PUT_CODE (insn
, NOTE
);
1395 NOTE_SOURCE_FILE (insn
) = 0;
1396 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1401 update_eliminable_offsets ();
1403 /* Remember for later shortcuts which insns had any reloads or
1404 register eliminations. */
1405 chain
->need_elim
= did_elimination
;
1406 chain
->need_reload
= n_reloads
> 0;
1407 chain
->need_operand_change
= operands_changed
;
1409 /* Discard any register replacements done. */
1410 if (did_elimination
)
1412 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1413 PATTERN (insn
) = old_body
;
1414 INSN_CODE (insn
) = old_code
;
1415 REG_NOTES (insn
) = old_notes
;
1416 something_needs_elimination
= 1;
1419 something_needs_operands_changed
|= operands_changed
;
1423 copy_reloads (chain
);
1424 *pprev_reload
= chain
;
1425 pprev_reload
= &chain
->next_need_reload
;
1432 /* Comparison function for qsort to decide which of two reloads
1433 should be handled first. *P1 and *P2 are the reload numbers. */
1436 reload_reg_class_lower (r1p
, r2p
)
1440 register int r1
= *(const short *)r1p
, r2
= *(const short *)r2p
;
1443 /* Consider required reloads before optional ones. */
1444 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1448 /* Count all solitary classes before non-solitary ones. */
1449 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1450 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1454 /* Aside from solitaires, consider all multi-reg groups first. */
1455 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1459 /* Consider reloads in order of increasing reg-class number. */
1460 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1464 /* If reloads are equally urgent, sort by reload number,
1465 so that the results of qsort leave nothing to chance. */
1469 /* The cost of spilling each hard reg. */
1470 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1472 /* When spilling multiple hard registers, we use SPILL_COST for the first
1473 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1474 only the first hard reg for a multi-reg pseudo. */
1475 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1477 /* Update the spill cost arrays, considering that pseudo REG is live. */
1482 int n_refs
= REG_N_REFS (reg
);
1483 int r
= reg_renumber
[reg
];
1486 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1487 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1490 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1495 spill_add_cost
[r
] += n_refs
;
1497 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1499 spill_cost
[r
+ nregs
] += n_refs
;
1502 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1503 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1505 order_regs_for_reload (chain
)
1506 struct insn_chain
*chain
;
1510 COPY_HARD_REG_SET (bad_spill_regs
, bad_spill_regs_global
);
1512 memset (spill_cost
, 0, sizeof spill_cost
);
1513 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1515 /* Count number of uses of each hard reg by pseudo regs allocated to it
1516 and then order them by decreasing use. */
1518 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1520 /* Test the various reasons why we can't use a register for
1521 spilling in this insn. */
1523 || REGNO_REG_SET_P (&chain
->live_throughout
, i
)
1524 || REGNO_REG_SET_P (&chain
->dead_or_set
, i
))
1525 SET_HARD_REG_BIT (bad_spill_regs
, i
);
1527 /* Now find out which pseudos are allocated to it, and update
1529 CLEAR_REG_SET (&pseudos_counted
);
1531 EXECUTE_IF_SET_IN_REG_SET
1532 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
,
1536 EXECUTE_IF_SET_IN_REG_SET
1537 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
,
1541 CLEAR_REG_SET (&pseudos_counted
);
1544 /* Vector of reload-numbers showing the order in which the reloads should
1546 static short reload_order
[MAX_RELOADS
];
1548 /* This is used to keep track of the spill regs used in one insn. */
1549 static HARD_REG_SET used_spill_regs_local
;
1551 /* We decided to spill hard register SPILLED, which has a size of
1552 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1553 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1554 update SPILL_COST/SPILL_ADD_COST. */
1556 count_spilled_pseudo (spilled
, spilled_nregs
, reg
)
1557 int spilled
, spilled_nregs
, reg
;
1559 int r
= reg_renumber
[reg
];
1560 int nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1562 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1563 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1566 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1568 spill_add_cost
[r
] -= REG_N_REFS (reg
);
1570 spill_cost
[r
+ nregs
] -= REG_N_REFS (reg
);
1573 /* Find reload register to use for reload number ORDER. */
1576 find_reg (chain
, order
, dumpfile
)
1577 struct insn_chain
*chain
;
1581 int rnum
= reload_order
[order
];
1582 struct reload
*rl
= rld
+ rnum
;
1583 int best_cost
= INT_MAX
;
1586 HARD_REG_SET not_usable
;
1587 HARD_REG_SET used_by_other_reload
;
1589 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1590 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1591 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1593 CLEAR_HARD_REG_SET (used_by_other_reload
);
1594 for (i
= 0; i
< order
; i
++)
1596 int other
= reload_order
[i
];
1597 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1598 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1599 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1602 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1605 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1606 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1607 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1609 int this_cost
= spill_cost
[regno
];
1611 int this_nregs
= HARD_REGNO_NREGS (regno
, rl
->mode
);
1613 for (j
= 1; j
< this_nregs
; j
++)
1615 this_cost
+= spill_add_cost
[regno
+ j
];
1616 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1617 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1622 if (rl
->in
&& GET_CODE (rl
->in
) == REG
&& REGNO (rl
->in
) == regno
)
1624 if (rl
->out
&& GET_CODE (rl
->out
) == REG
&& REGNO (rl
->out
) == regno
)
1626 if (this_cost
< best_cost
1627 /* Among registers with equal cost, prefer caller-saved ones, or
1628 use REG_ALLOC_ORDER if it is defined. */
1629 || (this_cost
== best_cost
1630 #ifdef REG_ALLOC_ORDER
1631 && (inv_reg_alloc_order
[regno
]
1632 < inv_reg_alloc_order
[best_reg
])
1634 && call_used_regs
[regno
]
1635 && ! call_used_regs
[best_reg
]
1640 best_cost
= this_cost
;
1647 fprintf (dumpfile
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1648 rl
->nregs
= HARD_REGNO_NREGS (best_reg
, rl
->mode
);
1649 rl
->regno
= best_reg
;
1651 EXECUTE_IF_SET_IN_REG_SET
1652 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
,
1654 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1656 EXECUTE_IF_SET_IN_REG_SET
1657 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
,
1659 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1662 for (i
= 0; i
< rl
->nregs
; i
++)
1664 if (spill_cost
[best_reg
+ i
] != 0
1665 || spill_add_cost
[best_reg
+ i
] != 0)
1667 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1672 /* Find more reload regs to satisfy the remaining need of an insn, which
1674 Do it by ascending class number, since otherwise a reg
1675 might be spilled for a big class and might fail to count
1676 for a smaller class even though it belongs to that class. */
1679 find_reload_regs (chain
, dumpfile
)
1680 struct insn_chain
*chain
;
1685 /* In order to be certain of getting the registers we need,
1686 we must sort the reloads into order of increasing register class.
1687 Then our grabbing of reload registers will parallel the process
1688 that provided the reload registers. */
1689 for (i
= 0; i
< chain
->n_reloads
; i
++)
1691 /* Show whether this reload already has a hard reg. */
1692 if (chain
->rld
[i
].reg_rtx
)
1694 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1695 chain
->rld
[i
].regno
= regno
;
1696 chain
->rld
[i
].nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (chain
->rld
[i
].reg_rtx
));
1699 chain
->rld
[i
].regno
= -1;
1700 reload_order
[i
] = i
;
1703 n_reloads
= chain
->n_reloads
;
1704 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1706 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1709 fprintf (dumpfile
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1711 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1713 /* Compute the order of preference for hard registers to spill. */
1715 order_regs_for_reload (chain
);
1717 for (i
= 0; i
< n_reloads
; i
++)
1719 int r
= reload_order
[i
];
1721 /* Ignore reloads that got marked inoperative. */
1722 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1723 && ! rld
[r
].optional
1724 && rld
[r
].regno
== -1)
1725 if (! find_reg (chain
, i
, dumpfile
))
1727 spill_failure (chain
->insn
, rld
[r
].class);
1733 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1734 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1736 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1740 select_reload_regs (dumpfile
)
1743 struct insn_chain
*chain
;
1745 /* Try to satisfy the needs for each insn. */
1746 for (chain
= insns_need_reload
; chain
!= 0;
1747 chain
= chain
->next_need_reload
)
1748 find_reload_regs (chain
, dumpfile
);
1751 /* Delete all insns that were inserted by emit_caller_save_insns during
1754 delete_caller_save_insns ()
1756 struct insn_chain
*c
= reload_insn_chain
;
1760 while (c
!= 0 && c
->is_caller_save_insn
)
1762 struct insn_chain
*next
= c
->next
;
1765 if (insn
== BLOCK_HEAD (c
->block
))
1766 BLOCK_HEAD (c
->block
) = NEXT_INSN (insn
);
1767 if (insn
== BLOCK_END (c
->block
))
1768 BLOCK_END (c
->block
) = PREV_INSN (insn
);
1769 if (c
== reload_insn_chain
)
1770 reload_insn_chain
= next
;
1772 if (NEXT_INSN (insn
) != 0)
1773 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1774 if (PREV_INSN (insn
) != 0)
1775 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1778 next
->prev
= c
->prev
;
1780 c
->prev
->next
= next
;
1781 c
->next
= unused_insn_chains
;
1782 unused_insn_chains
= c
;
1790 /* Handle the failure to find a register to spill.
1791 INSN should be one of the insns which needed this particular spill reg. */
1794 spill_failure (insn
, class)
1796 enum reg_class
class;
1798 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1799 if (asm_noperands (PATTERN (insn
)) >= 0)
1800 error_for_asm (insn
, "Can't find a register in class `%s' while reloading `asm'.",
1801 reg_class_names
[class]);
1804 error ("Unable to find a register to spill in class `%s'.",
1805 reg_class_names
[class]);
1806 fatal_insn ("This is the insn:", insn
);
1810 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1811 data that is dead in INSN. */
1814 delete_dead_insn (insn
)
1817 rtx prev
= prev_real_insn (insn
);
1820 /* If the previous insn sets a register that dies in our insn, delete it
1822 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
1823 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
1824 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
1825 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
1826 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
1827 delete_dead_insn (prev
);
1829 PUT_CODE (insn
, NOTE
);
1830 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1831 NOTE_SOURCE_FILE (insn
) = 0;
1834 /* Modify the home of pseudo-reg I.
1835 The new home is present in reg_renumber[I].
1837 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1838 or it may be -1, meaning there is none or it is not relevant.
1839 This is used so that all pseudos spilled from a given hard reg
1840 can share one stack slot. */
1843 alter_reg (i
, from_reg
)
1847 /* When outputting an inline function, this can happen
1848 for a reg that isn't actually used. */
1849 if (regno_reg_rtx
[i
] == 0)
1852 /* If the reg got changed to a MEM at rtl-generation time,
1854 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
1857 /* Modify the reg-rtx to contain the new hard reg
1858 number or else to contain its pseudo reg number. */
1859 REGNO (regno_reg_rtx
[i
])
1860 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
1862 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1863 allocate a stack slot for it. */
1865 if (reg_renumber
[i
] < 0
1866 && REG_N_REFS (i
) > 0
1867 && reg_equiv_constant
[i
] == 0
1868 && reg_equiv_memory_loc
[i
] == 0)
1871 int inherent_size
= PSEUDO_REGNO_BYTES (i
);
1872 int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
1875 /* Each pseudo reg has an inherent size which comes from its own mode,
1876 and a total size which provides room for paradoxical subregs
1877 which refer to the pseudo reg in wider modes.
1879 We can use a slot already allocated if it provides both
1880 enough inherent space and enough total space.
1881 Otherwise, we allocate a new slot, making sure that it has no less
1882 inherent space, and no less total space, then the previous slot. */
1885 /* No known place to spill from => no slot to reuse. */
1886 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
1887 inherent_size
== total_size
? 0 : -1);
1888 if (BYTES_BIG_ENDIAN
)
1889 /* Cancel the big-endian correction done in assign_stack_local.
1890 Get the address of the beginning of the slot.
1891 This is so we can do a big-endian correction unconditionally
1893 adjust
= inherent_size
- total_size
;
1895 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
1897 /* Reuse a stack slot if possible. */
1898 else if (spill_stack_slot
[from_reg
] != 0
1899 && spill_stack_slot_width
[from_reg
] >= total_size
1900 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
1902 x
= spill_stack_slot
[from_reg
];
1903 /* Allocate a bigger slot. */
1906 /* Compute maximum size needed, both for inherent size
1907 and for total size. */
1908 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
1910 if (spill_stack_slot
[from_reg
])
1912 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
1914 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
1915 if (spill_stack_slot_width
[from_reg
] > total_size
)
1916 total_size
= spill_stack_slot_width
[from_reg
];
1918 /* Make a slot with that size. */
1919 x
= assign_stack_local (mode
, total_size
,
1920 inherent_size
== total_size
? 0 : -1);
1922 if (BYTES_BIG_ENDIAN
)
1924 /* Cancel the big-endian correction done in assign_stack_local.
1925 Get the address of the beginning of the slot.
1926 This is so we can do a big-endian correction unconditionally
1928 adjust
= GET_MODE_SIZE (mode
) - total_size
;
1930 stack_slot
= gen_rtx_MEM (mode_for_size (total_size
1933 plus_constant (XEXP (x
, 0), adjust
));
1935 spill_stack_slot
[from_reg
] = stack_slot
;
1936 spill_stack_slot_width
[from_reg
] = total_size
;
1939 /* On a big endian machine, the "address" of the slot
1940 is the address of the low part that fits its inherent mode. */
1941 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
1942 adjust
+= (total_size
- inherent_size
);
1944 /* If we have any adjustment to make, or if the stack slot is the
1945 wrong mode, make a new stack slot. */
1946 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
1948 x
= gen_rtx_MEM (GET_MODE (regno_reg_rtx
[i
]),
1949 plus_constant (XEXP (x
, 0), adjust
));
1951 /* If this was shared among registers, must ensure we never
1952 set it readonly since that can cause scheduling
1953 problems. Note we would only have in this adjustment
1954 case in any event, since the code above doesn't set it. */
1957 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
1960 /* Save the stack slot for later. */
1961 reg_equiv_memory_loc
[i
] = x
;
1965 /* Mark the slots in regs_ever_live for the hard regs
1966 used by pseudo-reg number REGNO. */
1969 mark_home_live (regno
)
1972 register int i
, lim
;
1973 i
= reg_renumber
[regno
];
1976 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
1978 regs_ever_live
[i
++] = 1;
1981 /* This function handles the tracking of elimination offsets around branches.
1983 X is a piece of RTL being scanned.
1985 INSN is the insn that it came from, if any.
1987 INITIAL_P is non-zero if we are to set the offset to be the initial
1988 offset and zero if we are setting the offset of the label to be the
1992 set_label_offsets (x
, insn
, initial_p
)
1997 enum rtx_code code
= GET_CODE (x
);
2000 struct elim_table
*p
;
2005 if (LABEL_REF_NONLOCAL_P (x
))
2010 /* ... fall through ... */
2013 /* If we know nothing about this label, set the desired offsets. Note
2014 that this sets the offset at a label to be the offset before a label
2015 if we don't know anything about the label. This is not correct for
2016 the label after a BARRIER, but is the best guess we can make. If
2017 we guessed wrong, we will suppress an elimination that might have
2018 been possible had we been able to guess correctly. */
2020 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2022 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2023 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2024 = (initial_p
? reg_eliminate
[i
].initial_offset
2025 : reg_eliminate
[i
].offset
);
2026 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2029 /* Otherwise, if this is the definition of a label and it is
2030 preceded by a BARRIER, set our offsets to the known offset of
2034 && (tem
= prev_nonnote_insn (insn
)) != 0
2035 && GET_CODE (tem
) == BARRIER
)
2036 set_offsets_for_label (insn
);
2038 /* If neither of the above cases is true, compare each offset
2039 with those previously recorded and suppress any eliminations
2040 where the offsets disagree. */
2042 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2043 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2044 != (initial_p
? reg_eliminate
[i
].initial_offset
2045 : reg_eliminate
[i
].offset
))
2046 reg_eliminate
[i
].can_eliminate
= 0;
2051 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2053 /* ... fall through ... */
2057 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2058 and hence must have all eliminations at their initial offsets. */
2059 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2060 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2061 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2066 /* Each of the labels in the address vector must be at their initial
2067 offsets. We want the first field for ADDR_VEC and the second
2068 field for ADDR_DIFF_VEC. */
2070 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2071 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2076 /* We only care about setting PC. If the source is not RETURN,
2077 IF_THEN_ELSE, or a label, disable any eliminations not at
2078 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2079 isn't one of those possibilities. For branches to a label,
2080 call ourselves recursively.
2082 Note that this can disable elimination unnecessarily when we have
2083 a non-local goto since it will look like a non-constant jump to
2084 someplace in the current function. This isn't a significant
2085 problem since such jumps will normally be when all elimination
2086 pairs are back to their initial offsets. */
2088 if (SET_DEST (x
) != pc_rtx
)
2091 switch (GET_CODE (SET_SRC (x
)))
2098 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2102 tem
= XEXP (SET_SRC (x
), 1);
2103 if (GET_CODE (tem
) == LABEL_REF
)
2104 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2105 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2108 tem
= XEXP (SET_SRC (x
), 2);
2109 if (GET_CODE (tem
) == LABEL_REF
)
2110 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2111 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2119 /* If we reach here, all eliminations must be at their initial
2120 offset because we are doing a jump to a variable address. */
2121 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2122 if (p
->offset
!= p
->initial_offset
)
2123 p
->can_eliminate
= 0;
2131 /* Scan X and replace any eliminable registers (such as fp) with a
2132 replacement (such as sp), plus an offset.
2134 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2135 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2136 MEM, we are allowed to replace a sum of a register and the constant zero
2137 with the register, which we cannot do outside a MEM. In addition, we need
2138 to record the fact that a register is referenced outside a MEM.
2140 If INSN is an insn, it is the insn containing X. If we replace a REG
2141 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2142 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2143 the REG is being modified.
2145 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2146 That's used when we eliminate in expressions stored in notes.
2147 This means, do not set ref_outside_mem even if the reference
2150 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2151 replacements done assuming all offsets are at their initial values. If
2152 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2153 encounter, return the actual location so that find_reloads will do
2154 the proper thing. */
2157 eliminate_regs (x
, mem_mode
, insn
)
2159 enum machine_mode mem_mode
;
2162 enum rtx_code code
= GET_CODE (x
);
2163 struct elim_table
*ep
;
2170 if (! current_function_decl
)
2189 /* This is only for the benefit of the debugging backends, which call
2190 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2191 removed after CSE. */
2192 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2193 if (GET_CODE (new) == MEM
)
2194 return XEXP (new, 0);
2200 /* First handle the case where we encounter a bare register that
2201 is eliminable. Replace it with a PLUS. */
2202 if (regno
< FIRST_PSEUDO_REGISTER
)
2204 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2206 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2207 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2210 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2211 && reg_equiv_constant
[regno
]
2212 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2213 return eliminate_regs (copy_rtx (reg_equiv_constant
[regno
]),
2217 /* You might think handling MINUS in a manner similar to PLUS is a
2218 good idea. It is not. It has been tried multiple times and every
2219 time the change has had to have been reverted.
2221 Other parts of reload know a PLUS is special (gen_reload for example)
2222 and require special code to handle code a reloaded PLUS operand.
2224 Also consider backends where the flags register is clobbered by a
2225 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2226 lea instruction comes to mind). If we try to reload a MINUS, we
2227 may kill the flags register that was holding a useful value.
2229 So, please before trying to handle MINUS, consider reload as a
2230 whole instead of this little section as well as the backend issues. */
2232 /* If this is the sum of an eliminable register and a constant, rework
2234 if (GET_CODE (XEXP (x
, 0)) == REG
2235 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2236 && CONSTANT_P (XEXP (x
, 1)))
2238 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2240 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2242 /* The only time we want to replace a PLUS with a REG (this
2243 occurs when the constant operand of the PLUS is the negative
2244 of the offset) is when we are inside a MEM. We won't want
2245 to do so at other times because that would change the
2246 structure of the insn in a way that reload can't handle.
2247 We special-case the commonest situation in
2248 eliminate_regs_in_insn, so just replace a PLUS with a
2249 PLUS here, unless inside a MEM. */
2250 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2251 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2254 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2255 plus_constant (XEXP (x
, 1),
2256 ep
->previous_offset
));
2259 /* If the register is not eliminable, we are done since the other
2260 operand is a constant. */
2264 /* If this is part of an address, we want to bring any constant to the
2265 outermost PLUS. We will do this by doing register replacement in
2266 our operands and seeing if a constant shows up in one of them.
2268 Note that there is no risk of modifying the structure of the insn,
2269 since we only get called for its operands, thus we are either
2270 modifying the address inside a MEM, or something like an address
2271 operand of a load-address insn. */
2274 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2275 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2277 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2279 /* If one side is a PLUS and the other side is a pseudo that
2280 didn't get a hard register but has a reg_equiv_constant,
2281 we must replace the constant here since it may no longer
2282 be in the position of any operand. */
2283 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2284 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2285 && reg_renumber
[REGNO (new1
)] < 0
2286 && reg_equiv_constant
!= 0
2287 && reg_equiv_constant
[REGNO (new1
)] != 0)
2288 new1
= reg_equiv_constant
[REGNO (new1
)];
2289 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2290 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2291 && reg_renumber
[REGNO (new0
)] < 0
2292 && reg_equiv_constant
[REGNO (new0
)] != 0)
2293 new0
= reg_equiv_constant
[REGNO (new0
)];
2295 new = form_sum (new0
, new1
);
2297 /* As above, if we are not inside a MEM we do not want to
2298 turn a PLUS into something else. We might try to do so here
2299 for an addition of 0 if we aren't optimizing. */
2300 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2301 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2309 /* If this is the product of an eliminable register and a
2310 constant, apply the distribute law and move the constant out
2311 so that we have (plus (mult ..) ..). This is needed in order
2312 to keep load-address insns valid. This case is pathological.
2313 We ignore the possibility of overflow here. */
2314 if (GET_CODE (XEXP (x
, 0)) == REG
2315 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2316 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2317 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2319 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2322 /* Refs inside notes don't count for this purpose. */
2323 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2324 || GET_CODE (insn
) == INSN_LIST
)))
2325 ep
->ref_outside_mem
= 1;
2328 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2329 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2332 /* ... fall through ... */
2336 /* See comments before PLUS about handling MINUS. */
2338 case DIV
: case UDIV
:
2339 case MOD
: case UMOD
:
2340 case AND
: case IOR
: case XOR
:
2341 case ROTATERT
: case ROTATE
:
2342 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2344 case GE
: case GT
: case GEU
: case GTU
:
2345 case LE
: case LT
: case LEU
: case LTU
:
2347 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2349 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2351 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2352 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2357 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2360 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2361 if (new != XEXP (x
, 0))
2363 /* If this is a REG_DEAD note, it is not valid anymore.
2364 Using the eliminated version could result in creating a
2365 REG_DEAD note for the stack or frame pointer. */
2366 if (GET_MODE (x
) == REG_DEAD
)
2368 ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
)
2371 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2375 /* ... fall through ... */
2378 /* Now do eliminations in the rest of the chain. If this was
2379 an EXPR_LIST, this might result in allocating more memory than is
2380 strictly needed, but it simplifies the code. */
2383 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2384 if (new != XEXP (x
, 1))
2385 return gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2393 case STRICT_LOW_PART
:
2395 case SIGN_EXTEND
: case ZERO_EXTEND
:
2396 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2397 case FLOAT
: case FIX
:
2398 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2402 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2403 if (new != XEXP (x
, 0))
2404 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2408 /* Similar to above processing, but preserve SUBREG_WORD.
2409 Convert (subreg (mem)) to (mem) if not paradoxical.
2410 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2411 pseudo didn't get a hard reg, we must replace this with the
2412 eliminated version of the memory location because push_reloads
2413 may do the replacement in certain circumstances. */
2414 if (GET_CODE (SUBREG_REG (x
)) == REG
2415 && (GET_MODE_SIZE (GET_MODE (x
))
2416 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2417 && reg_equiv_memory_loc
!= 0
2418 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2420 new = SUBREG_REG (x
);
2423 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
2425 if (new != XEXP (x
, 0))
2427 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2428 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2430 if (GET_CODE (new) == MEM
2431 && ((x_size
< new_size
2432 #ifdef WORD_REGISTER_OPERATIONS
2433 /* On these machines, combine can create rtl of the form
2434 (set (subreg:m1 (reg:m2 R) 0) ...)
2435 where m1 < m2, and expects something interesting to
2436 happen to the entire word. Moreover, it will use the
2437 (reg:m2 R) later, expecting all bits to be preserved.
2438 So if the number of words is the same, preserve the
2439 subreg so that push_reloads can see it. */
2440 && ! ((x_size
-1)/UNITS_PER_WORD
== (new_size
-1)/UNITS_PER_WORD
)
2443 || (x_size
== new_size
))
2446 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
2447 enum machine_mode mode
= GET_MODE (x
);
2449 if (BYTES_BIG_ENDIAN
)
2450 offset
+= (MIN (UNITS_PER_WORD
,
2451 GET_MODE_SIZE (GET_MODE (new)))
2452 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
2454 PUT_MODE (new, mode
);
2455 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
2459 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_WORD (x
));
2465 /* This is only for the benefit of the debugging backends, which call
2466 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2467 removed after CSE. */
2468 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2469 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
2471 /* Our only special processing is to pass the mode of the MEM to our
2472 recursive call and copy the flags. While we are here, handle this
2473 case more efficiently. */
2474 new = eliminate_regs (XEXP (x
, 0), GET_MODE (x
), insn
);
2475 if (new != XEXP (x
, 0))
2477 new = gen_rtx_MEM (GET_MODE (x
), new);
2478 new->volatil
= x
->volatil
;
2479 new->unchanging
= x
->unchanging
;
2480 new->in_struct
= x
->in_struct
;
2496 /* Process each of our operands recursively. If any have changed, make a
2498 fmt
= GET_RTX_FORMAT (code
);
2499 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2503 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
2504 if (new != XEXP (x
, i
) && ! copied
)
2506 rtx new_x
= rtx_alloc (code
);
2507 bcopy ((char *) x
, (char *) new_x
,
2508 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2509 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
2515 else if (*fmt
== 'E')
2518 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2520 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
2521 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2523 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2527 rtx new_x
= rtx_alloc (code
);
2528 bcopy ((char *) x
, (char *) new_x
,
2529 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2530 + (sizeof (new_x
->fld
[0])
2531 * GET_RTX_LENGTH (code
))));
2535 XVEC (x
, i
) = new_v
;
2538 XVECEXP (x
, i
, j
) = new;
2546 /* Scan rtx X for modifications of elimination target registers. Update
2547 the table of eliminables to reflect the changed state. MEM_MODE is
2548 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2551 elimination_effects (x
, mem_mode
)
2553 enum machine_mode mem_mode
;
2556 enum rtx_code code
= GET_CODE (x
);
2557 struct elim_table
*ep
;
2583 /* First handle the case where we encounter a bare register that
2584 is eliminable. Replace it with a PLUS. */
2585 if (regno
< FIRST_PSEUDO_REGISTER
)
2587 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2589 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2592 ep
->ref_outside_mem
= 1;
2597 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2598 && reg_equiv_constant
[regno
]
2599 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2600 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2607 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2608 if (ep
->to_rtx
== XEXP (x
, 0))
2610 int size
= GET_MODE_SIZE (mem_mode
);
2612 /* If more bytes than MEM_MODE are pushed, account for them. */
2613 #ifdef PUSH_ROUNDING
2614 if (ep
->to_rtx
== stack_pointer_rtx
)
2615 size
= PUSH_ROUNDING (size
);
2617 if (code
== PRE_DEC
|| code
== POST_DEC
)
2623 /* Fall through to generic unary operation case. */
2624 case STRICT_LOW_PART
:
2626 case SIGN_EXTEND
: case ZERO_EXTEND
:
2627 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2628 case FLOAT
: case FIX
:
2629 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2633 elimination_effects (XEXP (x
, 0), mem_mode
);
2637 if (GET_CODE (SUBREG_REG (x
)) == REG
2638 && (GET_MODE_SIZE (GET_MODE (x
))
2639 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2640 && reg_equiv_memory_loc
!= 0
2641 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2644 elimination_effects (SUBREG_REG (x
), mem_mode
);
2648 /* If using a register that is the source of an eliminate we still
2649 think can be performed, note it cannot be performed since we don't
2650 know how this register is used. */
2651 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2652 if (ep
->from_rtx
== XEXP (x
, 0))
2653 ep
->can_eliminate
= 0;
2655 elimination_effects (XEXP (x
, 0), mem_mode
);
2659 /* If clobbering a register that is the replacement register for an
2660 elimination we still think can be performed, note that it cannot
2661 be performed. Otherwise, we need not be concerned about it. */
2662 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2663 if (ep
->to_rtx
== XEXP (x
, 0))
2664 ep
->can_eliminate
= 0;
2666 elimination_effects (XEXP (x
, 0), mem_mode
);
2670 /* Check for setting a register that we know about. */
2671 if (GET_CODE (SET_DEST (x
)) == REG
)
2673 /* See if this is setting the replacement register for an
2676 If DEST is the hard frame pointer, we do nothing because we
2677 assume that all assignments to the frame pointer are for
2678 non-local gotos and are being done at a time when they are valid
2679 and do not disturb anything else. Some machines want to
2680 eliminate a fake argument pointer (or even a fake frame pointer)
2681 with either the real frame or the stack pointer. Assignments to
2682 the hard frame pointer must not prevent this elimination. */
2684 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2686 if (ep
->to_rtx
== SET_DEST (x
)
2687 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2689 /* If it is being incremented, adjust the offset. Otherwise,
2690 this elimination can't be done. */
2691 rtx src
= SET_SRC (x
);
2693 if (GET_CODE (src
) == PLUS
2694 && XEXP (src
, 0) == SET_DEST (x
)
2695 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2696 ep
->offset
-= INTVAL (XEXP (src
, 1));
2698 ep
->can_eliminate
= 0;
2702 elimination_effects (SET_DEST (x
), 0);
2703 elimination_effects (SET_SRC (x
), 0);
2707 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2710 /* Our only special processing is to pass the mode of the MEM to our
2712 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2719 fmt
= GET_RTX_FORMAT (code
);
2720 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2723 elimination_effects (XEXP (x
, i
), mem_mode
);
2724 else if (*fmt
== 'E')
2725 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2726 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2730 /* Descend through rtx X and verify that no references to eliminable registers
2731 remain. If any do remain, mark the involved register as not
2734 check_eliminable_occurrences (x
)
2744 code
= GET_CODE (x
);
2746 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2748 struct elim_table
*ep
;
2750 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2751 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2752 ep
->can_eliminate
= 0;
2756 fmt
= GET_RTX_FORMAT (code
);
2757 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2760 check_eliminable_occurrences (XEXP (x
, i
));
2761 else if (*fmt
== 'E')
2764 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2765 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2770 /* Scan INSN and eliminate all eliminable registers in it.
2772 If REPLACE is nonzero, do the replacement destructively. Also
2773 delete the insn as dead it if it is setting an eliminable register.
2775 If REPLACE is zero, do all our allocations in reload_obstack.
2777 If no eliminations were done and this insn doesn't require any elimination
2778 processing (these are not identical conditions: it might be updating sp,
2779 but not referencing fp; this needs to be seen during reload_as_needed so
2780 that the offset between fp and sp can be taken into consideration), zero
2781 is returned. Otherwise, 1 is returned. */
2784 eliminate_regs_in_insn (insn
, replace
)
2788 int icode
= recog_memoized (insn
);
2789 rtx old_body
= PATTERN (insn
);
2790 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2791 rtx old_set
= single_set (insn
);
2795 rtx substed_operand
[MAX_RECOG_OPERANDS
];
2796 rtx orig_operand
[MAX_RECOG_OPERANDS
];
2797 struct elim_table
*ep
;
2799 if (! insn_is_asm
&& icode
< 0)
2801 if (GET_CODE (PATTERN (insn
)) == USE
2802 || GET_CODE (PATTERN (insn
)) == CLOBBER
2803 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
2804 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
2805 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
)
2811 push_obstacks (&reload_obstack
, &reload_obstack
);
2813 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
2814 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
2816 /* Check for setting an eliminable register. */
2817 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2818 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
2820 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2821 /* If this is setting the frame pointer register to the
2822 hardware frame pointer register and this is an elimination
2823 that will be done (tested above), this insn is really
2824 adjusting the frame pointer downward to compensate for
2825 the adjustment done before a nonlocal goto. */
2826 if (ep
->from
== FRAME_POINTER_REGNUM
2827 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
2829 rtx src
= SET_SRC (old_set
);
2830 int offset
= 0, ok
= 0;
2831 rtx prev_insn
, prev_set
;
2833 if (src
== ep
->to_rtx
)
2835 else if (GET_CODE (src
) == PLUS
2836 && GET_CODE (XEXP (src
, 0)) == CONST_INT
2837 && XEXP (src
, 1) == ep
->to_rtx
)
2838 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
2839 else if (GET_CODE (src
) == PLUS
2840 && GET_CODE (XEXP (src
, 1)) == CONST_INT
2841 && XEXP (src
, 0) == ep
->to_rtx
)
2842 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
2843 else if ((prev_insn
= prev_nonnote_insn (insn
)) != 0
2844 && (prev_set
= single_set (prev_insn
)) != 0
2845 && rtx_equal_p (SET_DEST (prev_set
), src
))
2847 src
= SET_SRC (prev_set
);
2848 if (src
== ep
->to_rtx
)
2850 else if (GET_CODE (src
) == PLUS
2851 && GET_CODE (XEXP (src
, 0)) == CONST_INT
2852 && XEXP (src
, 1) == ep
->to_rtx
)
2853 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
2854 else if (GET_CODE (src
) == PLUS
2855 && GET_CODE (XEXP (src
, 1)) == CONST_INT
2856 && XEXP (src
, 0) == ep
->to_rtx
)
2857 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
2865 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
2867 /* First see if this insn remains valid when we
2868 make the change. If not, keep the INSN_CODE
2869 the same and let reload fit it up. */
2870 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
2871 validate_change (insn
, &SET_DEST (old_set
),
2873 if (! apply_change_group ())
2875 SET_SRC (old_set
) = src
;
2876 SET_DEST (old_set
) = ep
->to_rtx
;
2886 /* In this case this insn isn't serving a useful purpose. We
2887 will delete it in reload_as_needed once we know that this
2888 elimination is, in fact, being done.
2890 If REPLACE isn't set, we can't delete this insn, but needn't
2891 process it since it won't be used unless something changes. */
2894 delete_dead_insn (insn
);
2902 /* We allow one special case which happens to work on all machines we
2903 currently support: a single set with the source being a PLUS of an
2904 eliminable register and a constant. */
2906 && GET_CODE (SET_SRC (old_set
)) == PLUS
2907 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
2908 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
2909 && REGNO (XEXP (SET_SRC (old_set
), 0)) < FIRST_PSEUDO_REGISTER
)
2911 rtx reg
= XEXP (SET_SRC (old_set
), 0);
2912 int offset
= INTVAL (XEXP (SET_SRC (old_set
), 1));
2914 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2915 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
2917 offset
+= ep
->offset
;
2921 /* We assume here that we don't need a PARALLEL of
2922 any CLOBBERs for this assignment. There's not
2923 much we can do if we do need it. */
2924 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
2927 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, 0);
2928 if (INSN_CODE (insn
) < 0)
2933 new_body
= old_body
;
2936 new_body
= copy_insn (old_body
);
2937 if (REG_NOTES (insn
))
2938 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
2940 PATTERN (insn
) = new_body
;
2941 old_set
= single_set (insn
);
2943 XEXP (SET_SRC (old_set
), 0) = ep
->to_rtx
;
2944 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
2947 /* This can't have an effect on elimination offsets, so skip right
2953 /* Determine the effects of this insn on elimination offsets. */
2954 elimination_effects (old_body
, 0);
2956 /* Eliminate all eliminable registers occurring in operands that
2957 can be handled by reload. */
2958 extract_insn (insn
);
2960 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2962 orig_operand
[i
] = recog_data
.operand
[i
];
2963 substed_operand
[i
] = recog_data
.operand
[i
];
2965 /* For an asm statement, every operand is eliminable. */
2966 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
2968 /* Check for setting a register that we know about. */
2969 if (recog_data
.operand_type
[i
] != OP_IN
2970 && GET_CODE (orig_operand
[i
]) == REG
)
2972 /* If we are assigning to a register that can be eliminated, it
2973 must be as part of a PARALLEL, since the code above handles
2974 single SETs. We must indicate that we can no longer
2975 eliminate this reg. */
2976 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2978 if (ep
->from_rtx
== orig_operand
[i
] && ep
->can_eliminate
)
2979 ep
->can_eliminate
= 0;
2982 substed_operand
[i
] = eliminate_regs (recog_data
.operand
[i
], 0,
2983 replace
? insn
: NULL_RTX
);
2984 if (substed_operand
[i
] != orig_operand
[i
])
2985 val
= any_changes
= 1;
2986 /* Terminate the search in check_eliminable_occurrences at
2988 *recog_data
.operand_loc
[i
] = 0;
2990 /* If an output operand changed from a REG to a MEM and INSN is an
2991 insn, write a CLOBBER insn. */
2992 if (recog_data
.operand_type
[i
] != OP_IN
2993 && GET_CODE (orig_operand
[i
]) == REG
2994 && GET_CODE (substed_operand
[i
]) == MEM
2996 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3001 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3002 *recog_data
.dup_loc
[i
]
3003 = *recog_data
.operand_loc
[(int)recog_data
.dup_num
[i
]];
3005 /* If any eliminable remain, they aren't eliminable anymore. */
3006 check_eliminable_occurrences (old_body
);
3008 /* Substitute the operands; the new values are in the substed_operand
3010 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3011 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3012 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3013 *recog_data
.dup_loc
[i
] = substed_operand
[(int)recog_data
.dup_num
[i
]];
3015 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3016 re-recognize the insn. We do this in case we had a simple addition
3017 but now can do this as a load-address. This saves an insn in this
3019 If re-recognition fails, the old insn code number will still be used,
3020 and some register operands may have changed into PLUS expressions.
3021 These will be handled by find_reloads by loading them into a register
3026 /* If we aren't replacing things permanently and we changed something,
3027 make another copy to ensure that all the RTL is new. Otherwise
3028 things can go wrong if find_reload swaps commutative operands
3029 and one is inside RTL that has been copied while the other is not. */
3030 new_body
= old_body
;
3033 new_body
= copy_insn (old_body
);
3034 if (REG_NOTES (insn
))
3035 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3037 PATTERN (insn
) = new_body
;
3039 /* If we had a move insn but now we don't, rerecognize it. This will
3040 cause spurious re-recognition if the old move had a PARALLEL since
3041 the new one still will, but we can't call single_set without
3042 having put NEW_BODY into the insn and the re-recognition won't
3043 hurt in this rare case. */
3044 /* ??? Why this huge if statement - why don't we just rerecognize the
3048 && ((GET_CODE (SET_SRC (old_set
)) == REG
3049 && (GET_CODE (new_body
) != SET
3050 || GET_CODE (SET_SRC (new_body
)) != REG
))
3051 /* If this was a load from or store to memory, compare
3052 the MEM in recog_data.operand to the one in the insn.
3053 If they are not equal, then rerecognize the insn. */
3055 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3056 && SET_SRC (old_set
) != recog_data
.operand
[1])
3057 || (GET_CODE (SET_DEST (old_set
)) == MEM
3058 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3059 /* If this was an add insn before, rerecognize. */
3060 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3062 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3064 INSN_CODE (insn
) = icode
;
3068 /* Restore the old body. If there were any changes to it, we made a copy
3069 of it while the changes were still in place, so we'll correctly return
3070 a modified insn below. */
3073 /* Restore the old body. */
3074 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3075 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3076 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3077 *recog_data
.dup_loc
[i
] = orig_operand
[(int)recog_data
.dup_num
[i
]];
3080 /* Update all elimination pairs to reflect the status after the current
3081 insn. The changes we make were determined by the earlier call to
3082 elimination_effects.
3084 We also detect a cases where register elimination cannot be done,
3085 namely, if a register would be both changed and referenced outside a MEM
3086 in the resulting insn since such an insn is often undefined and, even if
3087 not, we cannot know what meaning will be given to it. Note that it is
3088 valid to have a register used in an address in an insn that changes it
3089 (presumably with a pre- or post-increment or decrement).
3091 If anything changes, return nonzero. */
3093 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3095 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3096 ep
->can_eliminate
= 0;
3098 ep
->ref_outside_mem
= 0;
3100 if (ep
->previous_offset
!= ep
->offset
)
3105 /* If we changed something, perform elimination in REG_NOTES. This is
3106 needed even when REPLACE is zero because a REG_DEAD note might refer
3107 to a register that we eliminate and could cause a different number
3108 of spill registers to be needed in the final reload pass than in
3110 if (val
&& REG_NOTES (insn
) != 0)
3111 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3119 /* Loop through all elimination pairs.
3120 Recalculate the number not at initial offset.
3122 Compute the maximum offset (minimum offset if the stack does not
3123 grow downward) for each elimination pair. */
3126 update_eliminable_offsets ()
3128 struct elim_table
*ep
;
3130 num_not_at_initial_offset
= 0;
3131 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3133 ep
->previous_offset
= ep
->offset
;
3134 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3135 num_not_at_initial_offset
++;
3139 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3140 replacement we currently believe is valid, mark it as not eliminable if X
3141 modifies DEST in any way other than by adding a constant integer to it.
3143 If DEST is the frame pointer, we do nothing because we assume that
3144 all assignments to the hard frame pointer are nonlocal gotos and are being
3145 done at a time when they are valid and do not disturb anything else.
3146 Some machines want to eliminate a fake argument pointer with either the
3147 frame or stack pointer. Assignments to the hard frame pointer must not
3148 prevent this elimination.
3150 Called via note_stores from reload before starting its passes to scan
3151 the insns of the function. */
3154 mark_not_eliminable (dest
, x
, data
)
3157 void *data ATTRIBUTE_UNUSED
;
3159 register unsigned int i
;
3161 /* A SUBREG of a hard register here is just changing its mode. We should
3162 not see a SUBREG of an eliminable hard register, but check just in
3164 if (GET_CODE (dest
) == SUBREG
)
3165 dest
= SUBREG_REG (dest
);
3167 if (dest
== hard_frame_pointer_rtx
)
3170 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3171 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3172 && (GET_CODE (x
) != SET
3173 || GET_CODE (SET_SRC (x
)) != PLUS
3174 || XEXP (SET_SRC (x
), 0) != dest
3175 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3177 reg_eliminate
[i
].can_eliminate_previous
3178 = reg_eliminate
[i
].can_eliminate
= 0;
3183 /* Verify that the initial elimination offsets did not change since the
3184 last call to set_initial_elim_offsets. This is used to catch cases
3185 where something illegal happened during reload_as_needed that could
3186 cause incorrect code to be generated if we did not check for it. */
3189 verify_initial_elim_offsets ()
3193 #ifdef ELIMINABLE_REGS
3194 struct elim_table
*ep
;
3196 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3198 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3199 if (t
!= ep
->initial_offset
)
3203 INITIAL_FRAME_POINTER_OFFSET (t
);
3204 if (t
!= reg_eliminate
[0].initial_offset
)
3209 /* Reset all offsets on eliminable registers to their initial values. */
3211 set_initial_elim_offsets ()
3213 struct elim_table
*ep
= reg_eliminate
;
3215 #ifdef ELIMINABLE_REGS
3216 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3218 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3219 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3222 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3223 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3226 num_not_at_initial_offset
= 0;
3229 /* Initialize the known label offsets.
3230 Set a known offset for each forced label to be at the initial offset
3231 of each elimination. We do this because we assume that all
3232 computed jumps occur from a location where each elimination is
3233 at its initial offset.
3234 For all other labels, show that we don't know the offsets. */
3237 set_initial_label_offsets ()
3240 bzero ((char *) &offsets_known_at
[get_first_label_num ()], num_labels
);
3242 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3244 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3247 /* Set all elimination offsets to the known values for the code label given
3250 set_offsets_for_label (insn
)
3254 int label_nr
= CODE_LABEL_NUMBER (insn
);
3255 struct elim_table
*ep
;
3257 num_not_at_initial_offset
= 0;
3258 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3260 ep
->offset
= ep
->previous_offset
= offsets_at
[label_nr
][i
];
3261 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3262 num_not_at_initial_offset
++;
3266 /* See if anything that happened changes which eliminations are valid.
3267 For example, on the Sparc, whether or not the frame pointer can
3268 be eliminated can depend on what registers have been used. We need
3269 not check some conditions again (such as flag_omit_frame_pointer)
3270 since they can't have changed. */
3273 update_eliminables (pset
)
3276 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3277 int previous_frame_pointer_needed
= frame_pointer_needed
;
3279 struct elim_table
*ep
;
3281 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3282 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3283 #ifdef ELIMINABLE_REGS
3284 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3287 ep
->can_eliminate
= 0;
3289 /* Look for the case where we have discovered that we can't replace
3290 register A with register B and that means that we will now be
3291 trying to replace register A with register C. This means we can
3292 no longer replace register C with register B and we need to disable
3293 such an elimination, if it exists. This occurs often with A == ap,
3294 B == sp, and C == fp. */
3296 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3298 struct elim_table
*op
;
3299 register int new_to
= -1;
3301 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3303 /* Find the current elimination for ep->from, if there is a
3305 for (op
= reg_eliminate
;
3306 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3307 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3313 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3315 for (op
= reg_eliminate
;
3316 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3317 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3318 op
->can_eliminate
= 0;
3322 /* See if any registers that we thought we could eliminate the previous
3323 time are no longer eliminable. If so, something has changed and we
3324 must spill the register. Also, recompute the number of eliminable
3325 registers and see if the frame pointer is needed; it is if there is
3326 no elimination of the frame pointer that we can perform. */
3328 frame_pointer_needed
= 1;
3329 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3331 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3332 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3333 frame_pointer_needed
= 0;
3335 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3337 ep
->can_eliminate_previous
= 0;
3338 SET_HARD_REG_BIT (*pset
, ep
->from
);
3343 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3344 /* If we didn't need a frame pointer last time, but we do now, spill
3345 the hard frame pointer. */
3346 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3347 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3351 /* Initialize the table of registers to eliminate. */
3355 struct elim_table
*ep
;
3356 #ifdef ELIMINABLE_REGS
3357 struct elim_table_1
*ep1
;
3361 reg_eliminate
= (struct elim_table
*)
3362 xcalloc(sizeof(struct elim_table
), NUM_ELIMINABLE_REGS
);
3364 /* Does this function require a frame pointer? */
3366 frame_pointer_needed
= (! flag_omit_frame_pointer
3367 #ifdef EXIT_IGNORE_STACK
3368 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3369 and restore sp for alloca. So we can't eliminate
3370 the frame pointer in that case. At some point,
3371 we should improve this by emitting the
3372 sp-adjusting insns for this case. */
3373 || (current_function_calls_alloca
3374 && EXIT_IGNORE_STACK
)
3376 || FRAME_POINTER_REQUIRED
);
3380 #ifdef ELIMINABLE_REGS
3381 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3382 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3384 ep
->from
= ep1
->from
;
3386 ep
->can_eliminate
= ep
->can_eliminate_previous
3387 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3388 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3391 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3392 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3393 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3394 = ! frame_pointer_needed
;
3397 /* Count the number of eliminable registers and build the FROM and TO
3398 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3399 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3400 We depend on this. */
3401 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3403 num_eliminable
+= ep
->can_eliminate
;
3404 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3405 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3409 /* Kick all pseudos out of hard register REGNO.
3410 If DUMPFILE is nonzero, log actions taken on that file.
3412 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3413 because we found we can't eliminate some register. In the case, no pseudos
3414 are allowed to be in the register, even if they are only in a block that
3415 doesn't require spill registers, unlike the case when we are spilling this
3416 hard reg to produce another spill register.
3418 Return nonzero if any pseudos needed to be kicked out. */
3421 spill_hard_reg (regno
, dumpfile
, cant_eliminate
)
3423 FILE *dumpfile ATTRIBUTE_UNUSED
;
3430 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3431 regs_ever_live
[regno
] = 1;
3434 /* Spill every pseudo reg that was allocated to this reg
3435 or to something that overlaps this reg. */
3437 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3438 if (reg_renumber
[i
] >= 0
3439 && reg_renumber
[i
] <= regno
3441 + HARD_REGNO_NREGS (reg_renumber
[i
],
3442 PSEUDO_REGNO_MODE (i
))
3444 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3447 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3448 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3450 ior_hard_reg_set (set1
, set2
)
3451 HARD_REG_SET
*set1
, *set2
;
3453 IOR_HARD_REG_SET (*set1
, *set2
);
3456 /* After find_reload_regs has been run for all insn that need reloads,
3457 and/or spill_hard_regs was called, this function is used to actually
3458 spill pseudo registers and try to reallocate them. It also sets up the
3459 spill_regs array for use by choose_reload_regs. */
3462 finish_spills (global
, dumpfile
)
3466 struct insn_chain
*chain
;
3467 int something_changed
= 0;
3470 /* Build the spill_regs array for the function. */
3471 /* If there are some registers still to eliminate and one of the spill regs
3472 wasn't ever used before, additional stack space may have to be
3473 allocated to store this register. Thus, we may have changed the offset
3474 between the stack and frame pointers, so mark that something has changed.
3476 One might think that we need only set VAL to 1 if this is a call-used
3477 register. However, the set of registers that must be saved by the
3478 prologue is not identical to the call-used set. For example, the
3479 register used by the call insn for the return PC is a call-used register,
3480 but must be saved by the prologue. */
3483 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3484 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3486 spill_reg_order
[i
] = n_spills
;
3487 spill_regs
[n_spills
++] = i
;
3488 if (num_eliminable
&& ! regs_ever_live
[i
])
3489 something_changed
= 1;
3490 regs_ever_live
[i
] = 1;
3493 spill_reg_order
[i
] = -1;
3495 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3496 if (REGNO_REG_SET_P (&spilled_pseudos
, i
))
3498 /* Record the current hard register the pseudo is allocated to in
3499 pseudo_previous_regs so we avoid reallocating it to the same
3500 hard reg in a later pass. */
3501 if (reg_renumber
[i
] < 0)
3503 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3504 /* Mark it as no longer having a hard register home. */
3505 reg_renumber
[i
] = -1;
3506 /* We will need to scan everything again. */
3507 something_changed
= 1;
3510 /* Retry global register allocation if possible. */
3513 bzero ((char *) pseudo_forbidden_regs
, max_regno
* sizeof (HARD_REG_SET
));
3514 /* For every insn that needs reloads, set the registers used as spill
3515 regs in pseudo_forbidden_regs for every pseudo live across the
3517 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3519 EXECUTE_IF_SET_IN_REG_SET
3520 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
3522 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3523 &chain
->used_spill_regs
);
3525 EXECUTE_IF_SET_IN_REG_SET
3526 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
3528 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3529 &chain
->used_spill_regs
);
3533 /* Retry allocating the spilled pseudos. For each reg, merge the
3534 various reg sets that indicate which hard regs can't be used,
3535 and call retry_global_alloc.
3536 We change spill_pseudos here to only contain pseudos that did not
3537 get a new hard register. */
3538 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3539 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3541 HARD_REG_SET forbidden
;
3542 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3543 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3544 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3545 retry_global_alloc (i
, forbidden
);
3546 if (reg_renumber
[i
] >= 0)
3547 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3551 /* Fix up the register information in the insn chain.
3552 This involves deleting those of the spilled pseudos which did not get
3553 a new hard register home from the live_{before,after} sets. */
3554 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3556 HARD_REG_SET used_by_pseudos
;
3557 HARD_REG_SET used_by_pseudos2
;
3559 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3560 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3562 /* Mark any unallocated hard regs as available for spills. That
3563 makes inheritance work somewhat better. */
3564 if (chain
->need_reload
)
3566 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3567 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3568 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3570 /* Save the old value for the sanity test below. */
3571 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3573 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3574 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3575 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3576 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3578 /* Make sure we only enlarge the set. */
3579 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3585 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3586 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3588 int regno
= reg_renumber
[i
];
3589 if (reg_old_renumber
[i
] == regno
)
3592 alter_reg (i
, reg_old_renumber
[i
]);
3593 reg_old_renumber
[i
] = regno
;
3597 fprintf (dumpfile
, " Register %d now on stack.\n\n", i
);
3599 fprintf (dumpfile
, " Register %d now in %d.\n\n",
3600 i
, reg_renumber
[i
]);
3604 return something_changed
;
3607 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3608 Also mark any hard registers used to store user variables as
3609 forbidden from being used for spill registers. */
3612 scan_paradoxical_subregs (x
)
3616 register const char *fmt
;
3617 register enum rtx_code code
= GET_CODE (x
);
3623 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
3624 && REG_USERVAR_P (x
))
3625 SET_HARD_REG_BIT (bad_spill_regs_global
, REGNO (x
));
3641 if (GET_CODE (SUBREG_REG (x
)) == REG
3642 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3643 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3644 = GET_MODE_SIZE (GET_MODE (x
));
3651 fmt
= GET_RTX_FORMAT (code
);
3652 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3655 scan_paradoxical_subregs (XEXP (x
, i
));
3656 else if (fmt
[i
] == 'E')
3659 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
3660 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3665 /* Reload pseudo-registers into hard regs around each insn as needed.
3666 Additional register load insns are output before the insn that needs it
3667 and perhaps store insns after insns that modify the reloaded pseudo reg.
3669 reg_last_reload_reg and reg_reloaded_contents keep track of
3670 which registers are already available in reload registers.
3671 We update these for the reloads that we perform,
3672 as the insns are scanned. */
3675 reload_as_needed (live_known
)
3678 struct insn_chain
*chain
;
3679 #if defined (AUTO_INC_DEC)
3684 bzero ((char *) spill_reg_rtx
, sizeof spill_reg_rtx
);
3685 bzero ((char *) spill_reg_store
, sizeof spill_reg_store
);
3686 reg_last_reload_reg
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
3687 reg_has_output_reload
= (char *) xmalloc (max_regno
);
3688 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3690 set_initial_elim_offsets ();
3692 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3695 rtx insn
= chain
->insn
;
3696 rtx old_next
= NEXT_INSN (insn
);
3698 /* If we pass a label, copy the offsets from the label information
3699 into the current offsets of each elimination. */
3700 if (GET_CODE (insn
) == CODE_LABEL
)
3701 set_offsets_for_label (insn
);
3703 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
3705 rtx oldpat
= PATTERN (insn
);
3707 /* If this is a USE and CLOBBER of a MEM, ensure that any
3708 references to eliminable registers have been removed. */
3710 if ((GET_CODE (PATTERN (insn
)) == USE
3711 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3712 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
3713 XEXP (XEXP (PATTERN (insn
), 0), 0)
3714 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3715 GET_MODE (XEXP (PATTERN (insn
), 0)),
3718 /* If we need to do register elimination processing, do so.
3719 This might delete the insn, in which case we are done. */
3720 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
3722 eliminate_regs_in_insn (insn
, 1);
3723 if (GET_CODE (insn
) == NOTE
)
3725 update_eliminable_offsets ();
3730 /* If need_elim is nonzero but need_reload is zero, one might think
3731 that we could simply set n_reloads to 0. However, find_reloads
3732 could have done some manipulation of the insn (such as swapping
3733 commutative operands), and these manipulations are lost during
3734 the first pass for every insn that needs register elimination.
3735 So the actions of find_reloads must be redone here. */
3737 if (! chain
->need_elim
&& ! chain
->need_reload
3738 && ! chain
->need_operand_change
)
3740 /* First find the pseudo regs that must be reloaded for this insn.
3741 This info is returned in the tables reload_... (see reload.h).
3742 Also modify the body of INSN by substituting RELOAD
3743 rtx's for those pseudo regs. */
3746 bzero (reg_has_output_reload
, max_regno
);
3747 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3749 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3753 if (num_eliminable
&& chain
->need_elim
)
3754 update_eliminable_offsets ();
3758 rtx next
= NEXT_INSN (insn
);
3761 prev
= PREV_INSN (insn
);
3763 /* Now compute which reload regs to reload them into. Perhaps
3764 reusing reload regs from previous insns, or else output
3765 load insns to reload them. Maybe output store insns too.
3766 Record the choices of reload reg in reload_reg_rtx. */
3767 choose_reload_regs (chain
);
3769 /* Merge any reloads that we didn't combine for fear of
3770 increasing the number of spill registers needed but now
3771 discover can be safely merged. */
3772 if (SMALL_REGISTER_CLASSES
)
3773 merge_assigned_reloads (insn
);
3775 /* Generate the insns to reload operands into or out of
3776 their reload regs. */
3777 emit_reload_insns (chain
);
3779 /* Substitute the chosen reload regs from reload_reg_rtx
3780 into the insn's body (or perhaps into the bodies of other
3781 load and store insn that we just made for reloading
3782 and that we moved the structure into). */
3785 /* If this was an ASM, make sure that all the reload insns
3786 we have generated are valid. If not, give an error
3789 if (asm_noperands (PATTERN (insn
)) >= 0)
3790 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3791 if (p
!= insn
&& GET_RTX_CLASS (GET_CODE (p
)) == 'i'
3792 && (recog_memoized (p
) < 0
3793 || (extract_insn (p
), ! constrain_operands (1))))
3795 error_for_asm (insn
,
3796 "`asm' operand requires impossible reload");
3798 NOTE_SOURCE_FILE (p
) = 0;
3799 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
3802 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3803 is no longer validly lying around to save a future reload.
3804 Note that this does not detect pseudos that were reloaded
3805 for this insn in order to be stored in
3806 (obeying register constraints). That is correct; such reload
3807 registers ARE still valid. */
3808 note_stores (oldpat
, forget_old_reloads_1
, NULL
);
3810 /* There may have been CLOBBER insns placed after INSN. So scan
3811 between INSN and NEXT and use them to forget old reloads. */
3812 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
3813 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
3814 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
3817 /* Likewise for regs altered by auto-increment in this insn.
3818 REG_INC notes have been changed by reloading:
3819 find_reloads_address_1 records substitutions for them,
3820 which have been performed by subst_reloads above. */
3821 for (i
= n_reloads
- 1; i
>= 0; i
--)
3823 rtx in_reg
= rld
[i
].in_reg
;
3826 enum rtx_code code
= GET_CODE (in_reg
);
3827 /* PRE_INC / PRE_DEC will have the reload register ending up
3828 with the same value as the stack slot, but that doesn't
3829 hold true for POST_INC / POST_DEC. Either we have to
3830 convert the memory access to a true POST_INC / POST_DEC,
3831 or we can't use the reload register for inheritance. */
3832 if ((code
== POST_INC
|| code
== POST_DEC
)
3833 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
3834 REGNO (rld
[i
].reg_rtx
))
3835 /* Make sure it is the inc/dec pseudo, and not
3836 some other (e.g. output operand) pseudo. */
3837 && (reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
3838 == REGNO (XEXP (in_reg
, 0))))
3841 rtx reload_reg
= rld
[i
].reg_rtx
;
3842 enum machine_mode mode
= GET_MODE (reload_reg
);
3846 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
3848 /* We really want to ignore REG_INC notes here, so
3849 use PATTERN (p) as argument to reg_set_p . */
3850 if (reg_set_p (reload_reg
, PATTERN (p
)))
3852 n
= count_occurrences (PATTERN (p
), reload_reg
);
3857 n
= validate_replace_rtx (reload_reg
,
3858 gen_rtx (code
, mode
,
3862 /* We must also verify that the constraints
3863 are met after the replacement. */
3866 n
= constrain_operands (1);
3870 /* If the constraints were not met, then
3871 undo the replacement. */
3874 validate_replace_rtx (gen_rtx (code
, mode
,
3886 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
3888 /* Mark this as having an output reload so that the
3889 REG_INC processing code below won't invalidate
3890 the reload for inheritance. */
3891 SET_HARD_REG_BIT (reg_is_output_reload
,
3892 REGNO (reload_reg
));
3893 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
3896 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
3899 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
3900 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
3901 REGNO (rld
[i
].reg_rtx
))
3902 /* Make sure it is the inc/dec pseudo, and not
3903 some other (e.g. output operand) pseudo. */
3904 && (reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
3905 == REGNO (XEXP (in_reg
, 0))))
3907 SET_HARD_REG_BIT (reg_is_output_reload
,
3908 REGNO (rld
[i
].reg_rtx
));
3909 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
3913 /* If a pseudo that got a hard register is auto-incremented,
3914 we must purge records of copying it into pseudos without
3916 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
3917 if (REG_NOTE_KIND (x
) == REG_INC
)
3919 /* See if this pseudo reg was reloaded in this insn.
3920 If so, its last-reload info is still valid
3921 because it is based on this insn's reload. */
3922 for (i
= 0; i
< n_reloads
; i
++)
3923 if (rld
[i
].out
== XEXP (x
, 0))
3927 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
3931 /* A reload reg's contents are unknown after a label. */
3932 if (GET_CODE (insn
) == CODE_LABEL
)
3933 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3935 /* Don't assume a reload reg is still good after a call insn
3936 if it is a call-used reg. */
3937 else if (GET_CODE (insn
) == CALL_INSN
)
3938 AND_COMPL_HARD_REG_SET(reg_reloaded_valid
, call_used_reg_set
);
3942 free (reg_last_reload_reg
);
3943 free (reg_has_output_reload
);
3946 /* Discard all record of any value reloaded from X,
3947 or reloaded in X from someplace else;
3948 unless X is an output reload reg of the current insn.
3950 X may be a hard reg (the reload reg)
3951 or it may be a pseudo reg that was reloaded from. */
3954 forget_old_reloads_1 (x
, ignored
, data
)
3956 rtx ignored ATTRIBUTE_UNUSED
;
3957 void *data ATTRIBUTE_UNUSED
;
3963 /* note_stores does give us subregs of hard regs. */
3964 while (GET_CODE (x
) == SUBREG
)
3966 offset
+= SUBREG_WORD (x
);
3970 if (GET_CODE (x
) != REG
)
3973 regno
= REGNO (x
) + offset
;
3975 if (regno
>= FIRST_PSEUDO_REGISTER
)
3980 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
3981 /* Storing into a spilled-reg invalidates its contents.
3982 This can happen if a block-local pseudo is allocated to that reg
3983 and it wasn't spilled because this block's total need is 0.
3984 Then some insn might have an optional reload and use this reg. */
3985 for (i
= 0; i
< nr
; i
++)
3986 /* But don't do this if the reg actually serves as an output
3987 reload reg in the current instruction. */
3989 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
3990 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
3993 /* Since value of X has changed,
3994 forget any value previously copied from it. */
3997 /* But don't forget a copy if this is the output reload
3998 that establishes the copy's validity. */
3999 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4000 reg_last_reload_reg
[regno
+ nr
] = 0;
4003 /* The following HARD_REG_SETs indicate when each hard register is
4004 used for a reload of various parts of the current insn. */
4006 /* If reg is unavailable for all reloads. */
4007 static HARD_REG_SET reload_reg_unavailable
;
4008 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4009 static HARD_REG_SET reload_reg_used
;
4010 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4011 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4012 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4013 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4014 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4015 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4016 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4017 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4018 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4019 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4020 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4021 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4022 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4023 static HARD_REG_SET reload_reg_used_in_op_addr
;
4024 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4025 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4026 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4027 static HARD_REG_SET reload_reg_used_in_insn
;
4028 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4029 static HARD_REG_SET reload_reg_used_in_other_addr
;
4031 /* If reg is in use as a reload reg for any sort of reload. */
4032 static HARD_REG_SET reload_reg_used_at_all
;
4034 /* If reg is use as an inherited reload. We just mark the first register
4036 static HARD_REG_SET reload_reg_used_for_inherit
;
4038 /* Records which hard regs are used in any way, either as explicit use or
4039 by being allocated to a pseudo during any point of the current insn. */
4040 static HARD_REG_SET reg_used_in_insn
;
4042 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4043 TYPE. MODE is used to indicate how many consecutive regs are
4047 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4050 enum reload_type type
;
4051 enum machine_mode mode
;
4053 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4056 for (i
= regno
; i
< nregs
+ regno
; i
++)
4061 SET_HARD_REG_BIT (reload_reg_used
, i
);
4064 case RELOAD_FOR_INPUT_ADDRESS
:
4065 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4068 case RELOAD_FOR_INPADDR_ADDRESS
:
4069 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4072 case RELOAD_FOR_OUTPUT_ADDRESS
:
4073 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4076 case RELOAD_FOR_OUTADDR_ADDRESS
:
4077 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4080 case RELOAD_FOR_OPERAND_ADDRESS
:
4081 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4084 case RELOAD_FOR_OPADDR_ADDR
:
4085 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4088 case RELOAD_FOR_OTHER_ADDRESS
:
4089 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4092 case RELOAD_FOR_INPUT
:
4093 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4096 case RELOAD_FOR_OUTPUT
:
4097 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4100 case RELOAD_FOR_INSN
:
4101 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4105 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4109 /* Similarly, but show REGNO is no longer in use for a reload. */
4112 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4115 enum reload_type type
;
4116 enum machine_mode mode
;
4118 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4119 int start_regno
, end_regno
;
4121 /* A complication is that for some reload types, inheritance might
4122 allow multiple reloads of the same types to share a reload register.
4123 We set check_opnum if we have to check only reloads with the same
4124 operand number, and check_any if we have to check all reloads. */
4125 int check_opnum
= 0;
4127 HARD_REG_SET
*used_in_set
;
4132 used_in_set
= &reload_reg_used
;
4135 case RELOAD_FOR_INPUT_ADDRESS
:
4136 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4139 case RELOAD_FOR_INPADDR_ADDRESS
:
4141 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4144 case RELOAD_FOR_OUTPUT_ADDRESS
:
4145 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4148 case RELOAD_FOR_OUTADDR_ADDRESS
:
4150 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4153 case RELOAD_FOR_OPERAND_ADDRESS
:
4154 used_in_set
= &reload_reg_used_in_op_addr
;
4157 case RELOAD_FOR_OPADDR_ADDR
:
4159 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4162 case RELOAD_FOR_OTHER_ADDRESS
:
4163 used_in_set
= &reload_reg_used_in_other_addr
;
4167 case RELOAD_FOR_INPUT
:
4168 used_in_set
= &reload_reg_used_in_input
[opnum
];
4171 case RELOAD_FOR_OUTPUT
:
4172 used_in_set
= &reload_reg_used_in_output
[opnum
];
4175 case RELOAD_FOR_INSN
:
4176 used_in_set
= &reload_reg_used_in_insn
;
4181 /* We resolve conflicts with remaining reloads of the same type by
4182 excluding the intervals of of reload registers by them from the
4183 interval of freed reload registers. Since we only keep track of
4184 one set of interval bounds, we might have to exclude somewhat
4185 more then what would be necessary if we used a HARD_REG_SET here.
4186 But this should only happen very infrequently, so there should
4187 be no reason to worry about it. */
4189 start_regno
= regno
;
4190 end_regno
= regno
+ nregs
;
4191 if (check_opnum
|| check_any
)
4193 for (i
= n_reloads
- 1; i
>= 0; i
--)
4195 if (rld
[i
].when_needed
== type
4196 && (check_any
|| rld
[i
].opnum
== opnum
)
4199 int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4202 + HARD_REGNO_NREGS (conflict_start
, rld
[i
].mode
));
4204 /* If there is an overlap with the first to-be-freed register,
4205 adjust the interval start. */
4206 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4207 start_regno
= conflict_end
;
4208 /* Otherwise, if there is a conflict with one of the other
4209 to-be-freed registers, adjust the interval end. */
4210 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4211 end_regno
= conflict_start
;
4215 for (i
= start_regno
; i
< end_regno
; i
++)
4216 CLEAR_HARD_REG_BIT (*used_in_set
, i
);
4219 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4220 specified by OPNUM and TYPE. */
4223 reload_reg_free_p (regno
, opnum
, type
)
4226 enum reload_type type
;
4230 /* In use for a RELOAD_OTHER means it's not available for anything. */
4231 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4232 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4238 /* In use for anything means we can't use it for RELOAD_OTHER. */
4239 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4240 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4241 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4244 for (i
= 0; i
< reload_n_operands
; i
++)
4245 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4246 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4247 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4248 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4249 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4250 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4255 case RELOAD_FOR_INPUT
:
4256 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4257 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4260 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4263 /* If it is used for some other input, can't use it. */
4264 for (i
= 0; i
< reload_n_operands
; i
++)
4265 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4268 /* If it is used in a later operand's address, can't use it. */
4269 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4270 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4271 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4276 case RELOAD_FOR_INPUT_ADDRESS
:
4277 /* Can't use a register if it is used for an input address for this
4278 operand or used as an input in an earlier one. */
4279 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4280 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4283 for (i
= 0; i
< opnum
; i
++)
4284 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4289 case RELOAD_FOR_INPADDR_ADDRESS
:
4290 /* Can't use a register if it is used for an input address
4291 for this operand or used as an input in an earlier
4293 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4296 for (i
= 0; i
< opnum
; i
++)
4297 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4302 case RELOAD_FOR_OUTPUT_ADDRESS
:
4303 /* Can't use a register if it is used for an output address for this
4304 operand or used as an output in this or a later operand. */
4305 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4308 for (i
= opnum
; i
< reload_n_operands
; i
++)
4309 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4314 case RELOAD_FOR_OUTADDR_ADDRESS
:
4315 /* Can't use a register if it is used for an output address
4316 for this operand or used as an output in this or a
4318 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4321 for (i
= opnum
; i
< reload_n_operands
; i
++)
4322 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4327 case RELOAD_FOR_OPERAND_ADDRESS
:
4328 for (i
= 0; i
< reload_n_operands
; i
++)
4329 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4332 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4333 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4335 case RELOAD_FOR_OPADDR_ADDR
:
4336 for (i
= 0; i
< reload_n_operands
; i
++)
4337 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4340 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4342 case RELOAD_FOR_OUTPUT
:
4343 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4344 outputs, or an operand address for this or an earlier output. */
4345 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4348 for (i
= 0; i
< reload_n_operands
; i
++)
4349 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4352 for (i
= 0; i
<= opnum
; i
++)
4353 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4354 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4359 case RELOAD_FOR_INSN
:
4360 for (i
= 0; i
< reload_n_operands
; i
++)
4361 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4362 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4365 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4366 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4368 case RELOAD_FOR_OTHER_ADDRESS
:
4369 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4374 /* Return 1 if the value in reload reg REGNO, as used by a reload
4375 needed for the part of the insn specified by OPNUM and TYPE,
4376 is still available in REGNO at the end of the insn.
4378 We can assume that the reload reg was already tested for availability
4379 at the time it is needed, and we should not check this again,
4380 in case the reg has already been marked in use. */
4383 reload_reg_reaches_end_p (regno
, opnum
, type
)
4386 enum reload_type type
;
4393 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4394 its value must reach the end. */
4397 /* If this use is for part of the insn,
4398 its value reaches if no subsequent part uses the same register.
4399 Just like the above function, don't try to do this with lots
4402 case RELOAD_FOR_OTHER_ADDRESS
:
4403 /* Here we check for everything else, since these don't conflict
4404 with anything else and everything comes later. */
4406 for (i
= 0; i
< reload_n_operands
; i
++)
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4408 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4409 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4410 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4411 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4412 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4415 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4416 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4417 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4419 case RELOAD_FOR_INPUT_ADDRESS
:
4420 case RELOAD_FOR_INPADDR_ADDRESS
:
4421 /* Similar, except that we check only for this and subsequent inputs
4422 and the address of only subsequent inputs and we do not need
4423 to check for RELOAD_OTHER objects since they are known not to
4426 for (i
= opnum
; i
< reload_n_operands
; i
++)
4427 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4430 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4431 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4432 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4435 for (i
= 0; i
< reload_n_operands
; i
++)
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4437 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4438 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4444 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4445 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
4447 case RELOAD_FOR_INPUT
:
4448 /* Similar to input address, except we start at the next operand for
4449 both input and input address and we do not check for
4450 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4453 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4455 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4456 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4459 /* ... fall through ... */
4461 case RELOAD_FOR_OPERAND_ADDRESS
:
4462 /* Check outputs and their addresses. */
4464 for (i
= 0; i
< reload_n_operands
; i
++)
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4466 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4467 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4472 case RELOAD_FOR_OPADDR_ADDR
:
4473 for (i
= 0; i
< reload_n_operands
; i
++)
4474 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4475 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4476 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4479 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4480 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
4482 case RELOAD_FOR_INSN
:
4483 /* These conflict with other outputs with RELOAD_OTHER. So
4484 we need only check for output addresses. */
4488 /* ... fall through ... */
4490 case RELOAD_FOR_OUTPUT
:
4491 case RELOAD_FOR_OUTPUT_ADDRESS
:
4492 case RELOAD_FOR_OUTADDR_ADDRESS
:
4493 /* We already know these can't conflict with a later output. So the
4494 only thing to check are later output addresses. */
4495 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4496 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4497 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4506 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4509 This function uses the same algorithm as reload_reg_free_p above. */
4512 reloads_conflict (r1
, r2
)
4515 enum reload_type r1_type
= rld
[r1
].when_needed
;
4516 enum reload_type r2_type
= rld
[r2
].when_needed
;
4517 int r1_opnum
= rld
[r1
].opnum
;
4518 int r2_opnum
= rld
[r2
].opnum
;
4520 /* RELOAD_OTHER conflicts with everything. */
4521 if (r2_type
== RELOAD_OTHER
)
4524 /* Otherwise, check conflicts differently for each type. */
4528 case RELOAD_FOR_INPUT
:
4529 return (r2_type
== RELOAD_FOR_INSN
4530 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4531 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4532 || r2_type
== RELOAD_FOR_INPUT
4533 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4534 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4535 && r2_opnum
> r1_opnum
));
4537 case RELOAD_FOR_INPUT_ADDRESS
:
4538 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4539 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4541 case RELOAD_FOR_INPADDR_ADDRESS
:
4542 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4543 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4545 case RELOAD_FOR_OUTPUT_ADDRESS
:
4546 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4547 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
4549 case RELOAD_FOR_OUTADDR_ADDRESS
:
4550 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4551 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
4553 case RELOAD_FOR_OPERAND_ADDRESS
:
4554 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4555 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4557 case RELOAD_FOR_OPADDR_ADDR
:
4558 return (r2_type
== RELOAD_FOR_INPUT
4559 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4561 case RELOAD_FOR_OUTPUT
:
4562 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4563 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4564 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4565 && r2_opnum
<= r1_opnum
));
4567 case RELOAD_FOR_INSN
:
4568 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4569 || r2_type
== RELOAD_FOR_INSN
4570 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4572 case RELOAD_FOR_OTHER_ADDRESS
:
4573 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4583 /* Indexed by reload number, 1 if incoming value
4584 inherited from previous insns. */
4585 char reload_inherited
[MAX_RELOADS
];
4587 /* For an inherited reload, this is the insn the reload was inherited from,
4588 if we know it. Otherwise, this is 0. */
4589 rtx reload_inheritance_insn
[MAX_RELOADS
];
4591 /* If non-zero, this is a place to get the value of the reload,
4592 rather than using reload_in. */
4593 rtx reload_override_in
[MAX_RELOADS
];
4595 /* For each reload, the hard register number of the register used,
4596 or -1 if we did not need a register for this reload. */
4597 int reload_spill_index
[MAX_RELOADS
];
4599 /* Return 1 if the value in reload reg REGNO, as used by a reload
4600 needed for the part of the insn specified by OPNUM and TYPE,
4601 may be used to load VALUE into it.
4603 Other read-only reloads with the same value do not conflict
4604 unless OUT is non-zero and these other reloads have to live while
4605 output reloads live.
4606 If OUT is CONST0_RTX, this is a special case: it means that the
4607 test should not be for using register REGNO as reload register, but
4608 for copying from register REGNO into the reload register.
4610 RELOADNUM is the number of the reload we want to load this value for;
4611 a reload does not conflict with itself.
4613 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4614 reloads that load an address for the very reload we are considering.
4616 The caller has to make sure that there is no conflict with the return
4619 reload_reg_free_for_value_p (regno
, opnum
, type
, value
, out
, reloadnum
,
4620 ignore_address_reloads
)
4623 enum reload_type type
;
4626 int ignore_address_reloads
;
4629 /* Set if we see an input reload that must not share its reload register
4630 with any new earlyclobber, but might otherwise share the reload
4631 register with an output or input-output reload. */
4632 int check_earlyclobber
= 0;
4636 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4639 if (out
== const0_rtx
)
4645 /* We use some pseudo 'time' value to check if the lifetimes of the
4646 new register use would overlap with the one of a previous reload
4647 that is not read-only or uses a different value.
4648 The 'time' used doesn't have to be linear in any shape or form, just
4650 Some reload types use different 'buckets' for each operand.
4651 So there are MAX_RECOG_OPERANDS different time values for each
4653 We compute TIME1 as the time when the register for the prospective
4654 new reload ceases to be live, and TIME2 for each existing
4655 reload as the time when that the reload register of that reload
4657 Where there is little to be gained by exact lifetime calculations,
4658 we just make conservative assumptions, i.e. a longer lifetime;
4659 this is done in the 'default:' cases. */
4662 case RELOAD_FOR_OTHER_ADDRESS
:
4663 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4664 time1
= copy
? 0 : 1;
4667 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
4669 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4670 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4671 respectively, to the time values for these, we get distinct time
4672 values. To get distinct time values for each operand, we have to
4673 multiply opnum by at least three. We round that up to four because
4674 multiply by four is often cheaper. */
4675 case RELOAD_FOR_INPADDR_ADDRESS
:
4676 time1
= opnum
* 4 + 2;
4678 case RELOAD_FOR_INPUT_ADDRESS
:
4679 time1
= opnum
* 4 + 3;
4681 case RELOAD_FOR_INPUT
:
4682 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4683 executes (inclusive). */
4684 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
4686 case RELOAD_FOR_OPADDR_ADDR
:
4688 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4689 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
4691 case RELOAD_FOR_OPERAND_ADDRESS
:
4692 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4694 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
4696 case RELOAD_FOR_OUTADDR_ADDRESS
:
4697 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
4699 case RELOAD_FOR_OUTPUT_ADDRESS
:
4700 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
4703 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
4706 for (i
= 0; i
< n_reloads
; i
++)
4708 rtx reg
= rld
[i
].reg_rtx
;
4709 if (reg
&& GET_CODE (reg
) == REG
4710 && ((unsigned) regno
- true_regnum (reg
)
4711 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned)1)
4714 if (! rld
[i
].in
|| ! rtx_equal_p (rld
[i
].in
, value
)
4715 || rld
[i
].out
|| out
)
4718 switch (rld
[i
].when_needed
)
4720 case RELOAD_FOR_OTHER_ADDRESS
:
4723 case RELOAD_FOR_INPADDR_ADDRESS
:
4724 /* find_reloads makes sure that a
4725 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4726 by at most one - the first -
4727 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4728 address reload is inherited, the address address reload
4729 goes away, so we can ignore this conflict. */
4730 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
4731 && ignore_address_reloads
4732 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4733 Then the address address is still needed to store
4734 back the new address. */
4735 && ! rld
[reloadnum
].out
)
4737 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4738 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4740 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4741 && ignore_address_reloads
4742 /* Unless we are reloading an auto_inc expression. */
4743 && ! rld
[reloadnum
].out
)
4745 time2
= rld
[i
].opnum
* 4 + 2;
4747 case RELOAD_FOR_INPUT_ADDRESS
:
4748 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4749 && ignore_address_reloads
4750 && ! rld
[reloadnum
].out
)
4752 time2
= rld
[i
].opnum
* 4 + 3;
4754 case RELOAD_FOR_INPUT
:
4755 time2
= rld
[i
].opnum
* 4 + 4;
4756 check_earlyclobber
= 1;
4758 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4759 == MAX_RECOG_OPERAND * 4 */
4760 case RELOAD_FOR_OPADDR_ADDR
:
4761 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
4762 && ignore_address_reloads
4763 && ! rld
[reloadnum
].out
)
4765 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
4767 case RELOAD_FOR_OPERAND_ADDRESS
:
4768 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
4769 check_earlyclobber
= 1;
4771 case RELOAD_FOR_INSN
:
4772 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4774 case RELOAD_FOR_OUTPUT
:
4775 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4776 instruction is executed. */
4777 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4779 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4780 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4782 case RELOAD_FOR_OUTADDR_ADDRESS
:
4783 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
4784 && ignore_address_reloads
4785 && ! rld
[reloadnum
].out
)
4787 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
4789 case RELOAD_FOR_OUTPUT_ADDRESS
:
4790 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
4793 /* If there is no conflict in the input part, handle this
4794 like an output reload. */
4795 if (! rld
[i
].in
|| rtx_equal_p (rld
[i
].in
, value
))
4797 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4798 /* Earlyclobbered outputs must conflict with inputs. */
4799 if (earlyclobber_operand_p (rld
[i
].out
))
4800 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4805 /* RELOAD_OTHER might be live beyond instruction execution,
4806 but this is not obvious when we set time2 = 1. So check
4807 here if there might be a problem with the new reload
4808 clobbering the register used by the RELOAD_OTHER. */
4816 && (! rld
[i
].in
|| rld
[i
].out
4817 || ! rtx_equal_p (rld
[i
].in
, value
)))
4818 || (out
&& rld
[reloadnum
].out_reg
4819 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
4825 /* Earlyclobbered outputs must conflict with inputs. */
4826 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
4832 /* Give an error message saying we failed to find a reload for INSN,
4833 and clear out reload R. */
4835 failed_reload (insn
, r
)
4839 if (asm_noperands (PATTERN (insn
)) < 0)
4840 /* It's the compiler's fault. */
4841 fatal_insn ("Could not find a spill register", insn
);
4843 /* It's the user's fault; the operand's mode and constraint
4844 don't match. Disable this reload so we don't crash in final. */
4845 error_for_asm (insn
,
4846 "`asm' operand constraint incompatible with operand size");
4850 rld
[r
].optional
= 1;
4851 rld
[r
].secondary_p
= 1;
4854 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4855 for reload R. If it's valid, get an rtx for it. Return nonzero if
4858 set_reload_reg (i
, r
)
4862 rtx reg
= spill_reg_rtx
[i
];
4864 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
4865 spill_reg_rtx
[i
] = reg
4866 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
4868 regno
= true_regnum (reg
);
4870 /* Detect when the reload reg can't hold the reload mode.
4871 This used to be one `if', but Sequent compiler can't handle that. */
4872 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
4874 enum machine_mode test_mode
= VOIDmode
;
4876 test_mode
= GET_MODE (rld
[r
].in
);
4877 /* If rld[r].in has VOIDmode, it means we will load it
4878 in whatever mode the reload reg has: to wit, rld[r].mode.
4879 We have already tested that for validity. */
4880 /* Aside from that, we need to test that the expressions
4881 to reload from or into have modes which are valid for this
4882 reload register. Otherwise the reload insns would be invalid. */
4883 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
4884 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
4885 if (! (rld
[r
].out
!= 0
4886 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
4888 /* The reg is OK. */
4891 /* Mark as in use for this insn the reload regs we use
4893 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
4894 rld
[r
].when_needed
, rld
[r
].mode
);
4896 rld
[r
].reg_rtx
= reg
;
4897 reload_spill_index
[r
] = spill_regs
[i
];
4904 /* Find a spill register to use as a reload register for reload R.
4905 LAST_RELOAD is non-zero if this is the last reload for the insn being
4908 Set rld[R].reg_rtx to the register allocated.
4910 We return 1 if successful, or 0 if we couldn't find a spill reg and
4911 we didn't change anything. */
4914 allocate_reload_reg (chain
, r
, last_reload
)
4915 struct insn_chain
*chain ATTRIBUTE_UNUSED
;
4921 /* If we put this reload ahead, thinking it is a group,
4922 then insist on finding a group. Otherwise we can grab a
4923 reg that some other reload needs.
4924 (That can happen when we have a 68000 DATA_OR_FP_REG
4925 which is a group of data regs or one fp reg.)
4926 We need not be so restrictive if there are no more reloads
4929 ??? Really it would be nicer to have smarter handling
4930 for that kind of reg class, where a problem like this is normal.
4931 Perhaps those classes should be avoided for reloading
4932 by use of more alternatives. */
4934 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
4936 /* If we want a single register and haven't yet found one,
4937 take any reg in the right class and not in use.
4938 If we want a consecutive group, here is where we look for it.
4940 We use two passes so we can first look for reload regs to
4941 reuse, which are already in use for other reloads in this insn,
4942 and only then use additional registers.
4943 I think that maximizing reuse is needed to make sure we don't
4944 run out of reload regs. Suppose we have three reloads, and
4945 reloads A and B can share regs. These need two regs.
4946 Suppose A and B are given different regs.
4947 That leaves none for C. */
4948 for (pass
= 0; pass
< 2; pass
++)
4950 /* I is the index in spill_regs.
4951 We advance it round-robin between insns to use all spill regs
4952 equally, so that inherited reloads have a chance
4953 of leapfrogging each other. */
4957 for (count
= 0; count
< n_spills
; count
++)
4959 int class = (int) rld
[r
].class;
4965 regnum
= spill_regs
[i
];
4967 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
4970 /* We check reload_reg_used to make sure we
4971 don't clobber the return register. */
4972 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
4973 && reload_reg_free_for_value_p (regnum
,
4978 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
4979 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
4980 /* Look first for regs to share, then for unshared. But
4981 don't share regs used for inherited reloads; they are
4982 the ones we want to preserve. */
4984 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
4986 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
4989 int nr
= HARD_REGNO_NREGS (regnum
, rld
[r
].mode
);
4990 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4991 (on 68000) got us two FP regs. If NR is 1,
4992 we would reject both of them. */
4995 /* If we need only one reg, we have already won. */
4998 /* But reject a single reg if we demand a group. */
5003 /* Otherwise check that as many consecutive regs as we need
5004 are available here. */
5007 int regno
= regnum
+ nr
- 1;
5008 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5009 && spill_reg_order
[regno
] >= 0
5010 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5011 rld
[r
].when_needed
)))
5020 /* If we found something on pass 1, omit pass 2. */
5021 if (count
< n_spills
)
5025 /* We should have found a spill register by now. */
5026 if (count
>= n_spills
)
5029 /* I is the index in SPILL_REG_RTX of the reload register we are to
5030 allocate. Get an rtx for it and find its register number. */
5032 return set_reload_reg (i
, r
);
5035 /* Initialize all the tables needed to allocate reload registers.
5036 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5037 is the array we use to restore the reg_rtx field for every reload. */
5039 choose_reload_regs_init (chain
, save_reload_reg_rtx
)
5040 struct insn_chain
*chain
;
5041 rtx
*save_reload_reg_rtx
;
5045 for (i
= 0; i
< n_reloads
; i
++)
5046 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5048 bzero (reload_inherited
, MAX_RELOADS
);
5049 bzero ((char *) reload_inheritance_insn
, MAX_RELOADS
* sizeof (rtx
));
5050 bzero ((char *) reload_override_in
, MAX_RELOADS
* sizeof (rtx
));
5052 CLEAR_HARD_REG_SET (reload_reg_used
);
5053 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5054 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5055 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5056 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5057 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5059 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5062 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5063 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5064 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5065 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5066 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5067 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5069 for (i
= 0; i
< reload_n_operands
; i
++)
5071 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5072 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5073 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5074 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5075 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5076 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5079 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5081 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5083 for (i
= 0; i
< n_reloads
; i
++)
5084 /* If we have already decided to use a certain register,
5085 don't use it in another way. */
5087 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5088 rld
[i
].when_needed
, rld
[i
].mode
);
5091 /* Assign hard reg targets for the pseudo-registers we must reload
5092 into hard regs for this insn.
5093 Also output the instructions to copy them in and out of the hard regs.
5095 For machines with register classes, we are responsible for
5096 finding a reload reg in the proper class. */
5099 choose_reload_regs (chain
)
5100 struct insn_chain
*chain
;
5102 rtx insn
= chain
->insn
;
5104 int max_group_size
= 1;
5105 enum reg_class group_class
= NO_REGS
;
5106 int pass
, win
, inheritance
;
5108 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5110 /* In order to be certain of getting the registers we need,
5111 we must sort the reloads into order of increasing register class.
5112 Then our grabbing of reload registers will parallel the process
5113 that provided the reload registers.
5115 Also note whether any of the reloads wants a consecutive group of regs.
5116 If so, record the maximum size of the group desired and what
5117 register class contains all the groups needed by this insn. */
5119 for (j
= 0; j
< n_reloads
; j
++)
5121 reload_order
[j
] = j
;
5122 reload_spill_index
[j
] = -1;
5124 if (rld
[j
].nregs
> 1)
5126 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5127 group_class
= reg_class_superunion
[(int)rld
[j
].class][(int)group_class
];
5130 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5134 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5136 /* If -O, try first with inheritance, then turning it off.
5137 If not -O, don't do inheritance.
5138 Using inheritance when not optimizing leads to paradoxes
5139 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5140 because one side of the comparison might be inherited. */
5142 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5144 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5146 /* Process the reloads in order of preference just found.
5147 Beyond this point, subregs can be found in reload_reg_rtx.
5149 This used to look for an existing reloaded home for all
5150 of the reloads, and only then perform any new reloads.
5151 But that could lose if the reloads were done out of reg-class order
5152 because a later reload with a looser constraint might have an old
5153 home in a register needed by an earlier reload with a tighter constraint.
5155 To solve this, we make two passes over the reloads, in the order
5156 described above. In the first pass we try to inherit a reload
5157 from a previous insn. If there is a later reload that needs a
5158 class that is a proper subset of the class being processed, we must
5159 also allocate a spill register during the first pass.
5161 Then make a second pass over the reloads to allocate any reloads
5162 that haven't been given registers yet. */
5164 for (j
= 0; j
< n_reloads
; j
++)
5166 register int r
= reload_order
[j
];
5167 rtx search_equiv
= NULL_RTX
;
5169 /* Ignore reloads that got marked inoperative. */
5170 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5171 && ! rld
[r
].secondary_p
)
5174 /* If find_reloads chose to use reload_in or reload_out as a reload
5175 register, we don't need to chose one. Otherwise, try even if it
5176 found one since we might save an insn if we find the value lying
5178 Try also when reload_in is a pseudo without a hard reg. */
5179 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5180 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5181 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5182 && GET_CODE (rld
[r
].in
) != MEM
5183 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5186 #if 0 /* No longer needed for correct operation.
5187 It might give better code, or might not; worth an experiment? */
5188 /* If this is an optional reload, we can't inherit from earlier insns
5189 until we are sure that any non-optional reloads have been allocated.
5190 The following code takes advantage of the fact that optional reloads
5191 are at the end of reload_order. */
5192 if (rld
[r
].optional
!= 0)
5193 for (i
= 0; i
< j
; i
++)
5194 if ((rld
[reload_order
[i
]].out
!= 0
5195 || rld
[reload_order
[i
]].in
!= 0
5196 || rld
[reload_order
[i
]].secondary_p
)
5197 && ! rld
[reload_order
[i
]].optional
5198 && rld
[reload_order
[i
]].reg_rtx
== 0)
5199 allocate_reload_reg (chain
, reload_order
[i
], 0);
5202 /* First see if this pseudo is already available as reloaded
5203 for a previous insn. We cannot try to inherit for reloads
5204 that are smaller than the maximum number of registers needed
5205 for groups unless the register we would allocate cannot be used
5208 We could check here to see if this is a secondary reload for
5209 an object that is already in a register of the desired class.
5210 This would avoid the need for the secondary reload register.
5211 But this is complex because we can't easily determine what
5212 objects might want to be loaded via this reload. So let a
5213 register be allocated here. In `emit_reload_insns' we suppress
5214 one of the loads in the case described above. */
5219 register int regno
= -1;
5220 enum machine_mode mode
= VOIDmode
;
5224 else if (GET_CODE (rld
[r
].in
) == REG
)
5226 regno
= REGNO (rld
[r
].in
);
5227 mode
= GET_MODE (rld
[r
].in
);
5229 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
5231 regno
= REGNO (rld
[r
].in_reg
);
5232 mode
= GET_MODE (rld
[r
].in_reg
);
5234 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5235 && GET_CODE (SUBREG_REG (rld
[r
].in_reg
)) == REG
)
5237 word
= SUBREG_WORD (rld
[r
].in_reg
);
5238 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5239 if (regno
< FIRST_PSEUDO_REGISTER
)
5241 mode
= GET_MODE (rld
[r
].in_reg
);
5244 else if ((GET_CODE (rld
[r
].in_reg
) == PRE_INC
5245 || GET_CODE (rld
[r
].in_reg
) == PRE_DEC
5246 || GET_CODE (rld
[r
].in_reg
) == POST_INC
5247 || GET_CODE (rld
[r
].in_reg
) == POST_DEC
)
5248 && GET_CODE (XEXP (rld
[r
].in_reg
, 0)) == REG
)
5250 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5251 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5252 rld
[r
].out
= rld
[r
].in
;
5256 /* This won't work, since REGNO can be a pseudo reg number.
5257 Also, it takes much more hair to keep track of all the things
5258 that can invalidate an inherited reload of part of a pseudoreg. */
5259 else if (GET_CODE (rld
[r
].in
) == SUBREG
5260 && GET_CODE (SUBREG_REG (rld
[r
].in
)) == REG
)
5261 regno
= REGNO (SUBREG_REG (rld
[r
].in
)) + SUBREG_WORD (rld
[r
].in
);
5264 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5266 enum reg_class
class = rld
[r
].class, last_class
;
5267 rtx last_reg
= reg_last_reload_reg
[regno
];
5269 i
= REGNO (last_reg
) + word
;
5270 last_class
= REGNO_REG_CLASS (i
);
5271 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
5272 >= GET_MODE_SIZE (mode
) + word
* UNITS_PER_WORD
)
5273 && reg_reloaded_contents
[i
] == regno
5274 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5275 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5276 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5277 /* Even if we can't use this register as a reload
5278 register, we might use it for reload_override_in,
5279 if copying it to the desired class is cheap
5281 || ((REGISTER_MOVE_COST (last_class
, class)
5282 < MEMORY_MOVE_COST (mode
, class, 1))
5283 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5284 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5288 #ifdef SECONDARY_MEMORY_NEEDED
5289 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5294 && (rld
[r
].nregs
== max_group_size
5295 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5297 && reload_reg_free_for_value_p (i
, rld
[r
].opnum
,
5302 /* If a group is needed, verify that all the subsequent
5303 registers still have their values intact. */
5305 = HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5308 for (k
= 1; k
< nr
; k
++)
5309 if (reg_reloaded_contents
[i
+ k
] != regno
5310 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5317 last_reg
= (GET_MODE (last_reg
) == mode
5318 ? last_reg
: gen_rtx_REG (mode
, i
));
5320 /* We found a register that contains the
5321 value we need. If this register is the
5322 same as an `earlyclobber' operand of the
5323 current insn, just mark it as a place to
5324 reload from since we can't use it as the
5325 reload register itself. */
5327 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5328 if (reg_overlap_mentioned_for_reload_p
5329 (reg_last_reload_reg
[regno
],
5330 reload_earlyclobbers
[i1
]))
5333 if (i1
!= n_earlyclobbers
5334 || ! (reload_reg_free_for_value_p
5335 (i
, rld
[r
].opnum
, rld
[r
].when_needed
,
5336 rld
[r
].in
, rld
[r
].out
, r
, 1))
5337 /* Don't use it if we'd clobber a pseudo reg. */
5338 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5340 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5341 /* Don't clobber the frame pointer. */
5342 || (i
== HARD_FRAME_POINTER_REGNUM
&& rld
[r
].out
)
5343 /* Don't really use the inherited spill reg
5344 if we need it wider than we've got it. */
5345 || (GET_MODE_SIZE (rld
[r
].mode
)
5346 > GET_MODE_SIZE (mode
))
5347 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5350 /* If find_reloads chose reload_out as reload
5351 register, stay with it - that leaves the
5352 inherited register for subsequent reloads. */
5353 || (rld
[r
].out
&& rld
[r
].reg_rtx
5354 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5356 reload_override_in
[r
] = last_reg
;
5357 reload_inheritance_insn
[r
]
5358 = reg_reloaded_insn
[i
];
5363 /* We can use this as a reload reg. */
5364 /* Mark the register as in use for this part of
5366 mark_reload_reg_in_use (i
,
5370 rld
[r
].reg_rtx
= last_reg
;
5371 reload_inherited
[r
] = 1;
5372 reload_inheritance_insn
[r
]
5373 = reg_reloaded_insn
[i
];
5374 reload_spill_index
[r
] = i
;
5375 for (k
= 0; k
< nr
; k
++)
5376 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5384 /* Here's another way to see if the value is already lying around. */
5387 && ! reload_inherited
[r
]
5389 && (CONSTANT_P (rld
[r
].in
)
5390 || GET_CODE (rld
[r
].in
) == PLUS
5391 || GET_CODE (rld
[r
].in
) == REG
5392 || GET_CODE (rld
[r
].in
) == MEM
)
5393 && (rld
[r
].nregs
== max_group_size
5394 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5395 search_equiv
= rld
[r
].in
;
5396 /* If this is an output reload from a simple move insn, look
5397 if an equivalence for the input is available. */
5398 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5400 rtx set
= single_set (insn
);
5403 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5404 && CONSTANT_P (SET_SRC (set
)))
5405 search_equiv
= SET_SRC (set
);
5411 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5412 -1, NULL_PTR
, 0, rld
[r
].mode
);
5417 if (GET_CODE (equiv
) == REG
)
5418 regno
= REGNO (equiv
);
5419 else if (GET_CODE (equiv
) == SUBREG
)
5421 /* This must be a SUBREG of a hard register.
5422 Make a new REG since this might be used in an
5423 address and not all machines support SUBREGs
5425 regno
= REGNO (SUBREG_REG (equiv
)) + SUBREG_WORD (equiv
);
5426 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5432 /* If we found a spill reg, reject it unless it is free
5433 and of the desired class. */
5435 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
)
5436 && ! reload_reg_free_for_value_p (regno
, rld
[r
].opnum
,
5440 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5444 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5447 /* We found a register that contains the value we need.
5448 If this register is the same as an `earlyclobber' operand
5449 of the current insn, just mark it as a place to reload from
5450 since we can't use it as the reload register itself. */
5453 for (i
= 0; i
< n_earlyclobbers
; i
++)
5454 if (reg_overlap_mentioned_for_reload_p (equiv
,
5455 reload_earlyclobbers
[i
]))
5457 reload_override_in
[r
] = equiv
;
5462 /* If the equiv register we have found is explicitly clobbered
5463 in the current insn, it depends on the reload type if we
5464 can use it, use it for reload_override_in, or not at all.
5465 In particular, we then can't use EQUIV for a
5466 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5468 if (equiv
!= 0 && regno_clobbered_p (regno
, insn
))
5470 switch (rld
[r
].when_needed
)
5472 case RELOAD_FOR_OTHER_ADDRESS
:
5473 case RELOAD_FOR_INPADDR_ADDRESS
:
5474 case RELOAD_FOR_INPUT_ADDRESS
:
5475 case RELOAD_FOR_OPADDR_ADDR
:
5478 case RELOAD_FOR_INPUT
:
5479 case RELOAD_FOR_OPERAND_ADDRESS
:
5480 reload_override_in
[r
] = equiv
;
5488 /* If we found an equivalent reg, say no code need be generated
5489 to load it, and use it as our reload reg. */
5490 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
5492 int nr
= HARD_REGNO_NREGS (regno
, rld
[r
].mode
);
5494 rld
[r
].reg_rtx
= equiv
;
5495 reload_inherited
[r
] = 1;
5497 /* If reg_reloaded_valid is not set for this register,
5498 there might be a stale spill_reg_store lying around.
5499 We must clear it, since otherwise emit_reload_insns
5500 might delete the store. */
5501 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5502 spill_reg_store
[regno
] = NULL_RTX
;
5503 /* If any of the hard registers in EQUIV are spill
5504 registers, mark them as in use for this insn. */
5505 for (k
= 0; k
< nr
; k
++)
5507 i
= spill_reg_order
[regno
+ k
];
5510 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
5513 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5520 /* If we found a register to use already, or if this is an optional
5521 reload, we are done. */
5522 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
5525 #if 0 /* No longer needed for correct operation. Might or might not
5526 give better code on the average. Want to experiment? */
5528 /* See if there is a later reload that has a class different from our
5529 class that intersects our class or that requires less register
5530 than our reload. If so, we must allocate a register to this
5531 reload now, since that reload might inherit a previous reload
5532 and take the only available register in our class. Don't do this
5533 for optional reloads since they will force all previous reloads
5534 to be allocated. Also don't do this for reloads that have been
5537 for (i
= j
+ 1; i
< n_reloads
; i
++)
5539 int s
= reload_order
[i
];
5541 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
5542 && ! rld
[s
].secondary_p
)
5546 if ((rld
[s
].class != rld
[r
].class
5547 && reg_classes_intersect_p (rld
[r
].class,
5549 || rld
[s
].nregs
< rld
[r
].nregs
)
5556 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
5560 /* Now allocate reload registers for anything non-optional that
5561 didn't get one yet. */
5562 for (j
= 0; j
< n_reloads
; j
++)
5564 register int r
= reload_order
[j
];
5566 /* Ignore reloads that got marked inoperative. */
5567 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
5570 /* Skip reloads that already have a register allocated or are
5572 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
5575 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
5579 /* If that loop got all the way, we have won. */
5586 /* Loop around and try without any inheritance. */
5591 /* First undo everything done by the failed attempt
5592 to allocate with inheritance. */
5593 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5595 /* Some sanity tests to verify that the reloads found in the first
5596 pass are identical to the ones we have now. */
5597 if (chain
->n_reloads
!= n_reloads
)
5600 for (i
= 0; i
< n_reloads
; i
++)
5602 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
5604 if (chain
->rld
[i
].when_needed
!= rld
[i
].when_needed
)
5606 for (j
= 0; j
< n_spills
; j
++)
5607 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
5608 if (! set_reload_reg (j
, i
))
5609 failed_reload (chain
->insn
, i
);
5613 /* If we thought we could inherit a reload, because it seemed that
5614 nothing else wanted the same reload register earlier in the insn,
5615 verify that assumption, now that all reloads have been assigned.
5616 Likewise for reloads where reload_override_in has been set. */
5618 /* If doing expensive optimizations, do one preliminary pass that doesn't
5619 cancel any inheritance, but removes reloads that have been needed only
5620 for reloads that we know can be inherited. */
5621 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
5623 for (j
= 0; j
< n_reloads
; j
++)
5625 register int r
= reload_order
[j
];
5627 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
5628 check_reg
= rld
[r
].reg_rtx
;
5629 else if (reload_override_in
[r
]
5630 && (GET_CODE (reload_override_in
[r
]) == REG
5631 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5632 check_reg
= reload_override_in
[r
];
5635 if (! reload_reg_free_for_value_p (true_regnum (check_reg
),
5639 (reload_inherited
[r
]
5640 ? rld
[r
].out
: const0_rtx
),
5645 reload_inherited
[r
] = 0;
5646 reload_override_in
[r
] = 0;
5648 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5649 reload_override_in, then we do not need its related
5650 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5651 likewise for other reload types.
5652 We handle this by removing a reload when its only replacement
5653 is mentioned in reload_in of the reload we are going to inherit.
5654 A special case are auto_inc expressions; even if the input is
5655 inherited, we still need the address for the output. We can
5656 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5657 If we suceeded removing some reload and we are doing a preliminary
5658 pass just to remove such reloads, make another pass, since the
5659 removal of one reload might allow us to inherit another one. */
5661 && rld
[r
].out
!= rld
[r
].in
5662 && remove_address_replacements (rld
[r
].in
) && pass
)
5667 /* Now that reload_override_in is known valid,
5668 actually override reload_in. */
5669 for (j
= 0; j
< n_reloads
; j
++)
5670 if (reload_override_in
[j
])
5671 rld
[j
].in
= reload_override_in
[j
];
5673 /* If this reload won't be done because it has been cancelled or is
5674 optional and not inherited, clear reload_reg_rtx so other
5675 routines (such as subst_reloads) don't get confused. */
5676 for (j
= 0; j
< n_reloads
; j
++)
5677 if (rld
[j
].reg_rtx
!= 0
5678 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
5679 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
5680 && ! rld
[j
].secondary_p
)))
5682 int regno
= true_regnum (rld
[j
].reg_rtx
);
5684 if (spill_reg_order
[regno
] >= 0)
5685 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
5686 rld
[j
].when_needed
, rld
[j
].mode
);
5688 reload_spill_index
[j
] = -1;
5691 /* Record which pseudos and which spill regs have output reloads. */
5692 for (j
= 0; j
< n_reloads
; j
++)
5694 register int r
= reload_order
[j
];
5696 i
= reload_spill_index
[r
];
5698 /* I is nonneg if this reload uses a register.
5699 If rld[r].reg_rtx is 0, this is an optional reload
5700 that we opted to ignore. */
5701 if (rld
[r
].out_reg
!= 0 && GET_CODE (rld
[r
].out_reg
) == REG
5702 && rld
[r
].reg_rtx
!= 0)
5704 register int nregno
= REGNO (rld
[r
].out_reg
);
5707 if (nregno
< FIRST_PSEUDO_REGISTER
)
5708 nr
= HARD_REGNO_NREGS (nregno
, rld
[r
].mode
);
5711 reg_has_output_reload
[nregno
+ nr
] = 1;
5715 nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5717 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
5720 if (rld
[r
].when_needed
!= RELOAD_OTHER
5721 && rld
[r
].when_needed
!= RELOAD_FOR_OUTPUT
5722 && rld
[r
].when_needed
!= RELOAD_FOR_INSN
)
5728 /* Deallocate the reload register for reload R. This is called from
5729 remove_address_replacements. */
5731 deallocate_reload_reg (r
)
5736 if (! rld
[r
].reg_rtx
)
5738 regno
= true_regnum (rld
[r
].reg_rtx
);
5740 if (spill_reg_order
[regno
] >= 0)
5741 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
5743 reload_spill_index
[r
] = -1;
5746 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5747 reloads of the same item for fear that we might not have enough reload
5748 registers. However, normally they will get the same reload register
5749 and hence actually need not be loaded twice.
5751 Here we check for the most common case of this phenomenon: when we have
5752 a number of reloads for the same object, each of which were allocated
5753 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5754 reload, and is not modified in the insn itself. If we find such,
5755 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5756 This will not increase the number of spill registers needed and will
5757 prevent redundant code. */
5760 merge_assigned_reloads (insn
)
5765 /* Scan all the reloads looking for ones that only load values and
5766 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5767 assigned and not modified by INSN. */
5769 for (i
= 0; i
< n_reloads
; i
++)
5771 int conflicting_input
= 0;
5772 int max_input_address_opnum
= -1;
5773 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
5775 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
5776 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
5777 || reg_set_p (rld
[i
].reg_rtx
, insn
))
5780 /* Look at all other reloads. Ensure that the only use of this
5781 reload_reg_rtx is in a reload that just loads the same value
5782 as we do. Note that any secondary reloads must be of the identical
5783 class since the values, modes, and result registers are the
5784 same, so we need not do anything with any secondary reloads. */
5786 for (j
= 0; j
< n_reloads
; j
++)
5788 if (i
== j
|| rld
[j
].reg_rtx
== 0
5789 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
5793 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
5794 && rld
[j
].opnum
> max_input_address_opnum
)
5795 max_input_address_opnum
= rld
[j
].opnum
;
5797 /* If the reload regs aren't exactly the same (e.g, different modes)
5798 or if the values are different, we can't merge this reload.
5799 But if it is an input reload, we might still merge
5800 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5802 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
5803 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
5804 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
5806 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
5807 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
5808 || rld
[i
].opnum
> rld
[j
].opnum
)
5809 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
5811 conflicting_input
= 1;
5812 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
5813 min_conflicting_input_opnum
= rld
[j
].opnum
;
5817 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5818 we, in fact, found any matching reloads. */
5821 && max_input_address_opnum
<= min_conflicting_input_opnum
)
5823 for (j
= 0; j
< n_reloads
; j
++)
5824 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
5825 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
5826 && (! conflicting_input
5827 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
5828 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
5830 rld
[i
].when_needed
= RELOAD_OTHER
;
5832 reload_spill_index
[j
] = -1;
5833 transfer_replacements (i
, j
);
5836 /* If this is now RELOAD_OTHER, look for any reloads that load
5837 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5838 if they were for inputs, RELOAD_OTHER for outputs. Note that
5839 this test is equivalent to looking for reloads for this operand
5842 if (rld
[i
].when_needed
== RELOAD_OTHER
)
5843 for (j
= 0; j
< n_reloads
; j
++)
5845 && rld
[i
].when_needed
!= RELOAD_OTHER
5846 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
5849 = ((rld
[i
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
5850 || rld
[i
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
5851 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
5857 /* These arrays are filled by emit_reload_insns and its subroutines. */
5858 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
5859 static rtx other_input_address_reload_insns
= 0;
5860 static rtx other_input_reload_insns
= 0;
5861 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
5862 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
5863 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
5864 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
5865 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
5866 static rtx operand_reload_insns
= 0;
5867 static rtx other_operand_reload_insns
= 0;
5868 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
5870 /* Values to be put in spill_reg_store are put here first. */
5871 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
5872 static HARD_REG_SET reg_reloaded_died
;
5874 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5875 has the number J. OLD contains the value to be used as input. */
5877 emit_input_reload_insns (chain
, rl
, old
, j
)
5878 struct insn_chain
*chain
;
5883 rtx insn
= chain
->insn
;
5884 register rtx reloadreg
= rl
->reg_rtx
;
5885 rtx oldequiv_reg
= 0;
5888 enum machine_mode mode
;
5891 /* Determine the mode to reload in.
5892 This is very tricky because we have three to choose from.
5893 There is the mode the insn operand wants (rl->inmode).
5894 There is the mode of the reload register RELOADREG.
5895 There is the intrinsic mode of the operand, which we could find
5896 by stripping some SUBREGs.
5897 It turns out that RELOADREG's mode is irrelevant:
5898 we can change that arbitrarily.
5900 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5901 then the reload reg may not support QImode moves, so use SImode.
5902 If foo is in memory due to spilling a pseudo reg, this is safe,
5903 because the QImode value is in the least significant part of a
5904 slot big enough for a SImode. If foo is some other sort of
5905 memory reference, then it is impossible to reload this case,
5906 so previous passes had better make sure this never happens.
5908 Then consider a one-word union which has SImode and one of its
5909 members is a float, being fetched as (SUBREG:SF union:SI).
5910 We must fetch that as SFmode because we could be loading into
5911 a float-only register. In this case OLD's mode is correct.
5913 Consider an immediate integer: it has VOIDmode. Here we need
5914 to get a mode from something else.
5916 In some cases, there is a fourth mode, the operand's
5917 containing mode. If the insn specifies a containing mode for
5918 this operand, it overrides all others.
5920 I am not sure whether the algorithm here is always right,
5921 but it does the right things in those cases. */
5923 mode
= GET_MODE (old
);
5924 if (mode
== VOIDmode
)
5927 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5928 /* If we need a secondary register for this operation, see if
5929 the value is already in a register in that class. Don't
5930 do this if the secondary register will be used as a scratch
5933 if (rl
->secondary_in_reload
>= 0
5934 && rl
->secondary_in_icode
== CODE_FOR_nothing
5937 = find_equiv_reg (old
, insn
,
5938 rld
[rl
->secondary_in_reload
].class,
5939 -1, NULL_PTR
, 0, mode
);
5942 /* If reloading from memory, see if there is a register
5943 that already holds the same value. If so, reload from there.
5944 We can pass 0 as the reload_reg_p argument because
5945 any other reload has either already been emitted,
5946 in which case find_equiv_reg will see the reload-insn,
5947 or has yet to be emitted, in which case it doesn't matter
5948 because we will use this equiv reg right away. */
5950 if (oldequiv
== 0 && optimize
5951 && (GET_CODE (old
) == MEM
5952 || (GET_CODE (old
) == REG
5953 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
5954 && reg_renumber
[REGNO (old
)] < 0)))
5955 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
,
5956 -1, NULL_PTR
, 0, mode
);
5960 int regno
= true_regnum (oldequiv
);
5962 /* Don't use OLDEQUIV if any other reload changes it at an
5963 earlier stage of this insn or at this stage. */
5964 if (! reload_reg_free_for_value_p (regno
, rl
->opnum
,
5966 rl
->in
, const0_rtx
, j
,
5970 /* If it is no cheaper to copy from OLDEQUIV into the
5971 reload register than it would be to move from memory,
5972 don't use it. Likewise, if we need a secondary register
5976 && ((REGNO_REG_CLASS (regno
) != rl
->class
5977 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno
),
5979 >= MEMORY_MOVE_COST (mode
, rl
->class, 1)))
5980 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5981 || (SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
5985 #ifdef SECONDARY_MEMORY_NEEDED
5986 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
5994 /* delete_output_reload is only invoked properly if old contains
5995 the original pseudo register. Since this is replaced with a
5996 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
5997 find the pseudo in RELOAD_IN_REG. */
5999 && reload_override_in
[j
]
6000 && GET_CODE (rl
->in_reg
) == REG
)
6007 else if (GET_CODE (oldequiv
) == REG
)
6008 oldequiv_reg
= oldequiv
;
6009 else if (GET_CODE (oldequiv
) == SUBREG
)
6010 oldequiv_reg
= SUBREG_REG (oldequiv
);
6012 /* If we are reloading from a register that was recently stored in
6013 with an output-reload, see if we can prove there was
6014 actually no need to store the old value in it. */
6016 if (optimize
&& GET_CODE (oldequiv
) == REG
6017 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6018 && spill_reg_store
[REGNO (oldequiv
)]
6019 && GET_CODE (old
) == REG
6020 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6021 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6023 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6025 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6026 then load RELOADREG from OLDEQUIV. Note that we cannot use
6027 gen_lowpart_common since it can do the wrong thing when
6028 RELOADREG has a multi-word mode. Note that RELOADREG
6029 must always be a REG here. */
6031 if (GET_MODE (reloadreg
) != mode
)
6032 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6033 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6034 oldequiv
= SUBREG_REG (oldequiv
);
6035 if (GET_MODE (oldequiv
) != VOIDmode
6036 && mode
!= GET_MODE (oldequiv
))
6037 oldequiv
= gen_rtx_SUBREG (mode
, oldequiv
, 0);
6039 /* Switch to the right place to emit the reload insns. */
6040 switch (rl
->when_needed
)
6043 where
= &other_input_reload_insns
;
6045 case RELOAD_FOR_INPUT
:
6046 where
= &input_reload_insns
[rl
->opnum
];
6048 case RELOAD_FOR_INPUT_ADDRESS
:
6049 where
= &input_address_reload_insns
[rl
->opnum
];
6051 case RELOAD_FOR_INPADDR_ADDRESS
:
6052 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6054 case RELOAD_FOR_OUTPUT_ADDRESS
:
6055 where
= &output_address_reload_insns
[rl
->opnum
];
6057 case RELOAD_FOR_OUTADDR_ADDRESS
:
6058 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6060 case RELOAD_FOR_OPERAND_ADDRESS
:
6061 where
= &operand_reload_insns
;
6063 case RELOAD_FOR_OPADDR_ADDR
:
6064 where
= &other_operand_reload_insns
;
6066 case RELOAD_FOR_OTHER_ADDRESS
:
6067 where
= &other_input_address_reload_insns
;
6073 push_to_sequence (*where
);
6075 /* Auto-increment addresses must be reloaded in a special way. */
6076 if (rl
->out
&& ! rl
->out_reg
)
6078 /* We are not going to bother supporting the case where a
6079 incremented register can't be copied directly from
6080 OLDEQUIV since this seems highly unlikely. */
6081 if (rl
->secondary_in_reload
>= 0)
6084 if (reload_inherited
[j
])
6085 oldequiv
= reloadreg
;
6087 old
= XEXP (rl
->in_reg
, 0);
6089 if (optimize
&& GET_CODE (oldequiv
) == REG
6090 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6091 && spill_reg_store
[REGNO (oldequiv
)]
6092 && GET_CODE (old
) == REG
6093 && (dead_or_set_p (insn
,
6094 spill_reg_stored_to
[REGNO (oldequiv
)])
6095 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6097 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6099 /* Prevent normal processing of this reload. */
6101 /* Output a special code sequence for this case. */
6102 new_spill_reg_store
[REGNO (reloadreg
)]
6103 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6107 /* If we are reloading a pseudo-register that was set by the previous
6108 insn, see if we can get rid of that pseudo-register entirely
6109 by redirecting the previous insn into our reload register. */
6111 else if (optimize
&& GET_CODE (old
) == REG
6112 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6113 && dead_or_set_p (insn
, old
)
6114 /* This is unsafe if some other reload
6115 uses the same reg first. */
6116 && reload_reg_free_for_value_p (REGNO (reloadreg
),
6122 rtx temp
= PREV_INSN (insn
);
6123 while (temp
&& GET_CODE (temp
) == NOTE
)
6124 temp
= PREV_INSN (temp
);
6126 && GET_CODE (temp
) == INSN
6127 && GET_CODE (PATTERN (temp
)) == SET
6128 && SET_DEST (PATTERN (temp
)) == old
6129 /* Make sure we can access insn_operand_constraint. */
6130 && asm_noperands (PATTERN (temp
)) < 0
6131 /* This is unsafe if prev insn rejects our reload reg. */
6132 && constraint_accepts_reg_p (insn_data
[recog_memoized (temp
)].operand
[0].constraint
,
6134 /* This is unsafe if operand occurs more than once in current
6135 insn. Perhaps some occurrences aren't reloaded. */
6136 && count_occurrences (PATTERN (insn
), old
) == 1
6137 /* Don't risk splitting a matching pair of operands. */
6138 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
6140 /* Store into the reload register instead of the pseudo. */
6141 SET_DEST (PATTERN (temp
)) = reloadreg
;
6143 /* If the previous insn is an output reload, the source is
6144 a reload register, and its spill_reg_store entry will
6145 contain the previous destination. This is now
6147 if (GET_CODE (SET_SRC (PATTERN (temp
))) == REG
6148 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6150 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6151 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6154 /* If these are the only uses of the pseudo reg,
6155 pretend for GDB it lives in the reload reg we used. */
6156 if (REG_N_DEATHS (REGNO (old
)) == 1
6157 && REG_N_SETS (REGNO (old
)) == 1)
6159 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6160 alter_reg (REGNO (old
), -1);
6166 /* We can't do that, so output an insn to load RELOADREG. */
6168 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6169 /* If we have a secondary reload, pick up the secondary register
6170 and icode, if any. If OLDEQUIV and OLD are different or
6171 if this is an in-out reload, recompute whether or not we
6172 still need a secondary register and what the icode should
6173 be. If we still need a secondary register and the class or
6174 icode is different, go back to reloading from OLD if using
6175 OLDEQUIV means that we got the wrong type of register. We
6176 cannot have different class or icode due to an in-out reload
6177 because we don't make such reloads when both the input and
6178 output need secondary reload registers. */
6180 if (! special
&& rl
->secondary_in_reload
>= 0)
6182 rtx second_reload_reg
= 0;
6183 int secondary_reload
= rl
->secondary_in_reload
;
6184 rtx real_oldequiv
= oldequiv
;
6187 enum insn_code icode
;
6189 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6190 and similarly for OLD.
6191 See comments in get_secondary_reload in reload.c. */
6192 /* If it is a pseudo that cannot be replaced with its
6193 equivalent MEM, we must fall back to reload_in, which
6194 will have all the necessary substitutions registered.
6195 Likewise for a pseudo that can't be replaced with its
6196 equivalent constant.
6198 Take extra care for subregs of such pseudos. Note that
6199 we cannot use reg_equiv_mem in this case because it is
6200 not in the right mode. */
6203 if (GET_CODE (tmp
) == SUBREG
)
6204 tmp
= SUBREG_REG (tmp
);
6205 if (GET_CODE (tmp
) == REG
6206 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6207 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6208 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6210 if (! reg_equiv_mem
[REGNO (tmp
)]
6211 || num_not_at_initial_offset
6212 || GET_CODE (oldequiv
) == SUBREG
)
6213 real_oldequiv
= rl
->in
;
6215 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6219 if (GET_CODE (tmp
) == SUBREG
)
6220 tmp
= SUBREG_REG (tmp
);
6221 if (GET_CODE (tmp
) == REG
6222 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6223 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6224 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6226 if (! reg_equiv_mem
[REGNO (tmp
)]
6227 || num_not_at_initial_offset
6228 || GET_CODE (old
) == SUBREG
)
6231 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6234 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6235 icode
= rl
->secondary_in_icode
;
6237 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6238 || (rl
->in
!= 0 && rl
->out
!= 0))
6240 enum reg_class new_class
6241 = SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6242 mode
, real_oldequiv
);
6244 if (new_class
== NO_REGS
)
6245 second_reload_reg
= 0;
6248 enum insn_code new_icode
;
6249 enum machine_mode new_mode
;
6251 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6252 REGNO (second_reload_reg
)))
6253 oldequiv
= old
, real_oldequiv
= real_old
;
6256 new_icode
= reload_in_optab
[(int) mode
];
6257 if (new_icode
!= CODE_FOR_nothing
6258 && ((insn_data
[(int) new_icode
].operand
[0].predicate
6259 && ! ((*insn_data
[(int) new_icode
].operand
[0].predicate
)
6261 || (insn_data
[(int) new_icode
].operand
[1].predicate
6262 && ! ((*insn_data
[(int) new_icode
].operand
[1].predicate
)
6263 (real_oldequiv
, mode
)))))
6264 new_icode
= CODE_FOR_nothing
;
6266 if (new_icode
== CODE_FOR_nothing
)
6269 new_mode
= insn_data
[(int) new_icode
].operand
[2].mode
;
6271 if (GET_MODE (second_reload_reg
) != new_mode
)
6273 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6275 oldequiv
= old
, real_oldequiv
= real_old
;
6278 = gen_rtx_REG (new_mode
,
6279 REGNO (second_reload_reg
));
6285 /* If we still need a secondary reload register, check
6286 to see if it is being used as a scratch or intermediate
6287 register and generate code appropriately. If we need
6288 a scratch register, use REAL_OLDEQUIV since the form of
6289 the insn may depend on the actual address if it is
6292 if (second_reload_reg
)
6294 if (icode
!= CODE_FOR_nothing
)
6296 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6297 second_reload_reg
));
6302 /* See if we need a scratch register to load the
6303 intermediate register (a tertiary reload). */
6304 enum insn_code tertiary_icode
6305 = rld
[secondary_reload
].secondary_in_icode
;
6307 if (tertiary_icode
!= CODE_FOR_nothing
)
6309 rtx third_reload_reg
6310 = rld
[rld
[secondary_reload
].secondary_in_reload
].reg_rtx
;
6312 emit_insn ((GEN_FCN (tertiary_icode
)
6313 (second_reload_reg
, real_oldequiv
,
6314 third_reload_reg
)));
6317 gen_reload (second_reload_reg
, real_oldequiv
,
6321 oldequiv
= second_reload_reg
;
6327 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6329 rtx real_oldequiv
= oldequiv
;
6331 if ((GET_CODE (oldequiv
) == REG
6332 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6333 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6334 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6335 || (GET_CODE (oldequiv
) == SUBREG
6336 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
6337 && (REGNO (SUBREG_REG (oldequiv
))
6338 >= FIRST_PSEUDO_REGISTER
)
6339 && ((reg_equiv_memory_loc
6340 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6341 || (reg_equiv_constant
6342 [REGNO (SUBREG_REG (oldequiv
))] != 0))))
6343 real_oldequiv
= rl
->in
;
6344 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6348 /* End this sequence. */
6349 *where
= get_insns ();
6352 /* Update reload_override_in so that delete_address_reloads_1
6353 can see the actual register usage. */
6355 reload_override_in
[j
] = oldequiv
;
6358 /* Generate insns to for the output reload RL, which is for the insn described
6359 by CHAIN and has the number J. */
6361 emit_output_reload_insns (chain
, rl
, j
)
6362 struct insn_chain
*chain
;
6366 rtx reloadreg
= rl
->reg_rtx
;
6367 rtx insn
= chain
->insn
;
6370 enum machine_mode mode
= GET_MODE (old
);
6373 if (rl
->when_needed
== RELOAD_OTHER
)
6376 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6378 /* Determine the mode to reload in.
6379 See comments above (for input reloading). */
6381 if (mode
== VOIDmode
)
6383 /* VOIDmode should never happen for an output. */
6384 if (asm_noperands (PATTERN (insn
)) < 0)
6385 /* It's the compiler's fault. */
6386 fatal_insn ("VOIDmode on an output", insn
);
6387 error_for_asm (insn
, "output operand is constant in `asm'");
6388 /* Prevent crash--use something we know is valid. */
6390 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6393 if (GET_MODE (reloadreg
) != mode
)
6394 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6396 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6398 /* If we need two reload regs, set RELOADREG to the intermediate
6399 one, since it will be stored into OLD. We might need a secondary
6400 register only for an input reload, so check again here. */
6402 if (rl
->secondary_out_reload
>= 0)
6406 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
6407 && reg_equiv_mem
[REGNO (old
)] != 0)
6408 real_old
= reg_equiv_mem
[REGNO (old
)];
6410 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl
->class,
6414 rtx second_reloadreg
= reloadreg
;
6415 reloadreg
= rld
[rl
->secondary_out_reload
].reg_rtx
;
6417 /* See if RELOADREG is to be used as a scratch register
6418 or as an intermediate register. */
6419 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
6421 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
6422 (real_old
, second_reloadreg
, reloadreg
)));
6427 /* See if we need both a scratch and intermediate reload
6430 int secondary_reload
= rl
->secondary_out_reload
;
6431 enum insn_code tertiary_icode
6432 = rld
[secondary_reload
].secondary_out_icode
;
6434 if (GET_MODE (reloadreg
) != mode
)
6435 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6437 if (tertiary_icode
!= CODE_FOR_nothing
)
6440 = rld
[rld
[secondary_reload
].secondary_out_reload
].reg_rtx
;
6443 /* Copy primary reload reg to secondary reload reg.
6444 (Note that these have been swapped above, then
6445 secondary reload reg to OLD using our insn. */
6447 /* If REAL_OLD is a paradoxical SUBREG, remove it
6448 and try to put the opposite SUBREG on
6450 if (GET_CODE (real_old
) == SUBREG
6451 && (GET_MODE_SIZE (GET_MODE (real_old
))
6452 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
6453 && 0 != (tem
= gen_lowpart_common
6454 (GET_MODE (SUBREG_REG (real_old
)),
6456 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
6458 gen_reload (reloadreg
, second_reloadreg
,
6459 rl
->opnum
, rl
->when_needed
);
6460 emit_insn ((GEN_FCN (tertiary_icode
)
6461 (real_old
, reloadreg
, third_reloadreg
)));
6466 /* Copy between the reload regs here and then to
6469 gen_reload (reloadreg
, second_reloadreg
,
6470 rl
->opnum
, rl
->when_needed
);
6476 /* Output the last reload insn. */
6481 /* Don't output the last reload if OLD is not the dest of
6482 INSN and is in the src and is clobbered by INSN. */
6483 if (! flag_expensive_optimizations
6484 || GET_CODE (old
) != REG
6485 || !(set
= single_set (insn
))
6486 || rtx_equal_p (old
, SET_DEST (set
))
6487 || !reg_mentioned_p (old
, SET_SRC (set
))
6488 || !regno_clobbered_p (REGNO (old
), insn
))
6489 gen_reload (old
, reloadreg
, rl
->opnum
,
6493 /* Look at all insns we emitted, just to be safe. */
6494 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6495 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
6497 rtx pat
= PATTERN (p
);
6499 /* If this output reload doesn't come from a spill reg,
6500 clear any memory of reloaded copies of the pseudo reg.
6501 If this output reload comes from a spill reg,
6502 reg_has_output_reload will make this do nothing. */
6503 note_stores (pat
, forget_old_reloads_1
, NULL
);
6505 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
6507 rtx set
= single_set (insn
);
6508 if (reload_spill_index
[j
] < 0
6510 && SET_SRC (set
) == rl
->reg_rtx
)
6512 int src
= REGNO (SET_SRC (set
));
6514 reload_spill_index
[j
] = src
;
6515 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
6516 if (find_regno_note (insn
, REG_DEAD
, src
))
6517 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
6519 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6521 int s
= rl
->secondary_out_reload
;
6522 set
= single_set (p
);
6523 /* If this reload copies only to the secondary reload
6524 register, the secondary reload does the actual
6526 if (s
>= 0 && set
== NULL_RTX
)
6527 ; /* We can't tell what function the secondary reload
6528 has and where the actual store to the pseudo is
6529 made; leave new_spill_reg_store alone. */
6531 && SET_SRC (set
) == rl
->reg_rtx
6532 && SET_DEST (set
) == rld
[s
].reg_rtx
)
6534 /* Usually the next instruction will be the
6535 secondary reload insn; if we can confirm
6536 that it is, setting new_spill_reg_store to
6537 that insn will allow an extra optimization. */
6538 rtx s_reg
= rld
[s
].reg_rtx
;
6539 rtx next
= NEXT_INSN (p
);
6540 rld
[s
].out
= rl
->out
;
6541 rld
[s
].out_reg
= rl
->out_reg
;
6542 set
= single_set (next
);
6543 if (set
&& SET_SRC (set
) == s_reg
6544 && ! new_spill_reg_store
[REGNO (s_reg
)])
6546 SET_HARD_REG_BIT (reg_is_output_reload
,
6548 new_spill_reg_store
[REGNO (s_reg
)] = next
;
6552 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
6557 if (rl
->when_needed
== RELOAD_OTHER
)
6559 emit_insns (other_output_reload_insns
[rl
->opnum
]);
6560 other_output_reload_insns
[rl
->opnum
] = get_insns ();
6563 output_reload_insns
[rl
->opnum
] = get_insns ();
6568 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6569 and has the number J. */
6571 do_input_reload (chain
, rl
, j
)
6572 struct insn_chain
*chain
;
6576 int expect_occurrences
= 1;
6577 rtx insn
= chain
->insn
;
6578 rtx old
= (rl
->in
&& GET_CODE (rl
->in
) == MEM
6579 ? rl
->in_reg
: rl
->in
);
6582 /* AUTO_INC reloads need to be handled even if inherited. We got an
6583 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6584 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
6585 && ! rtx_equal_p (rl
->reg_rtx
, old
)
6586 && rl
->reg_rtx
!= 0)
6588 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
6591 /* When inheriting a wider reload, we have a MEM in rl->in,
6592 e.g. inheriting a SImode output reload for
6593 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6594 if (optimize
&& reload_inherited
[j
] && rl
->in
6595 && GET_CODE (rl
->in
) == MEM
6596 && GET_CODE (rl
->in_reg
) == MEM
6597 && reload_spill_index
[j
] >= 0
6598 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6601 = count_occurrences (PATTERN (insn
), rl
->in
) == 1 ? 0 : -1;
6603 = regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6606 /* If we are reloading a register that was recently stored in with an
6607 output-reload, see if we can prove there was
6608 actually no need to store the old value in it. */
6611 && (reload_inherited
[j
] || reload_override_in
[j
])
6613 && GET_CODE (rl
->reg_rtx
) == REG
6614 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
6616 /* There doesn't seem to be any reason to restrict this to pseudos
6617 and doing so loses in the case where we are copying from a
6618 register of the wrong class. */
6619 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6620 >= FIRST_PSEUDO_REGISTER
)
6622 /* The insn might have already some references to stackslots
6623 replaced by MEMs, while reload_out_reg still names the
6625 && (dead_or_set_p (insn
,
6626 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6627 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
6629 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
6632 /* Do output reloading for reload RL, which is for the insn described by
6633 CHAIN and has the number J.
6634 ??? At some point we need to support handling output reloads of
6635 JUMP_INSNs or insns that set cc0. */
6637 do_output_reload (chain
, rl
, j
)
6638 struct insn_chain
*chain
;
6643 rtx insn
= chain
->insn
;
6644 /* If this is an output reload that stores something that is
6645 not loaded in this same reload, see if we can eliminate a previous
6647 rtx pseudo
= rl
->out_reg
;
6650 && GET_CODE (pseudo
) == REG
6651 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
6652 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
6653 && reg_last_reload_reg
[REGNO (pseudo
)])
6655 int pseudo_no
= REGNO (pseudo
);
6656 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
6658 /* We don't need to test full validity of last_regno for
6659 inherit here; we only want to know if the store actually
6660 matches the pseudo. */
6661 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
6662 && reg_reloaded_contents
[last_regno
] == pseudo_no
6663 && spill_reg_store
[last_regno
]
6664 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
6665 delete_output_reload (insn
, j
, last_regno
);
6670 || rl
->reg_rtx
== old
6671 || rl
->reg_rtx
== 0)
6674 /* An output operand that dies right away does need a reload,
6675 but need not be copied from it. Show the new location in the
6677 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
6678 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
6680 XEXP (note
, 0) = rl
->reg_rtx
;
6683 /* Likewise for a SUBREG of an operand that dies. */
6684 else if (GET_CODE (old
) == SUBREG
6685 && GET_CODE (SUBREG_REG (old
)) == REG
6686 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
6689 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
6693 else if (GET_CODE (old
) == SCRATCH
)
6694 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6695 but we don't want to make an output reload. */
6698 /* If is a JUMP_INSN, we can't support output reloads yet. */
6699 if (GET_CODE (insn
) == JUMP_INSN
)
6702 emit_output_reload_insns (chain
, rld
+ j
, j
);
6705 /* Output insns to reload values in and out of the chosen reload regs. */
6708 emit_reload_insns (chain
)
6709 struct insn_chain
*chain
;
6711 rtx insn
= chain
->insn
;
6714 rtx following_insn
= NEXT_INSN (insn
);
6715 rtx before_insn
= PREV_INSN (insn
);
6717 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6719 for (j
= 0; j
< reload_n_operands
; j
++)
6720 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6721 = inpaddr_address_reload_insns
[j
]
6722 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6723 = outaddr_address_reload_insns
[j
]
6724 = other_output_reload_insns
[j
] = 0;
6725 other_input_address_reload_insns
= 0;
6726 other_input_reload_insns
= 0;
6727 operand_reload_insns
= 0;
6728 other_operand_reload_insns
= 0;
6730 /* Now output the instructions to copy the data into and out of the
6731 reload registers. Do these in the order that the reloads were reported,
6732 since reloads of base and index registers precede reloads of operands
6733 and the operands may need the base and index registers reloaded. */
6735 for (j
= 0; j
< n_reloads
; j
++)
6738 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6739 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
6741 do_input_reload (chain
, rld
+ j
, j
);
6742 do_output_reload (chain
, rld
+ j
, j
);
6745 /* Now write all the insns we made for reloads in the order expected by
6746 the allocation functions. Prior to the insn being reloaded, we write
6747 the following reloads:
6749 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6751 RELOAD_OTHER reloads.
6753 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6754 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6755 RELOAD_FOR_INPUT reload for the operand.
6757 RELOAD_FOR_OPADDR_ADDRS reloads.
6759 RELOAD_FOR_OPERAND_ADDRESS reloads.
6761 After the insn being reloaded, we write the following:
6763 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6764 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6765 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6766 reloads for the operand. The RELOAD_OTHER output reloads are
6767 output in descending order by reload number. */
6769 emit_insns_before (other_input_address_reload_insns
, insn
);
6770 emit_insns_before (other_input_reload_insns
, insn
);
6772 for (j
= 0; j
< reload_n_operands
; j
++)
6774 emit_insns_before (inpaddr_address_reload_insns
[j
], insn
);
6775 emit_insns_before (input_address_reload_insns
[j
], insn
);
6776 emit_insns_before (input_reload_insns
[j
], insn
);
6779 emit_insns_before (other_operand_reload_insns
, insn
);
6780 emit_insns_before (operand_reload_insns
, insn
);
6782 for (j
= 0; j
< reload_n_operands
; j
++)
6784 emit_insns_before (outaddr_address_reload_insns
[j
], following_insn
);
6785 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
6786 emit_insns_before (output_reload_insns
[j
], following_insn
);
6787 emit_insns_before (other_output_reload_insns
[j
], following_insn
);
6790 /* Keep basic block info up to date. */
6793 if (BLOCK_HEAD (chain
->block
) == insn
)
6794 BLOCK_HEAD (chain
->block
) = NEXT_INSN (before_insn
);
6795 if (BLOCK_END (chain
->block
) == insn
)
6796 BLOCK_END (chain
->block
) = PREV_INSN (following_insn
);
6799 /* For all the spill regs newly reloaded in this instruction,
6800 record what they were reloaded from, so subsequent instructions
6801 can inherit the reloads.
6803 Update spill_reg_store for the reloads of this insn.
6804 Copy the elements that were updated in the loop above. */
6806 for (j
= 0; j
< n_reloads
; j
++)
6808 register int r
= reload_order
[j
];
6809 register int i
= reload_spill_index
[r
];
6811 /* If this is a non-inherited input reload from a pseudo, we must
6812 clear any memory of a previous store to the same pseudo. Only do
6813 something if there will not be an output reload for the pseudo
6815 if (rld
[r
].in_reg
!= 0
6816 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
6818 rtx reg
= rld
[r
].in_reg
;
6820 if (GET_CODE (reg
) == SUBREG
)
6821 reg
= SUBREG_REG (reg
);
6823 if (GET_CODE (reg
) == REG
6824 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
6825 && ! reg_has_output_reload
[REGNO (reg
)])
6827 int nregno
= REGNO (reg
);
6829 if (reg_last_reload_reg
[nregno
])
6831 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
6833 if (reg_reloaded_contents
[last_regno
] == nregno
)
6834 spill_reg_store
[last_regno
] = 0;
6839 /* I is nonneg if this reload used a register.
6840 If rld[r].reg_rtx is 0, this is an optional reload
6841 that we opted to ignore. */
6843 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
6846 = HARD_REGNO_NREGS (i
, GET_MODE (rld
[r
].reg_rtx
));
6848 int part_reaches_end
= 0;
6849 int all_reaches_end
= 1;
6851 /* For a multi register reload, we need to check if all or part
6852 of the value lives to the end. */
6853 for (k
= 0; k
< nr
; k
++)
6855 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
6856 rld
[r
].when_needed
))
6857 part_reaches_end
= 1;
6859 all_reaches_end
= 0;
6862 /* Ignore reloads that don't reach the end of the insn in
6864 if (all_reaches_end
)
6866 /* First, clear out memory of what used to be in this spill reg.
6867 If consecutive registers are used, clear them all. */
6869 for (k
= 0; k
< nr
; k
++)
6870 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
6872 /* Maybe the spill reg contains a copy of reload_out. */
6874 && (GET_CODE (rld
[r
].out
) == REG
6878 || GET_CODE (rld
[r
].out_reg
) == REG
))
6880 rtx out
= (GET_CODE (rld
[r
].out
) == REG
6884 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
6885 register int nregno
= REGNO (out
);
6886 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
6887 : HARD_REGNO_NREGS (nregno
,
6888 GET_MODE (rld
[r
].reg_rtx
)));
6890 spill_reg_store
[i
] = new_spill_reg_store
[i
];
6891 spill_reg_stored_to
[i
] = out
;
6892 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
6894 /* If NREGNO is a hard register, it may occupy more than
6895 one register. If it does, say what is in the
6896 rest of the registers assuming that both registers
6897 agree on how many words the object takes. If not,
6898 invalidate the subsequent registers. */
6900 if (nregno
< FIRST_PSEUDO_REGISTER
)
6901 for (k
= 1; k
< nnr
; k
++)
6902 reg_last_reload_reg
[nregno
+ k
]
6904 ? gen_rtx_REG (reg_raw_mode
[REGNO (rld
[r
].reg_rtx
) + k
],
6905 REGNO (rld
[r
].reg_rtx
) + k
)
6908 /* Now do the inverse operation. */
6909 for (k
= 0; k
< nr
; k
++)
6911 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
6912 reg_reloaded_contents
[i
+ k
]
6913 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
6916 reg_reloaded_insn
[i
+ k
] = insn
;
6917 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
6921 /* Maybe the spill reg contains a copy of reload_in. Only do
6922 something if there will not be an output reload for
6923 the register being reloaded. */
6924 else if (rld
[r
].out_reg
== 0
6926 && ((GET_CODE (rld
[r
].in
) == REG
6927 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
6928 && ! reg_has_output_reload
[REGNO (rld
[r
].in
)])
6929 || (GET_CODE (rld
[r
].in_reg
) == REG
6930 && ! reg_has_output_reload
[REGNO (rld
[r
].in_reg
)]))
6931 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
6933 register int nregno
;
6936 if (GET_CODE (rld
[r
].in
) == REG
6937 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
6938 nregno
= REGNO (rld
[r
].in
);
6939 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
6940 nregno
= REGNO (rld
[r
].in_reg
);
6942 nregno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6944 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
6945 : HARD_REGNO_NREGS (nregno
,
6946 GET_MODE (rld
[r
].reg_rtx
)));
6948 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
6950 if (nregno
< FIRST_PSEUDO_REGISTER
)
6951 for (k
= 1; k
< nnr
; k
++)
6952 reg_last_reload_reg
[nregno
+ k
]
6954 ? gen_rtx_REG (reg_raw_mode
[REGNO (rld
[r
].reg_rtx
) + k
],
6955 REGNO (rld
[r
].reg_rtx
) + k
)
6958 /* Unless we inherited this reload, show we haven't
6959 recently done a store.
6960 Previous stores of inherited auto_inc expressions
6961 also have to be discarded. */
6962 if (! reload_inherited
[r
]
6963 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
6964 spill_reg_store
[i
] = 0;
6966 for (k
= 0; k
< nr
; k
++)
6968 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
6969 reg_reloaded_contents
[i
+ k
]
6970 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
6973 reg_reloaded_insn
[i
+ k
] = insn
;
6974 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
6979 /* However, if part of the reload reaches the end, then we must
6980 invalidate the old info for the part that survives to the end. */
6981 else if (part_reaches_end
)
6983 for (k
= 0; k
< nr
; k
++)
6984 if (reload_reg_reaches_end_p (i
+ k
,
6986 rld
[r
].when_needed
))
6987 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
6991 /* The following if-statement was #if 0'd in 1.34 (or before...).
6992 It's reenabled in 1.35 because supposedly nothing else
6993 deals with this problem. */
6995 /* If a register gets output-reloaded from a non-spill register,
6996 that invalidates any previous reloaded copy of it.
6997 But forget_old_reloads_1 won't get to see it, because
6998 it thinks only about the original insn. So invalidate it here. */
6999 if (i
< 0 && rld
[r
].out
!= 0
7000 && (GET_CODE (rld
[r
].out
) == REG
7001 || (GET_CODE (rld
[r
].out
) == MEM
7002 && GET_CODE (rld
[r
].out_reg
) == REG
)))
7004 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7005 ? rld
[r
].out
: rld
[r
].out_reg
);
7006 register int nregno
= REGNO (out
);
7007 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7009 rtx src_reg
, store_insn
= NULL_RTX
;
7011 reg_last_reload_reg
[nregno
] = 0;
7013 /* If we can find a hard register that is stored, record
7014 the storing insn so that we may delete this insn with
7015 delete_output_reload. */
7016 src_reg
= rld
[r
].reg_rtx
;
7018 /* If this is an optional reload, try to find the source reg
7019 from an input reload. */
7022 rtx set
= single_set (insn
);
7023 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7027 src_reg
= SET_SRC (set
);
7029 for (k
= 0; k
< n_reloads
; k
++)
7031 if (rld
[k
].in
== src_reg
)
7033 src_reg
= rld
[k
].reg_rtx
;
7040 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7041 if (src_reg
&& GET_CODE (src_reg
) == REG
7042 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7044 int src_regno
= REGNO (src_reg
);
7045 int nr
= HARD_REGNO_NREGS (src_regno
, rld
[r
].mode
);
7046 /* The place where to find a death note varies with
7047 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7048 necessarily checked exactly in the code that moves
7049 notes, so just check both locations. */
7050 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7052 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7055 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7056 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7057 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7058 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7059 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7060 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7061 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7063 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7065 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7067 reg_last_reload_reg
[nregno
] = src_reg
;
7072 int num_regs
= HARD_REGNO_NREGS (nregno
,GET_MODE (rld
[r
].out
));
7074 while (num_regs
-- > 0)
7075 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7079 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7082 /* Emit code to perform a reload from IN (which may be a reload register) to
7083 OUT (which may also be a reload register). IN or OUT is from operand
7084 OPNUM with reload type TYPE.
7086 Returns first insn emitted. */
7089 gen_reload (out
, in
, opnum
, type
)
7093 enum reload_type type
;
7095 rtx last
= get_last_insn ();
7098 /* If IN is a paradoxical SUBREG, remove it and try to put the
7099 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7100 if (GET_CODE (in
) == SUBREG
7101 && (GET_MODE_SIZE (GET_MODE (in
))
7102 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7103 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7104 in
= SUBREG_REG (in
), out
= tem
;
7105 else if (GET_CODE (out
) == SUBREG
7106 && (GET_MODE_SIZE (GET_MODE (out
))
7107 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7108 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7109 out
= SUBREG_REG (out
), in
= tem
;
7111 /* How to do this reload can get quite tricky. Normally, we are being
7112 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7113 register that didn't get a hard register. In that case we can just
7114 call emit_move_insn.
7116 We can also be asked to reload a PLUS that adds a register or a MEM to
7117 another register, constant or MEM. This can occur during frame pointer
7118 elimination and while reloading addresses. This case is handled by
7119 trying to emit a single insn to perform the add. If it is not valid,
7120 we use a two insn sequence.
7122 Finally, we could be called to handle an 'o' constraint by putting
7123 an address into a register. In that case, we first try to do this
7124 with a named pattern of "reload_load_address". If no such pattern
7125 exists, we just emit a SET insn and hope for the best (it will normally
7126 be valid on machines that use 'o').
7128 This entire process is made complex because reload will never
7129 process the insns we generate here and so we must ensure that
7130 they will fit their constraints and also by the fact that parts of
7131 IN might be being reloaded separately and replaced with spill registers.
7132 Because of this, we are, in some sense, just guessing the right approach
7133 here. The one listed above seems to work.
7135 ??? At some point, this whole thing needs to be rethought. */
7137 if (GET_CODE (in
) == PLUS
7138 && (GET_CODE (XEXP (in
, 0)) == REG
7139 || GET_CODE (XEXP (in
, 0)) == SUBREG
7140 || GET_CODE (XEXP (in
, 0)) == MEM
)
7141 && (GET_CODE (XEXP (in
, 1)) == REG
7142 || GET_CODE (XEXP (in
, 1)) == SUBREG
7143 || CONSTANT_P (XEXP (in
, 1))
7144 || GET_CODE (XEXP (in
, 1)) == MEM
))
7146 /* We need to compute the sum of a register or a MEM and another
7147 register, constant, or MEM, and put it into the reload
7148 register. The best possible way of doing this is if the machine
7149 has a three-operand ADD insn that accepts the required operands.
7151 The simplest approach is to try to generate such an insn and see if it
7152 is recognized and matches its constraints. If so, it can be used.
7154 It might be better not to actually emit the insn unless it is valid,
7155 but we need to pass the insn as an operand to `recog' and
7156 `extract_insn' and it is simpler to emit and then delete the insn if
7157 not valid than to dummy things up. */
7159 rtx op0
, op1
, tem
, insn
;
7162 op0
= find_replacement (&XEXP (in
, 0));
7163 op1
= find_replacement (&XEXP (in
, 1));
7165 /* Since constraint checking is strict, commutativity won't be
7166 checked, so we need to do that here to avoid spurious failure
7167 if the add instruction is two-address and the second operand
7168 of the add is the same as the reload reg, which is frequently
7169 the case. If the insn would be A = B + A, rearrange it so
7170 it will be A = A + B as constrain_operands expects. */
7172 if (GET_CODE (XEXP (in
, 1)) == REG
7173 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7174 tem
= op0
, op0
= op1
, op1
= tem
;
7176 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7177 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7179 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7180 code
= recog_memoized (insn
);
7184 extract_insn (insn
);
7185 /* We want constrain operands to treat this insn strictly in
7186 its validity determination, i.e., the way it would after reload
7188 if (constrain_operands (1))
7192 delete_insns_since (last
);
7194 /* If that failed, we must use a conservative two-insn sequence.
7196 Use a move to copy one operand into the reload register. Prefer
7197 to reload a constant, MEM or pseudo since the move patterns can
7198 handle an arbitrary operand. If OP1 is not a constant, MEM or
7199 pseudo and OP1 is not a valid operand for an add instruction, then
7202 After reloading one of the operands into the reload register, add
7203 the reload register to the output register.
7205 If there is another way to do this for a specific machine, a
7206 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7209 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7211 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7212 || (GET_CODE (op1
) == REG
7213 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7214 || (code
!= CODE_FOR_nothing
7215 && ! ((*insn_data
[code
].operand
[2].predicate
)
7216 (op1
, insn_data
[code
].operand
[2].mode
))))
7217 tem
= op0
, op0
= op1
, op1
= tem
;
7219 gen_reload (out
, op0
, opnum
, type
);
7221 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7222 This fixes a problem on the 32K where the stack pointer cannot
7223 be used as an operand of an add insn. */
7225 if (rtx_equal_p (op0
, op1
))
7228 insn
= emit_insn (gen_add2_insn (out
, op1
));
7230 /* If that failed, copy the address register to the reload register.
7231 Then add the constant to the reload register. */
7233 code
= recog_memoized (insn
);
7237 extract_insn (insn
);
7238 /* We want constrain operands to treat this insn strictly in
7239 its validity determination, i.e., the way it would after reload
7241 if (constrain_operands (1))
7243 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7245 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7250 delete_insns_since (last
);
7252 gen_reload (out
, op1
, opnum
, type
);
7253 insn
= emit_insn (gen_add2_insn (out
, op0
));
7254 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7257 #ifdef SECONDARY_MEMORY_NEEDED
7258 /* If we need a memory location to do the move, do it that way. */
7259 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
7260 && GET_CODE (out
) == REG
&& REGNO (out
) < FIRST_PSEUDO_REGISTER
7261 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
7262 REGNO_REG_CLASS (REGNO (out
)),
7265 /* Get the memory to use and rewrite both registers to its mode. */
7266 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7268 if (GET_MODE (loc
) != GET_MODE (out
))
7269 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7271 if (GET_MODE (loc
) != GET_MODE (in
))
7272 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7274 gen_reload (loc
, in
, opnum
, type
);
7275 gen_reload (out
, loc
, opnum
, type
);
7279 /* If IN is a simple operand, use gen_move_insn. */
7280 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7281 emit_insn (gen_move_insn (out
, in
));
7283 #ifdef HAVE_reload_load_address
7284 else if (HAVE_reload_load_address
)
7285 emit_insn (gen_reload_load_address (out
, in
));
7288 /* Otherwise, just write (set OUT IN) and hope for the best. */
7290 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7292 /* Return the first insn emitted.
7293 We can not just return get_last_insn, because there may have
7294 been multiple instructions emitted. Also note that gen_move_insn may
7295 emit more than one insn itself, so we can not assume that there is one
7296 insn emitted per emit_insn_before call. */
7298 return last
? NEXT_INSN (last
) : get_insns ();
7301 /* Delete a previously made output-reload
7302 whose result we now believe is not needed.
7303 First we double-check.
7305 INSN is the insn now being processed.
7306 LAST_RELOAD_REG is the hard register number for which we want to delete
7307 the last output reload.
7308 J is the reload-number that originally used REG. The caller has made
7309 certain that reload J doesn't use REG any longer for input. */
7312 delete_output_reload (insn
, j
, last_reload_reg
)
7315 int last_reload_reg
;
7317 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7318 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7321 int n_inherited
= 0;
7325 /* Get the raw pseudo-register referred to. */
7327 while (GET_CODE (reg
) == SUBREG
)
7328 reg
= SUBREG_REG (reg
);
7329 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7331 /* This is unsafe if the operand occurs more often in the current
7332 insn than it is inherited. */
7333 for (k
= n_reloads
- 1; k
>= 0; k
--)
7335 rtx reg2
= rld
[k
].in
;
7338 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
7339 reg2
= rld
[k
].in_reg
;
7341 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
7342 reg2
= XEXP (rld
[k
].in_reg
, 0);
7344 while (GET_CODE (reg2
) == SUBREG
)
7345 reg2
= SUBREG_REG (reg2
);
7346 if (rtx_equal_p (reg2
, reg
))
7348 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7351 reg2
= rld
[k
].out_reg
;
7354 while (GET_CODE (reg2
) == SUBREG
)
7355 reg2
= XEXP (reg2
, 0);
7356 if (rtx_equal_p (reg2
, reg
))
7363 n_occurrences
= count_occurrences (PATTERN (insn
), reg
);
7365 n_occurrences
+= count_occurrences (PATTERN (insn
), substed
);
7366 if (n_occurrences
> n_inherited
)
7369 /* If the pseudo-reg we are reloading is no longer referenced
7370 anywhere between the store into it and here,
7371 and no jumps or labels intervene, then the value can get
7372 here through the reload reg alone.
7373 Otherwise, give up--return. */
7374 for (i1
= NEXT_INSN (output_reload_insn
);
7375 i1
!= insn
; i1
= NEXT_INSN (i1
))
7377 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7379 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7380 && reg_mentioned_p (reg
, PATTERN (i1
)))
7382 /* If this is USE in front of INSN, we only have to check that
7383 there are no more references than accounted for by inheritance. */
7384 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
7386 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7387 i1
= NEXT_INSN (i1
);
7389 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7395 /* The caller has already checked that REG dies or is set in INSN.
7396 It has also checked that we are optimizing, and thus some inaccurancies
7397 in the debugging information are acceptable.
7398 So we could just delete output_reload_insn.
7399 But in some cases we can improve the debugging information without
7400 sacrificing optimization - maybe even improving the code:
7401 See if the pseudo reg has been completely replaced
7402 with reload regs. If so, delete the store insn
7403 and forget we had a stack slot for the pseudo. */
7404 if (rld
[j
].out
!= rld
[j
].in
7405 && REG_N_DEATHS (REGNO (reg
)) == 1
7406 && REG_N_SETS (REGNO (reg
)) == 1
7407 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7408 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7412 /* We know that it was used only between here
7413 and the beginning of the current basic block.
7414 (We also know that the last use before INSN was
7415 the output reload we are thinking of deleting, but never mind that.)
7416 Search that range; see if any ref remains. */
7417 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7419 rtx set
= single_set (i2
);
7421 /* Uses which just store in the pseudo don't count,
7422 since if they are the only uses, they are dead. */
7423 if (set
!= 0 && SET_DEST (set
) == reg
)
7425 if (GET_CODE (i2
) == CODE_LABEL
7426 || GET_CODE (i2
) == JUMP_INSN
)
7428 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
7429 && reg_mentioned_p (reg
, PATTERN (i2
)))
7431 /* Some other ref remains; just delete the output reload we
7433 delete_address_reloads (output_reload_insn
, insn
);
7434 PUT_CODE (output_reload_insn
, NOTE
);
7435 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7436 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7441 /* Delete the now-dead stores into this pseudo. */
7442 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7444 rtx set
= single_set (i2
);
7446 if (set
!= 0 && SET_DEST (set
) == reg
)
7448 delete_address_reloads (i2
, insn
);
7449 /* This might be a basic block head,
7450 thus don't use delete_insn. */
7451 PUT_CODE (i2
, NOTE
);
7452 NOTE_SOURCE_FILE (i2
) = 0;
7453 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
7455 if (GET_CODE (i2
) == CODE_LABEL
7456 || GET_CODE (i2
) == JUMP_INSN
)
7460 /* For the debugging info,
7461 say the pseudo lives in this reload reg. */
7462 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
7463 alter_reg (REGNO (reg
), -1);
7465 delete_address_reloads (output_reload_insn
, insn
);
7466 PUT_CODE (output_reload_insn
, NOTE
);
7467 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7468 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7472 /* We are going to delete DEAD_INSN. Recursively delete loads of
7473 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7474 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7476 delete_address_reloads (dead_insn
, current_insn
)
7477 rtx dead_insn
, current_insn
;
7479 rtx set
= single_set (dead_insn
);
7480 rtx set2
, dst
, prev
, next
;
7483 rtx dst
= SET_DEST (set
);
7484 if (GET_CODE (dst
) == MEM
)
7485 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7487 /* If we deleted the store from a reloaded post_{in,de}c expression,
7488 we can delete the matching adds. */
7489 prev
= PREV_INSN (dead_insn
);
7490 next
= NEXT_INSN (dead_insn
);
7491 if (! prev
|| ! next
)
7493 set
= single_set (next
);
7494 set2
= single_set (prev
);
7496 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7497 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7498 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7500 dst
= SET_DEST (set
);
7501 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7502 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7503 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7504 || (INTVAL (XEXP (SET_SRC (set
), 1))
7505 != - INTVAL (XEXP (SET_SRC (set2
), 1))))
7511 /* Subfunction of delete_address_reloads: process registers found in X. */
7513 delete_address_reloads_1 (dead_insn
, x
, current_insn
)
7514 rtx dead_insn
, x
, current_insn
;
7516 rtx prev
, set
, dst
, i2
;
7518 enum rtx_code code
= GET_CODE (x
);
7522 const char *fmt
= GET_RTX_FORMAT (code
);
7523 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7526 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
7527 else if (fmt
[i
] == 'E')
7529 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
7530 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
7537 if (spill_reg_order
[REGNO (x
)] < 0)
7540 /* Scan backwards for the insn that sets x. This might be a way back due
7542 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
7544 code
= GET_CODE (prev
);
7545 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
7547 if (GET_RTX_CLASS (code
) != 'i')
7549 if (reg_set_p (x
, PATTERN (prev
)))
7551 if (reg_referenced_p (x
, PATTERN (prev
)))
7554 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
7556 /* Check that PREV only sets the reload register. */
7557 set
= single_set (prev
);
7560 dst
= SET_DEST (set
);
7561 if (GET_CODE (dst
) != REG
7562 || ! rtx_equal_p (dst
, x
))
7564 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
7566 /* Check if DST was used in a later insn -
7567 it might have been inherited. */
7568 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
7570 if (GET_CODE (i2
) == CODE_LABEL
)
7572 if (GET_RTX_CLASS (GET_CODE (i2
)) != 'i')
7574 if (reg_referenced_p (dst
, PATTERN (i2
)))
7576 /* If there is a reference to the register in the current insn,
7577 it might be loaded in a non-inherited reload. If no other
7578 reload uses it, that means the register is set before
7580 if (i2
== current_insn
)
7582 for (j
= n_reloads
- 1; j
>= 0; j
--)
7583 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7584 || reload_override_in
[j
] == dst
)
7586 for (j
= n_reloads
- 1; j
>= 0; j
--)
7587 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
7594 if (GET_CODE (i2
) == JUMP_INSN
)
7596 /* If DST is still live at CURRENT_INSN, check if it is used for
7597 any reload. Note that even if CURRENT_INSN sets DST, we still
7598 have to check the reloads. */
7599 if (i2
== current_insn
)
7601 for (j
= n_reloads
- 1; j
>= 0; j
--)
7602 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7603 || reload_override_in
[j
] == dst
)
7605 /* ??? We can't finish the loop here, because dst might be
7606 allocated to a pseudo in this block if no reload in this
7607 block needs any of the clsses containing DST - see
7608 spill_hard_reg. There is no easy way to tell this, so we
7609 have to scan till the end of the basic block. */
7611 if (reg_set_p (dst
, PATTERN (i2
)))
7615 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
7616 reg_reloaded_contents
[REGNO (dst
)] = -1;
7617 /* Can't use delete_insn here because PREV might be a basic block head. */
7618 PUT_CODE (prev
, NOTE
);
7619 NOTE_LINE_NUMBER (prev
) = NOTE_INSN_DELETED
;
7620 NOTE_SOURCE_FILE (prev
) = 0;
7623 /* Output reload-insns to reload VALUE into RELOADREG.
7624 VALUE is an autoincrement or autodecrement RTX whose operand
7625 is a register or memory location;
7626 so reloading involves incrementing that location.
7627 IN is either identical to VALUE, or some cheaper place to reload from.
7629 INC_AMOUNT is the number to increment or decrement by (always positive).
7630 This cannot be deduced from VALUE.
7632 Return the instruction that stores into RELOADREG. */
7635 inc_for_reload (reloadreg
, in
, value
, inc_amount
)
7640 /* REG or MEM to be copied and incremented. */
7641 rtx incloc
= XEXP (value
, 0);
7642 /* Nonzero if increment after copying. */
7643 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
7649 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
7651 /* No hard register is equivalent to this register after
7652 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7653 we could inc/dec that register as well (maybe even using it for
7654 the source), but I'm not sure it's worth worrying about. */
7655 if (GET_CODE (incloc
) == REG
)
7656 reg_last_reload_reg
[REGNO (incloc
)] = 0;
7658 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
7659 inc_amount
= - inc_amount
;
7661 inc
= GEN_INT (inc_amount
);
7663 /* If this is post-increment, first copy the location to the reload reg. */
7664 if (post
&& real_in
!= reloadreg
)
7665 emit_insn (gen_move_insn (reloadreg
, real_in
));
7669 /* See if we can directly increment INCLOC. Use a method similar to
7670 that in gen_reload. */
7672 last
= get_last_insn ();
7673 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
7674 gen_rtx_PLUS (GET_MODE (incloc
),
7677 code
= recog_memoized (add_insn
);
7680 extract_insn (add_insn
);
7681 if (constrain_operands (1))
7683 /* If this is a pre-increment and we have incremented the value
7684 where it lives, copy the incremented value to RELOADREG to
7685 be used as an address. */
7688 emit_insn (gen_move_insn (reloadreg
, incloc
));
7693 delete_insns_since (last
);
7696 /* If couldn't do the increment directly, must increment in RELOADREG.
7697 The way we do this depends on whether this is pre- or post-increment.
7698 For pre-increment, copy INCLOC to the reload register, increment it
7699 there, then save back. */
7703 if (in
!= reloadreg
)
7704 emit_insn (gen_move_insn (reloadreg
, real_in
));
7705 emit_insn (gen_add2_insn (reloadreg
, inc
));
7706 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7711 Because this might be a jump insn or a compare, and because RELOADREG
7712 may not be available after the insn in an input reload, we must do
7713 the incrementation before the insn being reloaded for.
7715 We have already copied IN to RELOADREG. Increment the copy in
7716 RELOADREG, save that back, then decrement RELOADREG so it has
7717 the original value. */
7719 emit_insn (gen_add2_insn (reloadreg
, inc
));
7720 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7721 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
7727 /* Return 1 if we are certain that the constraint-string STRING allows
7728 the hard register REG. Return 0 if we can't be sure of this. */
7731 constraint_accepts_reg_p (string
, reg
)
7736 int regno
= true_regnum (reg
);
7739 /* Initialize for first alternative. */
7741 /* Check that each alternative contains `g' or `r'. */
7743 switch (c
= *string
++)
7746 /* If an alternative lacks `g' or `r', we lose. */
7749 /* If an alternative lacks `g' or `r', we lose. */
7752 /* Initialize for next alternative. */
7757 /* Any general reg wins for this alternative. */
7758 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
7762 /* Any reg in specified class wins for this alternative. */
7764 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
7766 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
7772 /* Return the number of places FIND appears within X, but don't count
7773 an occurrence if some SET_DEST is FIND. */
7776 count_occurrences (x
, find
)
7777 register rtx x
, find
;
7780 register enum rtx_code code
;
7781 register const char *format_ptr
;
7789 code
= GET_CODE (x
);
7804 if (GET_CODE (find
) == MEM
&& rtx_equal_p (x
, find
))
7808 if (SET_DEST (x
) == find
)
7809 return count_occurrences (SET_SRC (x
), find
);
7816 format_ptr
= GET_RTX_FORMAT (code
);
7819 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7821 switch (*format_ptr
++)
7824 count
+= count_occurrences (XEXP (x
, i
), find
);
7828 if (XVEC (x
, i
) != NULL
)
7830 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7831 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
);
7839 /* INSN is a no-op; delete it.
7840 If this sets the return value of the function, we must keep a USE around,
7841 in case this is in a different basic block than the final USE. Otherwise,
7842 we could loose important register lifeness information on
7843 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7844 spills: subsequent passes assume that spill registers are dead at the end
7846 VALUE must be the return value in such a case, NULL otherwise. */
7848 reload_cse_delete_noop_set (insn
, value
)
7853 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, value
);
7854 INSN_CODE (insn
) = -1;
7855 REG_NOTES (insn
) = NULL_RTX
;
7859 PUT_CODE (insn
, NOTE
);
7860 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
7861 NOTE_SOURCE_FILE (insn
) = 0;
7865 /* See whether a single set SET is a noop. */
7867 reload_cse_noop_set_p (set
)
7870 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
7873 /* Try to simplify INSN. */
7875 reload_cse_simplify (insn
)
7878 rtx body
= PATTERN (insn
);
7880 if (GET_CODE (body
) == SET
)
7883 if (reload_cse_noop_set_p (body
))
7885 rtx value
= SET_DEST (body
);
7886 if (! REG_FUNCTION_VALUE_P (SET_DEST (body
)))
7888 reload_cse_delete_noop_set (insn
, value
);
7892 /* It's not a no-op, but we can try to simplify it. */
7893 count
+= reload_cse_simplify_set (body
, insn
);
7896 apply_change_group ();
7898 reload_cse_simplify_operands (insn
);
7900 else if (GET_CODE (body
) == PARALLEL
)
7904 rtx value
= NULL_RTX
;
7906 /* If every action in a PARALLEL is a noop, we can delete
7907 the entire PARALLEL. */
7908 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
7910 rtx part
= XVECEXP (body
, 0, i
);
7911 if (GET_CODE (part
) == SET
)
7913 if (! reload_cse_noop_set_p (part
))
7915 if (REG_FUNCTION_VALUE_P (SET_DEST (part
)))
7919 value
= SET_DEST (part
);
7922 else if (GET_CODE (part
) != CLOBBER
)
7928 reload_cse_delete_noop_set (insn
, value
);
7929 /* We're done with this insn. */
7933 /* It's not a no-op, but we can try to simplify it. */
7934 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
7935 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
7936 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
7939 apply_change_group ();
7941 reload_cse_simplify_operands (insn
);
7945 /* Do a very simple CSE pass over the hard registers.
7947 This function detects no-op moves where we happened to assign two
7948 different pseudo-registers to the same hard register, and then
7949 copied one to the other. Reload will generate a useless
7950 instruction copying a register to itself.
7952 This function also detects cases where we load a value from memory
7953 into two different registers, and (if memory is more expensive than
7954 registers) changes it to simply copy the first register into the
7957 Another optimization is performed that scans the operands of each
7958 instruction to see whether the value is already available in a
7959 hard register. It then replaces the operand with the hard register
7960 if possible, much like an optional reload would. */
7963 reload_cse_regs_1 (first
)
7969 init_alias_analysis ();
7971 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
7973 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
7974 reload_cse_simplify (insn
);
7976 cselib_process_insn (insn
);
7980 end_alias_analysis ();
7984 /* Call cse / combine like post-reload optimization phases.
7985 FIRST is the first instruction. */
7987 reload_cse_regs (first
)
7990 reload_cse_regs_1 (first
);
7992 reload_cse_move2add (first
);
7993 if (flag_expensive_optimizations
)
7994 reload_cse_regs_1 (first
);
7997 /* Try to simplify a single SET instruction. SET is the set pattern.
7998 INSN is the instruction it came from.
7999 This function only handles one case: if we set a register to a value
8000 which is not a register, we try to find that value in some other register
8001 and change the set into a register copy. */
8004 reload_cse_simplify_set (set
, insn
)
8011 enum reg_class dclass
;
8014 struct elt_loc_list
*l
;
8016 dreg
= true_regnum (SET_DEST (set
));
8020 src
= SET_SRC (set
);
8021 if (side_effects_p (src
) || true_regnum (src
) >= 0)
8024 dclass
= REGNO_REG_CLASS (dreg
);
8026 /* If memory loads are cheaper than register copies, don't change them. */
8027 if (GET_CODE (src
) == MEM
)
8028 old_cost
= MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1);
8029 else if (CONSTANT_P (src
))
8030 old_cost
= rtx_cost (src
, SET
);
8031 else if (GET_CODE (src
) == REG
)
8032 old_cost
= REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src
)), dclass
);
8035 old_cost
= rtx_cost (src
, SET
);
8037 val
= cselib_lookup (src
, VOIDmode
, 0);
8040 for (l
= val
->locs
; l
; l
= l
->next
)
8043 if (CONSTANT_P (l
->loc
) && ! references_value_p (l
->loc
, 0))
8044 this_cost
= rtx_cost (l
->loc
, SET
);
8045 else if (GET_CODE (l
->loc
) == REG
)
8046 this_cost
= REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l
->loc
)),
8050 /* If equal costs, prefer registers over anything else. That tends to
8051 lead to smaller instructions on some machines. */
8052 if ((this_cost
< old_cost
8053 || (this_cost
== old_cost
8054 && GET_CODE (l
->loc
) == REG
8055 && GET_CODE (SET_SRC (set
)) != REG
))
8056 && validate_change (insn
, &SET_SRC (set
), copy_rtx (l
->loc
), 1))
8057 old_cost
= this_cost
, did_change
= 1;
8063 /* Try to replace operands in INSN with equivalent values that are already
8064 in registers. This can be viewed as optional reloading.
8066 For each non-register operand in the insn, see if any hard regs are
8067 known to be equivalent to that operand. Record the alternatives which
8068 can accept these hard registers. Among all alternatives, select the
8069 ones which are better or equal to the one currently matching, where
8070 "better" is in terms of '?' and '!' constraints. Among the remaining
8071 alternatives, select the one which replaces most operands with
8075 reload_cse_simplify_operands (insn
)
8080 /* For each operand, all registers that are equivalent to it. */
8081 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
8083 const char *constraints
[MAX_RECOG_OPERANDS
];
8085 /* Vector recording how bad an alternative is. */
8086 int *alternative_reject
;
8087 /* Vector recording how many registers can be introduced by choosing
8088 this alternative. */
8089 int *alternative_nregs
;
8090 /* Array of vectors recording, for each operand and each alternative,
8091 which hard register to substitute, or -1 if the operand should be
8093 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
8094 /* Array of alternatives, sorted in order of decreasing desirability. */
8095 int *alternative_order
;
8096 rtx reg
= gen_rtx_REG (VOIDmode
, -1);
8098 extract_insn (insn
);
8100 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
8103 /* Figure out which alternative currently matches. */
8104 if (! constrain_operands (1))
8105 fatal_insn_not_found (insn
);
8107 alternative_reject
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8108 alternative_nregs
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8109 alternative_order
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8110 bzero ((char *)alternative_reject
, recog_data
.n_alternatives
* sizeof (int));
8111 bzero ((char *)alternative_nregs
, recog_data
.n_alternatives
* sizeof (int));
8113 /* For each operand, find out which regs are equivalent. */
8114 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8117 struct elt_loc_list
*l
;
8119 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
8121 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8122 right, so avoid the problem here. */
8123 if (GET_CODE (recog_data
.operand
[i
]) == CODE_LABEL
)
8126 v
= cselib_lookup (recog_data
.operand
[i
], recog_data
.operand_mode
[i
], 0);
8130 for (l
= v
->locs
; l
; l
= l
->next
)
8131 if (GET_CODE (l
->loc
) == REG
)
8132 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
8135 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8137 enum machine_mode mode
;
8141 op_alt_regno
[i
] = (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8142 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
8143 op_alt_regno
[i
][j
] = -1;
8145 p
= constraints
[i
] = recog_data
.constraints
[i
];
8146 mode
= recog_data
.operand_mode
[i
];
8148 /* Add the reject values for each alternative given by the constraints
8149 for this operand. */
8157 alternative_reject
[j
] += 3;
8159 alternative_reject
[j
] += 300;
8162 /* We won't change operands which are already registers. We
8163 also don't want to modify output operands. */
8164 regno
= true_regnum (recog_data
.operand
[i
]);
8166 || constraints
[i
][0] == '='
8167 || constraints
[i
][0] == '+')
8170 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
8172 int class = (int) NO_REGS
;
8174 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
8177 REGNO (reg
) = regno
;
8178 PUT_MODE (reg
, mode
);
8180 /* We found a register equal to this operand. Now look for all
8181 alternatives that can accept this register and have not been
8182 assigned a register they can use yet. */
8191 case '=': case '+': case '?':
8192 case '#': case '&': case '!':
8194 case '0': case '1': case '2': case '3': case '4':
8195 case '5': case '6': case '7': case '8': case '9':
8196 case 'm': case '<': case '>': case 'V': case 'o':
8197 case 'E': case 'F': case 'G': case 'H':
8198 case 's': case 'i': case 'n':
8199 case 'I': case 'J': case 'K': case 'L':
8200 case 'M': case 'N': case 'O': case 'P':
8201 #ifdef EXTRA_CONSTRAINT
8202 case 'Q': case 'R': case 'S': case 'T': case 'U':
8205 /* These don't say anything we care about. */
8209 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
8214 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
8217 case ',': case '\0':
8218 /* See if REGNO fits this alternative, and set it up as the
8219 replacement register if we don't have one for this
8220 alternative yet and the operand being replaced is not
8221 a cheap CONST_INT. */
8222 if (op_alt_regno
[i
][j
] == -1
8223 && reg_fits_class_p (reg
, class, 0, mode
)
8224 && (GET_CODE (recog_data
.operand
[i
]) != CONST_INT
8225 || (rtx_cost (recog_data
.operand
[i
], SET
)
8226 > rtx_cost (reg
, SET
))))
8228 alternative_nregs
[j
]++;
8229 op_alt_regno
[i
][j
] = regno
;
8241 /* Record all alternatives which are better or equal to the currently
8242 matching one in the alternative_order array. */
8243 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
8244 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
8245 alternative_order
[j
++] = i
;
8246 recog_data
.n_alternatives
= j
;
8248 /* Sort it. Given a small number of alternatives, a dumb algorithm
8249 won't hurt too much. */
8250 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
8253 int best_reject
= alternative_reject
[alternative_order
[i
]];
8254 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
8257 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
8259 int this_reject
= alternative_reject
[alternative_order
[j
]];
8260 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
8262 if (this_reject
< best_reject
8263 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
8266 best_reject
= this_reject
;
8267 best_nregs
= this_nregs
;
8271 tmp
= alternative_order
[best
];
8272 alternative_order
[best
] = alternative_order
[i
];
8273 alternative_order
[i
] = tmp
;
8276 /* Substitute the operands as determined by op_alt_regno for the best
8278 j
= alternative_order
[0];
8280 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8282 enum machine_mode mode
= recog_data
.operand_mode
[i
];
8283 if (op_alt_regno
[i
][j
] == -1)
8286 validate_change (insn
, recog_data
.operand_loc
[i
],
8287 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
8290 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
8292 int op
= recog_data
.dup_num
[i
];
8293 enum machine_mode mode
= recog_data
.operand_mode
[op
];
8295 if (op_alt_regno
[op
][j
] == -1)
8298 validate_change (insn
, recog_data
.dup_loc
[i
],
8299 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
8302 return apply_change_group ();
8305 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8307 This code might also be useful when reload gave up on reg+reg addresssing
8308 because of clashes between the return register and INDEX_REG_CLASS. */
8310 /* The maximum number of uses of a register we can keep track of to
8311 replace them with reg+reg addressing. */
8312 #define RELOAD_COMBINE_MAX_USES 6
8314 /* INSN is the insn where a register has ben used, and USEP points to the
8315 location of the register within the rtl. */
8316 struct reg_use
{ rtx insn
, *usep
; };
8318 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8319 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8320 indicates where it becomes live again.
8321 Otherwise, USE_INDEX is the index of the last encountered use of the
8322 register (which is first among these we have seen since we scan backwards),
8323 OFFSET contains the constant offset that is added to the register in
8324 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8325 last, of these uses.
8326 STORE_RUID is always meaningful if we only want to use a value in a
8327 register in a different place: it denotes the next insn in the insn
8328 stream (i.e. the last ecountered) that sets or clobbers the register. */
8331 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
8336 } reg_state
[FIRST_PSEUDO_REGISTER
];
8338 /* Reverse linear uid. This is increased in reload_combine while scanning
8339 the instructions from last to first. It is used to set last_label_ruid
8340 and the store_ruid / use_ruid fields in reg_state. */
8341 static int reload_combine_ruid
;
8343 #define LABEL_LIVE(LABEL) \
8344 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8350 int first_index_reg
= 1, last_index_reg
= 0;
8352 int last_label_ruid
;
8353 int min_labelno
, n_labels
;
8354 HARD_REG_SET ever_live_at_start
, *label_live
;
8356 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8357 reload has already used it where appropriate, so there is no use in
8358 trying to generate it now. */
8359 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
8362 /* To avoid wasting too much time later searching for an index register,
8363 determine the minimum and maximum index register numbers. */
8364 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
8366 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
))
8368 if (! last_index_reg
)
8370 first_index_reg
= i
;
8373 /* If no index register is available, we can quit now. */
8374 if (first_index_reg
> last_index_reg
)
8377 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8378 information is a bit fuzzy immediately after reload, but it's
8379 still good enough to determine which registers are live at a jump
8381 min_labelno
= get_first_label_num ();
8382 n_labels
= max_label_num () - min_labelno
;
8383 label_live
= (HARD_REG_SET
*) xmalloc (n_labels
* sizeof (HARD_REG_SET
));
8384 CLEAR_HARD_REG_SET (ever_live_at_start
);
8385 for (i
= n_basic_blocks
- 1; i
>= 0; i
--)
8387 insn
= BLOCK_HEAD (i
);
8388 if (GET_CODE (insn
) == CODE_LABEL
)
8392 REG_SET_TO_HARD_REG_SET (live
, BASIC_BLOCK (i
)->global_live_at_start
);
8393 compute_use_by_pseudos (&live
, BASIC_BLOCK (i
)->global_live_at_start
);
8394 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
8395 IOR_HARD_REG_SET (ever_live_at_start
, live
);
8399 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8400 last_label_ruid
= reload_combine_ruid
= 0;
8401 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
8403 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8405 reg_state
[i
].use_index
= -1;
8407 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8410 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
8414 /* We cannot do our optimization across labels. Invalidating all the use
8415 information we have would be costly, so we just note where the label
8416 is and then later disable any optimization that would cross it. */
8417 if (GET_CODE (insn
) == CODE_LABEL
)
8418 last_label_ruid
= reload_combine_ruid
;
8419 if (GET_CODE (insn
) == BARRIER
)
8421 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
8422 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8424 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8426 reload_combine_ruid
++;
8428 /* Look for (set (REGX) (CONST_INT))
8429 (set (REGX) (PLUS (REGX) (REGY)))
8431 ... (MEM (REGX)) ...
8433 (set (REGZ) (CONST_INT))
8435 ... (MEM (PLUS (REGZ) (REGY)))... .
8437 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8438 and that we know all uses of REGX before it dies. */
8439 set
= single_set (insn
);
8441 && GET_CODE (SET_DEST (set
)) == REG
8442 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
8443 GET_MODE (SET_DEST (set
)))
8445 && GET_CODE (SET_SRC (set
)) == PLUS
8446 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
8447 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
8448 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
8450 rtx reg
= SET_DEST (set
);
8451 rtx plus
= SET_SRC (set
);
8452 rtx base
= XEXP (plus
, 1);
8453 rtx prev
= prev_nonnote_insn (insn
);
8454 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
8455 int regno
= REGNO (reg
);
8456 rtx const_reg
= NULL_RTX
;
8457 rtx reg_sum
= NULL_RTX
;
8459 /* Now, we need an index register.
8460 We'll set index_reg to this index register, const_reg to the
8461 register that is to be loaded with the constant
8462 (denoted as REGZ in the substitution illustration above),
8463 and reg_sum to the register-register that we want to use to
8464 substitute uses of REG (typically in MEMs) with.
8465 First check REG and BASE for being index registers;
8466 we can use them even if they are not dead. */
8467 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
8468 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
8476 /* Otherwise, look for a free index register. Since we have
8477 checked above that neiter REG nor BASE are index registers,
8478 if we find anything at all, it will be different from these
8480 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
8482 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
8483 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
8484 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
8485 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
8487 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
8488 const_reg
= index_reg
;
8489 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
8494 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8495 (REGY), i.e. BASE, is not clobbered before the last use we'll
8498 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
8499 && rtx_equal_p (SET_DEST (prev_set
), reg
)
8500 && reg_state
[regno
].use_index
>= 0
8501 && reg_state
[REGNO (base
)].store_ruid
<= reg_state
[regno
].use_ruid
8506 /* Change destination register and - if necessary - the
8507 constant value in PREV, the constant loading instruction. */
8508 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
8509 if (reg_state
[regno
].offset
!= const0_rtx
)
8510 validate_change (prev
,
8511 &SET_SRC (prev_set
),
8512 GEN_INT (INTVAL (SET_SRC (prev_set
))
8513 + INTVAL (reg_state
[regno
].offset
)),
8515 /* Now for every use of REG that we have recorded, replace REG
8517 for (i
= reg_state
[regno
].use_index
;
8518 i
< RELOAD_COMBINE_MAX_USES
; i
++)
8519 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
8520 reg_state
[regno
].reg_use
[i
].usep
,
8523 if (apply_change_group ())
8527 /* Delete the reg-reg addition. */
8528 PUT_CODE (insn
, NOTE
);
8529 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8530 NOTE_SOURCE_FILE (insn
) = 0;
8532 if (reg_state
[regno
].offset
!= const0_rtx
)
8534 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8536 for (np
= ®_NOTES (prev
); *np
; )
8538 if (REG_NOTE_KIND (*np
) == REG_EQUAL
8539 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
8540 *np
= XEXP (*np
, 1);
8542 np
= &XEXP (*np
, 1);
8545 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
8546 reg_state
[REGNO (const_reg
)].store_ruid
= reload_combine_ruid
;
8551 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
8552 if (GET_CODE (insn
) == CALL_INSN
)
8556 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
8558 if (call_used_regs
[i
])
8560 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8561 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8564 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
8565 link
= XEXP (link
, 1))
8567 rtx use
= XEXP (link
, 0);
8568 int regno
= REGNO (XEXP (use
, 0));
8569 if (GET_CODE (use
) == CLOBBER
)
8571 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
8572 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
8575 reg_state
[regno
].use_index
= -1;
8578 if (GET_CODE (insn
) == JUMP_INSN
&& GET_CODE (PATTERN (insn
)) != RETURN
)
8580 /* Non-spill registers might be used at the call destination in
8581 some unknown fashion, so we have to mark the unknown use. */
8583 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
8584 && JUMP_LABEL (insn
))
8585 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
8587 live
= &ever_live_at_start
;
8588 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
8590 if (TEST_HARD_REG_BIT (*live
, i
))
8591 reg_state
[i
].use_index
= -1;
8594 reload_combine_note_use (&PATTERN (insn
), insn
);
8595 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
8597 if (REG_NOTE_KIND (note
) == REG_INC
8598 && GET_CODE (XEXP (note
, 0)) == REG
)
8600 int regno
= REGNO (XEXP (note
, 0));
8602 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
8603 reg_state
[regno
].use_index
= -1;
8610 /* Check if DST is a register or a subreg of a register; if it is,
8611 update reg_state[regno].store_ruid and reg_state[regno].use_index
8612 accordingly. Called via note_stores from reload_combine. */
8614 reload_combine_note_store (dst
, set
, data
)
8616 void *data ATTRIBUTE_UNUSED
;
8620 enum machine_mode mode
= GET_MODE (dst
);
8622 if (GET_CODE (dst
) == SUBREG
)
8624 regno
= SUBREG_WORD (dst
);
8625 dst
= SUBREG_REG (dst
);
8627 if (GET_CODE (dst
) != REG
)
8629 regno
+= REGNO (dst
);
8631 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8632 careful with registers / register parts that are not full words.
8634 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8635 if (GET_CODE (set
) != SET
8636 || GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
8637 || GET_CODE (SET_DEST (set
)) == SIGN_EXTRACT
8638 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
8640 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8642 reg_state
[i
].use_index
= -1;
8643 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8648 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8650 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8651 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8656 /* XP points to a piece of rtl that has to be checked for any uses of
8658 *XP is the pattern of INSN, or a part of it.
8659 Called from reload_combine, and recursively by itself. */
8661 reload_combine_note_use (xp
, insn
)
8665 enum rtx_code code
= x
->code
;
8668 rtx offset
= const0_rtx
; /* For the REG case below. */
8673 if (GET_CODE (SET_DEST (x
)) == REG
)
8675 reload_combine_note_use (&SET_SRC (x
), insn
);
8681 /* If this is the USE of a return value, we can't change it. */
8682 if (GET_CODE (XEXP (x
, 0)) == REG
&& REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
8684 /* Mark the return register as used in an unknown fashion. */
8685 rtx reg
= XEXP (x
, 0);
8686 int regno
= REGNO (reg
);
8687 int nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8689 while (--nregs
>= 0)
8690 reg_state
[regno
+ nregs
].use_index
= -1;
8696 if (GET_CODE (SET_DEST (x
)) == REG
)
8701 /* We are interested in (plus (reg) (const_int)) . */
8702 if (GET_CODE (XEXP (x
, 0)) != REG
|| GET_CODE (XEXP (x
, 1)) != CONST_INT
)
8704 offset
= XEXP (x
, 1);
8709 int regno
= REGNO (x
);
8713 /* Some spurious USEs of pseudo registers might remain.
8714 Just ignore them. */
8715 if (regno
>= FIRST_PSEUDO_REGISTER
)
8718 nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8720 /* We can't substitute into multi-hard-reg uses. */
8723 while (--nregs
>= 0)
8724 reg_state
[regno
+ nregs
].use_index
= -1;
8728 /* If this register is already used in some unknown fashion, we
8730 If we decrement the index from zero to -1, we can't store more
8731 uses, so this register becomes used in an unknown fashion. */
8732 use_index
= --reg_state
[regno
].use_index
;
8736 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
8738 /* We have found another use for a register that is already
8739 used later. Check if the offsets match; if not, mark the
8740 register as used in an unknown fashion. */
8741 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
8743 reg_state
[regno
].use_index
= -1;
8749 /* This is the first use of this register we have seen since we
8750 marked it as dead. */
8751 reg_state
[regno
].offset
= offset
;
8752 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
8754 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
8755 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
8763 /* Recursively process the components of X. */
8764 fmt
= GET_RTX_FORMAT (code
);
8765 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8768 reload_combine_note_use (&XEXP (x
, i
), insn
);
8769 else if (fmt
[i
] == 'E')
8771 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8772 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
8777 /* See if we can reduce the cost of a constant by replacing a move with
8779 /* We cannot do our optimization across labels. Invalidating all the
8780 information about register contents we have would be costly, so we
8781 use last_label_luid (local variable of reload_cse_move2add) to note
8782 where the label is and then later disable any optimization that would
8784 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8785 reg_set_luid[n] is larger than last_label_luid[n] . */
8786 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
8787 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8788 reg_mode[n] to be valid.
8789 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8790 has been set to reg_offset[n] in mode reg_mode[n] .
8791 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8792 register n has been set to the sum of reg_offset[n] and register
8793 reg_base_reg[n], calculated in mode reg_mode[n] . */
8794 static rtx reg_offset
[FIRST_PSEUDO_REGISTER
];
8795 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
8796 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
8797 /* move2add_luid is linearily increased while scanning the instructions
8798 from first to last. It is used to set reg_set_luid in
8799 reload_cse_move2add and move2add_note_store. */
8800 static int move2add_luid
;
8802 /* Generate a CONST_INT and force it in the range of MODE. */
8804 gen_mode_int (mode
, value
)
8805 enum machine_mode mode
;
8806 HOST_WIDE_INT value
;
8808 HOST_WIDE_INT cval
= value
& GET_MODE_MASK (mode
);
8809 int width
= GET_MODE_BITSIZE (mode
);
8811 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8813 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8814 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8815 cval
|= (HOST_WIDE_INT
) -1 << width
;
8817 return GEN_INT (cval
);
8821 reload_cse_move2add (first
)
8826 int last_label_luid
;
8828 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
8829 reg_set_luid
[i
] = 0;
8831 last_label_luid
= 0;
8833 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
8837 if (GET_CODE (insn
) == CODE_LABEL
)
8838 last_label_luid
= move2add_luid
;
8839 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8841 pat
= PATTERN (insn
);
8842 /* For simplicity, we only perform this optimization on
8843 straightforward SETs. */
8844 if (GET_CODE (pat
) == SET
8845 && GET_CODE (SET_DEST (pat
)) == REG
)
8847 rtx reg
= SET_DEST (pat
);
8848 int regno
= REGNO (reg
);
8849 rtx src
= SET_SRC (pat
);
8851 /* Check if we have valid information on the contents of this
8852 register in the mode of REG. */
8853 /* ??? We don't know how zero / sign extension is handled, hence
8854 we can't go from a narrower to a wider mode. */
8855 if (reg_set_luid
[regno
] > last_label_luid
8856 && (GET_MODE_SIZE (GET_MODE (reg
))
8857 <= GET_MODE_SIZE (reg_mode
[regno
]))
8858 && GET_CODE (reg_offset
[regno
]) == CONST_INT
)
8860 /* Try to transform (set (REGX) (CONST_INT A))
8862 (set (REGX) (CONST_INT B))
8864 (set (REGX) (CONST_INT A))
8866 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8868 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
8872 = gen_mode_int (GET_MODE (reg
),
8873 INTVAL (src
) - INTVAL (reg_offset
[regno
]));
8874 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8875 use (set (reg) (reg)) instead.
8876 We don't delete this insn, nor do we convert it into a
8877 note, to avoid losing register notes or the return
8878 value flag. jump2 already knowns how to get rid of
8880 if (new_src
== const0_rtx
)
8881 success
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
8882 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
8883 && have_add2_insn (GET_MODE (reg
)))
8884 success
= validate_change (insn
, &PATTERN (insn
),
8885 gen_add2_insn (reg
, new_src
), 0);
8886 reg_set_luid
[regno
] = move2add_luid
;
8887 reg_mode
[regno
] = GET_MODE (reg
);
8888 reg_offset
[regno
] = src
;
8892 /* Try to transform (set (REGX) (REGY))
8893 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8896 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8899 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8901 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8902 else if (GET_CODE (src
) == REG
8903 && reg_base_reg
[regno
] == REGNO (src
)
8904 && reg_set_luid
[regno
] > reg_set_luid
[REGNO (src
)])
8906 rtx next
= next_nonnote_insn (insn
);
8909 set
= single_set (next
);
8912 && SET_DEST (set
) == reg
8913 && GET_CODE (SET_SRC (set
)) == PLUS
8914 && XEXP (SET_SRC (set
), 0) == reg
8915 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
8917 rtx src3
= XEXP (SET_SRC (set
), 1);
8919 = gen_mode_int (GET_MODE (reg
),
8921 - INTVAL (reg_offset
[regno
]));
8924 if (new_src
== const0_rtx
)
8925 /* See above why we create (set (reg) (reg)) here. */
8927 = validate_change (next
, &SET_SRC (set
), reg
, 0);
8928 else if ((rtx_cost (new_src
, PLUS
)
8929 < 2 + rtx_cost (src3
, SET
))
8930 && have_add2_insn (GET_MODE (reg
)))
8932 = validate_change (next
, &PATTERN (next
),
8933 gen_add2_insn (reg
, new_src
), 0);
8936 /* INSN might be the first insn in a basic block
8937 if the preceding insn is a conditional jump
8938 or a possible-throwing call. */
8939 PUT_CODE (insn
, NOTE
);
8940 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8941 NOTE_SOURCE_FILE (insn
) = 0;
8944 reg_set_luid
[regno
] = move2add_luid
;
8945 reg_mode
[regno
] = GET_MODE (reg
);
8946 reg_offset
[regno
] = src3
;
8953 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
8955 if (REG_NOTE_KIND (note
) == REG_INC
8956 && GET_CODE (XEXP (note
, 0)) == REG
)
8958 /* Indicate that this register has been recently written to,
8959 but the exact contents are not available. */
8960 int regno
= REGNO (XEXP (note
, 0));
8961 if (regno
< FIRST_PSEUDO_REGISTER
)
8963 reg_set_luid
[regno
] = move2add_luid
;
8964 reg_offset
[regno
] = note
;
8968 note_stores (PATTERN (insn
), move2add_note_store
, NULL
);
8969 /* If this is a CALL_INSN, all call used registers are stored with
8971 if (GET_CODE (insn
) == CALL_INSN
)
8973 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
8975 if (call_used_regs
[i
])
8977 reg_set_luid
[i
] = move2add_luid
;
8978 reg_offset
[i
] = insn
; /* Invalidate contents. */
8985 /* SET is a SET or CLOBBER that sets DST.
8986 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
8987 Called from reload_cse_move2add via note_stores. */
8989 move2add_note_store (dst
, set
, data
)
8991 void *data ATTRIBUTE_UNUSED
;
8996 enum machine_mode mode
= GET_MODE (dst
);
8997 if (GET_CODE (dst
) == SUBREG
)
8999 regno
= SUBREG_WORD (dst
);
9000 dst
= SUBREG_REG (dst
);
9002 if (GET_CODE (dst
) != REG
)
9005 regno
+= REGNO (dst
);
9007 if (HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
9008 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
9009 && GET_CODE (SET_DEST (set
)) != SIGN_EXTRACT
9010 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
9012 rtx src
= SET_SRC (set
);
9014 reg_mode
[regno
] = mode
;
9015 switch (GET_CODE (src
))
9019 rtx src0
= XEXP (src
, 0);
9020 if (GET_CODE (src0
) == REG
)
9022 if (REGNO (src0
) != regno
9023 || reg_offset
[regno
] != const0_rtx
)
9025 reg_base_reg
[regno
] = REGNO (src0
);
9026 reg_set_luid
[regno
] = move2add_luid
;
9028 reg_offset
[regno
] = XEXP (src
, 1);
9031 reg_set_luid
[regno
] = move2add_luid
;
9032 reg_offset
[regno
] = set
; /* Invalidate contents. */
9037 reg_base_reg
[regno
] = REGNO (SET_SRC (set
));
9038 reg_offset
[regno
] = const0_rtx
;
9039 reg_set_luid
[regno
] = move2add_luid
;
9043 reg_base_reg
[regno
] = -1;
9044 reg_offset
[regno
] = SET_SRC (set
);
9045 reg_set_luid
[regno
] = move2add_luid
;
9051 for (i
= regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1; i
>= regno
; i
--)
9053 /* Indicate that this register has been recently written to,
9054 but the exact contents are not available. */
9055 reg_set_luid
[i
] = move2add_luid
;
9056 reg_offset
[i
] = dst
;
9063 add_auto_inc_notes (insn
, x
)
9067 enum rtx_code code
= GET_CODE (x
);
9071 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9074 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
9078 /* Scan all the operand sub-expressions. */
9079 fmt
= GET_RTX_FORMAT (code
);
9080 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9083 add_auto_inc_notes (insn
, XEXP (x
, i
));
9084 else if (fmt
[i
] == 'E')
9085 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9086 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));