| blob | b2855721a6f61671b82f3f63522ce8ba3420f5de |
1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
30 #include <signal.h>
62 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
70 XVECEXP (X, 0, 0)
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
91 part of the frame. */
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
110 : (INSN))
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
116 : (INSN))
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
130 ADDRESS_REG
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
134 ADDRESS_LO_SUM
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
138 ADDRESS_CONST_INT
139 A signed 16-bit constant address.
141 ADDRESS_SYMBOLIC:
142 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
144 ADDRESS_REG,
145 ADDRESS_LO_SUM,
146 ADDRESS_CONST_INT,
147 ADDRESS_SYMBOLIC
148 };
150 /* Classifies the prototype of a builtin function. */
151 enum mips_function_type
152 {
153 MIPS_V2SF_FTYPE_V2SF,
154 MIPS_V2SF_FTYPE_V2SF_V2SF,
155 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
156 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
157 MIPS_V2SF_FTYPE_SF_SF,
158 MIPS_INT_FTYPE_V2SF_V2SF,
159 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
160 MIPS_INT_FTYPE_SF_SF,
161 MIPS_INT_FTYPE_DF_DF,
162 MIPS_SF_FTYPE_V2SF,
163 MIPS_SF_FTYPE_SF,
164 MIPS_SF_FTYPE_SF_SF,
165 MIPS_DF_FTYPE_DF,
166 MIPS_DF_FTYPE_DF_DF,
168 /* For MIPS DSP ASE */
169 MIPS_DI_FTYPE_DI_SI,
170 MIPS_DI_FTYPE_DI_SI_SI,
171 MIPS_DI_FTYPE_DI_V2HI_V2HI,
172 MIPS_DI_FTYPE_DI_V4QI_V4QI,
173 MIPS_SI_FTYPE_DI_SI,
174 MIPS_SI_FTYPE_PTR_SI,
175 MIPS_SI_FTYPE_SI,
176 MIPS_SI_FTYPE_SI_SI,
177 MIPS_SI_FTYPE_V2HI,
178 MIPS_SI_FTYPE_V2HI_V2HI,
179 MIPS_SI_FTYPE_V4QI,
180 MIPS_SI_FTYPE_V4QI_V4QI,
181 MIPS_SI_FTYPE_VOID,
182 MIPS_V2HI_FTYPE_SI,
183 MIPS_V2HI_FTYPE_SI_SI,
184 MIPS_V2HI_FTYPE_V2HI,
185 MIPS_V2HI_FTYPE_V2HI_SI,
186 MIPS_V2HI_FTYPE_V2HI_V2HI,
187 MIPS_V2HI_FTYPE_V4QI,
188 MIPS_V2HI_FTYPE_V4QI_V2HI,
189 MIPS_V4QI_FTYPE_SI,
190 MIPS_V4QI_FTYPE_V2HI_V2HI,
191 MIPS_V4QI_FTYPE_V4QI_SI,
192 MIPS_V4QI_FTYPE_V4QI_V4QI,
193 MIPS_VOID_FTYPE_SI_SI,
194 MIPS_VOID_FTYPE_V2HI_V2HI,
195 MIPS_VOID_FTYPE_V4QI_V4QI,
197 /* For MIPS DSP REV 2 ASE. */
198 MIPS_V4QI_FTYPE_V4QI,
199 MIPS_SI_FTYPE_SI_SI_SI,
200 MIPS_DI_FTYPE_DI_USI_USI,
201 MIPS_DI_FTYPE_SI_SI,
202 MIPS_DI_FTYPE_USI_USI,
203 MIPS_V2HI_FTYPE_SI_SI_SI,
205 /* The last type. */
206 MIPS_MAX_FTYPE_MAX
207 };
209 /* Specifies how a builtin function should be converted into rtl. */
210 enum mips_builtin_type
211 {
212 /* The builtin corresponds directly to an .md pattern. The return
213 value is mapped to operand 0 and the arguments are mapped to
214 operands 1 and above. */
215 MIPS_BUILTIN_DIRECT,
217 /* The builtin corresponds directly to an .md pattern. There is no return
218 value and the arguments are mapped to operands 0 and above. */
219 MIPS_BUILTIN_DIRECT_NO_TARGET,
221 /* The builtin corresponds to a comparison instruction followed by
222 a mips_cond_move_tf_ps pattern. The first two arguments are the
223 values to compare and the second two arguments are the vector
224 operands for the movt.ps or movf.ps instruction (in assembly order). */
225 MIPS_BUILTIN_MOVF,
226 MIPS_BUILTIN_MOVT,
228 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
229 of this instruction is the result of the comparison, which has mode
230 CCV2 or CCV4. The function arguments are mapped to operands 1 and
231 above. The function's return value is an SImode boolean that is
232 true under the following conditions:
234 MIPS_BUILTIN_CMP_ANY: one of the registers is true
235 MIPS_BUILTIN_CMP_ALL: all of the registers are true
236 MIPS_BUILTIN_CMP_LOWER: the first register is true
237 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
238 MIPS_BUILTIN_CMP_ANY,
239 MIPS_BUILTIN_CMP_ALL,
240 MIPS_BUILTIN_CMP_UPPER,
241 MIPS_BUILTIN_CMP_LOWER,
243 /* As above, but the instruction only sets a single $fcc register. */
244 MIPS_BUILTIN_CMP_SINGLE,
246 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
247 MIPS_BUILTIN_BPOSGE32
248 };
250 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
251 #define MIPS_FP_CONDITIONS(MACRO) \
252 MACRO (f), \
253 MACRO (un), \
254 MACRO (eq), \
255 MACRO (ueq), \
256 MACRO (olt), \
257 MACRO (ult), \
258 MACRO (ole), \
259 MACRO (ule), \
260 MACRO (sf), \
261 MACRO (ngle), \
262 MACRO (seq), \
263 MACRO (ngl), \
264 MACRO (lt), \
265 MACRO (nge), \
266 MACRO (le), \
267 MACRO (ngt)
269 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
270 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
273 };
275 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
276 #define STRINGIFY(X) #X
279 };
281 /* A function to save or store a register. The first argument is the
282 register and the second is the stack slot. */
332 mips_save_restore_fn);
436 /* Structure to be filled in by compute_frame_size with register
437 save masks, and offsets for the current function. */
440 {
456 };
459 /* Pseudo-reg holding the value of $28 in a mips16 function which
460 refers to GP relative global variables. */
461 rtx mips16_gp_pseudo_rtx;
463 /* The number of extra stack bytes taken up by register varargs.
464 This area is allocated by the callee at the very top of the frame. */
467 /* Current frame information, calculated by compute_frame_size. */
470 /* The register to use as the global pointer within this function. */
473 /* True if mips_adjust_insn_length should ignore an instruction's
474 hazard attribute. */
477 /* True if the whole function is suitable for .set noreorder and
478 .set nomacro. */
481 /* True if the function is known to have an instruction that needs $gp. */
484 /* True if we have emitted an instruction to initialize
485 mips16_gp_pseudo_rtx. */
487 };
489 /* Information about a single argument. */
490 struct mips_arg_info
491 {
492 /* True if the argument is passed in a floating-point register, or
493 would have been if we hadn't run out of registers. */
496 /* The number of words passed in registers, rounded up. */
499 /* For EABI, the offset of the first register from GP_ARG_FIRST or
500 FP_ARG_FIRST. For other ABIs, the offset of the first register from
501 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
502 comment for details).
504 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
505 on the stack. */
508 /* The number of words that must be passed on the stack, rounded up. */
511 /* The offset from the start of the stack overflow area of the argument's
512 first stack word. Only meaningful when STACK_WORDS is nonzero. */
514 };
517 /* Information about an address described by mips_address_type.
519 ADDRESS_CONST_INT
520 No fields are used.
522 ADDRESS_REG
523 REG is the base register and OFFSET is the constant offset.
525 ADDRESS_LO_SUM
526 REG is the register that contains the high part of the address,
527 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
528 is the type of OFFSET's symbol.
530 ADDRESS_SYMBOLIC
531 SYMBOL_TYPE is the type of symbol being referenced. */
533 struct mips_address_info
534 {
536 rtx reg;
537 rtx offset;
539 };
542 /* One stage in a constant building sequence. These sequences have
543 the form:
545 A = VALUE[0]
546 A = A CODE[1] VALUE[1]
547 A = A CODE[2] VALUE[2]
548 ...
550 where A is an accumulator, each CODE[i] is a binary rtl operation
551 and each VALUE[i] is a constant integer. */
555 };
558 /* The largest number of operations needed to load an integer constant.
559 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
560 When the lowest bit is clear, we can try, but reject a sequence with
561 an extra SLL at the end. */
562 #define MIPS_MAX_INTEGER_OPS 7
564 /* Information about a MIPS16e SAVE or RESTORE instruction. */
566 /* The number of argument registers saved by a SAVE instruction.
567 0 for RESTORE instructions. */
570 /* Bit X is set if the instruction saves or restores GPR X. */
573 /* The total number of bytes to allocate. */
574 HOST_WIDE_INT size;
575 };
577 /* Global variables for machine-dependent things. */
579 /* Threshold for data being put into the small data/bss area, instead
580 of the normal data area. */
583 /* Count the number of .file directives, so that .loc is up to date. */
586 /* Count the number of sdb related labels are generated (to find block
587 start and end boundaries). */
590 /* Next label # for each statement for Silicon Graphics IRIS systems. */
593 /* Name of the file containing the current function. */
596 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
602 /* The next branch instruction is a branch likely, not branch normal. */
605 /* The operands passed to the last cmpMM expander. */
608 /* The target cpu for code generation. */
612 /* The target cpu for optimization and scheduling. */
616 /* Which instruction set architecture to use. */
619 /* Which ABI to use. */
622 /* Cost information to use. */
625 /* Remember the ambient target flags, excluding mips16. */
627 /* The mips16 command-line target flags only. */
629 /* Similar copies of option settings. */
638 /* The -mtext-loads setting. */
641 /* The -mllsc setting. */
644 /* The architecture selected by -mipsN. */
647 /* If TRUE, we split addresses into their high and low parts in the RTL. */
650 /* Mode used for saving/restoring general purpose registers. */
653 /* Array giving truth value on whether or not a given hard register
654 can support a given mode. */
657 /* List of all MIPS punctuation characters used by print_operand. */
660 /* Map GCC register number to debugger register number. */
664 /* A copy of the original flag_delayed_branch: see override_options. */
669 /* mips_split_p[X] is true if symbols of type X can be split by
670 mips_split_symbol(). */
673 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
674 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
675 if they are matched by a special .md file pattern. */
678 /* Likewise for HIGHs. */
681 /* Map hard register number to register class */
683 {
731 };
733 /* Table of machine dependent attributes. */
735 {
739 /* Switch MIPS16 ASE on and off per-function. We would really like
740 to make these type attributes, but GCC doesn't provide the hooks
741 we need to support the right conversion rules. As declaration
742 attributes, they affect code generation but don't carry other
743 semantics. */
747 };
748 \f
749 /* A table describing all the processors gcc knows about. Names are
750 matched in the order listed. The first mention of an ISA level is
751 taken as the canonical name for that ISA.
753 To ease comparison, please keep this table in the same order
754 as gas's mips_cpu_info_table[]. Please also make sure that
755 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
756 options correctly. */
758 /* Entries for generic ISAs */
767 /* MIPS I */
772 /* MIPS II */
775 /* MIPS III */
787 /* MIPS IV */
795 /* MIPS32 */
801 /* MIPS32 Release 2 */
837 /* MIPS64 */
845 /* End marker */
847 };
849 /* Default costs. If these are used for a processor we should look
850 up the actual costs. */
863 /* Need to replace these with the costs of calling the appropriate
864 libgcc routine. */
872 {
884 };
887 {
901 },
903 SOFT_FP_COSTS,
910 },
912 SOFT_FP_COSTS,
919 },
921 SOFT_FP_COSTS,
928 },
941 },
954 },
956 SOFT_FP_COSTS,
963 },
976 },
989 },
991 SOFT_FP_COSTS,
998 },
1011 },
1024 },
1037 },
1039 DEFAULT_COSTS
1040 },
1053 },
1066 },
1079 },
1081 DEFAULT_COSTS
1082 },
1084 DEFAULT_COSTS
1085 },
1087 DEFAULT_COSTS
1088 },
1090 /* The only costs that appear to be updated here are
1091 integer multiplication. */
1092 SOFT_FP_COSTS,
1099 },
1101 DEFAULT_COSTS
1102 },
1104 DEFAULT_COSTS
1105 },
1107 DEFAULT_COSTS
1108 },
1121 },
1134 },
1147 },
1149 /* The only costs that are changed here are
1150 integer multiplication. */
1162 },
1164 DEFAULT_COSTS
1165 },
1167 /* The only costs that are changed here are
1168 integer multiplication. */
1180 },
1182 /* These costs are the same as the SB-1A below. */
1194 },
1196 /* These costs are the same as the SB-1 above. */
1208 },
1210 DEFAULT_COSTS
1211 },
1212 };
1214 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
1215 mips16e_s2_s8_regs[X], it must also save the registers in indexes
1216 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
1219 };
1222 };
1224 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
1225 ordered from the uppermost in memory to the lowest in memory. */
1228 };
1229 \f
1230 /* Initialize the GCC target structure. */
1231 #undef TARGET_ASM_ALIGNED_HI_OP
1233 #undef TARGET_ASM_ALIGNED_SI_OP
1235 #undef TARGET_ASM_ALIGNED_DI_OP
1238 #undef TARGET_ASM_FUNCTION_PROLOGUE
1239 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1240 #undef TARGET_ASM_FUNCTION_EPILOGUE
1241 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1242 #undef TARGET_ASM_SELECT_RTX_SECTION
1243 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1244 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1245 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1247 #undef TARGET_SCHED_INIT
1248 #define TARGET_SCHED_INIT mips_sched_init
1249 #undef TARGET_SCHED_REORDER
1250 #define TARGET_SCHED_REORDER mips_sched_reorder
1251 #undef TARGET_SCHED_REORDER2
1252 #define TARGET_SCHED_REORDER2 mips_sched_reorder
1253 #undef TARGET_SCHED_VARIABLE_ISSUE
1254 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1255 #undef TARGET_SCHED_ADJUST_COST
1256 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1257 #undef TARGET_SCHED_ISSUE_RATE
1258 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1259 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1260 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1261 mips_multipass_dfa_lookahead
1263 #undef TARGET_DEFAULT_TARGET_FLAGS
1264 #define TARGET_DEFAULT_TARGET_FLAGS \
1265 (TARGET_DEFAULT \
1266 | TARGET_CPU_DEFAULT \
1267 | TARGET_ENDIAN_DEFAULT \
1268 | TARGET_FP_EXCEPTIONS_DEFAULT \
1269 | MASK_CHECK_ZERO_DIV \
1270 | MASK_FUSED_MADD)
1271 #undef TARGET_HANDLE_OPTION
1272 #define TARGET_HANDLE_OPTION mips_handle_option
1274 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1275 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1277 #undef TARGET_INSERT_ATTRIBUTES
1278 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
1279 #undef TARGET_MERGE_DECL_ATTRIBUTES
1280 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
1281 #undef TARGET_SET_CURRENT_FUNCTION
1282 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
1284 #undef TARGET_VALID_POINTER_MODE
1285 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1286 #undef TARGET_RTX_COSTS
1287 #define TARGET_RTX_COSTS mips_rtx_costs
1288 #undef TARGET_ADDRESS_COST
1289 #define TARGET_ADDRESS_COST mips_address_cost
1291 #undef TARGET_IN_SMALL_DATA_P
1292 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1294 #undef TARGET_MACHINE_DEPENDENT_REORG
1295 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1297 #undef TARGET_ASM_FILE_START
1298 #define TARGET_ASM_FILE_START mips_file_start
1299 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1300 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1302 #undef TARGET_INIT_LIBFUNCS
1303 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1305 #undef TARGET_BUILD_BUILTIN_VA_LIST
1306 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1307 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1308 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1310 #undef TARGET_PROMOTE_FUNCTION_ARGS
1311 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1312 #undef TARGET_PROMOTE_FUNCTION_RETURN
1313 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1314 #undef TARGET_PROMOTE_PROTOTYPES
1315 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
1317 #undef TARGET_RETURN_IN_MEMORY
1318 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1319 #undef TARGET_RETURN_IN_MSB
1320 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1322 #undef TARGET_ASM_OUTPUT_MI_THUNK
1323 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1324 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1325 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1327 #undef TARGET_SETUP_INCOMING_VARARGS
1328 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1329 #undef TARGET_STRICT_ARGUMENT_NAMING
1330 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1331 #undef TARGET_MUST_PASS_IN_STACK
1332 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1333 #undef TARGET_PASS_BY_REFERENCE
1334 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1335 #undef TARGET_CALLEE_COPIES
1336 #define TARGET_CALLEE_COPIES mips_callee_copies
1337 #undef TARGET_ARG_PARTIAL_BYTES
1338 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1340 #undef TARGET_MODE_REP_EXTENDED
1341 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1343 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1344 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1346 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1347 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
1349 #undef TARGET_INIT_BUILTINS
1350 #define TARGET_INIT_BUILTINS mips_init_builtins
1351 #undef TARGET_EXPAND_BUILTIN
1352 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1354 #undef TARGET_HAVE_TLS
1355 #define TARGET_HAVE_TLS HAVE_AS_TLS
1357 #undef TARGET_CANNOT_FORCE_CONST_MEM
1358 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1360 #undef TARGET_ENCODE_SECTION_INFO
1361 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1363 #undef TARGET_ATTRIBUTE_TABLE
1364 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1365 /* All our function attributes are related to how out-of-line copies should
1366 be compiled or called. They don't in themselves prevent inlining. */
1367 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
1368 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
1370 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1371 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1373 #undef TARGET_MIN_ANCHOR_OFFSET
1374 #define TARGET_MIN_ANCHOR_OFFSET -32768
1375 #undef TARGET_MAX_ANCHOR_OFFSET
1376 #define TARGET_MAX_ANCHOR_OFFSET 32767
1377 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1378 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1379 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1380 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1382 #undef TARGET_COMP_TYPE_ATTRIBUTES
1383 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
1385 #ifdef HAVE_AS_DTPRELWORD
1386 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1387 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
1388 #endif
1393 /* Predicates to test for presence of "near" and "far"/"long_call"
1394 attributes on the given TYPE. */
1396 static bool
1398 {
1400 }
1402 static bool
1404 {
1407 }
1409 /* Similar predicates for "mips16"/"nomips16" attributes. */
1411 static bool
1413 {
1415 }
1417 static bool
1419 {
1421 }
1423 /* Return 0 if the attributes for two types are incompatible, 1 if they
1424 are compatible, and 2 if they are nearly compatible (which causes a
1425 warning to be generated). */
1427 static int
1429 {
1430 /* Check for mismatch of non-default calling convention. */
1434 /* Disallow mixed near/far attributes. */
1441 }
1442 \f
1443 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1444 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1446 static void
1448 {
1450 {
1453 }
1454 else
1455 {
1458 }
1459 }
1460 \f
1461 /* Return true if SYMBOL_REF X is associated with a global symbol
1462 (in the STB_GLOBAL sense). */
1464 static bool
1466 {
1472 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1473 or weak symbols. Relocations in the object file will be against
1474 the target symbol, so it's that symbol's binding that matters here. */
1476 }
1478 /* Return true if SYMBOL_REF X binds locally. */
1480 static bool
1482 {
1486 }
1488 /* Return true if rtx constants of mode MODE should be put into a small
1489 data section. */
1491 static bool
1493 {
1495 && TARGET_LOCAL_SDATA
1497 }
1499 /* Return the method that should be used to access SYMBOL_REF or
1500 LABEL_REF X in context CONTEXT. */
1502 static enum mips_symbol_type
1504 {
1509 {
1510 /* LABEL_REFs are used for jump tables as well as text labels.
1511 Only return SYMBOL_PC_RELATIVE if we know the label is in
1512 the text section. */
1518 }
1526 {
1535 }
1537 /* Do not use small-data accesses for weak symbols; they may end up
1538 being zero. */
1544 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1545 is in effect. */
1548 {
1549 /* There are three cases to consider:
1551 - o32 PIC (either with or without explicit relocs)
1552 - n32/n64 PIC without explicit relocs
1553 - n32/n64 PIC with explicit relocs
1555 In the first case, both local and global accesses will use an
1556 R_MIPS_GOT16 relocation. We must correctly predict which of
1557 the two semantics (local or global) the assembler and linker
1558 will apply. The choice depends on the symbol's binding rather
1559 than its visibility.
1561 In the second case, the assembler will not use R_MIPS_GOT16
1562 relocations, but it chooses between local and global accesses
1563 in the same way as for o32 PIC.
1565 In the third case we have more freedom since both forms of
1566 access will work for any kind of symbol. However, there seems
1567 little point in doing things differently. */
1572 }
1577 }
1579 /* Classify symbolic expression X, given that it appears in context
1580 CONTEXT. */
1582 static enum mips_symbol_type
1584 {
1585 rtx offset;
1592 }
1594 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1595 is the alignment (in bytes) of SYMBOL_REF X. */
1597 static bool
1599 {
1600 /* If for some reason we can't get the alignment for the
1601 symbol, initializing this to one means we will only accept
1602 a zero offset. */
1604 tree t;
1606 /* Get the alignment of the symbol we're referring to. */
1612 }
1614 /* Return true if X is a symbolic constant that can be used in context
1615 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1617 bool
1620 {
1621 rtx offset;
1625 {
1628 }
1630 {
1634 }
1635 else
1641 /* Check whether a nonzero offset is valid for the underlying
1642 relocations. */
1644 {
1651 /* If the target has 64-bit pointers and the object file only
1652 supports 32-bit symbols, the values of those symbols will be
1653 sign-extended. In this case we can't allow an arbitrary offset
1654 in case the 32-bit value X + OFFSET has a different sign from X. */
1658 /* In other cases the relocations can handle any offset. */
1662 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1663 In this case, we no longer have access to the underlying constant,
1664 but the original symbol-based access was known to be valid. */
1668 /* Fall through. */
1671 /* Make sure that the offset refers to something within the
1672 same object block. This should guarantee that the final
1673 PC- or GP-relative offset is within the 16-bit limit. */
1678 /* If the symbol is global, the GOT entry will contain the symbol's
1679 address, and we will apply a 16-bit offset after loading it.
1680 If the symbol is local, the linker should provide enough local
1681 GOT entries for a 16-bit offset, but larger offsets may lead
1682 to GOT overflow. */
1687 /* There is no carry between the HI and LO REL relocations, so the
1688 offset is only valid if we know it won't lead to such a carry. */
1701 }
1703 }
1706 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1708 int
1710 {
1712 {
1716 }
1718 /* These fake registers will be eliminated to either the stack or
1719 hard frame pointer, both of which are usually valid base registers.
1720 Reload deals with the cases where the eliminated form isn't valid. */
1724 /* In mips16 mode, the stack pointer can only address word and doubleword
1725 values, nothing smaller. There are two problems here:
1727 (a) Instantiating virtual registers can introduce new uses of the
1728 stack pointer. If these virtual registers are valid addresses,
1729 the stack pointer should be too.
1731 (b) Most uses of the stack pointer are not made explicit until
1732 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1733 We don't know until that stage whether we'll be eliminating to the
1734 stack pointer (which needs the restriction) or the hard frame
1735 pointer (which doesn't).
1737 All in all, it seems more consistent to only enforce this restriction
1738 during and after reload. */
1743 }
1746 /* Return true if X is a valid base register for the given mode.
1747 Allow only hard registers if STRICT. */
1749 static bool
1751 {
1757 }
1760 /* Return true if X is a valid address for machine mode MODE. If it is,
1761 fill in INFO appropriately. STRICT is true if we should only accept
1762 hard base registers. */
1764 static bool
1767 {
1769 {
1788 /* We have to trust the creator of the LO_SUM to do something vaguely
1789 sane. Target-independent code that creates a LO_SUM should also
1790 create and verify the matching HIGH. Target-independent code that
1791 adds an offset to a LO_SUM must prove that the offset will not
1792 induce a carry. Failure to do either of these things would be
1793 a bug, and we are not required to check for it here. The MIPS
1794 backend itself should only create LO_SUMs for valid symbolic
1795 constants, with the high part being either a HIGH or a copy
1796 of _gp. */
1797 info->symbol_type
1804 /* Small-integer addresses don't occur very often, but they
1805 are legitimate if $0 is a valid base register. */
1820 }
1821 }
1823 /* Return true if X is a thread-local symbol. */
1825 static bool
1827 {
1829 }
1831 /* Return true if X can not be forced into a constant pool. */
1833 static int
1835 {
1837 }
1839 /* Return true if X can not be forced into a constant pool. */
1841 static bool
1843 {
1847 {
1848 /* As an optimization, reject constants that mips_legitimize_move
1849 can expand inline.
1851 Suppose we have a multi-instruction sequence that loads constant C
1852 into register R. If R does not get allocated a hard register, and
1853 R is used in an operand that allows both registers and memory
1854 references, reload will consider forcing C into memory and using
1855 one of the instruction's memory alternatives. Returning false
1856 here will force it to use an input reload instead. */
1863 }
1869 }
1871 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1872 constants when we're using a per-function constant pool. */
1874 static bool
1876 const_rtx x ATTRIBUTE_UNUSED)
1877 {
1879 }
1880 \f
1881 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1882 single instruction. We rely on the fact that, in the worst case,
1883 all instructions involved in a MIPS16 address calculation are usually
1884 extended ones. */
1886 static int
1888 {
1890 {
1892 /* When using 64-bit symbols, we need 5 preparatory instructions,
1893 such as:
1895 lui $at,%highest(symbol)
1896 daddiu $at,$at,%higher(symbol)
1897 dsll $at,$at,16
1898 daddiu $at,$at,%hi(symbol)
1899 dsll $at,$at,16
1901 The final address is then $at + %lo(symbol). With 32-bit
1902 symbols we just need a preparatory lui for normal mode and
1903 a preparatory "li; sll" for MIPS16. */
1907 /* Treat GP-relative accesses as taking a single instruction on
1908 MIPS16 too; the copy of $gp can often be shared. */
1912 /* PC-relative constants can be only be used with addiupc,
1913 lwpc and ldpc. */
1919 /* The constant must be loaded using addiupc first. */
1923 /* LEAs will be converted into constant-pool references by
1924 mips_reorg. */
1928 /* The constant must be loaded from the constant pool. */
1932 /* The constant will have to be loaded from the GOT before it
1933 is used in an address. */
1937 /* Fall through. */
1940 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1941 the local/global classification is accurate. See override_options
1942 for details.
1944 The worst cases are:
1946 (1) For local symbols when generating o32 or o64 code. The assembler
1947 will use:
1949 lw $at,%got(symbol)
1950 nop
1952 ...and the final address will be $at + %lo(symbol).
1954 (2) For global symbols when -mxgot. The assembler will use:
1956 lui $at,%got_hi(symbol)
1957 (d)addu $at,$at,$gp
1959 ...and the final address will be $at + %got_lo(symbol). */
1976 /* A 16-bit constant formed by a single relocation, or a 32-bit
1977 constant formed from a high 16-bit relocation and a low 16-bit
1978 relocation. Use mips_split_p to determine which. */
1982 /* We don't treat a bare TLS symbol as a constant. */
1984 }
1986 }
1988 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1989 to load symbols of type TYPE into a register. Return 0 if the given
1990 type of symbol cannot be used as an immediate operand.
1992 Otherwise, return the number of instructions needed to load or store
1993 values of mode MODE to or from addresses of type TYPE. Return 0 if
1994 the given type of symbol is not valid in addresses.
1996 In both cases, treat extended MIPS16 instructions as two instructions. */
1998 static int
2000 {
2002 }
2004 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2006 bool
2008 {
2014 }
2016 /* Return true if a value at OFFSET bytes from BASE can be accessed
2017 using an unextended mips16 instruction. MODE is the mode of the
2018 value.
2020 Usually the offset in an unextended instruction is a 5-bit field.
2021 The offset is unsigned and shifted left once for HIs, twice
2022 for SIs, and so on. An exception is SImode accesses off the
2023 stack pointer, which have an 8-bit immediate field. */
2025 static bool
2027 {
2032 {
2036 }
2038 }
2041 /* Return the number of instructions needed to load or store a value
2042 of mode MODE at X. Return 0 if X isn't valid for MODE. Assume that
2043 multiword moves may need to be split into word moves if MIGHT_SPLIT_P,
2044 otherwise assume that a single load or store is enough.
2046 For mips16 code, count extended instructions as two instructions. */
2048 int
2050 {
2054 /* BLKmode is used for single unaligned loads and stores and should
2055 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2056 meaningless, so we have to single it out as a special case one way
2057 or the other.) */
2060 else
2065 {
2080 }
2082 }
2085 /* Likewise for constant X. */
2087 int
2089 {
2092 rtx offset;
2095 {
2102 /* This is simply an lui for normal mode. It is an extended
2103 "li" followed by an extended "sll" for MIPS16. */
2108 /* Unsigned 8-bit constants can be loaded using an unextended
2109 LI instruction. Unsigned 16-bit constants can be loaded
2110 using an extended LI. Negative constants must be loaded
2111 using LI and then negated. */
2128 /* See if we can refer to X directly. */
2132 /* Otherwise try splitting the constant into a base and offset.
2133 16-bit offsets can be added using an extra addiu. Larger offsets
2134 must be calculated separately and then added to the base. */
2137 {
2140 {
2143 else
2145 }
2146 }
2152 MAX_MACHINE_MODE);
2156 }
2157 }
2160 /* Return the number of instructions needed to implement INSN,
2161 given that it loads from or stores to MEM. Count extended
2162 mips16 instructions as two instructions. */
2164 int
2166 {
2169 rtx set;
2174 /* Try to prove that INSN does not need to be split. */
2177 {
2181 }
2184 }
2187 /* Return the number of instructions needed for an integer division. */
2189 int
2191 {
2196 {
2198 count++;
2199 else
2201 }
2204 count++;
2206 }
2207 \f
2208 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
2209 returns a nonzero value if X is a legitimate address for a memory
2210 operand of the indicated MODE. STRICT is nonzero if this function
2211 is called during reload. */
2213 bool
2215 {
2219 }
2221 /* Emit a move from SRC to DEST. Assume that the move expanders can
2222 handle all moves if !can_create_pseudo_p (). The distinction is
2223 important because, unlike emit_move_insn, the move expanders know
2224 how to force Pmode objects into the constant pool even when the
2225 constant pool address is not itself legitimate. */
2227 rtx
2229 {
2233 }
2235 /* Copy VALUE to a register and return that register. If new psuedos
2236 are allowed, copy it into a new register, otherwise use DEST. */
2238 static rtx
2240 {
2243 else
2244 {
2247 }
2248 }
2251 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2252 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2253 constant in that context and can be split into a high part and a LO_SUM.
2254 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2255 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2257 TEMP is as for mips_force_temporary and is used to load the high
2258 part into a register. */
2260 bool
2262 {
2265 rtx high;
2268 ? SYMBOL_CONTEXT_LEA
2276 {
2278 {
2280 {
2283 }
2284 else
2286 }
2287 else
2288 {
2291 }
2293 }
2295 }
2298 /* Wrap symbol or label BASE in an unspec address of type SYMBOL_TYPE
2299 and add CONST_INT OFFSET to the result. */
2301 static rtx
2304 {
2310 }
2312 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2313 type SYMBOL_TYPE. */
2315 rtx
2317 {
2322 }
2325 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2326 high part to BASE and return the result. Just return BASE otherwise.
2327 TEMP is available as a temporary register if needed.
2329 The returned expression can be used as the first operand to a LO_SUM. */
2331 static rtx
2334 {
2336 {
2340 }
2342 }
2345 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2346 mips_force_temporary; it is only needed when OFFSET is not a
2347 SMALL_OPERAND. */
2349 static rtx
2351 {
2353 {
2354 rtx high;
2356 {
2357 /* Load the full offset into a register so that we can use
2358 an unextended instruction for the address itself. */
2361 }
2362 else
2363 {
2364 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2367 }
2370 }
2372 }
2374 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2375 referencing, and TYPE is the symbol type to use (either global
2376 dynamic or local dynamic). V0 is an RTX for the return value
2377 location. The entire insn sequence is returned. */
2381 static rtx
2383 {
2407 }
2409 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2410 return value will be a valid address and move_operand (either a REG
2411 or a LO_SUM). */
2413 static rtx
2415 {
2420 {
2423 }
2429 /* Only TARGET_ABICALLS code can have more than one module; other
2430 code must be be static and should not use a GOT. All TLS models
2431 reduce to local exec in this situation. */
2436 {
2447 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2448 share the LDM result with other LD model accesses. */
2450 UNSPEC_TLS_LDM);
2462 {
2465 }
2466 else
2467 {
2470 }
2478 else
2488 }
2491 }
2493 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2494 be legitimized in a way that the generic machinery might not expect,
2495 put the new address in *XLOC and return true. MODE is the mode of
2496 the memory being accessed. */
2498 bool
2500 {
2502 {
2505 }
2507 /* See if the address can split into a high part and a LO_SUM. */
2512 {
2513 /* Handle REG + CONSTANT using mips_add_offset. */
2514 rtx reg;
2521 }
2524 }
2527 /* Subroutine of mips_build_integer (with the same interface).
2528 Assume that the final action in the sequence should be a left shift. */
2530 static unsigned int
2532 {
2535 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2536 since signed numbers are easier to load than unsigned ones. */
2545 }
2548 /* As for mips_build_shift, but assume that the final action will be
2549 an IOR or PLUS operation. */
2551 static unsigned int
2553 {
2559 {
2560 /* The constant is too complex to load with a simple lui/ori pair
2561 so our goal is to clear as many trailing zeros as possible.
2562 In this case, we know bit 16 is set and that the low 16 bits
2563 form a negative number. If we subtract that number from VALUE,
2564 we will clear at least the lowest 17 bits, maybe more. */
2568 }
2569 else
2570 {
2574 }
2576 }
2579 /* Fill CODES with a sequence of rtl operations to load VALUE.
2580 Return the number of operations needed. */
2582 static unsigned int
2585 {
2589 {
2590 /* The value can be loaded with a single instruction. */
2594 }
2596 {
2597 /* Either the constant is a simple LUI/ORI combination or its
2598 lowest bit is set. We don't want to shift in this case. */
2600 }
2602 {
2603 /* The constant will need at least three actions. The lowest
2604 16 bits are clear, so the final action will be a shift. */
2606 }
2607 else
2608 {
2609 /* The final action could be a shift, add or inclusive OR.
2610 Rather than use a complex condition to select the best
2611 approach, try both mips_build_shift and mips_build_lower
2612 and pick the one that gives the shortest sequence.
2613 Note that this case is only used once per constant. */
2620 {
2623 }
2625 }
2626 }
2629 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2631 void
2633 {
2637 rtx x;
2642 /* Apply each binary operation to X. Invariant: X is a legitimate
2643 source operand for a SET pattern. */
2646 {
2648 {
2651 }
2652 else
2655 }
2658 }
2661 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2662 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2663 move_operand. */
2665 static void
2667 {
2670 /* Split moves of big integers into smaller pieces. */
2672 {
2675 }
2677 /* Split moves of symbolic constants into high/low pairs. */
2679 {
2682 }
2685 {
2688 }
2690 /* If we have (const (plus symbol offset)), and that expression cannot
2691 be forced into memory, load the symbol first and add in the offset.
2692 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2693 forced into memory, as it usually produces better code. */
2698 {
2702 }
2706 /* When using explicit relocs, constant pool references are sometimes
2707 not legitimate addresses. */
2710 }
2713 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2714 sequence that is valid. */
2716 bool
2718 {
2720 {
2723 }
2725 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2729 {
2735 else
2740 }
2742 /* We need to deal with constants that would be legitimate
2743 immediate_operands but not legitimate move_operands. */
2745 {
2749 }
2751 }
2752 \f
2753 /* We need a lot of little routines to check constant values on the
2754 mips16. These are used to figure out how long the instruction will
2755 be. It would be much better to do this using constraints, but
2756 there aren't nearly enough letters available. */
2758 static int
2760 {
2765 }
2767 int
2769 {
2771 }
2773 int
2775 {
2777 }
2779 int
2781 {
2783 }
2785 int
2787 {
2789 }
2791 int
2793 {
2795 }
2797 int
2799 {
2801 }
2803 int
2805 {
2807 }
2809 int
2811 {
2813 }
2815 int
2817 {
2819 }
2821 int
2823 {
2825 }
2827 int
2829 {
2831 }
2833 int
2835 {
2837 }
2839 int
2841 {
2843 }
2845 int
2847 {
2849 }
2851 int
2853 {
2855 }
2857 int
2859 {
2861 }
2862 \f
2863 /* Return true if ADDR matches the pattern for the lwxs load scaled indexed
2864 address instruction. */
2866 static bool
2868 {
2872 {
2879 }
2881 }
2883 /* The cost of loading values from the constant pool. It should be
2884 larger than the cost of any constant we want to synthesize inline. */
2886 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2888 /* Return the cost of X when used as an operand to the MIPS16 instruction
2889 that implements CODE. Return -1 if there is no such instruction, or if
2890 X is not a valid immediate operand for it. */
2892 static int
2894 {
2896 {
2900 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2901 other shifts are extended. The shift patterns truncate the shift
2902 count to the right size, so there are no out-of-range values. */
2915 /* Like LE, but reject the always-true case. */
2919 /* We add 1 to the immediate and use SLT. */
2922 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2933 /* Equality comparisons with 0 are cheap. */
2940 }
2941 }
2943 /* Return true if there is a non-MIPS16 instruction that implements CODE
2944 and if that instruction accepts X as an immediate operand. */
2946 static int
2948 {
2950 {
2954 /* All shift counts are truncated to a valid constant. */
2959 /* Likewise rotates, if the target supports rotates at all. */
2965 /* These instructions take 16-bit unsigned immediates. */
2971 /* These instructions take 16-bit signed immediates. */
2978 /* The "immediate" forms of these instructions are really
2979 implemented as comparisons with register 0. */
2984 /* Likewise, meaning that the only valid immediate operand is 1. */
2988 /* We add 1 to the immediate and use SLT. */
2992 /* Likewise SLTU, but reject the always-true case. */
2997 /* The bit position and size are immediate operands. */
3001 /* By default assume that $0 can be used for 0. */
3003 }
3004 }
3006 /* Return the cost of binary operation X, given that the instruction
3007 sequence for a word-sized or smaller operation has cost SINGLE_COST
3008 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3010 static int
3012 {
3017 else
3022 }
3024 /* Return the cost of floating-point multiplications of mode MODE. */
3026 static int
3028 {
3030 }
3032 /* Return the cost of floating-point divisions of mode MODE. */
3034 static int
3036 {
3038 }
3040 /* Return the cost of sign-extending OP to mode MODE, not including the
3041 cost of OP itself. */
3043 static int
3045 {
3047 /* Extended loads are as cheap as unextended ones. */
3051 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3055 /* We can use SEB or SEH. */
3058 /* We need to use a shift left and a shift right. */
3060 }
3062 /* Return the cost of zero-extending OP to mode MODE, not including the
3063 cost of OP itself. */
3065 static int
3067 {
3069 /* Extended loads are as cheap as unextended ones. */
3073 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3077 /* We can use ZEB or ZEH. */
3081 /* We need to load 0xff or 0xffff into a register and use AND. */
3084 /* We can use ANDI. */
3086 }
3088 /* Implement TARGET_RTX_COSTS. */
3090 static bool
3092 {
3096 rtx addr;
3098 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3099 appear in the instruction stream, and the cost of a comparison is
3100 really the cost of the branch or scc condition. At the time of
3101 writing, gcc only uses an explicit outer COMPARE code when optabs
3102 is testing whether a constant is expensive enough to force into a
3103 register. We want optabs to pass such constants through the MIPS
3104 expanders instead, so make all constants very cheap here. */
3106 {
3110 }
3113 {
3115 /* Treat *clear_upper32-style ANDs as having zero cost in the
3116 second operand. The cost is entirely in the first operand.
3118 ??? This is needed because we would otherwise try to CSE
3119 the constant operand. Although that's the right thing for
3120 instructions that continue to be a register operation throughout
3121 compilation, it is disastrous for instructions that could
3122 later be converted into a memory operation. */
3126 {
3129 }
3132 {
3135 {
3138 }
3139 }
3140 else
3141 {
3142 /* When not optimizing for size, we care more about the cost
3143 of hot code, and hot code is often in a loop. If a constant
3144 operand needs to be forced into a register, we will often be
3145 able to hoist the constant load out of the loop, so the load
3146 should not contribute to the cost. */
3149 {
3152 }
3153 }
3154 /* Fall through. */
3161 {
3164 }
3167 {
3168 /* If the constant is likely to be stored in a GPR, SETs of
3169 single-insn constants are as cheap as register sets; we
3170 never want to CSE them.
3172 Don't reduce the cost of storing a floating-point zero in
3173 FPRs. If we have a zero in an FPR for other reasons, we
3174 can get better cfg-cleanup and delayed-branch results by
3175 using it consistently, rather than using $0 sometimes and
3176 an FPR at other times. Also, moves between floating-point
3177 registers are sometimes cheaper than (D)MTC1 $0. */
3182 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3183 want to CSE the constant itself. It is usually better to
3184 have N copies of the last operation in the sequence and one
3185 shared copy of the other operations. (Note that this is
3186 not true for MIPS16 code, where the final operation in the
3187 sequence is often an extended instruction.)
3189 Also, if we have a CONST_INT, we don't know whether it is
3190 for a word or doubleword operation, so we cannot rely on
3191 the result of mips_build_integer. */
3197 }
3198 /* The value will need to be fetched from the constant pool. */
3203 /* If the address is legitimate, return the number of
3204 instructions it needs. */
3208 {
3211 }
3212 /* Check for a scaled indexed address. */
3214 {
3217 }
3218 /* Otherwise use the default handling. */
3230 /* Check for a *clear_upper32 pattern and treat it like a zero
3231 extension. See the pattern's comment for details. */
3236 {
3240 }
3241 /* Fall through. */
3245 /* Double-word operations use two single-word operations. */
3256 else
3263 else
3268 /* Low-part immediates need an extended MIPS16 instruction. */
3285 /* Branch comparisons have VOIDmode, so use the first operand's
3286 mode instead. */
3289 {
3292 }
3298 && ISA_HAS_NMADD_NMSUB
3299 && TARGET_FUSED_MADD
3302 {
3303 /* See if we can use NMADD or NMSUB. See mips.md for the
3304 associated patterns. */
3308 {
3314 }
3316 {
3322 }
3323 }
3324 /* Fall through. */
3328 {
3330 && TARGET_FUSED_MADD
3333 else
3336 }
3338 /* Double-word operations require three single-word operations and
3339 an SLTU. The MIPS16 version then needs to move the result of
3340 the SLTU from $24 to a MIPS16 register. */
3347 && ISA_HAS_NMADD_NMSUB
3348 && TARGET_FUSED_MADD
3351 {
3352 /* See if we can use NMADD or NMSUB. See mips.md for the
3353 associated patterns. */
3357 {
3363 }
3364 }
3368 else
3376 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3377 where the mulsidi3 always includes an MFHI and an MFLO. */
3385 else
3390 /* Check for a reciprocal. */
3392 {
3394 && flag_unsafe_math_optimizations
3396 {
3397 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3398 division as being free. */
3401 }
3403 {
3406 }
3407 }
3408 /* Fall through. */
3413 {
3416 }
3417 /* Fall through. */
3422 {
3423 /* It is our responsibility to make division by a power of 2
3424 as cheap as 2 register additions if we want the division
3425 expanders to be used for such operations; see the setting
3426 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3427 should always produce shorter code than using
3428 expand_sdiv2_pow2. */
3432 {
3435 }
3437 }
3440 else
3462 }
3463 }
3465 /* Provide the costs of an addressing mode that contains ADDR.
3466 If ADDR is not a valid address, its cost is irrelevant. */
3468 static int
3470 {
3472 }
3473 \f
3474 /* Return one word of double-word value OP, taking into account the fixed
3475 endianness of certain registers. HIGH_P is true to select the high part,
3476 false to select the low part. */
3478 rtx
3480 {
3490 else
3500 }
3503 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3505 bool
3507 {
3511 /* FP->FP moves can be done in a single instruction. */
3515 /* Check for floating-point loads and stores. They can be done using
3516 ldc1 and sdc1 on MIPS II and above. */
3518 {
3523 }
3525 }
3528 /* Split a 64-bit move from SRC to DEST assuming that
3529 mips_split_64bit_move_p holds.
3531 Moves into and out of FPRs cause some difficulty here. Such moves
3532 will always be DFmode, since paired FPRs are not allowed to store
3533 DImode values. The most natural representation would be two separate
3534 32-bit moves, such as:
3536 (set (reg:SI $f0) (mem:SI ...))
3537 (set (reg:SI $f1) (mem:SI ...))
3539 However, the second insn is invalid because odd-numbered FPRs are
3540 not allowed to store independent values. Use the patterns load_df_low,
3541 load_df_high and store_df_high instead. */
3543 void
3545 {
3547 {
3548 /* Loading an FPR from memory or from GPRs. */
3550 {
3555 }
3556 else
3557 {
3562 }
3563 }
3565 {
3566 /* Storing an FPR into memory or GPRs. */
3568 {
3572 }
3573 else
3574 {
3577 }
3578 }
3579 else
3580 {
3581 /* The operation can be split into two normal moves. Decide in
3582 which order to do them. */
3583 rtx low_dest;
3588 {
3591 }
3592 else
3593 {
3596 }
3597 }
3598 }
3599 \f
3600 /* Return the appropriate instructions to move SRC into DEST. Assume
3601 that SRC is operand 1 and DEST is operand 0. */
3605 {
3619 {
3621 {
3629 {
3634 }
3640 {
3645 }
3646 }
3649 }
3651 {
3653 {
3655 {
3660 }
3669 {
3674 }
3675 }
3681 {
3682 /* Don't use the X format, because that will give out of
3683 range numbers for 64-bit hosts and 32-bit targets. */
3692 }
3702 {
3703 /* A signed 16-bit constant formed by applying a relocation
3704 operator to a symbolic address. */
3707 }
3710 {
3712 ? TARGET_MIPS16_TEXT_LOADS
3715 }
3716 }
3718 {
3720 {
3723 else
3725 }
3729 }
3731 {
3734 }
3736 {
3742 }
3744 {
3750 }
3752 }
3753 \f
3754 /* Restore $gp from its save slot. Valid only when using o32 or
3755 o64 abicalls. */
3757 void
3759 {
3765 frame_pointer_needed
3766 ? hard_frame_pointer_rtx
3768 current_function_outgoing_args_size);
3774 }
3775 \f
3776 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3778 static void
3780 {
3783 }
3785 /* Return true if CMP1 is a suitable second operand for relational
3786 operator CODE. See also the *sCC patterns in mips.md. */
3788 static bool
3790 {
3792 {
3813 }
3814 }
3816 /* Canonicalize LE or LEU comparisons into LT comparisons when
3817 possible to avoid extra instructions or inverting the
3818 comparison. */
3820 static bool
3823 {
3833 {
3836 {
3840 }
3845 {
3849 }
3854 }
3858 }
3860 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3861 result in TARGET. CMP0 and TARGET are register_operands that have
3862 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3863 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3865 static void
3868 {
3869 /* First see if there is a MIPS instruction that can do this operation
3870 with CMP1 in its current form. If not, try to canonicalize the
3871 comparison to LT. If that fails, try doing the same for the
3872 inverse operation. If that also fails, force CMP1 into a register
3873 and try again. */
3878 else
3879 {
3882 {
3885 }
3887 {
3891 }
3892 else
3893 {
3896 }
3897 }
3898 }
3900 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3901 The register will have the same mode as CMP0. */
3903 static rtx
3905 {
3915 }
3917 /* Convert *CODE into a code that can be used in a floating-point
3918 scc instruction (c.<cond>.<fmt>). Return true if the values of
3919 the condition code registers will be inverted, with 0 indicating
3920 that the condition holds. */
3922 static bool
3924 {
3926 {
3935 }
3936 }
3938 /* Convert a comparison into something that can be used in a branch or
3939 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3940 being compared and *CODE is the code used to compare them.
3942 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3943 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3944 otherwise any standard branch condition can be used. The standard branch
3945 conditions are:
3947 - EQ/NE between two registers.
3948 - any comparison between a register and zero. */
3950 static void
3952 {
3954 {
3956 {
3959 }
3961 {
3963 {
3966 }
3967 else
3968 {
3971 }
3972 }
3973 else
3974 {
3975 /* The comparison needs a separate scc instruction. Store the
3976 result of the scc in *OP0 and compare it against zero. */
3983 }
3984 }
3986 {
3991 }
3992 else
3993 {
3996 /* Floating-point tests use a separate c.cond.fmt comparison to
3997 set a condition code register. The branch or conditional move
3998 will then compare that register against zero.
4000 Set CMP_CODE to the code of the comparison instruction and
4001 *CODE to the code that the branch or move should use. */
4009 }
4010 }
4011 \f
4012 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
4013 Store the result in TARGET and return true if successful.
4015 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
4017 bool
4019 {
4025 {
4028 }
4029 else
4033 }
4035 /* Emit the common code for doing conditional branches.
4036 operand[0] is the label to jump to.
4037 The comparison operands are saved away by cmp{si,di,sf,df}. */
4039 void
4041 {
4047 }
4049 /* Implement:
4051 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4052 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4054 void
4057 {
4058 rtx cmp_result;
4067 cmp_result));
4068 else
4070 cmp_result));
4071 }
4073 /* Emit the common code for conditional moves. OPERANDS is the array
4074 of operands passed to the conditional move define_expand. */
4076 void
4078 {
4090 }
4092 /* Emit a conditional trap. OPERANDS is the array of operands passed to
4093 the conditional_trap expander. */
4095 void
4097 {
4102 /* MIPS conditional trap machine instructions don't have GT or LE
4103 flavors, so we must invert the comparison and convert to LT and
4104 GE, respectively. */
4106 {
4112 }
4114 {
4117 }
4118 else
4119 {
4122 }
4130 }
4131 \f
4132 /* Return true if function DECL is a MIPS16 function. Return the ambient
4133 setting if DECL is null. */
4135 static bool
4137 {
4139 {
4140 /* Nested functions must use the same frame pointer as their
4141 parent and must therefore use the same ISA mode. */
4149 }
4151 }
4153 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
4155 static bool
4157 {
4161 }
4163 /* Load function address ADDR into register DEST. SIBCALL_P is true
4164 if the address is needed for a sibling call. */
4166 static void
4168 {
4169 /* If we're generating PIC, and this call is to a global function,
4170 try to allow its address to be resolved lazily. This isn't
4171 possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
4172 to the stub would be our caller's gp, not ours. */
4176 {
4184 else
4186 }
4187 else
4189 }
4192 /* Expand a call or call_value instruction. RESULT is where the
4193 result will go (null for calls), ADDR is the address of the
4194 function, ARGS_SIZE is the size of the arguments and AUX is
4195 the value passed to us by mips_function_arg. SIBCALL_P is true
4196 if we are expanding a sibling call, false if we're expanding
4197 a normal call. */
4199 void
4201 {
4206 {
4209 }
4212 && TARGET_HARD_FLOAT_ABI
4218 pattern = (sibcall_p
4222 {
4227 pattern =
4228 (sibcall_p
4231 }
4232 else
4233 pattern = (sibcall_p
4239 /* Lazy-binding stubs require $gp to be valid on entry. */
4242 }
4245 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
4247 static bool
4249 {
4253 /* We can't do a sibcall if the called function is a MIPS16 function
4254 because there is no direct "jx" instruction equivalent to "jalx" to
4255 switch the ISA mode. */
4259 /* Otherwise OK. */
4261 }
4262 \f
4263 /* Emit code to move general operand SRC into condition-code
4264 register DEST. SCRATCH is a scratch TFmode float register.
4265 The sequence is:
4267 FP1 = SRC
4268 FP2 = 0.0f
4269 DEST = FP2 < FP1
4271 where FP1 and FP2 are single-precision float registers
4272 taken from SCRATCH. */
4274 void
4276 {
4279 /* Change the source to SFmode. */
4291 }
4292 \f
4293 /* Emit code to change the current function's return address to
4294 ADDRESS. SCRATCH is available as a scratch register, if needed.
4295 ADDRESS and SCRATCH are both word-mode GPRs. */
4297 void
4299 {
4300 rtx slot_address;
4308 }
4309 \f
4310 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
4311 Assume that the areas do not overlap. */
4313 static void
4315 {
4322 /* Work out how many bits to move at a time. If both operands have
4323 half-word alignment, it is usually better to move in half words.
4324 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
4325 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
4326 Otherwise move word-sized chunks. */
4330 else
4336 /* Allocate a buffer for the temporary registers. */
4339 /* Load as many BITS-sized chunks as possible. Use a normal load if
4340 the source has enough alignment, otherwise use left/right pairs. */
4342 {
4346 else
4347 {
4351 }
4352 }
4354 /* Copy the chunks to the destination. */
4358 else
4359 {
4363 }
4365 /* Mop up any left-over bytes. */
4367 {
4372 }
4373 }
4374 \f
4375 #define MAX_MOVE_REGS 4
4376 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
4379 /* Helper function for doing a loop-based block operation on memory
4380 reference MEM. Each iteration of the loop will operate on LENGTH
4381 bytes of MEM.
4383 Create a new base register for use within the loop and point it to
4384 the start of MEM. Create a new memory reference that uses this
4385 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
4387 static void
4390 {
4393 /* Although the new mem does not refer to a known location,
4394 it does keep up to LENGTH bytes of alignment. */
4397 }
4400 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
4401 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
4402 memory regions do not overlap. */
4404 static void
4406 {
4408 HOST_WIDE_INT leftover;
4413 /* Create registers and memory references for use within the loop. */
4417 /* Calculate the value that SRC_REG should have after the last iteration
4418 of the loop. */
4422 /* Emit the start of the loop. */
4426 /* Emit the loop body. */
4429 /* Move on to the next block. */
4433 /* Emit the loop condition. */
4436 else
4440 /* Mop up any left-over bytes. */
4443 }
4444 \f
4446 /* Expand a loop of synci insns for the address range [BEGIN, END). */
4448 void
4450 {
4453 /* Load INC with the cache line size (rdhwr INC,$1). */
4457 /* Loop back to here. */
4470 }
4471 \f
4472 /* Expand a movmemsi instruction. */
4474 bool
4476 {
4478 {
4480 {
4483 }
4485 {
4488 }
4489 }
4491 }
4492 \f
4493 /* Argument support functions. */
4495 /* Initialize CUMULATIVE_ARGS for a function. */
4497 void
4499 rtx libname ATTRIBUTE_UNUSED)
4500 {
4507 /* Determine if this function has variable arguments. This is
4508 indicated by the last argument being 'void_type_mode' if there
4509 are no variable arguments. The standard MIPS calling sequence
4510 passes all arguments in the general purpose registers in this case. */
4514 {
4518 }
4519 }
4522 /* Fill INFO with information about a single argument. CUM is the
4523 cumulative state for earlier arguments. MODE is the mode of this
4524 argument and TYPE is its type (if known). NAMED is true if this
4525 is a named (fixed) argument rather than a variable one. */
4527 static void
4530 {
4534 /* Work out the size of the argument. */
4538 /* Decide whether it should go in a floating-point register, assuming
4539 one is free. Later code checks for availability.
4541 The checks against UNITS_PER_FPVALUE handle the soft-float and
4542 single-float cases. */
4544 {
4546 /* The EABI conventions have traditionally been defined in terms
4547 of TYPE_MODE, regardless of the actual type. */
4555 /* Only leading floating-point scalars are passed in
4556 floating-point registers. We also handle vector floats the same
4557 say, which is OK because they are not covered by the standard ABI. */
4569 /* Scalar and complex floating-point types are passed in
4570 floating-point registers. */
4578 /* ??? According to the ABI documentation, the real and imaginary
4579 parts of complex floats should be passed in individual registers.
4580 The real and imaginary parts of stack arguments are supposed
4581 to be contiguous and there should be an extra word of padding
4582 at the end.
4584 This has two problems. First, it makes it impossible to use a
4585 single "void *" va_list type, since register and stack arguments
4586 are passed differently. (At the time of writing, MIPSpro cannot
4587 handle complex float varargs correctly.) Second, it's unclear
4588 what should happen when there is only one register free.
4590 For now, we assume that named complex floats should go into FPRs
4591 if there are two FPRs free, otherwise they should be passed in the
4592 same way as a struct containing two floats. */
4596 {
4599 else
4601 }
4606 }
4608 /* See whether the argument has doubleword alignment. */
4611 /* Set REG_OFFSET to the register count we're interested in.
4612 The EABI allocates the floating-point registers separately,
4613 but the other ABIs allocate them like integer registers. */
4618 /* Advance to an even register if the argument is doubleword-aligned. */
4622 /* Work out the offset of a stack argument. */
4629 /* Partition the argument between registers and stack. */
4632 }
4635 /* INFO describes an argument that is passed in a single-register value.
4636 Return the register it uses, assuming that FPRs are available if
4637 HARD_FLOAT_P. */
4639 static unsigned int
4641 {
4645 /* In o32, the second argument is always passed in $f14
4646 for TARGET_DOUBLE_FLOAT, regardless of whether the
4647 first argument was a word or doubleword. */
4649 else
4651 }
4653 /* Implement FUNCTION_ARG_ADVANCE. */
4655 void
4658 {
4666 /* See the comment above the cumulative args structure in mips.h
4667 for an explanation of what this code does. It assumes the O32
4668 ABI, which passes at most 2 arguments in float registers. */
4681 }
4683 /* Implement FUNCTION_ARG. */
4688 {
4691 /* We will be called with a mode of VOIDmode after the last argument
4692 has been seen. Whatever we return will be passed to the call
4693 insn. If we need a mips16 fp_code, return a REG with the code
4694 stored as the mode. */
4696 {
4700 else
4702 }
4706 /* Return straight away if the whole argument is passed on the stack. */
4712 && TARGET_NEWABI
4716 {
4717 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
4718 structure contains a double in its entirety, then that 64-bit
4719 chunk is passed in a floating point register. */
4720 tree field;
4722 /* First check to see if there is any such field. */
4732 {
4733 /* Now handle the special case by returning a PARALLEL
4734 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4735 chunks are passed in registers. */
4737 HOST_WIDE_INT bitpos;
4738 rtx ret;
4740 /* assign_parms checks the mode of ENTRY_PARM, so we must
4741 use the actual mode here. */
4747 {
4748 rtx reg;
4758 && !TARGET_SOFT_FLOAT
4761 else
4769 }
4771 }
4772 }
4774 /* Handle the n32/n64 conventions for passing complex floating-point
4775 arguments in FPR pairs. The real part goes in the lower register
4776 and the imaginary part goes in the upper register. */
4780 {
4788 {
4789 /* Real part in registers, imaginary part on stack. */
4792 }
4793 else
4794 {
4798 const0_rtx);
4804 }
4805 }
4808 }
4811 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4813 static int
4816 {
4821 }
4824 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4825 PARM_BOUNDARY bits of alignment, but will be given anything up
4826 to STACK_BOUNDARY bits if the type requires it. */
4828 int
4830 {
4839 }
4841 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4842 upward rather than downward. In other words, return true if the
4843 first byte of the stack slot has useful data, false if the last
4844 byte does. */
4846 bool
4848 {
4849 /* On little-endian targets, the first byte of every stack argument
4850 is passed in the first byte of the stack slot. */
4854 /* Otherwise, integral types are padded downward: the last byte of a
4855 stack argument is passed in the last byte of the stack slot. */
4864 /* Big-endian o64 pads floating-point arguments downward. */
4869 /* Other types are padded upward for o32, o64, n32 and n64. */
4873 /* Arguments smaller than a stack slot are padded downward. */
4876 else
4878 }
4881 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4882 if the least significant byte of the register has useful data. Return
4883 the opposite if the most significant byte does. */
4885 bool
4887 {
4888 /* No shifting is required for floating-point arguments. */
4892 /* Otherwise, apply the same padding to register arguments as we do
4893 to stack arguments. */
4895 }
4896 \f
4897 static void
4901 {
4902 CUMULATIVE_ARGS local_cum;
4905 /* The caller has advanced CUM up to, but not beyond, the last named
4906 argument. Advance a local copy of CUM past the last "real" named
4907 argument, to find out how many registers are left over. */
4912 /* Found out how many registers we need to save. */
4914 fp_saved = (EABI_FLOAT_VARARGS_P
4919 {
4921 {
4932 }
4934 {
4935 /* We can't use move_block_from_reg, because it will use
4936 the wrong mode. */
4940 /* Set OFF to the offset from virtual_incoming_args_rtx of
4941 the first float register. The FP save area lies below
4942 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4951 {
4959 }
4960 }
4961 }
4965 }
4967 /* Create the va_list data type.
4968 We keep 3 pointers, and two offsets.
4969 Two pointers are to the overflow area, which starts at the CFA.
4970 One of these is constant, for addressing into the GPR save area below it.
4971 The other is advanced up the stack through the overflow region.
4972 The third pointer is to the GPR save area. Since the FPR save area
4973 is just below it, we can address FPR slots off this pointer.
4974 We also keep two one-byte offsets, which are to be subtracted from the
4975 constant pointers to yield addresses in the GPR and FPR save areas.
4976 These are downcounted as float or non-float arguments are used,
4977 and when they get to zero, the argument must be obtained from the
4978 overflow region.
4979 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4980 pointer is enough. It's started at the GPR save area, and is
4981 advanced, period.
4982 Note that the GPR save area is not constant size, due to optimization
4983 in the prologue. Hence, we can't use a design with two pointers
4984 and two offsets, although we could have designed this with two pointers
4985 and three offsets. */
4987 static tree
4989 {
4991 {
4998 ptr_type_node);
5000 ptr_type_node);
5002 ptr_type_node);
5004 unsigned_char_type_node);
5006 unsigned_char_type_node);
5007 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5008 warn on every user file. */
5030 }
5032 /* On IRIX 6, this type is 'char *'. */
5034 else
5035 /* Otherwise, we use 'void *'. */
5037 }
5039 /* Implement va_start. */
5041 void
5043 {
5045 {
5049 tree t;
5055 gpr_save_area_size
5057 fpr_save_area_size
5067 NULL_TREE);
5069 NULL_TREE);
5071 NULL_TREE);
5073 NULL_TREE);
5075 NULL_TREE);
5077 /* Emit code to initialize OVFL, which points to the next varargs
5078 stack argument. CUM->STACK_WORDS gives the number of stack
5079 words used by named arguments. */
5087 /* Emit code to initialize GTOP, the top of the GPR save area. */
5092 /* Emit code to initialize FTOP, the top of the FPR save area.
5093 This address is gpr_save_area_bytes below GTOP, rounded
5094 down to the next fp-aligned boundary. */
5104 /* Emit code to initialize GOFF, the offset from GTOP of the
5105 next GPR argument. */
5110 /* Likewise emit code to initialize FOFF, the offset from FTOP
5111 of the next FPR argument. */
5115 }
5116 else
5117 {
5120 }
5121 }
5122 \f
5123 /* Implement va_arg. */
5125 static tree
5127 {
5129 tree addr;
5142 else
5143 {
5144 /* Not a simple merged stack. */
5148 HOST_WIDE_INT osize;
5157 /* We maintain separate pointers and offsets for floating-point
5158 and integer arguments, but we need similar code in both cases.
5159 Let:
5161 TOP be the top of the register save area;
5162 OFF be the offset from TOP of the next register;
5163 ADDR_RTX be the address of the argument;
5164 RSIZE be the number of bytes used to store the argument
5165 when it's in the register save area;
5166 OSIZE be the number of bytes used to store it when it's
5167 in the stack overflow area; and
5168 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
5170 The code we want is:
5172 1: off &= -rsize; // round down
5173 2: if (off != 0)
5174 3: {
5175 4: addr_rtx = top - off;
5176 5: off -= rsize;
5177 6: }
5178 7: else
5179 8: {
5180 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
5181 10: addr_rtx = ovfl + PADDING;
5182 11: ovfl += osize;
5183 14: }
5185 [1] and [9] can sometimes be optimized away. */
5188 NULL_TREE);
5192 {
5194 NULL_TREE);
5196 NULL_TREE);
5198 /* When floating-point registers are saved to the stack,
5199 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
5200 of the float's precision. */
5203 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5204 (= PARM_BOUNDARY bits). This can be different from RSIZE
5205 in two cases:
5207 (1) On 32-bit targets when TYPE is a structure such as:
5209 struct s { float f; };
5211 Such structures are passed in paired FPRs, so RSIZE
5212 will be 8 bytes. However, the structure only takes
5213 up 4 bytes of memory, so OSIZE will only be 4.
5215 (2) In combinations such as -mgp64 -msingle-float
5216 -fshort-double. Doubles passed in registers
5217 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
5218 but those passed on the stack take up
5219 UNITS_PER_WORD bytes. */
5221 }
5222 else
5223 {
5225 NULL_TREE);
5227 NULL_TREE);
5229 {
5230 /* [1] Emit code for: off &= -rsize. */
5235 }
5237 }
5239 /* [2] Emit code to branch if off == 0. */
5244 /* [5] Emit code for: off -= rsize. We do this as a form of
5245 post-increment not available to C. Also widen for the
5246 coming pointer arithmetic. */
5252 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
5253 the argument has RSIZE - SIZE bytes of leading padding. */
5256 {
5259 }
5263 {
5264 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
5272 }
5273 else
5276 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
5277 post-increment ovfl by osize. On big-endian machines,
5278 the argument has OSIZE - SIZE bytes of leading padding. */
5283 {
5286 }
5288 /* String [9] and [10,11] together. */
5295 }
5301 }
5302 \f
5303 /* Return true if it is possible to use left/right accesses for a
5304 bitfield of WIDTH bits starting BITPOS bits into *OP. When
5305 returning true, update *OP, *LEFT and *RIGHT as follows:
5307 *OP is a BLKmode reference to the whole field.
5309 *LEFT is a QImode reference to the first byte if big endian or
5310 the last byte if little endian. This address can be used in the
5311 left-side instructions (lwl, swl, ldl, sdl).
5313 *RIGHT is a QImode reference to the opposite end of the field and
5314 can be used in the patterning right-side instruction. */
5316 static bool
5319 {
5322 /* Check that the operand really is a MEM. Not all the extv and
5323 extzv predicates are checked. */
5327 /* Check that the size is valid. */
5331 /* We can only access byte-aligned values. Since we are always passed
5332 a reference to the first byte of the field, it is not necessary to
5333 do anything with BITPOS after this check. */
5337 /* Reject aligned bitfields: we want to use a normal load or store
5338 instead of a left/right pair. */
5342 /* Adjust *OP to refer to the whole field. This also has the effect
5343 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
5347 /* Get references to both ends of the field. We deliberately don't
5348 use the original QImode *OP for FIRST since the new BLKmode one
5349 might have a simpler address. */
5353 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
5354 be the upper word and RIGHT the lower word. */
5357 else
5361 }
5364 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
5365 Return true on success. We only handle cases where zero_extract is
5366 equivalent to sign_extract. */
5368 bool
5370 {
5373 /* If TARGET_64BIT, the destination of a 32-bit load will be a
5374 paradoxical word_mode subreg. This is the only case in which
5375 we allow the destination to be larger than the source. */
5382 /* After the above adjustment, the destination must be the same
5383 width as the source. */
5392 {
5395 }
5396 else
5397 {
5400 }
5402 }
5405 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
5406 true on success. */
5408 bool
5410 {
5421 {
5424 }
5425 else
5426 {
5429 }
5431 }
5433 /* Return true if X is a MEM with the same size as MODE. */
5435 bool
5437 {
5438 rtx size;
5445 }
5447 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
5448 source of an "ext" instruction or the destination of an "ins"
5449 instruction. OP must be a register operand and the following
5450 conditions must hold:
5452 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
5453 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
5454 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
5456 Also reject lengths equal to a word as they are better handled
5457 by the move patterns. */
5459 bool
5461 {
5477 }
5479 /* Set up globals to generate code for the ISA or processor
5480 described by INFO. */
5482 static void
5484 {
5486 {
5490 }
5491 }
5494 /* Likewise for tuning. */
5496 static void
5498 {
5500 {
5503 }
5504 }
5506 /* Initialize mips_split_addresses from the associated command-line
5507 settings.
5509 mips_split_addresses is a half-way house between explicit
5510 relocations and the traditional assembler macros. It can
5511 split absolute 32-bit symbolic constants into a high/lo_sum
5512 pair but uses macros for other sorts of access.
5514 Like explicit relocation support for REL targets, it relies
5515 on GNU extensions in the assembler and the linker.
5517 Although this code should work for -O0, it has traditionally
5518 been treated as an optimization. */
5520 static void
5522 {
5527 else
5529 }
5531 /* (Re-)Initialize information about relocs. */
5533 static void
5535 {
5541 {
5543 {
5558 }
5559 }
5560 else
5561 {
5563 {
5569 }
5570 }
5573 {
5574 /* The high part is provided by a pseudo copy of $gp. */
5577 }
5580 {
5581 /* Small data constants are kept whole until after reload,
5582 then lowered by mips_rewrite_small_data. */
5587 {
5590 }
5591 else
5592 {
5595 }
5598 {
5599 /* The HIGH and LO_SUM are matched by special .md patterns. */
5609 }
5610 else
5611 {
5614 else
5617 }
5618 }
5621 {
5625 }
5627 /* Thread-local relocation operators. */
5639 }
5643 /* Set up the target-dependent global state so that it matches the
5644 current function's ISA mode. */
5646 static void
5648 {
5652 /* Restore base settings of various flags. */
5663 {
5664 /* Select mips16 instruction set. */
5667 /* Don't run the scheduler before reload, since it tends to
5668 increase register pressure. */
5671 /* Don't do hot/cold partitioning. The constant layout code expects
5672 the whole function to be in a single section. */
5675 /* Don't move loop invariants, because it tends to increase
5676 register pressure. It also introduces an extra move in cases
5677 where the constant is the first operand in a two-operand binary
5678 instruction, or when it forms a register argument to a functon
5679 call. */
5682 /* Silently disable -mexplicit-relocs since it doesn't apply
5683 to mips16 code. Even so, it would overly pedantic to warn
5684 about "-mips16 -mexplicit-relocs", especially given that
5685 we use a %gprel() operator. */
5688 /* Silently disable DSP extensions. */
5692 /* Experiments suggest we get the best overall results from using
5693 the range of an unextended lw or sw. Code that makes heavy use
5694 of byte or short accesses can do better with ranges of 0...31
5695 and 0...63 respectively, but most code is sensitive to the range
5696 of lw and sw instead. */
5702 }
5703 else
5704 {
5705 /* Reset to select base non-mips16 ISA. */
5708 /* When using explicit relocs, we call dbr_schedule from within
5709 mips_reorg. */
5713 /* Provide default values for align_* for 64-bit targets. */
5715 {
5722 }
5726 }
5728 /* (Re)initialize mips target internals for new ISA. */
5733 /* Reinitialize target-dependent state. */
5737 }
5739 /* Use a hash table to keep track of implicit mips16/nomips16 attributes
5740 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
5745 };
5748 /* Hash table callbacks for mflip_mips16_htab. */
5750 static hashval_t
5752 {
5754 }
5756 static int
5758 {
5761 }
5763 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
5764 for -mflip-mips16. Return true if it should use "mips16" and false if
5765 it should use "nomips16". */
5767 static bool
5769 {
5772 hashval_t hash;
5775 /* Use the opposite of the command-line setting for anonymous decls. */
5788 {
5794 }
5796 }
5798 /* Implement TARGET_INSERT_ATTRIBUTES. */
5800 static void
5802 {
5806 /* Check for "mips16" and "nomips16" attributes. */
5810 {
5815 }
5816 else
5817 {
5821 {
5822 /* DECL cannot be simultaneously mips16 and nomips16. */
5827 }
5829 {
5830 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
5831 "mips16" attribute, arbitrarily pick one. We must pick the same
5832 setting for duplicate declarations of a function. */
5835 }
5836 }
5837 }
5839 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
5841 static tree
5843 {
5844 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
5854 }
5856 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
5857 function should use the MIPS16 ISA and switch modes accordingly. */
5859 static void
5861 {
5863 }
5865 /* Implement TARGET_HANDLE_OPTION. */
5867 static bool
5869 {
5871 {
5883 else
5906 else
5916 }
5917 }
5919 /* Set up the threshold for data to go into the small data area, instead
5920 of the normal data area, and detect any conflicts in the switches. */
5922 void
5924 {
5928 #ifdef SUBTARGET_OVERRIDE_OPTIONS
5929 SUBTARGET_OVERRIDE_OPTIONS;
5930 #endif
5934 /* The following code determines the architecture and register size.
5935 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
5936 The GAS and GCC code should be kept in sync as much as possible. */
5942 {
5950 }
5953 {
5954 #ifdef MIPS_CPU_STRING_DEFAULT
5956 #else
5958 #endif
5959 }
5965 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5972 /* Set cost structure for the processor. */
5975 else
5978 /* If the user hasn't specified a branch cost, use the processor's
5979 default. */
5984 {
5985 /* The user specified the size of the integer registers. Make sure
5986 it agrees with the ABI and ISA. */
5993 }
5994 else
5995 {
5996 /* Infer the integer register size from the ABI and processor.
5997 Restrict ourselves to 32-bit registers if that's all the
5998 processor has, or if the ABI cannot handle 64-bit registers. */
6001 else
6003 }
6006 {
6007 /* Really, -mfp32 and -mfp64 are ornamental options. There's
6008 only one right answer here. */
6017 }
6018 else
6019 {
6020 /* -msingle-float selects 32-bit float registers. Otherwise the
6021 float registers should be the same size as the integer ones. */
6024 else
6026 }
6028 /* End of code shared with GAS. */
6031 {
6034 else
6036 }
6042 {
6043 /* If neither -mbranch-likely nor -mno-branch-likely was given
6044 on the command line, set MASK_BRANCHLIKELY based on the target
6045 architecture.
6047 By default, we enable use of Branch Likely instructions on
6048 all architectures which support them with the following
6049 exceptions: when creating MIPS32 or MIPS64 code, and when
6050 tuning for architectures where their use tends to hurt
6051 performance.
6053 The MIPS32 and MIPS64 architecture specifications say "Software
6054 is strongly encouraged to avoid use of Branch Likely
6055 instructions, as they will be removed from a future revision
6056 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
6057 issue those instructions unless instructed to do so by
6058 -mbranch-likely. */
6063 else
6065 }
6067 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
6069 /* The effect of -mabicalls isn't defined for the EABI. */
6071 {
6074 }
6076 /* MIPS16 cannot generate PIC yet. */
6078 {
6082 }
6085 /* We need to set flag_pic for executables as well as DSOs
6086 because we may reference symbols that are not defined in
6087 the final executable. (MIPS does not use things like
6088 copy relocs, for example.)
6090 Also, there is a body of code that uses __PIC__ to distinguish
6091 between -mabicalls and -mno-abicalls code. */
6094 /* -mvr4130-align is a "speed over size" optimization: it usually produces
6095 faster code, but at the expense of more nops. Enable it at -O3 and
6096 above. */
6100 /* Prefer a call to memcpy over inline code when optimizing for size,
6101 though see MOVE_RATIO in mips.h. */
6105 /* If we have a nonzero small-data limit, check that the -mgpopt
6106 setting is consistent with the other target flags. */
6108 {
6110 {
6116 }
6117 else
6118 {
6125 }
6126 }
6128 #ifdef MIPS_TFMODE_FORMAT
6130 #endif
6132 /* Make sure that the user didn't turn off paired single support when
6133 MIPS-3D support is requested. */
6138 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
6142 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
6143 and TARGET_HARD_FLOAT are both true. */
6147 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
6148 enabled. */
6152 /* If TARGET_DSPR2, enable MASK_DSP. */
6179 /* Set up array to map GCC register number to debug register number.
6180 Ignore the special purpose register numbers. */
6183 {
6187 else
6189 }
6199 /* HI and LO debug registers use big-endian ordering. */
6205 {
6208 }
6210 /* Set up array giving whether a given register can hold a given mode. */
6215 {
6220 {
6224 temp = (ISA_HAS_8CC
6229 temp = (ISA_HAS_8CC
6234 {
6237 else
6240 }
6252 /* Allow integer modes that fit into a single
6253 register. We need to put integers into FPRs
6254 when using instructions like cvt and trunc.
6255 We can't allow sizes smaller than a word,
6256 the FPU has no appropriate load/store
6257 instructions for those. */
6261 /* Allow TFmode for CCmode reloads. */
6274 else
6278 }
6279 }
6281 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
6282 initialized yet, so we can't use that here. */
6285 /* Function to allocate machine-dependent function status. */
6288 /* Default to working around R4000 errata only if the processor
6289 was selected explicitly. */
6294 /* Default to working around R4400 errata only if the processor
6295 was selected explicitly. */
6300 /* Save base state of options. */
6311 /* Now select the mips16 or 32-bit instruction set, as requested. */
6313 }
6315 /* Swap the register information for registers I and I + 1, which
6316 currently have the wrong endianness. Note that the registers'
6317 fixedness and call-clobberedness might have been set on the
6318 command line. */
6320 static void
6322 {
6326 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
6327 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
6334 #undef SWAP_STRING
6335 #undef SWAP_INT
6336 }
6338 /* Implement CONDITIONAL_REGISTER_USAGE. */
6340 void
6342 {
6344 {
6349 }
6351 {
6358 }
6360 {
6363 /* We only have a single condition code register. We
6364 implement this by hiding all the condition code registers,
6365 and generating RTL that refers directly to ST_REG_FIRST. */
6368 }
6369 /* In mips16 mode, we permit the $t temporary registers to be used
6370 for reload. We prohibit the unused $s registers, since they
6371 are caller saved, and saving them via a mips16 register would
6372 probably waste more time than just reloading the value. */
6374 {
6384 }
6385 /* fp20-23 are now caller saved. */
6387 {
6391 }
6392 /* Odd registers from fp21 to fp31 are now caller saved. */
6394 {
6398 }
6399 /* Make sure that double-register accumulator values are correctly
6400 ordered for the current endianness. */
6402 {
6407 }
6408 }
6410 /* Allocate a chunk of memory for per-function machine-dependent data. */
6413 {
6416 }
6418 /* On the mips16, we want to allocate $24 (T_REG) before other
6419 registers for instructions for which it is possible. This helps
6420 avoid shuffling registers around in order to set up for an xor,
6421 encouraging the compiler to use a cmp instead. */
6423 void
6425 {
6432 {
6433 /* It really doesn't matter where we put register 0, since it is
6434 a fixed register anyhow. */
6437 }
6438 }
6440 \f
6441 /* The MIPS debug format wants all automatic variables and arguments
6442 to be in terms of the virtual frame pointer (stack pointer before
6443 any adjustment in the function), while the MIPS 3.0 linker wants
6444 the frame pointer to be the stack pointer after the initial
6445 adjustment. So, we do the adjustment here. The arg pointer (which
6446 is eliminated) points to the virtual frame pointer, while the frame
6447 pointer (which may be eliminated) points to the stack pointer after
6448 the initial adjustments. */
6450 HOST_WIDE_INT
6452 {
6461 {
6466 /* MIPS16 frame is smaller */
6471 }
6473 /* sdbout_parms does not want this to crash for unrecognized cases. */
6474 #if 0
6477 addr);
6478 #endif
6481 }
6482 \f
6483 /* If OP is an UNSPEC address, return the address to which it refers,
6484 otherwise return OP itself. */
6486 static rtx
6488 {
6495 }
6497 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6499 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
6500 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
6501 'h' OP is HIGH, prints %hi(X),
6502 'd' output integer constant in decimal,
6503 'z' if the operand is 0, use $0 instead of normal operand.
6504 'D' print second part of double-word register or memory operand.
6505 'L' print low-order register of double-word register operand.
6506 'M' print high-order register of double-word register operand.
6507 'C' print part of opcode for a branch condition.
6508 'F' print part of opcode for a floating-point branch condition.
6509 'N' print part of opcode for a branch condition, inverted.
6510 'W' print part of opcode for a floating-point branch condition, inverted.
6511 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6512 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6513 't' like 'T', but with the EQ/NE cases reversed
6514 'Y' for a CONST_INT X, print mips_fp_conditions[X]
6515 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
6516 'R' print the reloc associated with LO_SUM
6517 'q' print DSP accumulator registers
6519 The punctuation characters are:
6521 '(' Turn on .set noreorder
6522 ')' Turn on .set reorder
6523 '[' Turn on .set noat
6524 ']' Turn on .set at
6525 '<' Turn on .set nomacro
6526 '>' Turn on .set macro
6527 '{' Turn on .set volatile (not GAS)
6528 '}' Turn on .set novolatile (not GAS)
6529 '&' Turn on .set noreorder if filling delay slots
6530 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
6531 '!' Turn on .set nomacro if filling delay slots
6532 '#' Print nop if in a .set noreorder section.
6533 '/' Like '#', but does nothing within a delayed branch sequence
6534 '?' Print 'l' if we are to use a branch likely instead of normal branch.
6535 '@' Print the name of the assembler temporary register (at or $1).
6536 '.' Print the name of the register with a hard-wired zero (zero or $0).
6537 '^' Print the name of the pic call-through register (t9 or $25).
6538 '$' Print the name of the stack pointer register (sp or $29).
6539 '+' Print the name of the gp register (usually gp or $28).
6540 '~' Output a branch alignment to LABEL_ALIGN(NULL).
6541 '|' Print .set push; .set mips2 if mips_llsc == LLSC_YES
6542 && !ISA_HAS_LL_SC.
6543 '-' Print .set pop under the same conditions for '|'. */
6545 void
6547 {
6551 {
6553 {
6586 {
6592 }
6606 /* Print an extra newline so that the delayed insn is separated
6607 from the following ones. This looks neater and is consistent
6608 with non-nop delayed sequences. */
6667 {
6670 }
6686 }
6689 }
6692 {
6695 }
6701 {
6714 }
6718 {
6731 }
6735 {
6740 }
6744 {
6749 }
6752 {
6757 }
6763 {
6768 else
6770 }
6773 {
6775 {
6778 }
6779 }
6782 {
6793 else
6795 }
6798 {
6803 else
6809 regnum++;
6812 }
6815 {
6818 else
6820 }
6838 {
6841 }
6846 else
6848 }
6851 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6852 in context CONTEXT. RELOCS is the array of relocations to use. */
6854 static void
6857 {
6870 }
6871 \f
6872 /* Output address operand X to FILE. */
6874 void
6876 {
6881 {
6889 mips_lo_relocs);
6901 }
6903 }
6904 \f
6905 /* When using assembler macros, keep track of all of small-data externs
6906 so that mips_file_end can emit the appropriate declarations for them.
6908 In most cases it would be safe (though pointless) to emit .externs
6909 for other symbols too. One exception is when an object is within
6910 the -G limit but declared by the user to be in a section other
6911 than .sbss or .sdata. */
6913 void
6915 {
6918 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6919 set in order to avoid putting out names that are never really
6920 used. */
6922 {
6924 {
6929 }
6933 {
6934 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6935 `.global name .text' directive for every used but
6936 undefined function. If we don't, the linker may perform
6937 an optimization (skipping over the insns that set $gp)
6938 when it is unsafe. */
6942 }
6943 }
6944 }
6945 \f
6946 /* Emit a new filename to a stream. If we are smuggling stabs, try to
6947 put out a MIPS ECOFF file and a stab. */
6949 void
6951 {
6953 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6954 directives. */
6958 {
6965 }
6967 /* If we are emitting stabs, let dbxout.c handle this (except for
6968 the mips_output_filename_first_time case). */
6974 {
6980 }
6981 }
6982 \f
6983 /* Output an ASCII string, in a space-saving way. PREFIX is the string
6984 that should be written before the opening quote, such as "\t.ascii\t"
6985 for real string data or "\t# " for a comment. */
6987 void
6990 {
6998 {
7002 {
7004 {
7006 cur_pos++;
7007 }
7009 cur_pos++;
7010 }
7011 else
7012 {
7015 }
7018 {
7021 }
7022 }
7024 }
7025 \f
7026 /* Implement TARGET_ASM_FILE_START. */
7028 static void
7030 {
7034 {
7035 /* Generate a special section to describe the ABI switches used to
7036 produce the resultant binary. This used to be done by the assembler
7037 setting bits in the ELF header's flags field, but we have run out of
7038 bits. GDB needs this information in order to be able to correctly
7039 debug these binaries. See the function mips_gdbarch_init() in
7040 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
7041 causes unnecessary IRIX 6 ld warnings. */
7045 {
7053 }
7054 /* Note - we use fprintf directly rather than calling switch_to_section
7055 because in this way we can avoid creating an allocated section. We
7056 do not want this section to take up any space in the running
7057 executable. */
7060 /* There is no ELF header flag to distinguish long32 forms of the
7061 EABI from long64 forms. Emit a special section to help tools
7062 such as GDB. Do the same for o64, which is sometimes used with
7063 -mlong64. */
7068 /* Restore the default section. */
7071 #ifdef HAVE_AS_GNU_ATTRIBUTE
7074 #endif
7075 }
7077 /* Generate the pseudo ops that System V.4 wants. */
7083 ASM_COMMENT_START,
7085 }
7087 #ifdef BSS_SECTION_ASM_OP
7088 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
7089 in the use of sbss. */
7091 void
7094 {
7099 else
7105 }
7106 #endif
7107 \f
7108 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7109 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7111 void
7115 {
7116 /* If the target wants uninitialized const declarations in
7117 .rdata then don't put them in .comm. */
7121 {
7129 size);
7130 }
7131 else
7134 }
7136 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7137 NAME is the name of the object and ALIGN is the required alignment
7138 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7139 alignment argument. */
7141 void
7146 {
7148 {
7153 }
7154 else
7158 }
7160 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7161 macros, mark the symbol as written so that mips_file_end won't emit an
7162 .extern for it. STREAM is the output file, NAME is the name of the
7163 symbol, INIT_STRING is the string that should be written before the
7164 symbol and FINAL_STRING is the string that should be written after it.
7165 FINAL_STRING is a printf() format that consumes the remaining arguments. */
7167 void
7170 {
7180 {
7183 }
7184 }
7186 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7189 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7190 definitions except that it uses mips_declare_object() to emit the label. */
7192 void
7194 tree decl ATTRIBUTE_UNUSED)
7195 {
7196 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7198 #endif
7202 {
7203 HOST_WIDE_INT size;
7208 }
7211 }
7213 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7215 void
7217 {
7226 {
7227 HOST_WIDE_INT size;
7232 }
7233 }
7234 #endif
7235 \f
7236 /* Return true if X in context CONTEXT is a small data address that can
7237 be rewritten as a LO_SUM. */
7239 static bool
7241 {
7247 }
7250 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
7251 containing MEM, or null if none. */
7253 static int
7255 {
7262 {
7266 }
7270 }
7272 /* Return true if OP refers to small data symbols directly, not through
7273 a LO_SUM. */
7275 bool
7277 {
7279 }
7280 \f
7281 /* A for_each_rtx callback, used by mips_rewrite_small_data.
7282 DATA is the containing MEM, or null if none. */
7284 static int
7286 {
7290 {
7293 }
7303 }
7305 /* If possible, rewrite OP so that it refers to small data using
7306 explicit relocations. */
7308 rtx
7310 {
7314 }
7315 \f
7316 /* Return true if the current function has an insn that implicitly
7317 refers to $gp. */
7319 static bool
7321 {
7322 /* Don't bother rechecking if we found one last time. */
7324 {
7325 rtx insn;
7338 }
7340 }
7343 /* Return the register that should be used as the global pointer
7344 within this function. Return 0 if the function doesn't need
7345 a global pointer. */
7347 static unsigned int
7349 {
7352 /* $gp is always available unless we're using a GOT. */
7356 /* We must always provide $gp when it is used implicitly. */
7360 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7361 a valid gp. */
7365 /* If the function has a nonlocal goto, $gp must hold the correct
7366 global pointer for the target function. */
7370 /* If the gp is never referenced, there's no need to initialize it.
7371 Note that reload can sometimes introduce constant pool references
7372 into a function that otherwise didn't need them. For example,
7373 suppose we have an instruction like:
7375 (set (reg:DF R1) (float:DF (reg:SI R2)))
7377 If R2 turns out to be constant such as 1, the instruction may have a
7378 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7379 using this constant if R2 doesn't get allocated to a register.
7381 In cases like these, reload will have added the constant to the pool
7382 but no instruction will yet refer to it. */
7384 && !current_function_uses_const_pool
7388 /* We need a global pointer, but perhaps we can use a call-clobbered
7389 register instead of $gp. */
7399 }
7402 /* Return true if the function return value MODE will get returned in a
7403 floating-point register. */
7405 static bool
7407 {
7412 }
7414 /* Return a two-character string representing a function floating-point
7415 return mode, used to name MIPS16 function stubs. */
7419 {
7430 else
7432 }
7434 /* Return true if the current function returns its value in a floating-point
7435 register in MIPS16 mode. */
7437 static bool
7439 {
7442 && TARGET_HARD_FLOAT_ABI
7445 }
7448 /* Return true if the current function must save REGNO. */
7450 static bool
7452 {
7453 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7454 if we have not chosen a call-clobbered substitute. */
7458 /* Check call-saved registers. */
7463 /* Save both registers in an FPR pair if either one is used. This is
7464 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7465 register to be used without the even register. */
7472 /* We need to save the old frame pointer before setting up a new one. */
7476 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7480 /* We need to save the incoming return address if it is ever clobbered
7481 within the function, if __builtin_eh_return is being used to set a
7482 different return address, or if a stub is being used to return a
7483 value in FPRs. */
7486 || current_function_calls_eh_return
7491 }
7493 /* Return the index of the lowest X in the range [0, SIZE) for which
7494 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7496 static unsigned int
7499 {
7507 }
7509 /* *MASK_PTR is a mask of general purpose registers and *GP_REG_SIZE_PTR
7510 is the number of bytes that they occupy. If *MASK_PTR contains REGS[X]
7511 for some X in [0, SIZE), adjust *MASK_PTR and *GP_REG_SIZE_PTR so that
7512 the same is true for all indexes (X, SIZE). */
7514 static void
7517 {
7523 {
7526 }
7527 }
7529 /* Return the bytes needed to compute the frame pointer from the current
7530 stack pointer. SIZE is the size (in bytes) of the local variables.
7532 MIPS stack frames look like:
7534 Before call After call
7535 high +-----------------------+ +-----------------------+
7536 mem. | | | |
7537 | caller's temps. | | caller's temps. |
7538 | | | |
7539 +-----------------------+ +-----------------------+
7540 | | | |
7541 | arguments on stack. | | arguments on stack. |
7542 | | | |
7543 +-----------------------+ +-----------------------+
7544 | 4 words to save | | 4 words to save |
7545 | arguments passed | | arguments passed |
7546 | in registers, even | | in registers, even |
7547 | if not passed. | | if not passed. |
7548 SP->+-----------------------+ VFP->+-----------------------+
7549 (VFP = SP+fp_sp_offset) | |\
7550 | fp register save | | fp_reg_size
7551 | |/
7552 SP+gp_sp_offset->+-----------------------+
7553 /| |\
7554 | | gp register save | | gp_reg_size
7555 gp_reg_rounded | | |/
7556 | +-----------------------+
7557 \| alignment padding |
7558 +-----------------------+
7559 | |\
7560 | local variables | | var_size
7561 | |/
7562 +-----------------------+
7563 | |
7564 | alloca allocations |
7565 | |
7566 +-----------------------+
7567 /| |
7568 cprestore_size | | GP save for V.4 abi |
7569 \| |
7570 +-----------------------+
7571 | |\
7572 | arguments on stack | |
7573 | | |
7574 +-----------------------+ |
7575 | 4 words to save | | args_size
7576 | arguments passed | |
7577 | in registers, even | |
7578 | if not passed. | |
7579 low | (TARGET_OLDABI only) |/
7580 memory SP->+-----------------------+
7582 */
7584 HOST_WIDE_INT
7586 {
7608 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
7609 functions. If the function has local variables, we're committed
7610 to allocating it anyway. Otherwise reclaim it here. */
7614 /* The MIPS 3.0 linker does not like functions that dynamically
7615 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
7616 looks like we are trying to create a second frame pointer to the
7617 function, so allocate some stack space to make it happy. */
7624 /* Calculate space needed for gp registers. */
7627 {
7630 }
7632 /* We need to restore these for the handler. */
7634 {
7637 {
7643 }
7644 }
7646 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
7647 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
7648 save all later registers too. */
7650 {
7655 }
7657 /* This loop must iterate over the same space as its companion in
7658 mips_for_each_saved_reg. */
7664 {
7667 }
7672 /* Add in the space required for saving incoming register arguments. */
7676 /* Save other computed information. */
7691 {
7692 HOST_WIDE_INT offset;
7695 /* MIPS16e SAVE and RESTORE instructions require the GP save area
7696 to be aligned at the high end with any padding at the low end.
7697 It is only safe to use this calculation for o32, where we never
7698 have pretend arguments, and where any varargs will be saved in
7699 the caller-allocated area rather than at the top of the frame. */
7701 else
7706 }
7707 else
7708 {
7711 }
7714 {
7715 HOST_WIDE_INT offset;
7722 }
7723 else
7724 {
7727 }
7729 /* Ok, we're done. */
7731 }
7732 \f
7733 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
7734 pointer or argument pointer. TO is either the stack pointer or
7735 hard frame pointer. */
7737 HOST_WIDE_INT
7739 {
7740 HOST_WIDE_INT offset;
7744 /* Set OFFSET to the offset from the stack pointer. */
7746 {
7758 }
7764 }
7765 \f
7766 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
7767 back to a previous frame. */
7768 rtx
7770 {
7775 }
7776 \f
7777 /* Use FN to save or restore register REGNO. MODE is the register's
7778 mode and OFFSET is the offset of its save slot from the current
7779 stack pointer. */
7781 static void
7784 {
7785 rtx mem;
7790 }
7793 /* Call FN for each register that is saved by the current function.
7794 SP_OFFSET is the offset of the current stack pointer from the start
7795 of the frame. */
7797 static void
7799 {
7801 HOST_WIDE_INT offset;
7804 /* Save registers starting from high to low. The debuggers prefer at least
7805 the return register be stored at func+4, and also it allows us not to
7806 need a nop in the epilogue if at least one register is reloaded in
7807 addition to return address. */
7811 {
7814 }
7816 /* This loop must iterate over the same space as its companion in
7817 compute_frame_size. */
7824 {
7827 }
7828 }
7829 \f
7830 /* If we're generating n32 or n64 abicalls, and the current function
7831 does not use $28 as its global pointer, emit a cplocal directive.
7832 Use pic_offset_table_rtx as the argument to the directive. */
7834 static void
7836 {
7841 }
7843 /* Return the style of GP load sequence that is being used for the
7844 current function. */
7846 enum mips_loadgp_style
7848 {
7859 }
7861 /* The __gnu_local_gp symbol. */
7865 /* If we're generating n32 or n64 abicalls, emit instructions
7866 to set up the global pointer. */
7868 static void
7870 {
7874 {
7877 {
7880 }
7903 }
7904 }
7906 /* Set up the stack and frame (if desired) for the function. */
7908 static void
7910 {
7914 #ifdef SDB_DEBUGGING_INFO
7917 #endif
7919 /* In mips16 mode, we may need to generate a 32 bit to handle
7920 floating point arguments. The linker will arrange for any 32-bit
7921 functions to call this stub, which will then jump to the 16-bit
7922 function proper. */
7924 && TARGET_HARD_FLOAT_ABI
7928 /* Select the mips16 mode for this function. */
7931 else
7935 {
7936 /* Get the function name the same way that toplev.c does before calling
7937 assemble_start_function. This is needed so that the name used here
7938 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7942 {
7946 }
7950 }
7952 /* Stop mips_file_end from treating this function as external. */
7957 {
7958 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7962 ", args= " HOST_WIDE_INT_PRINT_DEC
7976 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7984 /* Require:
7985 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7986 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7987 }
7990 {
7991 /* Handle the initialization of $gp for SVR4 PIC. */
7994 else
7996 }
8000 /* Tell the assembler which register we're using as the global
8001 pointer. This is needed for thunks, since they can use either
8002 explicit relocs or assembler macros. */
8004 }
8005 \f
8006 /* Make the last instruction frame related and note that it performs
8007 the operation described by FRAME_PATTERN. */
8009 static void
8011 {
8012 rtx insn;
8017 frame_pattern,
8019 }
8022 /* Return a frame-related rtx that stores REG at MEM.
8023 REG must be a single register. */
8025 static rtx
8027 {
8028 rtx set;
8030 /* If we're saving the return address register and the dwarf return
8031 address column differs from the hard register number, adjust the
8032 note reg to refer to the former. */
8041 }
8044 /* Save register REG to MEM. Make the instruction frame-related. */
8046 static void
8048 {
8050 {
8055 else
8061 }
8062 else
8063 {
8067 {
8068 /* Save a non-mips16 register by moving it through a temporary.
8069 We don't need to do this for $31 since there's a special
8070 instruction for it. */
8073 }
8074 else
8078 }
8079 }
8081 /* Return a move between register REGNO and memory location SP + OFFSET.
8082 Make the move a load if RESTORE_P, otherwise make it a frame-related
8083 store. */
8085 static rtx
8088 {
8096 }
8098 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8099 The instruction must:
8101 - Allocate or deallocate SIZE bytes in total; SIZE is known
8102 to be nonzero.
8104 - Save or restore as many registers in *MASK_PTR as possible.
8105 The instruction saves the first registers at the top of the
8106 allocated area, with the other registers below it.
8108 - Save NARGS argument registers above the allocated area.
8110 (NARGS is always zero if RESTORE_P.)
8112 The SAVE and RESTORE instructions cannot save and restore all general
8113 registers, so there may be some registers left over for the caller to
8114 handle. Destructively modify *MASK_PTR so that it contains the registers
8115 that still need to be saved or restored. The caller can save these
8116 registers in the memory immediately below *OFFSET_PTR, which is a
8117 byte offset from the bottom of the allocated stack area. */
8119 static rtx
8122 HOST_WIDE_INT size)
8123 {
8131 /* Calculate the number of elements in the PARALLEL. We need one element
8132 for the stack adjustment, one for each argument register save, and one
8133 for each additional register move. */
8137 n++;
8139 /* Create the final PARALLEL. */
8143 /* Add the stack pointer adjustment. */
8150 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8153 /* Save the arguments. */
8155 {
8159 }
8161 /* Then fill in the other register moves. */
8164 {
8167 {
8172 }
8173 }
8175 /* Tell the caller what offset it should use for the remaining registers. */
8181 }
8183 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8184 pointer. Return true if PATTERN matches the kind of instruction
8185 generated by mips16e_build_save_restore. If INFO is nonnull,
8186 initialize it when returning true. */
8188 bool
8191 {
8200 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8203 /* Interpret all other members of the PARALLEL. */
8209 {
8210 /* Check that we have a SET. */
8215 /* Check that the SET is a load (if restoring) or a store
8216 (if saving). */
8221 /* Check that the address is the sum of the stack pointer and a
8222 possibly-zero constant offset. */
8227 /* Check that SET's other operand is a register. */
8232 /* Check for argument saves. */
8235 nargs++;
8237 {
8244 }
8245 else
8247 }
8249 /* Check that the restrictions on register ranges are met. */
8258 /* Make sure that the topmost argument register is not saved twice.
8259 The checks above ensure that the same is then true for the other
8260 argument registers. */
8264 /* Pass back information, if requested. */
8266 {
8270 }
8273 }
8275 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8276 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8277 the null terminator. */
8282 {
8285 else
8288 }
8290 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8291 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8295 {
8302 /* Parse the pattern. */
8306 /* Add the mnemonic. */
8310 /* Save the arguments. */
8317 /* Emit the amount of stack space to allocate or deallocate. */
8320 /* Save or restore $16. */
8324 /* Save or restore $17. */
8328 /* Save or restore registers in the range $s2...$s8, which
8329 mips16e_s2_s8_regs lists in decreasing order. Note that this
8330 is a software register range; the hardware registers are not
8331 numbered consecutively. */
8338 /* Save or restore registers in the range $a0...$a3. */
8345 /* Save or restore $31. */
8350 }
8352 /* Return a simplified form of X using the register values in REG_VALUES.
8353 REG_VALUES[R] is the last value assigned to hard register R, or null
8354 if R has not been modified.
8356 This function is rather limited, but is good enough for our purposes. */
8358 static rtx
8360 {
8366 {
8370 }
8373 {
8377 }
8385 }
8387 /* Return true if (set DEST SRC) stores an argument register into its
8388 caller-allocated save slot, storing the number of that argument
8389 register in *REGNO_PTR if so. REG_VALUES is as for
8390 mips16e_collect_propagate_value. */
8392 static bool
8395 {
8400 /* Check that this is a word-mode store. */
8404 /* Check that the register being saved is an unmodified argument
8405 register. */
8411 /* Check whether the address is an appropriate stack pointer or
8412 frame pointer access. The frame pointer is offset from the
8413 stack pointer by the size of the outgoing arguments. */
8426 }
8428 /* A subroutine of mips_expand_prologue, called only when generating
8429 MIPS16e SAVE instructions. Search the start of the function for any
8430 instructions that save argument registers into their caller-allocated
8431 save slots. Delete such instructions and return a value N such that
8432 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8433 instructions redundant. */
8435 static unsigned int
8437 {
8446 {
8461 {
8463 {
8466 }
8467 }
8471 else
8473 }
8477 }
8479 /* Expand the prologue into a bunch of separate insns. */
8481 void
8483 {
8484 HOST_WIDE_INT size;
8486 rtx insn;
8493 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8494 bytes beforehand; this is enough to cover the register save area
8495 without going out of range. */
8497 {
8498 HOST_WIDE_INT step1;
8503 {
8504 HOST_WIDE_INT offset;
8507 /* Try to merge argument stores into the save instruction. */
8510 /* Build the save instruction. */
8517 /* Check if we need to save other registers. */
8520 {
8523 }
8524 }
8525 else
8526 {
8528 stack_pointer_rtx,
8533 }
8534 }
8536 /* Allocate the rest of the frame. */
8538 {
8541 stack_pointer_rtx,
8543 else
8544 {
8547 {
8548 /* There are no instructions to add or subtract registers
8549 from the stack pointer, so use the frame pointer as a
8550 temporary. We should always be using a frame pointer
8551 in this case anyway. */
8555 hard_frame_pointer_rtx,
8558 }
8559 else
8561 stack_pointer_rtx,
8564 /* Describe the combined effect of the previous instructions. */
8565 mips_set_frame_expr
8568 }
8569 }
8571 /* Set up the frame pointer, if we're using one. In mips16 code,
8572 we point the frame pointer ahead of the outgoing argument area.
8573 This should allow more variables & incoming arguments to be
8574 accessed with unextended instructions. */
8576 {
8578 {
8581 RTX_FRAME_RELATED_P
8583 stack_pointer_rtx,
8585 else
8586 {
8590 hard_frame_pointer_rtx,
8592 mips_set_frame_expr
8596 }
8597 }
8598 else
8601 }
8605 /* If generating o32/o64 abicalls, save $gp on the stack. */
8609 /* If we are profiling, make sure no instructions are scheduled before
8610 the call to mcount. */
8614 }
8615 \f
8616 /* Do any necessary cleanup after a function to restore stack, frame,
8617 and regs. */
8621 static void
8623 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8624 {
8625 /* Reinstate the normal $gp. */
8630 {
8631 /* Avoid using %>%) since it adds excess whitespace. */
8635 }
8638 {
8641 /* Get the function name the same way that toplev.c does before calling
8642 assemble_start_function. This is needed so that the name used here
8643 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8648 }
8649 }
8650 \f
8651 /* Emit instructions to restore register REG from slot MEM. */
8653 static void
8655 {
8656 /* There's no mips16 instruction to load $31 directly. Load into
8657 $7 instead and adjust the return insn appropriately. */
8662 {
8663 /* Can't restore directly; move through a temporary. */
8666 }
8667 else
8669 }
8672 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
8673 if this epilogue precedes a sibling call, false if it is for a normal
8674 "epilogue" pattern. */
8676 void
8678 {
8683 {
8686 }
8688 /* In mips16 mode, if the return value should go into a floating-point
8689 register, we need to call a helper routine to copy it over. */
8691 {
8693 rtx func;
8694 rtx insn;
8695 rtx retval;
8696 rtx call;
8697 tree id;
8698 tree return_type;
8706 NULL));
8713 }
8715 /* Split the frame into two. STEP1 is the amount of stack we should
8716 deallocate before restoring the registers. STEP2 is the amount we
8717 should deallocate afterwards.
8719 Start off by assuming that no registers need to be restored. */
8723 /* Work out which register holds the frame address. Account for the
8724 frame pointer offset used by mips16 code. */
8727 else
8728 {
8732 }
8734 /* If we need to restore registers, deallocate as much stack as
8735 possible in the second step without going out of range. */
8737 {
8740 }
8742 /* Set TARGET to BASE + STEP1. */
8745 {
8746 rtx adjust;
8748 /* Get an rtx for STEP1 that we can add to BASE. */
8751 {
8754 }
8756 /* Normal mode code can copy the result straight into $sp. */
8761 }
8763 /* Copy TARGET into the stack pointer. */
8767 /* If we're using addressing macros, $gp is implicitly used by all
8768 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8769 from the stack. */
8774 {
8776 HOST_WIDE_INT offset;
8777 rtx restore;
8779 /* Generate the restore instruction. */
8783 /* Restore any other registers manually. */
8786 {
8789 }
8791 /* Restore the remaining registers and deallocate the final bit
8792 of the frame. */
8794 }
8795 else
8796 {
8797 /* Restore the registers. */
8799 mips_restore_reg);
8801 /* Deallocate the final bit of the frame. */
8804 stack_pointer_rtx,
8806 }
8808 /* Add in the __builtin_eh_return stack adjustment. We need to
8809 use a temporary in mips16 code. */
8811 {
8813 {
8817 EH_RETURN_STACKADJ_RTX));
8819 }
8820 else
8822 stack_pointer_rtx,
8823 EH_RETURN_STACKADJ_RTX));
8824 }
8827 {
8828 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8829 path will restore the return address into $7 rather than $31. */
8831 && !GENERATE_MIPS16E_SAVE_RESTORE
8835 else
8838 }
8839 }
8840 \f
8841 /* Return nonzero if this function is known to have a null epilogue.
8842 This allows the optimizer to omit jumps to jumps if no stack
8843 was created. */
8845 int
8847 {
8854 /* In mips16 mode, a function that returns a floating point value
8855 needs to arrange to copy the return value into the floating point
8856 registers. */
8864 }
8865 \f
8866 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
8867 in order to avoid duplicating too much logic from elsewhere. */
8869 static void
8872 tree function)
8873 {
8877 /* Pretend to be a post-reload pass while generating rtl. */
8880 /* Mark the end of the (empty) prologue. */
8883 /* Determine if we can use a sibcall to call FUNCTION directly. */
8888 /* Determine if we need to load FNADDR from the GOT. */
8891 {
8894 /* Pick a global pointer. Use a call-clobbered register if
8895 TARGET_CALL_SAVED_GP. */
8900 /* Set up the global pointer for n32 or n64 abicalls. */
8906 }
8908 /* We need two temporary registers in some cases. */
8912 /* Find out which register contains the "this" pointer. */
8915 else
8918 /* Add DELTA to THIS. */
8920 {
8923 {
8926 }
8928 }
8930 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
8932 {
8933 rtx addr;
8935 /* Set TEMP1 to *THIS. */
8938 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
8941 /* Load the offset and add it to THIS. */
8944 }
8946 /* Jump to the target function. Use a sibcall if direct jumps are
8947 allowed, otherwise load the address into a register first. */
8949 {
8952 }
8953 else
8954 {
8955 /* This is messy. gas treats "la $25,foo" as part of a call
8956 sequence and may allow a global "foo" to be lazily bound.
8957 The general move patterns therefore reject this combination.
8959 In this context, lazy binding would actually be OK
8960 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
8961 TARGET_CALL_SAVED_GP; see mips_load_call_address.
8962 We must therefore load the address via a temporary
8963 register if mips_dangerous_for_la25_p.
8965 If we jump to the temporary register rather than $25, the assembler
8966 can use the move insn to fill the jump's delay slot. */
8976 }
8978 /* Run just enough of rest_of_compilation. This sequence was
8979 "borrowed" from alpha.c. */
8989 /* Clean up the vars set above. Note that final_end_function resets
8990 the global pointer for us. */
8992 }
8993 \f
8994 /* Implement TARGET_SELECT_RTX_SECTION. */
8999 {
9000 /* ??? Consider using mergeable small data sections. */
9005 }
9007 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
9009 The complication here is that, with the combination TARGET_ABICALLS
9010 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
9011 therefore not be included in the read-only part of a DSO. Handle such
9012 cases by selecting a normal data section instead of a read-only one.
9013 The logic apes that in default_function_rodata_section. */
9017 {
9022 {
9025 {
9029 }
9032 {
9036 }
9037 }
9039 }
9041 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
9042 locally-defined objects go in a small data section. It also controls
9043 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
9044 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
9046 static bool
9048 {
9049 HOST_WIDE_INT size;
9054 /* We don't yet generate small-data references for -mabicalls or
9055 VxWorks RTP code. See the related -G handling in override_options. */
9060 {
9063 /* Reject anything that isn't in a known small-data section. */
9068 /* If a symbol is defined externally, the assembler will use the
9069 usual -G rules when deciding how to implement macros. */
9072 }
9074 {
9075 /* Don't put constants into the small data section: we want them
9076 to be in ROM rather than RAM. */
9084 }
9086 /* Enforce -mlocal-sdata. */
9090 /* Enforce -mextern-sdata. */
9092 {
9097 }
9101 }
9103 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
9104 anchors for small data: the GP register acts as an anchor in that
9105 case. We also don't want to use them for PC-relative accesses,
9106 where the PC acts as an anchor. */
9108 static bool
9110 {
9112 {
9119 }
9120 }
9121 \f
9122 /* See whether VALTYPE is a record whose fields should be returned in
9123 floating-point registers. If so, return the number of fields and
9124 list them in FIELDS (which should have two elements). Return 0
9125 otherwise.
9127 For n32 & n64, a structure with one or two fields is returned in
9128 floating-point registers as long as every field has a floating-point
9129 type. */
9131 static int
9133 {
9134 tree field;
9145 {
9156 }
9158 }
9161 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
9162 a value in the most significant part of $2/$3 if:
9164 - the target is big-endian;
9166 - the value has a structure or union type (we generalize this to
9167 cover aggregates from other languages too); and
9169 - the structure is not returned in floating-point registers. */
9171 static bool
9173 {
9177 && TARGET_BIG_ENDIAN
9180 }
9183 /* Return a composite value in a pair of floating-point registers.
9184 MODE1 and OFFSET1 are the mode and byte offset for the first value,
9185 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
9186 complete value.
9188 For n32 & n64, $f0 always holds the first value and $f2 the second.
9189 Otherwise the values are packed together as closely as possible. */
9191 static rtx
9195 {
9199 return gen_rtx_PARALLEL
9209 }
9212 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
9213 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
9214 VALTYPE is null and MODE is the mode of the return value. */
9216 rtx
9219 {
9221 {
9228 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
9229 true, we must promote the mode just as PROMOTE_MODE does. */
9232 /* Handle structures whose fields are returned in $f0/$f2. */
9234 {
9244 }
9246 /* If a value is passed in the most significant part of a register, see
9247 whether we have to round the mode up to a whole number of words. */
9249 {
9252 {
9255 }
9256 }
9258 /* For EABI, the class of return register depends entirely on MODE.
9259 For example, "struct { some_type x; }" and "union { some_type x; }"
9260 are returned in the same way as a bare "some_type" would be.
9261 Other ABIs only use FPRs for scalar, complex or vector types. */
9264 }
9267 {
9268 /* Handle long doubles for n32 & n64. */
9275 {
9281 else
9283 }
9284 }
9287 }
9289 /* Return nonzero when an argument must be passed by reference. */
9291 static bool
9295 {
9297 {
9300 /* ??? How should SCmode be handled? */
9308 }
9309 else
9310 {
9311 /* If we have a variable-sized parameter, we have no choice. */
9313 }
9314 }
9316 static bool
9320 {
9322 }
9324 /* Return true if registers of class CLASS cannot change from mode FROM
9325 to mode TO. */
9327 bool
9330 {
9333 {
9335 {
9336 /* When a multi-word value is stored in paired floating-point
9337 registers, the first register always holds the low word.
9338 We therefore can't allow FPRs to change between single-word
9339 and multi-word modes. */
9342 }
9343 }
9345 /* gcc assumes that each word of a multiword register can be accessed
9346 individually using SUBREGs. This is not true for floating-point
9347 registers if they are bigger than a word. */
9354 /* Loading a 32-bit value into a 64-bit floating-point register
9355 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
9356 We can't allow 64-bit float registers to change from SImode to
9357 to a wider mode. */
9359 && TARGET_FLOAT64
9366 }
9368 /* Return true if X should not be moved directly into register $25.
9369 We need this because many versions of GAS will treat "la $25,foo" as
9370 part of a call sequence and so allow a global "foo" to be lazily bound. */
9372 bool
9374 {
9376 && TARGET_USE_GOT
9379 }
9381 /* Implement PREFERRED_RELOAD_CLASS. */
9383 enum reg_class
9385 {
9401 }
9403 /* This function returns the register class required for a secondary
9404 register when copying between one of the registers in CLASS, and X,
9405 using MODE. If IN_P is nonzero, the copy is going from X to the
9406 register, otherwise the register is the source. A return value of
9407 NO_REGS means that no secondary register is required. */
9409 enum reg_class
9412 {
9423 {
9427 }
9429 /* Copying from HI or LO to anywhere other than a general register
9430 requires a general register.
9431 This rule applies to both the original HI/LO pair and the new
9432 DSP accumulators. */
9434 {
9436 {
9437 /* We can't really copy to HI or LO at all in mips16 mode. */
9439 }
9441 }
9443 {
9445 {
9446 /* We can't really copy to HI or LO at all in mips16 mode. */
9448 }
9450 }
9452 /* We can only copy a value to a condition code register from a
9453 floating point register, and even then we require a scratch
9454 floating point register. We can only copy a value out of a
9455 condition code register into a general register. */
9457 {
9461 }
9463 {
9467 }
9470 {
9472 {
9473 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
9475 }
9477 {
9478 /* We can use the l.s and l.d macros to load floating-point
9479 constants. ??? For l.s, we could probably get better
9480 code by returning GR_REGS here. */
9482 }
9484 {
9485 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9487 }
9489 {
9490 /* In this case we can use mov.s or mov.d. */
9492 }
9493 else
9494 {
9495 /* Otherwise, we need to reload through an integer register. */
9497 }
9498 }
9500 /* In mips16 mode, going between memory and anything but M16_REGS
9501 requires an M16_REG. */
9503 {
9505 {
9509 }
9511 {
9515 }
9516 }
9519 }
9521 /* Implement CLASS_MAX_NREGS.
9523 - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
9525 - ST_REGS are always hold CCmode values, and CCmode values are
9526 considered to be 4 bytes wide.
9528 All other register classes are covered by UNITS_PER_WORD. Note that
9529 this is true even for unions of integer and float registers when the
9530 latter are smaller than the former. The only supported combination
9531 in which case this occurs is -mgp64 -msingle-float, which has 64-bit
9532 words but 32-bit float registers. A word-based calculation is correct
9533 in that case since -msingle-float disallows multi-FPR values. */
9535 int
9538 {
9543 else
9545 }
9547 static bool
9549 {
9551 }
9553 /* Target hook for vector_mode_supported_p. */
9555 static bool
9557 {
9559 {
9575 }
9576 }
9578 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9580 static bool
9582 {
9588 }
9589 \f
9590 /* If we can access small data directly (using gp-relative relocation
9591 operators) return the small data pointer, otherwise return null.
9593 For each mips16 function which refers to GP relative symbols, we
9594 use a pseudo register, initialized at the start of the function, to
9595 hold the $gp value. */
9597 static rtx
9599 {
9603 /* Don't initialize the pseudo register if we are being called from
9604 the tree optimizers' cost-calculation routines. */
9607 {
9610 /* We want to initialize this to a value which gcc will believe
9611 is constant. */
9615 /* We need to emit the initialization after the FUNCTION_BEG
9616 note, so that it will be integrated. */
9627 }
9630 }
9632 /* Write out code to move floating point arguments in or out of
9633 general registers. Output the instructions to FILE. FP_CODE is
9634 the code describing which arguments are present (see the comment at
9635 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
9636 we are copying from the floating point registers. */
9638 static void
9640 {
9644 CUMULATIVE_ARGS cum;
9646 /* This code only works for the original 32-bit ABI and the O64 ABI. */
9651 else
9657 {
9665 else
9679 /* -mips32r2 -mfp64 */
9681 s,
9691 else
9697 }
9698 }
9700 /* Build a mips16 function stub. This is used for functions which
9701 take arguments in the floating point registers. It is 32-bit code
9702 that moves the floating point args into the general registers, and
9703 then jumps to the 16-bit code. */
9705 static void
9707 {
9729 {
9734 }
9741 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
9742 within a .ent, and we cannot emit another .ent. */
9744 {
9748 }
9753 /* We don't want the assembler to insert any nops here. */
9765 /* Unfortunately, we can't fill the jump delay slot. We can't fill
9766 with one of the mfc1 instructions, because the result is not
9767 available for one instruction, so if the very first instruction
9768 in the function refers to the register, it will see the wrong
9769 value. */
9775 {
9779 }
9782 }
9784 /* We keep a list of functions for which we have already built stubs
9785 in build_mips16_call_stub. */
9787 struct mips16_stub
9788 {
9792 };
9796 /* Emit code to return a double value from a mips16 stub. GPREG is the
9797 first GP reg to use, FPREG is the first FP reg to use. */
9799 static void
9801 {
9806 {
9813 }
9814 else
9815 {
9817 {
9824 }
9825 else
9826 {
9833 }
9834 }
9835 }
9837 /* Build a call stub for a mips16 call. A stub is needed if we are
9838 passing any floating point values which should go into the floating
9839 point registers. If we are, and the call turns out to be to a
9840 32-bit function, the stub will be used to move the values into the
9841 floating point registers before calling the 32-bit function. The
9842 linker will magically adjust the function call to either the 16-bit
9843 function or the 32-bit stub, depending upon where the function call
9844 is actually defined.
9846 Similarly, we need a stub if the return value might come back in a
9847 floating point register.
9849 RETVAL is the location of the return value, or null if this is
9850 a call rather than a call_value. FN is the address of the
9851 function and ARG_SIZE is the size of the arguments. FP_CODE
9852 is the code built by function_arg. This function returns a nonzero
9853 value if it builds the call instruction itself. */
9855 int
9857 {
9865 rtx insn;
9867 /* We don't need to do anything if we aren't in mips16 mode, or if
9868 we were invoked with the -msoft-float option. */
9872 /* Figure out whether the value might come back in a floating point
9873 register. */
9877 /* We don't need to do anything if there were no floating point
9878 arguments and the value will not be returned in a floating point
9879 register. */
9883 /* We don't need to do anything if this is a call to a special
9884 mips16 support function. */
9889 /* This code will only work for o32 and o64 abis. The other ABI's
9890 require more sophisticated support. */
9893 /* If we're calling via a function pointer, then we must always call
9894 via a stub. There are magic stubs provided in libgcc.a for each
9895 of the required cases. Each of them expects the function address
9896 to arrive in register $2. */
9899 {
9901 tree id;
9904 /* ??? If this code is modified to support other ABI's, we need
9905 to handle PARALLEL return values here. */
9910 fp_code);
9911 else
9913 fp_code);
9922 else
9926 /* Put the register usage information on the CALL. */
9932 /* If we are handling a floating point return value, we need to
9933 save $18 in the function prologue. Putting a note on the
9934 call will mean that df_regs_ever_live_p ($18) will be true if the
9935 call is not eliminated, and we can check that in the prologue
9936 code. */
9944 /* Return 1 to tell the caller that we've generated the call
9945 insn. */
9947 }
9949 /* We know the function we are going to call. If we have already
9950 built a stub, we don't need to do anything further. */
9958 {
9959 /* Build a special purpose stub. When the linker sees a
9960 function call in mips16 code, it will check where the target
9961 is defined. If the target is a 32-bit call, the linker will
9962 search for the section defined here. It can tell which
9963 symbol this section is associated with by looking at the
9964 relocation information (the name is unreliable, since this
9965 might be a static function). If such a section is found, the
9966 linker will redirect the call to the start of the magic
9967 section.
9969 If the function does not return a floating point value, the
9970 special stub section is named
9971 .mips16.call.FNNAME
9973 If the function does return a floating point value, the stub
9974 section is named
9975 .mips16.call.fp.FNNAME
9976 */
9981 fnname);
9985 fnname);
9993 (fpret
9996 fnname);
9999 {
10004 }
10011 {
10018 }
10020 /* We build the stub code by hand. That's the only way we can
10021 do it, since we can't generate 32-bit code during a 16-bit
10022 compilation. */
10024 /* We don't want the assembler to insert any nops here. */
10030 {
10033 fnname);
10036 /* Unfortunately, we can't fill the jump delay slot. We
10037 can't fill with one of the mtc1 instructions, because the
10038 result is not available for one instruction, so if the
10039 very first instruction in the function refers to the
10040 register, it will see the wrong value. */
10042 }
10043 else
10044 {
10048 /* As above, we can't fill the delay slot. */
10054 {
10061 }
10064 {
10066 }
10068 {
10073 }
10074 else
10075 {
10077 {
10084 }
10085 else
10086 {
10093 }
10094 }
10096 /* As above, we can't fill the delay slot. */
10098 }
10102 #ifdef ASM_DECLARE_FUNCTION_SIZE
10104 #endif
10107 {
10111 }
10113 /* Record this stub. */
10119 }
10121 /* If we expect a floating point return value, but we've built a
10122 stub which does not expect one, then we're in trouble. We can't
10123 use the existing stub, because it won't handle the floating point
10124 value. We can't build a new stub, because the linker won't know
10125 which stub to use for the various calls in this object file.
10126 Fortunately, this case is illegal, since it means that a function
10127 was declared in two different ways in a single compilation. */
10133 else
10137 /* If we are calling a stub which handles a floating point return
10138 value, we need to arrange to save $18 in the prologue. We do
10139 this by marking the function call as using the register. The
10140 prologue will later see that it is used, and emit code to save
10141 it. */
10148 /* Return 1 to tell the caller that we've generated the call
10149 insn. */
10151 }
10153 /* An entry in the mips16 constant pool. VALUE is the pool constant,
10154 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
10158 rtx value;
10159 rtx label;
10161 };
10163 /* Information about an incomplete mips16 constant pool. FIRST is the
10164 first constant, HIGHEST_ADDRESS is the highest address that the first
10165 byte of the pool can have, and INSN_ADDRESS is the current instruction
10166 address. */
10172 };
10174 /* Add constant VALUE to POOL and return its label. MODE is the
10175 value's mode (used for CONST_INTs, etc.). */
10177 static rtx
10180 {
10184 /* See whether the constant is already in the pool. If so, return the
10185 existing label, otherwise leave P pointing to the place where the
10186 constant should be added.
10188 Keep the pool sorted in increasing order of mode size so that we can
10189 reduce the number of alignments needed. */
10192 {
10199 }
10201 /* In the worst case, the constant needed by the earliest instruction
10202 will end up at the end of the pool. The entire pool must then be
10203 accessible from that instruction.
10205 When adding the first constant, set the pool's highest address to
10206 the address of the first out-of-range byte. Adjust this address
10207 downwards each time a new constant is added. */
10209 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
10210 is the address of the instruction with the lowest two bits clear.
10211 The base PC value for ld has the lowest three bits clear. Assume
10212 the worst case here. */
10216 /* Take into account the worst possible padding due to alignment. */
10219 /* Create a new entry. */
10228 }
10230 /* Output constant VALUE after instruction INSN and return the last
10231 instruction emitted. MODE is the mode of the constant. */
10233 static rtx
10235 {
10237 {
10239 {
10242 }
10249 {
10255 }
10259 }
10260 }
10263 /* Dump out the constants in CONSTANTS after INSN. */
10265 static void
10267 {
10273 {
10274 /* If necessary, increase the alignment of PC. */
10276 {
10279 }
10287 }
10290 }
10292 /* Return the length of instruction INSN. */
10294 static int
10296 {
10298 {
10304 }
10306 }
10308 /* If *X is a symbolic constant that refers to the constant pool, add
10309 the constant to POOL and rewrite *X to use the constant's label. */
10311 static void
10313 {
10318 {
10323 }
10324 }
10326 /* This structure is used to communicate with mips16_rewrite_pool_refs.
10327 INSN is the instruction we're rewriting and POOL points to the current
10328 constant pool. */
10330 rtx insn;
10332 };
10334 /* Rewrite *X so that constant pool references refer to the constant's
10335 label instead. DATA points to a mips16_rewrite_pool_refs_info
10336 structure. */
10338 static int
10340 {
10344 {
10347 }
10350 {
10353 }
10359 }
10361 /* Build MIPS16 constant pools. */
10363 static void
10365 {
10376 {
10377 /* Rewrite constant pool references in INSN. */
10379 {
10383 }
10388 {
10389 /* If there are no natural barriers between the first user of
10390 the pool and the highest acceptable address, we'll need to
10391 create a new instruction to jump around the constant pool.
10392 In the worst case, this instruction will be 4 bytes long.
10394 If it's too late to do this transformation after INSN,
10395 do it immediately before INSN. */
10397 {
10409 }
10411 /* See whether the constant pool is now out of range of the first
10412 user. If so, output the constants after the previous barrier.
10413 Note that any instructions between BARRIER and INSN (inclusive)
10414 will use negative offsets to refer to the pool. */
10416 {
10420 }
10423 }
10424 }
10426 }
10427 \f
10428 /* A temporary variable used by for_each_rtx callbacks, etc. */
10431 /* A structure representing the state of the processor pipeline.
10432 Used by the mips_sim_* family of functions. */
10434 /* The maximum number of instructions that can be issued in a cycle.
10435 (Caches mips_issue_rate.) */
10438 /* The current simulation time. */
10441 /* How many more instructions can be issued in the current cycle. */
10444 /* LAST_SET[X].INSN is the last instruction to set register X.
10445 LAST_SET[X].TIME is the time at which that instruction was issued.
10446 INSN is null if no instruction has yet set register X. */
10448 rtx insn;
10452 /* The pipeline's current DFA state. */
10453 state_t dfa_state;
10454 };
10456 /* Reset STATE to the initial simulation state. */
10458 static void
10460 {
10465 }
10467 /* Initialize STATE before its first use. DFA_STATE points to an
10468 allocated but uninitialized DFA state. */
10470 static void
10472 {
10476 }
10478 /* Advance STATE by one clock cycle. */
10480 static void
10482 {
10486 }
10488 /* Advance simulation state STATE until instruction INSN can read
10489 register REG. */
10491 static void
10493 {
10498 {
10505 }
10506 }
10508 /* A for_each_rtx callback. If *X is a register, advance simulation state
10509 DATA until mips_sim_insn can read the register's value. */
10511 static int
10513 {
10517 }
10519 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
10521 static void
10523 {
10525 }
10527 /* Advance simulation state STATE until all of INSN's register
10528 dependencies are satisfied. */
10530 static void
10532 {
10535 }
10537 /* Advance simulation state STATE until the units required by
10538 instruction INSN are available. */
10540 static void
10542 {
10543 state_t tmp_state;
10550 }
10552 /* Advance simulation state STATE until INSN is ready to issue. */
10554 static void
10556 {
10559 }
10561 /* mips_sim_insn has just set X. Update the LAST_SET array
10562 in simulation state DATA. */
10564 static void
10566 {
10573 {
10576 }
10577 }
10579 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
10580 can issue immediately (i.e., that mips_sim_wait_insn has already
10581 been called). */
10583 static void
10585 {
10591 }
10593 /* Simulate issuing a NOP in state STATE. */
10595 static void
10597 {
10601 }
10603 /* Update simulation state STATE so that it's ready to accept the instruction
10604 after INSN. INSN should be part of the main rtl chain, not a member of a
10605 SEQUENCE. */
10607 static void
10609 {
10610 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
10615 {
10618 /* We can't predict the processor state after a call or label. */
10623 /* The delay slots of branch likely instructions are only executed
10624 when the branch is taken. Therefore, if the caller has simulated
10625 the delay slot instruction, STATE does not really reflect the state
10626 of the pipeline for the instruction after the delay slot. Also,
10627 branch likely instructions tend to incur a penalty when not taken,
10628 so there will probably be an extra delay between the branch and
10629 the instruction after the delay slot. */
10636 }
10637 }
10638 \f
10639 /* The VR4130 pipeline issues aligned pairs of instructions together,
10640 but it stalls the second instruction if it depends on the first.
10641 In order to cut down the amount of logic required, this dependence
10642 check is not based on a full instruction decode. Instead, any non-SPECIAL
10643 instruction is assumed to modify the register specified by bits 20-16
10644 (which is usually the "rt" field).
10646 In beq, beql, bne and bnel instructions, the rt field is actually an
10647 input, so we can end up with a false dependence between the branch
10648 and its delay slot. If this situation occurs in instruction INSN,
10649 try to avoid it by swapping rs and rt. */
10651 static void
10653 {
10663 {
10664 /* Check for the right kind of condition. */
10671 {
10672 /* SECOND mentions the rt register but not the rs register. */
10676 }
10677 }
10678 }
10680 /* Implement -mvr4130-align. Go through each basic block and simulate the
10681 processor pipeline. If we find that a pair of instructions could execute
10682 in parallel, and the first of those instruction is not 8-byte aligned,
10683 insert a nop to make it aligned. */
10685 static void
10687 {
10694 /* LAST is the last instruction before INSN to have a nonzero length.
10695 LAST2 is the last such instruction before LAST. */
10699 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
10704 {
10709 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
10710 This isn't really related to the alignment pass, but we do it on
10711 the fly to avoid a separate instruction walk. */
10716 {
10719 /* If we want this instruction to issue in parallel with the
10720 previous one, make sure that the previous instruction is
10721 aligned. There are several reasons why this isn't worthwhile
10722 when the second instruction is a call:
10724 - Calls are less likely to be performance critical,
10725 - There's a good chance that the delay slot can execute
10726 in parallel with the call.
10727 - The return address would then be unaligned.
10729 In general, if we're going to insert a nop between instructions
10730 X and Y, it's better to insert it immediately after X. That
10731 way, if the nop makes Y aligned, it will also align any labels
10732 between X and Y. */
10735 {
10737 {
10738 /* SUBINSN is the first instruction in INSN and INSN is
10739 aligned. We want to align the previous instruction
10740 instead, so insert a nop between LAST2 and LAST.
10742 Note that LAST could be either a single instruction
10743 or a branch with a delay slot. In the latter case,
10744 LAST, like INSN, is already aligned, but the delay
10745 slot must have some extra delay that stops it from
10746 issuing at the same time as the branch. We therefore
10747 insert a nop before the branch in order to align its
10748 delay slot. */
10751 }
10753 {
10754 /* SUBINSN is the delay slot of INSN, but INSN is
10755 currently unaligned. Insert a nop between
10756 LAST and INSN to align it. */
10759 }
10760 }
10762 }
10765 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
10768 {
10769 /* If the instruction is an asm statement or multi-instruction
10770 mips.md patern, the length is only an estimate. Insert an
10771 8 byte alignment after it so that the following instructions
10772 can be handled correctly. */
10775 {
10780 }
10785 }
10787 /* See whether INSN is an aligned label. */
10790 }
10792 }
10793 \f
10794 /* Subroutine of mips_reorg. If there is a hazard between INSN
10795 and a previous instruction, avoid it by inserting nops after
10796 instruction AFTER.
10798 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
10799 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
10800 before using the value of that register. *HILO_DELAY counts the
10801 number of instructions since the last hilo hazard (that is,
10802 the number of instructions since the last mflo or mfhi).
10804 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
10805 for the next instruction.
10807 LO_REG is an rtx for the LO register, used in dependence checking. */
10809 static void
10812 {
10821 /* Do not put the whole function in .set noreorder if it contains
10822 an asm statement. We don't know whether there will be hazards
10823 between the asm statement and the gcc-generated code. */
10827 /* Ignore zero-length instructions (barriers and the like). */
10832 /* Work out how many nops are needed. Note that we only care about
10833 registers that are explicitly mentioned in the instruction's pattern.
10834 It doesn't matter that calls use the argument registers or that they
10835 clobber hi and lo. */
10840 else
10843 /* Insert the nops between this instruction and the previous one.
10844 Each new nop takes us further from the last hilo hazard. */
10849 /* Set up the state for the next instruction. */
10854 {
10867 }
10868 }
10871 /* Go through the instruction stream and insert nops where necessary.
10872 See if the whole function can then be put into .set noreorder &
10873 .set nomacro. */
10875 static void
10877 {
10881 /* Force all instructions to be split into their final form. */
10884 /* Recalculate instruction lengths without taking nops into account. */
10890 /* Profiled functions can't be all noreorder because the profiler
10891 support uses assembler macros. */
10895 /* Code compiled with -mfix-vr4120 can't be all noreorder because
10896 we rely on the assembler to work around some errata. */
10900 /* The same is true for -mfix-vr4130 if we might generate mflo or
10901 mfhi instructions. Note that we avoid using mflo and mfhi if
10902 the VR4130 macc and dmacc instructions are available instead;
10903 see the *mfhilo_{si,di}_macc patterns. */
10914 {
10919 else
10924 }
10925 }
10928 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
10930 static void
10932 {
10935 {
10941 }
10942 }
10944 /* This function does three things:
10946 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
10947 - Register the mips16 hardware floating point stubs.
10948 - Register the gofast functions if selected using --enable-gofast. */
10952 static void
10954 {
10956 {
10959 }
10962 {
10981 {
11001 }
11002 }
11003 else
11005 }
11007 /* Return a number assessing the cost of moving a register in class
11008 FROM to class TO. The classes are expressed using the enumeration
11009 values such as `GENERAL_REGS'. A value of 2 is the default; other
11010 values are interpreted relative to that.
11012 It is not required that the cost always equal 2 when FROM is the
11013 same as TO; on some machines it is expensive to move between
11014 registers if they are not general registers.
11016 If reload sees an insn consisting of a single `set' between two
11017 hard registers, and if `REGISTER_MOVE_COST' applied to their
11018 classes returns a value of 2, reload does not check to ensure that
11019 the constraints of the insn are met. Setting a cost of other than
11020 2 will allow reload to verify that the constraints are met. You
11021 should do this if the `movM' pattern's constraints do not allow
11022 such copying.
11024 ??? We make the cost of moving from HI/LO into general
11025 registers the same as for one of moving general registers to
11026 HI/LO for TARGET_MIPS16 in order to prevent allocating a
11027 pseudo to HI/LO. This might hurt optimizations though, it
11028 isn't clear if it is wise. And it might not work in all cases. We
11029 could solve the DImode LO reg problem by using a multiply, just
11030 like reload_{in,out}si. We could solve the SImode/HImode HI reg
11031 problem by using divide instructions. divu puts the remainder in
11032 the HI reg, so doing a divide by -1 will move the value in the HI
11033 reg for all values except -1. We could handle that case by using a
11034 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
11035 a compare/branch to test the input value to see which instruction
11036 we need to use. This gets pretty messy, but it is feasible. */
11038 int
11041 {
11047 {
11053 {
11056 else
11058 }
11062 {
11065 else
11067 }
11069 {
11071 }
11072 }
11074 {
11081 }
11083 {
11085 {
11088 else
11090 }
11091 }
11095 {
11097 }
11099 /* Fall through.
11100 ??? What cases are these? Shouldn't we return 2 here? */
11103 }
11105 /* Return the length of INSN. LENGTH is the initial length computed by
11106 attributes in the machine-description file. */
11108 int
11110 {
11111 /* A unconditional jump has an unfilled delay slot if it is not part
11112 of a sequence. A conditional jump normally has a delay slot, but
11113 does not on MIPS16. */
11117 /* See how many nops might be needed to avoid hardware hazards. */
11120 {
11131 }
11133 /* All MIPS16 instructions are a measly two bytes. */
11138 }
11141 /* Return an asm sequence to start a noat block and load the address
11142 of a label into $1. */
11146 {
11149 {
11160 }
11161 else
11162 {
11165 else
11167 }
11168 }
11170 /* Return the assembly code for INSN, which has the operands given by
11171 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
11172 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
11173 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11174 version of BRANCH_IF_TRUE. */
11180 {
11186 {
11187 /* Just a simple conditional branch. */
11190 }
11192 /* Generate a reversed branch around a direct jump. This fallback does
11193 not use branch-likely instructions. */
11198 /* Generate the reversed branch to NOT_TAKEN. */
11202 /* If INSN has a delay slot, we must provide delay slots for both the
11203 branch to NOT_TAKEN and the conditional jump. We must also ensure
11204 that INSN's delay slot is executed in the appropriate cases. */
11206 {
11207 /* This first delay slot will always be executed, so use INSN's
11208 delay slot if is not annulled. */
11210 {
11214 }
11215 else
11218 }
11220 /* Output the unconditional branch to TAKEN. */
11223 else
11224 {
11227 }
11229 /* Now deal with its delay slot; see above. */
11231 {
11232 /* This delay slot will only be executed if the branch is taken.
11233 Use INSN's delay slot if is annulled. */
11235 {
11239 }
11240 else
11243 }
11245 /* Output NOT_TAKEN. */
11249 }
11251 /* Return the assembly code for INSN, which branches to OPERANDS[1]
11252 if some ordered condition is true. The condition is given by
11253 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
11254 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
11255 its second is always zero. */
11259 {
11262 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
11263 Make BRANCH[0] branch on the inverse condition. */
11265 {
11266 /* These cases are equivalent to comparisons against zero. */
11269 /* Fall through. */
11275 /* These cases are always true or always false. */
11278 /* Fall through. */
11288 }
11290 }
11291 \f
11292 /* Used to output div or ddiv instruction DIVISION, which has the operands
11293 given by OPERANDS. Add in a divide-by-zero check if needed.
11295 When working around R4000 and R4400 errata, we need to make sure that
11296 the division is not immediately followed by a shift[1][2]. We also
11297 need to stop the division from being put into a branch delay slot[3].
11298 The easiest way to avoid both problems is to add a nop after the
11299 division. When a divide-by-zero check is needed, this nop can be
11300 used to fill the branch delay slot.
11302 [1] If a double-word or a variable shift executes immediately
11303 after starting an integer division, the shift may give an
11304 incorrect result. See quotations of errata #16 and #28 from
11305 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11306 in mips.md for details.
11308 [2] A similar bug to [1] exists for all revisions of the
11309 R4000 and the R4400 when run in an MC configuration.
11310 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11312 "19. In this following sequence:
11314 ddiv (or ddivu or div or divu)
11315 dsll32 (or dsrl32, dsra32)
11317 if an MPT stall occurs, while the divide is slipping the cpu
11318 pipeline, then the following double shift would end up with an
11319 incorrect result.
11321 Workaround: The compiler needs to avoid generating any
11322 sequence with divide followed by extended double shift."
11324 This erratum is also present in "MIPS R4400MC Errata, Processor
11325 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11326 & 3.0" as errata #10 and #4, respectively.
11328 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11329 (also valid for MIPS R4000MC processors):
11331 "52. R4000SC: This bug does not apply for the R4000PC.
11333 There are two flavors of this bug:
11335 1) If the instruction just after divide takes an RF exception
11336 (tlb-refill, tlb-invalid) and gets an instruction cache
11337 miss (both primary and secondary) and the line which is
11338 currently in secondary cache at this index had the first
11339 data word, where the bits 5..2 are set, then R4000 would
11340 get a wrong result for the div.
11342 ##1
11343 nop
11344 div r8, r9
11345 ------------------- # end-of page. -tlb-refill
11346 nop
11347 ##2
11348 nop
11349 div r8, r9
11350 ------------------- # end-of page. -tlb-invalid
11351 nop
11353 2) If the divide is in the taken branch delay slot, where the
11354 target takes RF exception and gets an I-cache miss for the
11355 exception vector or where I-cache miss occurs for the
11356 target address, under the above mentioned scenarios, the
11357 div would get wrong results.
11359 ##1
11360 j r2 # to next page mapped or unmapped
11361 div r8,r9 # this bug would be there as long
11362 # as there is an ICache miss and
11363 nop # the "data pattern" is present
11365 ##2
11366 beq r0, r0, NextPage # to Next page
11367 div r8,r9
11368 nop
11370 This bug is present for div, divu, ddiv, and ddivu
11371 instructions.
11373 Workaround: For item 1), OS could make sure that the next page
11374 after the divide instruction is also mapped. For item 2), the
11375 compiler could make sure that the divide instruction is not in
11376 the branch delay slot."
11378 These processors have PRId values of 0x00004220 and 0x00004300 for
11379 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11383 {
11388 {
11391 }
11393 {
11395 {
11398 }
11400 {
11403 }
11404 else
11405 {
11409 }
11410 }
11412 }
11413 \f
11414 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
11415 with a final "000" replaced by "k". Ignore case.
11417 Note: this function is shared between GCC and GAS. */
11419 static bool
11421 {
11427 }
11430 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
11431 CPU name. We've traditionally allowed a lot of variation here.
11433 Note: this function is shared between GCC and GAS. */
11435 static bool
11437 {
11438 /* First see if the name matches exactly, or with a final "000"
11439 turned into "k". */
11443 /* If not, try comparing based on numerical designation alone.
11444 See if GIVEN is an unadorned number, or 'r' followed by a number. */
11446 given++;
11450 /* Skip over some well-known prefixes in the canonical name,
11451 hoping to find a number there too. */
11460 }
11463 /* Return the mips_cpu_info entry for the processor or ISA given
11464 by CPU_STRING. Return null if the string isn't recognized.
11466 A similar function exists in GAS. */
11470 {
11474 /* In the past, we allowed upper-case CPU names, but it doesn't
11475 work well with the multilib machinery. */
11478 {
11481 }
11483 /* 'from-abi' selects the most compatible architecture for the given
11484 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
11485 EABIs, we have to decide whether we're using the 32-bit or 64-bit
11486 version. Look first at the -mgp options, if given, otherwise base
11487 the choice on MASK_64BIT in TARGET_DEFAULT. */
11493 /* 'default' has traditionally been a no-op. Probably not very useful. */
11502 }
11505 /* Return the processor associated with the given ISA level, or null
11506 if the ISA isn't valid. */
11510 {
11518 }
11519 \f
11520 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
11521 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
11522 they only hold condition code modes, and CCmode is always considered to
11523 be 4 bytes wide. All other registers are word sized. */
11525 unsigned int
11527 {
11532 else
11534 }
11536 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
11537 all BLKmode objects are returned in memory. Under the new (N32 and
11538 64-bit MIPS ABIs) small structures are returned in a register.
11539 Objects with varying size must still be returned in memory, of
11540 course. */
11542 static bool
11544 {
11547 else
11550 }
11552 static bool
11554 {
11556 }
11557 \f
11558 /* Return true if INSN is a multiply-add or multiply-subtract
11559 instruction and PREV assigns to the accumulator operand. */
11561 bool
11563 {
11564 rtx x;
11583 }
11584 \f
11585 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
11586 that may clobber hi or lo. */
11590 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
11591 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
11593 static void
11595 {
11598 }
11600 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
11601 has NREADY elements, looking for a multiply-add or multiply-subtract
11602 instruction that is cumulative with mips_macc_chains_last_hilo.
11603 If there is one, promote it ahead of anything else that might
11604 clobber hi or lo. */
11606 static void
11608 {
11614 {
11618 {
11621 }
11623 }
11624 }
11625 \f
11626 /* The last instruction to be scheduled. */
11630 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
11631 points to an rtx that is initially an instruction. Nullify the rtx
11632 if the instruction uses the value of register X. */
11634 static void
11636 {
11642 }
11644 /* Return true if there is true register dependence between vr4130_last_insn
11645 and INSN. */
11647 static bool
11649 {
11653 }
11655 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
11656 the ready queue and that INSN2 is the instruction after it, return
11657 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
11658 in which INSN1 and INSN2 can probably issue in parallel, but for
11659 which (INSN2, INSN1) should be less sensitive to instruction
11660 alignment than (INSN1, INSN2). See 4130.md for more details. */
11662 static bool
11664 {
11665 sd_iterator_def sd_it;
11666 dep_t dep;
11668 /* Check for the following case:
11670 1) there is some other instruction X with an anti dependence on INSN1;
11671 2) X has a higher priority than INSN2; and
11672 3) X is an arithmetic instruction (and thus has no unit restrictions).
11674 If INSN1 is the last instruction blocking X, it would better to
11675 choose (INSN1, X) over (INSN2, INSN1). */
11686 {
11687 /* See whether INSN1 and INSN2 use different execution units,
11688 or if they are both ALU-type instructions. If so, they can
11689 probably execute in parallel. */
11693 {
11694 /* If only one of the instructions has a dependence on
11695 vr4130_last_insn, prefer to schedule the other one first. */
11701 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
11702 is not an ALU-type instruction and if INSN1 uses the same
11703 execution unit. (Note that if this condition holds, we already
11704 know that INSN2 uses a different execution unit.) */
11709 }
11710 }
11712 }
11714 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
11715 queue with at least two instructions. Swap the first two if
11716 vr4130_swap_insns_p says that it could be worthwhile. */
11718 static void
11720 {
11723 }
11724 \f
11725 /* Remove the instruction at index LOWER from ready queue READY and
11726 reinsert it in front of the instruction at index HIGHER. LOWER must
11727 be <= HIGHER. */
11729 static void
11731 {
11732 rtx new_head;
11739 }
11741 /* If the priority of the instruction at POS2 in the ready queue READY
11742 is within LIMIT units of that of the instruction at POS1, swap the
11743 instructions if POS2 is not already less than POS1. */
11745 static void
11747 {
11750 {
11751 rtx temp;
11755 }
11756 }
11758 /* Record whether last 74k AGEN instruction was a load or store. */
11762 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
11763 resets to TYPE_UNKNOWN state. */
11765 static void
11767 {
11771 {
11775 }
11776 }
11778 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
11779 loads to be grouped together, and multiple stores to be grouped
11780 together. Swap things around in the ready queue to make this happen. */
11782 static void
11784 {
11792 {
11796 {
11809 }
11810 }
11816 {
11818 /* Prefer to schedule loads since they have a higher latency. */
11820 /* Swap loads to the front of the queue. */
11824 /* Swap stores to the front of the queue. */
11829 }
11830 }
11832 /* Implement TARGET_SCHED_INIT. */
11834 static void
11837 {
11841 }
11843 /* Implement TARGET_SCHED_REORDER and TARG_SCHED_REORDER2. */
11845 static int
11848 {
11850 && TUNE_MACC_CHAINS
11854 && TUNE_MIPS4130
11855 && !TARGET_VR4130_ALIGN
11861 }
11863 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
11865 static int
11868 {
11872 {
11875 /* Don't count USEs and CLOBBERs against the issue rate. */
11879 more--;
11884 }
11886 }
11887 \f
11888 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11889 dependencies have no cost, except on the 20Kc where output-dependence
11890 is treated like input-dependence. */
11892 static int
11895 {
11902 }
11904 /* Return the number of instructions that can be issued per cycle. */
11906 static int
11908 {
11910 {
11915 /* The 74k is not strictly quad-issue cpu, but can be seen as one
11916 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
11917 but in reality only a maximum of 3 insns can be issued as the
11918 floating point load/stores also require a slot in the AGEN pipe. */
11931 /* This is actually 4, but we get better performance if we claim 3.
11932 This is partly because of unwanted speculative code motion with the
11933 larger number, and partly because in most common cases we can't
11934 reach the theoretical max of 4. */
11939 }
11940 }
11942 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
11943 be as wide as the scheduling freedom in the DFA. */
11945 static int
11947 {
11948 /* Can schedule up to 4 of the 6 function units in any one cycle. */
11953 }
11955 /* Implements a store data bypass check. We need this because the cprestore
11956 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
11957 default routine to abort. We just return false for that case. */
11958 /* ??? Should try to give a better result here than assuming false. */
11960 int
11962 {
11967 }
11968 \f
11969 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
11970 return the first operand of the associated "pref" or "prefx" insn. */
11972 rtx
11974 {
11975 /* store_streamed / load_streamed. */
11979 /* store / load. */
11983 /* store_retained / load_retained. */
11985 }
11986 \f
11987 /* MIPS builtin function support. */
11989 struct builtin_description
11990 {
11991 /* The code of the main .md file instruction. See mips_builtin_type
11992 for more information. */
11995 /* The floating-point comparison code to use with ICODE, if any. */
11998 /* The name of the builtin function. */
12001 /* Specifies how the function should be expanded. */
12004 /* The function's prototype. */
12007 /* The target flags required for this function. */
12009 };
12011 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
12012 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
12013 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
12015 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
12017 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
12018 TARGET_FLAGS. */
12019 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
12020 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
12022 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
12023 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
12025 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
12027 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12028 The lower and upper forms require TARGET_FLAGS while the any and all
12029 forms require MASK_MIPS3D. */
12030 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
12031 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
12033 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
12034 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
12036 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
12037 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
12039 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
12040 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
12042 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
12044 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12045 require MASK_MIPS3D. */
12046 #define CMP_4S_BUILTINS(INSN, COND) \
12047 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
12049 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12050 MASK_MIPS3D }, \
12051 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
12053 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12054 MASK_MIPS3D }
12056 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12057 instruction requires TARGET_FLAGS. */
12058 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
12059 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
12061 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12062 TARGET_FLAGS }, \
12063 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
12065 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12066 TARGET_FLAGS }
12068 /* Define all the builtins related to c.cond.fmt condition COND. */
12069 #define CMP_BUILTINS(COND) \
12070 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
12071 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
12072 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
12073 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
12074 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
12075 CMP_4S_BUILTINS (c, COND), \
12076 CMP_4S_BUILTINS (cabs, COND)
12079 {
12090 MASK_PAIRED_SINGLE_FLOAT),
12111 };
12113 /* Builtin functions for the SB-1 processor. */
12115 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12118 {
12120 };
12122 /* Builtin functions for DSP ASE. */
12124 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12125 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12126 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12127 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12128 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12130 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
12131 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
12132 builtin_description fields. */
12133 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
12135 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
12137 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12138 branch instruction. TARGET_FLAGS is a builtin_description field. */
12139 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
12141 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
12144 {
12211 /* The following are for the MIPS DSP ASE REV 2. */
12246 };
12249 {
12272 /* The following are for the MIPS DSP ASE REV 2. */
12288 };
12290 /* This helps provide a mapping from builtin function codes to bdesc
12291 arrays. */
12293 struct bdesc_map
12294 {
12295 /* The builtin function table that this entry describes. */
12298 /* The number of entries in the builtin function table. */
12301 /* The target processor that supports these builtin functions.
12302 PROCESSOR_MAX means we enable them for all processors. */
12305 /* If the target has these flags, this builtin function table
12306 will not be supported. */
12308 };
12311 {
12316 MASK_64BIT }
12317 };
12319 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
12320 suitable for input operand OP of instruction ICODE. Return the value. */
12322 static rtx
12325 {
12326 rtx value;
12332 {
12334 /* Check the predicate again. */
12336 {
12339 }
12340 }
12343 }
12345 /* Return an rtx suitable for output operand OP of instruction ICODE.
12346 If TARGET is non-null, try to use it where possible. */
12348 static rtx
12350 {
12358 }
12360 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
12362 rtx
12366 {
12369 tree fndecl;
12378 {
12382 }
12386 {
12388 {
12393 }
12395 }
12400 {
12425 }
12426 }
12428 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
12430 void
12432 {
12436 tree V2SF_type_node;
12437 tree V2HI_type_node;
12438 tree V4QI_type_node;
12441 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
12446 {
12505 }
12508 {
12515 NULL_TREE);
12520 NULL_TREE);
12525 NULL_TREE);
12529 V4QI_type_node,
12530 NULL_TREE);
12534 V2HI_type_node,
12535 NULL_TREE);
12539 intSI_type_node,
12540 NULL_TREE);
12545 NULL_TREE);
12550 NULL_TREE);
12554 V2HI_type_node,
12555 NULL_TREE);
12559 V4QI_type_node,
12560 NULL_TREE);
12565 NULL_TREE);
12570 NULL_TREE);
12575 NULL_TREE);
12580 NULL_TREE);
12585 NULL_TREE);
12590 NULL_TREE);
12595 NULL_TREE);
12599 intSI_type_node,
12600 NULL_TREE);
12604 intSI_type_node,
12605 NULL_TREE);
12610 NULL_TREE);
12615 NULL_TREE);
12620 NULL_TREE);
12625 NULL_TREE);
12630 NULL_TREE);
12635 NULL_TREE);
12640 NULL_TREE);
12646 {
12649 V4QI_type_node,
12650 NULL_TREE);
12659 intDI_type_node,
12660 unsigned_intSI_type_node,
12666 NULL_TREE);
12670 unsigned_intSI_type_node,
12678 }
12679 }
12681 /* Iterate through all of the bdesc arrays, initializing all of the
12682 builtin functions. */
12686 {
12695 }
12696 }
12698 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
12699 .md pattern and CALL is the function expr with arguments. TARGET,
12700 if nonnull, suggests a good place to put the result.
12701 HAS_TARGET indicates the function must return something. */
12703 static rtx
12706 {
12712 {
12713 /* We save target to ops[0]. */
12716 }
12718 /* We need to test if the arglist is not zero. Some instructions have extra
12719 clobber registers. */
12724 {
12739 }
12741 }
12743 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
12744 function (TYPE says which). EXP is the tree for the function
12745 function, ICODE is the instruction that should be used to compare
12746 the first two arguments, and COND is the condition it should test.
12747 TARGET, if nonnull, suggests a good place to put the result. */
12749 static rtx
12753 {
12764 {
12767 }
12768 else
12769 {
12772 }
12775 }
12777 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
12778 into TARGET otherwise. Return TARGET. */
12780 static rtx
12783 {
12789 /* First assume that CONDITION is false. */
12792 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
12797 /* Fix TARGET if CONDITION is true. */
12803 }
12805 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
12806 of the comparison instruction and COND is the condition it should test.
12807 EXP is the function call and arguments and TARGET, if nonnull,
12808 suggests a good place to put the boolean result. */
12810 static rtx
12814 {
12822 /* Prepare the operands to the comparison. */
12828 {
12840 }
12842 /* If the comparison sets more than one register, we define the result
12843 to be 0 if all registers are false and -1 if all registers are true.
12844 The value of the complete result is indeterminate otherwise. */
12846 {
12863 }
12864 }
12866 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
12867 suggests a good place to put the boolean result. */
12869 static rtx
12871 {
12882 else
12888 }
12889 \f
12890 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
12891 FIRST is true if this is the first time handling this decl. */
12893 static void
12895 {
12899 {
12906 }
12907 }
12909 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
12910 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
12912 static void
12914 {
12917 }
12919 /* SImode values are represented as sign-extended to DImode. */
12921 int
12923 {
12928 }
12929 \f
12930 /* MIPS implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
12932 static void
12934 {
12936 {
12947 }
12950 }
12951 \f