1 /* Check that the SH specific sh_treg_combine RTL optimization pass works as
3 /* { dg-do compile } */
4 /* { dg-options "-O2" } */
6 /* { dg-final { scan-assembler-not "not\t" } } */
7 /* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
8 /* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
9 /* { dg-final { scan-assembler-times "cmp/gt" 2 } } */
11 /* { dg-final { scan-assembler-times "tst" 7 { target { ! sh2a } } } } */
12 /* { dg-final { scan-assembler-times "movt" 2 { target { ! sh2a } } } } */
14 /* { dg-final { scan-assembler-times "tst" 6 { target { sh2a } } } } */
15 /* { dg-final { scan-assembler-not "movt" { target { sh2a } } } } */
16 /* { dg-final { scan-assembler-times "nott" 2 { target { sh2a } } } } */
19 /* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi
20 SH2A: 1x tst, 1x nott, 2x cmp/eq, 1x cmp/hi */
22 blk_oversized_queue_0 (int* q
)
29 int __attribute__ ((noinline
))
30 get_request_0 (int* q
, int rw
)
32 if (blk_oversized_queue_0 (q
))
34 if ((rw
== 1) || (rw
== 0))
42 /* 1x tst, 1x cmp/gt, 1x cmp/hi
43 On SH2A mem loads/stores have a wrong length of 4 bytes and thus will
44 not be placed in a delay slot. This introduces an extra cmp/gt insn. */
46 blk_oversized_queue_1 (int* q
)
53 int __attribute__ ((noinline
))
54 get_request_1 (int* q
, int rw
)
56 if (blk_oversized_queue_1 (q
))
58 if ((rw
== 1) || (rw
== 0))
66 /* 1x tst, 1x cmp/gt, 1x cmp/hi, 1x cmp/hi */
68 blk_oversized_queue_2 (int* q
)
75 int __attribute__ ((noinline
))
76 get_request_2 (int* q
, int rw
)
78 if (blk_oversized_queue_2 (q
))
80 if ((rw
== 1) || (rw
== 0))
88 /* 3x tst, 1x movt, 1x cmp/hi, 1x not */
90 blk_oversized_queue_5 (int* q
)
97 int __attribute__ ((noinline
))
98 get_request_5 (int* q
, int rw
)
100 if (blk_oversized_queue_5 (q
))
102 if ((rw
== 1) || (rw
== 0))