PR target/83368
[official-gcc.git] / gcc / lra-constraints.c
blob3af31999ad8edbfec19a7f009d7134955fbb254d
1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
24 split.
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
37 allocations;
38 o some heuristics to choose insn alternative to improve the
39 inheritance;
40 o early clobbers etc.
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
45 changed.
47 There is special code for preventing all LRA and this pass cycling
48 in case of bugs.
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
57 traversal of EBBs.
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
65 ... => ...
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
70 pseudo*.
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
82 insns.
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
89 ... =>
90 ... r <- s (new insn -- restore)
91 ... <- r ... <- r
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
96 Splitting is done:
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
107 #undef REG_OK_STRICT
109 #include "config.h"
110 #include "system.h"
111 #include "coretypes.h"
112 #include "backend.h"
113 #include "target.h"
114 #include "rtl.h"
115 #include "tree.h"
116 #include "predict.h"
117 #include "df.h"
118 #include "memmodel.h"
119 #include "tm_p.h"
120 #include "expmed.h"
121 #include "optabs.h"
122 #include "regs.h"
123 #include "ira.h"
124 #include "recog.h"
125 #include "output.h"
126 #include "addresses.h"
127 #include "expr.h"
128 #include "cfgrtl.h"
129 #include "rtl-error.h"
130 #include "params.h"
131 #include "lra.h"
132 #include "lra-int.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 reload insns. */
138 static int bb_reload_num;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn *curr_insn;
144 static rtx curr_insn_set;
145 static basic_block curr_bb;
146 static lra_insn_recog_data_t curr_id;
147 static struct lra_static_insn_data *curr_static_id;
148 static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS];
156 /* Start numbers for new registers and insns at the current constraints
157 pass start. */
158 static int new_regno_start;
159 static int new_insn_uid_start;
161 /* If LOC is nonnull, strip any outer subreg from it. */
162 static inline rtx *
163 strip_subreg (rtx *loc)
165 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
170 static int
171 get_try_hard_regno (int regno)
173 int hard_regno;
174 enum reg_class rclass;
176 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
177 hard_regno = lra_get_regno_hard_regno (regno);
178 if (hard_regno >= 0)
179 return hard_regno;
180 rclass = lra_get_allocno_class (regno);
181 if (rclass == NO_REGS)
182 return -1;
183 return ira_class_hard_regs[rclass][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
190 static int
191 get_hard_regno (rtx x, bool final_p)
193 rtx reg;
194 int hard_regno;
196 reg = x;
197 if (SUBREG_P (x))
198 reg = SUBREG_REG (x);
199 if (! REG_P (reg))
200 return -1;
201 if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg)))
202 hard_regno = lra_get_regno_hard_regno (hard_regno);
203 if (hard_regno < 0)
204 return -1;
205 if (final_p)
206 hard_regno = lra_get_elimination_hard_regno (hard_regno);
207 if (SUBREG_P (x))
208 hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg),
209 SUBREG_BYTE (x), GET_MODE (x));
210 return hard_regno;
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno)
220 int hard_regno;
222 if (! HARD_REGISTER_NUM_P (hard_regno = regno))
223 hard_regno = lra_get_regno_hard_regno (regno);
224 if (hard_regno >= 0)
226 hard_regno = lra_get_elimination_hard_regno (hard_regno);
227 return REGNO_REG_CLASS (hard_regno);
229 if (regno >= new_regno_start)
230 return lra_get_allocno_class (regno);
231 return NO_REGS;
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
242 static bool
243 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
245 enum reg_class rclass, common_class;
246 machine_mode reg_mode;
247 int class_size, hard_regno, nregs, i, j;
248 int regno = REGNO (reg);
250 if (new_class != NULL)
251 *new_class = NO_REGS;
252 if (regno < FIRST_PSEUDO_REGISTER)
254 rtx final_reg = reg;
255 rtx *final_loc = &final_reg;
257 lra_eliminate_reg_if_possible (final_loc);
258 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
260 reg_mode = GET_MODE (reg);
261 rclass = get_reg_class (regno);
262 if (regno < new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn) >= new_insn_uid_start
269 && curr_insn_set != NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set)))
272 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno >= new_regno_start && rclass == ALL_REGS)
278 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
279 && ! hard_reg_set_subset_p (reg_class_contents[cl],
280 lra_no_alloc_regs)));
281 else
283 common_class = ira_reg_class_subset[rclass][cl];
284 if (new_class != NULL)
285 *new_class = common_class;
286 if (hard_reg_set_subset_p (reg_class_contents[common_class],
287 lra_no_alloc_regs))
288 return false;
289 /* Check that there are enough allocatable regs. */
290 class_size = ira_class_hard_regs_num[common_class];
291 for (i = 0; i < class_size; i++)
293 hard_regno = ira_class_hard_regs[common_class][i];
294 nregs = hard_regno_nregs (hard_regno, reg_mode);
295 if (nregs == 1)
296 return true;
297 for (j = 0; j < nregs; j++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
299 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class],
300 hard_regno + j))
301 break;
302 if (j >= nregs)
303 return true;
305 return false;
309 /* Return true if REGNO satisfies a memory constraint. */
310 static bool
311 in_mem_p (int regno)
313 return get_reg_class (regno) == NO_REGS;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
318 reg. */
319 static int
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED,
321 rtx addr, addr_space_t as)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as));
325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
326 return 0;
328 win:
329 return 1;
330 #else
331 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
332 #endif
335 namespace {
336 /* Temporarily eliminates registers in an address (for the lifetime of
337 the object). */
338 class address_eliminator {
339 public:
340 address_eliminator (struct address_info *ad);
341 ~address_eliminator ();
343 private:
344 struct address_info *m_ad;
345 rtx *m_base_loc;
346 rtx m_base_reg;
347 rtx *m_index_loc;
348 rtx m_index_reg;
352 address_eliminator::address_eliminator (struct address_info *ad)
353 : m_ad (ad),
354 m_base_loc (strip_subreg (ad->base_term)),
355 m_base_reg (NULL_RTX),
356 m_index_loc (strip_subreg (ad->index_term)),
357 m_index_reg (NULL_RTX)
359 if (m_base_loc != NULL)
361 m_base_reg = *m_base_loc;
362 lra_eliminate_reg_if_possible (m_base_loc);
363 if (m_ad->base_term2 != NULL)
364 *m_ad->base_term2 = *m_ad->base_term;
366 if (m_index_loc != NULL)
368 m_index_reg = *m_index_loc;
369 lra_eliminate_reg_if_possible (m_index_loc);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc && *m_base_loc != m_base_reg)
377 *m_base_loc = m_base_reg;
378 if (m_ad->base_term2 != NULL)
379 *m_ad->base_term2 = *m_ad->base_term;
381 if (m_index_loc && *m_index_loc != m_index_reg)
382 *m_index_loc = m_index_reg;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
386 static bool
387 valid_address_p (struct address_info *ad)
389 address_eliminator eliminator (ad);
390 return valid_address_p (ad->mode, *ad->outer, ad->as);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
395 static bool
396 satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
398 struct address_info ad;
400 decompose_mem_address (&ad, op);
401 address_eliminator eliminator (&ad);
402 return constraint_satisfied_p (op, constraint);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
407 static bool
408 satisfies_address_constraint_p (struct address_info *ad,
409 enum constraint_num constraint)
411 address_eliminator eliminator (ad);
412 return constraint_satisfied_p (*ad->outer, constraint);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
417 static bool
418 satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
420 struct address_info ad;
422 decompose_lea_address (&ad, &op);
423 return satisfies_address_constraint_p (&ad, constraint);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
429 void
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
435 rtx res;
437 if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
438 ira_reg_equiv[i].memory = copy_rtx (res);
439 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
440 ira_reg_equiv[i].invariant = copy_rtx (res);
444 static rtx loc_equivalence_callback (rtx, const_rtx, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
448 equivalences. */
449 static void
450 update_equiv (int regno)
452 rtx x;
454 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
455 ira_reg_equiv[regno].memory
456 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
457 NULL_RTX);
458 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
459 ira_reg_equiv[regno].invariant
460 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
461 NULL_RTX);
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
466 static rtx
467 get_equiv (rtx x)
469 int regno;
470 rtx res;
472 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv[regno].defined_p
474 || ! ira_reg_equiv[regno].profitable_p
475 || lra_get_regno_hard_regno (regno) >= 0)
476 return x;
477 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
479 if (targetm.cannot_substitute_mem_equiv_p (res))
480 return x;
481 return res;
483 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
484 return res;
485 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
486 return res;
487 gcc_unreachable ();
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
492 X. */
493 static rtx
494 get_equiv_with_elimination (rtx x, rtx_insn *insn)
496 rtx res = get_equiv (x);
498 if (x == res || CONSTANT_P (res))
499 return res;
500 return lra_eliminate_regs_1 (insn, res, GET_MODE (res),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
505 static void
506 init_curr_operand_mode (void)
508 int nop = curr_static_id->n_operands;
509 for (int i = 0; i < nop; i++)
511 machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
512 if (mode == VOIDmode)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
517 mode = Pmode;
518 else
519 mode = curr_static_id->operand[i].mode;
521 curr_operand_mode[i] = mode;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
530 struct input_reload
532 /* True for input reload of matched operands. */
533 bool match_p;
534 /* Reloaded value. */
535 rtx input;
536 /* Reload pseudo used. */
537 rtx reg;
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
546 /* Initiate data concerning reuse of input reloads for the current
547 insn. */
548 static void
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num = 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
561 static bool
562 get_reload_reg (enum op_type type, machine_mode mode, rtx original,
563 enum reg_class rclass, bool in_subreg_p,
564 const char *title, rtx *result_reg)
566 int i, regno;
567 enum reg_class new_class;
568 bool unique_p = false;
570 if (type == OP_OUT)
572 *result_reg
573 = lra_create_new_reg_with_unique_value (mode, original, rclass, title);
574 return true;
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original))
579 for (i = 0; i < curr_insn_input_reloads_num; i++)
581 if (! curr_insn_input_reloads[i].match_p
582 && rtx_equal_p (curr_insn_input_reloads[i].input, original)
583 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
585 rtx reg = curr_insn_input_reloads[i].reg;
586 regno = REGNO (reg);
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg) != mode)
592 if (in_subreg_p)
593 continue;
594 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)),
595 GET_MODE_SIZE (mode)))
596 continue;
597 reg = lowpart_subreg (mode, reg, GET_MODE (reg));
598 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
599 continue;
601 *result_reg = reg;
602 if (lra_dump_file != NULL)
604 fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
605 dump_value_slim (lra_dump_file, original, 1);
607 if (new_class != lra_get_allocno_class (regno))
608 lra_change_class (regno, new_class, ", change to", false);
609 if (lra_dump_file != NULL)
610 fprintf (lra_dump_file, "\n");
611 return false;
613 /* If we have an input reload with a different mode, make sure it
614 will get a different hard reg. */
615 else if (REG_P (original)
616 && REG_P (curr_insn_input_reloads[i].input)
617 && REGNO (original) == REGNO (curr_insn_input_reloads[i].input)
618 && (GET_MODE (original)
619 != GET_MODE (curr_insn_input_reloads[i].input)))
620 unique_p = true;
622 *result_reg = (unique_p
623 ? lra_create_new_reg_with_unique_value
624 : lra_create_new_reg) (mode, original, rclass, title);
625 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
626 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
627 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false;
628 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
629 return true;
634 /* The page contains code to extract memory address parts. */
636 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
637 static inline bool
638 ok_for_index_p_nonstrict (rtx reg)
640 unsigned regno = REGNO (reg);
642 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
645 /* A version of regno_ok_for_base_p for use here, when all pseudos
646 should count as OK. Arguments as for regno_ok_for_base_p. */
647 static inline bool
648 ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
649 enum rtx_code outer_code, enum rtx_code index_code)
651 unsigned regno = REGNO (reg);
653 if (regno >= FIRST_PSEUDO_REGISTER)
654 return true;
655 return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
660 /* The page contains major code to choose the current insn alternative
661 and generate reloads for it. */
663 /* Return the offset from REGNO of the least significant register
664 in (reg:MODE REGNO).
666 This function is used to tell whether two registers satisfy
667 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
669 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
670 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
672 lra_constraint_offset (int regno, machine_mode mode)
674 lra_assert (regno < FIRST_PSEUDO_REGISTER);
676 scalar_int_mode int_mode;
677 if (WORDS_BIG_ENDIAN
678 && is_a <scalar_int_mode> (mode, &int_mode)
679 && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD)
680 return hard_regno_nregs (regno, mode) - 1;
681 return 0;
684 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
685 if they are the same hard reg, and has special hacks for
686 auto-increment and auto-decrement. This is specifically intended for
687 process_alt_operands to use in determining whether two operands
688 match. X is the operand whose number is the lower of the two.
690 It is supposed that X is the output operand and Y is the input
691 operand. Y_HARD_REGNO is the final hard regno of register Y or
692 register in subreg Y as we know it now. Otherwise, it is a
693 negative value. */
694 static bool
695 operands_match_p (rtx x, rtx y, int y_hard_regno)
697 int i;
698 RTX_CODE code = GET_CODE (x);
699 const char *fmt;
701 if (x == y)
702 return true;
703 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
704 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
706 int j;
708 i = get_hard_regno (x, false);
709 if (i < 0)
710 goto slow;
712 if ((j = y_hard_regno) < 0)
713 goto slow;
715 i += lra_constraint_offset (i, GET_MODE (x));
716 j += lra_constraint_offset (j, GET_MODE (y));
718 return i == j;
721 /* If two operands must match, because they are really a single
722 operand of an assembler insn, then two post-increments are invalid
723 because the assembler insn would increment only once. On the
724 other hand, a post-increment matches ordinary indexing if the
725 post-increment is the output operand. */
726 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
727 return operands_match_p (XEXP (x, 0), y, y_hard_regno);
729 /* Two pre-increments are invalid because the assembler insn would
730 increment only once. On the other hand, a pre-increment matches
731 ordinary indexing if the pre-increment is the input operand. */
732 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
733 || GET_CODE (y) == PRE_MODIFY)
734 return operands_match_p (x, XEXP (y, 0), -1);
736 slow:
738 if (code == REG && REG_P (y))
739 return REGNO (x) == REGNO (y);
741 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
742 && x == SUBREG_REG (y))
743 return true;
744 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
745 && SUBREG_REG (x) == y)
746 return true;
748 /* Now we have disposed of all the cases in which different rtx
749 codes can match. */
750 if (code != GET_CODE (y))
751 return false;
753 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
754 if (GET_MODE (x) != GET_MODE (y))
755 return false;
757 switch (code)
759 CASE_CONST_UNIQUE:
760 return false;
762 case LABEL_REF:
763 return label_ref_label (x) == label_ref_label (y);
764 case SYMBOL_REF:
765 return XSTR (x, 0) == XSTR (y, 0);
767 default:
768 break;
771 /* Compare the elements. If any pair of corresponding elements fail
772 to match, return false for the whole things. */
774 fmt = GET_RTX_FORMAT (code);
775 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
777 int val, j;
778 switch (fmt[i])
780 case 'w':
781 if (XWINT (x, i) != XWINT (y, i))
782 return false;
783 break;
785 case 'i':
786 if (XINT (x, i) != XINT (y, i))
787 return false;
788 break;
790 case 'p':
791 if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y)))
792 return false;
793 break;
795 case 'e':
796 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
797 if (val == 0)
798 return false;
799 break;
801 case '0':
802 break;
804 case 'E':
805 if (XVECLEN (x, i) != XVECLEN (y, i))
806 return false;
807 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
809 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
810 if (val == 0)
811 return false;
813 break;
815 /* It is believed that rtx's at this level will never
816 contain anything but integers and other rtx's, except for
817 within LABEL_REFs and SYMBOL_REFs. */
818 default:
819 gcc_unreachable ();
822 return true;
825 /* True if X is a constant that can be forced into the constant pool.
826 MODE is the mode of the operand, or VOIDmode if not known. */
827 #define CONST_POOL_OK_P(MODE, X) \
828 ((MODE) != VOIDmode \
829 && CONSTANT_P (X) \
830 && GET_CODE (X) != HIGH \
831 && GET_MODE_SIZE (MODE).is_constant () \
832 && !targetm.cannot_force_const_mem (MODE, X))
834 /* True if C is a non-empty register class that has too few registers
835 to be safely used as a reload target class. */
836 #define SMALL_REGISTER_CLASS_P(C) \
837 (ira_class_hard_regs_num [(C)] == 1 \
838 || (ira_class_hard_regs_num [(C)] >= 1 \
839 && targetm.class_likely_spilled_p (C)))
841 /* If REG is a reload pseudo, try to make its class satisfying CL. */
842 static void
843 narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
845 enum reg_class rclass;
847 /* Do not make more accurate class from reloads generated. They are
848 mostly moves with a lot of constraints. Making more accurate
849 class may results in very narrow class and impossibility of find
850 registers for several reloads of one insn. */
851 if (INSN_UID (curr_insn) >= new_insn_uid_start)
852 return;
853 if (GET_CODE (reg) == SUBREG)
854 reg = SUBREG_REG (reg);
855 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
856 return;
857 if (in_class_p (reg, cl, &rclass) && rclass != cl)
858 lra_change_class (REGNO (reg), rclass, " Change to", true);
861 /* Searches X for any reference to a reg with the same value as REGNO,
862 returning the rtx of the reference found if any. Otherwise,
863 returns NULL_RTX. */
864 static rtx
865 regno_val_use_in (unsigned int regno, rtx x)
867 const char *fmt;
868 int i, j;
869 rtx tem;
871 if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val)
872 return x;
874 fmt = GET_RTX_FORMAT (GET_CODE (x));
875 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
877 if (fmt[i] == 'e')
879 if ((tem = regno_val_use_in (regno, XEXP (x, i))))
880 return tem;
882 else if (fmt[i] == 'E')
883 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
884 if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j))))
885 return tem;
888 return NULL_RTX;
891 /* Return true if all current insn non-output operands except INS (it
892 has a negaitve end marker) do not use pseudos with the same value
893 as REGNO. */
894 static bool
895 check_conflict_input_operands (int regno, signed char *ins)
897 int in;
898 int n_operands = curr_static_id->n_operands;
900 for (int nop = 0; nop < n_operands; nop++)
901 if (! curr_static_id->operand[nop].is_operator
902 && curr_static_id->operand[nop].type != OP_OUT)
904 for (int i = 0; (in = ins[i]) >= 0; i++)
905 if (in == nop)
906 break;
907 if (in < 0
908 && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX)
909 return false;
911 return true;
914 /* Generate reloads for matching OUT and INS (array of input operand
915 numbers with end marker -1) with reg class GOAL_CLASS, considering
916 output operands OUTS (similar array to INS) needing to be in different
917 registers. Add input and output reloads correspondingly to the lists
918 *BEFORE and *AFTER. OUT might be negative. In this case we generate
919 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
920 that the output operand is early clobbered for chosen alternative. */
921 static void
922 match_reload (signed char out, signed char *ins, signed char *outs,
923 enum reg_class goal_class, rtx_insn **before,
924 rtx_insn **after, bool early_clobber_p)
926 bool out_conflict;
927 int i, in;
928 rtx new_in_reg, new_out_reg, reg;
929 machine_mode inmode, outmode;
930 rtx in_rtx = *curr_id->operand_loc[ins[0]];
931 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
933 inmode = curr_operand_mode[ins[0]];
934 outmode = out < 0 ? inmode : curr_operand_mode[out];
935 push_to_sequence (*before);
936 if (inmode != outmode)
938 /* process_alt_operands has already checked that the mode sizes
939 are ordered. */
940 if (partial_subreg_p (outmode, inmode))
942 reg = new_in_reg
943 = lra_create_new_reg_with_unique_value (inmode, in_rtx,
944 goal_class, "");
945 if (SCALAR_INT_MODE_P (inmode))
946 new_out_reg = gen_lowpart_SUBREG (outmode, reg);
947 else
948 new_out_reg = gen_rtx_SUBREG (outmode, reg, 0);
949 LRA_SUBREG_P (new_out_reg) = 1;
950 /* If the input reg is dying here, we can use the same hard
951 register for REG and IN_RTX. We do it only for original
952 pseudos as reload pseudos can die although original
953 pseudos still live where reload pseudos dies. */
954 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
955 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
956 && (!early_clobber_p
957 || check_conflict_input_operands(REGNO (in_rtx), ins)))
958 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
960 else
962 reg = new_out_reg
963 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
964 goal_class, "");
965 if (SCALAR_INT_MODE_P (outmode))
966 new_in_reg = gen_lowpart_SUBREG (inmode, reg);
967 else
968 new_in_reg = gen_rtx_SUBREG (inmode, reg, 0);
969 /* NEW_IN_REG is non-paradoxical subreg. We don't want
970 NEW_OUT_REG living above. We add clobber clause for
971 this. This is just a temporary clobber. We can remove
972 it at the end of LRA work. */
973 rtx_insn *clobber = emit_clobber (new_out_reg);
974 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
975 LRA_SUBREG_P (new_in_reg) = 1;
976 if (GET_CODE (in_rtx) == SUBREG)
978 rtx subreg_reg = SUBREG_REG (in_rtx);
980 /* If SUBREG_REG is dying here and sub-registers IN_RTX
981 and NEW_IN_REG are similar, we can use the same hard
982 register for REG and SUBREG_REG. */
983 if (REG_P (subreg_reg)
984 && (int) REGNO (subreg_reg) < lra_new_regno_start
985 && GET_MODE (subreg_reg) == outmode
986 && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg))
987 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))
988 && (! early_clobber_p
989 || check_conflict_input_operands (REGNO (subreg_reg),
990 ins)))
991 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
995 else
997 /* Pseudos have values -- see comments for lra_reg_info.
998 Different pseudos with the same value do not conflict even if
999 they live in the same place. When we create a pseudo we
1000 assign value of original pseudo (if any) from which we
1001 created the new pseudo. If we create the pseudo from the
1002 input pseudo, the new pseudo will have no conflict with the
1003 input pseudo which is wrong when the input pseudo lives after
1004 the insn and as the new pseudo value is changed by the insn
1005 output. Therefore we create the new pseudo from the output
1006 except the case when we have single matched dying input
1007 pseudo.
1009 We cannot reuse the current output register because we might
1010 have a situation like "a <- a op b", where the constraints
1011 force the second input operand ("b") to match the output
1012 operand ("a"). "b" must then be copied into a new register
1013 so that it doesn't clobber the current value of "a".
1015 We can not use the same value if the output pseudo is
1016 early clobbered or the input pseudo is mentioned in the
1017 output, e.g. as an address part in memory, because
1018 output reload will actually extend the pseudo liveness.
1019 We don't care about eliminable hard regs here as we are
1020 interesting only in pseudos. */
1022 /* Matching input's register value is the same as one of the other
1023 output operand. Output operands in a parallel insn must be in
1024 different registers. */
1025 out_conflict = false;
1026 if (REG_P (in_rtx))
1028 for (i = 0; outs[i] >= 0; i++)
1030 rtx other_out_rtx = *curr_id->operand_loc[outs[i]];
1031 if (REG_P (other_out_rtx)
1032 && (regno_val_use_in (REGNO (in_rtx), other_out_rtx)
1033 != NULL_RTX))
1035 out_conflict = true;
1036 break;
1041 new_in_reg = new_out_reg
1042 = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx)
1043 && (int) REGNO (in_rtx) < lra_new_regno_start
1044 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
1045 && (! early_clobber_p
1046 || check_conflict_input_operands (REGNO (in_rtx), ins))
1047 && (out < 0
1048 || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX)
1049 && !out_conflict
1050 ? lra_create_new_reg (inmode, in_rtx, goal_class, "")
1051 : lra_create_new_reg_with_unique_value (outmode, out_rtx,
1052 goal_class, ""));
1054 /* In operand can be got from transformations before processing insn
1055 constraints. One example of such transformations is subreg
1056 reloading (see function simplify_operand_subreg). The new
1057 pseudos created by the transformations might have inaccurate
1058 class (ALL_REGS) and we should make their classes more
1059 accurate. */
1060 narrow_reload_pseudo_class (in_rtx, goal_class);
1061 lra_emit_move (copy_rtx (new_in_reg), in_rtx);
1062 *before = get_insns ();
1063 end_sequence ();
1064 /* Add the new pseudo to consider values of subsequent input reload
1065 pseudos. */
1066 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
1067 curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx;
1068 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true;
1069 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg;
1070 for (i = 0; (in = ins[i]) >= 0; i++)
1072 lra_assert
1073 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
1074 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]));
1075 *curr_id->operand_loc[in] = new_in_reg;
1077 lra_update_dups (curr_id, ins);
1078 if (out < 0)
1079 return;
1080 /* See a comment for the input operand above. */
1081 narrow_reload_pseudo_class (out_rtx, goal_class);
1082 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
1084 start_sequence ();
1085 lra_emit_move (out_rtx, copy_rtx (new_out_reg));
1086 emit_insn (*after);
1087 *after = get_insns ();
1088 end_sequence ();
1090 *curr_id->operand_loc[out] = new_out_reg;
1091 lra_update_dup (curr_id, out);
1094 /* Return register class which is union of all reg classes in insn
1095 constraint alternative string starting with P. */
1096 static enum reg_class
1097 reg_class_from_constraints (const char *p)
1099 int c, len;
1100 enum reg_class op_class = NO_REGS;
1103 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1105 case '#':
1106 case ',':
1107 return op_class;
1109 case 'g':
1110 op_class = reg_class_subunion[op_class][GENERAL_REGS];
1111 break;
1113 default:
1114 enum constraint_num cn = lookup_constraint (p);
1115 enum reg_class cl = reg_class_for_constraint (cn);
1116 if (cl == NO_REGS)
1118 if (insn_extra_address_constraint (cn))
1119 op_class
1120 = (reg_class_subunion
1121 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1122 ADDRESS, SCRATCH)]);
1123 break;
1126 op_class = reg_class_subunion[op_class][cl];
1127 break;
1129 while ((p += len), c);
1130 return op_class;
1133 /* If OP is a register, return the class of the register as per
1134 get_reg_class, otherwise return NO_REGS. */
1135 static inline enum reg_class
1136 get_op_class (rtx op)
1138 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
1141 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1142 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1143 SUBREG for VAL to make them equal. */
1144 static rtx_insn *
1145 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1147 if (GET_MODE (mem_pseudo) != GET_MODE (val))
1149 /* Usually size of mem_pseudo is greater than val size but in
1150 rare cases it can be less as it can be defined by target
1151 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1152 if (! MEM_P (val))
1154 val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
1155 GET_CODE (val) == SUBREG
1156 ? SUBREG_REG (val) : val);
1157 LRA_SUBREG_P (val) = 1;
1159 else
1161 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
1162 LRA_SUBREG_P (mem_pseudo) = 1;
1165 return to_p ? gen_move_insn (mem_pseudo, val)
1166 : gen_move_insn (val, mem_pseudo);
1169 /* Process a special case insn (register move), return true if we
1170 don't need to process it anymore. INSN should be a single set
1171 insn. Set up that RTL was changed through CHANGE_P and that hook
1172 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1173 SEC_MEM_P. */
1174 static bool
1175 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
1177 int sregno, dregno;
1178 rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1179 rtx_insn *before;
1180 enum reg_class dclass, sclass, secondary_class;
1181 secondary_reload_info sri;
1183 lra_assert (curr_insn_set != NULL_RTX);
1184 dreg = dest = SET_DEST (curr_insn_set);
1185 sreg = src = SET_SRC (curr_insn_set);
1186 if (GET_CODE (dest) == SUBREG)
1187 dreg = SUBREG_REG (dest);
1188 if (GET_CODE (src) == SUBREG)
1189 sreg = SUBREG_REG (src);
1190 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
1191 return false;
1192 sclass = dclass = NO_REGS;
1193 if (REG_P (dreg))
1194 dclass = get_reg_class (REGNO (dreg));
1195 gcc_assert (dclass < LIM_REG_CLASSES);
1196 if (dclass == ALL_REGS)
1197 /* ALL_REGS is used for new pseudos created by transformations
1198 like reload of SUBREG_REG (see function
1199 simplify_operand_subreg). We don't know their class yet. We
1200 should figure out the class from processing the insn
1201 constraints not in this fast path function. Even if ALL_REGS
1202 were a right class for the pseudo, secondary_... hooks usually
1203 are not define for ALL_REGS. */
1204 return false;
1205 if (REG_P (sreg))
1206 sclass = get_reg_class (REGNO (sreg));
1207 gcc_assert (sclass < LIM_REG_CLASSES);
1208 if (sclass == ALL_REGS)
1209 /* See comments above. */
1210 return false;
1211 if (sclass == NO_REGS && dclass == NO_REGS)
1212 return false;
1213 if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass)
1214 && ((sclass != NO_REGS && dclass != NO_REGS)
1215 || (GET_MODE (src)
1216 != targetm.secondary_memory_needed_mode (GET_MODE (src)))))
1218 *sec_mem_p = true;
1219 return false;
1221 if (! REG_P (dreg) || ! REG_P (sreg))
1222 return false;
1223 sri.prev_sri = NULL;
1224 sri.icode = CODE_FOR_nothing;
1225 sri.extra_cost = 0;
1226 secondary_class = NO_REGS;
1227 /* Set up hard register for a reload pseudo for hook
1228 secondary_reload because some targets just ignore unassigned
1229 pseudos in the hook. */
1230 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
1232 dregno = REGNO (dreg);
1233 reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
1235 else
1236 dregno = -1;
1237 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1239 sregno = REGNO (sreg);
1240 reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1242 else
1243 sregno = -1;
1244 if (sclass != NO_REGS)
1245 secondary_class
1246 = (enum reg_class) targetm.secondary_reload (false, dest,
1247 (reg_class_t) sclass,
1248 GET_MODE (src), &sri);
1249 if (sclass == NO_REGS
1250 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1251 && dclass != NO_REGS))
1253 enum reg_class old_sclass = secondary_class;
1254 secondary_reload_info old_sri = sri;
1256 sri.prev_sri = NULL;
1257 sri.icode = CODE_FOR_nothing;
1258 sri.extra_cost = 0;
1259 secondary_class
1260 = (enum reg_class) targetm.secondary_reload (true, src,
1261 (reg_class_t) dclass,
1262 GET_MODE (src), &sri);
1263 /* Check the target hook consistency. */
1264 lra_assert
1265 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1266 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1267 || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1269 if (sregno >= 0)
1270 reg_renumber [sregno] = -1;
1271 if (dregno >= 0)
1272 reg_renumber [dregno] = -1;
1273 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1274 return false;
1275 *change_p = true;
1276 new_reg = NULL_RTX;
1277 if (secondary_class != NO_REGS)
1278 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX,
1279 secondary_class,
1280 "secondary");
1281 start_sequence ();
1282 if (sri.icode == CODE_FOR_nothing)
1283 lra_emit_move (new_reg, src);
1284 else
1286 enum reg_class scratch_class;
1288 scratch_class = (reg_class_from_constraints
1289 (insn_data[sri.icode].operand[2].constraint));
1290 scratch_reg = (lra_create_new_reg_with_unique_value
1291 (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1292 scratch_class, "scratch"));
1293 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1294 src, scratch_reg));
1296 before = get_insns ();
1297 end_sequence ();
1298 lra_process_new_insns (curr_insn, before, NULL, "Inserting the move");
1299 if (new_reg != NULL_RTX)
1300 SET_SRC (curr_insn_set) = new_reg;
1301 else
1303 if (lra_dump_file != NULL)
1305 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1306 dump_insn_slim (lra_dump_file, curr_insn);
1308 lra_set_insn_deleted (curr_insn);
1309 return true;
1311 return false;
1314 /* The following data describe the result of process_alt_operands.
1315 The data are used in curr_insn_transform to generate reloads. */
1317 /* The chosen reg classes which should be used for the corresponding
1318 operands. */
1319 static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1320 /* True if the operand should be the same as another operand and that
1321 other operand does not need a reload. */
1322 static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1323 /* True if the operand does not need a reload. */
1324 static bool goal_alt_win[MAX_RECOG_OPERANDS];
1325 /* True if the operand can be offsetable memory. */
1326 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1327 /* The number of an operand to which given operand can be matched to. */
1328 static int goal_alt_matches[MAX_RECOG_OPERANDS];
1329 /* The number of elements in the following array. */
1330 static int goal_alt_dont_inherit_ops_num;
1331 /* Numbers of operands whose reload pseudos should not be inherited. */
1332 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1333 /* True if the insn commutative operands should be swapped. */
1334 static bool goal_alt_swapped;
1335 /* The chosen insn alternative. */
1336 static int goal_alt_number;
1338 /* True if the corresponding operand is the result of an equivalence
1339 substitution. */
1340 static bool equiv_substition_p[MAX_RECOG_OPERANDS];
1342 /* The following five variables are used to choose the best insn
1343 alternative. They reflect final characteristics of the best
1344 alternative. */
1346 /* Number of necessary reloads and overall cost reflecting the
1347 previous value and other unpleasantness of the best alternative. */
1348 static int best_losers, best_overall;
1349 /* Overall number hard registers used for reloads. For example, on
1350 some targets we need 2 general registers to reload DFmode and only
1351 one floating point register. */
1352 static int best_reload_nregs;
1353 /* Overall number reflecting distances of previous reloading the same
1354 value. The distances are counted from the current BB start. It is
1355 used to improve inheritance chances. */
1356 static int best_reload_sum;
1358 /* True if the current insn should have no correspondingly input or
1359 output reloads. */
1360 static bool no_input_reloads_p, no_output_reloads_p;
1362 /* True if we swapped the commutative operands in the current
1363 insn. */
1364 static int curr_swapped;
1366 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1367 register of class CL. Add any input reloads to list BEFORE. AFTER
1368 is nonnull if *LOC is an automodified value; handle that case by
1369 adding the required output reloads to list AFTER. Return true if
1370 the RTL was changed.
1372 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1373 register. Return false if the address register is correct. */
1374 static bool
1375 process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1376 enum reg_class cl)
1378 int regno;
1379 enum reg_class rclass, new_class;
1380 rtx reg;
1381 rtx new_reg;
1382 machine_mode mode;
1383 bool subreg_p, before_p = false;
1385 subreg_p = GET_CODE (*loc) == SUBREG;
1386 if (subreg_p)
1388 reg = SUBREG_REG (*loc);
1389 mode = GET_MODE (reg);
1391 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1392 between two registers with different classes, but there normally will
1393 be "mov" which transfers element of vector register into the general
1394 register, and this normally will be a subreg which should be reloaded
1395 as a whole. This is particularly likely to be triggered when
1396 -fno-split-wide-types specified. */
1397 if (!REG_P (reg)
1398 || in_class_p (reg, cl, &new_class)
1399 || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode)))
1400 loc = &SUBREG_REG (*loc);
1403 reg = *loc;
1404 mode = GET_MODE (reg);
1405 if (! REG_P (reg))
1407 if (check_only_p)
1408 return true;
1409 /* Always reload memory in an address even if the target supports
1410 such addresses. */
1411 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1412 before_p = true;
1414 else
1416 regno = REGNO (reg);
1417 rclass = get_reg_class (regno);
1418 if (! check_only_p
1419 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1421 if (lra_dump_file != NULL)
1423 fprintf (lra_dump_file,
1424 "Changing pseudo %d in address of insn %u on equiv ",
1425 REGNO (reg), INSN_UID (curr_insn));
1426 dump_value_slim (lra_dump_file, *loc, 1);
1427 fprintf (lra_dump_file, "\n");
1429 *loc = copy_rtx (*loc);
1431 if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1433 if (check_only_p)
1434 return true;
1435 reg = *loc;
1436 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1437 mode, reg, cl, subreg_p, "address", &new_reg))
1438 before_p = true;
1440 else if (new_class != NO_REGS && rclass != new_class)
1442 if (check_only_p)
1443 return true;
1444 lra_change_class (regno, new_class, " Change to", true);
1445 return false;
1447 else
1448 return false;
1450 if (before_p)
1452 push_to_sequence (*before);
1453 lra_emit_move (new_reg, reg);
1454 *before = get_insns ();
1455 end_sequence ();
1457 *loc = new_reg;
1458 if (after != NULL)
1460 start_sequence ();
1461 lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
1462 emit_insn (*after);
1463 *after = get_insns ();
1464 end_sequence ();
1466 return true;
1469 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1470 the insn to be inserted before curr insn. AFTER returns the
1471 the insn to be inserted after curr insn. ORIGREG and NEWREG
1472 are the original reg and new reg for reload. */
1473 static void
1474 insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1475 rtx newreg)
1477 if (before)
1479 push_to_sequence (*before);
1480 lra_emit_move (newreg, origreg);
1481 *before = get_insns ();
1482 end_sequence ();
1484 if (after)
1486 start_sequence ();
1487 lra_emit_move (origreg, newreg);
1488 emit_insn (*after);
1489 *after = get_insns ();
1490 end_sequence ();
1494 static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1495 static bool process_address (int, bool, rtx_insn **, rtx_insn **);
1497 /* Make reloads for subreg in operand NOP with internal subreg mode
1498 REG_MODE, add new reloads for further processing. Return true if
1499 any change was done. */
1500 static bool
1501 simplify_operand_subreg (int nop, machine_mode reg_mode)
1503 int hard_regno;
1504 rtx_insn *before, *after;
1505 machine_mode mode, innermode;
1506 rtx reg, new_reg;
1507 rtx operand = *curr_id->operand_loc[nop];
1508 enum reg_class regclass;
1509 enum op_type type;
1511 before = after = NULL;
1513 if (GET_CODE (operand) != SUBREG)
1514 return false;
1516 mode = GET_MODE (operand);
1517 reg = SUBREG_REG (operand);
1518 innermode = GET_MODE (reg);
1519 type = curr_static_id->operand[nop].type;
1520 if (MEM_P (reg))
1522 const bool addr_was_valid
1523 = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg));
1524 alter_subreg (curr_id->operand_loc[nop], false);
1525 rtx subst = *curr_id->operand_loc[nop];
1526 lra_assert (MEM_P (subst));
1528 if (!addr_was_valid
1529 || valid_address_p (GET_MODE (subst), XEXP (subst, 0),
1530 MEM_ADDR_SPACE (subst))
1531 || ((get_constraint_type (lookup_constraint
1532 (curr_static_id->operand[nop].constraint))
1533 != CT_SPECIAL_MEMORY)
1534 /* We still can reload address and if the address is
1535 valid, we can remove subreg without reloading its
1536 inner memory. */
1537 && valid_address_p (GET_MODE (subst),
1538 regno_reg_rtx
1539 [ira_class_hard_regs
1540 [base_reg_class (GET_MODE (subst),
1541 MEM_ADDR_SPACE (subst),
1542 ADDRESS, SCRATCH)][0]],
1543 MEM_ADDR_SPACE (subst))))
1545 /* If we change the address for a paradoxical subreg of memory, the
1546 new address might violate the necessary alignment or the access
1547 might be slow; take this into consideration. We need not worry
1548 about accesses beyond allocated memory for paradoxical memory
1549 subregs as we don't substitute such equiv memory (see processing
1550 equivalences in function lra_constraints) and because for spilled
1551 pseudos we allocate stack memory enough for the biggest
1552 corresponding paradoxical subreg.
1554 However, do not blindly simplify a (subreg (mem ...)) for
1555 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1556 data into a register when the inner is narrower than outer or
1557 missing important data from memory when the inner is wider than
1558 outer. This rule only applies to modes that are no wider than
1559 a word. */
1560 if (!(maybe_ne (GET_MODE_PRECISION (mode),
1561 GET_MODE_PRECISION (innermode))
1562 && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD)
1563 && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD)
1564 && WORD_REGISTER_OPERATIONS)
1565 && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode)
1566 && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst)))
1567 || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode)
1568 && targetm.slow_unaligned_access (innermode,
1569 MEM_ALIGN (reg)))))
1570 return true;
1572 *curr_id->operand_loc[nop] = operand;
1574 /* But if the address was not valid, we cannot reload the MEM without
1575 reloading the address first. */
1576 if (!addr_was_valid)
1577 process_address (nop, false, &before, &after);
1579 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1580 enum reg_class rclass
1581 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1582 if (get_reload_reg (curr_static_id->operand[nop].type, innermode,
1583 reg, rclass, TRUE, "slow mem", &new_reg))
1585 bool insert_before, insert_after;
1586 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1588 insert_before = (type != OP_OUT
1589 || partial_subreg_p (mode, innermode));
1590 insert_after = type != OP_IN;
1591 insert_move_for_subreg (insert_before ? &before : NULL,
1592 insert_after ? &after : NULL,
1593 reg, new_reg);
1595 SUBREG_REG (operand) = new_reg;
1597 /* Convert to MODE. */
1598 reg = operand;
1599 rclass
1600 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1601 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1602 rclass, TRUE, "slow mem", &new_reg))
1604 bool insert_before, insert_after;
1605 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1607 insert_before = type != OP_OUT;
1608 insert_after = type != OP_IN;
1609 insert_move_for_subreg (insert_before ? &before : NULL,
1610 insert_after ? &after : NULL,
1611 reg, new_reg);
1613 *curr_id->operand_loc[nop] = new_reg;
1614 lra_process_new_insns (curr_insn, before, after,
1615 "Inserting slow mem reload");
1616 return true;
1619 /* If the address was valid and became invalid, prefer to reload
1620 the memory. Typical case is when the index scale should
1621 correspond the memory. */
1622 *curr_id->operand_loc[nop] = operand;
1623 /* Do not return false here as the MEM_P (reg) will be processed
1624 later in this function. */
1626 else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
1628 alter_subreg (curr_id->operand_loc[nop], false);
1629 return true;
1631 else if (CONSTANT_P (reg))
1633 /* Try to simplify subreg of constant. It is usually result of
1634 equivalence substitution. */
1635 if (innermode == VOIDmode
1636 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode)
1637 innermode = curr_static_id->operand[nop].mode;
1638 if ((new_reg = simplify_subreg (mode, reg, innermode,
1639 SUBREG_BYTE (operand))) != NULL_RTX)
1641 *curr_id->operand_loc[nop] = new_reg;
1642 return true;
1645 /* Put constant into memory when we have mixed modes. It generates
1646 a better code in most cases as it does not need a secondary
1647 reload memory. It also prevents LRA looping when LRA is using
1648 secondary reload memory again and again. */
1649 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1650 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1652 SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1653 alter_subreg (curr_id->operand_loc[nop], false);
1654 return true;
1656 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1657 if there may be a problem accessing OPERAND in the outer
1658 mode. */
1659 if ((REG_P (reg)
1660 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1661 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1662 /* Don't reload paradoxical subregs because we could be looping
1663 having repeatedly final regno out of hard regs range. */
1664 && (hard_regno_nregs (hard_regno, innermode)
1665 >= hard_regno_nregs (hard_regno, mode))
1666 && simplify_subreg_regno (hard_regno, innermode,
1667 SUBREG_BYTE (operand), mode) < 0
1668 /* Don't reload subreg for matching reload. It is actually
1669 valid subreg in LRA. */
1670 && ! LRA_SUBREG_P (operand))
1671 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1673 enum reg_class rclass;
1675 if (REG_P (reg))
1676 /* There is a big probability that we will get the same class
1677 for the new pseudo and we will get the same insn which
1678 means infinite looping. So spill the new pseudo. */
1679 rclass = NO_REGS;
1680 else
1681 /* The class will be defined later in curr_insn_transform. */
1682 rclass
1683 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1685 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1686 rclass, TRUE, "subreg reg", &new_reg))
1688 bool insert_before, insert_after;
1689 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1691 insert_before = (type != OP_OUT
1692 || read_modify_subreg_p (operand));
1693 insert_after = (type != OP_IN);
1694 insert_move_for_subreg (insert_before ? &before : NULL,
1695 insert_after ? &after : NULL,
1696 reg, new_reg);
1698 SUBREG_REG (operand) = new_reg;
1699 lra_process_new_insns (curr_insn, before, after,
1700 "Inserting subreg reload");
1701 return true;
1703 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1704 IRA allocates hardreg to the inner pseudo reg according to its mode
1705 instead of the outermode, so the size of the hardreg may not be enough
1706 to contain the outermode operand, in that case we may need to insert
1707 reload for the reg. For the following two types of paradoxical subreg,
1708 we need to insert reload:
1709 1. If the op_type is OP_IN, and the hardreg could not be paired with
1710 other hardreg to contain the outermode operand
1711 (checked by in_hard_reg_set_p), we need to insert the reload.
1712 2. If the op_type is OP_OUT or OP_INOUT.
1714 Here is a paradoxical subreg example showing how the reload is generated:
1716 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1717 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1719 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1720 here, if reg107 is assigned to hardreg R15, because R15 is the last
1721 hardreg, compiler cannot find another hardreg to pair with R15 to
1722 contain TImode data. So we insert a TImode reload reg180 for it.
1723 After reload is inserted:
1725 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1726 (reg:DI 107 [ __comp ])) -1
1727 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1728 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1730 Two reload hard registers will be allocated to reg180 to save TImode data
1731 in LRA_assign. */
1732 else if (REG_P (reg)
1733 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1734 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1735 && (hard_regno_nregs (hard_regno, innermode)
1736 < hard_regno_nregs (hard_regno, mode))
1737 && (regclass = lra_get_allocno_class (REGNO (reg)))
1738 && (type != OP_IN
1739 || !in_hard_reg_set_p (reg_class_contents[regclass],
1740 mode, hard_regno)))
1742 /* The class will be defined later in curr_insn_transform. */
1743 enum reg_class rclass
1744 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1746 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1747 rclass, TRUE, "paradoxical subreg", &new_reg))
1749 rtx subreg;
1750 bool insert_before, insert_after;
1752 PUT_MODE (new_reg, mode);
1753 subreg = gen_lowpart_SUBREG (innermode, new_reg);
1754 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1756 insert_before = (type != OP_OUT);
1757 insert_after = (type != OP_IN);
1758 insert_move_for_subreg (insert_before ? &before : NULL,
1759 insert_after ? &after : NULL,
1760 reg, subreg);
1762 SUBREG_REG (operand) = new_reg;
1763 lra_process_new_insns (curr_insn, before, after,
1764 "Inserting paradoxical subreg reload");
1765 return true;
1767 return false;
1770 /* Return TRUE if X refers for a hard register from SET. */
1771 static bool
1772 uses_hard_regs_p (rtx x, HARD_REG_SET set)
1774 int i, j, x_hard_regno;
1775 machine_mode mode;
1776 const char *fmt;
1777 enum rtx_code code;
1779 if (x == NULL_RTX)
1780 return false;
1781 code = GET_CODE (x);
1782 mode = GET_MODE (x);
1783 if (code == SUBREG)
1785 mode = wider_subreg_mode (x);
1786 x = SUBREG_REG (x);
1787 code = GET_CODE (x);
1790 if (REG_P (x))
1792 x_hard_regno = get_hard_regno (x, true);
1793 return (x_hard_regno >= 0
1794 && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1796 if (MEM_P (x))
1798 struct address_info ad;
1800 decompose_mem_address (&ad, x);
1801 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set))
1802 return true;
1803 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set))
1804 return true;
1806 fmt = GET_RTX_FORMAT (code);
1807 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1809 if (fmt[i] == 'e')
1811 if (uses_hard_regs_p (XEXP (x, i), set))
1812 return true;
1814 else if (fmt[i] == 'E')
1816 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1817 if (uses_hard_regs_p (XVECEXP (x, i, j), set))
1818 return true;
1821 return false;
1824 /* Return true if OP is a spilled pseudo. */
1825 static inline bool
1826 spilled_pseudo_p (rtx op)
1828 return (REG_P (op)
1829 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
1832 /* Return true if X is a general constant. */
1833 static inline bool
1834 general_constant_p (rtx x)
1836 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
1839 static bool
1840 reg_in_class_p (rtx reg, enum reg_class cl)
1842 if (cl == NO_REGS)
1843 return get_reg_class (REGNO (reg)) == NO_REGS;
1844 return in_class_p (reg, cl, NULL);
1847 /* Return true if SET of RCLASS contains no hard regs which can be
1848 used in MODE. */
1849 static bool
1850 prohibited_class_reg_set_mode_p (enum reg_class rclass,
1851 HARD_REG_SET &set,
1852 machine_mode mode)
1854 HARD_REG_SET temp;
1856 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
1857 COPY_HARD_REG_SET (temp, set);
1858 AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs);
1859 return (hard_reg_set_subset_p
1860 (temp, ira_prohibited_class_mode_regs[rclass][mode]));
1864 /* Used to check validity info about small class input operands. It
1865 should be incremented at start of processing an insn
1866 alternative. */
1867 static unsigned int curr_small_class_check = 0;
1869 /* Update number of used inputs of class OP_CLASS for operand NOP.
1870 Return true if we have more such class operands than the number of
1871 available regs. */
1872 static bool
1873 update_and_check_small_class_inputs (int nop, enum reg_class op_class)
1875 static unsigned int small_class_check[LIM_REG_CLASSES];
1876 static int small_class_input_nums[LIM_REG_CLASSES];
1878 if (SMALL_REGISTER_CLASS_P (op_class)
1879 /* We are interesting in classes became small because of fixing
1880 some hard regs, e.g. by an user through GCC options. */
1881 && hard_reg_set_intersect_p (reg_class_contents[op_class],
1882 ira_no_alloc_regs)
1883 && (curr_static_id->operand[nop].type != OP_OUT
1884 || curr_static_id->operand[nop].early_clobber))
1886 if (small_class_check[op_class] == curr_small_class_check)
1887 small_class_input_nums[op_class]++;
1888 else
1890 small_class_check[op_class] = curr_small_class_check;
1891 small_class_input_nums[op_class] = 1;
1893 if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class])
1894 return true;
1896 return false;
1899 /* Major function to choose the current insn alternative and what
1900 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1901 negative we should consider only this alternative. Return false if
1902 we can not choose the alternative or find how to reload the
1903 operands. */
1904 static bool
1905 process_alt_operands (int only_alternative)
1907 bool ok_p = false;
1908 int nop, overall, nalt;
1909 int n_alternatives = curr_static_id->n_alternatives;
1910 int n_operands = curr_static_id->n_operands;
1911 /* LOSERS counts the operands that don't fit this alternative and
1912 would require loading. */
1913 int losers;
1914 int addr_losers;
1915 /* REJECT is a count of how undesirable this alternative says it is
1916 if any reloading is required. If the alternative matches exactly
1917 then REJECT is ignored, but otherwise it gets this much counted
1918 against it in addition to the reloading needed. */
1919 int reject;
1920 /* This is defined by '!' or '?' alternative constraint and added to
1921 reject. But in some cases it can be ignored. */
1922 int static_reject;
1923 int op_reject;
1924 /* The number of elements in the following array. */
1925 int early_clobbered_regs_num;
1926 /* Numbers of operands which are early clobber registers. */
1927 int early_clobbered_nops[MAX_RECOG_OPERANDS];
1928 enum reg_class curr_alt[MAX_RECOG_OPERANDS];
1929 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
1930 bool curr_alt_match_win[MAX_RECOG_OPERANDS];
1931 bool curr_alt_win[MAX_RECOG_OPERANDS];
1932 bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
1933 int curr_alt_matches[MAX_RECOG_OPERANDS];
1934 /* The number of elements in the following array. */
1935 int curr_alt_dont_inherit_ops_num;
1936 /* Numbers of operands whose reload pseudos should not be inherited. */
1937 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1938 rtx op;
1939 /* The register when the operand is a subreg of register, otherwise the
1940 operand itself. */
1941 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
1942 /* The register if the operand is a register or subreg of register,
1943 otherwise NULL. */
1944 rtx operand_reg[MAX_RECOG_OPERANDS];
1945 int hard_regno[MAX_RECOG_OPERANDS];
1946 machine_mode biggest_mode[MAX_RECOG_OPERANDS];
1947 int reload_nregs, reload_sum;
1948 bool costly_p;
1949 enum reg_class cl;
1951 /* Calculate some data common for all alternatives to speed up the
1952 function. */
1953 for (nop = 0; nop < n_operands; nop++)
1955 rtx reg;
1957 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
1958 /* The real hard regno of the operand after the allocation. */
1959 hard_regno[nop] = get_hard_regno (op, true);
1961 operand_reg[nop] = reg = op;
1962 biggest_mode[nop] = GET_MODE (op);
1963 if (GET_CODE (op) == SUBREG)
1965 biggest_mode[nop] = wider_subreg_mode (op);
1966 operand_reg[nop] = reg = SUBREG_REG (op);
1968 if (! REG_P (reg))
1969 operand_reg[nop] = NULL_RTX;
1970 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1971 || ((int) REGNO (reg)
1972 == lra_get_elimination_hard_regno (REGNO (reg))))
1973 no_subreg_reg_operand[nop] = reg;
1974 else
1975 operand_reg[nop] = no_subreg_reg_operand[nop]
1976 /* Just use natural mode for elimination result. It should
1977 be enough for extra constraints hooks. */
1978 = regno_reg_rtx[hard_regno[nop]];
1981 /* The constraints are made of several alternatives. Each operand's
1982 constraint looks like foo,bar,... with commas separating the
1983 alternatives. The first alternatives for all operands go
1984 together, the second alternatives go together, etc.
1986 First loop over alternatives. */
1987 alternative_mask preferred = curr_id->preferred_alternatives;
1988 if (only_alternative >= 0)
1989 preferred &= ALTERNATIVE_BIT (only_alternative);
1991 for (nalt = 0; nalt < n_alternatives; nalt++)
1993 /* Loop over operands for one constraint alternative. */
1994 if (!TEST_BIT (preferred, nalt))
1995 continue;
1997 curr_small_class_check++;
1998 overall = losers = addr_losers = 0;
1999 static_reject = reject = reload_nregs = reload_sum = 0;
2000 for (nop = 0; nop < n_operands; nop++)
2002 int inc = (curr_static_id
2003 ->operand_alternative[nalt * n_operands + nop].reject);
2004 if (lra_dump_file != NULL && inc != 0)
2005 fprintf (lra_dump_file,
2006 " Staticly defined alt reject+=%d\n", inc);
2007 static_reject += inc;
2009 reject += static_reject;
2010 early_clobbered_regs_num = 0;
2012 for (nop = 0; nop < n_operands; nop++)
2014 const char *p;
2015 char *end;
2016 int len, c, m, i, opalt_num, this_alternative_matches;
2017 bool win, did_match, offmemok, early_clobber_p;
2018 /* false => this operand can be reloaded somehow for this
2019 alternative. */
2020 bool badop;
2021 /* true => this operand can be reloaded if the alternative
2022 allows regs. */
2023 bool winreg;
2024 /* True if a constant forced into memory would be OK for
2025 this operand. */
2026 bool constmemok;
2027 enum reg_class this_alternative, this_costly_alternative;
2028 HARD_REG_SET this_alternative_set, this_costly_alternative_set;
2029 bool this_alternative_match_win, this_alternative_win;
2030 bool this_alternative_offmemok;
2031 bool scratch_p;
2032 machine_mode mode;
2033 enum constraint_num cn;
2035 opalt_num = nalt * n_operands + nop;
2036 if (curr_static_id->operand_alternative[opalt_num].anything_ok)
2038 /* Fast track for no constraints at all. */
2039 curr_alt[nop] = NO_REGS;
2040 CLEAR_HARD_REG_SET (curr_alt_set[nop]);
2041 curr_alt_win[nop] = true;
2042 curr_alt_match_win[nop] = false;
2043 curr_alt_offmemok[nop] = false;
2044 curr_alt_matches[nop] = -1;
2045 continue;
2048 op = no_subreg_reg_operand[nop];
2049 mode = curr_operand_mode[nop];
2051 win = did_match = winreg = offmemok = constmemok = false;
2052 badop = true;
2054 early_clobber_p = false;
2055 p = curr_static_id->operand_alternative[opalt_num].constraint;
2057 this_costly_alternative = this_alternative = NO_REGS;
2058 /* We update set of possible hard regs besides its class
2059 because reg class might be inaccurate. For example,
2060 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2061 is translated in HI_REGS because classes are merged by
2062 pairs and there is no accurate intermediate class. */
2063 CLEAR_HARD_REG_SET (this_alternative_set);
2064 CLEAR_HARD_REG_SET (this_costly_alternative_set);
2065 this_alternative_win = false;
2066 this_alternative_match_win = false;
2067 this_alternative_offmemok = false;
2068 this_alternative_matches = -1;
2070 /* An empty constraint should be excluded by the fast
2071 track. */
2072 lra_assert (*p != 0 && *p != ',');
2074 op_reject = 0;
2075 /* Scan this alternative's specs for this operand; set WIN
2076 if the operand fits any letter in this alternative.
2077 Otherwise, clear BADOP if this operand could fit some
2078 letter after reloads, or set WINREG if this operand could
2079 fit after reloads provided the constraint allows some
2080 registers. */
2081 costly_p = false;
2084 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
2086 case '\0':
2087 len = 0;
2088 break;
2089 case ',':
2090 c = '\0';
2091 break;
2093 case '&':
2094 early_clobber_p = true;
2095 break;
2097 case '$':
2098 op_reject += LRA_MAX_REJECT;
2099 break;
2100 case '^':
2101 op_reject += LRA_LOSER_COST_FACTOR;
2102 break;
2104 case '#':
2105 /* Ignore rest of this alternative. */
2106 c = '\0';
2107 break;
2109 case '0': case '1': case '2': case '3': case '4':
2110 case '5': case '6': case '7': case '8': case '9':
2112 int m_hregno;
2113 bool match_p;
2115 m = strtoul (p, &end, 10);
2116 p = end;
2117 len = 0;
2118 lra_assert (nop > m);
2120 /* Reject matches if we don't know which operand is
2121 bigger. This situation would arguably be a bug in
2122 an .md pattern, but could also occur in a user asm. */
2123 if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]),
2124 GET_MODE_SIZE (biggest_mode[nop])))
2125 break;
2127 this_alternative_matches = m;
2128 m_hregno = get_hard_regno (*curr_id->operand_loc[m], false);
2129 /* We are supposed to match a previous operand.
2130 If we do, we win if that one did. If we do
2131 not, count both of the operands as losers.
2132 (This is too conservative, since most of the
2133 time only a single reload insn will be needed
2134 to make the two operands win. As a result,
2135 this alternative may be rejected when it is
2136 actually desirable.) */
2137 match_p = false;
2138 if (operands_match_p (*curr_id->operand_loc[nop],
2139 *curr_id->operand_loc[m], m_hregno))
2141 /* We should reject matching of an early
2142 clobber operand if the matching operand is
2143 not dying in the insn. */
2144 if (! curr_static_id->operand[m].early_clobber
2145 || operand_reg[nop] == NULL_RTX
2146 || (find_regno_note (curr_insn, REG_DEAD,
2147 REGNO (op))
2148 || REGNO (op) == REGNO (operand_reg[m])))
2149 match_p = true;
2151 if (match_p)
2153 /* If we are matching a non-offsettable
2154 address where an offsettable address was
2155 expected, then we must reject this
2156 combination, because we can't reload
2157 it. */
2158 if (curr_alt_offmemok[m]
2159 && MEM_P (*curr_id->operand_loc[m])
2160 && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
2161 continue;
2163 else
2165 /* Operands don't match. Both operands must
2166 allow a reload register, otherwise we
2167 cannot make them match. */
2168 if (curr_alt[m] == NO_REGS)
2169 break;
2170 /* Retroactively mark the operand we had to
2171 match as a loser, if it wasn't already and
2172 it wasn't matched to a register constraint
2173 (e.g it might be matched by memory). */
2174 if (curr_alt_win[m]
2175 && (operand_reg[m] == NULL_RTX
2176 || hard_regno[m] < 0))
2178 losers++;
2179 reload_nregs
2180 += (ira_reg_class_max_nregs[curr_alt[m]]
2181 [GET_MODE (*curr_id->operand_loc[m])]);
2184 /* Prefer matching earlyclobber alternative as
2185 it results in less hard regs required for
2186 the insn than a non-matching earlyclobber
2187 alternative. */
2188 if (curr_static_id->operand[m].early_clobber)
2190 if (lra_dump_file != NULL)
2191 fprintf
2192 (lra_dump_file,
2193 " %d Matching earlyclobber alt:"
2194 " reject--\n",
2195 nop);
2196 reject--;
2198 /* Otherwise we prefer no matching
2199 alternatives because it gives more freedom
2200 in RA. */
2201 else if (operand_reg[nop] == NULL_RTX
2202 || (find_regno_note (curr_insn, REG_DEAD,
2203 REGNO (operand_reg[nop]))
2204 == NULL_RTX))
2206 if (lra_dump_file != NULL)
2207 fprintf
2208 (lra_dump_file,
2209 " %d Matching alt: reject+=2\n",
2210 nop);
2211 reject += 2;
2214 /* If we have to reload this operand and some
2215 previous operand also had to match the same
2216 thing as this operand, we don't know how to do
2217 that. */
2218 if (!match_p || !curr_alt_win[m])
2220 for (i = 0; i < nop; i++)
2221 if (curr_alt_matches[i] == m)
2222 break;
2223 if (i < nop)
2224 break;
2226 else
2227 did_match = true;
2229 /* This can be fixed with reloads if the operand
2230 we are supposed to match can be fixed with
2231 reloads. */
2232 badop = false;
2233 this_alternative = curr_alt[m];
2234 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]);
2235 winreg = this_alternative != NO_REGS;
2236 break;
2239 case 'g':
2240 if (MEM_P (op)
2241 || general_constant_p (op)
2242 || spilled_pseudo_p (op))
2243 win = true;
2244 cl = GENERAL_REGS;
2245 goto reg;
2247 default:
2248 cn = lookup_constraint (p);
2249 switch (get_constraint_type (cn))
2251 case CT_REGISTER:
2252 cl = reg_class_for_constraint (cn);
2253 if (cl != NO_REGS)
2254 goto reg;
2255 break;
2257 case CT_CONST_INT:
2258 if (CONST_INT_P (op)
2259 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
2260 win = true;
2261 break;
2263 case CT_MEMORY:
2264 if (MEM_P (op)
2265 && satisfies_memory_constraint_p (op, cn))
2266 win = true;
2267 else if (spilled_pseudo_p (op))
2268 win = true;
2270 /* If we didn't already win, we can reload constants
2271 via force_const_mem or put the pseudo value into
2272 memory, or make other memory by reloading the
2273 address like for 'o'. */
2274 if (CONST_POOL_OK_P (mode, op)
2275 || MEM_P (op) || REG_P (op)
2276 /* We can restore the equiv insn by a
2277 reload. */
2278 || equiv_substition_p[nop])
2279 badop = false;
2280 constmemok = true;
2281 offmemok = true;
2282 break;
2284 case CT_ADDRESS:
2285 /* If we didn't already win, we can reload the address
2286 into a base register. */
2287 if (satisfies_address_constraint_p (op, cn))
2288 win = true;
2289 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2290 ADDRESS, SCRATCH);
2291 badop = false;
2292 goto reg;
2294 case CT_FIXED_FORM:
2295 if (constraint_satisfied_p (op, cn))
2296 win = true;
2297 break;
2299 case CT_SPECIAL_MEMORY:
2300 if (MEM_P (op)
2301 && satisfies_memory_constraint_p (op, cn))
2302 win = true;
2303 else if (spilled_pseudo_p (op))
2304 win = true;
2305 break;
2307 break;
2309 reg:
2310 this_alternative = reg_class_subunion[this_alternative][cl];
2311 IOR_HARD_REG_SET (this_alternative_set,
2312 reg_class_contents[cl]);
2313 if (costly_p)
2315 this_costly_alternative
2316 = reg_class_subunion[this_costly_alternative][cl];
2317 IOR_HARD_REG_SET (this_costly_alternative_set,
2318 reg_class_contents[cl]);
2320 if (mode == BLKmode)
2321 break;
2322 winreg = true;
2323 if (REG_P (op))
2325 if (hard_regno[nop] >= 0
2326 && in_hard_reg_set_p (this_alternative_set,
2327 mode, hard_regno[nop]))
2328 win = true;
2329 else if (hard_regno[nop] < 0
2330 && in_class_p (op, this_alternative, NULL))
2331 win = true;
2333 break;
2335 if (c != ' ' && c != '\t')
2336 costly_p = c == '*';
2338 while ((p += len), c);
2340 scratch_p = (operand_reg[nop] != NULL_RTX
2341 && lra_former_scratch_p (REGNO (operand_reg[nop])));
2342 /* Record which operands fit this alternative. */
2343 if (win)
2345 this_alternative_win = true;
2346 if (operand_reg[nop] != NULL_RTX)
2348 if (hard_regno[nop] >= 0)
2350 if (in_hard_reg_set_p (this_costly_alternative_set,
2351 mode, hard_regno[nop]))
2353 if (lra_dump_file != NULL)
2354 fprintf (lra_dump_file,
2355 " %d Costly set: reject++\n",
2356 nop);
2357 reject++;
2360 else
2362 /* Prefer won reg to spilled pseudo under other
2363 equal conditions for possibe inheritance. */
2364 if (! scratch_p)
2366 if (lra_dump_file != NULL)
2367 fprintf
2368 (lra_dump_file,
2369 " %d Non pseudo reload: reject++\n",
2370 nop);
2371 reject++;
2373 if (in_class_p (operand_reg[nop],
2374 this_costly_alternative, NULL))
2376 if (lra_dump_file != NULL)
2377 fprintf
2378 (lra_dump_file,
2379 " %d Non pseudo costly reload:"
2380 " reject++\n",
2381 nop);
2382 reject++;
2385 /* We simulate the behavior of old reload here.
2386 Although scratches need hard registers and it
2387 might result in spilling other pseudos, no reload
2388 insns are generated for the scratches. So it
2389 might cost something but probably less than old
2390 reload pass believes. */
2391 if (scratch_p)
2393 if (lra_dump_file != NULL)
2394 fprintf (lra_dump_file,
2395 " %d Scratch win: reject+=2\n",
2396 nop);
2397 reject += 2;
2401 else if (did_match)
2402 this_alternative_match_win = true;
2403 else
2405 int const_to_mem = 0;
2406 bool no_regs_p;
2408 reject += op_reject;
2409 /* Never do output reload of stack pointer. It makes
2410 impossible to do elimination when SP is changed in
2411 RTL. */
2412 if (op == stack_pointer_rtx && ! frame_pointer_needed
2413 && curr_static_id->operand[nop].type != OP_IN)
2414 goto fail;
2416 /* If this alternative asks for a specific reg class, see if there
2417 is at least one allocatable register in that class. */
2418 no_regs_p
2419 = (this_alternative == NO_REGS
2420 || (hard_reg_set_subset_p
2421 (reg_class_contents[this_alternative],
2422 lra_no_alloc_regs)));
2424 /* For asms, verify that the class for this alternative is possible
2425 for the mode that is specified. */
2426 if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2428 int i;
2429 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2430 if (targetm.hard_regno_mode_ok (i, mode)
2431 && in_hard_reg_set_p (reg_class_contents[this_alternative],
2432 mode, i))
2433 break;
2434 if (i == FIRST_PSEUDO_REGISTER)
2435 winreg = false;
2438 /* If this operand accepts a register, and if the
2439 register class has at least one allocatable register,
2440 then this operand can be reloaded. */
2441 if (winreg && !no_regs_p)
2442 badop = false;
2444 if (badop)
2446 if (lra_dump_file != NULL)
2447 fprintf (lra_dump_file,
2448 " alt=%d: Bad operand -- refuse\n",
2449 nalt);
2450 goto fail;
2453 if (this_alternative != NO_REGS)
2455 HARD_REG_SET available_regs;
2457 COPY_HARD_REG_SET (available_regs,
2458 reg_class_contents[this_alternative]);
2459 AND_COMPL_HARD_REG_SET
2460 (available_regs,
2461 ira_prohibited_class_mode_regs[this_alternative][mode]);
2462 AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
2463 if (hard_reg_set_empty_p (available_regs))
2465 /* There are no hard regs holding a value of given
2466 mode. */
2467 if (offmemok)
2469 this_alternative = NO_REGS;
2470 if (lra_dump_file != NULL)
2471 fprintf (lra_dump_file,
2472 " %d Using memory because of"
2473 " a bad mode: reject+=2\n",
2474 nop);
2475 reject += 2;
2477 else
2479 if (lra_dump_file != NULL)
2480 fprintf (lra_dump_file,
2481 " alt=%d: Wrong mode -- refuse\n",
2482 nalt);
2483 goto fail;
2488 /* If not assigned pseudo has a class which a subset of
2489 required reg class, it is a less costly alternative
2490 as the pseudo still can get a hard reg of necessary
2491 class. */
2492 if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
2493 && (cl = get_reg_class (REGNO (op))) != NO_REGS
2494 && ira_class_subset_p[this_alternative][cl])
2496 if (lra_dump_file != NULL)
2497 fprintf
2498 (lra_dump_file,
2499 " %d Super set class reg: reject-=3\n", nop);
2500 reject -= 3;
2503 this_alternative_offmemok = offmemok;
2504 if (this_costly_alternative != NO_REGS)
2506 if (lra_dump_file != NULL)
2507 fprintf (lra_dump_file,
2508 " %d Costly loser: reject++\n", nop);
2509 reject++;
2511 /* If the operand is dying, has a matching constraint,
2512 and satisfies constraints of the matched operand
2513 which failed to satisfy the own constraints, most probably
2514 the reload for this operand will be gone. */
2515 if (this_alternative_matches >= 0
2516 && !curr_alt_win[this_alternative_matches]
2517 && REG_P (op)
2518 && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2519 && (hard_regno[nop] >= 0
2520 ? in_hard_reg_set_p (this_alternative_set,
2521 mode, hard_regno[nop])
2522 : in_class_p (op, this_alternative, NULL)))
2524 if (lra_dump_file != NULL)
2525 fprintf
2526 (lra_dump_file,
2527 " %d Dying matched operand reload: reject++\n",
2528 nop);
2529 reject++;
2531 else
2533 /* Strict_low_part requires to reload the register
2534 not the sub-register. In this case we should
2535 check that a final reload hard reg can hold the
2536 value mode. */
2537 if (curr_static_id->operand[nop].strict_low
2538 && REG_P (op)
2539 && hard_regno[nop] < 0
2540 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2541 && ira_class_hard_regs_num[this_alternative] > 0
2542 && (!targetm.hard_regno_mode_ok
2543 (ira_class_hard_regs[this_alternative][0],
2544 GET_MODE (*curr_id->operand_loc[nop]))))
2546 if (lra_dump_file != NULL)
2547 fprintf
2548 (lra_dump_file,
2549 " alt=%d: Strict low subreg reload -- refuse\n",
2550 nalt);
2551 goto fail;
2553 losers++;
2555 if (operand_reg[nop] != NULL_RTX
2556 /* Output operands and matched input operands are
2557 not inherited. The following conditions do not
2558 exactly describe the previous statement but they
2559 are pretty close. */
2560 && curr_static_id->operand[nop].type != OP_OUT
2561 && (this_alternative_matches < 0
2562 || curr_static_id->operand[nop].type != OP_IN))
2564 int last_reload = (lra_reg_info[ORIGINAL_REGNO
2565 (operand_reg[nop])]
2566 .last_reload);
2568 /* The value of reload_sum has sense only if we
2569 process insns in their order. It happens only on
2570 the first constraints sub-pass when we do most of
2571 reload work. */
2572 if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2573 reload_sum += last_reload - bb_reload_num;
2575 /* If this is a constant that is reloaded into the
2576 desired class by copying it to memory first, count
2577 that as another reload. This is consistent with
2578 other code and is required to avoid choosing another
2579 alternative when the constant is moved into memory.
2580 Note that the test here is precisely the same as in
2581 the code below that calls force_const_mem. */
2582 if (CONST_POOL_OK_P (mode, op)
2583 && ((targetm.preferred_reload_class
2584 (op, this_alternative) == NO_REGS)
2585 || no_input_reloads_p))
2587 const_to_mem = 1;
2588 if (! no_regs_p)
2589 losers++;
2592 /* Alternative loses if it requires a type of reload not
2593 permitted for this insn. We can always reload
2594 objects with a REG_UNUSED note. */
2595 if ((curr_static_id->operand[nop].type != OP_IN
2596 && no_output_reloads_p
2597 && ! find_reg_note (curr_insn, REG_UNUSED, op))
2598 || (curr_static_id->operand[nop].type != OP_OUT
2599 && no_input_reloads_p && ! const_to_mem)
2600 || (this_alternative_matches >= 0
2601 && (no_input_reloads_p
2602 || (no_output_reloads_p
2603 && (curr_static_id->operand
2604 [this_alternative_matches].type != OP_IN)
2605 && ! find_reg_note (curr_insn, REG_UNUSED,
2606 no_subreg_reg_operand
2607 [this_alternative_matches])))))
2609 if (lra_dump_file != NULL)
2610 fprintf
2611 (lra_dump_file,
2612 " alt=%d: No input/otput reload -- refuse\n",
2613 nalt);
2614 goto fail;
2617 /* Alternative loses if it required class pseudo can not
2618 hold value of required mode. Such insns can be
2619 described by insn definitions with mode iterators. */
2620 if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
2621 && ! hard_reg_set_empty_p (this_alternative_set)
2622 /* It is common practice for constraints to use a
2623 class which does not have actually enough regs to
2624 hold the value (e.g. x86 AREG for mode requiring
2625 more one general reg). Therefore we have 2
2626 conditions to check that the reload pseudo can
2627 not hold the mode value. */
2628 && (!targetm.hard_regno_mode_ok
2629 (ira_class_hard_regs[this_alternative][0],
2630 GET_MODE (*curr_id->operand_loc[nop])))
2631 /* The above condition is not enough as the first
2632 reg in ira_class_hard_regs can be not aligned for
2633 multi-words mode values. */
2634 && (prohibited_class_reg_set_mode_p
2635 (this_alternative, this_alternative_set,
2636 GET_MODE (*curr_id->operand_loc[nop]))))
2638 if (lra_dump_file != NULL)
2639 fprintf (lra_dump_file,
2640 " alt=%d: reload pseudo for op %d "
2641 " can not hold the mode value -- refuse\n",
2642 nalt, nop);
2643 goto fail;
2646 /* Check strong discouragement of reload of non-constant
2647 into class THIS_ALTERNATIVE. */
2648 if (! CONSTANT_P (op) && ! no_regs_p
2649 && (targetm.preferred_reload_class
2650 (op, this_alternative) == NO_REGS
2651 || (curr_static_id->operand[nop].type == OP_OUT
2652 && (targetm.preferred_output_reload_class
2653 (op, this_alternative) == NO_REGS))))
2655 if (lra_dump_file != NULL)
2656 fprintf (lra_dump_file,
2657 " %d Non-prefered reload: reject+=%d\n",
2658 nop, LRA_MAX_REJECT);
2659 reject += LRA_MAX_REJECT;
2662 if (! (MEM_P (op) && offmemok)
2663 && ! (const_to_mem && constmemok))
2665 /* We prefer to reload pseudos over reloading other
2666 things, since such reloads may be able to be
2667 eliminated later. So bump REJECT in other cases.
2668 Don't do this in the case where we are forcing a
2669 constant into memory and it will then win since
2670 we don't want to have a different alternative
2671 match then. */
2672 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2674 if (lra_dump_file != NULL)
2675 fprintf
2676 (lra_dump_file,
2677 " %d Non-pseudo reload: reject+=2\n",
2678 nop);
2679 reject += 2;
2682 if (! no_regs_p)
2683 reload_nregs
2684 += ira_reg_class_max_nregs[this_alternative][mode];
2686 if (SMALL_REGISTER_CLASS_P (this_alternative))
2688 if (lra_dump_file != NULL)
2689 fprintf
2690 (lra_dump_file,
2691 " %d Small class reload: reject+=%d\n",
2692 nop, LRA_LOSER_COST_FACTOR / 2);
2693 reject += LRA_LOSER_COST_FACTOR / 2;
2697 /* We are trying to spill pseudo into memory. It is
2698 usually more costly than moving to a hard register
2699 although it might takes the same number of
2700 reloads.
2702 Non-pseudo spill may happen also. Suppose a target allows both
2703 register and memory in the operand constraint alternatives,
2704 then it's typical that an eliminable register has a substition
2705 of "base + offset" which can either be reloaded by a simple
2706 "new_reg <= base + offset" which will match the register
2707 constraint, or a similar reg addition followed by further spill
2708 to and reload from memory which will match the memory
2709 constraint, but this memory spill will be much more costly
2710 usually.
2712 Code below increases the reject for both pseudo and non-pseudo
2713 spill. */
2714 if (no_regs_p
2715 && !(MEM_P (op) && offmemok)
2716 && !(REG_P (op) && hard_regno[nop] < 0))
2718 if (lra_dump_file != NULL)
2719 fprintf
2720 (lra_dump_file,
2721 " %d Spill %spseudo into memory: reject+=3\n",
2722 nop, REG_P (op) ? "" : "Non-");
2723 reject += 3;
2724 if (VECTOR_MODE_P (mode))
2726 /* Spilling vectors into memory is usually more
2727 costly as they contain big values. */
2728 if (lra_dump_file != NULL)
2729 fprintf
2730 (lra_dump_file,
2731 " %d Spill vector pseudo: reject+=2\n",
2732 nop);
2733 reject += 2;
2737 /* When we use an operand requiring memory in given
2738 alternative, the insn should write *and* read the
2739 value to/from memory it is costly in comparison with
2740 an insn alternative which does not use memory
2741 (e.g. register or immediate operand). We exclude
2742 memory operand for such case as we can satisfy the
2743 memory constraints by reloading address. */
2744 if (no_regs_p && offmemok && !MEM_P (op))
2746 if (lra_dump_file != NULL)
2747 fprintf
2748 (lra_dump_file,
2749 " Using memory insn operand %d: reject+=3\n",
2750 nop);
2751 reject += 3;
2754 /* If reload requires moving value through secondary
2755 memory, it will need one more insn at least. */
2756 if (this_alternative != NO_REGS
2757 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
2758 && ((curr_static_id->operand[nop].type != OP_OUT
2759 && targetm.secondary_memory_needed (GET_MODE (op), cl,
2760 this_alternative))
2761 || (curr_static_id->operand[nop].type != OP_IN
2762 && (targetm.secondary_memory_needed
2763 (GET_MODE (op), this_alternative, cl)))))
2764 losers++;
2766 /* Input reloads can be inherited more often than output
2767 reloads can be removed, so penalize output
2768 reloads. */
2769 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
2771 if (lra_dump_file != NULL)
2772 fprintf
2773 (lra_dump_file,
2774 " %d Non input pseudo reload: reject++\n",
2775 nop);
2776 reject++;
2779 if (MEM_P (op) && offmemok)
2780 addr_losers++;
2781 else if (curr_static_id->operand[nop].type == OP_INOUT)
2783 if (lra_dump_file != NULL)
2784 fprintf
2785 (lra_dump_file,
2786 " %d Input/Output reload: reject+=%d\n",
2787 nop, LRA_LOSER_COST_FACTOR);
2788 reject += LRA_LOSER_COST_FACTOR;
2792 if (early_clobber_p && ! scratch_p)
2794 if (lra_dump_file != NULL)
2795 fprintf (lra_dump_file,
2796 " %d Early clobber: reject++\n", nop);
2797 reject++;
2799 /* ??? We check early clobbers after processing all operands
2800 (see loop below) and there we update the costs more.
2801 Should we update the cost (may be approximately) here
2802 because of early clobber register reloads or it is a rare
2803 or non-important thing to be worth to do it. */
2804 overall = (losers * LRA_LOSER_COST_FACTOR + reject
2805 - (addr_losers == losers ? static_reject : 0));
2806 if ((best_losers == 0 || losers != 0) && best_overall < overall)
2808 if (lra_dump_file != NULL)
2809 fprintf (lra_dump_file,
2810 " alt=%d,overall=%d,losers=%d -- refuse\n",
2811 nalt, overall, losers);
2812 goto fail;
2815 if (update_and_check_small_class_inputs (nop, this_alternative))
2817 if (lra_dump_file != NULL)
2818 fprintf (lra_dump_file,
2819 " alt=%d, not enough small class regs -- refuse\n",
2820 nalt);
2821 goto fail;
2823 curr_alt[nop] = this_alternative;
2824 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set);
2825 curr_alt_win[nop] = this_alternative_win;
2826 curr_alt_match_win[nop] = this_alternative_match_win;
2827 curr_alt_offmemok[nop] = this_alternative_offmemok;
2828 curr_alt_matches[nop] = this_alternative_matches;
2830 if (this_alternative_matches >= 0
2831 && !did_match && !this_alternative_win)
2832 curr_alt_win[this_alternative_matches] = false;
2834 if (early_clobber_p && operand_reg[nop] != NULL_RTX)
2835 early_clobbered_nops[early_clobbered_regs_num++] = nop;
2838 if (curr_insn_set != NULL_RTX && n_operands == 2
2839 /* Prevent processing non-move insns. */
2840 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
2841 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
2842 && ((! curr_alt_win[0] && ! curr_alt_win[1]
2843 && REG_P (no_subreg_reg_operand[0])
2844 && REG_P (no_subreg_reg_operand[1])
2845 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2846 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
2847 || (! curr_alt_win[0] && curr_alt_win[1]
2848 && REG_P (no_subreg_reg_operand[1])
2849 /* Check that we reload memory not the memory
2850 address. */
2851 && ! (curr_alt_offmemok[0]
2852 && MEM_P (no_subreg_reg_operand[0]))
2853 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
2854 || (curr_alt_win[0] && ! curr_alt_win[1]
2855 && REG_P (no_subreg_reg_operand[0])
2856 /* Check that we reload memory not the memory
2857 address. */
2858 && ! (curr_alt_offmemok[1]
2859 && MEM_P (no_subreg_reg_operand[1]))
2860 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
2861 && (! CONST_POOL_OK_P (curr_operand_mode[1],
2862 no_subreg_reg_operand[1])
2863 || (targetm.preferred_reload_class
2864 (no_subreg_reg_operand[1],
2865 (enum reg_class) curr_alt[1]) != NO_REGS))
2866 /* If it is a result of recent elimination in move
2867 insn we can transform it into an add still by
2868 using this alternative. */
2869 && GET_CODE (no_subreg_reg_operand[1]) != PLUS
2870 /* Likewise if the source has been replaced with an
2871 equivalent value. This only happens once -- the reload
2872 will use the equivalent value instead of the register it
2873 replaces -- so there should be no danger of cycling. */
2874 && !equiv_substition_p[1])))
2876 /* We have a move insn and a new reload insn will be similar
2877 to the current insn. We should avoid such situation as
2878 it results in LRA cycling. */
2879 if (lra_dump_file != NULL)
2880 fprintf (lra_dump_file,
2881 " Cycle danger: overall += LRA_MAX_REJECT\n");
2882 overall += LRA_MAX_REJECT;
2884 ok_p = true;
2885 curr_alt_dont_inherit_ops_num = 0;
2886 for (nop = 0; nop < early_clobbered_regs_num; nop++)
2888 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
2889 HARD_REG_SET temp_set;
2891 i = early_clobbered_nops[nop];
2892 if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
2893 || hard_regno[i] < 0)
2894 continue;
2895 lra_assert (operand_reg[i] != NULL_RTX);
2896 clobbered_hard_regno = hard_regno[i];
2897 CLEAR_HARD_REG_SET (temp_set);
2898 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
2899 first_conflict_j = last_conflict_j = -1;
2900 for (j = 0; j < n_operands; j++)
2901 if (j == i
2902 /* We don't want process insides of match_operator and
2903 match_parallel because otherwise we would process
2904 their operands once again generating a wrong
2905 code. */
2906 || curr_static_id->operand[j].is_operator)
2907 continue;
2908 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
2909 || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
2910 continue;
2911 /* If we don't reload j-th operand, check conflicts. */
2912 else if ((curr_alt_win[j] || curr_alt_match_win[j])
2913 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
2915 if (first_conflict_j < 0)
2916 first_conflict_j = j;
2917 last_conflict_j = j;
2919 if (last_conflict_j < 0)
2920 continue;
2921 /* If earlyclobber operand conflicts with another
2922 non-matching operand which is actually the same register
2923 as the earlyclobber operand, it is better to reload the
2924 another operand as an operand matching the earlyclobber
2925 operand can be also the same. */
2926 if (first_conflict_j == last_conflict_j
2927 && operand_reg[last_conflict_j] != NULL_RTX
2928 && ! curr_alt_match_win[last_conflict_j]
2929 && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j]))
2931 curr_alt_win[last_conflict_j] = false;
2932 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
2933 = last_conflict_j;
2934 losers++;
2935 /* Early clobber was already reflected in REJECT. */
2936 lra_assert (reject > 0);
2937 if (lra_dump_file != NULL)
2938 fprintf
2939 (lra_dump_file,
2940 " %d Conflict early clobber reload: reject--\n",
2942 reject--;
2943 overall += LRA_LOSER_COST_FACTOR - 1;
2945 else
2947 /* We need to reload early clobbered register and the
2948 matched registers. */
2949 for (j = 0; j < n_operands; j++)
2950 if (curr_alt_matches[j] == i)
2952 curr_alt_match_win[j] = false;
2953 losers++;
2954 overall += LRA_LOSER_COST_FACTOR;
2956 if (! curr_alt_match_win[i])
2957 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
2958 else
2960 /* Remember pseudos used for match reloads are never
2961 inherited. */
2962 lra_assert (curr_alt_matches[i] >= 0);
2963 curr_alt_win[curr_alt_matches[i]] = false;
2965 curr_alt_win[i] = curr_alt_match_win[i] = false;
2966 losers++;
2967 /* Early clobber was already reflected in REJECT. */
2968 lra_assert (reject > 0);
2969 if (lra_dump_file != NULL)
2970 fprintf
2971 (lra_dump_file,
2972 " %d Matched conflict early clobber reloads: "
2973 "reject--\n",
2975 reject--;
2976 overall += LRA_LOSER_COST_FACTOR - 1;
2979 if (lra_dump_file != NULL)
2980 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2981 nalt, overall, losers, reload_nregs);
2983 /* If this alternative can be made to work by reloading, and it
2984 needs less reloading than the others checked so far, record
2985 it as the chosen goal for reloading. */
2986 if ((best_losers != 0 && losers == 0)
2987 || (((best_losers == 0 && losers == 0)
2988 || (best_losers != 0 && losers != 0))
2989 && (best_overall > overall
2990 || (best_overall == overall
2991 /* If the cost of the reloads is the same,
2992 prefer alternative which requires minimal
2993 number of reload regs. */
2994 && (reload_nregs < best_reload_nregs
2995 || (reload_nregs == best_reload_nregs
2996 && (best_reload_sum < reload_sum
2997 || (best_reload_sum == reload_sum
2998 && nalt < goal_alt_number))))))))
3000 for (nop = 0; nop < n_operands; nop++)
3002 goal_alt_win[nop] = curr_alt_win[nop];
3003 goal_alt_match_win[nop] = curr_alt_match_win[nop];
3004 goal_alt_matches[nop] = curr_alt_matches[nop];
3005 goal_alt[nop] = curr_alt[nop];
3006 goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
3008 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
3009 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
3010 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
3011 goal_alt_swapped = curr_swapped;
3012 best_overall = overall;
3013 best_losers = losers;
3014 best_reload_nregs = reload_nregs;
3015 best_reload_sum = reload_sum;
3016 goal_alt_number = nalt;
3018 if (losers == 0)
3019 /* Everything is satisfied. Do not process alternatives
3020 anymore. */
3021 break;
3022 fail:
3025 return ok_p;
3028 /* Make reload base reg from address AD. */
3029 static rtx
3030 base_to_reg (struct address_info *ad)
3032 enum reg_class cl;
3033 int code = -1;
3034 rtx new_inner = NULL_RTX;
3035 rtx new_reg = NULL_RTX;
3036 rtx_insn *insn;
3037 rtx_insn *last_insn = get_last_insn();
3039 lra_assert (ad->disp == ad->disp_term);
3040 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3041 get_index_code (ad));
3042 new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX,
3043 cl, "base");
3044 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
3045 ad->disp_term == NULL
3046 ? const0_rtx
3047 : *ad->disp_term);
3048 if (!valid_address_p (ad->mode, new_inner, ad->as))
3049 return NULL_RTX;
3050 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base));
3051 code = recog_memoized (insn);
3052 if (code < 0)
3054 delete_insns_since (last_insn);
3055 return NULL_RTX;
3058 return new_inner;
3061 /* Make reload base reg + disp from address AD. Return the new pseudo. */
3062 static rtx
3063 base_plus_disp_to_reg (struct address_info *ad)
3065 enum reg_class cl;
3066 rtx new_reg;
3068 lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term);
3069 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3070 get_index_code (ad));
3071 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX,
3072 cl, "base + disp");
3073 lra_emit_add (new_reg, *ad->base_term, *ad->disp_term);
3074 return new_reg;
3077 /* Make reload of index part of address AD. Return the new
3078 pseudo. */
3079 static rtx
3080 index_part_to_reg (struct address_info *ad)
3082 rtx new_reg;
3084 new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
3085 INDEX_REG_CLASS, "index term");
3086 expand_mult (GET_MODE (*ad->index), *ad->index_term,
3087 GEN_INT (get_index_scale (ad)), new_reg, 1);
3088 return new_reg;
3091 /* Return true if we can add a displacement to address AD, even if that
3092 makes the address invalid. The fix-up code requires any new address
3093 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3094 static bool
3095 can_add_disp_p (struct address_info *ad)
3097 return (!ad->autoinc_p
3098 && ad->segment == NULL
3099 && ad->base == ad->base_term
3100 && ad->disp == ad->disp_term);
3103 /* Make equiv substitution in address AD. Return true if a substitution
3104 was made. */
3105 static bool
3106 equiv_address_substitution (struct address_info *ad)
3108 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
3109 poly_int64 disp;
3110 HOST_WIDE_INT scale;
3111 bool change_p;
3113 base_term = strip_subreg (ad->base_term);
3114 if (base_term == NULL)
3115 base_reg = new_base_reg = NULL_RTX;
3116 else
3118 base_reg = *base_term;
3119 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
3121 index_term = strip_subreg (ad->index_term);
3122 if (index_term == NULL)
3123 index_reg = new_index_reg = NULL_RTX;
3124 else
3126 index_reg = *index_term;
3127 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
3129 if (base_reg == new_base_reg && index_reg == new_index_reg)
3130 return false;
3131 disp = 0;
3132 change_p = false;
3133 if (lra_dump_file != NULL)
3135 fprintf (lra_dump_file, "Changing address in insn %d ",
3136 INSN_UID (curr_insn));
3137 dump_value_slim (lra_dump_file, *ad->outer, 1);
3139 if (base_reg != new_base_reg)
3141 poly_int64 offset;
3142 if (REG_P (new_base_reg))
3144 *base_term = new_base_reg;
3145 change_p = true;
3147 else if (GET_CODE (new_base_reg) == PLUS
3148 && REG_P (XEXP (new_base_reg, 0))
3149 && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset)
3150 && can_add_disp_p (ad))
3152 disp += offset;
3153 *base_term = XEXP (new_base_reg, 0);
3154 change_p = true;
3156 if (ad->base_term2 != NULL)
3157 *ad->base_term2 = *ad->base_term;
3159 if (index_reg != new_index_reg)
3161 poly_int64 offset;
3162 if (REG_P (new_index_reg))
3164 *index_term = new_index_reg;
3165 change_p = true;
3167 else if (GET_CODE (new_index_reg) == PLUS
3168 && REG_P (XEXP (new_index_reg, 0))
3169 && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset)
3170 && can_add_disp_p (ad)
3171 && (scale = get_index_scale (ad)))
3173 disp += offset * scale;
3174 *index_term = XEXP (new_index_reg, 0);
3175 change_p = true;
3178 if (maybe_ne (disp, 0))
3180 if (ad->disp != NULL)
3181 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
3182 else
3184 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
3185 update_address (ad);
3187 change_p = true;
3189 if (lra_dump_file != NULL)
3191 if (! change_p)
3192 fprintf (lra_dump_file, " -- no change\n");
3193 else
3195 fprintf (lra_dump_file, " on equiv ");
3196 dump_value_slim (lra_dump_file, *ad->outer, 1);
3197 fprintf (lra_dump_file, "\n");
3200 return change_p;
3203 /* Major function to make reloads for an address in operand NOP or
3204 check its correctness (If CHECK_ONLY_P is true). The supported
3205 cases are:
3207 1) an address that existed before LRA started, at which point it
3208 must have been valid. These addresses are subject to elimination
3209 and may have become invalid due to the elimination offset being out
3210 of range.
3212 2) an address created by forcing a constant to memory
3213 (force_const_to_mem). The initial form of these addresses might
3214 not be valid, and it is this function's job to make them valid.
3216 3) a frame address formed from a register and a (possibly zero)
3217 constant offset. As above, these addresses might not be valid and
3218 this function must make them so.
3220 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3221 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3222 address. Return true for any RTL change.
3224 The function is a helper function which does not produce all
3225 transformations (when CHECK_ONLY_P is false) which can be
3226 necessary. It does just basic steps. To do all necessary
3227 transformations use function process_address. */
3228 static bool
3229 process_address_1 (int nop, bool check_only_p,
3230 rtx_insn **before, rtx_insn **after)
3232 struct address_info ad;
3233 rtx new_reg;
3234 HOST_WIDE_INT scale;
3235 rtx op = *curr_id->operand_loc[nop];
3236 const char *constraint = curr_static_id->operand[nop].constraint;
3237 enum constraint_num cn = lookup_constraint (constraint);
3238 bool change_p = false;
3240 if (MEM_P (op)
3241 && GET_MODE (op) == BLKmode
3242 && GET_CODE (XEXP (op, 0)) == SCRATCH)
3243 return false;
3245 if (insn_extra_address_constraint (cn))
3246 decompose_lea_address (&ad, curr_id->operand_loc[nop]);
3247 /* Do not attempt to decompose arbitrary addresses generated by combine
3248 for asm operands with loose constraints, e.g 'X'. */
3249 else if (MEM_P (op)
3250 && !(INSN_CODE (curr_insn) < 0
3251 && get_constraint_type (cn) == CT_FIXED_FORM
3252 && constraint_satisfied_p (op, cn)))
3253 decompose_mem_address (&ad, op);
3254 else if (GET_CODE (op) == SUBREG
3255 && MEM_P (SUBREG_REG (op)))
3256 decompose_mem_address (&ad, SUBREG_REG (op));
3257 else
3258 return false;
3259 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3260 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3261 when INDEX_REG_CLASS is a single register class. */
3262 if (ad.base_term != NULL
3263 && ad.index_term != NULL
3264 && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1
3265 && REG_P (*ad.base_term)
3266 && REG_P (*ad.index_term)
3267 && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL)
3268 && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL))
3270 std::swap (ad.base, ad.index);
3271 std::swap (ad.base_term, ad.index_term);
3273 if (! check_only_p)
3274 change_p = equiv_address_substitution (&ad);
3275 if (ad.base_term != NULL
3276 && (process_addr_reg
3277 (ad.base_term, check_only_p, before,
3278 (ad.autoinc_p
3279 && !(REG_P (*ad.base_term)
3280 && find_regno_note (curr_insn, REG_DEAD,
3281 REGNO (*ad.base_term)) != NULL_RTX)
3282 ? after : NULL),
3283 base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3284 get_index_code (&ad)))))
3286 change_p = true;
3287 if (ad.base_term2 != NULL)
3288 *ad.base_term2 = *ad.base_term;
3290 if (ad.index_term != NULL
3291 && process_addr_reg (ad.index_term, check_only_p,
3292 before, NULL, INDEX_REG_CLASS))
3293 change_p = true;
3295 /* Target hooks sometimes don't treat extra-constraint addresses as
3296 legitimate address_operands, so handle them specially. */
3297 if (insn_extra_address_constraint (cn)
3298 && satisfies_address_constraint_p (&ad, cn))
3299 return change_p;
3301 if (check_only_p)
3302 return change_p;
3304 /* There are three cases where the shape of *AD.INNER may now be invalid:
3306 1) the original address was valid, but either elimination or
3307 equiv_address_substitution was applied and that made
3308 the address invalid.
3310 2) the address is an invalid symbolic address created by
3311 force_const_to_mem.
3313 3) the address is a frame address with an invalid offset.
3315 4) the address is a frame address with an invalid base.
3317 All these cases involve a non-autoinc address, so there is no
3318 point revalidating other types. */
3319 if (ad.autoinc_p || valid_address_p (&ad))
3320 return change_p;
3322 /* Any index existed before LRA started, so we can assume that the
3323 presence and shape of the index is valid. */
3324 push_to_sequence (*before);
3325 lra_assert (ad.disp == ad.disp_term);
3326 if (ad.base == NULL)
3328 if (ad.index == NULL)
3330 rtx_insn *insn;
3331 rtx_insn *last = get_last_insn ();
3332 int code = -1;
3333 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3334 SCRATCH, SCRATCH);
3335 rtx addr = *ad.inner;
3337 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3338 if (HAVE_lo_sum)
3340 /* addr => lo_sum (new_base, addr), case (2) above. */
3341 insn = emit_insn (gen_rtx_SET
3342 (new_reg,
3343 gen_rtx_HIGH (Pmode, copy_rtx (addr))));
3344 code = recog_memoized (insn);
3345 if (code >= 0)
3347 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
3348 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3350 /* Try to put lo_sum into register. */
3351 insn = emit_insn (gen_rtx_SET
3352 (new_reg,
3353 gen_rtx_LO_SUM (Pmode, new_reg, addr)));
3354 code = recog_memoized (insn);
3355 if (code >= 0)
3357 *ad.inner = new_reg;
3358 if (! valid_address_p (ad.mode, *ad.outer, ad.as))
3360 *ad.inner = addr;
3361 code = -1;
3367 if (code < 0)
3368 delete_insns_since (last);
3371 if (code < 0)
3373 /* addr => new_base, case (2) above. */
3374 lra_emit_move (new_reg, addr);
3376 for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last);
3377 insn != NULL_RTX;
3378 insn = NEXT_INSN (insn))
3379 if (recog_memoized (insn) < 0)
3380 break;
3381 if (insn != NULL_RTX)
3383 /* Do nothing if we cannot generate right insns.
3384 This is analogous to reload pass behavior. */
3385 delete_insns_since (last);
3386 end_sequence ();
3387 return false;
3389 *ad.inner = new_reg;
3392 else
3394 /* index * scale + disp => new base + index * scale,
3395 case (1) above. */
3396 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3397 GET_CODE (*ad.index));
3399 lra_assert (INDEX_REG_CLASS != NO_REGS);
3400 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp");
3401 lra_emit_move (new_reg, *ad.disp);
3402 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3403 new_reg, *ad.index);
3406 else if (ad.index == NULL)
3408 int regno;
3409 enum reg_class cl;
3410 rtx set;
3411 rtx_insn *insns, *last_insn;
3412 /* Try to reload base into register only if the base is invalid
3413 for the address but with valid offset, case (4) above. */
3414 start_sequence ();
3415 new_reg = base_to_reg (&ad);
3417 /* base + disp => new base, cases (1) and (3) above. */
3418 /* Another option would be to reload the displacement into an
3419 index register. However, postreload has code to optimize
3420 address reloads that have the same base and different
3421 displacements, so reloading into an index register would
3422 not necessarily be a win. */
3423 if (new_reg == NULL_RTX)
3424 new_reg = base_plus_disp_to_reg (&ad);
3425 insns = get_insns ();
3426 last_insn = get_last_insn ();
3427 /* If we generated at least two insns, try last insn source as
3428 an address. If we succeed, we generate one less insn. */
3429 if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX
3430 && GET_CODE (SET_SRC (set)) == PLUS
3431 && REG_P (XEXP (SET_SRC (set), 0))
3432 && CONSTANT_P (XEXP (SET_SRC (set), 1)))
3434 *ad.inner = SET_SRC (set);
3435 if (valid_address_p (ad.mode, *ad.outer, ad.as))
3437 *ad.base_term = XEXP (SET_SRC (set), 0);
3438 *ad.disp_term = XEXP (SET_SRC (set), 1);
3439 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3440 get_index_code (&ad));
3441 regno = REGNO (*ad.base_term);
3442 if (regno >= FIRST_PSEUDO_REGISTER
3443 && cl != lra_get_allocno_class (regno))
3444 lra_change_class (regno, cl, " Change to", true);
3445 new_reg = SET_SRC (set);
3446 delete_insns_since (PREV_INSN (last_insn));
3449 /* Try if target can split displacement into legitimite new disp
3450 and offset. If it's the case, we replace the last insn with
3451 insns for base + offset => new_reg and set new_reg + new disp
3452 to *ad.inner. */
3453 last_insn = get_last_insn ();
3454 if ((set = single_set (last_insn)) != NULL_RTX
3455 && GET_CODE (SET_SRC (set)) == PLUS
3456 && REG_P (XEXP (SET_SRC (set), 0))
3457 && REGNO (XEXP (SET_SRC (set), 0)) < FIRST_PSEUDO_REGISTER
3458 && CONST_INT_P (XEXP (SET_SRC (set), 1)))
3460 rtx addend, disp = XEXP (SET_SRC (set), 1);
3461 if (targetm.legitimize_address_displacement (&disp, &addend,
3462 ad.mode))
3464 rtx_insn *new_insns;
3465 start_sequence ();
3466 lra_emit_add (new_reg, XEXP (SET_SRC (set), 0), addend);
3467 new_insns = get_insns ();
3468 end_sequence ();
3469 new_reg = gen_rtx_PLUS (Pmode, new_reg, disp);
3470 delete_insns_since (PREV_INSN (last_insn));
3471 add_insn (new_insns);
3472 insns = get_insns ();
3475 end_sequence ();
3476 emit_insn (insns);
3477 *ad.inner = new_reg;
3479 else if (ad.disp_term != NULL)
3481 /* base + scale * index + disp => new base + scale * index,
3482 case (1) above. */
3483 new_reg = base_plus_disp_to_reg (&ad);
3484 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3485 new_reg, *ad.index);
3487 else if ((scale = get_index_scale (&ad)) == 1)
3489 /* The last transformation to one reg will be made in
3490 curr_insn_transform function. */
3491 end_sequence ();
3492 return false;
3494 else if (scale != 0)
3496 /* base + scale * index => base + new_reg,
3497 case (1) above.
3498 Index part of address may become invalid. For example, we
3499 changed pseudo on the equivalent memory and a subreg of the
3500 pseudo onto the memory of different mode for which the scale is
3501 prohibitted. */
3502 new_reg = index_part_to_reg (&ad);
3503 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3504 *ad.base_term, new_reg);
3506 else
3508 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3509 SCRATCH, SCRATCH);
3510 rtx addr = *ad.inner;
3512 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr");
3513 /* addr => new_base. */
3514 lra_emit_move (new_reg, addr);
3515 *ad.inner = new_reg;
3517 *before = get_insns ();
3518 end_sequence ();
3519 return true;
3522 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3523 Use process_address_1 as a helper function. Return true for any
3524 RTL changes.
3526 If CHECK_ONLY_P is true, just check address correctness. Return
3527 false if the address correct. */
3528 static bool
3529 process_address (int nop, bool check_only_p,
3530 rtx_insn **before, rtx_insn **after)
3532 bool res = false;
3534 while (process_address_1 (nop, check_only_p, before, after))
3536 if (check_only_p)
3537 return true;
3538 res = true;
3540 return res;
3543 /* Emit insns to reload VALUE into a new register. VALUE is an
3544 auto-increment or auto-decrement RTX whose operand is a register or
3545 memory location; so reloading involves incrementing that location.
3546 IN is either identical to VALUE, or some cheaper place to reload
3547 value being incremented/decremented from.
3549 INC_AMOUNT is the number to increment or decrement by (always
3550 positive and ignored for POST_MODIFY/PRE_MODIFY).
3552 Return pseudo containing the result. */
3553 static rtx
3554 emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount)
3556 /* REG or MEM to be copied and incremented. */
3557 rtx incloc = XEXP (value, 0);
3558 /* Nonzero if increment after copying. */
3559 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
3560 || GET_CODE (value) == POST_MODIFY);
3561 rtx_insn *last;
3562 rtx inc;
3563 rtx_insn *add_insn;
3564 int code;
3565 rtx real_in = in == value ? incloc : in;
3566 rtx result;
3567 bool plus_p = true;
3569 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
3571 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS
3572 || GET_CODE (XEXP (value, 1)) == MINUS);
3573 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)));
3574 plus_p = GET_CODE (XEXP (value, 1)) == PLUS;
3575 inc = XEXP (XEXP (value, 1), 1);
3577 else
3579 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
3580 inc_amount = -inc_amount;
3582 inc = gen_int_mode (inc_amount, GET_MODE (value));
3585 if (! post && REG_P (incloc))
3586 result = incloc;
3587 else
3588 result = lra_create_new_reg (GET_MODE (value), value, new_rclass,
3589 "INC/DEC result");
3591 if (real_in != result)
3593 /* First copy the location to the result register. */
3594 lra_assert (REG_P (result));
3595 emit_insn (gen_move_insn (result, real_in));
3598 /* We suppose that there are insns to add/sub with the constant
3599 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3600 old reload worked with this assumption. If the assumption
3601 becomes wrong, we should use approach in function
3602 base_plus_disp_to_reg. */
3603 if (in == value)
3605 /* See if we can directly increment INCLOC. */
3606 last = get_last_insn ();
3607 add_insn = emit_insn (plus_p
3608 ? gen_add2_insn (incloc, inc)
3609 : gen_sub2_insn (incloc, inc));
3611 code = recog_memoized (add_insn);
3612 if (code >= 0)
3614 if (! post && result != incloc)
3615 emit_insn (gen_move_insn (result, incloc));
3616 return result;
3618 delete_insns_since (last);
3621 /* If couldn't do the increment directly, must increment in RESULT.
3622 The way we do this depends on whether this is pre- or
3623 post-increment. For pre-increment, copy INCLOC to the reload
3624 register, increment it there, then save back. */
3625 if (! post)
3627 if (real_in != result)
3628 emit_insn (gen_move_insn (result, real_in));
3629 if (plus_p)
3630 emit_insn (gen_add2_insn (result, inc));
3631 else
3632 emit_insn (gen_sub2_insn (result, inc));
3633 if (result != incloc)
3634 emit_insn (gen_move_insn (incloc, result));
3636 else
3638 /* Post-increment.
3640 Because this might be a jump insn or a compare, and because
3641 RESULT may not be available after the insn in an input
3642 reload, we must do the incrementing before the insn being
3643 reloaded for.
3645 We have already copied IN to RESULT. Increment the copy in
3646 RESULT, save that back, then decrement RESULT so it has
3647 the original value. */
3648 if (plus_p)
3649 emit_insn (gen_add2_insn (result, inc));
3650 else
3651 emit_insn (gen_sub2_insn (result, inc));
3652 emit_insn (gen_move_insn (incloc, result));
3653 /* Restore non-modified value for the result. We prefer this
3654 way because it does not require an additional hard
3655 register. */
3656 if (plus_p)
3658 poly_int64 offset;
3659 if (poly_int_rtx_p (inc, &offset))
3660 emit_insn (gen_add2_insn (result,
3661 gen_int_mode (-offset,
3662 GET_MODE (result))));
3663 else
3664 emit_insn (gen_sub2_insn (result, inc));
3666 else
3667 emit_insn (gen_add2_insn (result, inc));
3669 return result;
3672 /* Return true if the current move insn does not need processing as we
3673 already know that it satisfies its constraints. */
3674 static bool
3675 simple_move_p (void)
3677 rtx dest, src;
3678 enum reg_class dclass, sclass;
3680 lra_assert (curr_insn_set != NULL_RTX);
3681 dest = SET_DEST (curr_insn_set);
3682 src = SET_SRC (curr_insn_set);
3684 /* If the instruction has multiple sets we need to process it even if it
3685 is single_set. This can happen if one or more of the SETs are dead.
3686 See PR73650. */
3687 if (multiple_sets (curr_insn))
3688 return false;
3690 return ((dclass = get_op_class (dest)) != NO_REGS
3691 && (sclass = get_op_class (src)) != NO_REGS
3692 /* The backend guarantees that register moves of cost 2
3693 never need reloads. */
3694 && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2);
3697 /* Swap operands NOP and NOP + 1. */
3698 static inline void
3699 swap_operands (int nop)
3701 std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]);
3702 std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]);
3703 std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]);
3704 std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]);
3705 /* Swap the duplicates too. */
3706 lra_update_dup (curr_id, nop);
3707 lra_update_dup (curr_id, nop + 1);
3710 /* Main entry point of the constraint code: search the body of the
3711 current insn to choose the best alternative. It is mimicking insn
3712 alternative cost calculation model of former reload pass. That is
3713 because machine descriptions were written to use this model. This
3714 model can be changed in future. Make commutative operand exchange
3715 if it is chosen.
3717 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3718 constraints. Return true if any change happened during function
3719 call.
3721 If CHECK_ONLY_P is true then don't do any transformation. Just
3722 check that the insn satisfies all constraints. If the insn does
3723 not satisfy any constraint, return true. */
3724 static bool
3725 curr_insn_transform (bool check_only_p)
3727 int i, j, k;
3728 int n_operands;
3729 int n_alternatives;
3730 int n_outputs;
3731 int commutative;
3732 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
3733 signed char match_inputs[MAX_RECOG_OPERANDS + 1];
3734 signed char outputs[MAX_RECOG_OPERANDS + 1];
3735 rtx_insn *before, *after;
3736 bool alt_p = false;
3737 /* Flag that the insn has been changed through a transformation. */
3738 bool change_p;
3739 bool sec_mem_p;
3740 bool use_sec_mem_p;
3741 int max_regno_before;
3742 int reused_alternative_num;
3744 curr_insn_set = single_set (curr_insn);
3745 if (curr_insn_set != NULL_RTX && simple_move_p ())
3746 return false;
3748 no_input_reloads_p = no_output_reloads_p = false;
3749 goal_alt_number = -1;
3750 change_p = sec_mem_p = false;
3751 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3752 reloads; neither are insns that SET cc0. Insns that use CC0 are
3753 not allowed to have any input reloads. */
3754 if (JUMP_P (curr_insn) || CALL_P (curr_insn))
3755 no_output_reloads_p = true;
3757 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn)))
3758 no_input_reloads_p = true;
3759 if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn)))
3760 no_output_reloads_p = true;
3762 n_operands = curr_static_id->n_operands;
3763 n_alternatives = curr_static_id->n_alternatives;
3765 /* Just return "no reloads" if insn has no operands with
3766 constraints. */
3767 if (n_operands == 0 || n_alternatives == 0)
3768 return false;
3770 max_regno_before = max_reg_num ();
3772 for (i = 0; i < n_operands; i++)
3774 goal_alt_matched[i][0] = -1;
3775 goal_alt_matches[i] = -1;
3778 commutative = curr_static_id->commutative;
3780 /* Now see what we need for pseudos that didn't get hard regs or got
3781 the wrong kind of hard reg. For this, we must consider all the
3782 operands together against the register constraints. */
3784 best_losers = best_overall = INT_MAX;
3785 best_reload_sum = 0;
3787 curr_swapped = false;
3788 goal_alt_swapped = false;
3790 if (! check_only_p)
3791 /* Make equivalence substitution and memory subreg elimination
3792 before address processing because an address legitimacy can
3793 depend on memory mode. */
3794 for (i = 0; i < n_operands; i++)
3796 rtx op, subst, old;
3797 bool op_change_p = false;
3799 if (curr_static_id->operand[i].is_operator)
3800 continue;
3802 old = op = *curr_id->operand_loc[i];
3803 if (GET_CODE (old) == SUBREG)
3804 old = SUBREG_REG (old);
3805 subst = get_equiv_with_elimination (old, curr_insn);
3806 original_subreg_reg_mode[i] = VOIDmode;
3807 equiv_substition_p[i] = false;
3808 if (subst != old)
3810 equiv_substition_p[i] = true;
3811 subst = copy_rtx (subst);
3812 lra_assert (REG_P (old));
3813 if (GET_CODE (op) != SUBREG)
3814 *curr_id->operand_loc[i] = subst;
3815 else
3817 SUBREG_REG (op) = subst;
3818 if (GET_MODE (subst) == VOIDmode)
3819 original_subreg_reg_mode[i] = GET_MODE (old);
3821 if (lra_dump_file != NULL)
3823 fprintf (lra_dump_file,
3824 "Changing pseudo %d in operand %i of insn %u on equiv ",
3825 REGNO (old), i, INSN_UID (curr_insn));
3826 dump_value_slim (lra_dump_file, subst, 1);
3827 fprintf (lra_dump_file, "\n");
3829 op_change_p = change_p = true;
3831 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
3833 change_p = true;
3834 lra_update_dup (curr_id, i);
3838 /* Reload address registers and displacements. We do it before
3839 finding an alternative because of memory constraints. */
3840 before = after = NULL;
3841 for (i = 0; i < n_operands; i++)
3842 if (! curr_static_id->operand[i].is_operator
3843 && process_address (i, check_only_p, &before, &after))
3845 if (check_only_p)
3846 return true;
3847 change_p = true;
3848 lra_update_dup (curr_id, i);
3851 if (change_p)
3852 /* If we've changed the instruction then any alternative that
3853 we chose previously may no longer be valid. */
3854 lra_set_used_insn_alternative (curr_insn, -1);
3856 if (! check_only_p && curr_insn_set != NULL_RTX
3857 && check_and_process_move (&change_p, &sec_mem_p))
3858 return change_p;
3860 try_swapped:
3862 reused_alternative_num = check_only_p ? -1 : curr_id->used_insn_alternative;
3863 if (lra_dump_file != NULL && reused_alternative_num >= 0)
3864 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
3865 reused_alternative_num, INSN_UID (curr_insn));
3867 if (process_alt_operands (reused_alternative_num))
3868 alt_p = true;
3870 if (check_only_p)
3871 return ! alt_p || best_losers != 0;
3873 /* If insn is commutative (it's safe to exchange a certain pair of
3874 operands) then we need to try each alternative twice, the second
3875 time matching those two operands as if we had exchanged them. To
3876 do this, really exchange them in operands.
3878 If we have just tried the alternatives the second time, return
3879 operands to normal and drop through. */
3881 if (reused_alternative_num < 0 && commutative >= 0)
3883 curr_swapped = !curr_swapped;
3884 if (curr_swapped)
3886 swap_operands (commutative);
3887 goto try_swapped;
3889 else
3890 swap_operands (commutative);
3893 if (! alt_p && ! sec_mem_p)
3895 /* No alternative works with reloads?? */
3896 if (INSN_CODE (curr_insn) >= 0)
3897 fatal_insn ("unable to generate reloads for:", curr_insn);
3898 error_for_asm (curr_insn,
3899 "inconsistent operand constraints in an %<asm%>");
3900 /* Avoid further trouble with this insn. Don't generate use
3901 pattern here as we could use the insn SP offset. */
3902 lra_set_insn_deleted (curr_insn);
3903 return true;
3906 /* If the best alternative is with operands 1 and 2 swapped, swap
3907 them. Update the operand numbers of any reloads already
3908 pushed. */
3910 if (goal_alt_swapped)
3912 if (lra_dump_file != NULL)
3913 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
3914 INSN_UID (curr_insn));
3916 /* Swap the duplicates too. */
3917 swap_operands (commutative);
3918 change_p = true;
3921 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3922 too conservatively. So we use the secondary memory only if there
3923 is no any alternative without reloads. */
3924 use_sec_mem_p = false;
3925 if (! alt_p)
3926 use_sec_mem_p = true;
3927 else if (sec_mem_p)
3929 for (i = 0; i < n_operands; i++)
3930 if (! goal_alt_win[i] && ! goal_alt_match_win[i])
3931 break;
3932 use_sec_mem_p = i < n_operands;
3935 if (use_sec_mem_p)
3937 int in = -1, out = -1;
3938 rtx new_reg, src, dest, rld;
3939 machine_mode sec_mode, rld_mode;
3941 lra_assert (curr_insn_set != NULL_RTX && sec_mem_p);
3942 dest = SET_DEST (curr_insn_set);
3943 src = SET_SRC (curr_insn_set);
3944 for (i = 0; i < n_operands; i++)
3945 if (*curr_id->operand_loc[i] == dest)
3946 out = i;
3947 else if (*curr_id->operand_loc[i] == src)
3948 in = i;
3949 for (i = 0; i < curr_static_id->n_dups; i++)
3950 if (out < 0 && *curr_id->dup_loc[i] == dest)
3951 out = curr_static_id->dup_num[i];
3952 else if (in < 0 && *curr_id->dup_loc[i] == src)
3953 in = curr_static_id->dup_num[i];
3954 lra_assert (out >= 0 && in >= 0
3955 && curr_static_id->operand[out].type == OP_OUT
3956 && curr_static_id->operand[in].type == OP_IN);
3957 rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest;
3958 rld_mode = GET_MODE (rld);
3959 sec_mode = targetm.secondary_memory_needed_mode (rld_mode);
3960 new_reg = lra_create_new_reg (sec_mode, NULL_RTX,
3961 NO_REGS, "secondary");
3962 /* If the mode is changed, it should be wider. */
3963 lra_assert (!partial_subreg_p (sec_mode, rld_mode));
3964 if (sec_mode != rld_mode)
3966 /* If the target says specifically to use another mode for
3967 secondary memory moves we can not reuse the original
3968 insn. */
3969 after = emit_spill_move (false, new_reg, dest);
3970 lra_process_new_insns (curr_insn, NULL, after,
3971 "Inserting the sec. move");
3972 /* We may have non null BEFORE here (e.g. after address
3973 processing. */
3974 push_to_sequence (before);
3975 before = emit_spill_move (true, new_reg, src);
3976 emit_insn (before);
3977 before = get_insns ();
3978 end_sequence ();
3979 lra_process_new_insns (curr_insn, before, NULL, "Changing on");
3980 lra_set_insn_deleted (curr_insn);
3982 else if (dest == rld)
3984 *curr_id->operand_loc[out] = new_reg;
3985 lra_update_dup (curr_id, out);
3986 after = emit_spill_move (false, new_reg, dest);
3987 lra_process_new_insns (curr_insn, NULL, after,
3988 "Inserting the sec. move");
3990 else
3992 *curr_id->operand_loc[in] = new_reg;
3993 lra_update_dup (curr_id, in);
3994 /* See comments above. */
3995 push_to_sequence (before);
3996 before = emit_spill_move (true, new_reg, src);
3997 emit_insn (before);
3998 before = get_insns ();
3999 end_sequence ();
4000 lra_process_new_insns (curr_insn, before, NULL,
4001 "Inserting the sec. move");
4003 lra_update_insn_regno_info (curr_insn);
4004 return true;
4007 lra_assert (goal_alt_number >= 0);
4008 lra_set_used_insn_alternative (curr_insn, goal_alt_number);
4010 if (lra_dump_file != NULL)
4012 const char *p;
4014 fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
4015 goal_alt_number, INSN_UID (curr_insn));
4016 for (i = 0; i < n_operands; i++)
4018 p = (curr_static_id->operand_alternative
4019 [goal_alt_number * n_operands + i].constraint);
4020 if (*p == '\0')
4021 continue;
4022 fprintf (lra_dump_file, " (%d) ", i);
4023 for (; *p != '\0' && *p != ',' && *p != '#'; p++)
4024 fputc (*p, lra_dump_file);
4026 if (INSN_CODE (curr_insn) >= 0
4027 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
4028 fprintf (lra_dump_file, " {%s}", p);
4029 if (maybe_ne (curr_id->sp_offset, 0))
4031 fprintf (lra_dump_file, " (sp_off=");
4032 print_dec (curr_id->sp_offset, lra_dump_file);
4033 fprintf (lra_dump_file, ")");
4035 fprintf (lra_dump_file, "\n");
4038 /* Right now, for any pair of operands I and J that are required to
4039 match, with J < I, goal_alt_matches[I] is J. Add I to
4040 goal_alt_matched[J]. */
4042 for (i = 0; i < n_operands; i++)
4043 if ((j = goal_alt_matches[i]) >= 0)
4045 for (k = 0; goal_alt_matched[j][k] >= 0; k++)
4047 /* We allow matching one output operand and several input
4048 operands. */
4049 lra_assert (k == 0
4050 || (curr_static_id->operand[j].type == OP_OUT
4051 && curr_static_id->operand[i].type == OP_IN
4052 && (curr_static_id->operand
4053 [goal_alt_matched[j][0]].type == OP_IN)));
4054 goal_alt_matched[j][k] = i;
4055 goal_alt_matched[j][k + 1] = -1;
4058 for (i = 0; i < n_operands; i++)
4059 goal_alt_win[i] |= goal_alt_match_win[i];
4061 /* Any constants that aren't allowed and can't be reloaded into
4062 registers are here changed into memory references. */
4063 for (i = 0; i < n_operands; i++)
4064 if (goal_alt_win[i])
4066 int regno;
4067 enum reg_class new_class;
4068 rtx reg = *curr_id->operand_loc[i];
4070 if (GET_CODE (reg) == SUBREG)
4071 reg = SUBREG_REG (reg);
4073 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
4075 bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
4077 if (new_class != NO_REGS && get_reg_class (regno) != new_class)
4079 lra_assert (ok_p);
4080 lra_change_class (regno, new_class, " Change to", true);
4084 else
4086 const char *constraint;
4087 char c;
4088 rtx op = *curr_id->operand_loc[i];
4089 rtx subreg = NULL_RTX;
4090 machine_mode mode = curr_operand_mode[i];
4092 if (GET_CODE (op) == SUBREG)
4094 subreg = op;
4095 op = SUBREG_REG (op);
4096 mode = GET_MODE (op);
4099 if (CONST_POOL_OK_P (mode, op)
4100 && ((targetm.preferred_reload_class
4101 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
4102 || no_input_reloads_p))
4104 rtx tem = force_const_mem (mode, op);
4106 change_p = true;
4107 if (subreg != NULL_RTX)
4108 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
4110 *curr_id->operand_loc[i] = tem;
4111 lra_update_dup (curr_id, i);
4112 process_address (i, false, &before, &after);
4114 /* If the alternative accepts constant pool refs directly
4115 there will be no reload needed at all. */
4116 if (subreg != NULL_RTX)
4117 continue;
4118 /* Skip alternatives before the one requested. */
4119 constraint = (curr_static_id->operand_alternative
4120 [goal_alt_number * n_operands + i].constraint);
4121 for (;
4122 (c = *constraint) && c != ',' && c != '#';
4123 constraint += CONSTRAINT_LEN (c, constraint))
4125 enum constraint_num cn = lookup_constraint (constraint);
4126 if ((insn_extra_memory_constraint (cn)
4127 || insn_extra_special_memory_constraint (cn))
4128 && satisfies_memory_constraint_p (tem, cn))
4129 break;
4131 if (c == '\0' || c == ',' || c == '#')
4132 continue;
4134 goal_alt_win[i] = true;
4138 n_outputs = 0;
4139 outputs[0] = -1;
4140 for (i = 0; i < n_operands; i++)
4142 int regno;
4143 bool optional_p = false;
4144 rtx old, new_reg;
4145 rtx op = *curr_id->operand_loc[i];
4147 if (goal_alt_win[i])
4149 if (goal_alt[i] == NO_REGS
4150 && REG_P (op)
4151 /* When we assign NO_REGS it means that we will not
4152 assign a hard register to the scratch pseudo by
4153 assigment pass and the scratch pseudo will be
4154 spilled. Spilled scratch pseudos are transformed
4155 back to scratches at the LRA end. */
4156 && lra_former_scratch_operand_p (curr_insn, i)
4157 && lra_former_scratch_p (REGNO (op)))
4159 int regno = REGNO (op);
4160 lra_change_class (regno, NO_REGS, " Change to", true);
4161 if (lra_get_regno_hard_regno (regno) >= 0)
4162 /* We don't have to mark all insn affected by the
4163 spilled pseudo as there is only one such insn, the
4164 current one. */
4165 reg_renumber[regno] = -1;
4166 lra_assert (bitmap_single_bit_set_p
4167 (&lra_reg_info[REGNO (op)].insn_bitmap));
4169 /* We can do an optional reload. If the pseudo got a hard
4170 reg, we might improve the code through inheritance. If
4171 it does not get a hard register we coalesce memory/memory
4172 moves later. Ignore move insns to avoid cycling. */
4173 if (! lra_simple_p
4174 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
4175 && goal_alt[i] != NO_REGS && REG_P (op)
4176 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
4177 && regno < new_regno_start
4178 && ! lra_former_scratch_p (regno)
4179 && reg_renumber[regno] < 0
4180 /* Check that the optional reload pseudo will be able to
4181 hold given mode value. */
4182 && ! (prohibited_class_reg_set_mode_p
4183 (goal_alt[i], reg_class_contents[goal_alt[i]],
4184 PSEUDO_REGNO_MODE (regno)))
4185 && (curr_insn_set == NULL_RTX
4186 || !((REG_P (SET_SRC (curr_insn_set))
4187 || MEM_P (SET_SRC (curr_insn_set))
4188 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
4189 && (REG_P (SET_DEST (curr_insn_set))
4190 || MEM_P (SET_DEST (curr_insn_set))
4191 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
4192 optional_p = true;
4193 else
4194 continue;
4197 /* Operands that match previous ones have already been handled. */
4198 if (goal_alt_matches[i] >= 0)
4199 continue;
4201 /* We should not have an operand with a non-offsettable address
4202 appearing where an offsettable address will do. It also may
4203 be a case when the address should be special in other words
4204 not a general one (e.g. it needs no index reg). */
4205 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
4207 enum reg_class rclass;
4208 rtx *loc = &XEXP (op, 0);
4209 enum rtx_code code = GET_CODE (*loc);
4211 push_to_sequence (before);
4212 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
4213 MEM, SCRATCH);
4214 if (GET_RTX_CLASS (code) == RTX_AUTOINC)
4215 new_reg = emit_inc (rclass, *loc, *loc,
4216 /* This value does not matter for MODIFY. */
4217 GET_MODE_SIZE (GET_MODE (op)));
4218 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE,
4219 "offsetable address", &new_reg))
4220 lra_emit_move (new_reg, *loc);
4221 before = get_insns ();
4222 end_sequence ();
4223 *loc = new_reg;
4224 lra_update_dup (curr_id, i);
4226 else if (goal_alt_matched[i][0] == -1)
4228 machine_mode mode;
4229 rtx reg, *loc;
4230 int hard_regno;
4231 enum op_type type = curr_static_id->operand[i].type;
4233 loc = curr_id->operand_loc[i];
4234 mode = curr_operand_mode[i];
4235 if (GET_CODE (*loc) == SUBREG)
4237 reg = SUBREG_REG (*loc);
4238 poly_int64 byte = SUBREG_BYTE (*loc);
4239 if (REG_P (reg)
4240 /* Strict_low_part requires reloading the register and not
4241 just the subreg. Likewise for a strict subreg no wider
4242 than a word for WORD_REGISTER_OPERATIONS targets. */
4243 && (curr_static_id->operand[i].strict_low
4244 || (!paradoxical_subreg_p (mode, GET_MODE (reg))
4245 && (hard_regno
4246 = get_try_hard_regno (REGNO (reg))) >= 0
4247 && (simplify_subreg_regno
4248 (hard_regno,
4249 GET_MODE (reg), byte, mode) < 0)
4250 && (goal_alt[i] == NO_REGS
4251 || (simplify_subreg_regno
4252 (ira_class_hard_regs[goal_alt[i]][0],
4253 GET_MODE (reg), byte, mode) >= 0)))
4254 || (partial_subreg_p (mode, GET_MODE (reg))
4255 && known_le (GET_MODE_SIZE (GET_MODE (reg)),
4256 UNITS_PER_WORD)
4257 && WORD_REGISTER_OPERATIONS)))
4259 /* An OP_INOUT is required when reloading a subreg of a
4260 mode wider than a word to ensure that data beyond the
4261 word being reloaded is preserved. Also automatically
4262 ensure that strict_low_part reloads are made into
4263 OP_INOUT which should already be true from the backend
4264 constraints. */
4265 if (type == OP_OUT
4266 && (curr_static_id->operand[i].strict_low
4267 || read_modify_subreg_p (*loc)))
4268 type = OP_INOUT;
4269 loc = &SUBREG_REG (*loc);
4270 mode = GET_MODE (*loc);
4273 old = *loc;
4274 if (get_reload_reg (type, mode, old, goal_alt[i],
4275 loc != curr_id->operand_loc[i], "", &new_reg)
4276 && type != OP_OUT)
4278 push_to_sequence (before);
4279 lra_emit_move (new_reg, old);
4280 before = get_insns ();
4281 end_sequence ();
4283 *loc = new_reg;
4284 if (type != OP_IN
4285 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
4287 start_sequence ();
4288 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
4289 emit_insn (after);
4290 after = get_insns ();
4291 end_sequence ();
4292 *loc = new_reg;
4294 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
4295 if (goal_alt_dont_inherit_ops[j] == i)
4297 lra_set_regno_unique_value (REGNO (new_reg));
4298 break;
4300 lra_update_dup (curr_id, i);
4302 else if (curr_static_id->operand[i].type == OP_IN
4303 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4304 == OP_OUT
4305 || (curr_static_id->operand[goal_alt_matched[i][0]].type
4306 == OP_INOUT
4307 && (operands_match_p
4308 (*curr_id->operand_loc[i],
4309 *curr_id->operand_loc[goal_alt_matched[i][0]],
4310 -1)))))
4312 /* generate reloads for input and matched outputs. */
4313 match_inputs[0] = i;
4314 match_inputs[1] = -1;
4315 match_reload (goal_alt_matched[i][0], match_inputs, outputs,
4316 goal_alt[i], &before, &after,
4317 curr_static_id->operand_alternative
4318 [goal_alt_number * n_operands + goal_alt_matched[i][0]]
4319 .earlyclobber);
4321 else if ((curr_static_id->operand[i].type == OP_OUT
4322 || (curr_static_id->operand[i].type == OP_INOUT
4323 && (operands_match_p
4324 (*curr_id->operand_loc[i],
4325 *curr_id->operand_loc[goal_alt_matched[i][0]],
4326 -1))))
4327 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4328 == OP_IN))
4329 /* Generate reloads for output and matched inputs. */
4330 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4331 &after, curr_static_id->operand_alternative
4332 [goal_alt_number * n_operands + i].earlyclobber);
4333 else if (curr_static_id->operand[i].type == OP_IN
4334 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4335 == OP_IN))
4337 /* Generate reloads for matched inputs. */
4338 match_inputs[0] = i;
4339 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
4340 match_inputs[j + 1] = k;
4341 match_inputs[j + 1] = -1;
4342 match_reload (-1, match_inputs, outputs, goal_alt[i], &before,
4343 &after, false);
4345 else
4346 /* We must generate code in any case when function
4347 process_alt_operands decides that it is possible. */
4348 gcc_unreachable ();
4350 /* Memorise processed outputs so that output remaining to be processed
4351 can avoid using the same register value (see match_reload). */
4352 if (curr_static_id->operand[i].type == OP_OUT)
4354 outputs[n_outputs++] = i;
4355 outputs[n_outputs] = -1;
4358 if (optional_p)
4360 rtx reg = op;
4362 lra_assert (REG_P (reg));
4363 regno = REGNO (reg);
4364 op = *curr_id->operand_loc[i]; /* Substitution. */
4365 if (GET_CODE (op) == SUBREG)
4366 op = SUBREG_REG (op);
4367 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
4368 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
4369 lra_reg_info[REGNO (op)].restore_rtx = reg;
4370 if (lra_dump_file != NULL)
4371 fprintf (lra_dump_file,
4372 " Making reload reg %d for reg %d optional\n",
4373 REGNO (op), regno);
4376 if (before != NULL_RTX || after != NULL_RTX
4377 || max_regno_before != max_reg_num ())
4378 change_p = true;
4379 if (change_p)
4381 lra_update_operator_dups (curr_id);
4382 /* Something changes -- process the insn. */
4383 lra_update_insn_regno_info (curr_insn);
4385 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
4386 return change_p;
4389 /* Return true if INSN satisfies all constraints. In other words, no
4390 reload insns are needed. */
4391 bool
4392 lra_constrain_insn (rtx_insn *insn)
4394 int saved_new_regno_start = new_regno_start;
4395 int saved_new_insn_uid_start = new_insn_uid_start;
4396 bool change_p;
4398 curr_insn = insn;
4399 curr_id = lra_get_insn_recog_data (curr_insn);
4400 curr_static_id = curr_id->insn_static_data;
4401 new_insn_uid_start = get_max_uid ();
4402 new_regno_start = max_reg_num ();
4403 change_p = curr_insn_transform (true);
4404 new_regno_start = saved_new_regno_start;
4405 new_insn_uid_start = saved_new_insn_uid_start;
4406 return ! change_p;
4409 /* Return true if X is in LIST. */
4410 static bool
4411 in_list_p (rtx x, rtx list)
4413 for (; list != NULL_RTX; list = XEXP (list, 1))
4414 if (XEXP (list, 0) == x)
4415 return true;
4416 return false;
4419 /* Return true if X contains an allocatable hard register (if
4420 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4421 static bool
4422 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
4424 int i, j;
4425 const char *fmt;
4426 enum rtx_code code;
4428 code = GET_CODE (x);
4429 if (REG_P (x))
4431 int regno = REGNO (x);
4432 HARD_REG_SET alloc_regs;
4434 if (hard_reg_p)
4436 if (regno >= FIRST_PSEUDO_REGISTER)
4437 regno = lra_get_regno_hard_regno (regno);
4438 if (regno < 0)
4439 return false;
4440 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs);
4441 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
4443 else
4445 if (regno < FIRST_PSEUDO_REGISTER)
4446 return false;
4447 if (! spilled_p)
4448 return true;
4449 return lra_get_regno_hard_regno (regno) < 0;
4452 fmt = GET_RTX_FORMAT (code);
4453 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4455 if (fmt[i] == 'e')
4457 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
4458 return true;
4460 else if (fmt[i] == 'E')
4462 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4463 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
4464 return true;
4467 return false;
4470 /* Process all regs in location *LOC and change them on equivalent
4471 substitution. Return true if any change was done. */
4472 static bool
4473 loc_equivalence_change_p (rtx *loc)
4475 rtx subst, reg, x = *loc;
4476 bool result = false;
4477 enum rtx_code code = GET_CODE (x);
4478 const char *fmt;
4479 int i, j;
4481 if (code == SUBREG)
4483 reg = SUBREG_REG (x);
4484 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4485 && GET_MODE (subst) == VOIDmode)
4487 /* We cannot reload debug location. Simplify subreg here
4488 while we know the inner mode. */
4489 *loc = simplify_gen_subreg (GET_MODE (x), subst,
4490 GET_MODE (reg), SUBREG_BYTE (x));
4491 return true;
4494 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
4496 *loc = subst;
4497 return true;
4500 /* Scan all the operand sub-expressions. */
4501 fmt = GET_RTX_FORMAT (code);
4502 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4504 if (fmt[i] == 'e')
4505 result = loc_equivalence_change_p (&XEXP (x, i)) || result;
4506 else if (fmt[i] == 'E')
4507 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4508 result
4509 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result;
4511 return result;
4514 /* Similar to loc_equivalence_change_p, but for use as
4515 simplify_replace_fn_rtx callback. DATA is insn for which the
4516 elimination is done. If it null we don't do the elimination. */
4517 static rtx
4518 loc_equivalence_callback (rtx loc, const_rtx, void *data)
4520 if (!REG_P (loc))
4521 return NULL_RTX;
4523 rtx subst = (data == NULL
4524 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data));
4525 if (subst != loc)
4526 return subst;
4528 return NULL_RTX;
4531 /* Maximum number of generated reload insns per an insn. It is for
4532 preventing this pass cycling in a bug case. */
4533 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4535 /* The current iteration number of this LRA pass. */
4536 int lra_constraint_iter;
4538 /* True if we substituted equiv which needs checking register
4539 allocation correctness because the equivalent value contains
4540 allocatable hard registers or when we restore multi-register
4541 pseudo. */
4542 bool lra_risky_transformations_p;
4544 /* Return true if REGNO is referenced in more than one block. */
4545 static bool
4546 multi_block_pseudo_p (int regno)
4548 basic_block bb = NULL;
4549 unsigned int uid;
4550 bitmap_iterator bi;
4552 if (regno < FIRST_PSEUDO_REGISTER)
4553 return false;
4555 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
4556 if (bb == NULL)
4557 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
4558 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
4559 return true;
4560 return false;
4563 /* Return true if LIST contains a deleted insn. */
4564 static bool
4565 contains_deleted_insn_p (rtx_insn_list *list)
4567 for (; list != NULL_RTX; list = list->next ())
4568 if (NOTE_P (list->insn ())
4569 && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED)
4570 return true;
4571 return false;
4574 /* Return true if X contains a pseudo dying in INSN. */
4575 static bool
4576 dead_pseudo_p (rtx x, rtx_insn *insn)
4578 int i, j;
4579 const char *fmt;
4580 enum rtx_code code;
4582 if (REG_P (x))
4583 return (insn != NULL_RTX
4584 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX);
4585 code = GET_CODE (x);
4586 fmt = GET_RTX_FORMAT (code);
4587 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4589 if (fmt[i] == 'e')
4591 if (dead_pseudo_p (XEXP (x, i), insn))
4592 return true;
4594 else if (fmt[i] == 'E')
4596 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4597 if (dead_pseudo_p (XVECEXP (x, i, j), insn))
4598 return true;
4601 return false;
4604 /* Return true if INSN contains a dying pseudo in INSN right hand
4605 side. */
4606 static bool
4607 insn_rhs_dead_pseudo_p (rtx_insn *insn)
4609 rtx set = single_set (insn);
4611 gcc_assert (set != NULL);
4612 return dead_pseudo_p (SET_SRC (set), insn);
4615 /* Return true if any init insn of REGNO contains a dying pseudo in
4616 insn right hand side. */
4617 static bool
4618 init_insn_rhs_dead_pseudo_p (int regno)
4620 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4622 if (insns == NULL)
4623 return false;
4624 for (; insns != NULL_RTX; insns = insns->next ())
4625 if (insn_rhs_dead_pseudo_p (insns->insn ()))
4626 return true;
4627 return false;
4630 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4631 reverse only if we have one init insn with given REGNO as a
4632 source. */
4633 static bool
4634 reverse_equiv_p (int regno)
4636 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4637 rtx set;
4639 if (insns == NULL)
4640 return false;
4641 if (! INSN_P (insns->insn ())
4642 || insns->next () != NULL)
4643 return false;
4644 if ((set = single_set (insns->insn ())) == NULL_RTX)
4645 return false;
4646 return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno;
4649 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4650 call this function only for non-reverse equivalence. */
4651 static bool
4652 contains_reloaded_insn_p (int regno)
4654 rtx set;
4655 rtx_insn_list *list = ira_reg_equiv[regno].init_insns;
4657 for (; list != NULL; list = list->next ())
4658 if ((set = single_set (list->insn ())) == NULL_RTX
4659 || ! REG_P (SET_DEST (set))
4660 || (int) REGNO (SET_DEST (set)) != regno)
4661 return true;
4662 return false;
4665 /* Entry function of LRA constraint pass. Return true if the
4666 constraint pass did change the code. */
4667 bool
4668 lra_constraints (bool first_p)
4670 bool changed_p;
4671 int i, hard_regno, new_insns_num;
4672 unsigned int min_len, new_min_len, uid;
4673 rtx set, x, reg, dest_reg;
4674 basic_block last_bb;
4675 bitmap_iterator bi;
4677 lra_constraint_iter++;
4678 if (lra_dump_file != NULL)
4679 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
4680 lra_constraint_iter);
4681 changed_p = false;
4682 if (pic_offset_table_rtx
4683 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
4684 lra_risky_transformations_p = true;
4685 else
4686 /* On the first iteration we should check IRA assignment
4687 correctness. In rare cases, the assignments can be wrong as
4688 early clobbers operands are ignored in IRA. */
4689 lra_risky_transformations_p = first_p;
4690 new_insn_uid_start = get_max_uid ();
4691 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
4692 /* Mark used hard regs for target stack size calulations. */
4693 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4694 if (lra_reg_info[i].nrefs != 0
4695 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4697 int j, nregs;
4699 nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode);
4700 for (j = 0; j < nregs; j++)
4701 df_set_regs_ever_live (hard_regno + j, true);
4703 /* Do elimination before the equivalence processing as we can spill
4704 some pseudos during elimination. */
4705 lra_eliminate (false, first_p);
4706 auto_bitmap equiv_insn_bitmap (&reg_obstack);
4707 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4708 if (lra_reg_info[i].nrefs != 0)
4710 ira_reg_equiv[i].profitable_p = true;
4711 reg = regno_reg_rtx[i];
4712 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
4714 bool pseudo_p = contains_reg_p (x, false, false);
4716 /* After RTL transformation, we can not guarantee that
4717 pseudo in the substitution was not reloaded which might
4718 make equivalence invalid. For example, in reverse
4719 equiv of p0
4721 p0 <- ...
4723 equiv_mem <- p0
4725 the memory address register was reloaded before the 2nd
4726 insn. */
4727 if ((! first_p && pseudo_p)
4728 /* We don't use DF for compilation speed sake. So it
4729 is problematic to update live info when we use an
4730 equivalence containing pseudos in more than one
4731 BB. */
4732 || (pseudo_p && multi_block_pseudo_p (i))
4733 /* If an init insn was deleted for some reason, cancel
4734 the equiv. We could update the equiv insns after
4735 transformations including an equiv insn deletion
4736 but it is not worthy as such cases are extremely
4737 rare. */
4738 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
4739 /* If it is not a reverse equivalence, we check that a
4740 pseudo in rhs of the init insn is not dying in the
4741 insn. Otherwise, the live info at the beginning of
4742 the corresponding BB might be wrong after we
4743 removed the insn. When the equiv can be a
4744 constant, the right hand side of the init insn can
4745 be a pseudo. */
4746 || (! reverse_equiv_p (i)
4747 && (init_insn_rhs_dead_pseudo_p (i)
4748 /* If we reloaded the pseudo in an equivalence
4749 init insn, we can not remove the equiv init
4750 insns and the init insns might write into
4751 const memory in this case. */
4752 || contains_reloaded_insn_p (i)))
4753 /* Prevent access beyond equivalent memory for
4754 paradoxical subregs. */
4755 || (MEM_P (x)
4756 && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode),
4757 GET_MODE_SIZE (GET_MODE (x))))
4758 || (pic_offset_table_rtx
4759 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x)
4760 && (targetm.preferred_reload_class
4761 (x, lra_get_allocno_class (i)) == NO_REGS))
4762 || contains_symbol_ref_p (x))))
4763 ira_reg_equiv[i].defined_p = false;
4764 if (contains_reg_p (x, false, true))
4765 ira_reg_equiv[i].profitable_p = false;
4766 if (get_equiv (reg) != reg)
4767 bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
4770 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4771 update_equiv (i);
4772 /* We should add all insns containing pseudos which should be
4773 substituted by their equivalences. */
4774 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi)
4775 lra_push_insn_by_uid (uid);
4776 min_len = lra_insn_stack_length ();
4777 new_insns_num = 0;
4778 last_bb = NULL;
4779 changed_p = false;
4780 while ((new_min_len = lra_insn_stack_length ()) != 0)
4782 curr_insn = lra_pop_insn ();
4783 --new_min_len;
4784 curr_bb = BLOCK_FOR_INSN (curr_insn);
4785 if (curr_bb != last_bb)
4787 last_bb = curr_bb;
4788 bb_reload_num = lra_curr_reload_num;
4790 if (min_len > new_min_len)
4792 min_len = new_min_len;
4793 new_insns_num = 0;
4795 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
4796 internal_error
4797 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4798 MAX_RELOAD_INSNS_NUMBER);
4799 new_insns_num++;
4800 if (DEBUG_INSN_P (curr_insn))
4802 /* We need to check equivalence in debug insn and change
4803 pseudo to the equivalent value if necessary. */
4804 curr_id = lra_get_insn_recog_data (curr_insn);
4805 if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)))
4807 rtx old = *curr_id->operand_loc[0];
4808 *curr_id->operand_loc[0]
4809 = simplify_replace_fn_rtx (old, NULL_RTX,
4810 loc_equivalence_callback, curr_insn);
4811 if (old != *curr_id->operand_loc[0])
4813 lra_update_insn_regno_info (curr_insn);
4814 changed_p = true;
4818 else if (INSN_P (curr_insn))
4820 if ((set = single_set (curr_insn)) != NULL_RTX)
4822 dest_reg = SET_DEST (set);
4823 /* The equivalence pseudo could be set up as SUBREG in a
4824 case when it is a call restore insn in a mode
4825 different from the pseudo mode. */
4826 if (GET_CODE (dest_reg) == SUBREG)
4827 dest_reg = SUBREG_REG (dest_reg);
4828 if ((REG_P (dest_reg)
4829 && (x = get_equiv (dest_reg)) != dest_reg
4830 /* Remove insns which set up a pseudo whose value
4831 can not be changed. Such insns might be not in
4832 init_insns because we don't update equiv data
4833 during insn transformations.
4835 As an example, let suppose that a pseudo got
4836 hard register and on the 1st pass was not
4837 changed to equivalent constant. We generate an
4838 additional insn setting up the pseudo because of
4839 secondary memory movement. Then the pseudo is
4840 spilled and we use the equiv constant. In this
4841 case we should remove the additional insn and
4842 this insn is not init_insns list. */
4843 && (! MEM_P (x) || MEM_READONLY_P (x)
4844 /* Check that this is actually an insn setting
4845 up the equivalence. */
4846 || in_list_p (curr_insn,
4847 ira_reg_equiv
4848 [REGNO (dest_reg)].init_insns)))
4849 || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
4850 && in_list_p (curr_insn,
4851 ira_reg_equiv
4852 [REGNO (SET_SRC (set))].init_insns)))
4854 /* This is equiv init insn of pseudo which did not get a
4855 hard register -- remove the insn. */
4856 if (lra_dump_file != NULL)
4858 fprintf (lra_dump_file,
4859 " Removing equiv init insn %i (freq=%d)\n",
4860 INSN_UID (curr_insn),
4861 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
4862 dump_insn_slim (lra_dump_file, curr_insn);
4864 if (contains_reg_p (x, true, false))
4865 lra_risky_transformations_p = true;
4866 lra_set_insn_deleted (curr_insn);
4867 continue;
4870 curr_id = lra_get_insn_recog_data (curr_insn);
4871 curr_static_id = curr_id->insn_static_data;
4872 init_curr_insn_input_reloads ();
4873 init_curr_operand_mode ();
4874 if (curr_insn_transform (false))
4875 changed_p = true;
4876 /* Check non-transformed insns too for equiv change as USE
4877 or CLOBBER don't need reloads but can contain pseudos
4878 being changed on their equivalences. */
4879 else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))
4880 && loc_equivalence_change_p (&PATTERN (curr_insn)))
4882 lra_update_insn_regno_info (curr_insn);
4883 changed_p = true;
4888 /* If we used a new hard regno, changed_p should be true because the
4889 hard reg is assigned to a new pseudo. */
4890 if (flag_checking && !changed_p)
4892 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
4893 if (lra_reg_info[i].nrefs != 0
4894 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4896 int j, nregs = hard_regno_nregs (hard_regno,
4897 PSEUDO_REGNO_MODE (i));
4899 for (j = 0; j < nregs; j++)
4900 lra_assert (df_regs_ever_live_p (hard_regno + j));
4903 return changed_p;
4906 static void initiate_invariants (void);
4907 static void finish_invariants (void);
4909 /* Initiate the LRA constraint pass. It is done once per
4910 function. */
4911 void
4912 lra_constraints_init (void)
4914 initiate_invariants ();
4917 /* Finalize the LRA constraint pass. It is done once per
4918 function. */
4919 void
4920 lra_constraints_finish (void)
4922 finish_invariants ();
4927 /* Structure describes invariants for ineheritance. */
4928 struct lra_invariant
4930 /* The order number of the invariant. */
4931 int num;
4932 /* The invariant RTX. */
4933 rtx invariant_rtx;
4934 /* The origin insn of the invariant. */
4935 rtx_insn *insn;
4938 typedef lra_invariant invariant_t;
4939 typedef invariant_t *invariant_ptr_t;
4940 typedef const invariant_t *const_invariant_ptr_t;
4942 /* Pointer to the inheritance invariants. */
4943 static vec<invariant_ptr_t> invariants;
4945 /* Allocation pool for the invariants. */
4946 static object_allocator<lra_invariant> *invariants_pool;
4948 /* Hash table for the invariants. */
4949 static htab_t invariant_table;
4951 /* Hash function for INVARIANT. */
4952 static hashval_t
4953 invariant_hash (const void *invariant)
4955 rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx;
4956 return lra_rtx_hash (inv);
4959 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4960 static int
4961 invariant_eq_p (const void *invariant1, const void *invariant2)
4963 rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx;
4964 rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx;
4966 return rtx_equal_p (inv1, inv2);
4969 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4970 invariant which is in the table. */
4971 static invariant_ptr_t
4972 insert_invariant (rtx invariant_rtx)
4974 void **entry_ptr;
4975 invariant_t invariant;
4976 invariant_ptr_t invariant_ptr;
4978 invariant.invariant_rtx = invariant_rtx;
4979 entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT);
4980 if (*entry_ptr == NULL)
4982 invariant_ptr = invariants_pool->allocate ();
4983 invariant_ptr->invariant_rtx = invariant_rtx;
4984 invariant_ptr->insn = NULL;
4985 invariants.safe_push (invariant_ptr);
4986 *entry_ptr = (void *) invariant_ptr;
4988 return (invariant_ptr_t) *entry_ptr;
4991 /* Initiate the invariant table. */
4992 static void
4993 initiate_invariants (void)
4995 invariants.create (100);
4996 invariants_pool
4997 = new object_allocator<lra_invariant> ("Inheritance invariants");
4998 invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL);
5001 /* Finish the invariant table. */
5002 static void
5003 finish_invariants (void)
5005 htab_delete (invariant_table);
5006 delete invariants_pool;
5007 invariants.release ();
5010 /* Make the invariant table empty. */
5011 static void
5012 clear_invariants (void)
5014 htab_empty (invariant_table);
5015 invariants_pool->release ();
5016 invariants.truncate (0);
5021 /* This page contains code to do inheritance/split
5022 transformations. */
5024 /* Number of reloads passed so far in current EBB. */
5025 static int reloads_num;
5027 /* Number of calls passed so far in current EBB. */
5028 static int calls_num;
5030 /* Current reload pseudo check for validity of elements in
5031 USAGE_INSNS. */
5032 static int curr_usage_insns_check;
5034 /* Info about last usage of registers in EBB to do inheritance/split
5035 transformation. Inheritance transformation is done from a spilled
5036 pseudo and split transformations from a hard register or a pseudo
5037 assigned to a hard register. */
5038 struct usage_insns
5040 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5041 value INSNS is valid. The insns is chain of optional debug insns
5042 and a finishing non-debug insn using the corresponding reg. The
5043 value is also used to mark the registers which are set up in the
5044 current insn. The negated insn uid is used for this. */
5045 int check;
5046 /* Value of global reloads_num at the last insn in INSNS. */
5047 int reloads_num;
5048 /* Value of global reloads_nums at the last insn in INSNS. */
5049 int calls_num;
5050 /* It can be true only for splitting. And it means that the restore
5051 insn should be put after insn given by the following member. */
5052 bool after_p;
5053 /* Next insns in the current EBB which use the original reg and the
5054 original reg value is not changed between the current insn and
5055 the next insns. In order words, e.g. for inheritance, if we need
5056 to use the original reg value again in the next insns we can try
5057 to use the value in a hard register from a reload insn of the
5058 current insn. */
5059 rtx insns;
5062 /* Map: regno -> corresponding pseudo usage insns. */
5063 static struct usage_insns *usage_insns;
5065 static void
5066 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p)
5068 usage_insns[regno].check = curr_usage_insns_check;
5069 usage_insns[regno].insns = insn;
5070 usage_insns[regno].reloads_num = reloads_num;
5071 usage_insns[regno].calls_num = calls_num;
5072 usage_insns[regno].after_p = after_p;
5075 /* The function is used to form list REGNO usages which consists of
5076 optional debug insns finished by a non-debug insn using REGNO.
5077 RELOADS_NUM is current number of reload insns processed so far. */
5078 static void
5079 add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num)
5081 rtx next_usage_insns;
5083 if (usage_insns[regno].check == curr_usage_insns_check
5084 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX
5085 && DEBUG_INSN_P (insn))
5087 /* Check that we did not add the debug insn yet. */
5088 if (next_usage_insns != insn
5089 && (GET_CODE (next_usage_insns) != INSN_LIST
5090 || XEXP (next_usage_insns, 0) != insn))
5091 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn,
5092 next_usage_insns);
5094 else if (NONDEBUG_INSN_P (insn))
5095 setup_next_usage_insn (regno, insn, reloads_num, false);
5096 else
5097 usage_insns[regno].check = 0;
5100 /* Return first non-debug insn in list USAGE_INSNS. */
5101 static rtx_insn *
5102 skip_usage_debug_insns (rtx usage_insns)
5104 rtx insn;
5106 /* Skip debug insns. */
5107 for (insn = usage_insns;
5108 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST;
5109 insn = XEXP (insn, 1))
5111 return safe_as_a <rtx_insn *> (insn);
5114 /* Return true if we need secondary memory moves for insn in
5115 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5116 into the insn. */
5117 static bool
5118 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED,
5119 rtx usage_insns ATTRIBUTE_UNUSED)
5121 rtx_insn *insn;
5122 rtx set, dest;
5123 enum reg_class cl;
5125 if (inher_cl == ALL_REGS
5126 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX)
5127 return false;
5128 lra_assert (INSN_P (insn));
5129 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set)))
5130 return false;
5131 dest = SET_DEST (set);
5132 if (! REG_P (dest))
5133 return false;
5134 lra_assert (inher_cl != NO_REGS);
5135 cl = get_reg_class (REGNO (dest));
5136 return (cl != NO_REGS && cl != ALL_REGS
5137 && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl));
5140 /* Registers involved in inheritance/split in the current EBB
5141 (inheritance/split pseudos and original registers). */
5142 static bitmap_head check_only_regs;
5144 /* Reload pseudos can not be involded in invariant inheritance in the
5145 current EBB. */
5146 static bitmap_head invalid_invariant_regs;
5148 /* Do inheritance transformations for insn INSN, which defines (if
5149 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5150 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5151 form as the "insns" field of usage_insns. Return true if we
5152 succeed in such transformation.
5154 The transformations look like:
5156 p <- ... i <- ...
5157 ... p <- i (new insn)
5158 ... =>
5159 <- ... p ... <- ... i ...
5161 ... i <- p (new insn)
5162 <- ... p ... <- ... i ...
5163 ... =>
5164 <- ... p ... <- ... i ...
5165 where p is a spilled original pseudo and i is a new inheritance pseudo.
5168 The inheritance pseudo has the smallest class of two classes CL and
5169 class of ORIGINAL REGNO. */
5170 static bool
5171 inherit_reload_reg (bool def_p, int original_regno,
5172 enum reg_class cl, rtx_insn *insn, rtx next_usage_insns)
5174 if (optimize_function_for_size_p (cfun))
5175 return false;
5177 enum reg_class rclass = lra_get_allocno_class (original_regno);
5178 rtx original_reg = regno_reg_rtx[original_regno];
5179 rtx new_reg, usage_insn;
5180 rtx_insn *new_insns;
5182 lra_assert (! usage_insns[original_regno].after_p);
5183 if (lra_dump_file != NULL)
5184 fprintf (lra_dump_file,
5185 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5186 if (! ira_reg_classes_intersect_p[cl][rclass])
5188 if (lra_dump_file != NULL)
5190 fprintf (lra_dump_file,
5191 " Rejecting inheritance for %d "
5192 "because of disjoint classes %s and %s\n",
5193 original_regno, reg_class_names[cl],
5194 reg_class_names[rclass]);
5195 fprintf (lra_dump_file,
5196 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5198 return false;
5200 if ((ira_class_subset_p[cl][rclass] && cl != rclass)
5201 /* We don't use a subset of two classes because it can be
5202 NO_REGS. This transformation is still profitable in most
5203 cases even if the classes are not intersected as register
5204 move is probably cheaper than a memory load. */
5205 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass])
5207 if (lra_dump_file != NULL)
5208 fprintf (lra_dump_file, " Use smallest class of %s and %s\n",
5209 reg_class_names[cl], reg_class_names[rclass]);
5211 rclass = cl;
5213 if (check_secondary_memory_needed_p (rclass, next_usage_insns))
5215 /* Reject inheritance resulting in secondary memory moves.
5216 Otherwise, there is a danger in LRA cycling. Also such
5217 transformation will be unprofitable. */
5218 if (lra_dump_file != NULL)
5220 rtx_insn *insn = skip_usage_debug_insns (next_usage_insns);
5221 rtx set = single_set (insn);
5223 lra_assert (set != NULL_RTX);
5225 rtx dest = SET_DEST (set);
5227 lra_assert (REG_P (dest));
5228 fprintf (lra_dump_file,
5229 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5230 "as secondary mem is needed\n",
5231 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))],
5232 original_regno, reg_class_names[rclass]);
5233 fprintf (lra_dump_file,
5234 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5236 return false;
5238 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
5239 rclass, "inheritance");
5240 start_sequence ();
5241 if (def_p)
5242 lra_emit_move (original_reg, new_reg);
5243 else
5244 lra_emit_move (new_reg, original_reg);
5245 new_insns = get_insns ();
5246 end_sequence ();
5247 if (NEXT_INSN (new_insns) != NULL_RTX)
5249 if (lra_dump_file != NULL)
5251 fprintf (lra_dump_file,
5252 " Rejecting inheritance %d->%d "
5253 "as it results in 2 or more insns:\n",
5254 original_regno, REGNO (new_reg));
5255 dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0);
5256 fprintf (lra_dump_file,
5257 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5259 return false;
5261 lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false);
5262 lra_update_insn_regno_info (insn);
5263 if (! def_p)
5264 /* We now have a new usage insn for original regno. */
5265 setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
5266 if (lra_dump_file != NULL)
5267 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n",
5268 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5269 lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno];
5270 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5271 bitmap_set_bit (&check_only_regs, original_regno);
5272 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5273 if (def_p)
5274 lra_process_new_insns (insn, NULL, new_insns,
5275 "Add original<-inheritance");
5276 else
5277 lra_process_new_insns (insn, new_insns, NULL,
5278 "Add inheritance<-original");
5279 while (next_usage_insns != NULL_RTX)
5281 if (GET_CODE (next_usage_insns) != INSN_LIST)
5283 usage_insn = next_usage_insns;
5284 lra_assert (NONDEBUG_INSN_P (usage_insn));
5285 next_usage_insns = NULL;
5287 else
5289 usage_insn = XEXP (next_usage_insns, 0);
5290 lra_assert (DEBUG_INSN_P (usage_insn));
5291 next_usage_insns = XEXP (next_usage_insns, 1);
5293 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false);
5294 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5295 if (lra_dump_file != NULL)
5297 basic_block bb = BLOCK_FOR_INSN (usage_insn);
5298 fprintf (lra_dump_file,
5299 " Inheritance reuse change %d->%d (bb%d):\n",
5300 original_regno, REGNO (new_reg),
5301 bb ? bb->index : -1);
5302 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5305 if (lra_dump_file != NULL)
5306 fprintf (lra_dump_file,
5307 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5308 return true;
5311 /* Return true if we need a caller save/restore for pseudo REGNO which
5312 was assigned to a hard register. */
5313 static inline bool
5314 need_for_call_save_p (int regno)
5316 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
5317 return (usage_insns[regno].calls_num < calls_num
5318 && (overlaps_hard_reg_set_p
5319 ((flag_ipa_ra &&
5320 ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set))
5321 ? lra_reg_info[regno].actual_call_used_reg_set
5322 : call_used_reg_set,
5323 PSEUDO_REGNO_MODE (regno), reg_renumber[regno])
5324 || (targetm.hard_regno_call_part_clobbered
5325 (reg_renumber[regno], PSEUDO_REGNO_MODE (regno)))));
5328 /* Global registers occurring in the current EBB. */
5329 static bitmap_head ebb_global_regs;
5331 /* Return true if we need a split for hard register REGNO or pseudo
5332 REGNO which was assigned to a hard register.
5333 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5334 used for reloads since the EBB end. It is an approximation of the
5335 used hard registers in the split range. The exact value would
5336 require expensive calculations. If we were aggressive with
5337 splitting because of the approximation, the split pseudo will save
5338 the same hard register assignment and will be removed in the undo
5339 pass. We still need the approximation because too aggressive
5340 splitting would result in too inaccurate cost calculation in the
5341 assignment pass because of too many generated moves which will be
5342 probably removed in the undo pass. */
5343 static inline bool
5344 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
5346 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno];
5348 lra_assert (hard_regno >= 0);
5349 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
5350 /* Don't split eliminable hard registers, otherwise we can
5351 split hard registers like hard frame pointer, which
5352 lives on BB start/end according to DF-infrastructure,
5353 when there is a pseudo assigned to the register and
5354 living in the same BB. */
5355 && (regno >= FIRST_PSEUDO_REGISTER
5356 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
5357 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
5358 /* Don't split call clobbered hard regs living through
5359 calls, otherwise we might have a check problem in the
5360 assign sub-pass as in the most cases (exception is a
5361 situation when lra_risky_transformations_p value is
5362 true) the assign pass assumes that all pseudos living
5363 through calls are assigned to call saved hard regs. */
5364 && (regno >= FIRST_PSEUDO_REGISTER
5365 || ! TEST_HARD_REG_BIT (call_used_reg_set, regno)
5366 || usage_insns[regno].calls_num == calls_num)
5367 /* We need at least 2 reloads to make pseudo splitting
5368 profitable. We should provide hard regno splitting in
5369 any case to solve 1st insn scheduling problem when
5370 moving hard register definition up might result in
5371 impossibility to find hard register for reload pseudo of
5372 small register class. */
5373 && (usage_insns[regno].reloads_num
5374 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num)
5375 && (regno < FIRST_PSEUDO_REGISTER
5376 /* For short living pseudos, spilling + inheritance can
5377 be considered a substitution for splitting.
5378 Therefore we do not splitting for local pseudos. It
5379 decreases also aggressiveness of splitting. The
5380 minimal number of references is chosen taking into
5381 account that for 2 references splitting has no sense
5382 as we can just spill the pseudo. */
5383 || (regno >= FIRST_PSEUDO_REGISTER
5384 && lra_reg_info[regno].nrefs > 3
5385 && bitmap_bit_p (&ebb_global_regs, regno))))
5386 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno)));
5389 /* Return class for the split pseudo created from original pseudo with
5390 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5391 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5392 results in no secondary memory movements. */
5393 static enum reg_class
5394 choose_split_class (enum reg_class allocno_class,
5395 int hard_regno ATTRIBUTE_UNUSED,
5396 machine_mode mode ATTRIBUTE_UNUSED)
5398 int i;
5399 enum reg_class cl, best_cl = NO_REGS;
5400 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5401 = REGNO_REG_CLASS (hard_regno);
5403 if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class)
5404 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno))
5405 return allocno_class;
5406 for (i = 0;
5407 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES;
5408 i++)
5409 if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class)
5410 && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl)
5411 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno)
5412 && (best_cl == NO_REGS
5413 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl]))
5414 best_cl = cl;
5415 return best_cl;
5418 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5419 It only makes sense to call this function if NEW_REGNO is always
5420 equal to ORIGINAL_REGNO. */
5422 static void
5423 lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno)
5425 if (!ira_reg_equiv[original_regno].defined_p)
5426 return;
5428 ira_expand_reg_equiv ();
5429 ira_reg_equiv[new_regno].defined_p = true;
5430 if (ira_reg_equiv[original_regno].memory)
5431 ira_reg_equiv[new_regno].memory
5432 = copy_rtx (ira_reg_equiv[original_regno].memory);
5433 if (ira_reg_equiv[original_regno].constant)
5434 ira_reg_equiv[new_regno].constant
5435 = copy_rtx (ira_reg_equiv[original_regno].constant);
5436 if (ira_reg_equiv[original_regno].invariant)
5437 ira_reg_equiv[new_regno].invariant
5438 = copy_rtx (ira_reg_equiv[original_regno].invariant);
5441 /* Do split transformations for insn INSN, which defines or uses
5442 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5443 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5444 "insns" field of usage_insns.
5446 The transformations look like:
5448 p <- ... p <- ...
5449 ... s <- p (new insn -- save)
5450 ... =>
5451 ... p <- s (new insn -- restore)
5452 <- ... p ... <- ... p ...
5454 <- ... p ... <- ... p ...
5455 ... s <- p (new insn -- save)
5456 ... =>
5457 ... p <- s (new insn -- restore)
5458 <- ... p ... <- ... p ...
5460 where p is an original pseudo got a hard register or a hard
5461 register and s is a new split pseudo. The save is put before INSN
5462 if BEFORE_P is true. Return true if we succeed in such
5463 transformation. */
5464 static bool
5465 split_reg (bool before_p, int original_regno, rtx_insn *insn,
5466 rtx next_usage_insns)
5468 enum reg_class rclass;
5469 rtx original_reg;
5470 int hard_regno, nregs;
5471 rtx new_reg, usage_insn;
5472 rtx_insn *restore, *save;
5473 bool after_p;
5474 bool call_save_p;
5475 machine_mode mode;
5477 if (original_regno < FIRST_PSEUDO_REGISTER)
5479 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)];
5480 hard_regno = original_regno;
5481 call_save_p = false;
5482 nregs = 1;
5483 mode = lra_reg_info[hard_regno].biggest_mode;
5484 machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]);
5485 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5486 as part of a multi-word register. In that case, or if the biggest
5487 mode was larger than a register, just use the reg_rtx. Otherwise,
5488 limit the size to that of the biggest access in the function. */
5489 if (mode == VOIDmode
5490 || paradoxical_subreg_p (mode, reg_rtx_mode))
5492 original_reg = regno_reg_rtx[hard_regno];
5493 mode = reg_rtx_mode;
5495 else
5496 original_reg = gen_rtx_REG (mode, hard_regno);
5498 else
5500 mode = PSEUDO_REGNO_MODE (original_regno);
5501 hard_regno = reg_renumber[original_regno];
5502 nregs = hard_regno_nregs (hard_regno, mode);
5503 rclass = lra_get_allocno_class (original_regno);
5504 original_reg = regno_reg_rtx[original_regno];
5505 call_save_p = need_for_call_save_p (original_regno);
5507 lra_assert (hard_regno >= 0);
5508 if (lra_dump_file != NULL)
5509 fprintf (lra_dump_file,
5510 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5512 if (call_save_p)
5514 mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno,
5515 hard_regno_nregs (hard_regno, mode),
5516 mode);
5517 new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save");
5519 else
5521 rclass = choose_split_class (rclass, hard_regno, mode);
5522 if (rclass == NO_REGS)
5524 if (lra_dump_file != NULL)
5526 fprintf (lra_dump_file,
5527 " Rejecting split of %d(%s): "
5528 "no good reg class for %d(%s)\n",
5529 original_regno,
5530 reg_class_names[lra_get_allocno_class (original_regno)],
5531 hard_regno,
5532 reg_class_names[REGNO_REG_CLASS (hard_regno)]);
5533 fprintf
5534 (lra_dump_file,
5535 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5537 return false;
5539 /* Split_if_necessary can split hard registers used as part of a
5540 multi-register mode but splits each register individually. The
5541 mode used for each independent register may not be supported
5542 so reject the split. Splitting the wider mode should theoretically
5543 be possible but is not implemented. */
5544 if (!targetm.hard_regno_mode_ok (hard_regno, mode))
5546 if (lra_dump_file != NULL)
5548 fprintf (lra_dump_file,
5549 " Rejecting split of %d(%s): unsuitable mode %s\n",
5550 original_regno,
5551 reg_class_names[lra_get_allocno_class (original_regno)],
5552 GET_MODE_NAME (mode));
5553 fprintf
5554 (lra_dump_file,
5555 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5557 return false;
5559 new_reg = lra_create_new_reg (mode, original_reg, rclass, "split");
5560 reg_renumber[REGNO (new_reg)] = hard_regno;
5562 int new_regno = REGNO (new_reg);
5563 save = emit_spill_move (true, new_reg, original_reg);
5564 if (NEXT_INSN (save) != NULL_RTX && !call_save_p)
5566 if (lra_dump_file != NULL)
5568 fprintf
5569 (lra_dump_file,
5570 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5571 original_regno, new_regno);
5572 dump_rtl_slim (lra_dump_file, save, NULL, -1, 0);
5573 fprintf (lra_dump_file,
5574 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5576 return false;
5578 restore = emit_spill_move (false, new_reg, original_reg);
5579 if (NEXT_INSN (restore) != NULL_RTX && !call_save_p)
5581 if (lra_dump_file != NULL)
5583 fprintf (lra_dump_file,
5584 " Rejecting split %d->%d "
5585 "resulting in > 2 restore insns:\n",
5586 original_regno, new_regno);
5587 dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0);
5588 fprintf (lra_dump_file,
5589 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5591 return false;
5593 /* Transfer equivalence information to the spill register, so that
5594 if we fail to allocate the spill register, we have the option of
5595 rematerializing the original value instead of spilling to the stack. */
5596 if (!HARD_REGISTER_NUM_P (original_regno)
5597 && mode == PSEUDO_REGNO_MODE (original_regno))
5598 lra_copy_reg_equiv (new_regno, original_regno);
5599 after_p = usage_insns[original_regno].after_p;
5600 lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno];
5601 bitmap_set_bit (&check_only_regs, new_regno);
5602 bitmap_set_bit (&check_only_regs, original_regno);
5603 bitmap_set_bit (&lra_split_regs, new_regno);
5604 for (;;)
5606 if (GET_CODE (next_usage_insns) != INSN_LIST)
5608 usage_insn = next_usage_insns;
5609 break;
5611 usage_insn = XEXP (next_usage_insns, 0);
5612 lra_assert (DEBUG_INSN_P (usage_insn));
5613 next_usage_insns = XEXP (next_usage_insns, 1);
5614 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false);
5615 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5616 if (lra_dump_file != NULL)
5618 fprintf (lra_dump_file, " Split reuse change %d->%d:\n",
5619 original_regno, new_regno);
5620 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5623 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn));
5624 lra_assert (usage_insn != insn || (after_p && before_p));
5625 lra_process_new_insns (as_a <rtx_insn *> (usage_insn),
5626 after_p ? NULL : restore,
5627 after_p ? restore : NULL,
5628 call_save_p
5629 ? "Add reg<-save" : "Add reg<-split");
5630 lra_process_new_insns (insn, before_p ? save : NULL,
5631 before_p ? NULL : save,
5632 call_save_p
5633 ? "Add save<-reg" : "Add split<-reg");
5634 if (nregs > 1)
5635 /* If we are trying to split multi-register. We should check
5636 conflicts on the next assignment sub-pass. IRA can allocate on
5637 sub-register levels, LRA do this on pseudos level right now and
5638 this discrepancy may create allocation conflicts after
5639 splitting. */
5640 lra_risky_transformations_p = true;
5641 if (lra_dump_file != NULL)
5642 fprintf (lra_dump_file,
5643 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5644 return true;
5647 /* Recognize that we need a split transformation for insn INSN, which
5648 defines or uses REGNO in its insn biggest MODE (we use it only if
5649 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5650 hard registers which might be used for reloads since the EBB end.
5651 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5652 uid before starting INSN processing. Return true if we succeed in
5653 such transformation. */
5654 static bool
5655 split_if_necessary (int regno, machine_mode mode,
5656 HARD_REG_SET potential_reload_hard_regs,
5657 bool before_p, rtx_insn *insn, int max_uid)
5659 bool res = false;
5660 int i, nregs = 1;
5661 rtx next_usage_insns;
5663 if (regno < FIRST_PSEUDO_REGISTER)
5664 nregs = hard_regno_nregs (regno, mode);
5665 for (i = 0; i < nregs; i++)
5666 if (usage_insns[regno + i].check == curr_usage_insns_check
5667 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX
5668 /* To avoid processing the register twice or more. */
5669 && ((GET_CODE (next_usage_insns) != INSN_LIST
5670 && INSN_UID (next_usage_insns) < max_uid)
5671 || (GET_CODE (next_usage_insns) == INSN_LIST
5672 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid)))
5673 && need_for_split_p (potential_reload_hard_regs, regno + i)
5674 && split_reg (before_p, regno + i, insn, next_usage_insns))
5675 res = true;
5676 return res;
5679 /* Return TRUE if rtx X is considered as an invariant for
5680 inheritance. */
5681 static bool
5682 invariant_p (const_rtx x)
5684 machine_mode mode;
5685 const char *fmt;
5686 enum rtx_code code;
5687 int i, j;
5689 code = GET_CODE (x);
5690 mode = GET_MODE (x);
5691 if (code == SUBREG)
5693 x = SUBREG_REG (x);
5694 code = GET_CODE (x);
5695 mode = wider_subreg_mode (mode, GET_MODE (x));
5698 if (MEM_P (x))
5699 return false;
5701 if (REG_P (x))
5703 int i, nregs, regno = REGNO (x);
5705 if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM
5706 || TEST_HARD_REG_BIT (eliminable_regset, regno)
5707 || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
5708 return false;
5709 nregs = hard_regno_nregs (regno, mode);
5710 for (i = 0; i < nregs; i++)
5711 if (! fixed_regs[regno + i]
5712 /* A hard register may be clobbered in the current insn
5713 but we can ignore this case because if the hard
5714 register is used it should be set somewhere after the
5715 clobber. */
5716 || bitmap_bit_p (&invalid_invariant_regs, regno + i))
5717 return false;
5719 fmt = GET_RTX_FORMAT (code);
5720 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5722 if (fmt[i] == 'e')
5724 if (! invariant_p (XEXP (x, i)))
5725 return false;
5727 else if (fmt[i] == 'E')
5729 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5730 if (! invariant_p (XVECEXP (x, i, j)))
5731 return false;
5734 return true;
5737 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5738 inheritance transformation (using dest_reg instead invariant in a
5739 subsequent insn). */
5740 static bool
5741 process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx)
5743 invariant_ptr_t invariant_ptr;
5744 rtx_insn *insn, *new_insns;
5745 rtx insn_set, insn_reg, new_reg;
5746 int insn_regno;
5747 bool succ_p = false;
5748 int dst_regno = REGNO (dst_reg);
5749 machine_mode dst_mode = GET_MODE (dst_reg);
5750 enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl;
5752 invariant_ptr = insert_invariant (invariant_rtx);
5753 if ((insn = invariant_ptr->insn) != NULL_RTX)
5755 /* We have a subsequent insn using the invariant. */
5756 insn_set = single_set (insn);
5757 lra_assert (insn_set != NULL);
5758 insn_reg = SET_DEST (insn_set);
5759 lra_assert (REG_P (insn_reg));
5760 insn_regno = REGNO (insn_reg);
5761 insn_reg_cl = lra_get_allocno_class (insn_regno);
5763 if (dst_mode == GET_MODE (insn_reg)
5764 /* We should consider only result move reg insns which are
5765 cheap. */
5766 && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2
5767 && targetm.register_move_cost (dst_mode, cl, cl) == 2)
5769 if (lra_dump_file != NULL)
5770 fprintf (lra_dump_file,
5771 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5772 new_reg = lra_create_new_reg (dst_mode, dst_reg,
5773 cl, "invariant inheritance");
5774 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5775 bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5776 lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn);
5777 start_sequence ();
5778 lra_emit_move (new_reg, dst_reg);
5779 new_insns = get_insns ();
5780 end_sequence ();
5781 lra_process_new_insns (curr_insn, NULL, new_insns,
5782 "Add invariant inheritance<-original");
5783 start_sequence ();
5784 lra_emit_move (SET_DEST (insn_set), new_reg);
5785 new_insns = get_insns ();
5786 end_sequence ();
5787 lra_process_new_insns (insn, NULL, new_insns,
5788 "Changing reload<-inheritance");
5789 lra_set_insn_deleted (insn);
5790 succ_p = true;
5791 if (lra_dump_file != NULL)
5793 fprintf (lra_dump_file,
5794 " Invariant inheritance reuse change %d (bb%d):\n",
5795 REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5796 dump_insn_slim (lra_dump_file, insn);
5797 fprintf (lra_dump_file,
5798 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5802 invariant_ptr->insn = curr_insn;
5803 return succ_p;
5806 /* Check only registers living at the current program point in the
5807 current EBB. */
5808 static bitmap_head live_regs;
5810 /* Update live info in EBB given by its HEAD and TAIL insns after
5811 inheritance/split transformation. The function removes dead moves
5812 too. */
5813 static void
5814 update_ebb_live_info (rtx_insn *head, rtx_insn *tail)
5816 unsigned int j;
5817 int i, regno;
5818 bool live_p;
5819 rtx_insn *prev_insn;
5820 rtx set;
5821 bool remove_p;
5822 basic_block last_bb, prev_bb, curr_bb;
5823 bitmap_iterator bi;
5824 struct lra_insn_reg *reg;
5825 edge e;
5826 edge_iterator ei;
5828 last_bb = BLOCK_FOR_INSN (tail);
5829 prev_bb = NULL;
5830 for (curr_insn = tail;
5831 curr_insn != PREV_INSN (head);
5832 curr_insn = prev_insn)
5834 prev_insn = PREV_INSN (curr_insn);
5835 /* We need to process empty blocks too. They contain
5836 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5837 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK)
5838 continue;
5839 curr_bb = BLOCK_FOR_INSN (curr_insn);
5840 if (curr_bb != prev_bb)
5842 if (prev_bb != NULL)
5844 /* Update df_get_live_in (prev_bb): */
5845 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5846 if (bitmap_bit_p (&live_regs, j))
5847 bitmap_set_bit (df_get_live_in (prev_bb), j);
5848 else
5849 bitmap_clear_bit (df_get_live_in (prev_bb), j);
5851 if (curr_bb != last_bb)
5853 /* Update df_get_live_out (curr_bb): */
5854 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
5856 live_p = bitmap_bit_p (&live_regs, j);
5857 if (! live_p)
5858 FOR_EACH_EDGE (e, ei, curr_bb->succs)
5859 if (bitmap_bit_p (df_get_live_in (e->dest), j))
5861 live_p = true;
5862 break;
5864 if (live_p)
5865 bitmap_set_bit (df_get_live_out (curr_bb), j);
5866 else
5867 bitmap_clear_bit (df_get_live_out (curr_bb), j);
5870 prev_bb = curr_bb;
5871 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb));
5873 if (! NONDEBUG_INSN_P (curr_insn))
5874 continue;
5875 curr_id = lra_get_insn_recog_data (curr_insn);
5876 curr_static_id = curr_id->insn_static_data;
5877 remove_p = false;
5878 if ((set = single_set (curr_insn)) != NULL_RTX
5879 && REG_P (SET_DEST (set))
5880 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
5881 && SET_DEST (set) != pic_offset_table_rtx
5882 && bitmap_bit_p (&check_only_regs, regno)
5883 && ! bitmap_bit_p (&live_regs, regno))
5884 remove_p = true;
5885 /* See which defined values die here. */
5886 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5887 if (reg->type == OP_OUT && ! reg->subreg_p)
5888 bitmap_clear_bit (&live_regs, reg->regno);
5889 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5890 if (reg->type == OP_OUT && ! reg->subreg_p)
5891 bitmap_clear_bit (&live_regs, reg->regno);
5892 if (curr_id->arg_hard_regs != NULL)
5893 /* Make clobbered argument hard registers die. */
5894 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5895 if (regno >= FIRST_PSEUDO_REGISTER)
5896 bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER);
5897 /* Mark each used value as live. */
5898 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5899 if (reg->type != OP_OUT
5900 && bitmap_bit_p (&check_only_regs, reg->regno))
5901 bitmap_set_bit (&live_regs, reg->regno);
5902 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
5903 if (reg->type != OP_OUT
5904 && bitmap_bit_p (&check_only_regs, reg->regno))
5905 bitmap_set_bit (&live_regs, reg->regno);
5906 if (curr_id->arg_hard_regs != NULL)
5907 /* Make used argument hard registers live. */
5908 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
5909 if (regno < FIRST_PSEUDO_REGISTER
5910 && bitmap_bit_p (&check_only_regs, regno))
5911 bitmap_set_bit (&live_regs, regno);
5912 /* It is quite important to remove dead move insns because it
5913 means removing dead store. We don't need to process them for
5914 constraints. */
5915 if (remove_p)
5917 if (lra_dump_file != NULL)
5919 fprintf (lra_dump_file, " Removing dead insn:\n ");
5920 dump_insn_slim (lra_dump_file, curr_insn);
5922 lra_set_insn_deleted (curr_insn);
5927 /* The structure describes info to do an inheritance for the current
5928 insn. We need to collect such info first before doing the
5929 transformations because the transformations change the insn
5930 internal representation. */
5931 struct to_inherit
5933 /* Original regno. */
5934 int regno;
5935 /* Subsequent insns which can inherit original reg value. */
5936 rtx insns;
5939 /* Array containing all info for doing inheritance from the current
5940 insn. */
5941 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS];
5943 /* Number elements in the previous array. */
5944 static int to_inherit_num;
5946 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5947 structure to_inherit. */
5948 static void
5949 add_to_inherit (int regno, rtx insns)
5951 int i;
5953 for (i = 0; i < to_inherit_num; i++)
5954 if (to_inherit[i].regno == regno)
5955 return;
5956 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS);
5957 to_inherit[to_inherit_num].regno = regno;
5958 to_inherit[to_inherit_num++].insns = insns;
5961 /* Return the last non-debug insn in basic block BB, or the block begin
5962 note if none. */
5963 static rtx_insn *
5964 get_last_insertion_point (basic_block bb)
5966 rtx_insn *insn;
5968 FOR_BB_INSNS_REVERSE (bb, insn)
5969 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn))
5970 return insn;
5971 gcc_unreachable ();
5974 /* Set up RES by registers living on edges FROM except the edge (FROM,
5975 TO) or by registers set up in a jump insn in BB FROM. */
5976 static void
5977 get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
5979 rtx_insn *last;
5980 struct lra_insn_reg *reg;
5981 edge e;
5982 edge_iterator ei;
5984 lra_assert (to != NULL);
5985 bitmap_clear (res);
5986 FOR_EACH_EDGE (e, ei, from->succs)
5987 if (e->dest != to)
5988 bitmap_ior_into (res, df_get_live_in (e->dest));
5989 last = get_last_insertion_point (from);
5990 if (! JUMP_P (last))
5991 return;
5992 curr_id = lra_get_insn_recog_data (last);
5993 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
5994 if (reg->type != OP_IN)
5995 bitmap_set_bit (res, reg->regno);
5998 /* Used as a temporary results of some bitmap calculations. */
5999 static bitmap_head temp_bitmap;
6001 /* We split for reloads of small class of hard regs. The following
6002 defines how many hard regs the class should have to be qualified as
6003 small. The code is mostly oriented to x86/x86-64 architecture
6004 where some insns need to use only specific register or pair of
6005 registers and these register can live in RTL explicitly, e.g. for
6006 parameter passing. */
6007 static const int max_small_class_regs_num = 2;
6009 /* Do inheritance/split transformations in EBB starting with HEAD and
6010 finishing on TAIL. We process EBB insns in the reverse order.
6011 Return true if we did any inheritance/split transformation in the
6012 EBB.
6014 We should avoid excessive splitting which results in worse code
6015 because of inaccurate cost calculations for spilling new split
6016 pseudos in such case. To achieve this we do splitting only if
6017 register pressure is high in given basic block and there are reload
6018 pseudos requiring hard registers. We could do more register
6019 pressure calculations at any given program point to avoid necessary
6020 splitting even more but it is to expensive and the current approach
6021 works well enough. */
6022 static bool
6023 inherit_in_ebb (rtx_insn *head, rtx_insn *tail)
6025 int i, src_regno, dst_regno, nregs;
6026 bool change_p, succ_p, update_reloads_num_p;
6027 rtx_insn *prev_insn, *last_insn;
6028 rtx next_usage_insns, curr_set;
6029 enum reg_class cl;
6030 struct lra_insn_reg *reg;
6031 basic_block last_processed_bb, curr_bb = NULL;
6032 HARD_REG_SET potential_reload_hard_regs, live_hard_regs;
6033 bitmap to_process;
6034 unsigned int j;
6035 bitmap_iterator bi;
6036 bool head_p, after_p;
6038 change_p = false;
6039 curr_usage_insns_check++;
6040 clear_invariants ();
6041 reloads_num = calls_num = 0;
6042 bitmap_clear (&check_only_regs);
6043 bitmap_clear (&invalid_invariant_regs);
6044 last_processed_bb = NULL;
6045 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6046 COPY_HARD_REG_SET (live_hard_regs, eliminable_regset);
6047 IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
6048 /* We don't process new insns generated in the loop. */
6049 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
6051 prev_insn = PREV_INSN (curr_insn);
6052 if (BLOCK_FOR_INSN (curr_insn) != NULL)
6053 curr_bb = BLOCK_FOR_INSN (curr_insn);
6054 if (last_processed_bb != curr_bb)
6056 /* We are at the end of BB. Add qualified living
6057 pseudos for potential splitting. */
6058 to_process = df_get_live_out (curr_bb);
6059 if (last_processed_bb != NULL)
6061 /* We are somewhere in the middle of EBB. */
6062 get_live_on_other_edges (curr_bb, last_processed_bb,
6063 &temp_bitmap);
6064 to_process = &temp_bitmap;
6066 last_processed_bb = curr_bb;
6067 last_insn = get_last_insertion_point (curr_bb);
6068 after_p = (! JUMP_P (last_insn)
6069 && (! CALL_P (last_insn)
6070 || (find_reg_note (last_insn,
6071 REG_NORETURN, NULL_RTX) == NULL_RTX
6072 && ! SIBLING_CALL_P (last_insn))));
6073 CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6074 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6076 if ((int) j >= lra_constraint_new_regno_start)
6077 break;
6078 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6080 if (j < FIRST_PSEUDO_REGISTER)
6081 SET_HARD_REG_BIT (live_hard_regs, j);
6082 else
6083 add_to_hard_reg_set (&live_hard_regs,
6084 PSEUDO_REGNO_MODE (j),
6085 reg_renumber[j]);
6086 setup_next_usage_insn (j, last_insn, reloads_num, after_p);
6090 src_regno = dst_regno = -1;
6091 curr_set = single_set (curr_insn);
6092 if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set)))
6093 dst_regno = REGNO (SET_DEST (curr_set));
6094 if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set)))
6095 src_regno = REGNO (SET_SRC (curr_set));
6096 update_reloads_num_p = true;
6097 if (src_regno < lra_constraint_new_regno_start
6098 && src_regno >= FIRST_PSEUDO_REGISTER
6099 && reg_renumber[src_regno] < 0
6100 && dst_regno >= lra_constraint_new_regno_start
6101 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
6103 /* 'reload_pseudo <- original_pseudo'. */
6104 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6105 reloads_num++;
6106 update_reloads_num_p = false;
6107 succ_p = false;
6108 if (usage_insns[src_regno].check == curr_usage_insns_check
6109 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX)
6110 succ_p = inherit_reload_reg (false, src_regno, cl,
6111 curr_insn, next_usage_insns);
6112 if (succ_p)
6113 change_p = true;
6114 else
6115 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6116 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6117 IOR_HARD_REG_SET (potential_reload_hard_regs,
6118 reg_class_contents[cl]);
6120 else if (src_regno < 0
6121 && dst_regno >= lra_constraint_new_regno_start
6122 && invariant_p (SET_SRC (curr_set))
6123 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS
6124 && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno)
6125 && ! bitmap_bit_p (&invalid_invariant_regs,
6126 ORIGINAL_REGNO(regno_reg_rtx[dst_regno])))
6128 /* 'reload_pseudo <- invariant'. */
6129 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6130 reloads_num++;
6131 update_reloads_num_p = false;
6132 if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set)))
6133 change_p = true;
6134 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6135 IOR_HARD_REG_SET (potential_reload_hard_regs,
6136 reg_class_contents[cl]);
6138 else if (src_regno >= lra_constraint_new_regno_start
6139 && dst_regno < lra_constraint_new_regno_start
6140 && dst_regno >= FIRST_PSEUDO_REGISTER
6141 && reg_renumber[dst_regno] < 0
6142 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS
6143 && usage_insns[dst_regno].check == curr_usage_insns_check
6144 && (next_usage_insns
6145 = usage_insns[dst_regno].insns) != NULL_RTX)
6147 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6148 reloads_num++;
6149 update_reloads_num_p = false;
6150 /* 'original_pseudo <- reload_pseudo'. */
6151 if (! JUMP_P (curr_insn)
6152 && inherit_reload_reg (true, dst_regno, cl,
6153 curr_insn, next_usage_insns))
6154 change_p = true;
6155 /* Invalidate. */
6156 usage_insns[dst_regno].check = 0;
6157 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6158 IOR_HARD_REG_SET (potential_reload_hard_regs,
6159 reg_class_contents[cl]);
6161 else if (INSN_P (curr_insn))
6163 int iter;
6164 int max_uid = get_max_uid ();
6166 curr_id = lra_get_insn_recog_data (curr_insn);
6167 curr_static_id = curr_id->insn_static_data;
6168 to_inherit_num = 0;
6169 /* Process insn definitions. */
6170 for (iter = 0; iter < 2; iter++)
6171 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6172 reg != NULL;
6173 reg = reg->next)
6174 if (reg->type != OP_IN
6175 && (dst_regno = reg->regno) < lra_constraint_new_regno_start)
6177 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT
6178 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p
6179 && usage_insns[dst_regno].check == curr_usage_insns_check
6180 && (next_usage_insns
6181 = usage_insns[dst_regno].insns) != NULL_RTX)
6183 struct lra_insn_reg *r;
6185 for (r = curr_id->regs; r != NULL; r = r->next)
6186 if (r->type != OP_OUT && r->regno == dst_regno)
6187 break;
6188 /* Don't do inheritance if the pseudo is also
6189 used in the insn. */
6190 if (r == NULL)
6191 /* We can not do inheritance right now
6192 because the current insn reg info (chain
6193 regs) can change after that. */
6194 add_to_inherit (dst_regno, next_usage_insns);
6196 /* We can not process one reg twice here because of
6197 usage_insns invalidation. */
6198 if ((dst_regno < FIRST_PSEUDO_REGISTER
6199 || reg_renumber[dst_regno] >= 0)
6200 && ! reg->subreg_p && reg->type != OP_IN)
6202 HARD_REG_SET s;
6204 if (split_if_necessary (dst_regno, reg->biggest_mode,
6205 potential_reload_hard_regs,
6206 false, curr_insn, max_uid))
6207 change_p = true;
6208 CLEAR_HARD_REG_SET (s);
6209 if (dst_regno < FIRST_PSEUDO_REGISTER)
6210 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
6211 else
6212 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
6213 reg_renumber[dst_regno]);
6214 AND_COMPL_HARD_REG_SET (live_hard_regs, s);
6216 /* We should invalidate potential inheritance or
6217 splitting for the current insn usages to the next
6218 usage insns (see code below) as the output pseudo
6219 prevents this. */
6220 if ((dst_regno >= FIRST_PSEUDO_REGISTER
6221 && reg_renumber[dst_regno] < 0)
6222 || (reg->type == OP_OUT && ! reg->subreg_p
6223 && (dst_regno < FIRST_PSEUDO_REGISTER
6224 || reg_renumber[dst_regno] >= 0)))
6226 /* Invalidate and mark definitions. */
6227 if (dst_regno >= FIRST_PSEUDO_REGISTER)
6228 usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn);
6229 else
6231 nregs = hard_regno_nregs (dst_regno,
6232 reg->biggest_mode);
6233 for (i = 0; i < nregs; i++)
6234 usage_insns[dst_regno + i].check
6235 = -(int) INSN_UID (curr_insn);
6239 /* Process clobbered call regs. */
6240 if (curr_id->arg_hard_regs != NULL)
6241 for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6242 if (dst_regno >= FIRST_PSEUDO_REGISTER)
6243 usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check
6244 = -(int) INSN_UID (curr_insn);
6245 if (! JUMP_P (curr_insn))
6246 for (i = 0; i < to_inherit_num; i++)
6247 if (inherit_reload_reg (true, to_inherit[i].regno,
6248 ALL_REGS, curr_insn,
6249 to_inherit[i].insns))
6250 change_p = true;
6251 if (CALL_P (curr_insn))
6253 rtx cheap, pat, dest;
6254 rtx_insn *restore;
6255 int regno, hard_regno;
6257 calls_num++;
6258 if ((cheap = find_reg_note (curr_insn,
6259 REG_RETURNED, NULL_RTX)) != NULL_RTX
6260 && ((cheap = XEXP (cheap, 0)), true)
6261 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
6262 && (hard_regno = reg_renumber[regno]) >= 0
6263 && usage_insns[regno].check == curr_usage_insns_check
6264 /* If there are pending saves/restores, the
6265 optimization is not worth. */
6266 && usage_insns[regno].calls_num == calls_num - 1
6267 && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno))
6269 /* Restore the pseudo from the call result as
6270 REG_RETURNED note says that the pseudo value is
6271 in the call result and the pseudo is an argument
6272 of the call. */
6273 pat = PATTERN (curr_insn);
6274 if (GET_CODE (pat) == PARALLEL)
6275 pat = XVECEXP (pat, 0, 0);
6276 dest = SET_DEST (pat);
6277 /* For multiple return values dest is PARALLEL.
6278 Currently we handle only single return value case. */
6279 if (REG_P (dest))
6281 start_sequence ();
6282 emit_move_insn (cheap, copy_rtx (dest));
6283 restore = get_insns ();
6284 end_sequence ();
6285 lra_process_new_insns (curr_insn, NULL, restore,
6286 "Inserting call parameter restore");
6287 /* We don't need to save/restore of the pseudo from
6288 this call. */
6289 usage_insns[regno].calls_num = calls_num;
6290 bitmap_set_bit (&check_only_regs, regno);
6294 to_inherit_num = 0;
6295 /* Process insn usages. */
6296 for (iter = 0; iter < 2; iter++)
6297 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6298 reg != NULL;
6299 reg = reg->next)
6300 if ((reg->type != OP_OUT
6301 || (reg->type == OP_OUT && reg->subreg_p))
6302 && (src_regno = reg->regno) < lra_constraint_new_regno_start)
6304 if (src_regno >= FIRST_PSEUDO_REGISTER
6305 && reg_renumber[src_regno] < 0 && reg->type == OP_IN)
6307 if (usage_insns[src_regno].check == curr_usage_insns_check
6308 && (next_usage_insns
6309 = usage_insns[src_regno].insns) != NULL_RTX
6310 && NONDEBUG_INSN_P (curr_insn))
6311 add_to_inherit (src_regno, next_usage_insns);
6312 else if (usage_insns[src_regno].check
6313 != -(int) INSN_UID (curr_insn))
6314 /* Add usages but only if the reg is not set up
6315 in the same insn. */
6316 add_next_usage_insn (src_regno, curr_insn, reloads_num);
6318 else if (src_regno < FIRST_PSEUDO_REGISTER
6319 || reg_renumber[src_regno] >= 0)
6321 bool before_p;
6322 rtx_insn *use_insn = curr_insn;
6324 before_p = (JUMP_P (curr_insn)
6325 || (CALL_P (curr_insn) && reg->type == OP_IN));
6326 if (NONDEBUG_INSN_P (curr_insn)
6327 && (! JUMP_P (curr_insn) || reg->type == OP_IN)
6328 && split_if_necessary (src_regno, reg->biggest_mode,
6329 potential_reload_hard_regs,
6330 before_p, curr_insn, max_uid))
6332 if (reg->subreg_p)
6333 lra_risky_transformations_p = true;
6334 change_p = true;
6335 /* Invalidate. */
6336 usage_insns[src_regno].check = 0;
6337 if (before_p)
6338 use_insn = PREV_INSN (curr_insn);
6340 if (NONDEBUG_INSN_P (curr_insn))
6342 if (src_regno < FIRST_PSEUDO_REGISTER)
6343 add_to_hard_reg_set (&live_hard_regs,
6344 reg->biggest_mode, src_regno);
6345 else
6346 add_to_hard_reg_set (&live_hard_regs,
6347 PSEUDO_REGNO_MODE (src_regno),
6348 reg_renumber[src_regno]);
6350 add_next_usage_insn (src_regno, use_insn, reloads_num);
6353 /* Process used call regs. */
6354 if (curr_id->arg_hard_regs != NULL)
6355 for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6356 if (src_regno < FIRST_PSEUDO_REGISTER)
6358 SET_HARD_REG_BIT (live_hard_regs, src_regno);
6359 add_next_usage_insn (src_regno, curr_insn, reloads_num);
6361 for (i = 0; i < to_inherit_num; i++)
6363 src_regno = to_inherit[i].regno;
6364 if (inherit_reload_reg (false, src_regno, ALL_REGS,
6365 curr_insn, to_inherit[i].insns))
6366 change_p = true;
6367 else
6368 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6371 if (update_reloads_num_p
6372 && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX)
6374 int regno = -1;
6375 if ((REG_P (SET_DEST (curr_set))
6376 && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start
6377 && reg_renumber[regno] < 0
6378 && (cl = lra_get_allocno_class (regno)) != NO_REGS)
6379 || (REG_P (SET_SRC (curr_set))
6380 && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start
6381 && reg_renumber[regno] < 0
6382 && (cl = lra_get_allocno_class (regno)) != NO_REGS))
6384 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6385 reloads_num++;
6386 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6387 IOR_HARD_REG_SET (potential_reload_hard_regs,
6388 reg_class_contents[cl]);
6391 if (NONDEBUG_INSN_P (curr_insn))
6393 int regno;
6395 /* Invalidate invariants with changed regs. */
6396 curr_id = lra_get_insn_recog_data (curr_insn);
6397 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6398 if (reg->type != OP_IN)
6400 bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6401 bitmap_set_bit (&invalid_invariant_regs,
6402 ORIGINAL_REGNO (regno_reg_rtx[reg->regno]));
6404 curr_static_id = curr_id->insn_static_data;
6405 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6406 if (reg->type != OP_IN)
6407 bitmap_set_bit (&invalid_invariant_regs, reg->regno);
6408 if (curr_id->arg_hard_regs != NULL)
6409 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6410 if (regno >= FIRST_PSEUDO_REGISTER)
6411 bitmap_set_bit (&invalid_invariant_regs,
6412 regno - FIRST_PSEUDO_REGISTER);
6414 /* We reached the start of the current basic block. */
6415 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head)
6416 || BLOCK_FOR_INSN (prev_insn) != curr_bb)
6418 /* We reached the beginning of the current block -- do
6419 rest of spliting in the current BB. */
6420 to_process = df_get_live_in (curr_bb);
6421 if (BLOCK_FOR_INSN (head) != curr_bb)
6423 /* We are somewhere in the middle of EBB. */
6424 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src,
6425 curr_bb, &temp_bitmap);
6426 to_process = &temp_bitmap;
6428 head_p = true;
6429 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6431 if ((int) j >= lra_constraint_new_regno_start)
6432 break;
6433 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6434 && usage_insns[j].check == curr_usage_insns_check
6435 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX)
6437 if (need_for_split_p (potential_reload_hard_regs, j))
6439 if (lra_dump_file != NULL && head_p)
6441 fprintf (lra_dump_file,
6442 " ----------------------------------\n");
6443 head_p = false;
6445 if (split_reg (false, j, bb_note (curr_bb),
6446 next_usage_insns))
6447 change_p = true;
6449 usage_insns[j].check = 0;
6454 return change_p;
6457 /* This value affects EBB forming. If probability of edge from EBB to
6458 a BB is not greater than the following value, we don't add the BB
6459 to EBB. */
6460 #define EBB_PROBABILITY_CUTOFF \
6461 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6463 /* Current number of inheritance/split iteration. */
6464 int lra_inheritance_iter;
6466 /* Entry function for inheritance/split pass. */
6467 void
6468 lra_inheritance (void)
6470 int i;
6471 basic_block bb, start_bb;
6472 edge e;
6474 lra_inheritance_iter++;
6475 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
6476 return;
6477 timevar_push (TV_LRA_INHERITANCE);
6478 if (lra_dump_file != NULL)
6479 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n",
6480 lra_inheritance_iter);
6481 curr_usage_insns_check = 0;
6482 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start);
6483 for (i = 0; i < lra_constraint_new_regno_start; i++)
6484 usage_insns[i].check = 0;
6485 bitmap_initialize (&check_only_regs, &reg_obstack);
6486 bitmap_initialize (&invalid_invariant_regs, &reg_obstack);
6487 bitmap_initialize (&live_regs, &reg_obstack);
6488 bitmap_initialize (&temp_bitmap, &reg_obstack);
6489 bitmap_initialize (&ebb_global_regs, &reg_obstack);
6490 FOR_EACH_BB_FN (bb, cfun)
6492 start_bb = bb;
6493 if (lra_dump_file != NULL)
6494 fprintf (lra_dump_file, "EBB");
6495 /* Form a EBB starting with BB. */
6496 bitmap_clear (&ebb_global_regs);
6497 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb));
6498 for (;;)
6500 if (lra_dump_file != NULL)
6501 fprintf (lra_dump_file, " %d", bb->index);
6502 if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
6503 || LABEL_P (BB_HEAD (bb->next_bb)))
6504 break;
6505 e = find_fallthru_edge (bb->succs);
6506 if (! e)
6507 break;
6508 if (e->probability.initialized_p ()
6509 && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF)
6510 break;
6511 bb = bb->next_bb;
6513 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb));
6514 if (lra_dump_file != NULL)
6515 fprintf (lra_dump_file, "\n");
6516 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
6517 /* Remember that the EBB head and tail can change in
6518 inherit_in_ebb. */
6519 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
6521 bitmap_clear (&ebb_global_regs);
6522 bitmap_clear (&temp_bitmap);
6523 bitmap_clear (&live_regs);
6524 bitmap_clear (&invalid_invariant_regs);
6525 bitmap_clear (&check_only_regs);
6526 free (usage_insns);
6528 timevar_pop (TV_LRA_INHERITANCE);
6533 /* This page contains code to undo failed inheritance/split
6534 transformations. */
6536 /* Current number of iteration undoing inheritance/split. */
6537 int lra_undo_inheritance_iter;
6539 /* Fix BB live info LIVE after removing pseudos created on pass doing
6540 inheritance/split which are REMOVED_PSEUDOS. */
6541 static void
6542 fix_bb_live_info (bitmap live, bitmap removed_pseudos)
6544 unsigned int regno;
6545 bitmap_iterator bi;
6547 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi)
6548 if (bitmap_clear_bit (live, regno)
6549 && REG_P (lra_reg_info[regno].restore_rtx))
6550 bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx));
6553 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6554 number. */
6555 static int
6556 get_regno (rtx reg)
6558 if (GET_CODE (reg) == SUBREG)
6559 reg = SUBREG_REG (reg);
6560 if (REG_P (reg))
6561 return REGNO (reg);
6562 return -1;
6565 /* Delete a move INSN with destination reg DREGNO and a previous
6566 clobber insn with the same regno. The inheritance/split code can
6567 generate moves with preceding clobber and when we delete such moves
6568 we should delete the clobber insn too to keep the correct life
6569 info. */
6570 static void
6571 delete_move_and_clobber (rtx_insn *insn, int dregno)
6573 rtx_insn *prev_insn = PREV_INSN (insn);
6575 lra_set_insn_deleted (insn);
6576 lra_assert (dregno >= 0);
6577 if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn)
6578 && GET_CODE (PATTERN (prev_insn)) == CLOBBER
6579 && dregno == get_regno (XEXP (PATTERN (prev_insn), 0)))
6580 lra_set_insn_deleted (prev_insn);
6583 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6584 return true if we did any change. The undo transformations for
6585 inheritance looks like
6586 i <- i2
6587 p <- i => p <- i2
6588 or removing
6589 p <- i, i <- p, and i <- i3
6590 where p is original pseudo from which inheritance pseudo i was
6591 created, i and i3 are removed inheritance pseudos, i2 is another
6592 not removed inheritance pseudo. All split pseudos or other
6593 occurrences of removed inheritance pseudos are changed on the
6594 corresponding original pseudos.
6596 The function also schedules insns changed and created during
6597 inheritance/split pass for processing by the subsequent constraint
6598 pass. */
6599 static bool
6600 remove_inheritance_pseudos (bitmap remove_pseudos)
6602 basic_block bb;
6603 int regno, sregno, prev_sregno, dregno;
6604 rtx restore_rtx;
6605 rtx set, prev_set;
6606 rtx_insn *prev_insn;
6607 bool change_p, done_p;
6609 change_p = ! bitmap_empty_p (remove_pseudos);
6610 /* We can not finish the function right away if CHANGE_P is true
6611 because we need to marks insns affected by previous
6612 inheritance/split pass for processing by the subsequent
6613 constraint pass. */
6614 FOR_EACH_BB_FN (bb, cfun)
6616 fix_bb_live_info (df_get_live_in (bb), remove_pseudos);
6617 fix_bb_live_info (df_get_live_out (bb), remove_pseudos);
6618 FOR_BB_INSNS_REVERSE (bb, curr_insn)
6620 if (! INSN_P (curr_insn))
6621 continue;
6622 done_p = false;
6623 sregno = dregno = -1;
6624 if (change_p && NONDEBUG_INSN_P (curr_insn)
6625 && (set = single_set (curr_insn)) != NULL_RTX)
6627 dregno = get_regno (SET_DEST (set));
6628 sregno = get_regno (SET_SRC (set));
6631 if (sregno >= 0 && dregno >= 0)
6633 if (bitmap_bit_p (remove_pseudos, dregno)
6634 && ! REG_P (lra_reg_info[dregno].restore_rtx))
6636 /* invariant inheritance pseudo <- original pseudo */
6637 if (lra_dump_file != NULL)
6639 fprintf (lra_dump_file, " Removing invariant inheritance:\n");
6640 dump_insn_slim (lra_dump_file, curr_insn);
6641 fprintf (lra_dump_file, "\n");
6643 delete_move_and_clobber (curr_insn, dregno);
6644 done_p = true;
6646 else if (bitmap_bit_p (remove_pseudos, sregno)
6647 && ! REG_P (lra_reg_info[sregno].restore_rtx))
6649 /* reload pseudo <- invariant inheritance pseudo */
6650 start_sequence ();
6651 /* We can not just change the source. It might be
6652 an insn different from the move. */
6653 emit_insn (lra_reg_info[sregno].restore_rtx);
6654 rtx_insn *new_insns = get_insns ();
6655 end_sequence ();
6656 lra_assert (single_set (new_insns) != NULL
6657 && SET_DEST (set) == SET_DEST (single_set (new_insns)));
6658 lra_process_new_insns (curr_insn, NULL, new_insns,
6659 "Changing reload<-invariant inheritance");
6660 delete_move_and_clobber (curr_insn, dregno);
6661 done_p = true;
6663 else if ((bitmap_bit_p (remove_pseudos, sregno)
6664 && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno
6665 || (bitmap_bit_p (remove_pseudos, dregno)
6666 && get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6667 && (get_regno (lra_reg_info[sregno].restore_rtx)
6668 == get_regno (lra_reg_info[dregno].restore_rtx)))))
6669 || (bitmap_bit_p (remove_pseudos, dregno)
6670 && get_regno (lra_reg_info[dregno].restore_rtx) == sregno))
6671 /* One of the following cases:
6672 original <- removed inheritance pseudo
6673 removed inherit pseudo <- another removed inherit pseudo
6674 removed inherit pseudo <- original pseudo
6676 removed_split_pseudo <- original_reg
6677 original_reg <- removed_split_pseudo */
6679 if (lra_dump_file != NULL)
6681 fprintf (lra_dump_file, " Removing %s:\n",
6682 bitmap_bit_p (&lra_split_regs, sregno)
6683 || bitmap_bit_p (&lra_split_regs, dregno)
6684 ? "split" : "inheritance");
6685 dump_insn_slim (lra_dump_file, curr_insn);
6687 delete_move_and_clobber (curr_insn, dregno);
6688 done_p = true;
6690 else if (bitmap_bit_p (remove_pseudos, sregno)
6691 && bitmap_bit_p (&lra_inheritance_pseudos, sregno))
6693 /* Search the following pattern:
6694 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6695 original_pseudo <- inherit_or_split_pseudo1
6696 where the 2nd insn is the current insn and
6697 inherit_or_split_pseudo2 is not removed. If it is found,
6698 change the current insn onto:
6699 original_pseudo <- inherit_or_split_pseudo2. */
6700 for (prev_insn = PREV_INSN (curr_insn);
6701 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn);
6702 prev_insn = PREV_INSN (prev_insn))
6704 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb
6705 && (prev_set = single_set (prev_insn)) != NULL_RTX
6706 /* There should be no subregs in insn we are
6707 searching because only the original reg might
6708 be in subreg when we changed the mode of
6709 load/store for splitting. */
6710 && REG_P (SET_DEST (prev_set))
6711 && REG_P (SET_SRC (prev_set))
6712 && (int) REGNO (SET_DEST (prev_set)) == sregno
6713 && ((prev_sregno = REGNO (SET_SRC (prev_set)))
6714 >= FIRST_PSEUDO_REGISTER)
6715 && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX
6717 /* As we consider chain of inheritance or
6718 splitting described in above comment we should
6719 check that sregno and prev_sregno were
6720 inheritance/split pseudos created from the
6721 same original regno. */
6722 (get_regno (lra_reg_info[sregno].restore_rtx) >= 0
6723 && (get_regno (lra_reg_info[sregno].restore_rtx)
6724 == get_regno (lra_reg_info[prev_sregno].restore_rtx))))
6725 && ! bitmap_bit_p (remove_pseudos, prev_sregno))
6727 lra_assert (GET_MODE (SET_SRC (prev_set))
6728 == GET_MODE (regno_reg_rtx[sregno]));
6729 if (GET_CODE (SET_SRC (set)) == SUBREG)
6730 SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set);
6731 else
6732 SET_SRC (set) = SET_SRC (prev_set);
6733 /* As we are finishing with processing the insn
6734 here, check the destination too as it might
6735 inheritance pseudo for another pseudo. */
6736 if (bitmap_bit_p (remove_pseudos, dregno)
6737 && bitmap_bit_p (&lra_inheritance_pseudos, dregno)
6738 && (restore_rtx
6739 = lra_reg_info[dregno].restore_rtx) != NULL_RTX)
6741 if (GET_CODE (SET_DEST (set)) == SUBREG)
6742 SUBREG_REG (SET_DEST (set)) = restore_rtx;
6743 else
6744 SET_DEST (set) = restore_rtx;
6746 lra_push_insn_and_update_insn_regno_info (curr_insn);
6747 lra_set_used_insn_alternative_by_uid
6748 (INSN_UID (curr_insn), -1);
6749 done_p = true;
6750 if (lra_dump_file != NULL)
6752 fprintf (lra_dump_file, " Change reload insn:\n");
6753 dump_insn_slim (lra_dump_file, curr_insn);
6758 if (! done_p)
6760 struct lra_insn_reg *reg;
6761 bool restored_regs_p = false;
6762 bool kept_regs_p = false;
6764 curr_id = lra_get_insn_recog_data (curr_insn);
6765 for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6767 regno = reg->regno;
6768 restore_rtx = lra_reg_info[regno].restore_rtx;
6769 if (restore_rtx != NULL_RTX)
6771 if (change_p && bitmap_bit_p (remove_pseudos, regno))
6773 lra_substitute_pseudo_within_insn
6774 (curr_insn, regno, restore_rtx, false);
6775 restored_regs_p = true;
6777 else
6778 kept_regs_p = true;
6781 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p)
6783 /* The instruction has changed since the previous
6784 constraints pass. */
6785 lra_push_insn_and_update_insn_regno_info (curr_insn);
6786 lra_set_used_insn_alternative_by_uid
6787 (INSN_UID (curr_insn), -1);
6789 else if (restored_regs_p)
6790 /* The instruction has been restored to the form that
6791 it had during the previous constraints pass. */
6792 lra_update_insn_regno_info (curr_insn);
6793 if (restored_regs_p && lra_dump_file != NULL)
6795 fprintf (lra_dump_file, " Insn after restoring regs:\n");
6796 dump_insn_slim (lra_dump_file, curr_insn);
6801 return change_p;
6804 /* If optional reload pseudos failed to get a hard register or was not
6805 inherited, it is better to remove optional reloads. We do this
6806 transformation after undoing inheritance to figure out necessity to
6807 remove optional reloads easier. Return true if we do any
6808 change. */
6809 static bool
6810 undo_optional_reloads (void)
6812 bool change_p, keep_p;
6813 unsigned int regno, uid;
6814 bitmap_iterator bi, bi2;
6815 rtx_insn *insn;
6816 rtx set, src, dest;
6817 auto_bitmap removed_optional_reload_pseudos (&reg_obstack);
6819 bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos);
6820 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
6822 keep_p = false;
6823 /* Keep optional reloads from previous subpasses. */
6824 if (lra_reg_info[regno].restore_rtx == NULL_RTX
6825 /* If the original pseudo changed its allocation, just
6826 removing the optional pseudo is dangerous as the original
6827 pseudo will have longer live range. */
6828 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0)
6829 keep_p = true;
6830 else if (reg_renumber[regno] >= 0)
6831 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2)
6833 insn = lra_insn_recog_data[uid]->insn;
6834 if ((set = single_set (insn)) == NULL_RTX)
6835 continue;
6836 src = SET_SRC (set);
6837 dest = SET_DEST (set);
6838 if (! REG_P (src) || ! REG_P (dest))
6839 continue;
6840 if (REGNO (dest) == regno
6841 /* Ignore insn for optional reloads itself. */
6842 && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src)
6843 /* Check only inheritance on last inheritance pass. */
6844 && (int) REGNO (src) >= new_regno_start
6845 /* Check that the optional reload was inherited. */
6846 && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src)))
6848 keep_p = true;
6849 break;
6852 if (keep_p)
6854 bitmap_clear_bit (removed_optional_reload_pseudos, regno);
6855 if (lra_dump_file != NULL)
6856 fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno);
6859 change_p = ! bitmap_empty_p (removed_optional_reload_pseudos);
6860 auto_bitmap insn_bitmap (&reg_obstack);
6861 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi)
6863 if (lra_dump_file != NULL)
6864 fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno);
6865 bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap);
6866 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2)
6868 insn = lra_insn_recog_data[uid]->insn;
6869 if ((set = single_set (insn)) != NULL_RTX)
6871 src = SET_SRC (set);
6872 dest = SET_DEST (set);
6873 if (REG_P (src) && REG_P (dest)
6874 && ((REGNO (src) == regno
6875 && (REGNO (lra_reg_info[regno].restore_rtx)
6876 == REGNO (dest)))
6877 || (REGNO (dest) == regno
6878 && (REGNO (lra_reg_info[regno].restore_rtx)
6879 == REGNO (src)))))
6881 if (lra_dump_file != NULL)
6883 fprintf (lra_dump_file, " Deleting move %u\n",
6884 INSN_UID (insn));
6885 dump_insn_slim (lra_dump_file, insn);
6887 delete_move_and_clobber (insn, REGNO (dest));
6888 continue;
6890 /* We should not worry about generation memory-memory
6891 moves here as if the corresponding inheritance did
6892 not work (inheritance pseudo did not get a hard reg),
6893 we remove the inheritance pseudo and the optional
6894 reload. */
6896 lra_substitute_pseudo_within_insn
6897 (insn, regno, lra_reg_info[regno].restore_rtx, false);
6898 lra_update_insn_regno_info (insn);
6899 if (lra_dump_file != NULL)
6901 fprintf (lra_dump_file,
6902 " Restoring original insn:\n");
6903 dump_insn_slim (lra_dump_file, insn);
6907 /* Clear restore_regnos. */
6908 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
6909 lra_reg_info[regno].restore_rtx = NULL_RTX;
6910 return change_p;
6913 /* Entry function for undoing inheritance/split transformation. Return true
6914 if we did any RTL change in this pass. */
6915 bool
6916 lra_undo_inheritance (void)
6918 unsigned int regno;
6919 int hard_regno;
6920 int n_all_inherit, n_inherit, n_all_split, n_split;
6921 rtx restore_rtx;
6922 bitmap_iterator bi;
6923 bool change_p;
6925 lra_undo_inheritance_iter++;
6926 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
6927 return false;
6928 if (lra_dump_file != NULL)
6929 fprintf (lra_dump_file,
6930 "\n********** Undoing inheritance #%d: **********\n\n",
6931 lra_undo_inheritance_iter);
6932 auto_bitmap remove_pseudos (&reg_obstack);
6933 n_inherit = n_all_inherit = 0;
6934 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
6935 if (lra_reg_info[regno].restore_rtx != NULL_RTX)
6937 n_all_inherit++;
6938 if (reg_renumber[regno] < 0
6939 /* If the original pseudo changed its allocation, just
6940 removing inheritance is dangerous as for changing
6941 allocation we used shorter live-ranges. */
6942 && (! REG_P (lra_reg_info[regno].restore_rtx)
6943 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0))
6944 bitmap_set_bit (remove_pseudos, regno);
6945 else
6946 n_inherit++;
6948 if (lra_dump_file != NULL && n_all_inherit != 0)
6949 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n",
6950 n_inherit, n_all_inherit,
6951 (double) n_inherit / n_all_inherit * 100);
6952 n_split = n_all_split = 0;
6953 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
6954 if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX)
6956 int restore_regno = REGNO (restore_rtx);
6958 n_all_split++;
6959 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER
6960 ? reg_renumber[restore_regno] : restore_regno);
6961 if (hard_regno < 0 || reg_renumber[regno] == hard_regno)
6962 bitmap_set_bit (remove_pseudos, regno);
6963 else
6965 n_split++;
6966 if (lra_dump_file != NULL)
6967 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n",
6968 regno, restore_regno);
6971 if (lra_dump_file != NULL && n_all_split != 0)
6972 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n",
6973 n_split, n_all_split,
6974 (double) n_split / n_all_split * 100);
6975 change_p = remove_inheritance_pseudos (remove_pseudos);
6976 /* Clear restore_regnos. */
6977 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
6978 lra_reg_info[regno].restore_rtx = NULL_RTX;
6979 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
6980 lra_reg_info[regno].restore_rtx = NULL_RTX;
6981 change_p = undo_optional_reloads () || change_p;
6982 return change_p;