| blob | 6a37bf829e29196ff47e91c00f0534c5dc6e48e8 |
1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
47 /* Forward definitions of types. */
51 /* In order to improve the layout of the prototypes below
52 some short type abbreviations are defined here. */
53 #define Hint HOST_WIDE_INT
54 #define Mmode enum machine_mode
55 #define Ulong unsigned long
57 /* Forward function declarations. */
71 static const char * output_multi_immediate PARAMS ((rtx *, const char *, const char *, int, Hint));
96 \f
97 #undef Hint
98 #undef Mmode
99 #undef Ulong
101 /* The maximum number of insns skipped which will be conditionalised if
102 possible. */
107 /* True if we are currently building a constant table. */
110 /* Define the information needed to generate branch insns. This is
111 stored from the compare operation. */
114 /* What type of floating point are we tuning for? */
117 /* What type of floating point instructions are available? */
120 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
123 /* Set by the -mfp=... option. */
126 /* Used to parse -mstructure_size_boundary command line option. */
130 /* Bit values used to identify processor capabilities. */
141 /* The bits in this mask specify which instructions we are
142 allowed to generate. */
145 /* The bits in this mask specify which instruction scheduling options should
146 be used. Note - there is an overlap with the FL_FAST_MULT. For some
147 hardware we want to be able to generate the multiply instructions, but to
148 tune as if they were not present in the architecture. */
151 /* The following are used in the arm.md file as equivalents to bits
152 in the above two flag variables. */
154 /* Nonzero if this is an "M" variant of the processor. */
157 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
160 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
163 /* Nonzero if this chip can benefit from load scheduling. */
166 /* Nonzero if this chip is a StrongARM. */
169 /* Nonzero if this chip is a an ARM6 or an ARM7. */
172 /* Nonzero if generating Thumb instructions. */
175 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
176 must report the mode of the memory reference from PRINT_OPERAND to
177 PRINT_OPERAND_ADDRESS. */
180 /* Nonzero if the prologue must setup `fp'. */
183 /* The register number to be used for the PIC offset register. */
187 /* Set to 1 when a return insn is output, this means that the epilogue
188 is not needed. */
191 /* Set to 1 after arm_reorg has started. Reset to start at the start of
192 the next function. */
195 /* The maximum number of insns to be used when loading a constant. */
198 /* For an explanation of these variables, see final_prescan_insn below. */
201 rtx arm_target_insn;
204 /* The condition codes of the ARM, and the inverse function. */
206 {
209 };
211 #define streq(string1, string2) (strcmp (string1, string2) == 0)
212 \f
213 /* Initialization code. */
215 struct processors
216 {
219 };
221 /* Not all of these give usefully different compilation alternatives,
222 but there is no simple way of generalizing them. */
224 {
225 /* ARM Cores */
236 /* arm7m doesn't exist on its own, but only with D, (and I), but
237 those don't alter the code, so arm7m is sometimes used. */
251 /* Doesn't have an external co-proc, but does have embedded fpu. */
265 };
268 {
269 /* ARM Architectures */
276 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
277 implementations that support it, so we will leave it out for now. */
281 };
283 /* This is a magic stucture. The 'string' field is magically filled in
284 with a pointer to the value specified by the user on the command line
285 assuming that the user has specified such a value. */
288 {
289 /* string name processors */
293 };
295 /* Return the number of bits set in value' */
296 static unsigned long
299 {
303 {
306 }
309 }
311 /* Fix up any incompatible options that the user has specified.
312 This has now turned into a maze. */
313 void
315 {
318 /* Set up the flags based on the cpu/architecture selected by the user. */
320 {
324 {
329 {
332 else
333 {
334 /* If we have been given an architecture and a processor
335 make sure that they are compatible. We only generate
336 a warning though, and we prefer the CPU over the
337 architecture. */
343 }
346 }
350 }
351 }
353 /* If the user did not specify a processor, choose one for them. */
355 {
358 static struct cpu_default
359 {
362 }
363 cpu_defaults[] =
364 {
378 };
381 /* Find the default. */
386 /* Make sure we found the default CPU. */
390 /* Find the default CPU's flags. */
400 /* Now check to see if the user has specified some command line
401 switch that require certain abilities from the cpu. */
405 {
408 /* Force apcs-32 to be used for interworking. */
411 /* There are no ARM processors that support both APCS-26 and
412 interworking. Therefore we force FL_MODE26 to be removed
413 from insn_flags here (if it was set), so that the search
414 below will always be able to find a compatible processor. */
416 }
421 {
422 /* Try to locate a CPU type that supports all of the abilities
423 of the default CPU, plus the extra abilities requested by
424 the user. */
430 {
434 /* Ideally we would like to issue an error message here
435 saying that it was not possible to find a CPU compatible
436 with the default CPU, but which also supports the command
437 line options specified by the programmer, and so they
438 ought to use the -mcpu=<name> command line option to
439 override the default CPU type.
441 Unfortunately this does not work with multilibing. We
442 need to be able to support multilibs for -mapcs-26 and for
443 -mthumb-interwork and there is no CPU that can support both
444 options. Instead if we cannot find a cpu that has both the
445 characteristics of the default cpu and the given command line
446 options we scan the array again looking for a best match. */
449 {
455 {
458 }
459 }
463 else
465 }
468 }
469 }
471 /* If tuning has not been specified, tune for whichever processor or
472 architecture has been selected. */
476 /* Make sure that the processor choice does not conflict with any of the
477 other command line choices. */
479 {
480 /* If APCS-32 was not the default then it must have been set by the
481 user, so issue a warning message. If the user has specified
482 "-mapcs-32 -mcpu=arm2" then we loose here. */
486 }
488 {
491 }
494 {
497 }
500 {
503 }
506 {
507 /* warning ("ignoring -mapcs-frame because -mthumb was used."); */
509 }
511 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
512 from here where no function is being compiled currently. */
518 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb.");
521 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb.");
523 /* If interworking is enabled then APCS-32 must be selected as well. */
525 {
529 }
532 {
535 }
546 /* If this target is normally configured to use APCS frames, warn if they
547 are turned off and debugging is turned on. */
550 && ! TARGET_APCS_FRAME
554 /* If stack checking is disabled, we can use r10 as the PIC register,
555 which keeps r9 available. */
562 /* Initialise boolean versions of the flags, for use in the arm.md file. */
573 /* Default value for floating point code... if no co-processor
574 bus, then schedule for emulated floating point. Otherwise,
575 assume the user has an FPA.
576 Note: this does not prevent use of floating point instructions,
577 -msoft-float does that. */
581 {
586 else
588 target_fp_name);
589 }
590 else
596 /* For arm2/3 there is no need to do any scheduling if there is only
597 a floating point emulator, or we are doing software floating-point. */
605 {
610 else
612 }
615 {
623 /* Prevent the user from choosing an obviously stupid PIC register. */
629 else
631 }
634 {
635 /* Don't warn since it's on by default in -O2. */
637 }
639 /* If optimizing for space, don't synthesize constants.
640 For processors with load scheduling, it never costs more than 2 cycles
641 to load a constant, and the load scheduler may well reduce that to 1. */
645 /* If optimizing for size, bump the number of instructions that we
646 are prepared to conditionally execute (even on a StrongARM).
647 Otherwise for the StrongARM, which has early execution of branches,
648 a sequence that is worth skipping is shorter. */
654 /* Register global variables with the garbage collector. */
656 }
658 static void
660 {
664 /* XXX: What about the minipool tables? */
665 }
666 \f
667 /* Return 1 if it is possible to return using a single instruction. */
668 int
671 {
674 /* Never use a return instruction before reload has run. */
676 /* Or if the function is variadic. */
677 || current_function_pretend_args_size
678 || current_function_anonymous_args
679 /* Of if the function calls __builtin_eh_return () */
681 /* Or if there is no frame pointer and there is a stack adjustment. */
686 /* Can't be done if interworking with Thumb, and any registers have been
687 stacked. Similarly, on StrongARM, conditional returns are expensive
688 if they aren't taken and registers have been stacked. */
694 {
701 }
703 /* Can't be done if any of the FPU regs are pushed, since this also
704 requires an insn. */
710 /* If a function is naked, don't use the "return" insn. */
715 }
717 /* Return TRUE if int I is a valid immediate ARM constant. */
719 int
721 HOST_WIDE_INT i;
722 {
725 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
726 be all zero, or all one. */
733 /* Fast return for 0 and powers of 2 */
737 do
738 {
741 mask =
747 }
749 /* Return true if I is a valid constant for the operation CODE. */
750 static int
752 HOST_WIDE_INT i;
754 {
759 {
773 }
774 }
776 /* Emit a sequence of insns to handle a large constant.
777 CODE is the code of the operation required, it can be any of SET, PLUS,
778 IOR, AND, XOR, MINUS;
779 MODE is the mode in which the operation is being performed;
780 VAL is the integer to operate on;
781 SOURCE is the other operand (a register, or a null-pointer for SET);
782 SUBTARGETS means it is safe to create scratch registers if that will
783 either produce a simpler sequence, or we will want to cse the values.
784 Return value is the number of insns emitted. */
786 int
790 HOST_WIDE_INT val;
791 rtx target;
792 rtx source;
794 {
798 {
799 /* After arm_reorg has been called, we can't fix up expensive
800 constants by pushing them into memory so we must synthesise
801 them in-line, regardless of the cost. This is only likely to
802 be more costly on chips that have load delay slots and we are
803 compiling without running the scheduler (so no splitting
804 occurred before the final instruction emission).
806 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
807 */
811 {
813 {
814 /* Currently SET is the only monadic value for CODE, all
815 the rest are diadic. */
818 }
819 else
820 {
824 /* For MINUS, the value is subtracted from, since we never
825 have subtraction of a constant. */
829 else
833 }
834 }
835 }
838 }
840 /* As above, but extra parameter GENERATE which, if clear, suppresses
841 RTL generation. */
842 static int
846 HOST_WIDE_INT val;
847 rtx target;
848 rtx source;
851 {
866 /* Find out which operations are safe for a given CODE. Also do a quick
867 check for degenerate cases; these can occur when DImode operations
868 are split. */
870 {
884 {
889 }
891 {
897 }
902 {
906 }
908 {
914 }
920 {
926 }
928 {
933 }
935 /* We don't know how to handle this yet below. */
939 /* We treat MINUS as (val - source), since (source - val) is always
940 passed as (source + (-val)). */
942 {
947 }
949 {
953 source)));
955 }
962 }
964 /* If we can do it in one insn get out quickly. */
968 {
975 }
977 /* Calculate a few attributes that may be useful for specific
978 optimizations. */
980 {
982 clear_sign_bit_copies++;
983 else
985 }
988 {
990 set_sign_bit_copies++;
991 else
993 }
996 {
998 clear_zero_bit_copies++;
999 else
1001 }
1004 {
1006 set_zero_bit_copies++;
1007 else
1009 }
1012 {
1014 /* See if we can do this by sign_extending a constant that is known
1015 to be negative. This is a good, way of doing it, since the shift
1016 may well merge into a subsequent insn. */
1018 {
1022 {
1024 {
1030 }
1032 }
1033 /* For an inverted constant, we will need to set the low bits,
1034 these will be shifted out of harm's way. */
1037 {
1039 {
1045 }
1047 }
1048 }
1050 /* See if we can generate this by setting the bottom (or the top)
1051 16 bits, and then shifting these into the other half of the
1052 word. We only look for the simplest cases, to do more would cost
1053 too much. Be careful, however, not to generate this when the
1054 alternative would take fewer insns. */
1056 {
1060 /* Overlaps outside this range are best done using other methods. */
1062 {
1066 {
1067 rtx new_src = (subtargets
1079 source)));
1081 }
1082 }
1084 /* Don't duplicate cases already considered. */
1086 {
1089 {
1090 rtx new_src = (subtargets
1097 emit_insn
1099 gen_rtx_IOR
1103 source)));
1105 }
1106 }
1107 }
1112 /* If we have IOR or XOR, and the constant can be loaded in a
1113 single instruction, and we can find a temporary to put it in,
1114 then this can be done in two instructions instead of 3-4. */
1116 /* TARGET can't be NULL if SUBTARGETS is 0 */
1118 {
1120 {
1122 {
1128 }
1130 }
1131 }
1138 {
1140 {
1147 source,
1148 shift))));
1152 shift))));
1153 }
1155 }
1159 {
1161 {
1168 source,
1169 shift))));
1173 shift))));
1174 }
1176 }
1179 {
1181 {
1193 }
1195 }
1199 /* See if two shifts will do 2 or more insn's worth of work. */
1201 {
1207 {
1209 {
1214 }
1215 else
1216 {
1220 }
1221 }
1224 {
1230 }
1233 }
1236 {
1240 {
1242 {
1248 }
1249 else
1250 {
1255 }
1256 }
1259 {
1265 }
1268 }
1274 }
1278 num_bits_set++;
1284 else
1285 {
1288 }
1290 /* Now try and find a way of doing the job in either two or three
1291 instructions.
1292 We start by looking for the largest block of zeros that are aligned on
1293 a 2-bit boundary, we then fill up the temps, wrapping around to the
1294 top of the word when we drop off the bottom.
1295 In the worst case this code should produce no more than four insns. */
1296 {
1301 {
1305 {
1307 {
1310 }
1312 {
1315 }
1317 }
1318 }
1320 /* Now start emitting the insns, starting with the one with the highest
1321 bit set: we do this so that the smallest number will be emitted last;
1322 this is more likely to be combinable with addressing insns. */
1324 do
1325 {
1331 {
1340 {
1341 rtx new_src;
1345 new_src = (subtargets
1352 new_src = (subtargets
1356 source)));
1357 else
1359 new_src = (remainder
1360 ? (subtargets
1366 : (can_negate
1367 ? -temp1
1370 }
1373 {
1376 }
1380 insns++;
1382 }
1385 }
1387 }
1389 /* Canonicalize a comparison so that we are more likely to recognize it.
1390 This can be done for a few constant compares, where we can make the
1391 immediate value easier to load. */
1392 enum rtx_code
1396 {
1400 {
1410 {
1413 }
1420 {
1423 }
1430 {
1433 }
1440 {
1443 }
1448 }
1451 }
1453 /* Decide whether a type should be returned in memory (true)
1454 or in a register (false). This is called by the macro
1455 RETURN_IN_MEMORY. */
1456 int
1458 tree type;
1459 {
1461 /* All simple types are returned in registers. */
1464 /* For the arm-wince targets we choose to be compitable with Microsoft's
1465 ARM and Thumb compilers, which always return aggregates in memory. */
1466 #ifndef ARM_WINCE
1469 /* All structures/unions bigger than one word are returned in memory. */
1473 {
1474 tree field;
1476 /* For a struct the APCS says that we only return in a register
1477 if the type is 'integer like' and every addressable element
1478 has an offset of zero. For practical purposes this means
1479 that the structure can have at most one non bit-field element
1480 and that this element must be the first one in the structure. */
1482 /* Find the first field, ignoring non FIELD_DECL things which will
1483 have been created by C++. */
1492 /* Check that the first field is valid for returning in a register. */
1494 /* ... Floats are not allowed */
1498 /* ... Aggregates that are not themselves valid for returning in
1499 a register are not allowed. */
1503 /* Now check the remaining fields, if any. Only bitfields are allowed,
1504 since they are not addressable. */
1506 field;
1508 {
1514 }
1517 }
1520 {
1521 tree field;
1523 /* Unions can be returned in registers if every element is
1524 integral, or can be returned in an integer register. */
1526 field;
1528 {
1537 }
1540 }
1543 /* Return all other types in memory. */
1545 }
1547 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1548 for a call to a function whose data type is FNTYPE.
1549 For a library call, FNTYPE is NULL. */
1550 void
1553 tree fntype;
1554 rtx libname ATTRIBUTE_UNUSED;
1556 {
1557 /* On the ARM, the offset starts at 0. */
1565 /* Check for long call/short call attributes. The attributes
1566 override any command line option. */
1568 {
1573 }
1574 }
1576 /* Determine where to put an argument to a function.
1577 Value is zero to push the argument on the stack,
1578 or a hard register in which to store the argument.
1580 MODE is the argument's machine mode.
1581 TYPE is the data type of the argument (as a tree).
1582 This is null for libcalls where that information may
1583 not be available.
1584 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1585 the preceding args and about the function being called.
1586 NAMED is nonzero if this argument is a named parameter
1587 (otherwise it is an extra parameter matching an ellipsis). */
1588 rtx
1592 tree type ATTRIBUTE_UNUSED;
1594 {
1596 /* Compute operand 2 of the call insn. */
1603 }
1604 \f
1605 /* Encode the current state of the #pragma [no_]long_calls. */
1607 {
1610 SHORT /* #pragma no_long_calls is in effect. */
1615 /* Handle pragmas for compatibility with Intel's compilers.
1616 FIXME: This is incomplete, since it does not handle all
1617 the pragmas that the Intel compilers understand. */
1618 int
1623 {
1624 /* Should be pragma 'far' or equivalent for callx/balx here. */
1631 else
1635 }
1636 \f
1637 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
1638 attribute for TYPE. The attributes in ATTRIBUTES have previously been
1639 assigned to TYPE. */
1640 int
1642 tree type;
1643 tree attributes ATTRIBUTE_UNUSED;
1644 tree identifier;
1645 tree args;
1646 {
1653 /* Function calls made to this symbol must be done indirectly, because
1654 it may lie outside of the 26 bit addressing range of a normal function
1655 call. */
1659 /* Whereas these functions are always known to reside within the 26 bit
1660 addressing range. */
1665 }
1667 /* Return 0 if the attributes for two types are incompatible, 1 if they
1668 are compatible, and 2 if they are nearly compatible (which causes a
1669 warning to be generated). */
1670 int
1672 tree type1;
1673 tree type2;
1674 {
1677 /* Check for mismatch of non-default calling convention. */
1681 /* Check for mismatched call attributes. */
1687 /* Only bother to check if an attribute is defined. */
1689 {
1690 /* If one type has an attribute, the other must have the same attribute. */
1694 /* Disallow mixed attributes. */
1697 }
1700 }
1702 /* Encode long_call or short_call attribute by prefixing
1703 symbol name in DECL with a special character FLAG. */
1704 void
1706 tree decl;
1708 {
1716 /* Do not allow weak functions to be treated as short call. */
1722 else
1728 }
1730 /* Assigns default attributes to newly defined type. This is used to
1731 set short_call/long_call attributes for function types of
1732 functions defined inside corresponding #pragma scopes. */
1733 void
1735 tree type;
1736 {
1737 /* Add __attribute__ ((long_call)) to all functions, when
1738 inside #pragma long_calls or __attribute__ ((short_call)),
1739 when inside #pragma no_long_calls. */
1741 {
1749 else
1754 }
1755 }
1756 \f
1757 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
1758 defined within the current compilation unit. If this caanot be
1759 determined, then 0 is returned. */
1760 static int
1762 rtx sym_ref;
1763 {
1764 /* This is a bit of a fib. A function will have a short call flag
1765 applied to its name if it has the short call attribute, or it has
1766 already been defined within the current compilation unit. */
1770 /* The current function is always defined within the current compilation
1771 unit. if it s a weak defintion however, then this may not be the real
1772 defintion of the function, and so we have to say no. */
1777 /* We cannot make the determination - default to returning 0. */
1779 }
1781 /* Return non-zero if a 32 bit "long_call" should be generated for
1782 this call. We generate a long_call if the function:
1784 a. has an __attribute__((long call))
1785 or b. is within the scope of a #pragma long_calls
1786 or c. the -mlong-calls command line switch has been specified
1788 However we do not generate a long call if the function:
1790 d. has an __attribute__ ((short_call))
1791 or e. is inside the scope of a #pragma no_long_calls
1792 or f. has an __attribute__ ((section))
1793 or g. is defined within the current compilation unit.
1795 This function will be called by C fragments contained in the machine
1796 description file. CALL_REF and CALL_COOKIE correspond to the matched
1797 rtl operands. CALL_SYMBOL is used to distinguish between
1798 two different callers of the function. It is set to 1 in the
1799 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
1800 and "call_value" patterns. This is because of the difference in the
1801 SYM_REFs passed by these patterns. */
1802 int
1804 rtx sym_ref;
1807 {
1809 {
1814 }
1831 }
1832 \f
1833 int
1835 rtx x;
1836 {
1838 && flag_pic
1846 }
1848 rtx
1850 rtx orig;
1852 rtx reg;
1853 {
1855 {
1857 rtx insn;
1861 {
1864 else
1868 }
1870 #ifdef AOF_ASSEMBLER
1871 /* The AOF assembler can generate relocations for these directly, and
1872 understands that the PIC register has to be added into the offset. */
1874 #else
1877 else
1884 address));
1887 #endif
1889 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1890 by loop. */
1894 }
1896 {
1904 {
1907 else
1909 }
1912 {
1916 }
1917 else
1921 {
1922 /* The base register doesn't really matter, we only want to
1923 test the index for the appropriate mode. */
1928 else
1931 win:
1934 }
1939 {
1942 }
1945 }
1947 {
1951 {
1959 }
1960 }
1963 }
1967 int
1969 rtx x;
1970 {
1974 }
1976 void
1978 {
1979 #ifndef AOF_ASSEMBLER
1981 rtx global_offset_table;
1993 /* On the ARM the PC register contains 'dot + 8' at the time of the
1994 addition, on the Thumb it is 'dot + 4'. */
1999 else
2007 else
2014 /* Need to emit this whether or not we obey regdecls,
2015 since setjmp/longjmp can cause life info to screw up. */
2018 }
2020 #define REG_OR_SUBREG_REG(X) \
2021 (GET_CODE (X) == REG \
2022 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2024 #define REG_OR_SUBREG_RTX(X) \
2025 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2027 #ifndef COSTS_N_INSNS
2028 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2029 #endif
2031 int
2033 rtx x;
2036 {
2042 {
2044 {
2058 {
2063 {
2065 cycles ++;
2066 }
2068 }
2078 {
2084 }
2114 /* XXX guess. */
2119 /* XXX another guess. */
2120 /* Memory costs quite a lot for the first word, but subsequent words
2121 load at the equivalent of a single insn each. */
2126 /* XXX a guess. */
2132 /* XXX still guessing. */
2134 {
2148 }
2152 #if 0
2157 /* XXX guess */
2161 #endif
2162 }
2163 }
2166 {
2168 /* Memory costs quite a lot for the first word, but subsequent words
2169 load at the equivalent of a single insn each. */
2180 /* Fall through */
2184 /* Fall through */
2235 /* Fall through */
2245 /* Fall through */
2249 /* Normally the frame registers will be spilt into reg+const during
2250 reload, so it is a bad idea to combine them with other instructions,
2251 since then they might not be moved outside of loops. As a compromise
2252 we allow integration with ops that have a constant as their second
2253 operand. */
2292 /* There is no point basing this on the tuning, since it is always the
2293 fast variant if it exists at all. */
2305 {
2311 /* Tune as appropriate. */
2315 {
2318 }
2321 }
2341 /* Fall through */
2363 /* Fall through */
2366 {
2380 }
2393 else
2411 }
2412 }
2414 int
2416 rtx insn;
2417 rtx link;
2418 rtx dep;
2420 {
2423 /* XXX This is not strictly true for the FPA. */
2428 /* Call insns don't incur a stall, even if they follow a load. */
2437 {
2438 /* This is a load after a store, there is no conflict if the load reads
2439 from a cached area. Assume that loads from the stack, and from the
2440 constant pool are cached, and that others will miss. This is a
2441 hack. */
2449 }
2452 }
2454 /* This code has been fixed for cross compilation. */
2459 {
2462 };
2466 static void
2468 {
2470 REAL_VALUE_TYPE r;
2473 {
2476 }
2479 }
2481 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2483 int
2485 rtx x;
2486 {
2487 REAL_VALUE_TYPE r;
2502 }
2504 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2506 int
2508 rtx x;
2509 {
2510 REAL_VALUE_TYPE r;
2526 }
2527 \f
2528 /* Predicates for `match_operand' and `match_operator'. */
2530 /* s_register_operand is the same as register_operand, but it doesn't accept
2531 (SUBREG (MEM)...).
2533 This function exists because at the time it was put in it led to better
2534 code. SUBREG(MEM) always needs a reload in the places where
2535 s_register_operand is used, and this seemed to lead to excessive
2536 reloading. */
2538 int
2542 {
2549 /* We don't consider registers whose class is NO_REGS
2550 to be a register operand. */
2551 /* XXX might have to check for lo regs only for thumb ??? */
2555 }
2557 /* Only accept reg, subreg(reg), const_int. */
2559 int
2563 {
2573 /* We don't consider registers whose class is NO_REGS
2574 to be a register operand. */
2578 }
2580 /* Return 1 if OP is an item in memory, given that we are in reload. */
2582 int
2584 rtx op;
2586 {
2593 }
2595 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2596 memory access (architecture V4).
2597 MODE is QImode if called when computing contraints, or VOIDmode when
2598 emitting patterns. In this latter case we cannot use memory_operand()
2599 because it will fail on badly formed MEMs, which is precisly what we are
2600 trying to catch. */
2601 int
2603 rtx op;
2605 {
2606 #if 0
2609 #endif
2615 /* A sum of anything more complex than reg + reg or reg + const is bad. */
2622 /* Big constants are also bad. */
2628 /* Everything else is good, or can will automatically be made so. */
2630 }
2632 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
2634 int
2636 rtx op;
2638 {
2641 }
2643 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
2644 */
2646 int
2648 rtx op;
2650 {
2654 }
2656 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
2657 constant that is valid when negated. */
2659 int
2661 rtx op;
2663 {
2671 }
2673 int
2675 rtx op;
2677 {
2682 }
2684 /* Return TRUE if the operand is a memory reference which contains an
2685 offsettable address. */
2686 int
2690 {
2698 }
2700 /* Return TRUE if the operand is a memory reference which is, or can be
2701 made word aligned by adjusting the offset. */
2702 int
2706 {
2707 rtx reg;
2726 }
2728 /* Similar to s_register_operand, but does not allow hard integer
2729 registers. */
2730 int
2734 {
2741 /* We don't consider registers whose class is NO_REGS
2742 to be a register operand. */
2746 }
2748 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
2750 int
2752 rtx op;
2754 {
2765 }
2767 int
2769 rtx op;
2771 {
2783 }
2785 /* Return nonzero if OP is a constant power of two. */
2787 int
2789 rtx op;
2791 {
2793 {
2796 }
2798 }
2800 /* Return TRUE for a valid operand of a DImode operation.
2801 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2802 Note that this disallows MEM(REG+REG), but allows
2803 MEM(PRE/POST_INC/DEC(REG)). */
2805 int
2807 rtx op;
2809 {
2820 {
2830 }
2831 }
2833 /* Like di_operand, but don't accept constants. */
2834 int
2836 rtx op;
2838 {
2852 }
2854 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
2855 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
2856 Note that this disallows MEM(REG+REG), but allows
2857 MEM(PRE/POST_INC/DEC(REG)). */
2859 int
2861 rtx op;
2863 {
2877 {
2886 }
2887 }
2889 /* Like soft_df_operand, but don't accept constants. */
2890 int
2892 rtx op;
2894 {
2907 }
2909 /* Return TRUE for valid index operands. */
2910 int
2912 rtx op;
2914 {
2919 }
2921 /* Return TRUE for valid shifts by a constant. This also accepts any
2922 power of two on the (somewhat overly relaxed) assumption that the
2923 shift operator in this case was a mult. */
2925 int
2927 rtx op;
2929 {
2934 }
2936 /* Return TRUE for arithmetic operators which can be combined with a multiply
2937 (shift). */
2939 int
2941 rtx x;
2943 {
2946 else
2947 {
2952 }
2953 }
2955 /* Return TRUE for binary logical operators. */
2957 int
2959 rtx x;
2961 {
2964 else
2965 {
2969 }
2970 }
2972 /* Return TRUE for shift operators. */
2974 int
2976 rtx x;
2978 {
2981 else
2982 {
2990 }
2991 }
2993 /* Return TRUE if x is EQ or NE. */
2994 int
2996 rtx x;
2998 {
3000 }
3002 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3003 int
3005 rtx x;
3007 {
3014 }
3016 /* Return TRUE if this is the condition code register, if we aren't given
3017 a mode, accept any class CCmode register. */
3018 int
3020 rtx x;
3022 {
3024 {
3029 }
3037 }
3039 /* Return TRUE if this is the condition code register, if we aren't given
3040 a mode, accept any class CCmode register which indicates a dominance
3041 expression. */
3042 int
3044 rtx x;
3046 {
3048 {
3053 }
3063 }
3065 /* Return TRUE if X references a SYMBOL_REF. */
3066 int
3068 rtx x;
3069 {
3079 {
3081 {
3087 }
3090 }
3093 }
3095 /* Return TRUE if X references a LABEL_REF. */
3096 int
3098 rtx x;
3099 {
3108 {
3110 {
3116 }
3119 }
3122 }
3124 enum rtx_code
3126 rtx x;
3127 {
3140 }
3142 /* Return 1 if memory locations are adjacent. */
3143 int
3146 {
3156 {
3158 {
3161 }
3162 else
3165 {
3168 }
3169 else
3172 }
3174 }
3176 /* Return 1 if OP is a load multiple operation. It is known to be
3177 parallel and the first section will be tested. */
3178 int
3180 rtx op;
3182 {
3185 rtx src_addr;
3187 rtx elt;
3193 /* Check to see if this might be a write-back. */
3195 {
3196 i++;
3199 /* Now check it more carefully. */
3206 }
3208 /* Perform a quick check so we don't blow up below. */
3219 {
3233 }
3236 }
3238 /* Return 1 if OP is a store multiple operation. It is known to be
3239 parallel and the first section will be tested. */
3240 int
3242 rtx op;
3244 {
3247 rtx dest_addr;
3249 rtx elt;
3255 /* Check to see if this might be a write-back. */
3257 {
3258 i++;
3261 /* Now check it more carefully. */
3268 }
3270 /* Perform a quick check so we don't blow up below. */
3281 {
3295 }
3298 }
3300 int
3307 {
3314 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3315 extended if required. */
3319 /* Loop over the operands and check that the memory references are
3320 suitable (ie immediate offsets from the same base register). At
3321 the same time, extract the target register, and the memory
3322 offsets. */
3324 {
3325 rtx reg;
3326 rtx offset;
3328 /* Convert a subreg of a mem into the mem itself. */
3335 /* Don't reorder volatile memory references; it doesn't seem worth
3336 looking for the case where the order is ok anyway. */
3352 {
3354 {
3360 }
3361 else
3362 {
3364 /* Not addressed from the same base register. */
3372 }
3374 /* If it isn't an integer register, or if it overwrites the
3375 base register but isn't the last insn in the list, then
3376 we can't do this. */
3382 }
3383 else
3384 /* Not a suitable memory address. */
3386 }
3388 /* All the useful information has now been extracted from the
3389 operands into unsorted_regs and unsorted_offsets; additionally,
3390 order[0] has been set to the lowest numbered register in the
3391 list. Sort the registers into order, and check that the memory
3392 offsets are ascending and adjacent. */
3395 {
3405 /* Have we found a suitable register? if not, one must be used more
3406 than once. */
3410 /* Is the memory address adjacent and ascending? */
3413 }
3416 {
3423 }
3437 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3438 if the offset isn't small enough. The reason 2 ldrs are faster
3439 is because these ARMs are able to do more than one cache access
3440 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3441 whilst the ARM8 has a double bandwidth cache. This means that
3442 these cores can do both an instruction fetch and a data fetch in
3443 a single cycle, so the trick of calculating the address into a
3444 scratch register (one of the result regs) and then doing a load
3445 multiple actually becomes slower (and no smaller in code size).
3446 That is the transformation
3448 ldr rd1, [rbase + offset]
3449 ldr rd2, [rbase + offset + 4]
3451 to
3453 add rd1, rbase, offset
3454 ldmia rd1, {rd1, rd2}
3456 produces worse code -- '3 cycles + any stalls on rd2' instead of
3457 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3458 access per cycle, the first sequence could never complete in less
3459 than 6 cycles, whereas the ldm sequence would only take 5 and
3460 would make better use of sequential accesses if not hitting the
3461 cache.
3463 We cheat here and test 'arm_ld_sched' which we currently know to
3464 only be true for the ARM8, ARM9 and StrongARM. If this ever
3465 changes, then the test below needs to be reworked. */
3469 /* Can't do it without setting up the offset, only do this if it takes
3470 no more than one insn. */
3473 }
3479 {
3482 HOST_WIDE_INT offset;
3487 {
3509 else
3520 }
3533 }
3535 int
3542 {
3549 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3550 extended if required. */
3554 /* Loop over the operands and check that the memory references are
3555 suitable (ie immediate offsets from the same base register). At
3556 the same time, extract the target register, and the memory
3557 offsets. */
3559 {
3560 rtx reg;
3561 rtx offset;
3563 /* Convert a subreg of a mem into the mem itself. */
3570 /* Don't reorder volatile memory references; it doesn't seem worth
3571 looking for the case where the order is ok anyway. */
3587 {
3589 {
3595 }
3596 else
3597 {
3599 /* Not addressed from the same base register. */
3607 }
3609 /* If it isn't an integer register, then we can't do this. */
3614 }
3615 else
3616 /* Not a suitable memory address. */
3618 }
3620 /* All the useful information has now been extracted from the
3621 operands into unsorted_regs and unsorted_offsets; additionally,
3622 order[0] has been set to the lowest numbered register in the
3623 list. Sort the registers into order, and check that the memory
3624 offsets are ascending and adjacent. */
3627 {
3637 /* Have we found a suitable register? if not, one must be used more
3638 than once. */
3642 /* Is the memory address adjacent and ascending? */
3645 }
3648 {
3655 }
3670 }
3676 {
3679 HOST_WIDE_INT offset;
3684 {
3703 }
3716 }
3718 int
3720 rtx op;
3722 {
3730 }
3731 \f
3732 /* Routines for use with attributes. */
3734 /* Return nonzero if ATTR is a valid attribute for DECL.
3735 ATTRIBUTES are any existing attributes and ARGS are
3736 the arguments supplied with ATTR.
3738 Supported attributes:
3740 naked:
3741 don't output any prologue or epilogue code, the user is assumed
3742 to do the right thing.
3744 interfacearm:
3745 Always assume that this function will be entered in ARM mode,
3746 not Thumb mode, and that the caller wishes to be returned to in
3747 ARM mode. */
3748 int
3750 tree decl;
3751 tree attr;
3752 tree args;
3753 {
3760 #ifdef ARM_PE
3766 }
3768 /* Return non-zero if FUNC is a naked function. */
3769 static int
3771 tree func;
3772 {
3773 tree a;
3780 }
3781 \f
3782 /* Routines for use in generating RTL. */
3783 rtx
3788 rtx from;
3794 {
3796 rtx result;
3798 rtx mem;
3803 {
3808 count++;
3809 }
3812 {
3819 }
3822 }
3824 rtx
3829 rtx to;
3835 {
3837 rtx result;
3839 rtx mem;
3844 {
3849 count++;
3850 }
3853 {
3861 }
3864 }
3866 int
3869 {
3875 rtx mem;
3906 {
3909 src_unchanging_p,
3910 src_in_struct_p,
3911 src_scalar_p));
3912 else
3918 {
3921 dst_unchanging_p,
3922 dst_in_struct_p,
3923 dst_scalar_p));
3929 dst_unchanging_p,
3930 dst_in_struct_p,
3931 dst_scalar_p));
3932 else
3933 {
3941 }
3942 }
3946 }
3948 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
3950 {
3951 rtx sreg;
3966 in_words_to_go--;
3970 }
3973 {
3982 }
3988 {
3991 /* The bytes we want are in the top end of the word. */
3997 {
4005 {
4009 }
4010 }
4012 }
4013 else
4014 {
4016 {
4024 {
4030 }
4031 }
4034 {
4040 }
4041 }
4044 }
4046 /* Generate a memory reference for a half word, such that it will be loaded
4047 into the top 16 bits of the word. We can assume that the address is
4048 known to be alignable and of the form reg, or plus (reg, const). */
4049 rtx
4051 rtx memref;
4052 {
4057 {
4060 }
4062 /* If we aren't allowed to generate unaligned addresses, then fail. */
4073 }
4075 static enum machine_mode
4077 rtx x;
4078 rtx y;
4079 HOST_WIDE_INT cond_or;
4080 {
4084 /* Currently we will probably get the wrong result if the individual
4085 comparisons are not simple. This also ensures that it is safe to
4086 reverse a comparison if necessary. */
4096 /* If the comparisons are not equal, and one doesn't dominate the other,
4097 then we can't do this. */
4104 {
4108 }
4111 {
4117 {
4123 }
4163 /* The remaining cases only occur when both comparisons are the
4164 same. */
4182 }
4185 }
4187 enum machine_mode
4190 rtx x;
4191 rtx y;
4192 {
4193 /* All floating point compares return CCFP if it is an equality
4194 comparison, and CCFPE otherwise. */
4198 /* A compare with a shifted operand. Because of canonicalization, the
4199 comparison will have to be swapped when we emit the assembler. */
4206 /* This is a special case that is used by combine to allow a
4207 comparison of a shifted byte load to be split into a zero-extend
4208 followed by a comparison of the shifted integer (only valid for
4209 equalities and unsigned inequalities). */
4221 /* An operation that sets the condition codes as a side-effect, the
4222 V flag is not set correctly, so we can only use comparisons where
4223 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4224 instead. */
4237 /* A construct for a conditional compare, if the false arm contains
4238 0, then both conditions must be true, otherwise either condition
4239 must be true. Not all conditions are possible, so CCmode is
4240 returned if it can't be done. */
4258 }
4260 /* X and Y are two things to compare using CODE. Emit the compare insn and
4261 return the rtx for register 0 in the proper mode. FP means this is a
4262 floating point compare: I don't think that it is needed on the arm. */
4264 rtx
4268 {
4276 }
4278 void
4281 {
4287 {
4294 }
4297 {
4298 /* We have a pseudo which has been spilt onto the stack; there
4299 are two cases here: the first where there is a simple
4300 stack-slot replacement and a second where the stack-slot is
4301 out of range, or is used as a subreg. */
4303 {
4306 }
4307 else
4308 /* The slot is out of range, or was dressed up in a SUBREG. */
4310 }
4311 else
4314 /* Handle the case where the address is too complex to be offset by 1. */
4317 {
4322 }
4324 {
4325 /* The addend must be CONST_INT, or we would have dealt with it above. */
4331 /* Rework the address into a legal sequence of insns. */
4332 /* Valid range for lo is -4095 -> 4095 */
4337 /* Corner case, if lo is the max offset then we would be out of range
4338 once we have added the additional 1 below, so bump the msb into the
4339 pre-loading insn(s). */
4351 {
4354 /* Get the base address; addsi3 knows how to handle constants
4355 that require more than one insn. */
4359 }
4360 }
4366 offset))));
4374 gen_rtx_ASHIFT
4378 scratch)));
4379 else
4386 }
4388 /* Handle storing a half-word to memory during reload by synthesising as two
4389 byte stores. Take care not to clobber the input values until after we
4390 have moved them somewhere safe. This code assumes that if the DImode
4391 scratch in operands[2] overlaps either the input value or output address
4392 in some way, then that value must die in this insn (we absolutely need
4393 two scratch registers for some corner cases). */
4394 void
4397 {
4404 {
4411 }
4415 {
4416 /* We have a pseudo which has been spilt onto the stack; there
4417 are two cases here: the first where there is a simple
4418 stack-slot replacement and a second where the stack-slot is
4419 out of range, or is used as a subreg. */
4421 {
4424 }
4425 else
4426 /* The slot is out of range, or was dressed up in a SUBREG. */
4428 }
4429 else
4434 /* Handle the case where the address is too complex to be offset by 1. */
4437 {
4440 /* Be careful not to destroy OUTVAL. */
4442 {
4443 /* Updating base_plus might destroy outval, see if we can
4444 swap the scratch and base_plus. */
4446 {
4450 }
4451 else
4452 {
4455 /* Be conservative and copy OUTVAL into the scratch now,
4456 this should only be necessary if outval is a subreg
4457 of something larger than a word. */
4458 /* XXX Might this clobber base? I can't see how it can,
4459 since scratch is known to overlap with OUTVAL, and
4460 must be wider than a word. */
4463 }
4464 }
4468 }
4470 {
4471 /* The addend must be CONST_INT, or we would have dealt with it above. */
4477 /* Rework the address into a legal sequence of insns. */
4478 /* Valid range for lo is -4095 -> 4095 */
4483 /* Corner case, if lo is the max offset then we would be out of range
4484 once we have added the additional 1 below, so bump the msb into the
4485 pre-loading insn(s). */
4497 {
4500 /* Be careful not to destroy OUTVAL. */
4502 {
4503 /* Updating base_plus might destroy outval, see if we
4504 can swap the scratch and base_plus. */
4506 {
4510 }
4511 else
4512 {
4515 /* Be conservative and copy outval into scratch now,
4516 this should only be necessary if outval is a
4517 subreg of something larger than a word. */
4518 /* XXX Might this clobber base? I can't see how it
4519 can, since scratch is known to overlap with
4520 outval. */
4523 }
4524 }
4526 /* Get the base address; addsi3 knows how to handle constants
4527 that require more than one insn. */
4531 }
4532 }
4535 {
4544 }
4545 else
4546 {
4555 }
4556 }
4557 \f
4558 /* Print a symbolic form of X to the debug file, F. */
4559 static void
4562 rtx x;
4563 {
4565 {
4603 }
4604 }
4605 \f
4606 /* Routines for manipulation of the constant pool. */
4608 /* Arm instructions cannot load a large constant directly into a
4609 register; they have to come from a pc relative load. The constant
4610 must therefore be placed in the addressable range of the pc
4611 relative load. Depending on the precise pc relative load
4612 instruction the range is somewhere between 256 bytes and 4k. This
4613 means that we often have to dump a constant inside a function, and
4614 generate code to branch around it.
4616 It is important to minimize this, since the branches will slow
4617 things down and make the code larger.
4619 Normally we can hide the table after an existing unconditional
4620 branch so that there is no interruption of the flow, but in the
4621 worst case the code looks like this:
4623 ldr rn, L1
4624 ...
4625 b L2
4626 align
4627 L1: .long value
4628 L2:
4629 ...
4631 ldr rn, L3
4632 ...
4633 b L4
4634 align
4635 L3: .long value
4636 L4:
4637 ...
4639 We fix this by performing a scan after scheduling, which notices
4640 which instructions need to have their operands fetched from the
4641 constant table and builds the table.
4643 The algorithm starts by building a table of all the constants that
4644 need fixing up and all the natural barriers in the function (places
4645 where a constant table can be dropped without breaking the flow).
4646 For each fixup we note how far the pc-relative replacement will be
4647 able to reach and the offset of the instruction into the function.
4649 Having built the table we then group the fixes together to form
4650 tables that are as large as possible (subject to addressing
4651 constraints) and emit each table of constants after the last
4652 barrier that is within range of all the instructions in the group.
4653 If a group does not contain a barrier, then we forcibly create one
4654 by inserting a jump instruction into the flow. Once the table has
4655 been inserted, the insns are then modified to reference the
4656 relevant entry in the pool.
4658 Possible enhancements to the algorithm (not implemented) are:
4660 1) For some processors and object formats, there may be benefit in
4661 aligning the pools to the start of cache lines; this alignment
4662 would need to be taken into account when calculating addressability
4663 of a pool. */
4665 /* These typedefs are located at the start of this file, so that
4666 they can be used in the prototypes there. This comment is to
4667 remind readers of that fact so that the following structures
4668 can be understood more easily.
4670 typedef struct minipool_node Mnode;
4671 typedef struct minipool_fixup Mfix; */
4673 struct minipool_node
4674 {
4675 /* Doubly linked chain of entries. */
4678 /* The maximum offset into the code that this entry can be placed. While
4679 pushing fixes for forward references, all entries are sorted in order
4680 of increasing max_address. */
4681 HOST_WIDE_INT max_address;
4682 /* Similarly for a entry inserted for a backwards ref. */
4683 HOST_WIDE_INT min_address;
4684 /* The number of fixes referencing this entry. This can become zero
4685 if we "unpush" an entry. In this case we ignore the entry when we
4686 come to emit the code. */
4688 /* The offset from the start of the minipool. */
4689 HOST_WIDE_INT offset;
4690 /* The value in table. */
4691 rtx value;
4692 /* The mode of value. */
4695 };
4697 struct minipool_fixup
4698 {
4700 rtx insn;
4701 HOST_WIDE_INT address;
4705 rtx value;
4707 HOST_WIDE_INT forwards;
4708 HOST_WIDE_INT backwards;
4709 };
4711 /* Fixes less than a word need padding out to a word boundary. */
4712 #define MINIPOOL_FIX_SIZE(mode) \
4713 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
4719 /* The linked list of all minipool fixes required for this function. */
4722 /* The fix entry for the current minipool, once it has been placed. */
4725 /* Determines if INSN is the start of a jump table. Returns the end
4726 of the TABLE or NULL_RTX. */
4727 static rtx
4729 rtx insn;
4730 {
4731 rtx table;
4744 }
4746 static HOST_WIDE_INT
4748 rtx insn;
4749 {
4754 }
4756 /* Move a minipool fix MP from its current location to before MAX_MP.
4757 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
4758 contrains may need updating. */
4763 HOST_WIDE_INT max_address;
4764 {
4765 /* This should never be true and the code below assumes these are
4766 different. */
4771 {
4774 }
4775 else
4776 {
4779 else
4782 /* Unlink MP from its current position. Since max_mp is non-null,
4783 mp->prev must be non-null. */
4787 else
4790 /* Re-insert it before MAX_MP. */
4797 else
4799 }
4801 /* Save the new entry. */
4804 /* Scan over the preceeding entries and adjust their addresses as
4805 required. */
4808 {
4811 }
4814 }
4816 /* Add a constant to the minipool for a forward reference. Returns the
4817 node added or NULL if the constant will not fit in this pool. */
4821 {
4822 /* If set, max_mp is the first pool_entry that has a lower
4823 constraint than the one we are trying to add. */
4828 /* If this fix's address is greater than the address of the first
4829 entry, then we can't put the fix in this pool. We subtract the
4830 size of the current fix to ensure that if the table is fully
4831 packed we still have enough room to insert this value by suffling
4832 the other fixes forwards. */
4837 /* Scan the pool to see if a constant with the same value has
4838 already been added. While we are doing this, also note the
4839 location where we must insert the constant if it doesn't already
4840 exist. */
4842 {
4849 {
4850 /* More than one fix references this entry. */
4853 }
4855 /* Note the insertion point if necessary. */
4859 }
4861 /* The value is not currently in the minipool, so we need to create
4862 a new entry for it. If MAX_MP is NULL, the entry will be put on
4863 the end of the list since the placement is less constrained than
4864 any existing entry. Otherwise, we insert the new fix before
4865 MAX_MP and, if neceesary, adjust the constraints on the other
4866 entries. */
4872 /* Not yet required for a backwards ref. */
4876 {
4882 {
4885 }
4886 else
4890 }
4891 else
4892 {
4895 else
4903 else
4905 }
4907 /* Save the new entry. */
4910 /* Scan over the preceeding entries and adjust their addresses as
4911 required. */
4914 {
4917 }
4920 }
4926 HOST_WIDE_INT min_address;
4927 {
4928 HOST_WIDE_INT offset;
4930 /* This should never be true, and the code below assumes these are
4931 different. */
4936 {
4939 }
4940 else
4941 {
4942 /* We will adjust this below if it is too loose. */
4945 /* Unlink MP from its current position. Since min_mp is non-null,
4946 mp->next must be non-null. */
4950 else
4953 /* Reinsert it after MIN_MP. */
4959 else
4961 }
4967 {
4974 }
4977 }
4979 /* Add a constant to the minipool for a backward reference. Returns the
4980 node added or NULL if the constant will not fit in this pool.
4982 Note that the code for insertion for a backwards reference can be
4983 somewhat confusing because the calculated offsets for each fix do
4984 not take into account the size of the pool (which is still under
4985 construction. */
4989 {
4990 /* If set, min_mp is the last pool_entry that has a lower constraint
4991 than the one we are trying to add. */
4993 /* This can be negative, since it is only a constraint. */
4997 /* If we can't reach the current pool from this insn, or if we can't
4998 insert this entry at the end of the pool without pushing other
4999 fixes out of range, then we don't try. This ensures that we
5000 can't fail later on. */
5006 /* Scan the pool to see if a constant with the same value has
5007 already been added. While we are doing this, also note the
5008 location where we must insert the constant if it doesn't already
5009 exist. */
5011 {
5018 /* Check that there is enough slack to move this entry to the
5019 end of the table (this is conservative). */
5024 {
5027 }
5031 else
5032 {
5033 /* Note the insertion point if necessary. */
5038 {
5039 /* Inserting before this entry would push the fix beyond
5040 its maximum address (which can happen if we have
5041 re-located a forwards fix); force the new fix to come
5042 after it. */
5045 }
5046 }
5047 }
5049 /* We need to create a new entry. */
5060 {
5065 {
5068 }
5069 else
5073 }
5074 else
5075 {
5082 else
5084 }
5086 /* Save the new entry. */
5091 else
5094 /* Scan over the following entries and adjust their offsets. */
5096 {
5102 else
5106 }
5109 }
5111 static void
5114 {
5121 {
5126 }
5127 }
5129 /* Output the literal table */
5130 static void
5132 rtx scan;
5133 {
5147 {
5149 {
5151 {
5158 }
5161 {
5162 #ifdef HAVE_consttable_1
5167 #endif
5168 #ifdef HAVE_consttable_2
5173 #endif
5174 #ifdef HAVE_consttable_4
5179 #endif
5180 #ifdef HAVE_consttable_8
5185 #endif
5189 }
5190 }
5194 }
5199 }
5201 /* Return the cost of forcibly inserting a barrier after INSN. */
5202 static int
5204 rtx insn;
5205 {
5206 /* Basing the location of the pool on the loop depth is preferable,
5207 but at the moment, the basic block information seems to be
5208 corrupt by this stage of the compilation. */
5216 {
5218 /* It will always be better to place the table before the label, rather
5219 than after it. */
5231 }
5232 }
5234 /* Find the best place in the insn stream in the range
5235 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5236 Create the barrier by inserting a jump and add a new fix entry for
5237 it. */
5241 HOST_WIDE_INT max_address;
5242 {
5244 rtx barrier;
5248 HOST_WIDE_INT selected_address;
5257 {
5258 rtx tmp;
5261 /* This code shouldn't have been called if there was a natural barrier
5262 within range. */
5266 /* Count the length of this insn. */
5269 /* If there is a jump table, add its length. */
5272 {
5275 /* Jump tables aren't in a basic block, so base the cost on
5276 the dispatch insn. If we select this location, we will
5277 still put the pool after the table. */
5281 {
5285 }
5287 /* Continue after the dispatch table. */
5290 }
5295 {
5299 }
5302 }
5304 /* Create a new JUMP_INSN that branches around a barrier. */
5310 /* Create a minipool barrier entry for the new barrier. */
5318 }
5320 /* Record that there is a natural barrier in the insn stream at
5321 ADDRESS. */
5322 static void
5324 rtx insn;
5325 HOST_WIDE_INT address;
5326 {
5335 else
5339 }
5341 /* Record INSN, which will need fixing up to load a value from the
5342 minipool. ADDRESS is the offset of the insn since the start of the
5343 function; LOC is a pointer to the part of the insn which requires
5344 fixing; VALUE is the constant that must be loaded, which is of type
5345 MODE. */
5346 static void
5348 rtx insn;
5349 HOST_WIDE_INT address;
5352 rtx value;
5353 {
5356 #ifdef AOF_ASSEMBLER
5357 /* PIC symbol refereneces need to be converted into offsets into the
5358 based area. */
5359 /* XXX This shouldn't be done here. */
5374 /* If an insn doesn't have a range defined for it, then it isn't
5375 expecting to be reworked by this code. Better to abort now than
5376 to generate duff assembly code. */
5381 {
5389 }
5391 /* Add it to the chain of fixes. */
5396 else
5400 }
5402 /* Scan INSN and note any of its operands that need fixing. */
5403 static void
5405 rtx insn;
5406 HOST_WIDE_INT address;
5407 {
5415 /* Fill in recog_op_alt with information about the constraints of this
5416 insn. */
5420 {
5421 /* Things we need to fix can only occur in inputs. */
5425 /* If this alternative is a memory reference, then any mention
5426 of constants in this alternative is really to fool reload
5427 into allowing us to accept one there. We need to fix them up
5428 now so that we output the right code. */
5430 {
5436 #if 0
5437 /* RWE: Now we look correctly at the operands for the insn,
5438 this shouldn't be needed any more. */
5439 #ifndef AOF_ASSEMBLER
5440 /* XXX Is this still needed? */
5445 #endif
5446 #endif
5453 }
5454 }
5455 }
5457 void
5459 rtx first;
5460 {
5461 rtx insn;
5467 /* The first insn must always be a note, or the code below won't
5468 scan it properly. */
5472 /* Scan all the insns and record the operands that will need fixing. */
5474 {
5480 {
5481 rtx table;
5486 /* If the insn is a vector jump, add the size of the table
5487 and skip the table. */
5489 {
5492 }
5493 }
5494 }
5498 /* Now scan the fixups and perform the required changes. */
5500 {
5507 /* Skip any further barriers before the next fix. */
5511 /* No more fixes. */
5518 {
5520 {
5525 }
5530 }
5532 /* If we found a barrier, drop back to that; any fixes that we
5533 could have reached but come after the barrier will now go in
5534 the next mini-pool. */
5536 {
5537 /* Reduce the refcount for those fixes that won't go into this
5538 pool after all. */
5542 {
5545 }
5548 }
5549 else
5550 {
5551 /* ftmp is first fix that we can't fit into this pool and
5552 there no natural barriers that we could use. Insert a
5553 new barrier in the code somewhere between the previous
5554 fix and this one, and arrange to jump around it. */
5555 HOST_WIDE_INT max_address;
5557 /* The last item on the list of fixes must be a barrier, so
5558 we can never run off the end of the list of fixes without
5559 last_barrier being set. */
5564 /* Check that there isn't another fix that is in range that
5565 we couldn't fit into this pool because the pool was
5566 already too large: we need to put the pool before such an
5567 instruction. */
5572 }
5577 {
5584 }
5586 /* Scan over the fixes we have identified for this pool, fixing them
5587 up and adding the constants to the pool itself. */
5591 {
5592 rtx addr
5594 minipool_vector_label),
5597 }
5601 }
5603 /* From now on we must synthesize any constants that we can't handle
5604 directly. This can happen if the RTL gets split during final
5605 instruction generation. */
5607 }
5608 \f
5609 /* Routines to output assembly language. */
5611 /* If the rtx is the correct value then return the string of the number.
5612 In this way we can ensure that valid double constants are generated even
5613 when cross compiling. */
5616 rtx x;
5617 {
5618 REAL_VALUE_TYPE r;
5630 }
5632 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
5636 {
5647 }
5649 /* Output the operands of a LDM/STM instruction to STREAM.
5650 MASK is the ARM register set mask of which only bits 0-15 are important.
5651 INSTR is the possibly suffixed base register. HAT unequals zero if a hat
5652 must follow the register list. */
5654 static void
5661 {
5671 {
5677 }
5680 }
5682 /* Output a 'call' insn. */
5687 {
5688 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
5691 {
5694 }
5700 else
5704 }
5706 static int
5709 {
5717 {
5720 {
5723 }
5726 /* Scan through the sub-elements and change any references there. */
5737 }
5738 }
5740 /* Output a 'call' insn that is a reference in memory. */
5745 {
5747 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
5752 {
5756 }
5757 else
5758 {
5761 }
5764 }
5767 /* Output a move from arm registers to an fpu registers.
5768 OPERANDS[0] is an fpu register.
5769 OPERANDS[1] is the first registers of an arm register pair. */
5774 {
5789 }
5791 /* Output a move from an fpu register to arm registers.
5792 OPERANDS[0] is the first registers of an arm register pair.
5793 OPERANDS[1] is an fpu register. */
5798 {
5812 }
5814 /* Output a move from arm registers to arm registers of a long double
5815 OPERANDS[0] is the destination.
5816 OPERANDS[1] is the source. */
5820 {
5821 /* We have to be careful here because the two might overlap. */
5828 {
5830 {
5834 }
5835 }
5836 else
5837 {
5839 {
5843 }
5844 }
5847 }
5850 /* Output a move from arm registers to an fpu registers.
5851 OPERANDS[0] is an fpu register.
5852 OPERANDS[1] is the first registers of an arm register pair. */
5857 {
5869 }
5871 /* Output a move from an fpu register to arm registers.
5872 OPERANDS[0] is the first registers of an arm register pair.
5873 OPERANDS[1] is an fpu register. */
5878 {
5890 }
5892 /* Output a move between double words.
5893 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
5894 or MEM<-REG and all MEMs must be offsettable addresses. */
5899 {
5905 {
5911 {
5916 /* Ensure the second source is not overwritten. */
5919 else
5921 }
5923 {
5925 {
5934 }
5938 {
5942 }
5943 else
5944 {
5948 }
5952 }
5954 {
5955 #if HOST_BITS_PER_WIDE_INT > 32
5956 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
5957 what the upper word is. */
5959 {
5962 }
5963 else
5964 {
5967 }
5968 #else
5969 /* Sign extend the intval into the high-order word. */
5971 {
5975 }
5976 else
5978 #endif
5981 }
5983 {
5985 {
6015 {
6020 {
6022 {
6024 {
6034 }
6037 else
6039 }
6040 else
6042 }
6043 else
6047 }
6048 else
6049 {
6051 /* Take care of overlapping base/data reg. */
6053 {
6056 }
6057 else
6058 {
6061 }
6062 }
6063 }
6064 }
6065 else
6067 }
6069 {
6074 {
6097 {
6099 {
6111 }
6112 }
6113 /* Fall through */
6120 }
6121 }
6122 else
6126 }
6129 /* Output an arbitrary MOV reg, #n.
6130 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6135 {
6140 /* Try to use one MOV */
6142 {
6145 }
6147 /* Try to use one MVN */
6149 {
6153 }
6155 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6159 n_ones++;
6163 else
6167 }
6170 /* Output an ADD r, s, #n where n may be too big for one instruction. If
6171 adding zero to one register, output nothing. */
6176 {
6180 {
6185 else
6188 n);
6189 }
6192 }
6194 /* Output a multiple immediate operation.
6195 OPERANDS is the vector of operands referred to in the output patterns.
6196 INSTR1 is the output pattern to use for the first constant.
6197 INSTR2 is the output pattern to use for subsequent constants.
6198 IMMED_OP is the index of the constant slot in OPERANDS.
6199 N is the constant value. */
6207 HOST_WIDE_INT n;
6208 {
6209 #if HOST_BITS_PER_WIDE_INT > 32
6211 #endif
6214 {
6217 }
6218 else
6219 {
6223 /* Note that n is never zero here (which would give no output). */
6225 {
6227 {
6232 }
6233 }
6234 }
6237 }
6240 /* Return the appropriate ARM instruction for the operation code.
6241 The returned result should not be overwritten. OP is the rtx of the
6242 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6243 was shifted. */
6247 rtx op;
6249 {
6251 {
6269 }
6270 }
6273 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6274 for the operation code. The returned result should not be overwritten.
6275 OP is the rtx code of the shift.
6276 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6277 shift. */
6281 rtx op;
6283 {
6291 else
6295 {
6313 /* We never have to worry about the amount being other than a
6314 power of 2, since this case can never be reloaded from a reg. */
6317 else
6323 }
6326 {
6327 /* This is not 100% correct, but follows from the desire to merge
6328 multiplication by a power of 2 with the recognizer for a
6329 shift. >=32 is not a valid shift for "asl", so we must try and
6330 output a shift that produces the correct arithmetical result.
6331 Using lsr #32 is identical except for the fact that the carry bit
6332 is not set correctly if we set the flags; but we never use the
6333 carry bit from such an operation, so we can ignore that. */
6337 {
6341 }
6343 /* Shifts of 0 are no-ops. */
6346 }
6349 }
6352 /* Obtain the shift from the POWER of two. */
6353 static HOST_WIDE_INT
6355 HOST_WIDE_INT power;
6356 {
6360 {
6363 shift++;
6364 }
6367 }
6369 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6370 /bin/as is horribly restrictive. */
6371 #define MAX_ASCII_LEN 51
6373 void
6378 {
6385 {
6389 {
6392 }
6395 {
6421 /* This is a good place for a line break. */
6423 else
6430 len_so_far ++;
6431 /* drop through. */
6435 {
6437 len_so_far ++;
6438 }
6439 else
6440 {
6443 }
6445 }
6446 }
6449 }
6450 \f
6454 rtx operand;
6457 {
6462 /* If a function is naked, don't use the "return" insn. */
6469 {
6470 /* If this function was declared non-returning, and we have found a tail
6471 call, then we have to trust that the called function won't return. */
6473 {
6476 /* Otherwise, trap an attempted return by aborting. */
6482 }
6485 }
6492 live_regs++;
6495 && ! frame_pointer_needed
6498 live_regs++;
6502 live_regs++;
6505 live_regs++;
6510 /* On some ARM architectures it is faster to use LDR rather than LDM to
6511 load a single register. On other architectures, the cost is the same. */
6523 {
6525 live_regs++;
6530 else
6539 {
6544 }
6547 {
6557 }
6558 else
6559 {
6563 {
6567 }
6573 else
6575 }
6581 {
6588 }
6589 }
6591 {
6594 else
6599 }
6602 }
6604 /* Return nonzero if optimizing and the current function is volatile.
6605 Such functions never return, and many memory cycles can be saved
6606 by not storing register values that will never be needed again.
6607 This optimization was added to speed up context switching in a
6608 kernel application. */
6609 int
6611 {
6613 && current_function_nothrow
6615 }
6617 /* Write the function name into the code section, directly preceding
6618 the function prologue.
6620 Code will be output similar to this:
6621 t0
6622 .ascii "arm_poke_function_name", 0
6623 .align
6624 t1
6625 .word 0xff000000 + (t1 - t0)
6626 arm_poke_function_name
6627 mov ip, sp
6628 stmfd sp!, {fp, ip, lr, pc}
6629 sub fp, ip, #4
6631 When performing a stack backtrace, code can inspect the value
6632 of 'pc' stored at 'fp' + 0. If the trace function then looks
6633 at location pc - 12 and the top 8 bits are set, then we know
6634 that there is a function name embedded immediately preceding this
6635 location and has length ((pc[-3]) & 0xff000000).
6637 We assume that pc is declared as a pointer to an unsigned long.
6639 It is of no benefit to output the function name if we are assembling
6640 a leaf function. These function types will not contain a stack
6641 backtrace structure, therefore it is not possible to determine the
6642 function name. */
6644 void
6648 {
6651 rtx x;
6660 }
6662 /* The amount of stack adjustment that happens here, in output_return and in
6663 output_epilogue must be exactly the same as was calculated during reload,
6664 or things will point to the wrong place. The only time we can safely
6665 ignore this constraint is when a function has no arguments on the stack,
6666 no stack frame requirement and no live registers execpt for `lr'. If we
6667 can guarantee that by making all function calls into tail calls and that
6668 lr is not clobbered in any other way, then there is no need to push lr
6669 onto the stack. */
6670 void
6674 {
6678 /* Nonzero if we must stuff some register arguments onto the stack as if
6679 they were passed there. */
6691 current_function_args_size,
6694 frame_pointer_needed,
6695 current_function_anonymous_args);
6708 && ! frame_pointer_needed
6720 {
6722 }
6725 /* If a di mode load/store multiple is used, and the base register
6726 is r3, then r4 can become an ever live register without lr
6727 doing so, in this case we need to push lr as well, or we
6728 will fail to get a proper return. */
6731 #ifdef AOF_ASSEMBLER
6734 #endif
6735 }
6740 {
6743 /* If we need this, then it will always be at least this much. */
6755 /* Naked functions don't have epilogues. */
6759 /* If we are throwing an exception, the address we want to jump to is in
6760 R1; otherwise, it's in LR. */
6763 /* If we are throwing an exception, then we really must be doing a return,
6764 so we can't tail-call. */
6768 /* A volatile function should never return. Call abort. */
6770 {
6771 rtx op;
6776 }
6780 {
6783 }
6785 /* Handle the frame pointer as a special case. */
6787 && ! frame_pointer_needed
6790 {
6793 }
6795 /* If we aren't loading the PIC register, don't stack it even though it may
6796 be live. */
6799 {
6802 }
6805 {
6807 {
6810 {
6814 }
6815 }
6816 else
6817 {
6821 {
6823 {
6826 /* We can't unstack more than four registers at once. */
6828 {
6832 }
6833 }
6834 else
6835 {
6841 }
6842 }
6844 /* Just in case the last register checked also needs unstacking. */
6849 }
6852 {
6860 }
6862 {
6866 {
6869 /* Even in 26-bit mode we do a mov (rather than a movs)
6870 because we don't have the PSR bits set in the
6871 address. */
6873 }
6874 }
6875 else
6876 {
6880 }
6881 }
6882 else
6883 {
6884 /* Restore stack pointer if necessary. */
6886 {
6891 }
6894 {
6899 }
6900 else
6901 {
6905 {
6907 {
6909 {
6913 }
6914 }
6915 else
6916 {
6920 SP_REGNUM);
6923 }
6924 }
6926 /* Just in case the last register checked also needs unstacking. */
6930 }
6933 {
6935 {
6938 /* Handle LR on its own. */
6940 {
6943 SP_REGNUM);
6944 else
6946 SP_REGNUM);
6947 }
6950 FALSE);
6958 }
6960 {
6963 else
6969 /* Jump to the target; even in 26-bit mode. */
6971 }
6979 else
6983 }
6984 else
6985 {
6987 {
6988 /* Restore the integer regs, and the return address into lr. */
6992 {
6995 SP_REGNUM);
6996 else
6998 SP_REGNUM);
6999 }
7002 FALSE);
7003 }
7006 {
7007 /* Unwind the pre-pushed regs. */
7011 }
7018 {
7019 /* And finally, go home. */
7024 else
7026 }
7027 }
7028 }
7031 }
7033 void
7036 {
7038 {
7039 /* ??? Probably not safe to set this here, since it assumes that a
7040 function will be emitted as assembly immediately after we generate
7041 RTL for it. This does not happen for inline functions. */
7043 }
7044 else
7045 {
7047 && return_used_this_function
7052 /* Reset the ARM-specific per-function variables. */
7055 }
7056 }
7058 /* Generate and emit an insn that we will recognize as a push_multi.
7059 Unfortunately, since this insn does not reflect very well the actual
7060 semantics of the operation, we need to annotate the insn for the benefit
7061 of DWARF2 frame unwind information. */
7062 static rtx
7065 {
7068 rtx par;
7069 rtx dwarf;
7074 num_regs ++;
7084 {
7086 {
7093 stack_pointer_rtx)),
7101 stack_pointer_rtx)),
7102 reg);
7107 }
7108 }
7111 {
7113 {
7121 stack_pointer_rtx)),
7122 reg);
7126 j++;
7127 }
7128 }
7134 }
7136 static rtx
7140 {
7141 rtx par;
7142 rtx dwarf;
7159 tmp
7163 reg);
7168 {
7175 stack_pointer_rtx)),
7176 reg);
7179 }
7185 }
7187 void
7189 {
7195 /* If this function doesn't return, then there is no need to push
7196 the call-saved regs. */
7198 rtx insn;
7200 /* Naked functions don't have prologues. */
7208 {
7214 && ! frame_pointer_needed
7224 }
7227 {
7230 stack_pointer_rtx));
7232 }
7235 {
7237 insn = emit_multi_reg_push
7239 else
7240 insn = emit_insn
7244 }
7247 {
7248 /* If we have to push any regs, then we must push lr as well, or
7249 we won't get a proper return. */
7253 }
7255 /* For now the integer regs are still pushed in output_arm_epilogue (). */
7258 {
7260 {
7263 {
7269 }
7270 }
7271 else
7272 {
7276 {
7278 {
7280 {
7284 }
7285 }
7286 else
7287 {
7289 {
7292 }
7294 }
7295 }
7298 {
7301 }
7302 }
7303 }
7306 {
7310 insn));
7312 }
7315 {
7317 amount));
7321 }
7323 /* If we are profiling, make sure no instructions are scheduled before
7324 the call to mcount. Similarly if the user has requested no
7325 scheduling in the prolog. */
7328 }
7329 \f
7330 /* If CODE is 'd', then the X is a condition operand and the instruction
7331 should only be executed if the condition is true.
7332 if CODE is 'D', then the X is a condition operand and the instruction
7333 should only be executed if the condition is false: however, if the mode
7334 of the comparison is CCFPEmode, then always execute the instruction -- we
7335 do this because in these circumstances !GE does not necessarily imply LT;
7336 in these cases the instruction pattern will take care to make sure that
7337 an instruction containing %d will follow, thereby undoing the effects of
7338 doing this instruction unconditionally.
7339 If CODE is 'N' then X is a floating point operand that must be negated
7340 before output.
7341 If CODE is 'B' then output a bitwise inverted value of X (a const int).
7342 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
7344 void
7347 rtx x;
7349 {
7351 {
7370 {
7371 REAL_VALUE_TYPE r;
7375 }
7380 {
7381 HOST_WIDE_INT val;
7384 }
7385 else
7386 {
7389 }
7401 {
7402 HOST_WIDE_INT val;
7406 {
7410 else
7411 {
7414 }
7415 }
7416 }
7419 /* An explanation of the 'Q', 'R' and 'H' register operands:
7421 In a pair of registers containing a DI or DF value the 'Q'
7422 operand returns the register number of the register containing
7423 the least signficant part of the value. The 'R' operand returns
7424 the register number of the register containing the most
7425 significant part of the value.
7427 The 'H' operand returns the higher of the two register numbers.
7428 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
7429 same as the 'Q' operand, since the most signficant part of the
7430 value is held in the lower number register. The reverse is true
7431 on systems where WORDS_BIG_ENDIAN is false.
7433 The purpose of these operands is to distinguish between cases
7434 where the endian-ness of the values is important (for example
7435 when they are added together), and cases where the endian-ness
7436 is irrelevant, but the order of register operations is important.
7437 For example when loading a value from memory into a register
7438 pair, the endian-ness does not matter. Provided that the value
7439 from the lower memory address is put into the lower numbered
7440 register, and the value from the higher address is put into the
7441 higher numbered register, the load will work regardless of whether
7442 the value being loaded is big-wordian or little-wordian. The
7443 order of the two register loads can matter however, if the address
7444 of the memory location is actually held in one of the registers
7445 being overwritten by the load. */
7482 stream);
7483 else
7494 stream);
7495 else
7506 {
7509 }
7514 else
7515 {
7518 }
7519 }
7520 }
7521 \f
7522 /* A finite state machine takes care of noticing whether or not instructions
7523 can be conditionally executed, and thus decrease execution time and code
7524 size by deleting branch instructions. The fsm is controlled by
7525 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
7527 /* The state of the fsm controlling condition codes are:
7528 0: normal, do nothing special
7529 1: make ASM_OUTPUT_OPCODE not output this instruction
7530 2: make ASM_OUTPUT_OPCODE not output this instruction
7531 3: make instructions conditional
7532 4: make instructions conditional
7534 State transitions (state->state by whom under condition):
7535 0 -> 1 final_prescan_insn if the `target' is a label
7536 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
7537 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
7538 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
7539 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
7540 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
7541 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
7542 (the target insn is arm_target_insn).
7544 If the jump clobbers the conditions then we use states 2 and 4.
7546 A similar thing can be done with conditional return insns.
7548 XXX In case the `target' is an unconditional branch, this conditionalising
7549 of the instructions always reduces code size, but not always execution
7550 time. But then, I want to reduce the code size to somewhere near what
7551 /bin/cc produces. */
7553 /* Returns the index of the ARM condition code string in
7554 `arm_condition_codes'. COMPARISON should be an rtx like
7555 `(eq (...) (...))'. */
7557 static enum arm_cond_code
7559 rtx comparison;
7560 {
7570 {
7582 dominance:
7592 {
7598 }
7603 {
7607 }
7611 {
7617 }
7621 {
7633 }
7637 {
7641 }
7645 {
7657 }
7660 }
7663 }
7666 void
7668 rtx insn;
7669 {
7670 /* BODY will hold the body of INSN. */
7673 /* This will be 1 if trying to repeat the trick, and things need to be
7674 reversed if it appears to fail. */
7677 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
7678 taken are clobbered, even if the rtl suggests otherwise. It also
7679 means that we have to grub around within the jump expression to find
7680 out what the conditions are when the jump isn't taken. */
7683 /* If we start with a return insn, we only succeed if we find another one. */
7686 /* START_INSN will hold the insn from where we start looking. This is the
7687 first insn after the following code_label if REVERSE is true. */
7690 /* If in state 4, check if the target branch is reached, in order to
7691 change back to state 0. */
7693 {
7695 {
7698 }
7700 }
7702 /* If in state 3, it is possible to repeat the trick, if this insn is an
7703 unconditional branch to a label, and immediately following this branch
7704 is the previous target label which is only used once, and the label this
7705 branch jumps to is not too far off. */
7707 {
7709 {
7712 {
7713 /* XXX Isn't this always a barrier? */
7715 }
7720 else
7722 }
7724 {
7731 {
7734 }
7735 else
7737 }
7738 else
7740 }
7747 /* This jump might be paralleled with a clobber of the condition codes
7748 the jump should always come first */
7752 #if 0
7753 /* If this is a conditional return then we don't want to know */
7759 #endif
7764 {
7767 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
7772 {
7773 /* The code below is wrong for these, and I haven't time to
7774 fix it now. So we just do the safe thing and return. This
7775 whole function needs re-writing anyway. */
7778 }
7780 /* Register the insn jumped to. */
7782 {
7785 }
7789 {
7792 }
7796 {
7799 }
7800 else
7803 /* See how many insns this branch skips, and what kind of insns. If all
7804 insns are okay, and the label or unconditional branch to the same
7805 label is not too far away, succeed. */
7808 {
7809 rtx scanbody;
7816 {
7818 /* Succeed if it is the target label, otherwise fail since
7819 control falls in from somewhere else. */
7821 {
7823 {
7826 }
7827 else
7830 }
7831 else
7836 /* Succeed if the following insn is the target label.
7837 Otherwise fail.
7838 If return insns are used then the last insn in a function
7839 will be a barrier. */
7842 {
7844 {
7847 }
7848 else
7851 }
7852 else
7857 /* If using 32-bit addresses the cc is not preserved over
7858 calls. */
7860 {
7861 /* Succeed if the following insn is the target label,
7862 or if the following two insns are a barrier and
7863 the target label. */
7870 {
7872 {
7875 }
7876 else
7879 }
7880 else
7882 }
7886 /* If this is an unconditional branch to the same label, succeed.
7887 If it is to another label, do nothing. If it is conditional,
7888 fail. */
7889 /* XXX Probably, the tests for SET and the PC are unnecessary. */
7894 {
7897 {
7900 }
7903 }
7904 /* Fail if a conditional return is undesirable (eg on a
7905 StrongARM), but still allow this if optimizing for size. */
7912 {
7915 }
7917 {
7919 {
7925 }
7926 }
7930 /* Instructions using or affecting the condition codes make it
7931 fail. */
7941 }
7942 }
7944 {
7948 {
7950 {
7955 }
7957 {
7958 /* Oh, dear! we ran off the end.. give up */
7963 }
7965 }
7966 else
7969 {
7972 arm_current_cc =
7979 }
7980 else
7981 {
7982 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
7983 what it was. */
7987 }
7991 }
7993 /* Restore recog_data (getting the attributes of other insns can
7994 destroy this array, but final.c assumes that it remains intact
7995 across this call; since the insn has been recognized already we
7996 call recog direct). */
7998 }
7999 }
8001 int
8004 {
8006 {
8014 }
8025 }
8027 /* Handle a special case when computing the offset
8028 of an argument from the frame pointer. */
8029 int
8032 rtx addr;
8033 {
8034 rtx insn;
8036 /* We are only interested if dbxout_parms() failed to compute the offset. */
8040 /* We can only cope with the case where the address is held in a register. */
8044 /* If we are using the frame pointer to point at the argument, then
8045 an offset of 0 is correct. */
8049 /* If we are using the stack pointer to point at the
8050 argument, then an offset of 0 is correct. */
8055 /* Oh dear. The argument is pointed to by a register rather
8056 than being held in a register, or being stored at a known
8057 offset from the frame pointer. Since GDB only understands
8058 those two kinds of argument we must translate the address
8059 held in the register into an offset from the frame pointer.
8060 We do this by searching through the insns for the function
8061 looking to see where this register gets its value. If the
8062 register is initialised from the frame pointer plus an offset
8063 then we are in luck and we can continue, otherwise we give up.
8065 This code is exercised by producing debugging information
8066 for a function with arguments like this:
8068 double func (double a, double b, int c, double d) {return d;}
8070 Without this code the stab for parameter 'd' will be set to
8071 an offset of 0 from the frame pointer, rather than 8. */
8073 /* The if() statement says:
8075 If the insn is a normal instruction
8076 and if the insn is setting the value in a register
8077 and if the register being set is the register holding the address of the argument
8078 and if the address is computing by an addition
8079 that involves adding to a register
8080 which is the frame pointer
8081 a constant integer
8083 then... */
8086 {
8094 )
8095 {
8099 }
8100 }
8103 {
8107 }
8110 }
8112 \f
8113 /* Recursively search through all of the blocks in a function
8114 checking to see if any of the variables created in that
8115 function match the RTX called 'orig'. If they do then
8116 replace them with the RTX called 'new'. */
8118 static void
8120 tree block;
8121 rtx orig;
8123 {
8125 {
8126 tree sym;
8132 {
8138 )
8142 }
8145 }
8146 }
8148 /* Return the number (counting from 0) of the least significant set
8149 bit in MASK. */
8150 #ifdef __GNUC__
8151 inline
8152 #endif
8153 static int
8156 {
8165 }
8167 /* Generate code to return from a thumb function.
8168 If 'reg_containing_return_addr' is -1, then the return address is
8169 actually on the stack, at the stack pointer. */
8170 static void
8174 rtx eh_ofs;
8175 {
8185 /* Compute the registers we need to pop. */
8189 /* There is an assumption here, that if eh_ofs is not NULL, the
8190 normal return address will have been pushed. */
8192 {
8193 /* When we are generating a return for __builtin_eh_return,
8194 reg_containing_return_addr must specify the return regno. */
8200 }
8203 {
8204 /* Restore the (ARM) frame pointer and stack pointer. */
8207 }
8209 /* If there is nothing to pop then just emit the BX instruction and
8210 return. */
8212 {
8218 }
8219 /* Otherwise if we are not supporting interworking and we have not created
8220 a backtrace structure and the function was not entered in ARM mode then
8221 just pop the return address straight into the PC. */
8223 && ! TARGET_BACKTRACE
8225 {
8227 {
8231 }
8232 else
8236 }
8238 /* Find out how many of the (return) argument registers we can corrupt. */
8241 /* If returning via __builtin_eh_return, the bottom three registers
8242 all contain information needed for the return. */
8245 else
8246 {
8247 #ifdef RTX_CODE
8248 /* If we can deduce the registers used from the function's
8249 return value. This is more reliable that examining
8250 regs_ever_live[] because that will be set if the register is
8251 ever used in the function, not just if the register is used
8252 to hold a return value. */
8256 else
8257 #endif
8263 {
8264 /* In a void function we can use any argument register.
8265 In a function that returns a structure on the stack
8266 we can use the second and third argument registers. */
8268 regs_available_for_popping =
8272 else
8273 regs_available_for_popping =
8276 }
8278 regs_available_for_popping =
8282 regs_available_for_popping =
8284 }
8286 /* Match registers to be popped with registers into which we pop them. */
8294 /* If we have any popping registers left over, remove them. */
8298 /* Otherwise if we need another popping register we can use
8299 the fourth argument register. */
8301 {
8302 /* If we have not found any free argument registers and
8303 reg a4 contains the return address, we must move it. */
8306 {
8309 }
8311 {
8312 /* Register a4 is being used to hold part of the return value,
8313 but we have dire need of a free, low register. */
8317 }
8320 {
8321 /* The fourth argument register is available. */
8325 }
8326 }
8328 /* Pop as many registers as we can. */
8331 /* Process the registers we popped. */
8333 {
8334 /* The return address was popped into the lowest numbered register. */
8337 reg_containing_return_addr =
8340 /* Remove this register for the mask of available registers, so that
8341 the return address will not be corrupted by futher pops. */
8343 }
8345 /* If we popped other registers then handle them here. */
8347 {
8350 /* Work out which register currently contains the frame pointer. */
8353 /* Move it into the correct place. */
8357 /* (Temporarily) remove it from the mask of popped registers. */
8362 {
8365 /* We popped the stack pointer as well,
8366 find the register that contains it. */
8369 /* Move it into the stack register. */
8372 /* At this point we have popped all necessary registers, so
8373 do not worry about restoring regs_available_for_popping
8374 to its correct value:
8376 assert (pops_needed == 0)
8377 assert (regs_available_for_popping == (1 << frame_pointer))
8378 assert (regs_to_pop == (1 << STACK_POINTER)) */
8379 }
8380 else
8381 {
8382 /* Since we have just move the popped value into the frame
8383 pointer, the popping register is available for reuse, and
8384 we know that we still have the stack pointer left to pop. */
8386 }
8387 }
8389 /* If we still have registers left on the stack, but we no longer have
8390 any registers into which we can pop them, then we must move the return
8391 address into the link register and make available the register that
8392 contained it. */
8394 {
8398 reg_containing_return_addr);
8401 }
8403 /* If we have registers left on the stack then pop some more.
8404 We know that at most we will want to pop FP and SP. */
8406 {
8412 /* We have popped either FP or SP.
8413 Move whichever one it is into the correct register. */
8422 }
8424 /* If we still have not popped everything then we must have only
8425 had one register available to us and we are now popping the SP. */
8427 {
8435 /*
8436 assert (regs_to_pop == (1 << STACK_POINTER))
8437 assert (pops_needed == 1)
8438 */
8439 }
8441 /* If necessary restore the a4 register. */
8443 {
8445 {
8448 }
8451 }
8456 /* Return to caller. */
8458 }
8460 /* Emit code to push or pop registers to or from the stack. */
8461 static void
8466 {
8471 {
8472 /* Special case. Do not generate a POP PC statement here, do it in
8473 thumb_exit() */
8476 }
8480 /* Look at the low registers first. */
8482 {
8484 {
8489 }
8490 }
8493 {
8494 /* Catch pushing the LR. */
8499 }
8501 {
8502 /* Catch popping the PC. */
8504 {
8505 /* The PC is never poped directly, instead
8506 it is popped into r3 and then BX is used. */
8512 }
8513 else
8514 {
8519 }
8520 }
8523 }
8524 \f
8525 void
8527 rtx insn;
8528 {
8533 }
8535 int
8538 {
8550 }
8552 /* Returns non-zero if the current function contains,
8553 or might contain a far jump. */
8554 int
8556 {
8557 rtx insn;
8559 /* This test is only important for leaf functions. */
8560 /* assert (! leaf_function_p ()); */
8562 /* If we have already decided that far jumps may be used,
8563 do not bother checking again, and always return true even if
8564 it turns out that they are not being used. Once we have made
8565 the decision that far jumps are present (and that hence the link
8566 register will be pushed onto the stack) we cannot go back on it. */
8570 /* If this function is not being called from the prologue/epilogue
8571 generation code then it must be being called from the
8572 INITIAL_ELIMINATION_OFFSET macro. */
8574 {
8575 /* In this case we know that we are being asked about the elimination
8576 of the arg pointer register. If that register is not being used,
8577 then there are no arguments on the stack, and we do not have to
8578 worry that a far jump might force the prologue to push the link
8579 register, changing the stack offsets. In this case we can just
8580 return false, since the presence of far jumps in the function will
8581 not affect stack offsets.
8583 If the arg pointer is live (or if it was live, but has now been
8584 eliminated and so set to dead) then we do have to test to see if
8585 the function might contain a far jump. This test can lead to some
8586 false negatives, since before reload is completed, then length of
8587 branch instructions is not known, so gcc defaults to returning their
8588 longest length, which in turn sets the far jump attribute to true.
8590 A false negative will not result in bad code being generated, but it
8591 will result in a needless push and pop of the link register. We
8592 hope that this does not occur too often. */
8597 }
8599 /* Check to see if the function contains a branch
8600 insn with the far jump attribute set. */
8602 {
8604 /* Ignore tablejump patterns. */
8608 )
8609 {
8610 /* Record the fact that we have decied that
8611 the function does use far jumps. */
8614 }
8615 }
8618 }
8620 /* Return non-zero if FUNC must be entered in ARM mode. */
8621 int
8623 tree func;
8624 {
8628 /* Ignore the problem about functions whoes address is taken. */
8632 #ifdef ARM_PE
8634 #else
8636 #endif
8637 }
8639 /* The bits which aren't usefully expanded as rtl. */
8642 {
8659 {
8662 high_regs_pushed ++;
8663 }
8665 /* The prolog may have pushed some high registers to use as
8666 work registers. eg the testuite file:
8667 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
8668 compiles to produce:
8669 push {r4, r5, r6, r7, lr}
8670 mov r7, r9
8671 mov r6, r8
8672 push {r6, r7}
8673 as part of the prolog. We have to undo that pushing here. */
8676 {
8682 #ifdef RTX_CODE
8683 /* If we can deduce the registers used from the function's return value.
8684 This is more reliable that examining regs_ever_live[] because that
8685 will be set if the register is ever used in the function, not just if
8686 the register is used to hold a return value. */
8690 else
8691 #endif
8696 /* Unless we are returning a type of size > 12 register r3 is
8697 available. */
8702 /* Oh dear! We have no low registers into which we can pop
8703 high registers! */
8712 {
8713 /* Find lo register(s) into which the high register(s) can
8714 be popped. */
8716 {
8718 high_regs_pushed--;
8721 }
8725 /* Pop the values into the low register(s). */
8728 /* Move the value(s) into the high registers. */
8730 {
8732 {
8734 regno);
8739 && ! (TARGET_SINGLE_PIC_BASE
8742 }
8743 }
8744 }
8745 }
8753 {
8754 /* The stack backtrace structure creation code had to
8755 push R7 in order to get a work register, so we pop
8756 it now. */
8758 }
8761 {
8767 /* Either no argument registers were pushed or a backtrace
8768 structure was created which includes an adjusted stack
8769 pointer, so just pop everything. */
8775 /* We have either just popped the return address into the
8776 PC or it is was kept in LR for the entire function or
8777 it is still on the stack because we do not want to
8778 return by doing a pop {pc}. */
8781 (had_to_push_lr
8784 }
8785 else
8786 {
8787 /* Pop everything but the return address. */
8794 /* Get the return address into a temporary register. */
8797 /* Remove the argument registers that were pushed onto the stack. */
8800 current_function_pretend_args_size);
8804 else
8807 }
8810 }
8812 /* Functions to save and restore machine-specific function data. */
8814 static void
8817 {
8822 }
8824 static void
8827 {
8830 }
8832 /* Return an RTX indicating where the return address to the
8833 calling function can be found. */
8834 rtx
8837 rtx frame ATTRIBUTE_UNUSED;
8838 {
8839 rtx reg;
8847 {
8848 rtx init;
8850 /* No rtx yet. Invent one, and initialize it for r14 (lr) in
8851 the prologue. */
8858 else
8863 /* Emit the insn to the prologue with the other argument copies. */
8867 }
8870 }
8872 /* Do anything needed before RTL is emitted for each function. */
8873 void
8875 {
8876 /* Arrange to initialize and mark the machine per-function status. */
8879 }
8881 /* Generate the rest of a function's prologue. */
8882 void
8884 {
8888 /* Naked functions don't have prologues. */
8896 {
8902 else
8903 {
8905 rtx reg;
8907 /* The stack decrement is too big for an immediate value in a single
8908 insn. In theory we could issue multiple subtracts, but after
8909 three of them it becomes more space efficient to place the full
8910 value in the constant pool and load into a register. (Also the
8911 ARM debugger really likes to see only one stack decrement per
8912 function). So instead we look for a scratch register into which
8913 we can load the decrement, and then we subtract this from the
8914 stack pointer. Unfortunately on the thumb the only available
8915 scratch registers are the argument registers, and we cannot use
8916 these as they may hold arguments to the function. Instead we
8917 attempt to locate a call preserved register which is used by this
8918 function. If we can find one, then we know that it will have
8919 been pushed at the start of the prologue and so we can corrupt
8920 it now. */
8925 && ! (frame_pointer_needed
8930 {
8933 /* Choose an arbitary, non-argument low register. */
8936 /* Save it by copying it into a high, scratch register. */
8939 /* Decrement the stack. */
8942 reg));
8944 /* Restore the low register's original value. */
8947 /* Emit a USE of the restored scratch register, so that flow
8948 analysis will not consider the restore redundant. The
8949 register won't be used again in this function and isn't
8950 restored by the epilogue. */
8952 }
8953 else
8954 {
8959 reg));
8960 }
8961 }
8962 }
8966 }
8968 void
8970 {
8974 /* Naked functions don't have epilogues. */
8981 {
8987 else
8988 {
8989 /* r3 is always free in the epilogue. */
8994 }
8995 }
8997 /* Emit a USE (stack_pointer_rtx), so that
8998 the stack adjustment will not be deleted. */
9003 }
9005 void
9008 {
9018 {
9027 /* Generate code sequence to switch us into Thumb mode. */
9028 /* The .code 32 directive has already been emitted by
9029 ASM_DECLARE_FUNCTION_NAME. */
9033 /* Generate a label, so that the debugger will notice the
9034 change in instruction sets. This label is also used by
9035 the assembler to bypass the ARM code when this function
9036 is called from a Thumb encoded function elsewhere in the
9037 same file. Hence the definition of STUB_NAME here must
9038 agree with the definition in gas/config/tc-arm.c */
9043 #ifdef ARM_PE
9046 #endif
9050 }
9056 {
9058 {
9067 regno ++)
9072 }
9073 else
9076 current_function_pretend_args_size);
9077 }
9088 {
9093 /* We have been asked to create a stack backtrace structure.
9094 The code looks like this:
9096 0 .align 2
9097 0 func:
9098 0 sub SP, #16 Reserve space for 4 registers.
9099 2 push {R7} Get a work register.
9100 4 add R7, SP, #20 Get the stack pointer before the push.
9101 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
9102 8 mov R7, PC Get hold of the start of this code plus 12.
9103 10 str R7, [SP, #16] Store it.
9104 12 mov R7, FP Get hold of the current frame pointer.
9105 14 str R7, [SP, #4] Store it.
9106 16 mov R7, LR Get hold of the current return address.
9107 18 str R7, [SP, #12] Store it.
9108 20 add R7, SP, #16 Point at the start of the backtrace structure.
9109 22 mov FP, R7 Put this value into the frame pointer. */
9112 {
9113 /* See if the a4 register is free. */
9119 }
9122 {
9123 /* Select a register from the list that will be pushed to
9124 use as our work register. */
9128 }
9130 asm_fprintf
9147 /* Make sure that the instruction fetching the PC is in the right place
9148 to calculate "start of backtrace creation code + 12". */
9150 {
9155 ARM_HARD_FRAME_POINTER_REGNUM);
9157 offset);
9158 }
9159 else
9160 {
9162 ARM_HARD_FRAME_POINTER_REGNUM);
9164 offset);
9168 }
9177 }
9182 {
9185 high_regs_pushed ++;
9186 }
9189 {
9195 {
9197 && ! (TARGET_SINGLE_PIC_BASE
9200 }
9205 {
9206 /* Desperation time -- this probably will never happen. */
9211 }
9214 {
9216 {
9218 {
9221 high_regs_pushed --;
9225 next_hi_reg--)
9226 {
9229 && ! (TARGET_SINGLE_PIC_BASE
9232 }
9233 else
9234 {
9237 }
9238 }
9239 }
9242 }
9248 }
9249 }
9251 /* Handle the case of a double word load into a low register from
9252 a computed memory address. The computed address may involve a
9253 register which is overwritten by the load. */
9258 {
9259 rtx addr;
9260 rtx base;
9261 rtx offset;
9262 rtx arg1;
9263 rtx arg2;
9269 {
9272 }
9274 /* Get the memory address. */
9277 /* Work out how the memory address is computed. */
9279 {
9285 {
9288 }
9289 else
9290 {
9293 }
9297 /* Compute <address> + 4 for the high order load. */
9311 else
9317 /* Catch the case of <address> = <reg> + <reg> */
9319 {
9324 /* Add the base and offset registers together into the
9325 higher destination register. */
9329 /* Load the lower destination register from the address in
9330 the higher destination register. */
9334 /* Load the higher destination register from its own address
9335 plus 4. */
9338 }
9339 else
9340 {
9341 /* Compute <address> + 4 for the high order load. */
9345 /* If the computed address is held in the low order register
9346 then load the high order register first, otherwise always
9347 load the low order register first. */
9349 {
9352 }
9353 else
9354 {
9357 }
9358 }
9362 /* With no registers to worry about we can just load the value
9363 directly. */
9375 }
9378 }
9385 {
9386 rtx tmp;
9389 {
9392 {
9396 }
9403 {
9407 }
9409 {
9413 }
9415 {
9419 }
9427 }
9430 }
9432 /* Routines for generating rtl */
9434 void
9437 {
9444 {
9447 }
9450 {
9453 }
9456 {
9462 }
9465 {
9470 reg));
9473 }
9476 {
9481 reg));
9482 }
9483 }
9485 int
9487 rtx op;
9489 {
9493 }
9497 rtx x;
9499 {
9501 {
9504 };
9508 {
9521 }
9524 }
9526 /* Handle storing a half-word to memory during reload. */
9527 void
9530 {
9532 }
9534 /* Handle storing a half-word to memory during reload. */
9535 void
9538 {
9540 }
9542 /* Return the length of a function name prefix
9543 that starts with the character 'c'. */
9544 static int
9546 {
9548 {
9549 ARM_NAME_ENCODING_LENGTHS
9551 }
9552 }
9554 /* Return a pointer to a function's name with any
9555 and all prefix encodings stripped from it. */
9558 {
9565 }
9567 #ifdef AOF_ASSEMBLER
9568 /* Special functions only needed when producing AOF syntax assembler. */
9571 struct pic_chain
9572 {
9575 };
9579 rtx
9581 rtx x;
9582 {
9587 {
9588 /* We mark this here and not in arm_add_gc_roots() to avoid
9589 polluting even more code with ifdefs, and because it never
9590 contains anything useful until we assign to it here. */
9592 /* This needs to persist throughout the compilation. */
9596 }
9607 }
9609 void
9612 {
9619 PIC_OFFSET_TABLE_REGNUM,
9620 PIC_OFFSET_TABLE_REGNUM);
9624 {
9628 }
9629 }
9635 {
9638 arm_text_section_count++);
9642 }
9648 {
9652 }
9654 /* The AOF assembler is religiously strict about declarations of
9655 imported and exported symbols, so that it is impossible to declare
9656 a function as imported near the beginning of the file, and then to
9657 export it later on. It is, however, possible to delay the decision
9658 until all the functions in the file have been compiled. To get
9659 around this, we maintain a list of the imports and exports, and
9660 delete from it any that are subsequently defined. At the end of
9661 compilation we spit the remainder of the list out before the END
9662 directive. */
9664 struct import
9665 {
9668 };
9672 void
9675 {
9686 }
9688 void
9691 {
9695 {
9697 {
9700 }
9701 }
9702 }
9706 void
9709 {
9710 /* The AOF assembler needs this to cause the startup code to be extracted
9711 from the library. Brining in __main causes the whole thing to work
9712 automagically. */
9714 {
9718 }
9720 /* Now dump the remaining imports. */
9722 {
9727 }
9728 }