1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
124 #include "hash-set.h"
126 #include "machmode.h"
128 #include "function.h"
131 #include "dominance.h"
134 #include "basic-block.h"
139 #include "rtl-error.h"
142 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
143 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
145 static int bb_reload_num
;
147 /* The current insn being processed and corresponding its single set
148 (NULL otherwise), its data (basic block, the insn data, the insn
149 static data, and the mode of each operand). */
150 static rtx_insn
*curr_insn
;
151 static rtx curr_insn_set
;
152 static basic_block curr_bb
;
153 static lra_insn_recog_data_t curr_id
;
154 static struct lra_static_insn_data
*curr_static_id
;
155 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
159 /* Start numbers for new registers and insns at the current constraints
161 static int new_regno_start
;
162 static int new_insn_uid_start
;
164 /* If LOC is nonnull, strip any outer subreg from it. */
166 strip_subreg (rtx
*loc
)
168 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
171 /* Return hard regno of REGNO or if it is was not assigned to a hard
172 register, use a hard register from its allocno class. */
174 get_try_hard_regno (int regno
)
177 enum reg_class rclass
;
179 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
180 hard_regno
= lra_get_regno_hard_regno (regno
);
183 rclass
= lra_get_allocno_class (regno
);
184 if (rclass
== NO_REGS
)
186 return ira_class_hard_regs
[rclass
][0];
189 /* Return final hard regno (plus offset) which will be after
190 elimination. We do this for matching constraints because the final
191 hard regno could have a different class. */
193 get_final_hard_regno (int hard_regno
, int offset
)
197 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
198 return hard_regno
+ offset
;
201 /* Return hard regno of X after removing subreg and making
202 elimination. If X is not a register or subreg of register, return
203 -1. For pseudo use its assignment. */
205 get_hard_regno (rtx x
)
208 int offset
, hard_regno
;
211 if (GET_CODE (x
) == SUBREG
)
212 reg
= SUBREG_REG (x
);
215 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
216 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
220 if (GET_CODE (x
) == SUBREG
)
221 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
222 SUBREG_BYTE (x
), GET_MODE (x
));
223 return get_final_hard_regno (hard_regno
, offset
);
226 /* If REGNO is a hard register or has been allocated a hard register,
227 return the class of that register. If REGNO is a reload pseudo
228 created by the current constraints pass, return its allocno class.
229 Return NO_REGS otherwise. */
230 static enum reg_class
231 get_reg_class (int regno
)
235 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
236 hard_regno
= lra_get_regno_hard_regno (regno
);
239 hard_regno
= get_final_hard_regno (hard_regno
, 0);
240 return REGNO_REG_CLASS (hard_regno
);
242 if (regno
>= new_regno_start
)
243 return lra_get_allocno_class (regno
);
247 /* Return true if REG satisfies (or will satisfy) reg class constraint
248 CL. Use elimination first if REG is a hard register. If REG is a
249 reload pseudo created by this constraints pass, assume that it will
250 be allocated a hard register from its allocno class, but allow that
251 class to be narrowed to CL if it is currently a superset of CL.
253 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
254 REGNO (reg), or NO_REGS if no change in its class was needed. */
256 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
258 enum reg_class rclass
, common_class
;
259 machine_mode reg_mode
;
260 int class_size
, hard_regno
, nregs
, i
, j
;
261 int regno
= REGNO (reg
);
263 if (new_class
!= NULL
)
264 *new_class
= NO_REGS
;
265 if (regno
< FIRST_PSEUDO_REGISTER
)
268 rtx
*final_loc
= &final_reg
;
270 lra_eliminate_reg_if_possible (final_loc
);
271 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
273 reg_mode
= GET_MODE (reg
);
274 rclass
= get_reg_class (regno
);
275 if (regno
< new_regno_start
276 /* Do not allow the constraints for reload instructions to
277 influence the classes of new pseudos. These reloads are
278 typically moves that have many alternatives, and restricting
279 reload pseudos for one alternative may lead to situations
280 where other reload pseudos are no longer allocatable. */
281 || (INSN_UID (curr_insn
) >= new_insn_uid_start
282 && curr_insn_set
!= NULL
283 && ((OBJECT_P (SET_SRC (curr_insn_set
))
284 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
285 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
286 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
287 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
288 /* When we don't know what class will be used finally for reload
289 pseudos, we use ALL_REGS. */
290 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
291 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
292 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
293 lra_no_alloc_regs
)));
296 common_class
= ira_reg_class_subset
[rclass
][cl
];
297 if (new_class
!= NULL
)
298 *new_class
= common_class
;
299 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
302 /* Check that there are enough allocatable regs. */
303 class_size
= ira_class_hard_regs_num
[common_class
];
304 for (i
= 0; i
< class_size
; i
++)
306 hard_regno
= ira_class_hard_regs
[common_class
][i
];
307 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
310 for (j
= 0; j
< nregs
; j
++)
311 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
312 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
322 /* Return true if REGNO satisfies a memory constraint. */
326 return get_reg_class (regno
) == NO_REGS
;
329 /* Return 1 if ADDR is a valid memory address for mode MODE in address
330 space AS, and check that each pseudo has the proper kind of hard
333 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
334 rtx addr
, addr_space_t as
)
336 #ifdef GO_IF_LEGITIMATE_ADDRESS
337 lra_assert (ADDR_SPACE_GENERIC_P (as
));
338 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
344 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
349 /* Temporarily eliminates registers in an address (for the lifetime of
351 class address_eliminator
{
353 address_eliminator (struct address_info
*ad
);
354 ~address_eliminator ();
357 struct address_info
*m_ad
;
365 address_eliminator::address_eliminator (struct address_info
*ad
)
367 m_base_loc (strip_subreg (ad
->base_term
)),
368 m_base_reg (NULL_RTX
),
369 m_index_loc (strip_subreg (ad
->index_term
)),
370 m_index_reg (NULL_RTX
)
372 if (m_base_loc
!= NULL
)
374 m_base_reg
= *m_base_loc
;
375 lra_eliminate_reg_if_possible (m_base_loc
);
376 if (m_ad
->base_term2
!= NULL
)
377 *m_ad
->base_term2
= *m_ad
->base_term
;
379 if (m_index_loc
!= NULL
)
381 m_index_reg
= *m_index_loc
;
382 lra_eliminate_reg_if_possible (m_index_loc
);
386 address_eliminator::~address_eliminator ()
388 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
390 *m_base_loc
= m_base_reg
;
391 if (m_ad
->base_term2
!= NULL
)
392 *m_ad
->base_term2
= *m_ad
->base_term
;
394 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
395 *m_index_loc
= m_index_reg
;
398 /* Return true if the eliminated form of AD is a legitimate target address. */
400 valid_address_p (struct address_info
*ad
)
402 address_eliminator
eliminator (ad
);
403 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
406 /* Return true if the eliminated form of memory reference OP satisfies
407 extra memory constraint CONSTRAINT. */
409 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
411 struct address_info ad
;
413 decompose_mem_address (&ad
, op
);
414 address_eliminator
eliminator (&ad
);
415 return constraint_satisfied_p (op
, constraint
);
418 /* Return true if the eliminated form of address AD satisfies extra
419 address constraint CONSTRAINT. */
421 satisfies_address_constraint_p (struct address_info
*ad
,
422 enum constraint_num constraint
)
424 address_eliminator
eliminator (ad
);
425 return constraint_satisfied_p (*ad
->outer
, constraint
);
428 /* Return true if the eliminated form of address OP satisfies extra
429 address constraint CONSTRAINT. */
431 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
433 struct address_info ad
;
435 decompose_lea_address (&ad
, &op
);
436 return satisfies_address_constraint_p (&ad
, constraint
);
439 /* Initiate equivalences for LRA. As we keep original equivalences
440 before any elimination, we need to make copies otherwise any change
441 in insns might change the equivalences. */
443 lra_init_equiv (void)
445 ira_expand_reg_equiv ();
446 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
450 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
451 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
452 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
453 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
457 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
459 /* Update equivalence for REGNO. We need to this as the equivalence
460 might contain other pseudos which are changed by their
463 update_equiv (int regno
)
467 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
468 ira_reg_equiv
[regno
].memory
469 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
471 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
472 ira_reg_equiv
[regno
].invariant
473 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
477 /* If we have decided to substitute X with another value, return that
478 value, otherwise return X. */
485 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
486 || ! ira_reg_equiv
[regno
].defined_p
487 || ! ira_reg_equiv
[regno
].profitable_p
488 || lra_get_regno_hard_regno (regno
) >= 0)
490 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
492 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
494 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
499 /* If we have decided to substitute X with the equivalent value,
500 return that value after elimination for INSN, otherwise return
503 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
505 rtx res
= get_equiv (x
);
507 if (x
== res
|| CONSTANT_P (res
))
509 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
510 0, false, false, true);
513 /* Set up curr_operand_mode. */
515 init_curr_operand_mode (void)
517 int nop
= curr_static_id
->n_operands
;
518 for (int i
= 0; i
< nop
; i
++)
520 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
521 if (mode
== VOIDmode
)
523 /* The .md mode for address operands is the mode of the
524 addressed value rather than the mode of the address itself. */
525 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
528 mode
= curr_static_id
->operand
[i
].mode
;
530 curr_operand_mode
[i
] = mode
;
536 /* The page contains code to reuse input reloads. */
538 /* Structure describes input reload of the current insns. */
541 /* Reloaded value. */
543 /* Reload pseudo used. */
547 /* The number of elements in the following array. */
548 static int curr_insn_input_reloads_num
;
549 /* Array containing info about input reloads. It is used to find the
550 same input reload and reuse the reload pseudo in this case. */
551 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
553 /* Initiate data concerning reuse of input reloads for the current
556 init_curr_insn_input_reloads (void)
558 curr_insn_input_reloads_num
= 0;
561 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
562 created input reload pseudo (only if TYPE is not OP_OUT). Don't
563 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
564 wrapped up in SUBREG. The result pseudo is returned through
565 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
566 reused the already created input reload pseudo. Use TITLE to
567 describe new registers for debug purposes. */
569 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
570 enum reg_class rclass
, bool in_subreg_p
,
571 const char *title
, rtx
*result_reg
)
574 enum reg_class new_class
;
579 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
582 /* Prevent reuse value of expression with side effects,
583 e.g. volatile memory. */
584 if (! side_effects_p (original
))
585 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
586 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
587 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
589 rtx reg
= curr_insn_input_reloads
[i
].reg
;
591 /* If input is equal to original and both are VOIDmode,
592 GET_MODE (reg) might be still different from mode.
593 Ensure we don't return *result_reg with wrong mode. */
594 if (GET_MODE (reg
) != mode
)
598 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
600 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
601 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
605 if (lra_dump_file
!= NULL
)
607 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
608 dump_value_slim (lra_dump_file
, original
, 1);
610 if (new_class
!= lra_get_allocno_class (regno
))
611 lra_change_class (regno
, new_class
, ", change to", false);
612 if (lra_dump_file
!= NULL
)
613 fprintf (lra_dump_file
, "\n");
616 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
617 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
618 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
619 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
625 /* The page contains code to extract memory address parts. */
627 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
629 ok_for_index_p_nonstrict (rtx reg
)
631 unsigned regno
= REGNO (reg
);
633 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
636 /* A version of regno_ok_for_base_p for use here, when all pseudos
637 should count as OK. Arguments as for regno_ok_for_base_p. */
639 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
640 enum rtx_code outer_code
, enum rtx_code index_code
)
642 unsigned regno
= REGNO (reg
);
644 if (regno
>= FIRST_PSEUDO_REGISTER
)
646 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
651 /* The page contains major code to choose the current insn alternative
652 and generate reloads for it. */
654 /* Return the offset from REGNO of the least significant register
657 This function is used to tell whether two registers satisfy
658 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
660 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
661 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
663 lra_constraint_offset (int regno
, machine_mode mode
)
665 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
666 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
667 && SCALAR_INT_MODE_P (mode
))
668 return hard_regno_nregs
[regno
][mode
] - 1;
672 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
673 if they are the same hard reg, and has special hacks for
674 auto-increment and auto-decrement. This is specifically intended for
675 process_alt_operands to use in determining whether two operands
676 match. X is the operand whose number is the lower of the two.
678 It is supposed that X is the output operand and Y is the input
679 operand. Y_HARD_REGNO is the final hard regno of register Y or
680 register in subreg Y as we know it now. Otherwise, it is a
683 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
686 RTX_CODE code
= GET_CODE (x
);
691 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
692 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
696 i
= get_hard_regno (x
);
700 if ((j
= y_hard_regno
) < 0)
703 i
+= lra_constraint_offset (i
, GET_MODE (x
));
704 j
+= lra_constraint_offset (j
, GET_MODE (y
));
709 /* If two operands must match, because they are really a single
710 operand of an assembler insn, then two post-increments are invalid
711 because the assembler insn would increment only once. On the
712 other hand, a post-increment matches ordinary indexing if the
713 post-increment is the output operand. */
714 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
715 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
717 /* Two pre-increments are invalid because the assembler insn would
718 increment only once. On the other hand, a pre-increment matches
719 ordinary indexing if the pre-increment is the input operand. */
720 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
721 || GET_CODE (y
) == PRE_MODIFY
)
722 return operands_match_p (x
, XEXP (y
, 0), -1);
726 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
727 && x
== SUBREG_REG (y
))
729 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
730 && SUBREG_REG (x
) == y
)
733 /* Now we have disposed of all the cases in which different rtx
735 if (code
!= GET_CODE (y
))
738 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
739 if (GET_MODE (x
) != GET_MODE (y
))
748 return LABEL_REF_LABEL (x
) == LABEL_REF_LABEL (y
);
750 return XSTR (x
, 0) == XSTR (y
, 0);
756 /* Compare the elements. If any pair of corresponding elements fail
757 to match, return false for the whole things. */
759 fmt
= GET_RTX_FORMAT (code
);
760 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
766 if (XWINT (x
, i
) != XWINT (y
, i
))
771 if (XINT (x
, i
) != XINT (y
, i
))
776 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
785 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
787 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
789 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
795 /* It is believed that rtx's at this level will never
796 contain anything but integers and other rtx's, except for
797 within LABEL_REFs and SYMBOL_REFs. */
805 /* True if X is a constant that can be forced into the constant pool.
806 MODE is the mode of the operand, or VOIDmode if not known. */
807 #define CONST_POOL_OK_P(MODE, X) \
808 ((MODE) != VOIDmode \
810 && GET_CODE (X) != HIGH \
811 && !targetm.cannot_force_const_mem (MODE, X))
813 /* True if C is a non-empty register class that has too few registers
814 to be safely used as a reload target class. */
815 #define SMALL_REGISTER_CLASS_P(C) \
816 (ira_class_hard_regs_num [(C)] == 1 \
817 || (ira_class_hard_regs_num [(C)] >= 1 \
818 && targetm.class_likely_spilled_p (C)))
820 /* If REG is a reload pseudo, try to make its class satisfying CL. */
822 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
824 enum reg_class rclass
;
826 /* Do not make more accurate class from reloads generated. They are
827 mostly moves with a lot of constraints. Making more accurate
828 class may results in very narrow class and impossibility of find
829 registers for several reloads of one insn. */
830 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
832 if (GET_CODE (reg
) == SUBREG
)
833 reg
= SUBREG_REG (reg
);
834 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
836 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
837 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
840 /* Generate reloads for matching OUT and INS (array of input operand
841 numbers with end marker -1) with reg class GOAL_CLASS. Add input
842 and output reloads correspondingly to the lists *BEFORE and *AFTER.
843 OUT might be negative. In this case we generate input reloads for
844 matched input operands INS. */
846 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
847 rtx_insn
**before
, rtx_insn
**after
)
850 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
851 machine_mode inmode
, outmode
;
852 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
853 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
855 inmode
= curr_operand_mode
[ins
[0]];
856 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
857 push_to_sequence (*before
);
858 if (inmode
!= outmode
)
860 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
863 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
865 if (SCALAR_INT_MODE_P (inmode
))
866 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
868 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
869 LRA_SUBREG_P (new_out_reg
) = 1;
870 /* If the input reg is dying here, we can use the same hard
871 register for REG and IN_RTX. We do it only for original
872 pseudos as reload pseudos can die although original
873 pseudos still live where reload pseudos dies. */
874 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
875 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
876 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
881 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
883 if (SCALAR_INT_MODE_P (outmode
))
884 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
886 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
887 /* NEW_IN_REG is non-paradoxical subreg. We don't want
888 NEW_OUT_REG living above. We add clobber clause for
889 this. This is just a temporary clobber. We can remove
890 it at the end of LRA work. */
891 clobber
= emit_clobber (new_out_reg
);
892 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
893 LRA_SUBREG_P (new_in_reg
) = 1;
894 if (GET_CODE (in_rtx
) == SUBREG
)
896 rtx subreg_reg
= SUBREG_REG (in_rtx
);
898 /* If SUBREG_REG is dying here and sub-registers IN_RTX
899 and NEW_IN_REG are similar, we can use the same hard
900 register for REG and SUBREG_REG. */
901 if (REG_P (subreg_reg
)
902 && (int) REGNO (subreg_reg
) < lra_new_regno_start
903 && GET_MODE (subreg_reg
) == outmode
904 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
905 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
906 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
912 /* Pseudos have values -- see comments for lra_reg_info.
913 Different pseudos with the same value do not conflict even if
914 they live in the same place. When we create a pseudo we
915 assign value of original pseudo (if any) from which we
916 created the new pseudo. If we create the pseudo from the
917 input pseudo, the new pseudo will no conflict with the input
918 pseudo which is wrong when the input pseudo lives after the
919 insn and as the new pseudo value is changed by the insn
920 output. Therefore we create the new pseudo from the output.
922 We cannot reuse the current output register because we might
923 have a situation like "a <- a op b", where the constraints
924 force the second input operand ("b") to match the output
925 operand ("a"). "b" must then be copied into a new register
926 so that it doesn't clobber the current value of "a". */
928 new_in_reg
= new_out_reg
929 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
932 /* In operand can be got from transformations before processing insn
933 constraints. One example of such transformations is subreg
934 reloading (see function simplify_operand_subreg). The new
935 pseudos created by the transformations might have inaccurate
936 class (ALL_REGS) and we should make their classes more
938 narrow_reload_pseudo_class (in_rtx
, goal_class
);
939 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
940 *before
= get_insns ();
942 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
945 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
946 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
947 *curr_id
->operand_loc
[in
] = new_in_reg
;
949 lra_update_dups (curr_id
, ins
);
952 /* See a comment for the input operand above. */
953 narrow_reload_pseudo_class (out_rtx
, goal_class
);
954 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
957 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
959 *after
= get_insns ();
962 *curr_id
->operand_loc
[out
] = new_out_reg
;
963 lra_update_dup (curr_id
, out
);
966 /* Return register class which is union of all reg classes in insn
967 constraint alternative string starting with P. */
968 static enum reg_class
969 reg_class_from_constraints (const char *p
)
972 enum reg_class op_class
= NO_REGS
;
975 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
982 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
986 enum constraint_num cn
= lookup_constraint (p
);
987 enum reg_class cl
= reg_class_for_constraint (cn
);
990 if (insn_extra_address_constraint (cn
))
992 = (reg_class_subunion
993 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
998 op_class
= reg_class_subunion
[op_class
][cl
];
1001 while ((p
+= len
), c
);
1005 /* If OP is a register, return the class of the register as per
1006 get_reg_class, otherwise return NO_REGS. */
1007 static inline enum reg_class
1008 get_op_class (rtx op
)
1010 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1013 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1014 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1015 SUBREG for VAL to make them equal. */
1017 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1019 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1021 /* Usually size of mem_pseudo is greater than val size but in
1022 rare cases it can be less as it can be defined by target
1023 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1026 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1027 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1029 LRA_SUBREG_P (val
) = 1;
1033 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1034 LRA_SUBREG_P (mem_pseudo
) = 1;
1037 return as_a
<rtx_insn
*> (to_p
1038 ? gen_move_insn (mem_pseudo
, val
)
1039 : gen_move_insn (val
, mem_pseudo
));
1042 /* Process a special case insn (register move), return true if we
1043 don't need to process it anymore. INSN should be a single set
1044 insn. Set up that RTL was changed through CHANGE_P and macro
1045 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1048 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1051 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, scratch_reg
;
1053 enum reg_class dclass
, sclass
, secondary_class
;
1054 machine_mode sreg_mode
;
1055 secondary_reload_info sri
;
1057 lra_assert (curr_insn_set
!= NULL_RTX
);
1058 dreg
= dest
= SET_DEST (curr_insn_set
);
1059 sreg
= src
= SET_SRC (curr_insn_set
);
1060 if (GET_CODE (dest
) == SUBREG
)
1061 dreg
= SUBREG_REG (dest
);
1062 if (GET_CODE (src
) == SUBREG
)
1063 sreg
= SUBREG_REG (src
);
1064 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1066 sclass
= dclass
= NO_REGS
;
1068 dclass
= get_reg_class (REGNO (dreg
));
1069 if (dclass
== ALL_REGS
)
1070 /* ALL_REGS is used for new pseudos created by transformations
1071 like reload of SUBREG_REG (see function
1072 simplify_operand_subreg). We don't know their class yet. We
1073 should figure out the class from processing the insn
1074 constraints not in this fast path function. Even if ALL_REGS
1075 were a right class for the pseudo, secondary_... hooks usually
1076 are not define for ALL_REGS. */
1078 sreg_mode
= GET_MODE (sreg
);
1081 sclass
= get_reg_class (REGNO (sreg
));
1082 if (sclass
== ALL_REGS
)
1083 /* See comments above. */
1085 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1087 #ifdef SECONDARY_MEMORY_NEEDED
1088 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1089 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1090 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1091 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1099 if (! REG_P (dreg
) || ! REG_P (sreg
))
1101 sri
.prev_sri
= NULL
;
1102 sri
.icode
= CODE_FOR_nothing
;
1104 secondary_class
= NO_REGS
;
1105 /* Set up hard register for a reload pseudo for hook
1106 secondary_reload because some targets just ignore unassigned
1107 pseudos in the hook. */
1108 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1110 dregno
= REGNO (dreg
);
1111 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1115 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1117 sregno
= REGNO (sreg
);
1118 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1122 if (sclass
!= NO_REGS
)
1124 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1125 (reg_class_t
) sclass
,
1126 GET_MODE (src
), &sri
);
1127 if (sclass
== NO_REGS
1128 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1129 && dclass
!= NO_REGS
))
1131 enum reg_class old_sclass
= secondary_class
;
1132 secondary_reload_info old_sri
= sri
;
1134 sri
.prev_sri
= NULL
;
1135 sri
.icode
= CODE_FOR_nothing
;
1138 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1139 (reg_class_t
) dclass
,
1141 /* Check the target hook consistency. */
1143 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1144 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1145 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1148 reg_renumber
[sregno
] = -1;
1150 reg_renumber
[dregno
] = -1;
1151 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1155 if (secondary_class
!= NO_REGS
)
1156 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1160 if (old_sreg
!= sreg
)
1161 sreg
= copy_rtx (sreg
);
1162 if (sri
.icode
== CODE_FOR_nothing
)
1163 lra_emit_move (new_reg
, sreg
);
1166 enum reg_class scratch_class
;
1168 scratch_class
= (reg_class_from_constraints
1169 (insn_data
[sri
.icode
].operand
[2].constraint
));
1170 scratch_reg
= (lra_create_new_reg_with_unique_value
1171 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1172 scratch_class
, "scratch"));
1173 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1174 sreg
, scratch_reg
));
1176 before
= get_insns ();
1178 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1179 if (new_reg
!= NULL_RTX
)
1181 if (GET_CODE (src
) == SUBREG
)
1182 SUBREG_REG (src
) = new_reg
;
1184 SET_SRC (curr_insn_set
) = new_reg
;
1188 if (lra_dump_file
!= NULL
)
1190 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1191 dump_insn_slim (lra_dump_file
, curr_insn
);
1193 lra_set_insn_deleted (curr_insn
);
1199 /* The following data describe the result of process_alt_operands.
1200 The data are used in curr_insn_transform to generate reloads. */
1202 /* The chosen reg classes which should be used for the corresponding
1204 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1205 /* True if the operand should be the same as another operand and that
1206 other operand does not need a reload. */
1207 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1208 /* True if the operand does not need a reload. */
1209 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1210 /* True if the operand can be offsetable memory. */
1211 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1212 /* The number of an operand to which given operand can be matched to. */
1213 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1214 /* The number of elements in the following array. */
1215 static int goal_alt_dont_inherit_ops_num
;
1216 /* Numbers of operands whose reload pseudos should not be inherited. */
1217 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1218 /* True if the insn commutative operands should be swapped. */
1219 static bool goal_alt_swapped
;
1220 /* The chosen insn alternative. */
1221 static int goal_alt_number
;
1223 /* The following five variables are used to choose the best insn
1224 alternative. They reflect final characteristics of the best
1227 /* Number of necessary reloads and overall cost reflecting the
1228 previous value and other unpleasantness of the best alternative. */
1229 static int best_losers
, best_overall
;
1230 /* Overall number hard registers used for reloads. For example, on
1231 some targets we need 2 general registers to reload DFmode and only
1232 one floating point register. */
1233 static int best_reload_nregs
;
1234 /* Overall number reflecting distances of previous reloading the same
1235 value. The distances are counted from the current BB start. It is
1236 used to improve inheritance chances. */
1237 static int best_reload_sum
;
1239 /* True if the current insn should have no correspondingly input or
1241 static bool no_input_reloads_p
, no_output_reloads_p
;
1243 /* True if we swapped the commutative operands in the current
1245 static int curr_swapped
;
1247 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1248 register of class CL. Add any input reloads to list BEFORE. AFTER
1249 is nonnull if *LOC is an automodified value; handle that case by
1250 adding the required output reloads to list AFTER. Return true if
1251 the RTL was changed.
1253 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1254 register. Return false if the address register is correct. */
1256 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1260 enum reg_class rclass
, new_class
;
1264 bool subreg_p
, before_p
= false;
1266 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1268 loc
= &SUBREG_REG (*loc
);
1270 mode
= GET_MODE (reg
);
1275 /* Always reload memory in an address even if the target supports
1277 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1282 regno
= REGNO (reg
);
1283 rclass
= get_reg_class (regno
);
1285 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1287 if (lra_dump_file
!= NULL
)
1289 fprintf (lra_dump_file
,
1290 "Changing pseudo %d in address of insn %u on equiv ",
1291 REGNO (reg
), INSN_UID (curr_insn
));
1292 dump_value_slim (lra_dump_file
, *loc
, 1);
1293 fprintf (lra_dump_file
, "\n");
1295 *loc
= copy_rtx (*loc
);
1297 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1302 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1303 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1306 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1310 lra_change_class (regno
, new_class
, " Change to", true);
1318 push_to_sequence (*before
);
1319 lra_emit_move (new_reg
, reg
);
1320 *before
= get_insns ();
1327 lra_emit_move (reg
, new_reg
);
1329 *after
= get_insns ();
1335 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1336 the insn to be inserted before curr insn. AFTER returns the
1337 the insn to be inserted after curr insn. ORIGREG and NEWREG
1338 are the original reg and new reg for reload. */
1340 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1345 push_to_sequence (*before
);
1346 lra_emit_move (newreg
, origreg
);
1347 *before
= get_insns ();
1353 lra_emit_move (origreg
, newreg
);
1355 *after
= get_insns ();
1360 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1362 /* Make reloads for subreg in operand NOP with internal subreg mode
1363 REG_MODE, add new reloads for further processing. Return true if
1364 any reload was generated. */
1366 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1369 rtx_insn
*before
, *after
;
1372 rtx operand
= *curr_id
->operand_loc
[nop
];
1373 enum reg_class regclass
;
1376 before
= after
= NULL
;
1378 if (GET_CODE (operand
) != SUBREG
)
1381 mode
= GET_MODE (operand
);
1382 reg
= SUBREG_REG (operand
);
1383 type
= curr_static_id
->operand
[nop
].type
;
1384 /* If we change address for paradoxical subreg of memory, the
1385 address might violate the necessary alignment or the access might
1386 be slow. So take this into consideration. We should not worry
1387 about access beyond allocated memory for paradoxical memory
1388 subregs as we don't substitute such equiv memory (see processing
1389 equivalences in function lra_constraints) and because for spilled
1390 pseudos we allocate stack memory enough for the biggest
1391 corresponding paradoxical subreg. */
1393 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1394 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1396 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1398 alter_subreg (curr_id
->operand_loc
[nop
], false);
1399 subst
= *curr_id
->operand_loc
[nop
];
1400 lra_assert (MEM_P (subst
));
1401 if (! valid_address_p (GET_MODE (reg
), XEXP (reg
, 0),
1402 MEM_ADDR_SPACE (reg
))
1403 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1404 MEM_ADDR_SPACE (subst
)))
1406 /* If the address was valid and became invalid, prefer to reload
1407 the memory. Typical case is when the index scale should
1408 correspond the memory. */
1409 *curr_id
->operand_loc
[nop
] = old
;
1411 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1413 alter_subreg (curr_id
->operand_loc
[nop
], false);
1416 /* Put constant into memory when we have mixed modes. It generates
1417 a better code in most cases as it does not need a secondary
1418 reload memory. It also prevents LRA looping when LRA is using
1419 secondary reload memory again and again. */
1420 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1421 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1423 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1424 alter_subreg (curr_id
->operand_loc
[nop
], false);
1427 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1428 if there may be a problem accessing OPERAND in the outer
1431 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1432 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1433 /* Don't reload paradoxical subregs because we could be looping
1434 having repeatedly final regno out of hard regs range. */
1435 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1436 >= hard_regno_nregs
[hard_regno
][mode
])
1437 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1438 SUBREG_BYTE (operand
), mode
) < 0
1439 /* Don't reload subreg for matching reload. It is actually
1440 valid subreg in LRA. */
1441 && ! LRA_SUBREG_P (operand
))
1442 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1444 enum reg_class rclass
;
1447 /* There is a big probability that we will get the same class
1448 for the new pseudo and we will get the same insn which
1449 means infinite looping. So spill the new pseudo. */
1452 /* The class will be defined later in curr_insn_transform. */
1454 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1456 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1457 rclass
, TRUE
, "subreg reg", &new_reg
))
1459 bool insert_before
, insert_after
;
1460 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1462 insert_before
= (type
!= OP_OUT
1463 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1464 insert_after
= (type
!= OP_IN
);
1465 insert_move_for_subreg (insert_before
? &before
: NULL
,
1466 insert_after
? &after
: NULL
,
1469 SUBREG_REG (operand
) = new_reg
;
1470 lra_process_new_insns (curr_insn
, before
, after
,
1471 "Inserting subreg reload");
1474 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1475 IRA allocates hardreg to the inner pseudo reg according to its mode
1476 instead of the outermode, so the size of the hardreg may not be enough
1477 to contain the outermode operand, in that case we may need to insert
1478 reload for the reg. For the following two types of paradoxical subreg,
1479 we need to insert reload:
1480 1. If the op_type is OP_IN, and the hardreg could not be paired with
1481 other hardreg to contain the outermode operand
1482 (checked by in_hard_reg_set_p), we need to insert the reload.
1483 2. If the op_type is OP_OUT or OP_INOUT.
1485 Here is a paradoxical subreg example showing how the reload is generated:
1487 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1488 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1490 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1491 here, if reg107 is assigned to hardreg R15, because R15 is the last
1492 hardreg, compiler cannot find another hardreg to pair with R15 to
1493 contain TImode data. So we insert a TImode reload reg180 for it.
1494 After reload is inserted:
1496 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1497 (reg:DI 107 [ __comp ])) -1
1498 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1499 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1501 Two reload hard registers will be allocated to reg180 to save TImode data
1503 else if (REG_P (reg
)
1504 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1505 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1506 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1507 < hard_regno_nregs
[hard_regno
][mode
])
1508 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1510 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1513 /* The class will be defined later in curr_insn_transform. */
1514 enum reg_class rclass
1515 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1517 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1518 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1521 bool insert_before
, insert_after
;
1523 PUT_MODE (new_reg
, mode
);
1524 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1525 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1527 insert_before
= (type
!= OP_OUT
);
1528 insert_after
= (type
!= OP_IN
);
1529 insert_move_for_subreg (insert_before
? &before
: NULL
,
1530 insert_after
? &after
: NULL
,
1533 SUBREG_REG (operand
) = new_reg
;
1534 lra_process_new_insns (curr_insn
, before
, after
,
1535 "Inserting paradoxical subreg reload");
1541 /* Return TRUE if X refers for a hard register from SET. */
1543 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1545 int i
, j
, x_hard_regno
;
1552 code
= GET_CODE (x
);
1553 mode
= GET_MODE (x
);
1557 code
= GET_CODE (x
);
1558 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1559 mode
= GET_MODE (x
);
1564 x_hard_regno
= get_hard_regno (x
);
1565 return (x_hard_regno
>= 0
1566 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1570 struct address_info ad
;
1572 decompose_mem_address (&ad
, x
);
1573 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1575 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1578 fmt
= GET_RTX_FORMAT (code
);
1579 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1583 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1586 else if (fmt
[i
] == 'E')
1588 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1589 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1596 /* Return true if OP is a spilled pseudo. */
1598 spilled_pseudo_p (rtx op
)
1601 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1604 /* Return true if X is a general constant. */
1606 general_constant_p (rtx x
)
1608 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1612 reg_in_class_p (rtx reg
, enum reg_class cl
)
1615 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1616 return in_class_p (reg
, cl
, NULL
);
1619 /* Major function to choose the current insn alternative and what
1620 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1621 negative we should consider only this alternative. Return false if
1622 we can not choose the alternative or find how to reload the
1625 process_alt_operands (int only_alternative
)
1628 int nop
, overall
, nalt
;
1629 int n_alternatives
= curr_static_id
->n_alternatives
;
1630 int n_operands
= curr_static_id
->n_operands
;
1631 /* LOSERS counts the operands that don't fit this alternative and
1632 would require loading. */
1634 /* REJECT is a count of how undesirable this alternative says it is
1635 if any reloading is required. If the alternative matches exactly
1636 then REJECT is ignored, but otherwise it gets this much counted
1637 against it in addition to the reloading needed. */
1639 /* The number of elements in the following array. */
1640 int early_clobbered_regs_num
;
1641 /* Numbers of operands which are early clobber registers. */
1642 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1643 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1644 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1645 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1646 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1647 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1648 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1649 /* The number of elements in the following array. */
1650 int curr_alt_dont_inherit_ops_num
;
1651 /* Numbers of operands whose reload pseudos should not be inherited. */
1652 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1654 /* The register when the operand is a subreg of register, otherwise the
1656 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1657 /* The register if the operand is a register or subreg of register,
1659 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1660 int hard_regno
[MAX_RECOG_OPERANDS
];
1661 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1662 int reload_nregs
, reload_sum
;
1666 /* Calculate some data common for all alternatives to speed up the
1668 for (nop
= 0; nop
< n_operands
; nop
++)
1672 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1673 /* The real hard regno of the operand after the allocation. */
1674 hard_regno
[nop
] = get_hard_regno (op
);
1676 operand_reg
[nop
] = reg
= op
;
1677 biggest_mode
[nop
] = GET_MODE (op
);
1678 if (GET_CODE (op
) == SUBREG
)
1680 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1681 if (GET_MODE_SIZE (biggest_mode
[nop
])
1682 < GET_MODE_SIZE (GET_MODE (reg
)))
1683 biggest_mode
[nop
] = GET_MODE (reg
);
1686 operand_reg
[nop
] = NULL_RTX
;
1687 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1688 || ((int) REGNO (reg
)
1689 == lra_get_elimination_hard_regno (REGNO (reg
))))
1690 no_subreg_reg_operand
[nop
] = reg
;
1692 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1693 /* Just use natural mode for elimination result. It should
1694 be enough for extra constraints hooks. */
1695 = regno_reg_rtx
[hard_regno
[nop
]];
1698 /* The constraints are made of several alternatives. Each operand's
1699 constraint looks like foo,bar,... with commas separating the
1700 alternatives. The first alternatives for all operands go
1701 together, the second alternatives go together, etc.
1703 First loop over alternatives. */
1704 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1705 if (only_alternative
>= 0)
1706 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1708 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1710 /* Loop over operands for one constraint alternative. */
1711 if (!TEST_BIT (preferred
, nalt
))
1714 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1715 for (nop
= 0; nop
< n_operands
; nop
++)
1717 int inc
= (curr_static_id
1718 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1719 if (lra_dump_file
!= NULL
&& inc
!= 0)
1720 fprintf (lra_dump_file
,
1721 " Staticly defined alt reject+=%d\n", inc
);
1724 early_clobbered_regs_num
= 0;
1726 for (nop
= 0; nop
< n_operands
; nop
++)
1730 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1731 bool win
, did_match
, offmemok
, early_clobber_p
;
1732 /* false => this operand can be reloaded somehow for this
1735 /* true => this operand can be reloaded if the alternative
1738 /* True if a constant forced into memory would be OK for
1741 enum reg_class this_alternative
, this_costly_alternative
;
1742 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1743 bool this_alternative_match_win
, this_alternative_win
;
1744 bool this_alternative_offmemok
;
1747 enum constraint_num cn
;
1749 opalt_num
= nalt
* n_operands
+ nop
;
1750 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1752 /* Fast track for no constraints at all. */
1753 curr_alt
[nop
] = NO_REGS
;
1754 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1755 curr_alt_win
[nop
] = true;
1756 curr_alt_match_win
[nop
] = false;
1757 curr_alt_offmemok
[nop
] = false;
1758 curr_alt_matches
[nop
] = -1;
1762 op
= no_subreg_reg_operand
[nop
];
1763 mode
= curr_operand_mode
[nop
];
1765 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1768 early_clobber_p
= false;
1769 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1771 this_costly_alternative
= this_alternative
= NO_REGS
;
1772 /* We update set of possible hard regs besides its class
1773 because reg class might be inaccurate. For example,
1774 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1775 is translated in HI_REGS because classes are merged by
1776 pairs and there is no accurate intermediate class. */
1777 CLEAR_HARD_REG_SET (this_alternative_set
);
1778 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1779 this_alternative_win
= false;
1780 this_alternative_match_win
= false;
1781 this_alternative_offmemok
= false;
1782 this_alternative_matches
= -1;
1784 /* An empty constraint should be excluded by the fast
1786 lra_assert (*p
!= 0 && *p
!= ',');
1788 /* Scan this alternative's specs for this operand; set WIN
1789 if the operand fits any letter in this alternative.
1790 Otherwise, clear BADOP if this operand could fit some
1791 letter after reloads, or set WINREG if this operand could
1792 fit after reloads provided the constraint allows some
1797 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1807 early_clobber_p
= true;
1811 /* Ignore rest of this alternative. */
1815 case '0': case '1': case '2': case '3': case '4':
1816 case '5': case '6': case '7': case '8': case '9':
1821 m
= strtoul (p
, &end
, 10);
1824 lra_assert (nop
> m
);
1826 this_alternative_matches
= m
;
1827 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1828 /* We are supposed to match a previous operand.
1829 If we do, we win if that one did. If we do
1830 not, count both of the operands as losers.
1831 (This is too conservative, since most of the
1832 time only a single reload insn will be needed
1833 to make the two operands win. As a result,
1834 this alternative may be rejected when it is
1835 actually desirable.) */
1837 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1838 *curr_id
->operand_loc
[m
], m_hregno
))
1840 /* We should reject matching of an early
1841 clobber operand if the matching operand is
1842 not dying in the insn. */
1843 if (! curr_static_id
->operand
[m
].early_clobber
1844 || operand_reg
[nop
] == NULL_RTX
1845 || (find_regno_note (curr_insn
, REG_DEAD
,
1847 || REGNO (op
) == REGNO (operand_reg
[m
])))
1852 /* If we are matching a non-offsettable
1853 address where an offsettable address was
1854 expected, then we must reject this
1855 combination, because we can't reload
1857 if (curr_alt_offmemok
[m
]
1858 && MEM_P (*curr_id
->operand_loc
[m
])
1859 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1864 /* Operands don't match. Both operands must
1865 allow a reload register, otherwise we
1866 cannot make them match. */
1867 if (curr_alt
[m
] == NO_REGS
)
1869 /* Retroactively mark the operand we had to
1870 match as a loser, if it wasn't already and
1871 it wasn't matched to a register constraint
1872 (e.g it might be matched by memory). */
1874 && (operand_reg
[m
] == NULL_RTX
1875 || hard_regno
[m
] < 0))
1879 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1880 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1883 /* Prefer matching earlyclobber alternative as
1884 it results in less hard regs required for
1885 the insn than a non-matching earlyclobber
1887 if (curr_static_id
->operand
[m
].early_clobber
)
1889 if (lra_dump_file
!= NULL
)
1892 " %d Matching earlyclobber alt:"
1897 /* Otherwise we prefer no matching
1898 alternatives because it gives more freedom
1900 else if (operand_reg
[nop
] == NULL_RTX
1901 || (find_regno_note (curr_insn
, REG_DEAD
,
1902 REGNO (operand_reg
[nop
]))
1905 if (lra_dump_file
!= NULL
)
1908 " %d Matching alt: reject+=2\n",
1913 /* If we have to reload this operand and some
1914 previous operand also had to match the same
1915 thing as this operand, we don't know how to do
1917 if (!match_p
|| !curr_alt_win
[m
])
1919 for (i
= 0; i
< nop
; i
++)
1920 if (curr_alt_matches
[i
] == m
)
1928 /* This can be fixed with reloads if the operand
1929 we are supposed to match can be fixed with
1932 this_alternative
= curr_alt
[m
];
1933 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1934 winreg
= this_alternative
!= NO_REGS
;
1940 || general_constant_p (op
)
1941 || spilled_pseudo_p (op
))
1947 cn
= lookup_constraint (p
);
1948 switch (get_constraint_type (cn
))
1951 cl
= reg_class_for_constraint (cn
);
1957 if (CONST_INT_P (op
)
1958 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1964 && satisfies_memory_constraint_p (op
, cn
))
1966 else if (spilled_pseudo_p (op
))
1969 /* If we didn't already win, we can reload constants
1970 via force_const_mem or put the pseudo value into
1971 memory, or make other memory by reloading the
1972 address like for 'o'. */
1973 if (CONST_POOL_OK_P (mode
, op
)
1974 || MEM_P (op
) || REG_P (op
))
1981 /* If we didn't already win, we can reload the address
1982 into a base register. */
1983 if (satisfies_address_constraint_p (op
, cn
))
1985 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1991 if (constraint_satisfied_p (op
, cn
))
1998 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1999 IOR_HARD_REG_SET (this_alternative_set
,
2000 reg_class_contents
[cl
]);
2003 this_costly_alternative
2004 = reg_class_subunion
[this_costly_alternative
][cl
];
2005 IOR_HARD_REG_SET (this_costly_alternative_set
,
2006 reg_class_contents
[cl
]);
2008 if (mode
== BLKmode
)
2013 if (hard_regno
[nop
] >= 0
2014 && in_hard_reg_set_p (this_alternative_set
,
2015 mode
, hard_regno
[nop
]))
2017 else if (hard_regno
[nop
] < 0
2018 && in_class_p (op
, this_alternative
, NULL
))
2023 if (c
!= ' ' && c
!= '\t')
2024 costly_p
= c
== '*';
2026 while ((p
+= len
), c
);
2028 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2029 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2030 /* Record which operands fit this alternative. */
2033 this_alternative_win
= true;
2034 if (operand_reg
[nop
] != NULL_RTX
)
2036 if (hard_regno
[nop
] >= 0)
2038 if (in_hard_reg_set_p (this_costly_alternative_set
,
2039 mode
, hard_regno
[nop
]))
2041 if (lra_dump_file
!= NULL
)
2042 fprintf (lra_dump_file
,
2043 " %d Costly set: reject++\n",
2050 /* Prefer won reg to spilled pseudo under other
2051 equal conditions for possibe inheritance. */
2054 if (lra_dump_file
!= NULL
)
2057 " %d Non pseudo reload: reject++\n",
2061 if (in_class_p (operand_reg
[nop
],
2062 this_costly_alternative
, NULL
))
2064 if (lra_dump_file
!= NULL
)
2067 " %d Non pseudo costly reload:"
2073 /* We simulate the behaviour of old reload here.
2074 Although scratches need hard registers and it
2075 might result in spilling other pseudos, no reload
2076 insns are generated for the scratches. So it
2077 might cost something but probably less than old
2078 reload pass believes. */
2081 if (lra_dump_file
!= NULL
)
2082 fprintf (lra_dump_file
,
2083 " %d Scratch win: reject+=2\n",
2090 this_alternative_match_win
= true;
2093 int const_to_mem
= 0;
2096 /* Never do output reload of stack pointer. It makes
2097 impossible to do elimination when SP is changed in
2099 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2100 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2103 /* If this alternative asks for a specific reg class, see if there
2104 is at least one allocatable register in that class. */
2106 = (this_alternative
== NO_REGS
2107 || (hard_reg_set_subset_p
2108 (reg_class_contents
[this_alternative
],
2109 lra_no_alloc_regs
)));
2111 /* For asms, verify that the class for this alternative is possible
2112 for the mode that is specified. */
2113 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2116 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2117 if (HARD_REGNO_MODE_OK (i
, mode
)
2118 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2121 if (i
== FIRST_PSEUDO_REGISTER
)
2125 /* If this operand accepts a register, and if the
2126 register class has at least one allocatable register,
2127 then this operand can be reloaded. */
2128 if (winreg
&& !no_regs_p
)
2133 if (lra_dump_file
!= NULL
)
2134 fprintf (lra_dump_file
,
2135 " alt=%d: Bad operand -- refuse\n",
2140 /* If not assigned pseudo has a class which a subset of
2141 required reg class, it is a less costly alternative
2142 as the pseudo still can get a hard reg of necessary
2144 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2145 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2146 && ira_class_subset_p
[this_alternative
][cl
])
2148 if (lra_dump_file
!= NULL
)
2151 " %d Super set class reg: reject-=3\n", nop
);
2155 this_alternative_offmemok
= offmemok
;
2156 if (this_costly_alternative
!= NO_REGS
)
2158 if (lra_dump_file
!= NULL
)
2159 fprintf (lra_dump_file
,
2160 " %d Costly loser: reject++\n", nop
);
2163 /* If the operand is dying, has a matching constraint,
2164 and satisfies constraints of the matched operand
2165 which failed to satisfy the own constraints, most probably
2166 the reload for this operand will be gone. */
2167 if (this_alternative_matches
>= 0
2168 && !curr_alt_win
[this_alternative_matches
]
2170 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2171 && (hard_regno
[nop
] >= 0
2172 ? in_hard_reg_set_p (this_alternative_set
,
2173 mode
, hard_regno
[nop
])
2174 : in_class_p (op
, this_alternative
, NULL
)))
2176 if (lra_dump_file
!= NULL
)
2179 " %d Dying matched operand reload: reject++\n",
2185 /* Strict_low_part requires to reload the register
2186 not the sub-register. In this case we should
2187 check that a final reload hard reg can hold the
2189 if (curr_static_id
->operand
[nop
].strict_low
2191 && hard_regno
[nop
] < 0
2192 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2193 && ira_class_hard_regs_num
[this_alternative
] > 0
2194 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2195 [this_alternative
][0],
2197 (*curr_id
->operand_loc
[nop
])))
2199 if (lra_dump_file
!= NULL
)
2202 " alt=%d: Strict low subreg reload -- refuse\n",
2208 if (operand_reg
[nop
] != NULL_RTX
2209 /* Output operands and matched input operands are
2210 not inherited. The following conditions do not
2211 exactly describe the previous statement but they
2212 are pretty close. */
2213 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2214 && (this_alternative_matches
< 0
2215 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2217 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2221 /* The value of reload_sum has sense only if we
2222 process insns in their order. It happens only on
2223 the first constraints sub-pass when we do most of
2225 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2226 reload_sum
+= last_reload
- bb_reload_num
;
2228 /* If this is a constant that is reloaded into the
2229 desired class by copying it to memory first, count
2230 that as another reload. This is consistent with
2231 other code and is required to avoid choosing another
2232 alternative when the constant is moved into memory.
2233 Note that the test here is precisely the same as in
2234 the code below that calls force_const_mem. */
2235 if (CONST_POOL_OK_P (mode
, op
)
2236 && ((targetm
.preferred_reload_class
2237 (op
, this_alternative
) == NO_REGS
)
2238 || no_input_reloads_p
))
2245 /* Alternative loses if it requires a type of reload not
2246 permitted for this insn. We can always reload
2247 objects with a REG_UNUSED note. */
2248 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2249 && no_output_reloads_p
2250 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2251 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2252 && no_input_reloads_p
&& ! const_to_mem
)
2253 || (this_alternative_matches
>= 0
2254 && (no_input_reloads_p
2255 || (no_output_reloads_p
2256 && (curr_static_id
->operand
2257 [this_alternative_matches
].type
!= OP_IN
)
2258 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2259 no_subreg_reg_operand
2260 [this_alternative_matches
])))))
2262 if (lra_dump_file
!= NULL
)
2265 " alt=%d: No input/otput reload -- refuse\n",
2270 /* Alternative loses if it required class pseudo can not
2271 hold value of required mode. Such insns can be
2272 described by insn definitions with mode iterators. */
2273 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2274 && ! hard_reg_set_empty_p (this_alternative_set
)
2275 /* It is common practice for constraints to use a
2276 class which does not have actually enough regs to
2277 hold the value (e.g. x86 AREG for mode requiring
2278 more one general reg). Therefore we have 2
2279 conditions to check that the reload pseudo can
2280 not hold the mode value. */
2281 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2282 [this_alternative
][0],
2283 GET_MODE (*curr_id
->operand_loc
[nop
]))
2284 /* The above condition is not enough as the first
2285 reg in ira_class_hard_regs can be not aligned for
2286 multi-words mode values. */
2287 && hard_reg_set_subset_p (this_alternative_set
,
2288 ira_prohibited_class_mode_regs
2290 [GET_MODE (*curr_id
->operand_loc
[nop
])]))
2292 if (lra_dump_file
!= NULL
)
2295 " alt=%d: reload pseudo for op %d "
2296 " can not hold the mode value -- refuse\n",
2301 /* Check strong discouragement of reload of non-constant
2302 into class THIS_ALTERNATIVE. */
2303 if (! CONSTANT_P (op
) && ! no_regs_p
2304 && (targetm
.preferred_reload_class
2305 (op
, this_alternative
) == NO_REGS
2306 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2307 && (targetm
.preferred_output_reload_class
2308 (op
, this_alternative
) == NO_REGS
))))
2310 if (lra_dump_file
!= NULL
)
2311 fprintf (lra_dump_file
,
2312 " %d Non-prefered reload: reject+=%d\n",
2313 nop
, LRA_MAX_REJECT
);
2314 reject
+= LRA_MAX_REJECT
;
2317 if (! (MEM_P (op
) && offmemok
)
2318 && ! (const_to_mem
&& constmemok
))
2320 /* We prefer to reload pseudos over reloading other
2321 things, since such reloads may be able to be
2322 eliminated later. So bump REJECT in other cases.
2323 Don't do this in the case where we are forcing a
2324 constant into memory and it will then win since
2325 we don't want to have a different alternative
2327 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2329 if (lra_dump_file
!= NULL
)
2332 " %d Non-pseudo reload: reject+=2\n",
2339 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2341 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2343 if (lra_dump_file
!= NULL
)
2346 " %d Small class reload: reject+=%d\n",
2347 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2348 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2352 /* We are trying to spill pseudo into memory. It is
2353 usually more costly than moving to a hard register
2354 although it might takes the same number of
2356 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2358 if (lra_dump_file
!= NULL
)
2361 " %d Spill pseudo into memory: reject+=3\n",
2364 if (VECTOR_MODE_P (mode
))
2366 /* Spilling vectors into memory is usually more
2367 costly as they contain big values. */
2368 if (lra_dump_file
!= NULL
)
2371 " %d Spill vector pseudo: reject+=2\n",
2377 #ifdef SECONDARY_MEMORY_NEEDED
2378 /* If reload requires moving value through secondary
2379 memory, it will need one more insn at least. */
2380 if (this_alternative
!= NO_REGS
2381 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2382 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2383 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2385 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2386 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2390 /* Input reloads can be inherited more often than output
2391 reloads can be removed, so penalize output
2393 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2395 if (lra_dump_file
!= NULL
)
2398 " %d Non input pseudo reload: reject++\n",
2404 if (early_clobber_p
&& ! scratch_p
)
2406 if (lra_dump_file
!= NULL
)
2407 fprintf (lra_dump_file
,
2408 " %d Early clobber: reject++\n", nop
);
2411 /* ??? We check early clobbers after processing all operands
2412 (see loop below) and there we update the costs more.
2413 Should we update the cost (may be approximately) here
2414 because of early clobber register reloads or it is a rare
2415 or non-important thing to be worth to do it. */
2416 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2417 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2419 if (lra_dump_file
!= NULL
)
2420 fprintf (lra_dump_file
,
2421 " alt=%d,overall=%d,losers=%d -- refuse\n",
2422 nalt
, overall
, losers
);
2426 curr_alt
[nop
] = this_alternative
;
2427 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2428 curr_alt_win
[nop
] = this_alternative_win
;
2429 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2430 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2431 curr_alt_matches
[nop
] = this_alternative_matches
;
2433 if (this_alternative_matches
>= 0
2434 && !did_match
&& !this_alternative_win
)
2435 curr_alt_win
[this_alternative_matches
] = false;
2437 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2438 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2440 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2441 /* Prevent processing non-move insns. */
2442 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2443 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2444 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2445 && REG_P (no_subreg_reg_operand
[0])
2446 && REG_P (no_subreg_reg_operand
[1])
2447 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2448 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2449 || (! curr_alt_win
[0] && curr_alt_win
[1]
2450 && REG_P (no_subreg_reg_operand
[1])
2451 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2452 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2453 && REG_P (no_subreg_reg_operand
[0])
2454 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2455 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2456 no_subreg_reg_operand
[1])
2457 || (targetm
.preferred_reload_class
2458 (no_subreg_reg_operand
[1],
2459 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2460 /* If it is a result of recent elimination in move
2461 insn we can transform it into an add still by
2462 using this alternative. */
2463 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2465 /* We have a move insn and a new reload insn will be similar
2466 to the current insn. We should avoid such situation as it
2467 results in LRA cycling. */
2468 overall
+= LRA_MAX_REJECT
;
2471 curr_alt_dont_inherit_ops_num
= 0;
2472 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2474 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2475 HARD_REG_SET temp_set
;
2477 i
= early_clobbered_nops
[nop
];
2478 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2479 || hard_regno
[i
] < 0)
2481 lra_assert (operand_reg
[i
] != NULL_RTX
);
2482 clobbered_hard_regno
= hard_regno
[i
];
2483 CLEAR_HARD_REG_SET (temp_set
);
2484 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2485 first_conflict_j
= last_conflict_j
= -1;
2486 for (j
= 0; j
< n_operands
; j
++)
2488 /* We don't want process insides of match_operator and
2489 match_parallel because otherwise we would process
2490 their operands once again generating a wrong
2492 || curr_static_id
->operand
[j
].is_operator
)
2494 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2495 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2497 /* If we don't reload j-th operand, check conflicts. */
2498 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2499 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2501 if (first_conflict_j
< 0)
2502 first_conflict_j
= j
;
2503 last_conflict_j
= j
;
2505 if (last_conflict_j
< 0)
2507 /* If earlyclobber operand conflicts with another
2508 non-matching operand which is actually the same register
2509 as the earlyclobber operand, it is better to reload the
2510 another operand as an operand matching the earlyclobber
2511 operand can be also the same. */
2512 if (first_conflict_j
== last_conflict_j
2513 && operand_reg
[last_conflict_j
]
2514 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2515 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2517 curr_alt_win
[last_conflict_j
] = false;
2518 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2521 /* Early clobber was already reflected in REJECT. */
2522 lra_assert (reject
> 0);
2523 if (lra_dump_file
!= NULL
)
2526 " %d Conflict early clobber reload: reject--\n",
2529 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2533 /* We need to reload early clobbered register and the
2534 matched registers. */
2535 for (j
= 0; j
< n_operands
; j
++)
2536 if (curr_alt_matches
[j
] == i
)
2538 curr_alt_match_win
[j
] = false;
2540 overall
+= LRA_LOSER_COST_FACTOR
;
2542 if (! curr_alt_match_win
[i
])
2543 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2546 /* Remember pseudos used for match reloads are never
2548 lra_assert (curr_alt_matches
[i
] >= 0);
2549 curr_alt_win
[curr_alt_matches
[i
]] = false;
2551 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2553 /* Early clobber was already reflected in REJECT. */
2554 lra_assert (reject
> 0);
2555 if (lra_dump_file
!= NULL
)
2558 " %d Matched conflict early clobber reloads:"
2562 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2565 if (lra_dump_file
!= NULL
)
2566 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2567 nalt
, overall
, losers
, reload_nregs
);
2569 /* If this alternative can be made to work by reloading, and it
2570 needs less reloading than the others checked so far, record
2571 it as the chosen goal for reloading. */
2572 if ((best_losers
!= 0 && losers
== 0)
2573 || (((best_losers
== 0 && losers
== 0)
2574 || (best_losers
!= 0 && losers
!= 0))
2575 && (best_overall
> overall
2576 || (best_overall
== overall
2577 /* If the cost of the reloads is the same,
2578 prefer alternative which requires minimal
2579 number of reload regs. */
2580 && (reload_nregs
< best_reload_nregs
2581 || (reload_nregs
== best_reload_nregs
2582 && (best_reload_sum
< reload_sum
2583 || (best_reload_sum
== reload_sum
2584 && nalt
< goal_alt_number
))))))))
2586 for (nop
= 0; nop
< n_operands
; nop
++)
2588 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2589 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2590 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2591 goal_alt
[nop
] = curr_alt
[nop
];
2592 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2594 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2595 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2596 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2597 goal_alt_swapped
= curr_swapped
;
2598 best_overall
= overall
;
2599 best_losers
= losers
;
2600 best_reload_nregs
= reload_nregs
;
2601 best_reload_sum
= reload_sum
;
2602 goal_alt_number
= nalt
;
2605 /* Everything is satisfied. Do not process alternatives
2614 /* Make reload base reg from address AD. */
2616 base_to_reg (struct address_info
*ad
)
2620 rtx new_inner
= NULL_RTX
;
2621 rtx new_reg
= NULL_RTX
;
2623 rtx_insn
*last_insn
= get_last_insn();
2625 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2626 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2627 get_index_code (ad
));
2628 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2630 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2631 ad
->disp_term
== NULL
2632 ? gen_int_mode (0, ad
->mode
)
2634 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2636 insn
= emit_insn (gen_rtx_SET (ad
->mode
, new_reg
, *ad
->base_term
));
2637 code
= recog_memoized (insn
);
2640 delete_insns_since (last_insn
);
2647 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2649 base_plus_disp_to_reg (struct address_info
*ad
)
2654 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2655 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2656 get_index_code (ad
));
2657 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2659 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2663 /* Make reload of index part of address AD. Return the new
2666 index_part_to_reg (struct address_info
*ad
)
2670 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2671 INDEX_REG_CLASS
, "index term");
2672 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2673 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2677 /* Return true if we can add a displacement to address AD, even if that
2678 makes the address invalid. The fix-up code requires any new address
2679 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2681 can_add_disp_p (struct address_info
*ad
)
2683 return (!ad
->autoinc_p
2684 && ad
->segment
== NULL
2685 && ad
->base
== ad
->base_term
2686 && ad
->disp
== ad
->disp_term
);
2689 /* Make equiv substitution in address AD. Return true if a substitution
2692 equiv_address_substitution (struct address_info
*ad
)
2694 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2695 HOST_WIDE_INT disp
, scale
;
2698 base_term
= strip_subreg (ad
->base_term
);
2699 if (base_term
== NULL
)
2700 base_reg
= new_base_reg
= NULL_RTX
;
2703 base_reg
= *base_term
;
2704 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2706 index_term
= strip_subreg (ad
->index_term
);
2707 if (index_term
== NULL
)
2708 index_reg
= new_index_reg
= NULL_RTX
;
2711 index_reg
= *index_term
;
2712 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2714 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2718 if (lra_dump_file
!= NULL
)
2720 fprintf (lra_dump_file
, "Changing address in insn %d ",
2721 INSN_UID (curr_insn
));
2722 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2724 if (base_reg
!= new_base_reg
)
2726 if (REG_P (new_base_reg
))
2728 *base_term
= new_base_reg
;
2731 else if (GET_CODE (new_base_reg
) == PLUS
2732 && REG_P (XEXP (new_base_reg
, 0))
2733 && CONST_INT_P (XEXP (new_base_reg
, 1))
2734 && can_add_disp_p (ad
))
2736 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2737 *base_term
= XEXP (new_base_reg
, 0);
2740 if (ad
->base_term2
!= NULL
)
2741 *ad
->base_term2
= *ad
->base_term
;
2743 if (index_reg
!= new_index_reg
)
2745 if (REG_P (new_index_reg
))
2747 *index_term
= new_index_reg
;
2750 else if (GET_CODE (new_index_reg
) == PLUS
2751 && REG_P (XEXP (new_index_reg
, 0))
2752 && CONST_INT_P (XEXP (new_index_reg
, 1))
2753 && can_add_disp_p (ad
)
2754 && (scale
= get_index_scale (ad
)))
2756 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2757 *index_term
= XEXP (new_index_reg
, 0);
2763 if (ad
->disp
!= NULL
)
2764 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2767 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2768 update_address (ad
);
2772 if (lra_dump_file
!= NULL
)
2775 fprintf (lra_dump_file
, " -- no change\n");
2778 fprintf (lra_dump_file
, " on equiv ");
2779 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2780 fprintf (lra_dump_file
, "\n");
2786 /* Major function to make reloads for an address in operand NOP or
2787 check its correctness (If CHECK_ONLY_P is true). The supported
2790 1) an address that existed before LRA started, at which point it
2791 must have been valid. These addresses are subject to elimination
2792 and may have become invalid due to the elimination offset being out
2795 2) an address created by forcing a constant to memory
2796 (force_const_to_mem). The initial form of these addresses might
2797 not be valid, and it is this function's job to make them valid.
2799 3) a frame address formed from a register and a (possibly zero)
2800 constant offset. As above, these addresses might not be valid and
2801 this function must make them so.
2803 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2804 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2805 address. Return true for any RTL change.
2807 The function is a helper function which does not produce all
2808 transformations (when CHECK_ONLY_P is false) which can be
2809 necessary. It does just basic steps. To do all necessary
2810 transformations use function process_address. */
2812 process_address_1 (int nop
, bool check_only_p
,
2813 rtx_insn
**before
, rtx_insn
**after
)
2815 struct address_info ad
;
2817 rtx op
= *curr_id
->operand_loc
[nop
];
2818 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2819 enum constraint_num cn
= lookup_constraint (constraint
);
2820 bool change_p
= false;
2822 if (insn_extra_address_constraint (cn
))
2823 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2824 else if (MEM_P (op
))
2825 decompose_mem_address (&ad
, op
);
2826 else if (GET_CODE (op
) == SUBREG
2827 && MEM_P (SUBREG_REG (op
)))
2828 decompose_mem_address (&ad
, SUBREG_REG (op
));
2832 change_p
= equiv_address_substitution (&ad
);
2833 if (ad
.base_term
!= NULL
2834 && (process_addr_reg
2835 (ad
.base_term
, check_only_p
, before
,
2837 && !(REG_P (*ad
.base_term
)
2838 && find_regno_note (curr_insn
, REG_DEAD
,
2839 REGNO (*ad
.base_term
)) != NULL_RTX
)
2841 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2842 get_index_code (&ad
)))))
2845 if (ad
.base_term2
!= NULL
)
2846 *ad
.base_term2
= *ad
.base_term
;
2848 if (ad
.index_term
!= NULL
2849 && process_addr_reg (ad
.index_term
, check_only_p
,
2850 before
, NULL
, INDEX_REG_CLASS
))
2853 /* Target hooks sometimes don't treat extra-constraint addresses as
2854 legitimate address_operands, so handle them specially. */
2855 if (insn_extra_address_constraint (cn
)
2856 && satisfies_address_constraint_p (&ad
, cn
))
2862 /* There are three cases where the shape of *AD.INNER may now be invalid:
2864 1) the original address was valid, but either elimination or
2865 equiv_address_substitution was applied and that made
2866 the address invalid.
2868 2) the address is an invalid symbolic address created by
2871 3) the address is a frame address with an invalid offset.
2873 4) the address is a frame address with an invalid base.
2875 All these cases involve a non-autoinc address, so there is no
2876 point revalidating other types. */
2877 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2880 /* Any index existed before LRA started, so we can assume that the
2881 presence and shape of the index is valid. */
2882 push_to_sequence (*before
);
2883 lra_assert (ad
.disp
== ad
.disp_term
);
2884 if (ad
.base
== NULL
)
2886 if (ad
.index
== NULL
)
2889 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2891 rtx addr
= *ad
.inner
;
2893 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2897 rtx_insn
*last
= get_last_insn ();
2899 /* addr => lo_sum (new_base, addr), case (2) above. */
2900 insn
= emit_insn (gen_rtx_SET
2902 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2903 code
= recog_memoized (insn
);
2906 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2907 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2909 /* Try to put lo_sum into register. */
2910 insn
= emit_insn (gen_rtx_SET
2912 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2913 code
= recog_memoized (insn
);
2916 *ad
.inner
= new_reg
;
2917 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2927 delete_insns_since (last
);
2932 /* addr => new_base, case (2) above. */
2933 lra_emit_move (new_reg
, addr
);
2934 *ad
.inner
= new_reg
;
2939 /* index * scale + disp => new base + index * scale,
2941 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2942 GET_CODE (*ad
.index
));
2944 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2945 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2946 lra_emit_move (new_reg
, *ad
.disp
);
2947 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2948 new_reg
, *ad
.index
);
2951 else if (ad
.index
== NULL
)
2956 rtx_insn
*insns
, *last_insn
;
2957 /* Try to reload base into register only if the base is invalid
2958 for the address but with valid offset, case (4) above. */
2960 new_reg
= base_to_reg (&ad
);
2962 /* base + disp => new base, cases (1) and (3) above. */
2963 /* Another option would be to reload the displacement into an
2964 index register. However, postreload has code to optimize
2965 address reloads that have the same base and different
2966 displacements, so reloading into an index register would
2967 not necessarily be a win. */
2968 if (new_reg
== NULL_RTX
)
2969 new_reg
= base_plus_disp_to_reg (&ad
);
2970 insns
= get_insns ();
2971 last_insn
= get_last_insn ();
2972 /* If we generated at least two insns, try last insn source as
2973 an address. If we succeed, we generate one less insn. */
2974 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2975 && GET_CODE (SET_SRC (set
)) == PLUS
2976 && REG_P (XEXP (SET_SRC (set
), 0))
2977 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2979 *ad
.inner
= SET_SRC (set
);
2980 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2982 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2983 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2984 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2985 get_index_code (&ad
));
2986 regno
= REGNO (*ad
.base_term
);
2987 if (regno
>= FIRST_PSEUDO_REGISTER
2988 && cl
!= lra_get_allocno_class (regno
))
2989 lra_change_class (regno
, cl
, " Change to", true);
2990 new_reg
= SET_SRC (set
);
2991 delete_insns_since (PREV_INSN (last_insn
));
2996 *ad
.inner
= new_reg
;
2998 else if (ad
.disp_term
!= NULL
)
3000 /* base + scale * index + disp => new base + scale * index,
3002 new_reg
= base_plus_disp_to_reg (&ad
);
3003 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3004 new_reg
, *ad
.index
);
3006 else if (get_index_scale (&ad
) == 1)
3008 /* The last transformation to one reg will be made in
3009 curr_insn_transform function. */
3015 /* base + scale * index => base + new_reg,
3017 Index part of address may become invalid. For example, we
3018 changed pseudo on the equivalent memory and a subreg of the
3019 pseudo onto the memory of different mode for which the scale is
3021 new_reg
= index_part_to_reg (&ad
);
3022 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3023 *ad
.base_term
, new_reg
);
3025 *before
= get_insns ();
3030 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3031 Use process_address_1 as a helper function. Return true for any
3034 If CHECK_ONLY_P is true, just check address correctness. Return
3035 false if the address correct. */
3037 process_address (int nop
, bool check_only_p
,
3038 rtx_insn
**before
, rtx_insn
**after
)
3042 while (process_address_1 (nop
, check_only_p
, before
, after
))
3051 /* Emit insns to reload VALUE into a new register. VALUE is an
3052 auto-increment or auto-decrement RTX whose operand is a register or
3053 memory location; so reloading involves incrementing that location.
3054 IN is either identical to VALUE, or some cheaper place to reload
3055 value being incremented/decremented from.
3057 INC_AMOUNT is the number to increment or decrement by (always
3058 positive and ignored for POST_MODIFY/PRE_MODIFY).
3060 Return pseudo containing the result. */
3062 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3064 /* REG or MEM to be copied and incremented. */
3065 rtx incloc
= XEXP (value
, 0);
3066 /* Nonzero if increment after copying. */
3067 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3068 || GET_CODE (value
) == POST_MODIFY
);
3073 rtx real_in
= in
== value
? incloc
: in
;
3077 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3079 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3080 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3081 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3082 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3083 inc
= XEXP (XEXP (value
, 1), 1);
3087 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3088 inc_amount
= -inc_amount
;
3090 inc
= GEN_INT (inc_amount
);
3093 if (! post
&& REG_P (incloc
))
3096 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3099 if (real_in
!= result
)
3101 /* First copy the location to the result register. */
3102 lra_assert (REG_P (result
));
3103 emit_insn (gen_move_insn (result
, real_in
));
3106 /* We suppose that there are insns to add/sub with the constant
3107 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3108 old reload worked with this assumption. If the assumption
3109 becomes wrong, we should use approach in function
3110 base_plus_disp_to_reg. */
3113 /* See if we can directly increment INCLOC. */
3114 last
= get_last_insn ();
3115 add_insn
= emit_insn (plus_p
3116 ? gen_add2_insn (incloc
, inc
)
3117 : gen_sub2_insn (incloc
, inc
));
3119 code
= recog_memoized (add_insn
);
3122 if (! post
&& result
!= incloc
)
3123 emit_insn (gen_move_insn (result
, incloc
));
3126 delete_insns_since (last
);
3129 /* If couldn't do the increment directly, must increment in RESULT.
3130 The way we do this depends on whether this is pre- or
3131 post-increment. For pre-increment, copy INCLOC to the reload
3132 register, increment it there, then save back. */
3135 if (real_in
!= result
)
3136 emit_insn (gen_move_insn (result
, real_in
));
3138 emit_insn (gen_add2_insn (result
, inc
));
3140 emit_insn (gen_sub2_insn (result
, inc
));
3141 if (result
!= incloc
)
3142 emit_insn (gen_move_insn (incloc
, result
));
3148 Because this might be a jump insn or a compare, and because
3149 RESULT may not be available after the insn in an input
3150 reload, we must do the incrementing before the insn being
3153 We have already copied IN to RESULT. Increment the copy in
3154 RESULT, save that back, then decrement RESULT so it has
3155 the original value. */
3157 emit_insn (gen_add2_insn (result
, inc
));
3159 emit_insn (gen_sub2_insn (result
, inc
));
3160 emit_insn (gen_move_insn (incloc
, result
));
3161 /* Restore non-modified value for the result. We prefer this
3162 way because it does not require an additional hard
3166 if (CONST_INT_P (inc
))
3167 emit_insn (gen_add2_insn (result
,
3168 gen_int_mode (-INTVAL (inc
),
3169 GET_MODE (result
))));
3171 emit_insn (gen_sub2_insn (result
, inc
));
3174 emit_insn (gen_add2_insn (result
, inc
));
3179 /* Return true if the current move insn does not need processing as we
3180 already know that it satisfies its constraints. */
3182 simple_move_p (void)
3185 enum reg_class dclass
, sclass
;
3187 lra_assert (curr_insn_set
!= NULL_RTX
);
3188 dest
= SET_DEST (curr_insn_set
);
3189 src
= SET_SRC (curr_insn_set
);
3190 return ((dclass
= get_op_class (dest
)) != NO_REGS
3191 && (sclass
= get_op_class (src
)) != NO_REGS
3192 /* The backend guarantees that register moves of cost 2
3193 never need reloads. */
3194 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3197 /* Swap operands NOP and NOP + 1. */
3199 swap_operands (int nop
)
3201 machine_mode mode
= curr_operand_mode
[nop
];
3202 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3203 curr_operand_mode
[nop
+ 1] = mode
;
3204 rtx x
= *curr_id
->operand_loc
[nop
];
3205 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3206 *curr_id
->operand_loc
[nop
+ 1] = x
;
3207 /* Swap the duplicates too. */
3208 lra_update_dup (curr_id
, nop
);
3209 lra_update_dup (curr_id
, nop
+ 1);
3212 /* Main entry point of the constraint code: search the body of the
3213 current insn to choose the best alternative. It is mimicking insn
3214 alternative cost calculation model of former reload pass. That is
3215 because machine descriptions were written to use this model. This
3216 model can be changed in future. Make commutative operand exchange
3219 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3220 constraints. Return true if any change happened during function
3223 If CHECK_ONLY_P is true then don't do any transformation. Just
3224 check that the insn satisfies all constraints. If the insn does
3225 not satisfy any constraint, return true. */
3227 curr_insn_transform (bool check_only_p
)
3233 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3234 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3235 rtx_insn
*before
, *after
;
3237 /* Flag that the insn has been changed through a transformation. */
3240 #ifdef SECONDARY_MEMORY_NEEDED
3243 int max_regno_before
;
3244 int reused_alternative_num
;
3246 curr_insn_set
= single_set (curr_insn
);
3247 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3250 no_input_reloads_p
= no_output_reloads_p
= false;
3251 goal_alt_number
= -1;
3252 change_p
= sec_mem_p
= false;
3253 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3254 reloads; neither are insns that SET cc0. Insns that use CC0 are
3255 not allowed to have any input reloads. */
3256 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3257 no_output_reloads_p
= true;
3260 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3261 no_input_reloads_p
= true;
3262 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3263 no_output_reloads_p
= true;
3266 n_operands
= curr_static_id
->n_operands
;
3267 n_alternatives
= curr_static_id
->n_alternatives
;
3269 /* Just return "no reloads" if insn has no operands with
3271 if (n_operands
== 0 || n_alternatives
== 0)
3274 max_regno_before
= max_reg_num ();
3276 for (i
= 0; i
< n_operands
; i
++)
3278 goal_alt_matched
[i
][0] = -1;
3279 goal_alt_matches
[i
] = -1;
3282 commutative
= curr_static_id
->commutative
;
3284 /* Now see what we need for pseudos that didn't get hard regs or got
3285 the wrong kind of hard reg. For this, we must consider all the
3286 operands together against the register constraints. */
3288 best_losers
= best_overall
= INT_MAX
;
3289 best_reload_sum
= 0;
3291 curr_swapped
= false;
3292 goal_alt_swapped
= false;
3295 /* Make equivalence substitution and memory subreg elimination
3296 before address processing because an address legitimacy can
3297 depend on memory mode. */
3298 for (i
= 0; i
< n_operands
; i
++)
3300 rtx op
= *curr_id
->operand_loc
[i
];
3301 rtx subst
, old
= op
;
3302 bool op_change_p
= false;
3304 if (GET_CODE (old
) == SUBREG
)
3305 old
= SUBREG_REG (old
);
3306 subst
= get_equiv_with_elimination (old
, curr_insn
);
3309 subst
= copy_rtx (subst
);
3310 lra_assert (REG_P (old
));
3311 if (GET_CODE (op
) == SUBREG
)
3312 SUBREG_REG (op
) = subst
;
3314 *curr_id
->operand_loc
[i
] = subst
;
3315 if (lra_dump_file
!= NULL
)
3317 fprintf (lra_dump_file
,
3318 "Changing pseudo %d in operand %i of insn %u on equiv ",
3319 REGNO (old
), i
, INSN_UID (curr_insn
));
3320 dump_value_slim (lra_dump_file
, subst
, 1);
3321 fprintf (lra_dump_file
, "\n");
3323 op_change_p
= change_p
= true;
3325 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3328 lra_update_dup (curr_id
, i
);
3332 /* Reload address registers and displacements. We do it before
3333 finding an alternative because of memory constraints. */
3334 before
= after
= NULL
;
3335 for (i
= 0; i
< n_operands
; i
++)
3336 if (! curr_static_id
->operand
[i
].is_operator
3337 && process_address (i
, check_only_p
, &before
, &after
))
3342 lra_update_dup (curr_id
, i
);
3346 /* If we've changed the instruction then any alternative that
3347 we chose previously may no longer be valid. */
3348 lra_set_used_insn_alternative (curr_insn
, -1);
3350 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3351 && check_and_process_move (&change_p
, &sec_mem_p
))
3356 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3357 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3358 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3359 reused_alternative_num
, INSN_UID (curr_insn
));
3361 if (process_alt_operands (reused_alternative_num
))
3365 return ! alt_p
|| best_losers
!= 0;
3367 /* If insn is commutative (it's safe to exchange a certain pair of
3368 operands) then we need to try each alternative twice, the second
3369 time matching those two operands as if we had exchanged them. To
3370 do this, really exchange them in operands.
3372 If we have just tried the alternatives the second time, return
3373 operands to normal and drop through. */
3375 if (reused_alternative_num
< 0 && commutative
>= 0)
3377 curr_swapped
= !curr_swapped
;
3380 swap_operands (commutative
);
3384 swap_operands (commutative
);
3387 if (! alt_p
&& ! sec_mem_p
)
3389 /* No alternative works with reloads?? */
3390 if (INSN_CODE (curr_insn
) >= 0)
3391 fatal_insn ("unable to generate reloads for:", curr_insn
);
3392 error_for_asm (curr_insn
,
3393 "inconsistent operand constraints in an %<asm%>");
3394 /* Avoid further trouble with this insn. */
3395 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3396 lra_invalidate_insn_data (curr_insn
);
3400 /* If the best alternative is with operands 1 and 2 swapped, swap
3401 them. Update the operand numbers of any reloads already
3404 if (goal_alt_swapped
)
3406 if (lra_dump_file
!= NULL
)
3407 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3408 INSN_UID (curr_insn
));
3410 /* Swap the duplicates too. */
3411 swap_operands (commutative
);
3415 #ifdef SECONDARY_MEMORY_NEEDED
3416 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3417 too conservatively. So we use the secondary memory only if there
3418 is no any alternative without reloads. */
3419 use_sec_mem_p
= false;
3421 use_sec_mem_p
= true;
3424 for (i
= 0; i
< n_operands
; i
++)
3425 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3427 use_sec_mem_p
= i
< n_operands
;
3432 rtx new_reg
, src
, dest
, rld
;
3433 machine_mode sec_mode
, rld_mode
;
3435 lra_assert (sec_mem_p
);
3436 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3437 && curr_static_id
->operand
[1].type
== OP_IN
);
3438 dest
= *curr_id
->operand_loc
[0];
3439 src
= *curr_id
->operand_loc
[1];
3440 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3442 rld_mode
= GET_MODE (rld
);
3443 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3444 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3446 sec_mode
= rld_mode
;
3448 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3449 NO_REGS
, "secondary");
3450 /* If the mode is changed, it should be wider. */
3451 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3452 if (sec_mode
!= rld_mode
)
3454 /* If the target says specifically to use another mode for
3455 secondary memory moves we can not reuse the original
3457 after
= emit_spill_move (false, new_reg
, dest
);
3458 lra_process_new_insns (curr_insn
, NULL
, after
,
3459 "Inserting the sec. move");
3460 /* We may have non null BEFORE here (e.g. after address
3462 push_to_sequence (before
);
3463 before
= emit_spill_move (true, new_reg
, src
);
3465 before
= get_insns ();
3467 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3468 lra_set_insn_deleted (curr_insn
);
3470 else if (dest
== rld
)
3472 *curr_id
->operand_loc
[0] = new_reg
;
3473 after
= emit_spill_move (false, new_reg
, dest
);
3474 lra_process_new_insns (curr_insn
, NULL
, after
,
3475 "Inserting the sec. move");
3479 *curr_id
->operand_loc
[1] = new_reg
;
3480 /* See comments above. */
3481 push_to_sequence (before
);
3482 before
= emit_spill_move (true, new_reg
, src
);
3484 before
= get_insns ();
3486 lra_process_new_insns (curr_insn
, before
, NULL
,
3487 "Inserting the sec. move");
3489 lra_update_insn_regno_info (curr_insn
);
3494 lra_assert (goal_alt_number
>= 0);
3495 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3497 if (lra_dump_file
!= NULL
)
3501 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3502 goal_alt_number
, INSN_UID (curr_insn
));
3503 for (i
= 0; i
< n_operands
; i
++)
3505 p
= (curr_static_id
->operand_alternative
3506 [goal_alt_number
* n_operands
+ i
].constraint
);
3509 fprintf (lra_dump_file
, " (%d) ", i
);
3510 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3511 fputc (*p
, lra_dump_file
);
3513 if (INSN_CODE (curr_insn
) >= 0
3514 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3515 fprintf (lra_dump_file
, " {%s}", p
);
3516 if (curr_id
->sp_offset
!= 0)
3517 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3518 curr_id
->sp_offset
);
3519 fprintf (lra_dump_file
, "\n");
3522 /* Right now, for any pair of operands I and J that are required to
3523 match, with J < I, goal_alt_matches[I] is J. Add I to
3524 goal_alt_matched[J]. */
3526 for (i
= 0; i
< n_operands
; i
++)
3527 if ((j
= goal_alt_matches
[i
]) >= 0)
3529 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3531 /* We allow matching one output operand and several input
3534 || (curr_static_id
->operand
[j
].type
== OP_OUT
3535 && curr_static_id
->operand
[i
].type
== OP_IN
3536 && (curr_static_id
->operand
3537 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3538 goal_alt_matched
[j
][k
] = i
;
3539 goal_alt_matched
[j
][k
+ 1] = -1;
3542 for (i
= 0; i
< n_operands
; i
++)
3543 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3545 /* Any constants that aren't allowed and can't be reloaded into
3546 registers are here changed into memory references. */
3547 for (i
= 0; i
< n_operands
; i
++)
3548 if (goal_alt_win
[i
])
3551 enum reg_class new_class
;
3552 rtx reg
= *curr_id
->operand_loc
[i
];
3554 if (GET_CODE (reg
) == SUBREG
)
3555 reg
= SUBREG_REG (reg
);
3557 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3559 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3561 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3564 lra_change_class (regno
, new_class
, " Change to", true);
3570 const char *constraint
;
3572 rtx op
= *curr_id
->operand_loc
[i
];
3573 rtx subreg
= NULL_RTX
;
3574 machine_mode mode
= curr_operand_mode
[i
];
3576 if (GET_CODE (op
) == SUBREG
)
3579 op
= SUBREG_REG (op
);
3580 mode
= GET_MODE (op
);
3583 if (CONST_POOL_OK_P (mode
, op
)
3584 && ((targetm
.preferred_reload_class
3585 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3586 || no_input_reloads_p
))
3588 rtx tem
= force_const_mem (mode
, op
);
3591 if (subreg
!= NULL_RTX
)
3592 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3594 *curr_id
->operand_loc
[i
] = tem
;
3595 lra_update_dup (curr_id
, i
);
3596 process_address (i
, false, &before
, &after
);
3598 /* If the alternative accepts constant pool refs directly
3599 there will be no reload needed at all. */
3600 if (subreg
!= NULL_RTX
)
3602 /* Skip alternatives before the one requested. */
3603 constraint
= (curr_static_id
->operand_alternative
3604 [goal_alt_number
* n_operands
+ i
].constraint
);
3606 (c
= *constraint
) && c
!= ',' && c
!= '#';
3607 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3609 enum constraint_num cn
= lookup_constraint (constraint
);
3610 if (insn_extra_memory_constraint (cn
)
3611 && satisfies_memory_constraint_p (tem
, cn
))
3614 if (c
== '\0' || c
== ',' || c
== '#')
3617 goal_alt_win
[i
] = true;
3621 for (i
= 0; i
< n_operands
; i
++)
3624 bool optional_p
= false;
3626 rtx op
= *curr_id
->operand_loc
[i
];
3628 if (goal_alt_win
[i
])
3630 if (goal_alt
[i
] == NO_REGS
3632 /* When we assign NO_REGS it means that we will not
3633 assign a hard register to the scratch pseudo by
3634 assigment pass and the scratch pseudo will be
3635 spilled. Spilled scratch pseudos are transformed
3636 back to scratches at the LRA end. */
3637 && lra_former_scratch_operand_p (curr_insn
, i
))
3639 int regno
= REGNO (op
);
3640 lra_change_class (regno
, NO_REGS
, " Change to", true);
3641 if (lra_get_regno_hard_regno (regno
) >= 0)
3642 /* We don't have to mark all insn affected by the
3643 spilled pseudo as there is only one such insn, the
3645 reg_renumber
[regno
] = -1;
3647 /* We can do an optional reload. If the pseudo got a hard
3648 reg, we might improve the code through inheritance. If
3649 it does not get a hard register we coalesce memory/memory
3650 moves later. Ignore move insns to avoid cycling. */
3652 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3653 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3654 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3655 && regno
< new_regno_start
3656 && ! lra_former_scratch_p (regno
)
3657 && reg_renumber
[regno
] < 0
3658 && (curr_insn_set
== NULL_RTX
3659 || !((REG_P (SET_SRC (curr_insn_set
))
3660 || MEM_P (SET_SRC (curr_insn_set
))
3661 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3662 && (REG_P (SET_DEST (curr_insn_set
))
3663 || MEM_P (SET_DEST (curr_insn_set
))
3664 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3670 /* Operands that match previous ones have already been handled. */
3671 if (goal_alt_matches
[i
] >= 0)
3674 /* We should not have an operand with a non-offsettable address
3675 appearing where an offsettable address will do. It also may
3676 be a case when the address should be special in other words
3677 not a general one (e.g. it needs no index reg). */
3678 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3680 enum reg_class rclass
;
3681 rtx
*loc
= &XEXP (op
, 0);
3682 enum rtx_code code
= GET_CODE (*loc
);
3684 push_to_sequence (before
);
3685 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3687 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3688 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3689 /* This value does not matter for MODIFY. */
3690 GET_MODE_SIZE (GET_MODE (op
)));
3691 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3692 "offsetable address", &new_reg
))
3693 lra_emit_move (new_reg
, *loc
);
3694 before
= get_insns ();
3697 lra_update_dup (curr_id
, i
);
3699 else if (goal_alt_matched
[i
][0] == -1)
3703 int hard_regno
, byte
;
3704 enum op_type type
= curr_static_id
->operand
[i
].type
;
3706 loc
= curr_id
->operand_loc
[i
];
3707 mode
= curr_operand_mode
[i
];
3708 if (GET_CODE (*loc
) == SUBREG
)
3710 reg
= SUBREG_REG (*loc
);
3711 byte
= SUBREG_BYTE (*loc
);
3713 /* Strict_low_part requires reload the register not
3714 the sub-register. */
3715 && (curr_static_id
->operand
[i
].strict_low
3716 || (GET_MODE_SIZE (mode
)
3717 <= GET_MODE_SIZE (GET_MODE (reg
))
3719 = get_try_hard_regno (REGNO (reg
))) >= 0
3720 && (simplify_subreg_regno
3722 GET_MODE (reg
), byte
, mode
) < 0)
3723 && (goal_alt
[i
] == NO_REGS
3724 || (simplify_subreg_regno
3725 (ira_class_hard_regs
[goal_alt
[i
]][0],
3726 GET_MODE (reg
), byte
, mode
) >= 0)))))
3728 loc
= &SUBREG_REG (*loc
);
3729 mode
= GET_MODE (*loc
);
3733 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3734 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3737 push_to_sequence (before
);
3738 lra_emit_move (new_reg
, old
);
3739 before
= get_insns ();
3744 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3747 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3749 after
= get_insns ();
3753 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3754 if (goal_alt_dont_inherit_ops
[j
] == i
)
3756 lra_set_regno_unique_value (REGNO (new_reg
));
3759 lra_update_dup (curr_id
, i
);
3761 else if (curr_static_id
->operand
[i
].type
== OP_IN
3762 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3765 /* generate reloads for input and matched outputs. */
3766 match_inputs
[0] = i
;
3767 match_inputs
[1] = -1;
3768 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3769 goal_alt
[i
], &before
, &after
);
3771 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3772 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3774 /* Generate reloads for output and matched inputs. */
3775 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3776 else if (curr_static_id
->operand
[i
].type
== OP_IN
3777 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3780 /* Generate reloads for matched inputs. */
3781 match_inputs
[0] = i
;
3782 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3783 match_inputs
[j
+ 1] = k
;
3784 match_inputs
[j
+ 1] = -1;
3785 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3788 /* We must generate code in any case when function
3789 process_alt_operands decides that it is possible. */
3793 lra_assert (REG_P (op
));
3795 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3796 if (GET_CODE (op
) == SUBREG
)
3797 op
= SUBREG_REG (op
);
3798 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3799 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3800 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3801 if (lra_dump_file
!= NULL
)
3802 fprintf (lra_dump_file
,
3803 " Making reload reg %d for reg %d optional\n",
3807 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3808 || max_regno_before
!= max_reg_num ())
3812 lra_update_operator_dups (curr_id
);
3813 /* Something changes -- process the insn. */
3814 lra_update_insn_regno_info (curr_insn
);
3816 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3820 /* Return true if INSN satisfies all constraints. In other words, no
3821 reload insns are needed. */
3823 lra_constrain_insn (rtx_insn
*insn
)
3825 int saved_new_regno_start
= new_regno_start
;
3826 int saved_new_insn_uid_start
= new_insn_uid_start
;
3830 curr_id
= lra_get_insn_recog_data (curr_insn
);
3831 curr_static_id
= curr_id
->insn_static_data
;
3832 new_insn_uid_start
= get_max_uid ();
3833 new_regno_start
= max_reg_num ();
3834 change_p
= curr_insn_transform (true);
3835 new_regno_start
= saved_new_regno_start
;
3836 new_insn_uid_start
= saved_new_insn_uid_start
;
3840 /* Return true if X is in LIST. */
3842 in_list_p (rtx x
, rtx list
)
3844 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3845 if (XEXP (list
, 0) == x
)
3850 /* Return true if X contains an allocatable hard register (if
3851 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3853 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3859 code
= GET_CODE (x
);
3862 int regno
= REGNO (x
);
3863 HARD_REG_SET alloc_regs
;
3867 if (regno
>= FIRST_PSEUDO_REGISTER
)
3868 regno
= lra_get_regno_hard_regno (regno
);
3871 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3872 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3876 if (regno
< FIRST_PSEUDO_REGISTER
)
3880 return lra_get_regno_hard_regno (regno
) < 0;
3883 fmt
= GET_RTX_FORMAT (code
);
3884 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3888 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3891 else if (fmt
[i
] == 'E')
3893 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3894 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3901 /* Return true if X contains a symbol reg. */
3903 contains_symbol_ref_p (rtx x
)
3909 code
= GET_CODE (x
);
3910 if (code
== SYMBOL_REF
)
3912 fmt
= GET_RTX_FORMAT (code
);
3913 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3917 if (contains_symbol_ref_p (XEXP (x
, i
)))
3920 else if (fmt
[i
] == 'E')
3922 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3923 if (contains_symbol_ref_p (XVECEXP (x
, i
, j
)))
3930 /* Process all regs in location *LOC and change them on equivalent
3931 substitution. Return true if any change was done. */
3933 loc_equivalence_change_p (rtx
*loc
)
3935 rtx subst
, reg
, x
= *loc
;
3936 bool result
= false;
3937 enum rtx_code code
= GET_CODE (x
);
3943 reg
= SUBREG_REG (x
);
3944 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3945 && GET_MODE (subst
) == VOIDmode
)
3947 /* We cannot reload debug location. Simplify subreg here
3948 while we know the inner mode. */
3949 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3950 GET_MODE (reg
), SUBREG_BYTE (x
));
3954 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3960 /* Scan all the operand sub-expressions. */
3961 fmt
= GET_RTX_FORMAT (code
);
3962 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3965 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3966 else if (fmt
[i
] == 'E')
3967 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3969 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3974 /* Similar to loc_equivalence_change_p, but for use as
3975 simplify_replace_fn_rtx callback. DATA is insn for which the
3976 elimination is done. If it null we don't do the elimination. */
3978 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3983 rtx subst
= (data
== NULL
3984 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
3991 /* Maximum number of generated reload insns per an insn. It is for
3992 preventing this pass cycling in a bug case. */
3993 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3995 /* The current iteration number of this LRA pass. */
3996 int lra_constraint_iter
;
3998 /* True if we substituted equiv which needs checking register
3999 allocation correctness because the equivalent value contains
4000 allocatable hard registers or when we restore multi-register
4002 bool lra_risky_transformations_p
;
4004 /* Return true if REGNO is referenced in more than one block. */
4006 multi_block_pseudo_p (int regno
)
4008 basic_block bb
= NULL
;
4012 if (regno
< FIRST_PSEUDO_REGISTER
)
4015 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4017 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4018 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4023 /* Return true if LIST contains a deleted insn. */
4025 contains_deleted_insn_p (rtx_insn_list
*list
)
4027 for (; list
!= NULL_RTX
; list
= list
->next ())
4028 if (NOTE_P (list
->insn ())
4029 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4034 /* Return true if X contains a pseudo dying in INSN. */
4036 dead_pseudo_p (rtx x
, rtx insn
)
4043 return (insn
!= NULL_RTX
4044 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4045 code
= GET_CODE (x
);
4046 fmt
= GET_RTX_FORMAT (code
);
4047 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4051 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4054 else if (fmt
[i
] == 'E')
4056 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4057 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4064 /* Return true if INSN contains a dying pseudo in INSN right hand
4067 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4069 rtx set
= single_set (insn
);
4071 gcc_assert (set
!= NULL
);
4072 return dead_pseudo_p (SET_SRC (set
), insn
);
4075 /* Return true if any init insn of REGNO contains a dying pseudo in
4076 insn right hand side. */
4078 init_insn_rhs_dead_pseudo_p (int regno
)
4080 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4084 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4085 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4090 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4091 reverse only if we have one init insn with given REGNO as a
4094 reverse_equiv_p (int regno
)
4096 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4101 if (! INSN_P (insns
->insn ())
4102 || insns
->next () != NULL
)
4104 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4106 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4109 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4110 call this function only for non-reverse equivalence. */
4112 contains_reloaded_insn_p (int regno
)
4115 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4117 for (; list
!= NULL
; list
= list
->next ())
4118 if ((set
= single_set (list
->insn ())) == NULL_RTX
4119 || ! REG_P (SET_DEST (set
))
4120 || (int) REGNO (SET_DEST (set
)) != regno
)
4125 /* Entry function of LRA constraint pass. Return true if the
4126 constraint pass did change the code. */
4128 lra_constraints (bool first_p
)
4131 int i
, hard_regno
, new_insns_num
;
4132 unsigned int min_len
, new_min_len
, uid
;
4133 rtx set
, x
, reg
, dest_reg
;
4134 basic_block last_bb
;
4135 bitmap_head equiv_insn_bitmap
;
4138 lra_constraint_iter
++;
4139 if (lra_dump_file
!= NULL
)
4140 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4141 lra_constraint_iter
);
4143 if (pic_offset_table_rtx
4144 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4145 lra_risky_transformations_p
= true;
4147 lra_risky_transformations_p
= false;
4148 new_insn_uid_start
= get_max_uid ();
4149 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4150 /* Mark used hard regs for target stack size calulations. */
4151 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4152 if (lra_reg_info
[i
].nrefs
!= 0
4153 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4157 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4158 for (j
= 0; j
< nregs
; j
++)
4159 df_set_regs_ever_live (hard_regno
+ j
, true);
4161 /* Do elimination before the equivalence processing as we can spill
4162 some pseudos during elimination. */
4163 lra_eliminate (false, first_p
);
4164 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4165 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4166 if (lra_reg_info
[i
].nrefs
!= 0)
4168 ira_reg_equiv
[i
].profitable_p
= true;
4169 reg
= regno_reg_rtx
[i
];
4170 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4172 bool pseudo_p
= contains_reg_p (x
, false, false);
4174 /* After RTL transformation, we can not guarantee that
4175 pseudo in the substitution was not reloaded which might
4176 make equivalence invalid. For example, in reverse
4183 the memory address register was reloaded before the 2nd
4185 if ((! first_p
&& pseudo_p
)
4186 /* We don't use DF for compilation speed sake. So it
4187 is problematic to update live info when we use an
4188 equivalence containing pseudos in more than one
4190 || (pseudo_p
&& multi_block_pseudo_p (i
))
4191 /* If an init insn was deleted for some reason, cancel
4192 the equiv. We could update the equiv insns after
4193 transformations including an equiv insn deletion
4194 but it is not worthy as such cases are extremely
4196 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4197 /* If it is not a reverse equivalence, we check that a
4198 pseudo in rhs of the init insn is not dying in the
4199 insn. Otherwise, the live info at the beginning of
4200 the corresponding BB might be wrong after we
4201 removed the insn. When the equiv can be a
4202 constant, the right hand side of the init insn can
4204 || (! reverse_equiv_p (i
)
4205 && (init_insn_rhs_dead_pseudo_p (i
)
4206 /* If we reloaded the pseudo in an equivalence
4207 init insn, we can not remove the equiv init
4208 insns and the init insns might write into
4209 const memory in this case. */
4210 || contains_reloaded_insn_p (i
)))
4211 /* Prevent access beyond equivalent memory for
4212 paradoxical subregs. */
4214 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4215 > GET_MODE_SIZE (GET_MODE (x
))))
4216 || (pic_offset_table_rtx
4217 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4218 && (targetm
.preferred_reload_class
4219 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4220 || contains_symbol_ref_p (x
))))
4221 ira_reg_equiv
[i
].defined_p
= false;
4222 if (contains_reg_p (x
, false, true))
4223 ira_reg_equiv
[i
].profitable_p
= false;
4224 if (get_equiv (reg
) != reg
)
4225 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4228 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4230 /* We should add all insns containing pseudos which should be
4231 substituted by their equivalences. */
4232 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4233 lra_push_insn_by_uid (uid
);
4234 min_len
= lra_insn_stack_length ();
4238 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4240 curr_insn
= lra_pop_insn ();
4242 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4243 if (curr_bb
!= last_bb
)
4246 bb_reload_num
= lra_curr_reload_num
;
4248 if (min_len
> new_min_len
)
4250 min_len
= new_min_len
;
4253 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4255 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4256 MAX_RELOAD_INSNS_NUMBER
);
4258 if (DEBUG_INSN_P (curr_insn
))
4260 /* We need to check equivalence in debug insn and change
4261 pseudo to the equivalent value if necessary. */
4262 curr_id
= lra_get_insn_recog_data (curr_insn
);
4263 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4265 rtx old
= *curr_id
->operand_loc
[0];
4266 *curr_id
->operand_loc
[0]
4267 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4268 loc_equivalence_callback
, curr_insn
);
4269 if (old
!= *curr_id
->operand_loc
[0])
4271 lra_update_insn_regno_info (curr_insn
);
4276 else if (INSN_P (curr_insn
))
4278 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4280 dest_reg
= SET_DEST (set
);
4281 /* The equivalence pseudo could be set up as SUBREG in a
4282 case when it is a call restore insn in a mode
4283 different from the pseudo mode. */
4284 if (GET_CODE (dest_reg
) == SUBREG
)
4285 dest_reg
= SUBREG_REG (dest_reg
);
4286 if ((REG_P (dest_reg
)
4287 && (x
= get_equiv (dest_reg
)) != dest_reg
4288 /* Remove insns which set up a pseudo whose value
4289 can not be changed. Such insns might be not in
4290 init_insns because we don't update equiv data
4291 during insn transformations.
4293 As an example, let suppose that a pseudo got
4294 hard register and on the 1st pass was not
4295 changed to equivalent constant. We generate an
4296 additional insn setting up the pseudo because of
4297 secondary memory movement. Then the pseudo is
4298 spilled and we use the equiv constant. In this
4299 case we should remove the additional insn and
4300 this insn is not init_insns list. */
4301 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4302 /* Check that this is actually an insn setting
4303 up the equivalence. */
4304 || in_list_p (curr_insn
,
4306 [REGNO (dest_reg
)].init_insns
)))
4307 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4308 && in_list_p (curr_insn
,
4310 [REGNO (SET_SRC (set
))].init_insns
)))
4312 /* This is equiv init insn of pseudo which did not get a
4313 hard register -- remove the insn. */
4314 if (lra_dump_file
!= NULL
)
4316 fprintf (lra_dump_file
,
4317 " Removing equiv init insn %i (freq=%d)\n",
4318 INSN_UID (curr_insn
),
4319 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4320 dump_insn_slim (lra_dump_file
, curr_insn
);
4322 if (contains_reg_p (x
, true, false))
4323 lra_risky_transformations_p
= true;
4324 lra_set_insn_deleted (curr_insn
);
4328 curr_id
= lra_get_insn_recog_data (curr_insn
);
4329 curr_static_id
= curr_id
->insn_static_data
;
4330 init_curr_insn_input_reloads ();
4331 init_curr_operand_mode ();
4332 if (curr_insn_transform (false))
4334 /* Check non-transformed insns too for equiv change as USE
4335 or CLOBBER don't need reloads but can contain pseudos
4336 being changed on their equivalences. */
4337 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4338 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4340 lra_update_insn_regno_info (curr_insn
);
4345 bitmap_clear (&equiv_insn_bitmap
);
4346 /* If we used a new hard regno, changed_p should be true because the
4347 hard reg is assigned to a new pseudo. */
4348 #ifdef ENABLE_CHECKING
4351 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4352 if (lra_reg_info
[i
].nrefs
!= 0
4353 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4355 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4357 for (j
= 0; j
< nregs
; j
++)
4358 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4365 /* Initiate the LRA constraint pass. It is done once per
4368 lra_constraints_init (void)
4372 /* Finalize the LRA constraint pass. It is done once per
4375 lra_constraints_finish (void)
4381 /* This page contains code to do inheritance/split
4384 /* Number of reloads passed so far in current EBB. */
4385 static int reloads_num
;
4387 /* Number of calls passed so far in current EBB. */
4388 static int calls_num
;
4390 /* Current reload pseudo check for validity of elements in
4392 static int curr_usage_insns_check
;
4394 /* Info about last usage of registers in EBB to do inheritance/split
4395 transformation. Inheritance transformation is done from a spilled
4396 pseudo and split transformations from a hard register or a pseudo
4397 assigned to a hard register. */
4400 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4401 value INSNS is valid. The insns is chain of optional debug insns
4402 and a finishing non-debug insn using the corresponding reg. The
4403 value is also used to mark the registers which are set up in the
4404 current insn. The negated insn uid is used for this. */
4406 /* Value of global reloads_num at the last insn in INSNS. */
4408 /* Value of global reloads_nums at the last insn in INSNS. */
4410 /* It can be true only for splitting. And it means that the restore
4411 insn should be put after insn given by the following member. */
4413 /* Next insns in the current EBB which use the original reg and the
4414 original reg value is not changed between the current insn and
4415 the next insns. In order words, e.g. for inheritance, if we need
4416 to use the original reg value again in the next insns we can try
4417 to use the value in a hard register from a reload insn of the
4422 /* Map: regno -> corresponding pseudo usage insns. */
4423 static struct usage_insns
*usage_insns
;
4426 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4428 usage_insns
[regno
].check
= curr_usage_insns_check
;
4429 usage_insns
[regno
].insns
= insn
;
4430 usage_insns
[regno
].reloads_num
= reloads_num
;
4431 usage_insns
[regno
].calls_num
= calls_num
;
4432 usage_insns
[regno
].after_p
= after_p
;
4435 /* The function is used to form list REGNO usages which consists of
4436 optional debug insns finished by a non-debug insn using REGNO.
4437 RELOADS_NUM is current number of reload insns processed so far. */
4439 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4441 rtx next_usage_insns
;
4443 if (usage_insns
[regno
].check
== curr_usage_insns_check
4444 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4445 && DEBUG_INSN_P (insn
))
4447 /* Check that we did not add the debug insn yet. */
4448 if (next_usage_insns
!= insn
4449 && (GET_CODE (next_usage_insns
) != INSN_LIST
4450 || XEXP (next_usage_insns
, 0) != insn
))
4451 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4454 else if (NONDEBUG_INSN_P (insn
))
4455 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4457 usage_insns
[regno
].check
= 0;
4460 /* Return first non-debug insn in list USAGE_INSNS. */
4462 skip_usage_debug_insns (rtx usage_insns
)
4466 /* Skip debug insns. */
4467 for (insn
= usage_insns
;
4468 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4469 insn
= XEXP (insn
, 1))
4471 return safe_as_a
<rtx_insn
*> (insn
);
4474 /* Return true if we need secondary memory moves for insn in
4475 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4478 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4479 rtx usage_insns ATTRIBUTE_UNUSED
)
4481 #ifndef SECONDARY_MEMORY_NEEDED
4488 if (inher_cl
== ALL_REGS
4489 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4491 lra_assert (INSN_P (insn
));
4492 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4494 dest
= SET_DEST (set
);
4497 lra_assert (inher_cl
!= NO_REGS
);
4498 cl
= get_reg_class (REGNO (dest
));
4499 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4500 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4504 /* Registers involved in inheritance/split in the current EBB
4505 (inheritance/split pseudos and original registers). */
4506 static bitmap_head check_only_regs
;
4508 /* Do inheritance transformations for insn INSN, which defines (if
4509 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4510 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4511 form as the "insns" field of usage_insns. Return true if we
4512 succeed in such transformation.
4514 The transformations look like:
4517 ... p <- i (new insn)
4519 <- ... p ... <- ... i ...
4521 ... i <- p (new insn)
4522 <- ... p ... <- ... i ...
4524 <- ... p ... <- ... i ...
4525 where p is a spilled original pseudo and i is a new inheritance pseudo.
4528 The inheritance pseudo has the smallest class of two classes CL and
4529 class of ORIGINAL REGNO. */
4531 inherit_reload_reg (bool def_p
, int original_regno
,
4532 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4534 if (optimize_function_for_size_p (cfun
))
4537 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4538 rtx original_reg
= regno_reg_rtx
[original_regno
];
4539 rtx new_reg
, usage_insn
;
4540 rtx_insn
*new_insns
;
4542 lra_assert (! usage_insns
[original_regno
].after_p
);
4543 if (lra_dump_file
!= NULL
)
4544 fprintf (lra_dump_file
,
4545 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4546 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4548 if (lra_dump_file
!= NULL
)
4550 fprintf (lra_dump_file
,
4551 " Rejecting inheritance for %d "
4552 "because of disjoint classes %s and %s\n",
4553 original_regno
, reg_class_names
[cl
],
4554 reg_class_names
[rclass
]);
4555 fprintf (lra_dump_file
,
4556 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4560 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4561 /* We don't use a subset of two classes because it can be
4562 NO_REGS. This transformation is still profitable in most
4563 cases even if the classes are not intersected as register
4564 move is probably cheaper than a memory load. */
4565 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4567 if (lra_dump_file
!= NULL
)
4568 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4569 reg_class_names
[cl
], reg_class_names
[rclass
]);
4573 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4575 /* Reject inheritance resulting in secondary memory moves.
4576 Otherwise, there is a danger in LRA cycling. Also such
4577 transformation will be unprofitable. */
4578 if (lra_dump_file
!= NULL
)
4580 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
4581 rtx set
= single_set (insn
);
4583 lra_assert (set
!= NULL_RTX
);
4585 rtx dest
= SET_DEST (set
);
4587 lra_assert (REG_P (dest
));
4588 fprintf (lra_dump_file
,
4589 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4590 "as secondary mem is needed\n",
4591 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4592 original_regno
, reg_class_names
[rclass
]);
4593 fprintf (lra_dump_file
,
4594 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4598 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4599 rclass
, "inheritance");
4602 lra_emit_move (original_reg
, new_reg
);
4604 lra_emit_move (new_reg
, original_reg
);
4605 new_insns
= get_insns ();
4607 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4609 if (lra_dump_file
!= NULL
)
4611 fprintf (lra_dump_file
,
4612 " Rejecting inheritance %d->%d "
4613 "as it results in 2 or more insns:\n",
4614 original_regno
, REGNO (new_reg
));
4615 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
4616 fprintf (lra_dump_file
,
4617 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4621 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
);
4622 lra_update_insn_regno_info (insn
);
4624 /* We now have a new usage insn for original regno. */
4625 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4626 if (lra_dump_file
!= NULL
)
4627 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4628 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4629 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4630 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4631 bitmap_set_bit (&check_only_regs
, original_regno
);
4632 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4634 lra_process_new_insns (insn
, NULL
, new_insns
,
4635 "Add original<-inheritance");
4637 lra_process_new_insns (insn
, new_insns
, NULL
,
4638 "Add inheritance<-original");
4639 while (next_usage_insns
!= NULL_RTX
)
4641 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4643 usage_insn
= next_usage_insns
;
4644 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4645 next_usage_insns
= NULL
;
4649 usage_insn
= XEXP (next_usage_insns
, 0);
4650 lra_assert (DEBUG_INSN_P (usage_insn
));
4651 next_usage_insns
= XEXP (next_usage_insns
, 1);
4653 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4654 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4655 if (lra_dump_file
!= NULL
)
4657 fprintf (lra_dump_file
,
4658 " Inheritance reuse change %d->%d (bb%d):\n",
4659 original_regno
, REGNO (new_reg
),
4660 BLOCK_FOR_INSN (usage_insn
)->index
);
4661 dump_insn_slim (lra_dump_file
, usage_insn
);
4664 if (lra_dump_file
!= NULL
)
4665 fprintf (lra_dump_file
,
4666 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4670 /* Return true if we need a caller save/restore for pseudo REGNO which
4671 was assigned to a hard register. */
4673 need_for_call_save_p (int regno
)
4675 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4676 return (usage_insns
[regno
].calls_num
< calls_num
4677 && (overlaps_hard_reg_set_p
4679 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4680 ? lra_reg_info
[regno
].actual_call_used_reg_set
4681 : call_used_reg_set
,
4682 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4683 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4684 PSEUDO_REGNO_MODE (regno
))));
4687 /* Global registers occurring in the current EBB. */
4688 static bitmap_head ebb_global_regs
;
4690 /* Return true if we need a split for hard register REGNO or pseudo
4691 REGNO which was assigned to a hard register.
4692 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4693 used for reloads since the EBB end. It is an approximation of the
4694 used hard registers in the split range. The exact value would
4695 require expensive calculations. If we were aggressive with
4696 splitting because of the approximation, the split pseudo will save
4697 the same hard register assignment and will be removed in the undo
4698 pass. We still need the approximation because too aggressive
4699 splitting would result in too inaccurate cost calculation in the
4700 assignment pass because of too many generated moves which will be
4701 probably removed in the undo pass. */
4703 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4705 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4707 lra_assert (hard_regno
>= 0);
4708 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4709 /* Don't split eliminable hard registers, otherwise we can
4710 split hard registers like hard frame pointer, which
4711 lives on BB start/end according to DF-infrastructure,
4712 when there is a pseudo assigned to the register and
4713 living in the same BB. */
4714 && (regno
>= FIRST_PSEUDO_REGISTER
4715 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4716 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4717 /* Don't split call clobbered hard regs living through
4718 calls, otherwise we might have a check problem in the
4719 assign sub-pass as in the most cases (exception is a
4720 situation when lra_risky_transformations_p value is
4721 true) the assign pass assumes that all pseudos living
4722 through calls are assigned to call saved hard regs. */
4723 && (regno
>= FIRST_PSEUDO_REGISTER
4724 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4725 || usage_insns
[regno
].calls_num
== calls_num
)
4726 /* We need at least 2 reloads to make pseudo splitting
4727 profitable. We should provide hard regno splitting in
4728 any case to solve 1st insn scheduling problem when
4729 moving hard register definition up might result in
4730 impossibility to find hard register for reload pseudo of
4731 small register class. */
4732 && (usage_insns
[regno
].reloads_num
4733 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4734 && (regno
< FIRST_PSEUDO_REGISTER
4735 /* For short living pseudos, spilling + inheritance can
4736 be considered a substitution for splitting.
4737 Therefore we do not splitting for local pseudos. It
4738 decreases also aggressiveness of splitting. The
4739 minimal number of references is chosen taking into
4740 account that for 2 references splitting has no sense
4741 as we can just spill the pseudo. */
4742 || (regno
>= FIRST_PSEUDO_REGISTER
4743 && lra_reg_info
[regno
].nrefs
> 3
4744 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4745 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4748 /* Return class for the split pseudo created from original pseudo with
4749 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4750 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4751 results in no secondary memory movements. */
4752 static enum reg_class
4753 choose_split_class (enum reg_class allocno_class
,
4754 int hard_regno ATTRIBUTE_UNUSED
,
4755 machine_mode mode ATTRIBUTE_UNUSED
)
4757 #ifndef SECONDARY_MEMORY_NEEDED
4758 return allocno_class
;
4761 enum reg_class cl
, best_cl
= NO_REGS
;
4762 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4763 = REGNO_REG_CLASS (hard_regno
);
4765 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4766 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4767 return allocno_class
;
4769 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4771 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4772 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4773 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4774 && (best_cl
== NO_REGS
4775 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4781 /* Do split transformations for insn INSN, which defines or uses
4782 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4783 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4784 "insns" field of usage_insns.
4786 The transformations look like:
4789 ... s <- p (new insn -- save)
4791 ... p <- s (new insn -- restore)
4792 <- ... p ... <- ... p ...
4794 <- ... p ... <- ... p ...
4795 ... s <- p (new insn -- save)
4797 ... p <- s (new insn -- restore)
4798 <- ... p ... <- ... p ...
4800 where p is an original pseudo got a hard register or a hard
4801 register and s is a new split pseudo. The save is put before INSN
4802 if BEFORE_P is true. Return true if we succeed in such
4805 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
4806 rtx next_usage_insns
)
4808 enum reg_class rclass
;
4810 int hard_regno
, nregs
;
4811 rtx new_reg
, usage_insn
;
4812 rtx_insn
*restore
, *save
;
4816 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4818 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4819 hard_regno
= original_regno
;
4820 call_save_p
= false;
4825 hard_regno
= reg_renumber
[original_regno
];
4826 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4827 rclass
= lra_get_allocno_class (original_regno
);
4828 original_reg
= regno_reg_rtx
[original_regno
];
4829 call_save_p
= need_for_call_save_p (original_regno
);
4831 original_reg
= regno_reg_rtx
[original_regno
];
4832 lra_assert (hard_regno
>= 0);
4833 if (lra_dump_file
!= NULL
)
4834 fprintf (lra_dump_file
,
4835 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4838 machine_mode mode
= GET_MODE (original_reg
);
4840 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4841 hard_regno_nregs
[hard_regno
][mode
],
4843 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4847 rclass
= choose_split_class (rclass
, hard_regno
,
4848 GET_MODE (original_reg
));
4849 if (rclass
== NO_REGS
)
4851 if (lra_dump_file
!= NULL
)
4853 fprintf (lra_dump_file
,
4854 " Rejecting split of %d(%s): "
4855 "no good reg class for %d(%s)\n",
4857 reg_class_names
[lra_get_allocno_class (original_regno
)],
4859 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4862 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4866 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4868 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4870 save
= emit_spill_move (true, new_reg
, original_reg
);
4871 if (NEXT_INSN (save
) != NULL_RTX
)
4873 lra_assert (! call_save_p
);
4874 if (lra_dump_file
!= NULL
)
4878 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4879 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4880 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
4881 fprintf (lra_dump_file
,
4882 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4886 restore
= emit_spill_move (false, new_reg
, original_reg
);
4887 if (NEXT_INSN (restore
) != NULL_RTX
)
4889 lra_assert (! call_save_p
);
4890 if (lra_dump_file
!= NULL
)
4892 fprintf (lra_dump_file
,
4893 " Rejecting split %d->%d "
4894 "resulting in > 2 %s restore insns:\n",
4895 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4896 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
4897 fprintf (lra_dump_file
,
4898 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4902 after_p
= usage_insns
[original_regno
].after_p
;
4903 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4904 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4905 bitmap_set_bit (&check_only_regs
, original_regno
);
4906 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4909 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4911 usage_insn
= next_usage_insns
;
4914 usage_insn
= XEXP (next_usage_insns
, 0);
4915 lra_assert (DEBUG_INSN_P (usage_insn
));
4916 next_usage_insns
= XEXP (next_usage_insns
, 1);
4917 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4918 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4919 if (lra_dump_file
!= NULL
)
4921 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4922 original_regno
, REGNO (new_reg
));
4923 dump_insn_slim (lra_dump_file
, usage_insn
);
4926 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4927 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4928 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
4929 after_p
? NULL
: restore
,
4930 after_p
? restore
: NULL
,
4932 ? "Add reg<-save" : "Add reg<-split");
4933 lra_process_new_insns (insn
, before_p
? save
: NULL
,
4934 before_p
? NULL
: save
,
4936 ? "Add save<-reg" : "Add split<-reg");
4938 /* If we are trying to split multi-register. We should check
4939 conflicts on the next assignment sub-pass. IRA can allocate on
4940 sub-register levels, LRA do this on pseudos level right now and
4941 this discrepancy may create allocation conflicts after
4943 lra_risky_transformations_p
= true;
4944 if (lra_dump_file
!= NULL
)
4945 fprintf (lra_dump_file
,
4946 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4950 /* Recognize that we need a split transformation for insn INSN, which
4951 defines or uses REGNO in its insn biggest MODE (we use it only if
4952 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4953 hard registers which might be used for reloads since the EBB end.
4954 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4955 uid before starting INSN processing. Return true if we succeed in
4956 such transformation. */
4958 split_if_necessary (int regno
, machine_mode mode
,
4959 HARD_REG_SET potential_reload_hard_regs
,
4960 bool before_p
, rtx_insn
*insn
, int max_uid
)
4964 rtx next_usage_insns
;
4966 if (regno
< FIRST_PSEUDO_REGISTER
)
4967 nregs
= hard_regno_nregs
[regno
][mode
];
4968 for (i
= 0; i
< nregs
; i
++)
4969 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4970 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4971 /* To avoid processing the register twice or more. */
4972 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4973 && INSN_UID (next_usage_insns
) < max_uid
)
4974 || (GET_CODE (next_usage_insns
) == INSN_LIST
4975 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4976 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4977 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4982 /* Check only registers living at the current program point in the
4984 static bitmap_head live_regs
;
4986 /* Update live info in EBB given by its HEAD and TAIL insns after
4987 inheritance/split transformation. The function removes dead moves
4990 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
4995 rtx_insn
*prev_insn
;
4998 basic_block last_bb
, prev_bb
, curr_bb
;
5000 struct lra_insn_reg
*reg
;
5004 last_bb
= BLOCK_FOR_INSN (tail
);
5006 for (curr_insn
= tail
;
5007 curr_insn
!= PREV_INSN (head
);
5008 curr_insn
= prev_insn
)
5010 prev_insn
= PREV_INSN (curr_insn
);
5011 /* We need to process empty blocks too. They contain
5012 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5013 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5015 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5016 if (curr_bb
!= prev_bb
)
5018 if (prev_bb
!= NULL
)
5020 /* Update df_get_live_in (prev_bb): */
5021 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5022 if (bitmap_bit_p (&live_regs
, j
))
5023 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5025 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5027 if (curr_bb
!= last_bb
)
5029 /* Update df_get_live_out (curr_bb): */
5030 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5032 live_p
= bitmap_bit_p (&live_regs
, j
);
5034 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5035 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5041 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5043 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5047 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5049 if (! NONDEBUG_INSN_P (curr_insn
))
5051 curr_id
= lra_get_insn_recog_data (curr_insn
);
5052 curr_static_id
= curr_id
->insn_static_data
;
5054 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
5055 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5056 && bitmap_bit_p (&check_only_regs
, regno
)
5057 && ! bitmap_bit_p (&live_regs
, regno
))
5059 /* See which defined values die here. */
5060 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5061 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5062 bitmap_clear_bit (&live_regs
, reg
->regno
);
5063 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5064 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5065 bitmap_clear_bit (&live_regs
, reg
->regno
);
5066 /* Mark each used value as live. */
5067 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5068 if (reg
->type
!= OP_OUT
5069 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5070 bitmap_set_bit (&live_regs
, reg
->regno
);
5071 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5072 if (reg
->type
!= OP_OUT
5073 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5074 bitmap_set_bit (&live_regs
, reg
->regno
);
5075 if (curr_id
->arg_hard_regs
!= NULL
)
5076 /* Make argument hard registers live. */
5077 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5078 if (bitmap_bit_p (&check_only_regs
, regno
))
5079 bitmap_set_bit (&live_regs
, regno
);
5080 /* It is quite important to remove dead move insns because it
5081 means removing dead store. We don't need to process them for
5085 if (lra_dump_file
!= NULL
)
5087 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5088 dump_insn_slim (lra_dump_file
, curr_insn
);
5090 lra_set_insn_deleted (curr_insn
);
5095 /* The structure describes info to do an inheritance for the current
5096 insn. We need to collect such info first before doing the
5097 transformations because the transformations change the insn
5098 internal representation. */
5101 /* Original regno. */
5103 /* Subsequent insns which can inherit original reg value. */
5107 /* Array containing all info for doing inheritance from the current
5109 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5111 /* Number elements in the previous array. */
5112 static int to_inherit_num
;
5114 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5115 structure to_inherit. */
5117 add_to_inherit (int regno
, rtx insns
)
5121 for (i
= 0; i
< to_inherit_num
; i
++)
5122 if (to_inherit
[i
].regno
== regno
)
5124 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5125 to_inherit
[to_inherit_num
].regno
= regno
;
5126 to_inherit
[to_inherit_num
++].insns
= insns
;
5129 /* Return the last non-debug insn in basic block BB, or the block begin
5132 get_last_insertion_point (basic_block bb
)
5136 FOR_BB_INSNS_REVERSE (bb
, insn
)
5137 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5142 /* Set up RES by registers living on edges FROM except the edge (FROM,
5143 TO) or by registers set up in a jump insn in BB FROM. */
5145 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5148 struct lra_insn_reg
*reg
;
5152 lra_assert (to
!= NULL
);
5154 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5156 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5157 last
= get_last_insertion_point (from
);
5158 if (! JUMP_P (last
))
5160 curr_id
= lra_get_insn_recog_data (last
);
5161 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5162 if (reg
->type
!= OP_IN
)
5163 bitmap_set_bit (res
, reg
->regno
);
5166 /* Used as a temporary results of some bitmap calculations. */
5167 static bitmap_head temp_bitmap
;
5169 /* We split for reloads of small class of hard regs. The following
5170 defines how many hard regs the class should have to be qualified as
5171 small. The code is mostly oriented to x86/x86-64 architecture
5172 where some insns need to use only specific register or pair of
5173 registers and these register can live in RTL explicitly, e.g. for
5174 parameter passing. */
5175 static const int max_small_class_regs_num
= 2;
5177 /* Do inheritance/split transformations in EBB starting with HEAD and
5178 finishing on TAIL. We process EBB insns in the reverse order.
5179 Return true if we did any inheritance/split transformation in the
5182 We should avoid excessive splitting which results in worse code
5183 because of inaccurate cost calculations for spilling new split
5184 pseudos in such case. To achieve this we do splitting only if
5185 register pressure is high in given basic block and there are reload
5186 pseudos requiring hard registers. We could do more register
5187 pressure calculations at any given program point to avoid necessary
5188 splitting even more but it is to expensive and the current approach
5189 works well enough. */
5191 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5193 int i
, src_regno
, dst_regno
, nregs
;
5194 bool change_p
, succ_p
, update_reloads_num_p
;
5195 rtx_insn
*prev_insn
, *last_insn
;
5196 rtx next_usage_insns
, set
;
5198 struct lra_insn_reg
*reg
;
5199 basic_block last_processed_bb
, curr_bb
= NULL
;
5200 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5204 bool head_p
, after_p
;
5207 curr_usage_insns_check
++;
5208 reloads_num
= calls_num
= 0;
5209 bitmap_clear (&check_only_regs
);
5210 last_processed_bb
= NULL
;
5211 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5212 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5213 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5214 /* We don't process new insns generated in the loop. */
5215 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5217 prev_insn
= PREV_INSN (curr_insn
);
5218 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5219 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5220 if (last_processed_bb
!= curr_bb
)
5222 /* We are at the end of BB. Add qualified living
5223 pseudos for potential splitting. */
5224 to_process
= df_get_live_out (curr_bb
);
5225 if (last_processed_bb
!= NULL
)
5227 /* We are somewhere in the middle of EBB. */
5228 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5230 to_process
= &temp_bitmap
;
5232 last_processed_bb
= curr_bb
;
5233 last_insn
= get_last_insertion_point (curr_bb
);
5234 after_p
= (! JUMP_P (last_insn
)
5235 && (! CALL_P (last_insn
)
5236 || (find_reg_note (last_insn
,
5237 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5238 && ! SIBLING_CALL_P (last_insn
))));
5239 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5240 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5242 if ((int) j
>= lra_constraint_new_regno_start
)
5244 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5246 if (j
< FIRST_PSEUDO_REGISTER
)
5247 SET_HARD_REG_BIT (live_hard_regs
, j
);
5249 add_to_hard_reg_set (&live_hard_regs
,
5250 PSEUDO_REGNO_MODE (j
),
5252 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5256 src_regno
= dst_regno
= -1;
5257 if (NONDEBUG_INSN_P (curr_insn
)
5258 && (set
= single_set (curr_insn
)) != NULL_RTX
5259 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5261 src_regno
= REGNO (SET_SRC (set
));
5262 dst_regno
= REGNO (SET_DEST (set
));
5264 update_reloads_num_p
= true;
5265 if (src_regno
< lra_constraint_new_regno_start
5266 && src_regno
>= FIRST_PSEUDO_REGISTER
5267 && reg_renumber
[src_regno
] < 0
5268 && dst_regno
>= lra_constraint_new_regno_start
5269 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5271 /* 'reload_pseudo <- original_pseudo'. */
5272 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5274 update_reloads_num_p
= false;
5276 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5277 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5278 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5279 curr_insn
, next_usage_insns
);
5283 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5284 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5285 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5286 reg_class_contents
[cl
]);
5288 else if (src_regno
>= lra_constraint_new_regno_start
5289 && dst_regno
< lra_constraint_new_regno_start
5290 && dst_regno
>= FIRST_PSEUDO_REGISTER
5291 && reg_renumber
[dst_regno
] < 0
5292 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5293 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5294 && (next_usage_insns
5295 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5297 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5299 update_reloads_num_p
= false;
5300 /* 'original_pseudo <- reload_pseudo'. */
5301 if (! JUMP_P (curr_insn
)
5302 && inherit_reload_reg (true, dst_regno
, cl
,
5303 curr_insn
, next_usage_insns
))
5306 usage_insns
[dst_regno
].check
= 0;
5307 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5308 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5309 reg_class_contents
[cl
]);
5311 else if (INSN_P (curr_insn
))
5314 int max_uid
= get_max_uid ();
5316 curr_id
= lra_get_insn_recog_data (curr_insn
);
5317 curr_static_id
= curr_id
->insn_static_data
;
5319 /* Process insn definitions. */
5320 for (iter
= 0; iter
< 2; iter
++)
5321 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5324 if (reg
->type
!= OP_IN
5325 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5327 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5328 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5329 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5330 && (next_usage_insns
5331 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5333 struct lra_insn_reg
*r
;
5335 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5336 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5338 /* Don't do inheritance if the pseudo is also
5339 used in the insn. */
5341 /* We can not do inheritance right now
5342 because the current insn reg info (chain
5343 regs) can change after that. */
5344 add_to_inherit (dst_regno
, next_usage_insns
);
5346 /* We can not process one reg twice here because of
5347 usage_insns invalidation. */
5348 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5349 || reg_renumber
[dst_regno
] >= 0)
5350 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5354 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5355 potential_reload_hard_regs
,
5356 false, curr_insn
, max_uid
))
5358 CLEAR_HARD_REG_SET (s
);
5359 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5360 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5362 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5363 reg_renumber
[dst_regno
]);
5364 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5366 /* We should invalidate potential inheritance or
5367 splitting for the current insn usages to the next
5368 usage insns (see code below) as the output pseudo
5370 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5371 && reg_renumber
[dst_regno
] < 0)
5372 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5373 && (dst_regno
< FIRST_PSEUDO_REGISTER
5374 || reg_renumber
[dst_regno
] >= 0)))
5376 /* Invalidate and mark definitions. */
5377 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5378 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5381 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5382 for (i
= 0; i
< nregs
; i
++)
5383 usage_insns
[dst_regno
+ i
].check
5384 = -(int) INSN_UID (curr_insn
);
5388 if (! JUMP_P (curr_insn
))
5389 for (i
= 0; i
< to_inherit_num
; i
++)
5390 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5391 ALL_REGS
, curr_insn
,
5392 to_inherit
[i
].insns
))
5394 if (CALL_P (curr_insn
))
5396 rtx cheap
, pat
, dest
;
5398 int regno
, hard_regno
;
5401 if ((cheap
= find_reg_note (curr_insn
,
5402 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5403 && ((cheap
= XEXP (cheap
, 0)), true)
5404 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5405 && (hard_regno
= reg_renumber
[regno
]) >= 0
5406 /* If there are pending saves/restores, the
5407 optimization is not worth. */
5408 && usage_insns
[regno
].calls_num
== calls_num
- 1
5409 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5411 /* Restore the pseudo from the call result as
5412 REG_RETURNED note says that the pseudo value is
5413 in the call result and the pseudo is an argument
5415 pat
= PATTERN (curr_insn
);
5416 if (GET_CODE (pat
) == PARALLEL
)
5417 pat
= XVECEXP (pat
, 0, 0);
5418 dest
= SET_DEST (pat
);
5419 /* For multiple return values dest is PARALLEL.
5420 Currently we handle only single return value case. */
5424 emit_move_insn (cheap
, copy_rtx (dest
));
5425 restore
= get_insns ();
5427 lra_process_new_insns (curr_insn
, NULL
, restore
,
5428 "Inserting call parameter restore");
5429 /* We don't need to save/restore of the pseudo from
5431 usage_insns
[regno
].calls_num
= calls_num
;
5432 bitmap_set_bit (&check_only_regs
, regno
);
5437 /* Process insn usages. */
5438 for (iter
= 0; iter
< 2; iter
++)
5439 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5442 if ((reg
->type
!= OP_OUT
5443 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5444 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5446 if (src_regno
>= FIRST_PSEUDO_REGISTER
5447 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5449 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5450 && (next_usage_insns
5451 = usage_insns
[src_regno
].insns
) != NULL_RTX
5452 && NONDEBUG_INSN_P (curr_insn
))
5453 add_to_inherit (src_regno
, next_usage_insns
);
5454 else if (usage_insns
[src_regno
].check
5455 != -(int) INSN_UID (curr_insn
))
5456 /* Add usages but only if the reg is not set up
5457 in the same insn. */
5458 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5460 else if (src_regno
< FIRST_PSEUDO_REGISTER
5461 || reg_renumber
[src_regno
] >= 0)
5464 rtx use_insn
= curr_insn
;
5466 before_p
= (JUMP_P (curr_insn
)
5467 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5468 if (NONDEBUG_INSN_P (curr_insn
)
5469 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5470 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5471 potential_reload_hard_regs
,
5472 before_p
, curr_insn
, max_uid
))
5475 lra_risky_transformations_p
= true;
5478 usage_insns
[src_regno
].check
= 0;
5480 use_insn
= PREV_INSN (curr_insn
);
5482 if (NONDEBUG_INSN_P (curr_insn
))
5484 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5485 add_to_hard_reg_set (&live_hard_regs
,
5486 reg
->biggest_mode
, src_regno
);
5488 add_to_hard_reg_set (&live_hard_regs
,
5489 PSEUDO_REGNO_MODE (src_regno
),
5490 reg_renumber
[src_regno
]);
5492 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5495 /* Process call args. */
5496 if (curr_id
->arg_hard_regs
!= NULL
)
5497 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5498 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5500 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5501 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5503 for (i
= 0; i
< to_inherit_num
; i
++)
5505 src_regno
= to_inherit
[i
].regno
;
5506 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5507 curr_insn
, to_inherit
[i
].insns
))
5510 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5513 if (update_reloads_num_p
5514 && NONDEBUG_INSN_P (curr_insn
)
5515 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5518 if ((REG_P (SET_DEST (set
))
5519 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5520 && reg_renumber
[regno
] < 0
5521 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5522 || (REG_P (SET_SRC (set
))
5523 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5524 && reg_renumber
[regno
] < 0
5525 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5527 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5529 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5530 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5531 reg_class_contents
[cl
]);
5534 /* We reached the start of the current basic block. */
5535 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5536 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5538 /* We reached the beginning of the current block -- do
5539 rest of spliting in the current BB. */
5540 to_process
= df_get_live_in (curr_bb
);
5541 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5543 /* We are somewhere in the middle of EBB. */
5544 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5545 curr_bb
, &temp_bitmap
);
5546 to_process
= &temp_bitmap
;
5549 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5551 if ((int) j
>= lra_constraint_new_regno_start
)
5553 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5554 && usage_insns
[j
].check
== curr_usage_insns_check
5555 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5557 if (need_for_split_p (potential_reload_hard_regs
, j
))
5559 if (lra_dump_file
!= NULL
&& head_p
)
5561 fprintf (lra_dump_file
,
5562 " ----------------------------------\n");
5565 if (split_reg (false, j
, bb_note (curr_bb
),
5569 usage_insns
[j
].check
= 0;
5577 /* This value affects EBB forming. If probability of edge from EBB to
5578 a BB is not greater than the following value, we don't add the BB
5580 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5582 /* Current number of inheritance/split iteration. */
5583 int lra_inheritance_iter
;
5585 /* Entry function for inheritance/split pass. */
5587 lra_inheritance (void)
5590 basic_block bb
, start_bb
;
5593 lra_inheritance_iter
++;
5594 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5596 timevar_push (TV_LRA_INHERITANCE
);
5597 if (lra_dump_file
!= NULL
)
5598 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5599 lra_inheritance_iter
);
5600 curr_usage_insns_check
= 0;
5601 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5602 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5603 usage_insns
[i
].check
= 0;
5604 bitmap_initialize (&check_only_regs
, ®_obstack
);
5605 bitmap_initialize (&live_regs
, ®_obstack
);
5606 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5607 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5608 FOR_EACH_BB_FN (bb
, cfun
)
5611 if (lra_dump_file
!= NULL
)
5612 fprintf (lra_dump_file
, "EBB");
5613 /* Form a EBB starting with BB. */
5614 bitmap_clear (&ebb_global_regs
);
5615 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5618 if (lra_dump_file
!= NULL
)
5619 fprintf (lra_dump_file
, " %d", bb
->index
);
5620 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5621 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5623 e
= find_fallthru_edge (bb
->succs
);
5626 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5630 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5631 if (lra_dump_file
!= NULL
)
5632 fprintf (lra_dump_file
, "\n");
5633 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5634 /* Remember that the EBB head and tail can change in
5636 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5638 bitmap_clear (&ebb_global_regs
);
5639 bitmap_clear (&temp_bitmap
);
5640 bitmap_clear (&live_regs
);
5641 bitmap_clear (&check_only_regs
);
5644 timevar_pop (TV_LRA_INHERITANCE
);
5649 /* This page contains code to undo failed inheritance/split
5652 /* Current number of iteration undoing inheritance/split. */
5653 int lra_undo_inheritance_iter
;
5655 /* Fix BB live info LIVE after removing pseudos created on pass doing
5656 inheritance/split which are REMOVED_PSEUDOS. */
5658 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5663 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5664 if (bitmap_clear_bit (live
, regno
))
5665 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5668 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5673 if (GET_CODE (reg
) == SUBREG
)
5674 reg
= SUBREG_REG (reg
);
5680 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5681 return true if we did any change. The undo transformations for
5682 inheritance looks like
5686 p <- i, i <- p, and i <- i3
5687 where p is original pseudo from which inheritance pseudo i was
5688 created, i and i3 are removed inheritance pseudos, i2 is another
5689 not removed inheritance pseudo. All split pseudos or other
5690 occurrences of removed inheritance pseudos are changed on the
5691 corresponding original pseudos.
5693 The function also schedules insns changed and created during
5694 inheritance/split pass for processing by the subsequent constraint
5697 remove_inheritance_pseudos (bitmap remove_pseudos
)
5700 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5702 rtx_insn
*prev_insn
;
5703 bool change_p
, done_p
;
5705 change_p
= ! bitmap_empty_p (remove_pseudos
);
5706 /* We can not finish the function right away if CHANGE_P is true
5707 because we need to marks insns affected by previous
5708 inheritance/split pass for processing by the subsequent
5710 FOR_EACH_BB_FN (bb
, cfun
)
5712 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5713 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5714 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5716 if (! INSN_P (curr_insn
))
5719 sregno
= dregno
= -1;
5720 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5721 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5723 dregno
= get_regno (SET_DEST (set
));
5724 sregno
= get_regno (SET_SRC (set
));
5727 if (sregno
>= 0 && dregno
>= 0)
5729 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5730 && (lra_reg_info
[sregno
].restore_regno
== dregno
5731 || (bitmap_bit_p (remove_pseudos
, dregno
)
5732 && (lra_reg_info
[sregno
].restore_regno
5733 == lra_reg_info
[dregno
].restore_regno
))))
5734 || (bitmap_bit_p (remove_pseudos
, dregno
)
5735 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5736 /* One of the following cases:
5737 original <- removed inheritance pseudo
5738 removed inherit pseudo <- another removed inherit pseudo
5739 removed inherit pseudo <- original pseudo
5741 removed_split_pseudo <- original_reg
5742 original_reg <- removed_split_pseudo */
5744 if (lra_dump_file
!= NULL
)
5746 fprintf (lra_dump_file
, " Removing %s:\n",
5747 bitmap_bit_p (&lra_split_regs
, sregno
)
5748 || bitmap_bit_p (&lra_split_regs
, dregno
)
5749 ? "split" : "inheritance");
5750 dump_insn_slim (lra_dump_file
, curr_insn
);
5752 lra_set_insn_deleted (curr_insn
);
5755 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5756 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5758 /* Search the following pattern:
5759 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5760 original_pseudo <- inherit_or_split_pseudo1
5761 where the 2nd insn is the current insn and
5762 inherit_or_split_pseudo2 is not removed. If it is found,
5763 change the current insn onto:
5764 original_pseudo <- inherit_or_split_pseudo2. */
5765 for (prev_insn
= PREV_INSN (curr_insn
);
5766 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5767 prev_insn
= PREV_INSN (prev_insn
))
5769 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5770 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5771 /* There should be no subregs in insn we are
5772 searching because only the original reg might
5773 be in subreg when we changed the mode of
5774 load/store for splitting. */
5775 && REG_P (SET_DEST (prev_set
))
5776 && REG_P (SET_SRC (prev_set
))
5777 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5778 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5779 >= FIRST_PSEUDO_REGISTER
)
5780 /* As we consider chain of inheritance or
5781 splitting described in above comment we should
5782 check that sregno and prev_sregno were
5783 inheritance/split pseudos created from the
5784 same original regno. */
5785 && (lra_reg_info
[sregno
].restore_regno
5786 == lra_reg_info
[prev_sregno
].restore_regno
)
5787 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5789 lra_assert (GET_MODE (SET_SRC (prev_set
))
5790 == GET_MODE (regno_reg_rtx
[sregno
]));
5791 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5792 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5794 SET_SRC (set
) = SET_SRC (prev_set
);
5795 /* As we are finishing with processing the insn
5796 here, check the destination too as it might
5797 inheritance pseudo for another pseudo. */
5798 if (bitmap_bit_p (remove_pseudos
, dregno
)
5799 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
5801 = lra_reg_info
[dregno
].restore_regno
) >= 0)
5803 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
5804 SUBREG_REG (SET_DEST (set
))
5805 = regno_reg_rtx
[restore_regno
];
5807 SET_DEST (set
) = regno_reg_rtx
[restore_regno
];
5809 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5810 lra_set_used_insn_alternative_by_uid
5811 (INSN_UID (curr_insn
), -1);
5813 if (lra_dump_file
!= NULL
)
5815 fprintf (lra_dump_file
, " Change reload insn:\n");
5816 dump_insn_slim (lra_dump_file
, curr_insn
);
5823 struct lra_insn_reg
*reg
;
5824 bool restored_regs_p
= false;
5825 bool kept_regs_p
= false;
5827 curr_id
= lra_get_insn_recog_data (curr_insn
);
5828 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5831 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5832 if (restore_regno
>= 0)
5834 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5836 lra_substitute_pseudo_within_insn (
5837 curr_insn
, regno
, regno_reg_rtx
[restore_regno
]);
5838 restored_regs_p
= true;
5844 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5846 /* The instruction has changed since the previous
5847 constraints pass. */
5848 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5849 lra_set_used_insn_alternative_by_uid
5850 (INSN_UID (curr_insn
), -1);
5852 else if (restored_regs_p
)
5853 /* The instruction has been restored to the form that
5854 it had during the previous constraints pass. */
5855 lra_update_insn_regno_info (curr_insn
);
5856 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5858 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5859 dump_insn_slim (lra_dump_file
, curr_insn
);
5867 /* If optional reload pseudos failed to get a hard register or was not
5868 inherited, it is better to remove optional reloads. We do this
5869 transformation after undoing inheritance to figure out necessity to
5870 remove optional reloads easier. Return true if we do any
5873 undo_optional_reloads (void)
5875 bool change_p
, keep_p
;
5876 unsigned int regno
, uid
;
5877 bitmap_iterator bi
, bi2
;
5880 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5882 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5883 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5884 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5887 /* Keep optional reloads from previous subpasses. */
5888 if (lra_reg_info
[regno
].restore_regno
< 0
5889 /* If the original pseudo changed its allocation, just
5890 removing the optional pseudo is dangerous as the original
5891 pseudo will have longer live range. */
5892 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5894 else if (reg_renumber
[regno
] >= 0)
5895 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5897 insn
= lra_insn_recog_data
[uid
]->insn
;
5898 if ((set
= single_set (insn
)) == NULL_RTX
)
5900 src
= SET_SRC (set
);
5901 dest
= SET_DEST (set
);
5902 if (! REG_P (src
) || ! REG_P (dest
))
5904 if (REGNO (dest
) == regno
5905 /* Ignore insn for optional reloads itself. */
5906 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5907 /* Check only inheritance on last inheritance pass. */
5908 && (int) REGNO (src
) >= new_regno_start
5909 /* Check that the optional reload was inherited. */
5910 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5918 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5919 if (lra_dump_file
!= NULL
)
5920 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5923 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5924 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5925 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5927 if (lra_dump_file
!= NULL
)
5928 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5929 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5930 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5932 insn
= lra_insn_recog_data
[uid
]->insn
;
5933 if ((set
= single_set (insn
)) != NULL_RTX
)
5935 src
= SET_SRC (set
);
5936 dest
= SET_DEST (set
);
5937 if (REG_P (src
) && REG_P (dest
)
5938 && ((REGNO (src
) == regno
5939 && (lra_reg_info
[regno
].restore_regno
5940 == (int) REGNO (dest
)))
5941 || (REGNO (dest
) == regno
5942 && (lra_reg_info
[regno
].restore_regno
5943 == (int) REGNO (src
)))))
5945 if (lra_dump_file
!= NULL
)
5947 fprintf (lra_dump_file
, " Deleting move %u\n",
5949 dump_insn_slim (lra_dump_file
, insn
);
5951 lra_set_insn_deleted (insn
);
5954 /* We should not worry about generation memory-memory
5955 moves here as if the corresponding inheritance did
5956 not work (inheritance pseudo did not get a hard reg),
5957 we remove the inheritance pseudo and the optional
5960 lra_substitute_pseudo_within_insn (
5962 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5963 lra_update_insn_regno_info (insn
);
5964 if (lra_dump_file
!= NULL
)
5966 fprintf (lra_dump_file
,
5967 " Restoring original insn:\n");
5968 dump_insn_slim (lra_dump_file
, insn
);
5972 /* Clear restore_regnos. */
5973 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5974 lra_reg_info
[regno
].restore_regno
= -1;
5975 bitmap_clear (&insn_bitmap
);
5976 bitmap_clear (&removed_optional_reload_pseudos
);
5980 /* Entry function for undoing inheritance/split transformation. Return true
5981 if we did any RTL change in this pass. */
5983 lra_undo_inheritance (void)
5986 int restore_regno
, hard_regno
;
5987 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5988 bitmap_head remove_pseudos
;
5992 lra_undo_inheritance_iter
++;
5993 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5995 if (lra_dump_file
!= NULL
)
5996 fprintf (lra_dump_file
,
5997 "\n********** Undoing inheritance #%d: **********\n\n",
5998 lra_undo_inheritance_iter
);
5999 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6000 n_inherit
= n_all_inherit
= 0;
6001 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6002 if (lra_reg_info
[regno
].restore_regno
>= 0)
6005 if (reg_renumber
[regno
] < 0
6006 /* If the original pseudo changed its allocation, just
6007 removing inheritance is dangerous as for changing
6008 allocation we used shorter live-ranges. */
6009 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
6010 bitmap_set_bit (&remove_pseudos
, regno
);
6014 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6015 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6016 n_inherit
, n_all_inherit
,
6017 (double) n_inherit
/ n_all_inherit
* 100);
6018 n_split
= n_all_split
= 0;
6019 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6020 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
6023 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6024 ? reg_renumber
[restore_regno
] : restore_regno
);
6025 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6026 bitmap_set_bit (&remove_pseudos
, regno
);
6030 if (lra_dump_file
!= NULL
)
6031 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6032 regno
, restore_regno
);
6035 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6036 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6037 n_split
, n_all_split
,
6038 (double) n_split
/ n_all_split
* 100);
6039 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6040 bitmap_clear (&remove_pseudos
);
6041 /* Clear restore_regnos. */
6042 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6043 lra_reg_info
[regno
].restore_regno
= -1;
6044 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6045 lra_reg_info
[regno
].restore_regno
= -1;
6046 change_p
= undo_optional_reloads () || change_p
;