gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrhadd.c

   1 #include <arm_neon.h>
   2 #include "arm-neon-ref.h"
   3 #include "compute-ref-data.h"
   4
   5 #define INSN_NAME vrhadd
   6 #define TEST_MSG "VRHADD/VRHADDQ"
   7
   8 /* Expected results.  */
   9 VECT_VAR_DECL(expected,int,8,8) [] = { 0xf2, 0xf2, 0xf3, 0xf3,
  10                                        0xf4, 0xf4, 0xf5, 0xf5 };
  11 VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff2, 0xfff2, 0xfff3 };
  12 VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
  13 VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf2, 0xf2, 0xf3, 0xf3,
  14                                         0xf4, 0xf4, 0xf5, 0xf5 };
  15 VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff2 };
  16 VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
  17 VECT_VAR_DECL(expected,int,8,16) [] = { 0xf2, 0xf3, 0xf3, 0xf4,
  18                                         0xf4, 0xf5, 0xf5, 0xf6,
  19                                         0xf6, 0xf7, 0xf7, 0xf8,
  20                                         0xf8, 0xf9, 0xf9, 0xfa };
  21 VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff2, 0xfff2, 0xfff3, 0xfff3,
  22                                         0xfff4, 0xfff4, 0xfff5, 0xfff5 };
  23 VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
  24                                         0xfffffff2, 0xfffffff2 };
  25 VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf5, 0xf5, 0xf6, 0xf6,
  26                                          0xf7, 0xf7, 0xf8, 0xf8,
  27                                          0xf9, 0xf9, 0xfa, 0xfa,
  28                                          0xfb, 0xfb, 0xfc, 0xfc };
  29 VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff1, 0xfff2, 0xfff2, 0xfff3,
  30                                          0xfff3, 0xfff4, 0xfff4, 0xfff5 };
  31 VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
  32                                          0xfffffff2, 0xfffffff2 };
  33
  34 #include "binary_op_no64.inc"