gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqsub.c

   1 #define INSN_NAME vqsub
   2 #define TEST_MSG "VQSUB/VQSUBQ"
   3
   4 /* Extra tests for special cases:
   5    - some requiring intermediate types larger than 64 bits to
   6    compute saturation flag.
   7    - corner case saturations with types smaller than 64 bits.
   8 */
   9 void vqsub_extras(void);
  10 #define EXTRA_TESTS vqsub_extras
  11
  12 #include "binary_sat_op.inc"
  13
  14
  15 /* Expected results.  */
  16 VECT_VAR_DECL(expected,int,8,8) [] = { 0xdf, 0xe0, 0xe1, 0xe2,
  17                                        0xe3, 0xe4, 0xe5, 0xe6 };
  18 VECT_VAR_DECL(expected,int,16,4) [] = { 0xffce, 0xffcf,
  19                                         0xffd0, 0xffd1 };
  20 VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffbd, 0xffffffbe };
  21 VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffffac };
  22 VECT_VAR_DECL(expected,uint,8,8) [] = { 0x9b, 0x9c, 0x9d, 0x9e,
  23                                         0x9f, 0xa0, 0xa1, 0xa2 };
  24 VECT_VAR_DECL(expected,uint,16,4) [] = { 0xff8a, 0xff8b,
  25                                          0xff8c, 0xff8d };
  26 VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffff79, 0xffffff7a };
  27 VECT_VAR_DECL(expected,uint,64,1) [] = { 0xffffffffffffff68 };
  28 VECT_VAR_DECL(expected,int,8,16) [] = { 0xdf, 0xe0, 0xe1, 0xe2,
  29                                         0xe3, 0xe4, 0xe5, 0xe6,
  30                                         0xe7, 0xe8, 0xe9, 0xea,
  31                                         0xeb, 0xec, 0xed, 0xee };
  32 VECT_VAR_DECL(expected,int,16,8) [] = { 0xffce, 0xffcf, 0xffd0, 0xffd1,
  33                                         0xffd2, 0xffd3, 0xffd4, 0xffd5 };
  34 VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffbd, 0xffffffbe,
  35                                         0xffffffbf, 0xffffffc0 };
  36 VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffac,
  37                                         0xffffffffffffffad };
  38 VECT_VAR_DECL(expected,uint,8,16) [] = { 0x9b, 0x9c, 0x9d, 0x9e,
  39                                          0x9f, 0xa0, 0xa1, 0xa2,
  40                                          0xa3, 0xa4, 0xa5, 0xa6,
  41                                          0xa7, 0xa8, 0xa9, 0xaa };
  42 VECT_VAR_DECL(expected,uint,16,8) [] = { 0xff8a, 0xff8b, 0xff8c, 0xff8d,
  43                                          0xff8e, 0xff8f, 0xff90, 0xff91 };
  44 VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffff79, 0xffffff7a,
  45                                          0xffffff7b, 0xffffff7c };
  46 VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffff68,
  47                                          0xffffffffffffff69 };
  48
  49 /* Expected values of cumulative saturation flag.  */
  50 int VECT_VAR(expected_cumulative_sat,int,8,8) = 0;
  51 int VECT_VAR(expected_cumulative_sat,int,16,4) = 0;
  52 int VECT_VAR(expected_cumulative_sat,int,32,2) = 0;
  53 int VECT_VAR(expected_cumulative_sat,int,64,1) = 0;
  54 int VECT_VAR(expected_cumulative_sat,uint,8,8) = 0;
  55 int VECT_VAR(expected_cumulative_sat,uint,16,4) = 0;
  56 int VECT_VAR(expected_cumulative_sat,uint,32,2) = 0;
  57 int VECT_VAR(expected_cumulative_sat,uint,64,1) = 0;
  58 int VECT_VAR(expected_cumulative_sat,int,8,16) = 0;
  59 int VECT_VAR(expected_cumulative_sat,int,16,8) = 0;
  60 int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
  61 int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
  62 int VECT_VAR(expected_cumulative_sat,uint,8,16) = 0;
  63 int VECT_VAR(expected_cumulative_sat,uint,16,8) = 0;
  64 int VECT_VAR(expected_cumulative_sat,uint,32,4) = 0;
  65 int VECT_VAR(expected_cumulative_sat,uint,64,2) = 0;
  66
  67 /* 64-bits types, with 0 as second input.  */
  68 VECT_VAR_DECL(expected_64,int,64,1) [] = { 0xfffffffffffffff0 };
  69 VECT_VAR_DECL(expected_64,uint,64,1) [] = { 0xfffffffffffffff0 };
  70 VECT_VAR_DECL(expected_64,int,64,2) [] = { 0xfffffffffffffff0,
  71                                            0xfffffffffffffff1 };
  72 VECT_VAR_DECL(expected_64,uint,64,2) [] = { 0xfffffffffffffff0,
  73                                             0xfffffffffffffff1 };
  74 int VECT_VAR(expected_cumulative_sat_64,int,64,1) = 0;
  75 int VECT_VAR(expected_cumulative_sat_64,uint,64,1) = 0;
  76 int VECT_VAR(expected_cumulative_sat_64,int,64,2) = 0;
  77 int VECT_VAR(expected_cumulative_sat_64,uint,64,2) = 0;
  78
  79 /* 64-bits types, other cases.  */
  80 VECT_VAR_DECL(expected_64_2,int,64,1) [] = { 0xffffffffffffffac };
  81 VECT_VAR_DECL(expected_64_2,uint,64,1) [] = { 0xffffffffffffff68 };
  82 VECT_VAR_DECL(expected_64_2,int,64,2) [] = { 0xffffffffffffffac,
  83                                              0xffffffffffffffad };
  84 VECT_VAR_DECL(expected_64_2,uint,64,2) [] = { 0xffffffffffffff68,
  85                                               0xffffffffffffff69 };
  86 int VECT_VAR(expected_cumulative_sat_64_2,int,64,1) = 0;
  87 int VECT_VAR(expected_cumulative_sat_64_2,uint,64,1) = 0;
  88 int VECT_VAR(expected_cumulative_sat_64_2,int,64,2) = 0;
  89 int VECT_VAR(expected_cumulative_sat_64_2,uint,64,2) = 0;
  90
  91 /* 64-bits types, all causing cumulative saturation.  */
  92 VECT_VAR_DECL(expected_64_3,int,64,1) [] = { 0x8000000000000000 };
  93 VECT_VAR_DECL(expected_64_3,uint,64,1) [] = { 0x0 };
  94 VECT_VAR_DECL(expected_64_3,int,64,2) [] = { 0x7fffffffffffffff,
  95                                              0x7fffffffffffffff };
  96 VECT_VAR_DECL(expected_64_3,uint,64,2) [] = { 0x0, 0x0 };
  97 int VECT_VAR(expected_cumulative_sat_64_3,int,64,1) = 1;
  98 int VECT_VAR(expected_cumulative_sat_64_3,uint,64,1) = 1;
  99 int VECT_VAR(expected_cumulative_sat_64_3,int,64,2) = 1;
 100 int VECT_VAR(expected_cumulative_sat_64_3,uint,64,2) = 1;
 101
 102 /* smaller types, corner cases causing cumulative saturation. (1)  */
 103 VECT_VAR_DECL(expected_lt_64_1,int,8,8) [] = { 0x80, 0x80, 0x80, 0x80,
 104                                                0x80, 0x80, 0x80, 0x80 };
 105 VECT_VAR_DECL(expected_lt_64_1,int,16,4) [] = { 0x8000, 0x8000,
 106                                                 0x8000, 0x8000 };
 107 VECT_VAR_DECL(expected_lt_64_1,int,32,2) [] = { 0x80000000, 0x80000000 };
 108 VECT_VAR_DECL(expected_lt_64_1,int,8,16) [] = { 0x80, 0x80, 0x80, 0x80,
 109                                                 0x80, 0x80, 0x80, 0x80,
 110                                                 0x80, 0x80, 0x80, 0x80,
 111                                                 0x80, 0x80, 0x80, 0x80 };
 112 VECT_VAR_DECL(expected_lt_64_1,int,16,8) [] = { 0x8000, 0x8000,
 113                                                 0x8000, 0x8000,
 114                                                 0x8000, 0x8000,
 115                                                 0x8000, 0x8000 };
 116 VECT_VAR_DECL(expected_lt_64_1,int,32,4) [] = { 0x80000000, 0x80000000,
 117                                                 0x80000000, 0x80000000 };
 118 int VECT_VAR(expected_csat_lt_64_1,int,8,8) = 1;
 119 int VECT_VAR(expected_csat_lt_64_1,int,16,4) = 1;
 120 int VECT_VAR(expected_csat_lt_64_1,int,32,2) = 1;
 121 int VECT_VAR(expected_csat_lt_64_1,int,8,16) = 1;
 122 int VECT_VAR(expected_csat_lt_64_1,int,16,8) = 1;
 123 int VECT_VAR(expected_csat_lt_64_1,int,32,4) = 1;
 124
 125 /* smaller types, corner cases causing cumulative saturation. (2)  */
 126 VECT_VAR_DECL(expected_lt_64_2,uint,8,8) [] = { 0x0, 0x0, 0x0, 0x0,
 127                                                 0x0, 0x0, 0x0, 0x0 };
 128 VECT_VAR_DECL(expected_lt_64_2,uint,16,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 129 VECT_VAR_DECL(expected_lt_64_2,uint,32,2) [] = { 0x0, 0x0 };
 130 VECT_VAR_DECL(expected_lt_64_2,uint,8,16) [] = { 0x0, 0x0, 0x0, 0x0,
 131                                                  0x0, 0x0, 0x0, 0x0,
 132                                                  0x0, 0x0, 0x0, 0x0,
 133                                                  0x0, 0x0, 0x0, 0x0 };
 134 VECT_VAR_DECL(expected_lt_64_2,uint,16,8) [] = { 0x0, 0x0, 0x0, 0x0,
 135                                                  0x0, 0x0, 0x0, 0x0 };
 136 VECT_VAR_DECL(expected_lt_64_2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
 137 int VECT_VAR(expected_csat_lt_64_2,uint,8,8) = 1;
 138 int VECT_VAR(expected_csat_lt_64_2,uint,16,4) = 1;
 139 int VECT_VAR(expected_csat_lt_64_2,uint,32,2) = 1;
 140 int VECT_VAR(expected_csat_lt_64_2,uint,8,16) = 1;
 141 int VECT_VAR(expected_csat_lt_64_2,uint,16,8) = 1;
 142 int VECT_VAR(expected_csat_lt_64_2,uint,32,4) = 1;
 143
 144 void vqsub_extras(void)
 145 {
 146   DECL_VARIABLE_ALL_VARIANTS(vector1);
 147   DECL_VARIABLE_ALL_VARIANTS(vector2);
 148   DECL_VARIABLE_ALL_VARIANTS(vector_res);
 149
 150   /* Initialize input "vector1" from "buffer".  */
 151   TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
 152
 153   /* Use a second vector full of 0.  */
 154   VDUP(vector2, , int, s, 64, 1, 0x0);
 155   VDUP(vector2, , uint, u, 64, 1, 0x0);
 156   VDUP(vector2, q, int, s, 64, 2, 0x0);
 157   VDUP(vector2, q, uint, u, 64, 2, 0x0);
 158
 159 #define MSG "64 bits saturation when adding zero"
 160   TEST_BINARY_SAT_OP(INSN_NAME, , int, s, 64, 1, expected_cumulative_sat_64, MSG);
 161   TEST_BINARY_SAT_OP(INSN_NAME, , uint, u, 64, 1, expected_cumulative_sat_64, MSG);
 162   TEST_BINARY_SAT_OP(INSN_NAME, q, int, s, 64, 2, expected_cumulative_sat_64, MSG);
 163   TEST_BINARY_SAT_OP(INSN_NAME, q, uint, u, 64, 2, expected_cumulative_sat_64, MSG);
 164
 165   CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_64, MSG);
 166   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_64, MSG);
 167   CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_64, MSG);
 168   CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_64, MSG);
 169
 170   /* Another set of tests with non-zero values.  */
 171   VDUP(vector2, , int, s, 64, 1, 0x44);
 172   VDUP(vector2, , uint, u, 64, 1, 0x88);
 173   VDUP(vector2, q, int, s, 64, 2, 0x44);
 174   VDUP(vector2, q, uint, u, 64, 2, 0x88);
 175
 176 #undef MSG
 177 #define MSG "64 bits saturation cumulative_sat (2)"
 178   TEST_BINARY_SAT_OP(INSN_NAME, , int, s, 64, 1, expected_cumulative_sat_64_2, MSG);
 179   TEST_BINARY_SAT_OP(INSN_NAME, , uint, u, 64, 1, expected_cumulative_sat_64_2, MSG);
 180   TEST_BINARY_SAT_OP(INSN_NAME, q, int, s, 64, 2, expected_cumulative_sat_64_2, MSG);
 181   TEST_BINARY_SAT_OP(INSN_NAME, q, uint, u, 64, 2, expected_cumulative_sat_64_2, MSG);
 182
 183   CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_64_2, MSG);
 184   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_64_2, MSG);
 185   CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_64_2, MSG);
 186   CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_64_2, MSG);
 187
 188   /* Another set of tests, with input values chosen to set
 189      cumulative_sat in all cases.  */
 190   VDUP(vector2, , int, s, 64, 1, 0x7fffffffffffffffLL);
 191   VDUP(vector2, , uint, u, 64, 1, 0xffffffffffffffffULL);
 192   /* To check positive saturation, we need to write a positive value
 193      in vector1.  */
 194   VDUP(vector1, q, int, s, 64, 2, 0x3fffffffffffffffLL);
 195   VDUP(vector2, q, int, s, 64, 2, 0x8000000000000000LL);
 196   VDUP(vector2, q, uint, u, 64, 2, 0xffffffffffffffffULL);
 197
 198 #undef MSG
 199 #define MSG "64 bits saturation cumulative_sat (3)"
 200   TEST_BINARY_SAT_OP(INSN_NAME, , int, s, 64, 1, expected_cumulative_sat_64_3, MSG);
 201   TEST_BINARY_SAT_OP(INSN_NAME, , uint, u, 64, 1, expected_cumulative_sat_64_3, MSG);
 202   TEST_BINARY_SAT_OP(INSN_NAME, q, int, s, 64, 2, expected_cumulative_sat_64_3, MSG);
 203   TEST_BINARY_SAT_OP(INSN_NAME, q, uint, u, 64, 2, expected_cumulative_sat_64_3, MSG);
 204
 205   CHECK(TEST_MSG, int, 64, 1, PRIx64, expected_64_3, MSG);
 206   CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected_64_3, MSG);
 207   CHECK(TEST_MSG, int, 64, 2, PRIx64, expected_64_3, MSG);
 208   CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected_64_3, MSG);
 209
 210   /* To improve coverage, check saturation with less than 64 bits
 211      too.  */
 212   VDUP(vector2, , int, s, 8, 8, 0x7F);
 213   VDUP(vector2, , int, s, 16, 4, 0x7FFF);
 214   VDUP(vector2, , int, s, 32, 2, 0x7FFFFFFF);
 215   VDUP(vector2, q, int, s, 8, 16, 0x7F);
 216   VDUP(vector2, q, int, s, 16, 8, 0x7FFF);
 217   VDUP(vector2, q, int, s, 32, 4, 0x7FFFFFFF);
 218
 219 #undef MSG
 220 #define MSG "less than 64 bits saturation cumulative_sat (1)"
 221   TEST_BINARY_SAT_OP(INSN_NAME, , int, s, 8, 8, expected_csat_lt_64_1, MSG);
 222   TEST_BINARY_SAT_OP(INSN_NAME, , int, s, 16, 4, expected_csat_lt_64_1, MSG);
 223   TEST_BINARY_SAT_OP(INSN_NAME, , int, s, 32, 2, expected_csat_lt_64_1, MSG);
 224   TEST_BINARY_SAT_OP(INSN_NAME, q, int, s, 8, 16, expected_csat_lt_64_1, MSG);
 225   TEST_BINARY_SAT_OP(INSN_NAME, q, int, s, 16, 8, expected_csat_lt_64_1, MSG);
 226   TEST_BINARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_csat_lt_64_1, MSG);
 227
 228   CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_lt_64_1, MSG);
 229   CHECK(TEST_MSG, int, 16, 4, PRIx16, expected_lt_64_1, MSG);
 230   CHECK(TEST_MSG, int, 32, 2, PRIx32, expected_lt_64_1, MSG);
 231   CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_lt_64_1, MSG);
 232   CHECK(TEST_MSG, int, 16, 8, PRIx16, expected_lt_64_1, MSG);
 233   CHECK(TEST_MSG, int, 32, 4, PRIx32, expected_lt_64_1, MSG);
 234
 235   /* Another set of tests with vector1 values smaller than
 236      vector2.  */
 237   VDUP(vector1, , uint, u, 8, 8, 0x10);
 238   VDUP(vector1, , uint, u, 16, 4, 0x10);
 239   VDUP(vector1, , uint, u, 32, 2, 0x10);
 240   VDUP(vector1, q, uint, u, 8, 16, 0x10);
 241   VDUP(vector1, q, uint, u, 16, 8, 0x10);
 242   VDUP(vector1, q, uint, u, 32, 4, 0x10);
 243
 244   VDUP(vector2, , uint, u, 8, 8, 0x20);
 245   VDUP(vector2, , uint, u, 16, 4, 0x20);
 246   VDUP(vector2, , uint, u, 32, 2, 0x20);
 247   VDUP(vector2, q, uint, u, 8, 16, 0x20);
 248   VDUP(vector2, q, uint, u, 16, 8, 0x20);
 249   VDUP(vector2, q, uint, u, 32, 4, 0x20);
 250
 251 #undef MSG
 252 #define MSG "less than 64 bits saturation cumulative_sat (2)"
 253   TEST_BINARY_SAT_OP(INSN_NAME, , uint, u, 8, 8, expected_csat_lt_64_2, MSG);
 254   TEST_BINARY_SAT_OP(INSN_NAME, , uint, u, 16, 4, expected_csat_lt_64_2, MSG);
 255   TEST_BINARY_SAT_OP(INSN_NAME, , uint, u, 32, 2, expected_csat_lt_64_2, MSG);
 256   TEST_BINARY_SAT_OP(INSN_NAME, q, uint, u, 8, 16, expected_csat_lt_64_2, MSG);
 257   TEST_BINARY_SAT_OP(INSN_NAME, q, uint, u, 16, 8, expected_csat_lt_64_2, MSG);
 258   TEST_BINARY_SAT_OP(INSN_NAME, q, uint, u, 32, 4, expected_csat_lt_64_2, MSG);
 259
 260   CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_lt_64_2, MSG);
 261   CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_lt_64_2, MSG);
 262   CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_lt_64_2, MSG);
 263   CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_lt_64_2, MSG);
 264   CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_lt_64_2, MSG);
 265   CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_lt_64_2, MSG);
 266 }