1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts
;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges
;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras
;
121 /* Number of instructions combined in this function. */
123 static int combine_successes
;
125 /* Totals over entire compilation. */
127 static int total_attempts
, total_merges
, total_extras
, total_successes
;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs
;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs
;
146 typedef struct reg_stat_struct
{
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick
;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
216 char last_set_sign_bit_copies
;
217 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid
;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies
;
239 unsigned HOST_WIDE_INT nonzero_bits
;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label
;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 DEF_VEC_O(reg_stat_type
);
256 DEF_VEC_ALLOC_O(reg_stat_type
,heap
);
258 static VEC(reg_stat_type
,heap
) *reg_stat
;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set
;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid
;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn
;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid
;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs
;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn
;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block
;
300 static bool optimize_this_for_speed_p
;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known
;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost
;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx
*uid_log_links
;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick
;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start
;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode
;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid
;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
};
351 union { rtx r
; int i
; enum machine_mode m
; } old_contents
;
352 union { rtx
*r
; int *i
; } where
;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf
;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences
;
375 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
377 unsigned HOST_WIDE_INT
,
378 unsigned HOST_WIDE_INT
*);
379 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx
*, rtx
);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx
);
386 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
387 static int cant_combine_insn_p (rtx
);
388 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
389 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
390 static int contains_muldiv (rtx
);
391 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx
*find_split_point (rtx
*, rtx
, bool);
395 static rtx
subst (rtx
, rtx
, rtx
, int, int);
396 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
397 static rtx
simplify_if_then_else (rtx
);
398 static rtx
simplify_set (rtx
);
399 static rtx
simplify_logical (rtx
);
400 static rtx
expand_compound_operation (rtx
);
401 static const_rtx
expand_field_assignment (const_rtx
);
402 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
403 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
404 static rtx
extract_left_shift (rtx
, int);
405 static rtx
make_compound_operation (rtx
, enum rtx_code
);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
407 unsigned HOST_WIDE_INT
*);
408 static rtx
canon_reg_for_combine (rtx
, rtx
);
409 static rtx
force_to_mode (rtx
, enum machine_mode
,
410 unsigned HOST_WIDE_INT
, int);
411 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
412 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
413 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
414 static rtx
make_field_assignment (rtx
);
415 static rtx
apply_distributive_law (rtx
);
416 static rtx
distribute_and_simplify_rtx (rtx
, int);
417 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
418 unsigned HOST_WIDE_INT
);
419 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
420 unsigned HOST_WIDE_INT
);
421 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
422 HOST_WIDE_INT
, enum machine_mode
, int *);
423 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
424 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
426 static int recog_for_combine (rtx
*, rtx
, rtx
*);
427 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
428 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
429 static void update_table_tick (rtx
);
430 static void record_value_for_reg (rtx
, rtx
, rtx
);
431 static void check_promoted_subreg (rtx
, rtx
);
432 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
433 static void record_dead_and_set_regs (rtx
);
434 static int get_last_value_validate (rtx
*, rtx
, int, int);
435 static rtx
get_last_value (const_rtx
);
436 static int use_crosses_set_p (const_rtx
, int);
437 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
438 static int reg_dead_at_p (rtx
, rtx
);
439 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
440 static int reg_bitfield_target_p (rtx
, rtx
);
441 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
442 static void distribute_links (rtx
);
443 static void mark_used_regs_combine (rtx
);
444 static void record_promoted_value (rtx
, rtx
);
445 static int unmentioned_reg_p_1 (rtx
*, void *);
446 static bool unmentioned_reg_p (rtx
, rtx
);
447 static int record_truncated_value (rtx
*, void *);
448 static void record_truncated_values (rtx
*, void *);
449 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
450 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern
, rtx insn
)
486 ret
= split_insns (pattern
, insn
);
487 nregs
= max_reg_num ();
488 if (nregs
> VEC_length (reg_stat_type
, reg_stat
))
489 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest
, rtx
*loc
)
503 enum rtx_code code
= GET_CODE (x
);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x
)) != CC0
526 && GET_CODE (SET_DEST (x
)) != PC
527 && !REG_P (SET_DEST (x
))
528 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x
)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
531 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
533 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
536 return find_single_use_1 (dest
, &SET_SRC (x
));
540 return find_single_use_1 (dest
, &XEXP (x
, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt
= GET_RTX_FORMAT (code
);
550 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
554 if (dest
== XEXP (x
, i
)
555 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
556 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
559 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
562 result
= this_result
;
563 else if (this_result
)
564 /* Duplicate usage. */
567 else if (fmt
[i
] == 'E')
571 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
573 if (XVECEXP (x
, i
, j
) == dest
575 && REG_P (XVECEXP (x
, i
, j
))
576 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
579 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
582 result
= this_result
;
583 else if (this_result
)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
618 next
= NEXT_INSN (insn
);
620 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
623 result
= find_single_use_1 (dest
, &PATTERN (next
));
633 bb
= BLOCK_FOR_INSN (insn
);
634 for (next
= NEXT_INSN (insn
);
635 next
&& BLOCK_FOR_INSN (next
) == bb
;
636 next
= NEXT_INSN (next
))
637 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
639 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
640 if (XEXP (link
, 0) == insn
)
645 result
= find_single_use_1 (dest
, &PATTERN (next
));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx
*into
, rtx newval
)
667 if (oldval
== newval
)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
676 && CONST_INT_P (newval
))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval
)
681 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval
) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval
))));
691 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval
, 0))));
696 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
698 buf
= XNEW (struct undo
);
700 buf
->kind
= UNDO_RTX
;
702 buf
->old_contents
.r
= oldval
;
705 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into
, int newval
)
720 if (oldval
== newval
)
724 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
726 buf
= XNEW (struct undo
);
728 buf
->kind
= UNDO_INT
;
730 buf
->old_contents
.i
= oldval
;
733 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
747 enum machine_mode oldval
= GET_MODE (*into
);
749 if (oldval
== newval
)
753 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
755 buf
= XNEW (struct undo
);
757 buf
->kind
= UNDO_MODE
;
759 buf
->old_contents
.m
= oldval
;
760 adjust_reg_mode (*into
, newval
);
762 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
778 rtx newi2pat
, rtx newotherpat
)
780 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
781 int new_i2_cost
, new_i3_cost
;
782 int old_cost
, new_cost
;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost
= INSN_COST (i2
);
786 i3_cost
= INSN_COST (i3
);
790 i1_cost
= INSN_COST (i1
);
793 i0_cost
= INSN_COST (i0
);
794 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
795 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
799 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
800 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
806 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
807 i1_cost
= i0_cost
= 0;
810 /* Calculate the replacement insn_rtx_costs. */
811 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
814 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
815 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
816 ? new_i2_cost
+ new_i3_cost
: 0;
820 new_cost
= new_i3_cost
;
824 if (undobuf
.other_insn
)
826 int old_other_cost
, new_other_cost
;
828 old_other_cost
= INSN_COST (undobuf
.other_insn
);
829 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
830 if (old_other_cost
> 0 && new_other_cost
> 0)
832 old_cost
+= old_other_cost
;
833 new_cost
+= new_other_cost
;
839 /* Disallow this recombination if both new_cost and old_cost are
840 greater than zero, and new_cost is greater than old cost. */
842 && new_cost
> old_cost
)
849 "rejecting combination of insns %d, %d, %d and %d\n",
850 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
852 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
853 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
858 "rejecting combination of insns %d, %d and %d\n",
859 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
860 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
861 i1_cost
, i2_cost
, i3_cost
, old_cost
);
866 "rejecting combination of insns %d and %d\n",
867 INSN_UID (i2
), INSN_UID (i3
));
868 fprintf (dump_file
, "original costs %d + %d = %d\n",
869 i2_cost
, i3_cost
, old_cost
);
874 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
875 new_i2_cost
, new_i3_cost
, new_cost
);
878 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
884 /* Update the uid_insn_cost array with the replacement costs. */
885 INSN_COST (i2
) = new_i2_cost
;
886 INSN_COST (i3
) = new_i3_cost
;
894 /* Delete any insns that copy a register to itself. */
897 delete_noop_moves (void)
904 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
906 next
= NEXT_INSN (insn
);
907 if (INSN_P (insn
) && noop_move_p (insn
))
910 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
912 delete_insn_and_edges (insn
);
919 /* Fill in log links field for all insns. */
922 create_log_links (void)
926 df_ref
*def_vec
, *use_vec
;
928 next_use
= XCNEWVEC (rtx
, max_reg_num ());
930 /* Pass through each block from the end, recording the uses of each
931 register and establishing log links when def is encountered.
932 Note that we do not clear next_use array in order to save time,
933 so we have to test whether the use is in the same basic block as def.
935 There are a few cases below when we do not consider the definition or
936 usage -- these are taken from original flow.c did. Don't ask me why it is
937 done this way; I don't know and if it works, I don't want to know. */
941 FOR_BB_INSNS_REVERSE (bb
, insn
)
943 if (!NONDEBUG_INSN_P (insn
))
946 /* Log links are created only once. */
947 gcc_assert (!LOG_LINKS (insn
));
949 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
951 df_ref def
= *def_vec
;
952 int regno
= DF_REF_REGNO (def
);
955 if (!next_use
[regno
])
958 /* Do not consider if it is pre/post modification in MEM. */
959 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
962 /* Do not make the log link for frame pointer. */
963 if ((regno
== FRAME_POINTER_REGNUM
964 && (! reload_completed
|| frame_pointer_needed
))
965 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
966 || (regno
== HARD_FRAME_POINTER_REGNUM
967 && (! reload_completed
|| frame_pointer_needed
))
969 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
970 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
975 use_insn
= next_use
[regno
];
976 if (BLOCK_FOR_INSN (use_insn
) == bb
)
980 We don't build a LOG_LINK for hard registers contained
981 in ASM_OPERANDs. If these registers get replaced,
982 we might wind up changing the semantics of the insn,
983 even if reload can make what appear to be valid
984 assignments later. */
985 if (regno
>= FIRST_PSEUDO_REGISTER
986 || asm_noperands (PATTERN (use_insn
)) < 0)
988 /* Don't add duplicate links between instructions. */
990 for (links
= LOG_LINKS (use_insn
); links
;
991 links
= XEXP (links
, 1))
992 if (insn
== XEXP (links
, 0))
996 LOG_LINKS (use_insn
) =
997 alloc_INSN_LIST (insn
, LOG_LINKS (use_insn
));
1000 next_use
[regno
] = NULL_RTX
;
1003 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1005 df_ref use
= *use_vec
;
1006 int regno
= DF_REF_REGNO (use
);
1008 /* Do not consider the usage of the stack pointer
1009 by function call. */
1010 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1013 next_use
[regno
] = insn
;
1021 /* Clear LOG_LINKS fields of insns. */
1024 clear_log_links (void)
1028 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1030 free_INSN_LIST_list (&LOG_LINKS (insn
));
1033 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1034 true if we found a LOG_LINK that proves that A feeds B. This only works
1035 if there are no instructions between A and B which could have a link
1036 depending on A, since in that case we would not record a link for B. */
1039 insn_a_feeds_b (rtx a
, rtx b
)
1042 for (links
= LOG_LINKS (b
); links
; links
= XEXP (links
, 1))
1043 if (XEXP (links
, 0) == a
)
1048 /* Main entry point for combiner. F is the first insn of the function.
1049 NREGS is the first unused pseudo-reg number.
1051 Return nonzero if the combiner has turned an indirect jump
1052 instruction into a direct jump. */
1054 combine_instructions (rtx f
, unsigned int nregs
)
1060 rtx links
, nextlinks
;
1062 basic_block last_bb
;
1064 int new_direct_jump_p
= 0;
1066 for (first
= f
; first
&& !INSN_P (first
); )
1067 first
= NEXT_INSN (first
);
1071 combine_attempts
= 0;
1074 combine_successes
= 0;
1076 rtl_hooks
= combine_rtl_hooks
;
1078 VEC_safe_grow_cleared (reg_stat_type
, heap
, reg_stat
, nregs
);
1080 init_recog_no_volatile ();
1082 /* Allocate array for insn info. */
1083 max_uid_known
= get_max_uid ();
1084 uid_log_links
= XCNEWVEC (rtx
, max_uid_known
+ 1);
1085 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1087 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1089 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1090 problems when, for example, we have j <<= 1 in a loop. */
1092 nonzero_sign_valid
= 0;
1093 label_tick
= label_tick_ebb_start
= 1;
1095 /* Scan all SETs and see if we can deduce anything about what
1096 bits are known to be zero for some registers and how many copies
1097 of the sign bit are known to exist for those registers.
1099 Also set any known values so that we can use it while searching
1100 for what bits are known to be set. */
1102 setup_incoming_promotions (first
);
1103 /* Allow the entry block and the first block to fall into the same EBB.
1104 Conceptually the incoming promotions are assigned to the entry block. */
1105 last_bb
= ENTRY_BLOCK_PTR
;
1107 create_log_links ();
1108 FOR_EACH_BB (this_basic_block
)
1110 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1115 if (!single_pred_p (this_basic_block
)
1116 || single_pred (this_basic_block
) != last_bb
)
1117 label_tick_ebb_start
= label_tick
;
1118 last_bb
= this_basic_block
;
1120 FOR_BB_INSNS (this_basic_block
, insn
)
1121 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1123 subst_low_luid
= DF_INSN_LUID (insn
);
1126 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1128 record_dead_and_set_regs (insn
);
1131 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1132 if (REG_NOTE_KIND (links
) == REG_INC
)
1133 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1137 /* Record the current insn_rtx_cost of this instruction. */
1138 if (NONJUMP_INSN_P (insn
))
1139 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1140 optimize_this_for_speed_p
);
1142 fprintf(dump_file
, "insn_cost %d: %d\n",
1143 INSN_UID (insn
), INSN_COST (insn
));
1147 nonzero_sign_valid
= 1;
1149 /* Now scan all the insns in forward order. */
1150 label_tick
= label_tick_ebb_start
= 1;
1152 setup_incoming_promotions (first
);
1153 last_bb
= ENTRY_BLOCK_PTR
;
1155 FOR_EACH_BB (this_basic_block
)
1157 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1162 if (!single_pred_p (this_basic_block
)
1163 || single_pred (this_basic_block
) != last_bb
)
1164 label_tick_ebb_start
= label_tick
;
1165 last_bb
= this_basic_block
;
1167 rtl_profile_for_bb (this_basic_block
);
1168 for (insn
= BB_HEAD (this_basic_block
);
1169 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1170 insn
= next
? next
: NEXT_INSN (insn
))
1173 if (NONDEBUG_INSN_P (insn
))
1175 /* See if we know about function return values before this
1176 insn based upon SUBREG flags. */
1177 check_promoted_subreg (insn
, PATTERN (insn
));
1179 /* See if we can find hardregs and subreg of pseudos in
1180 narrower modes. This could help turning TRUNCATEs
1182 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1184 /* Try this insn with each insn it links back to. */
1186 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1187 if ((next
= try_combine (insn
, XEXP (links
, 0), NULL_RTX
,
1188 NULL_RTX
, &new_direct_jump_p
)) != 0)
1191 /* Try each sequence of three linked insns ending with this one. */
1193 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1195 rtx link
= XEXP (links
, 0);
1197 /* If the linked insn has been replaced by a note, then there
1198 is no point in pursuing this chain any further. */
1202 for (nextlinks
= LOG_LINKS (link
);
1204 nextlinks
= XEXP (nextlinks
, 1))
1205 if ((next
= try_combine (insn
, link
, XEXP (nextlinks
, 0),
1207 &new_direct_jump_p
)) != 0)
1212 /* Try to combine a jump insn that uses CC0
1213 with a preceding insn that sets CC0, and maybe with its
1214 logical predecessor as well.
1215 This is how we make decrement-and-branch insns.
1216 We need this special code because data flow connections
1217 via CC0 do not get entered in LOG_LINKS. */
1220 && (prev
= prev_nonnote_insn (insn
)) != 0
1221 && NONJUMP_INSN_P (prev
)
1222 && sets_cc0_p (PATTERN (prev
)))
1224 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1225 &new_direct_jump_p
)) != 0)
1228 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1229 nextlinks
= XEXP (nextlinks
, 1))
1230 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1232 &new_direct_jump_p
)) != 0)
1236 /* Do the same for an insn that explicitly references CC0. */
1237 if (NONJUMP_INSN_P (insn
)
1238 && (prev
= prev_nonnote_insn (insn
)) != 0
1239 && NONJUMP_INSN_P (prev
)
1240 && sets_cc0_p (PATTERN (prev
))
1241 && GET_CODE (PATTERN (insn
)) == SET
1242 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1244 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1245 &new_direct_jump_p
)) != 0)
1248 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
1249 nextlinks
= XEXP (nextlinks
, 1))
1250 if ((next
= try_combine (insn
, prev
, XEXP (nextlinks
, 0),
1252 &new_direct_jump_p
)) != 0)
1256 /* Finally, see if any of the insns that this insn links to
1257 explicitly references CC0. If so, try this insn, that insn,
1258 and its predecessor if it sets CC0. */
1259 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1260 if (NONJUMP_INSN_P (XEXP (links
, 0))
1261 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
1262 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
1263 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
1264 && NONJUMP_INSN_P (prev
)
1265 && sets_cc0_p (PATTERN (prev
))
1266 && (next
= try_combine (insn
, XEXP (links
, 0),
1268 &new_direct_jump_p
)) != 0)
1272 /* Try combining an insn with two different insns whose results it
1274 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1275 for (nextlinks
= XEXP (links
, 1); nextlinks
;
1276 nextlinks
= XEXP (nextlinks
, 1))
1277 if ((next
= try_combine (insn
, XEXP (links
, 0),
1278 XEXP (nextlinks
, 0), NULL_RTX
,
1279 &new_direct_jump_p
)) != 0)
1282 /* Try four-instruction combinations. */
1283 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1286 rtx link
= XEXP (links
, 0);
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 for (next1
= LOG_LINKS (link
); next1
; next1
= XEXP (next1
, 1))
1295 rtx link1
= XEXP (next1
, 0);
1298 /* I0 -> I1 -> I2 -> I3. */
1299 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1300 nextlinks
= XEXP (nextlinks
, 1))
1301 if ((next
= try_combine (insn
, link
, link1
,
1302 XEXP (nextlinks
, 0),
1303 &new_direct_jump_p
)) != 0)
1305 /* I0, I1 -> I2, I2 -> I3. */
1306 for (nextlinks
= XEXP (next1
, 1); nextlinks
;
1307 nextlinks
= XEXP (nextlinks
, 1))
1308 if ((next
= try_combine (insn
, link
, link1
,
1309 XEXP (nextlinks
, 0),
1310 &new_direct_jump_p
)) != 0)
1314 for (next1
= XEXP (links
, 1); next1
; next1
= XEXP (next1
, 1))
1316 rtx link1
= XEXP (next1
, 0);
1319 /* I0 -> I2; I1, I2 -> I3. */
1320 for (nextlinks
= LOG_LINKS (link
); nextlinks
;
1321 nextlinks
= XEXP (nextlinks
, 1))
1322 if ((next
= try_combine (insn
, link
, link1
,
1323 XEXP (nextlinks
, 0),
1324 &new_direct_jump_p
)) != 0)
1326 /* I0 -> I1; I1, I2 -> I3. */
1327 for (nextlinks
= LOG_LINKS (link1
); nextlinks
;
1328 nextlinks
= XEXP (nextlinks
, 1))
1329 if ((next
= try_combine (insn
, link
, link1
,
1330 XEXP (nextlinks
, 0),
1331 &new_direct_jump_p
)) != 0)
1336 /* Try this insn with each REG_EQUAL note it links back to. */
1337 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
1340 rtx temp
= XEXP (links
, 0);
1341 if ((set
= single_set (temp
)) != 0
1342 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1343 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1344 /* Avoid using a register that may already been marked
1345 dead by an earlier instruction. */
1346 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1347 && (GET_MODE (note
) == VOIDmode
1348 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1349 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1351 /* Temporarily replace the set's source with the
1352 contents of the REG_EQUAL note. The insn will
1353 be deleted or recognized by try_combine. */
1354 rtx orig
= SET_SRC (set
);
1355 SET_SRC (set
) = note
;
1357 i2mod_old_rhs
= copy_rtx (orig
);
1358 i2mod_new_rhs
= copy_rtx (note
);
1359 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1360 &new_direct_jump_p
);
1364 SET_SRC (set
) = orig
;
1369 record_dead_and_set_regs (insn
);
1377 default_rtl_profile ();
1380 new_direct_jump_p
|= purge_all_dead_edges ();
1381 delete_noop_moves ();
1384 free (uid_log_links
);
1385 free (uid_insn_cost
);
1386 VEC_free (reg_stat_type
, heap
, reg_stat
);
1389 struct undo
*undo
, *next
;
1390 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1398 total_attempts
+= combine_attempts
;
1399 total_merges
+= combine_merges
;
1400 total_extras
+= combine_extras
;
1401 total_successes
+= combine_successes
;
1403 nonzero_sign_valid
= 0;
1404 rtl_hooks
= general_rtl_hooks
;
1406 /* Make recognizer allow volatile MEMs again. */
1409 return new_direct_jump_p
;
1412 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1415 init_reg_last (void)
1420 FOR_EACH_VEC_ELT (reg_stat_type
, reg_stat
, i
, p
)
1421 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1424 /* Set up any promoted values for incoming argument registers. */
1427 setup_incoming_promotions (rtx first
)
1430 bool strictly_local
= false;
1432 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1433 arg
= DECL_CHAIN (arg
))
1435 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1437 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1439 /* Only continue if the incoming argument is in a register. */
1443 /* Determine, if possible, whether all call sites of the current
1444 function lie within the current compilation unit. (This does
1445 take into account the exporting of a function via taking its
1446 address, and so forth.) */
1447 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1449 /* The mode and signedness of the argument before any promotions happen
1450 (equal to the mode of the pseudo holding it at that stage). */
1451 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1452 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1454 /* The mode and signedness of the argument after any source language and
1455 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1456 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1457 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1459 /* The mode and signedness of the argument as it is actually passed,
1460 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1461 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1462 TREE_TYPE (cfun
->decl
), 0);
1464 /* The mode of the register in which the argument is being passed. */
1465 mode4
= GET_MODE (reg
);
1467 /* Eliminate sign extensions in the callee when:
1468 (a) A mode promotion has occurred; */
1471 /* (b) The mode of the register is the same as the mode of
1472 the argument as it is passed; */
1475 /* (c) There's no language level extension; */
1478 /* (c.1) All callers are from the current compilation unit. If that's
1479 the case we don't have to rely on an ABI, we only have to know
1480 what we're generating right now, and we know that we will do the
1481 mode1 to mode2 promotion with the given sign. */
1482 else if (!strictly_local
)
1484 /* (c.2) The combination of the two promotions is useful. This is
1485 true when the signs match, or if the first promotion is unsigned.
1486 In the later case, (sign_extend (zero_extend x)) is the same as
1487 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1493 /* Record that the value was promoted from mode1 to mode3,
1494 so that any sign extension at the head of the current
1495 function may be eliminated. */
1496 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1497 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1498 record_value_for_reg (reg
, first
, x
);
1502 /* Called via note_stores. If X is a pseudo that is narrower than
1503 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1505 If we are setting only a portion of X and we can't figure out what
1506 portion, assume all bits will be used since we don't know what will
1509 Similarly, set how many bits of X are known to be copies of the sign bit
1510 at all locations in the function. This is the smallest number implied
1514 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1516 rtx insn
= (rtx
) data
;
1520 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1521 /* If this register is undefined at the start of the file, we can't
1522 say what its contents were. */
1523 && ! REGNO_REG_SET_P
1524 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1525 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
1527 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
1529 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1531 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1532 rsp
->sign_bit_copies
= 1;
1536 /* If this register is being initialized using itself, and the
1537 register is uninitialized in this basic block, and there are
1538 no LOG_LINKS which set the register, then part of the
1539 register is uninitialized. In that case we can't assume
1540 anything about the number of nonzero bits.
1542 ??? We could do better if we checked this in
1543 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1544 could avoid making assumptions about the insn which initially
1545 sets the register, while still using the information in other
1546 insns. We would have to be careful to check every insn
1547 involved in the combination. */
1550 && reg_referenced_p (x
, PATTERN (insn
))
1551 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1556 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1558 if (dead_or_set_p (XEXP (link
, 0), x
))
1563 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1564 rsp
->sign_bit_copies
= 1;
1569 /* If this is a complex assignment, see if we can convert it into a
1570 simple assignment. */
1571 set
= expand_field_assignment (set
);
1573 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1574 set what we know about X. */
1576 if (SET_DEST (set
) == x
1577 || (GET_CODE (SET_DEST (set
)) == SUBREG
1578 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1579 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1580 && SUBREG_REG (SET_DEST (set
)) == x
))
1582 rtx src
= SET_SRC (set
);
1584 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1585 /* If X is narrower than a word and SRC is a non-negative
1586 constant that would appear negative in the mode of X,
1587 sign-extend it for use in reg_stat[].nonzero_bits because some
1588 machines (maybe most) will actually do the sign-extension
1589 and this is the conservative approach.
1591 ??? For 2.5, try to tighten up the MD files in this regard
1592 instead of this kludge. */
1594 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1595 && CONST_INT_P (src
)
1597 && 0 != (INTVAL (src
)
1598 & ((HOST_WIDE_INT
) 1
1599 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1600 src
= GEN_INT (INTVAL (src
)
1601 | ((HOST_WIDE_INT
) (-1)
1602 << GET_MODE_BITSIZE (GET_MODE (x
))));
1605 /* Don't call nonzero_bits if it cannot change anything. */
1606 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1607 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1608 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1609 if (rsp
->sign_bit_copies
== 0
1610 || rsp
->sign_bit_copies
> num
)
1611 rsp
->sign_bit_copies
= num
;
1615 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1616 rsp
->sign_bit_copies
= 1;
1621 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1622 optionally insns that were previously combined into I3 or that will be
1623 combined into the merger of INSN and I3. The order is PRED, PRED2,
1624 INSN, SUCC, SUCC2, I3.
1626 Return 0 if the combination is not allowed for any reason.
1628 If the combination is allowed, *PDEST will be set to the single
1629 destination of INSN and *PSRC to the single source, and this function
1633 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1634 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1635 rtx
*pdest
, rtx
*psrc
)
1644 bool all_adjacent
= true;
1650 if (next_active_insn (succ2
) != i3
)
1651 all_adjacent
= false;
1652 if (next_active_insn (succ
) != succ2
)
1653 all_adjacent
= false;
1655 else if (next_active_insn (succ
) != i3
)
1656 all_adjacent
= false;
1657 if (next_active_insn (insn
) != succ
)
1658 all_adjacent
= false;
1660 else if (next_active_insn (insn
) != i3
)
1661 all_adjacent
= false;
1663 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1664 or a PARALLEL consisting of such a SET and CLOBBERs.
1666 If INSN has CLOBBER parallel parts, ignore them for our processing.
1667 By definition, these happen during the execution of the insn. When it
1668 is merged with another insn, all bets are off. If they are, in fact,
1669 needed and aren't also supplied in I3, they may be added by
1670 recog_for_combine. Otherwise, it won't match.
1672 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1675 Get the source and destination of INSN. If more than one, can't
1678 if (GET_CODE (PATTERN (insn
)) == SET
)
1679 set
= PATTERN (insn
);
1680 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1681 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1683 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1685 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1687 switch (GET_CODE (elt
))
1689 /* This is important to combine floating point insns
1690 for the SH4 port. */
1692 /* Combining an isolated USE doesn't make sense.
1693 We depend here on combinable_i3pat to reject them. */
1694 /* The code below this loop only verifies that the inputs of
1695 the SET in INSN do not change. We call reg_set_between_p
1696 to verify that the REG in the USE does not change between
1698 If the USE in INSN was for a pseudo register, the matching
1699 insn pattern will likely match any register; combining this
1700 with any other USE would only be safe if we knew that the
1701 used registers have identical values, or if there was
1702 something to tell them apart, e.g. different modes. For
1703 now, we forgo such complicated tests and simply disallow
1704 combining of USES of pseudo registers with any other USE. */
1705 if (REG_P (XEXP (elt
, 0))
1706 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1708 rtx i3pat
= PATTERN (i3
);
1709 int i
= XVECLEN (i3pat
, 0) - 1;
1710 unsigned int regno
= REGNO (XEXP (elt
, 0));
1714 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1716 if (GET_CODE (i3elt
) == USE
1717 && REG_P (XEXP (i3elt
, 0))
1718 && (REGNO (XEXP (i3elt
, 0)) == regno
1719 ? reg_set_between_p (XEXP (elt
, 0),
1720 PREV_INSN (insn
), i3
)
1721 : regno
>= FIRST_PSEUDO_REGISTER
))
1728 /* We can ignore CLOBBERs. */
1733 /* Ignore SETs whose result isn't used but not those that
1734 have side-effects. */
1735 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1736 && insn_nothrow_p (insn
)
1737 && !side_effects_p (elt
))
1740 /* If we have already found a SET, this is a second one and
1741 so we cannot combine with this insn. */
1749 /* Anything else means we can't combine. */
1755 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1756 so don't do anything with it. */
1757 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1766 set
= expand_field_assignment (set
);
1767 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1769 /* Don't eliminate a store in the stack pointer. */
1770 if (dest
== stack_pointer_rtx
1771 /* Don't combine with an insn that sets a register to itself if it has
1772 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1773 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1774 /* Can't merge an ASM_OPERANDS. */
1775 || GET_CODE (src
) == ASM_OPERANDS
1776 /* Can't merge a function call. */
1777 || GET_CODE (src
) == CALL
1778 /* Don't eliminate a function call argument. */
1780 && (find_reg_fusage (i3
, USE
, dest
)
1782 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1783 && global_regs
[REGNO (dest
)])))
1784 /* Don't substitute into an incremented register. */
1785 || FIND_REG_INC_NOTE (i3
, dest
)
1786 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1787 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1788 /* Don't substitute into a non-local goto, this confuses CFG. */
1789 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1790 /* Make sure that DEST is not used after SUCC but before I3. */
1793 && (reg_used_between_p (dest
, succ2
, i3
)
1794 || reg_used_between_p (dest
, succ
, succ2
)))
1795 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1796 /* Make sure that the value that is to be substituted for the register
1797 does not use any registers whose values alter in between. However,
1798 If the insns are adjacent, a use can't cross a set even though we
1799 think it might (this can happen for a sequence of insns each setting
1800 the same destination; last_set of that register might point to
1801 a NOTE). If INSN has a REG_EQUIV note, the register is always
1802 equivalent to the memory so the substitution is valid even if there
1803 are intervening stores. Also, don't move a volatile asm or
1804 UNSPEC_VOLATILE across any other insns. */
1807 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1808 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1809 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1810 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1811 /* Don't combine across a CALL_INSN, because that would possibly
1812 change whether the life span of some REGs crosses calls or not,
1813 and it is a pain to update that information.
1814 Exception: if source is a constant, moving it later can't hurt.
1815 Accept that as a special case. */
1816 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1819 /* DEST must either be a REG or CC0. */
1822 /* If register alignment is being enforced for multi-word items in all
1823 cases except for parameters, it is possible to have a register copy
1824 insn referencing a hard register that is not allowed to contain the
1825 mode being copied and which would not be valid as an operand of most
1826 insns. Eliminate this problem by not combining with such an insn.
1828 Also, on some machines we don't want to extend the life of a hard
1832 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1833 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1834 /* Don't extend the life of a hard register unless it is
1835 user variable (if we have few registers) or it can't
1836 fit into the desired register (meaning something special
1838 Also avoid substituting a return register into I3, because
1839 reload can't handle a conflict with constraints of other
1841 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1842 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1845 else if (GET_CODE (dest
) != CC0
)
1849 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1850 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1851 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1853 /* Don't substitute for a register intended as a clobberable
1855 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1856 if (rtx_equal_p (reg
, dest
))
1859 /* If the clobber represents an earlyclobber operand, we must not
1860 substitute an expression containing the clobbered register.
1861 As we do not analyze the constraint strings here, we have to
1862 make the conservative assumption. However, if the register is
1863 a fixed hard reg, the clobber cannot represent any operand;
1864 we leave it up to the machine description to either accept or
1865 reject use-and-clobber patterns. */
1867 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1868 || !fixed_regs
[REGNO (reg
)])
1869 if (reg_overlap_mentioned_p (reg
, src
))
1873 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1874 or not), reject, unless nothing volatile comes between it and I3 */
1876 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1878 /* Make sure neither succ nor succ2 contains a volatile reference. */
1879 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1881 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1883 /* We'll check insns between INSN and I3 below. */
1886 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1887 to be an explicit register variable, and was chosen for a reason. */
1889 if (GET_CODE (src
) == ASM_OPERANDS
1890 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1893 /* If there are any volatile insns between INSN and I3, reject, because
1894 they might affect machine state. */
1896 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1897 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& volatile_insn_p (PATTERN (p
)))
1900 /* If INSN contains an autoincrement or autodecrement, make sure that
1901 register is not used between there and I3, and not already used in
1902 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1903 Also insist that I3 not be a jump; if it were one
1904 and the incremented register were spilled, we would lose. */
1907 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1908 if (REG_NOTE_KIND (link
) == REG_INC
1910 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1911 || (pred
!= NULL_RTX
1912 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1913 || (pred2
!= NULL_RTX
1914 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1915 || (succ
!= NULL_RTX
1916 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1917 || (succ2
!= NULL_RTX
1918 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1919 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1924 /* Don't combine an insn that follows a CC0-setting insn.
1925 An insn that uses CC0 must not be separated from the one that sets it.
1926 We do, however, allow I2 to follow a CC0-setting insn if that insn
1927 is passed as I1; in that case it will be deleted also.
1928 We also allow combining in this case if all the insns are adjacent
1929 because that would leave the two CC0 insns adjacent as well.
1930 It would be more logical to test whether CC0 occurs inside I1 or I2,
1931 but that would be much slower, and this ought to be equivalent. */
1933 p
= prev_nonnote_insn (insn
);
1934 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1939 /* If we get here, we have passed all the tests and the combination is
1948 /* LOC is the location within I3 that contains its pattern or the component
1949 of a PARALLEL of the pattern. We validate that it is valid for combining.
1951 One problem is if I3 modifies its output, as opposed to replacing it
1952 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1953 doing so would produce an insn that is not equivalent to the original insns.
1957 (set (reg:DI 101) (reg:DI 100))
1958 (set (subreg:SI (reg:DI 101) 0) <foo>)
1960 This is NOT equivalent to:
1962 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1963 (set (reg:DI 101) (reg:DI 100))])
1965 Not only does this modify 100 (in which case it might still be valid
1966 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1968 We can also run into a problem if I2 sets a register that I1
1969 uses and I1 gets directly substituted into I3 (not via I2). In that
1970 case, we would be getting the wrong value of I2DEST into I3, so we
1971 must reject the combination. This case occurs when I2 and I1 both
1972 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1973 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1974 of a SET must prevent combination from occurring. The same situation
1975 can occur for I0, in which case I0_NOT_IN_SRC is set.
1977 Before doing the above check, we first try to expand a field assignment
1978 into a set of logical operations.
1980 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1981 we place a register that is both set and used within I3. If more than one
1982 such register is detected, we fail.
1984 Return 1 if the combination is valid, zero otherwise. */
1987 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
1988 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
1992 if (GET_CODE (x
) == SET
)
1995 rtx dest
= SET_DEST (set
);
1996 rtx src
= SET_SRC (set
);
1997 rtx inner_dest
= dest
;
2000 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2001 || GET_CODE (inner_dest
) == SUBREG
2002 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2003 inner_dest
= XEXP (inner_dest
, 0);
2005 /* Check for the case where I3 modifies its output, as discussed
2006 above. We don't want to prevent pseudos from being combined
2007 into the address of a MEM, so only prevent the combination if
2008 i1 or i2 set the same MEM. */
2009 if ((inner_dest
!= dest
&&
2010 (!MEM_P (inner_dest
)
2011 || rtx_equal_p (i2dest
, inner_dest
)
2012 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2013 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2014 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2015 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2016 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2018 /* This is the same test done in can_combine_p except we can't test
2019 all_adjacent; we don't have to, since this instruction will stay
2020 in place, thus we are not considering increasing the lifetime of
2023 Also, if this insn sets a function argument, combining it with
2024 something that might need a spill could clobber a previous
2025 function argument; the all_adjacent test in can_combine_p also
2026 checks this; here, we do a more specific test for this case. */
2028 || (REG_P (inner_dest
)
2029 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2030 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2031 GET_MODE (inner_dest
))))
2032 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2033 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2036 /* If DEST is used in I3, it is being killed in this insn, so
2037 record that for later. We have to consider paradoxical
2038 subregs here, since they kill the whole register, but we
2039 ignore partial subregs, STRICT_LOW_PART, etc.
2040 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2041 STACK_POINTER_REGNUM, since these are always considered to be
2042 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2044 if (GET_CODE (subdest
) == SUBREG
2045 && (GET_MODE_SIZE (GET_MODE (subdest
))
2046 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2047 subdest
= SUBREG_REG (subdest
);
2050 && reg_referenced_p (subdest
, PATTERN (i3
))
2051 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2052 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2053 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2055 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2056 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2057 || ! fixed_regs
[REGNO (subdest
)])
2059 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2061 if (*pi3dest_killed
)
2064 *pi3dest_killed
= subdest
;
2068 else if (GET_CODE (x
) == PARALLEL
)
2072 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2073 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2074 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2081 /* Return 1 if X is an arithmetic expression that contains a multiplication
2082 and division. We don't count multiplications by powers of two here. */
2085 contains_muldiv (rtx x
)
2087 switch (GET_CODE (x
))
2089 case MOD
: case DIV
: case UMOD
: case UDIV
:
2093 return ! (CONST_INT_P (XEXP (x
, 1))
2094 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
2097 return contains_muldiv (XEXP (x
, 0))
2098 || contains_muldiv (XEXP (x
, 1));
2101 return contains_muldiv (XEXP (x
, 0));
2107 /* Determine whether INSN can be used in a combination. Return nonzero if
2108 not. This is used in try_combine to detect early some cases where we
2109 can't perform combinations. */
2112 cant_combine_insn_p (rtx insn
)
2117 /* If this isn't really an insn, we can't do anything.
2118 This can occur when flow deletes an insn that it has merged into an
2119 auto-increment address. */
2120 if (! INSN_P (insn
))
2123 /* Never combine loads and stores involving hard regs that are likely
2124 to be spilled. The register allocator can usually handle such
2125 reg-reg moves by tying. If we allow the combiner to make
2126 substitutions of likely-spilled regs, reload might die.
2127 As an exception, we allow combinations involving fixed regs; these are
2128 not available to the register allocator so there's no risk involved. */
2130 set
= single_set (insn
);
2133 src
= SET_SRC (set
);
2134 dest
= SET_DEST (set
);
2135 if (GET_CODE (src
) == SUBREG
)
2136 src
= SUBREG_REG (src
);
2137 if (GET_CODE (dest
) == SUBREG
)
2138 dest
= SUBREG_REG (dest
);
2139 if (REG_P (src
) && REG_P (dest
)
2140 && ((HARD_REGISTER_P (src
)
2141 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2142 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2143 || (HARD_REGISTER_P (dest
)
2144 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2145 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2151 struct likely_spilled_retval_info
2153 unsigned regno
, nregs
;
2157 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2158 hard registers that are known to be written to / clobbered in full. */
2160 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2162 struct likely_spilled_retval_info
*const info
=
2163 (struct likely_spilled_retval_info
*) data
;
2164 unsigned regno
, nregs
;
2167 if (!REG_P (XEXP (set
, 0)))
2170 if (regno
>= info
->regno
+ info
->nregs
)
2172 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2173 if (regno
+ nregs
<= info
->regno
)
2175 new_mask
= (2U << (nregs
- 1)) - 1;
2176 if (regno
< info
->regno
)
2177 new_mask
>>= info
->regno
- regno
;
2179 new_mask
<<= regno
- info
->regno
;
2180 info
->mask
&= ~new_mask
;
2183 /* Return nonzero iff part of the return value is live during INSN, and
2184 it is likely spilled. This can happen when more than one insn is needed
2185 to copy the return value, e.g. when we consider to combine into the
2186 second copy insn for a complex value. */
2189 likely_spilled_retval_p (rtx insn
)
2191 rtx use
= BB_END (this_basic_block
);
2193 unsigned regno
, nregs
;
2194 /* We assume here that no machine mode needs more than
2195 32 hard registers when the value overlaps with a register
2196 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2198 struct likely_spilled_retval_info info
;
2200 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2202 reg
= XEXP (PATTERN (use
), 0);
2203 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2205 regno
= REGNO (reg
);
2206 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2209 mask
= (2U << (nregs
- 1)) - 1;
2211 /* Disregard parts of the return value that are set later. */
2215 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2217 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2220 /* Check if any of the (probably) live return value registers is
2225 if ((mask
& 1 << nregs
)
2226 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2232 /* Adjust INSN after we made a change to its destination.
2234 Changing the destination can invalidate notes that say something about
2235 the results of the insn and a LOG_LINK pointing to the insn. */
2238 adjust_for_new_dest (rtx insn
)
2240 /* For notes, be conservative and simply remove them. */
2241 remove_reg_equal_equiv_notes (insn
);
2243 /* The new insn will have a destination that was previously the destination
2244 of an insn just above it. Call distribute_links to make a LOG_LINK from
2245 the next use of that destination. */
2246 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
2248 df_insn_rescan (insn
);
2251 /* Return TRUE if combine can reuse reg X in mode MODE.
2252 ADDED_SETS is nonzero if the original set is still required. */
2254 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2262 /* Allow hard registers if the new mode is legal, and occupies no more
2263 registers than the old mode. */
2264 if (regno
< FIRST_PSEUDO_REGISTER
)
2265 return (HARD_REGNO_MODE_OK (regno
, mode
)
2266 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2267 >= hard_regno_nregs
[regno
][mode
]));
2269 /* Or a pseudo that is only used once. */
2270 return (REG_N_SETS (regno
) == 1 && !added_sets
2271 && !REG_USERVAR_P (x
));
2275 /* Check whether X, the destination of a set, refers to part of
2276 the register specified by REG. */
2279 reg_subword_p (rtx x
, rtx reg
)
2281 /* Check that reg is an integer mode register. */
2282 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2285 if (GET_CODE (x
) == STRICT_LOW_PART
2286 || GET_CODE (x
) == ZERO_EXTRACT
)
2289 return GET_CODE (x
) == SUBREG
2290 && SUBREG_REG (x
) == reg
2291 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2295 /* Replace auto-increment addressing modes with explicit operations to access
2296 the same addresses without modifying the corresponding registers. */
2299 cleanup_auto_inc_dec (rtx src
, enum machine_mode mem_mode
)
2302 const RTX_CODE code
= GET_CODE (x
);
2318 /* SCRATCH must be shared because they represent distinct values. */
2321 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
2326 if (shared_const_p (x
))
2331 mem_mode
= GET_MODE (x
);
2336 gcc_assert (mem_mode
!= VOIDmode
&& mem_mode
!= BLKmode
);
2337 return gen_rtx_PLUS (GET_MODE (x
),
2338 cleanup_auto_inc_dec (XEXP (x
, 0), mem_mode
),
2339 GEN_INT (code
== PRE_INC
2340 ? GET_MODE_SIZE (mem_mode
)
2341 : -GET_MODE_SIZE (mem_mode
)));
2347 return cleanup_auto_inc_dec (code
== PRE_MODIFY
2348 ? XEXP (x
, 1) : XEXP (x
, 0),
2355 /* Copy the various flags, fields, and other information. We assume
2356 that all fields need copying, and then clear the fields that should
2357 not be copied. That is the sensible default behavior, and forces
2358 us to explicitly document why we are *not* copying a flag. */
2359 x
= shallow_copy_rtx (x
);
2361 /* We do not copy the USED flag, which is used as a mark bit during
2362 walks over the RTL. */
2363 RTX_FLAG (x
, used
) = 0;
2365 /* We do not copy FRAME_RELATED for INSNs. */
2367 RTX_FLAG (x
, frame_related
) = 0;
2369 fmt
= GET_RTX_FORMAT (code
);
2370 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2372 XEXP (x
, i
) = cleanup_auto_inc_dec (XEXP (x
, i
), mem_mode
);
2373 else if (fmt
[i
] == 'E' || fmt
[i
] == 'V')
2376 XVEC (x
, i
) = rtvec_alloc (XVECLEN (x
, i
));
2377 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2379 = cleanup_auto_inc_dec (XVECEXP (src
, i
, j
), mem_mode
);
2386 /* Auxiliary data structure for propagate_for_debug_stmt. */
2388 struct rtx_subst_pair
2394 /* DATA points to an rtx_subst_pair. Return the value that should be
2398 propagate_for_debug_subst (rtx from
, const_rtx old_rtx
, void *data
)
2400 struct rtx_subst_pair
*pair
= (struct rtx_subst_pair
*)data
;
2402 if (!rtx_equal_p (from
, old_rtx
))
2404 if (!pair
->adjusted
)
2406 pair
->adjusted
= true;
2408 pair
->to
= cleanup_auto_inc_dec (pair
->to
, VOIDmode
);
2410 pair
->to
= copy_rtx (pair
->to
);
2412 pair
->to
= make_compound_operation (pair
->to
, SET
);
2415 return copy_rtx (pair
->to
);
2418 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2422 propagate_for_debug (rtx insn
, rtx last
, rtx dest
, rtx src
)
2426 struct rtx_subst_pair p
;
2430 next
= NEXT_INSN (insn
);
2431 while (next
!= last
)
2434 next
= NEXT_INSN (insn
);
2435 if (DEBUG_INSN_P (insn
))
2437 loc
= simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn
),
2438 dest
, propagate_for_debug_subst
, &p
);
2439 if (loc
== INSN_VAR_LOCATION_LOC (insn
))
2441 INSN_VAR_LOCATION_LOC (insn
) = loc
;
2442 df_insn_rescan (insn
);
2447 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2448 Note that the INSN should be deleted *after* removing dead edges, so
2449 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2450 but not for a (set (pc) (label_ref FOO)). */
2453 update_cfg_for_uncondjump (rtx insn
)
2455 basic_block bb
= BLOCK_FOR_INSN (insn
);
2456 bool at_end
= (BB_END (bb
) == insn
);
2459 purge_dead_edges (bb
);
2462 if (at_end
&& EDGE_COUNT (bb
->succs
) == 1)
2463 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2466 /* Try to combine the insns I0, I1 and I2 into I3.
2467 Here I0, I1 and I2 appear earlier than I3.
2468 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2471 If we are combining more than two insns and the resulting insn is not
2472 recognized, try splitting it into two insns. If that happens, I2 and I3
2473 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2474 Otherwise, I0, I1 and I2 are pseudo-deleted.
2476 Return 0 if the combination does not work. Then nothing is changed.
2477 If we did the combination, return the insn at which combine should
2480 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2481 new direct jump instruction. */
2484 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
)
2486 /* New patterns for I3 and I2, respectively. */
2487 rtx newpat
, newi2pat
= 0;
2488 rtvec newpat_vec_with_clobbers
= 0;
2489 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2490 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2492 int added_sets_0
, added_sets_1
, added_sets_2
;
2493 /* Total number of SETs to put into I3. */
2495 /* Nonzero if I2's or I1's body now appears in I3. */
2496 int i2_is_used
= 0, i1_is_used
= 0;
2497 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2498 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2499 /* Contains I3 if the destination of I3 is used in its source, which means
2500 that the old life of I3 is being killed. If that usage is placed into
2501 I2 and not in I3, a REG_DEAD note must be made. */
2502 rtx i3dest_killed
= 0;
2503 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2504 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2505 /* Set if I2DEST was reused as a scratch register. */
2506 bool i2scratch
= false;
2507 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2508 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2509 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2510 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2511 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2512 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2513 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2514 /* Notes that must be added to REG_NOTES in I3 and I2. */
2515 rtx new_i3_notes
, new_i2_notes
;
2516 /* Notes that we substituted I3 into I2 instead of the normal case. */
2517 int i3_subst_into_i2
= 0;
2518 /* Notes that I1, I2 or I3 is a MULT operation. */
2521 int changed_i3_dest
= 0;
2527 rtx new_other_notes
;
2530 /* Only try four-insn combinations when there's high likelihood of
2531 success. Look for simple insns, such as loads of constants or
2532 binary operations involving a constant. */
2539 if (!flag_expensive_optimizations
)
2542 for (i
= 0; i
< 4; i
++)
2544 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2545 rtx set
= single_set (insn
);
2549 src
= SET_SRC (set
);
2550 if (CONSTANT_P (src
))
2555 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2557 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2558 || GET_CODE (src
) == LSHIFTRT
)
2561 if (ngood
< 2 && nshift
< 2)
2565 /* Exit early if one of the insns involved can't be used for
2567 if (cant_combine_insn_p (i3
)
2568 || cant_combine_insn_p (i2
)
2569 || (i1
&& cant_combine_insn_p (i1
))
2570 || (i0
&& cant_combine_insn_p (i0
))
2571 || likely_spilled_retval_p (i3
))
2575 undobuf
.other_insn
= 0;
2577 /* Reset the hard register usage information. */
2578 CLEAR_HARD_REG_SET (newpat_used_regs
);
2580 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2583 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2584 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2586 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2587 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2589 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2590 INSN_UID (i2
), INSN_UID (i3
));
2593 /* If multiple insns feed into one of I2 or I3, they can be in any
2594 order. To simplify the code below, reorder them in sequence. */
2595 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2596 temp
= i2
, i2
= i0
, i0
= temp
;
2597 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2598 temp
= i1
, i1
= i0
, i0
= temp
;
2599 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2600 temp
= i1
, i1
= i2
, i2
= temp
;
2602 added_links_insn
= 0;
2604 /* First check for one important special case that the code below will
2605 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2606 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2607 we may be able to replace that destination with the destination of I3.
2608 This occurs in the common code where we compute both a quotient and
2609 remainder into a structure, in which case we want to do the computation
2610 directly into the structure to avoid register-register copies.
2612 Note that this case handles both multiple sets in I2 and also cases
2613 where I2 has a number of CLOBBERs inside the PARALLEL.
2615 We make very conservative checks below and only try to handle the
2616 most common cases of this. For example, we only handle the case
2617 where I2 and I3 are adjacent to avoid making difficult register
2620 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2621 && REG_P (SET_SRC (PATTERN (i3
)))
2622 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2623 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2624 && GET_CODE (PATTERN (i2
)) == PARALLEL
2625 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2626 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2627 below would need to check what is inside (and reg_overlap_mentioned_p
2628 doesn't support those codes anyway). Don't allow those destinations;
2629 the resulting insn isn't likely to be recognized anyway. */
2630 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2631 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2632 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2633 SET_DEST (PATTERN (i3
)))
2634 && next_active_insn (i2
) == i3
)
2636 rtx p2
= PATTERN (i2
);
2638 /* Make sure that the destination of I3,
2639 which we are going to substitute into one output of I2,
2640 is not used within another output of I2. We must avoid making this:
2641 (parallel [(set (mem (reg 69)) ...)
2642 (set (reg 69) ...)])
2643 which is not well-defined as to order of actions.
2644 (Besides, reload can't handle output reloads for this.)
2646 The problem can also happen if the dest of I3 is a memory ref,
2647 if another dest in I2 is an indirect memory ref. */
2648 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2649 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2650 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2651 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2652 SET_DEST (XVECEXP (p2
, 0, i
))))
2655 if (i
== XVECLEN (p2
, 0))
2656 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2657 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2658 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2663 subst_low_luid
= DF_INSN_LUID (i2
);
2665 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2666 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2667 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2668 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2670 /* Replace the dest in I2 with our dest and make the resulting
2671 insn the new pattern for I3. Then skip to where we validate
2672 the pattern. Everything was set up above. */
2673 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2675 i3_subst_into_i2
= 1;
2676 goto validate_replacement
;
2680 /* If I2 is setting a pseudo to a constant and I3 is setting some
2681 sub-part of it to another constant, merge them by making a new
2684 && (temp
= single_set (i2
)) != 0
2685 && (CONST_INT_P (SET_SRC (temp
))
2686 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
2687 && GET_CODE (PATTERN (i3
)) == SET
2688 && (CONST_INT_P (SET_SRC (PATTERN (i3
)))
2689 || GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_DOUBLE
)
2690 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2692 rtx dest
= SET_DEST (PATTERN (i3
));
2696 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2698 if (CONST_INT_P (XEXP (dest
, 1))
2699 && CONST_INT_P (XEXP (dest
, 2)))
2701 width
= INTVAL (XEXP (dest
, 1));
2702 offset
= INTVAL (XEXP (dest
, 2));
2703 dest
= XEXP (dest
, 0);
2704 if (BITS_BIG_ENDIAN
)
2705 offset
= GET_MODE_BITSIZE (GET_MODE (dest
)) - width
- offset
;
2710 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2711 dest
= XEXP (dest
, 0);
2712 width
= GET_MODE_BITSIZE (GET_MODE (dest
));
2718 /* If this is the low part, we're done. */
2719 if (subreg_lowpart_p (dest
))
2721 /* Handle the case where inner is twice the size of outer. */
2722 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2723 == 2 * GET_MODE_BITSIZE (GET_MODE (dest
)))
2724 offset
+= GET_MODE_BITSIZE (GET_MODE (dest
));
2725 /* Otherwise give up for now. */
2731 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp
)))
2732 <= HOST_BITS_PER_DOUBLE_INT
))
2735 rtx inner
= SET_SRC (PATTERN (i3
));
2736 rtx outer
= SET_SRC (temp
);
2738 o
= rtx_to_double_int (outer
);
2739 i
= rtx_to_double_int (inner
);
2741 m
= double_int_mask (width
);
2742 i
= double_int_and (i
, m
);
2743 m
= double_int_lshift (m
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2744 i
= double_int_lshift (i
, offset
, HOST_BITS_PER_DOUBLE_INT
, false);
2745 o
= double_int_ior (double_int_and_not (o
, m
), i
);
2749 subst_low_luid
= DF_INSN_LUID (i2
);
2750 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2751 i2dest
= SET_DEST (temp
);
2752 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2754 /* Replace the source in I2 with the new constant and make the
2755 resulting insn the new pattern for I3. Then skip to where we
2756 validate the pattern. Everything was set up above. */
2757 SUBST (SET_SRC (temp
),
2758 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2760 newpat
= PATTERN (i2
);
2762 /* The dest of I3 has been replaced with the dest of I2. */
2763 changed_i3_dest
= 1;
2764 goto validate_replacement
;
2769 /* If we have no I1 and I2 looks like:
2770 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2772 make up a dummy I1 that is
2775 (set (reg:CC X) (compare:CC Y (const_int 0)))
2777 (We can ignore any trailing CLOBBERs.)
2779 This undoes a previous combination and allows us to match a branch-and-
2782 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2783 && XVECLEN (PATTERN (i2
), 0) >= 2
2784 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2785 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2787 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2788 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2789 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2790 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2791 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2792 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2794 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2795 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2800 /* We make I1 with the same INSN_UID as I2. This gives it
2801 the same DF_INSN_LUID for value tracking. Our fake I1 will
2802 never appear in the insn stream so giving it the same INSN_UID
2803 as I2 will not cause a problem. */
2805 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2806 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2807 INSN_LOCATOR (i2
), -1, NULL_RTX
);
2809 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2810 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2811 SET_DEST (PATTERN (i1
)));
2816 /* Verify that I2 and I1 are valid for combining. */
2817 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2818 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2820 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2827 /* Record whether I2DEST is used in I2SRC and similarly for the other
2828 cases. Knowing this will help in register status updating below. */
2829 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2830 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2831 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2832 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2833 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2834 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2835 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2836 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2837 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2839 /* For the earlier insns, determine which of the subsequent ones they
2841 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2842 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2843 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2844 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2845 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2847 /* Ensure that I3's pattern can be the destination of combines. */
2848 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2849 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2850 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2851 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2858 /* See if any of the insns is a MULT operation. Unless one is, we will
2859 reject a combination that is, since it must be slower. Be conservative
2861 if (GET_CODE (i2src
) == MULT
2862 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2863 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2864 || (GET_CODE (PATTERN (i3
)) == SET
2865 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2868 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2869 We used to do this EXCEPT in one case: I3 has a post-inc in an
2870 output operand. However, that exception can give rise to insns like
2872 which is a famous insn on the PDP-11 where the value of r3 used as the
2873 source was model-dependent. Avoid this sort of thing. */
2876 if (!(GET_CODE (PATTERN (i3
)) == SET
2877 && REG_P (SET_SRC (PATTERN (i3
)))
2878 && MEM_P (SET_DEST (PATTERN (i3
)))
2879 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2880 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2881 /* It's not the exception. */
2884 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2885 if (REG_NOTE_KIND (link
) == REG_INC
2886 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2888 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2895 /* See if the SETs in I1 or I2 need to be kept around in the merged
2896 instruction: whenever the value set there is still needed past I3.
2897 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2899 For the SET in I1, we have two cases: If I1 and I2 independently
2900 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2901 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2902 in I1 needs to be kept around unless I1DEST dies or is set in either
2903 I2 or I3. The same consideration applies to I0. */
2905 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2908 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2909 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2914 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2915 || (i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
2916 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)));
2920 /* If the set in I2 needs to be kept around, we must make a copy of
2921 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2922 PATTERN (I2), we are only substituting for the original I1DEST, not into
2923 an already-substituted copy. This also prevents making self-referential
2924 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2929 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2930 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2932 i2pat
= copy_rtx (PATTERN (i2
));
2937 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2938 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2940 i1pat
= copy_rtx (PATTERN (i1
));
2945 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2946 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2948 i0pat
= copy_rtx (PATTERN (i0
));
2953 /* Substitute in the latest insn for the regs set by the earlier ones. */
2955 maxreg
= max_reg_num ();
2960 /* Many machines that don't use CC0 have insns that can both perform an
2961 arithmetic operation and set the condition code. These operations will
2962 be represented as a PARALLEL with the first element of the vector
2963 being a COMPARE of an arithmetic operation with the constant zero.
2964 The second element of the vector will set some pseudo to the result
2965 of the same arithmetic operation. If we simplify the COMPARE, we won't
2966 match such a pattern and so will generate an extra insn. Here we test
2967 for this case, where both the comparison and the operation result are
2968 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2969 I2SRC. Later we will make the PARALLEL that contains I2. */
2971 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2972 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2973 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2974 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2976 #ifdef SELECT_CC_MODE
2978 enum machine_mode compare_mode
;
2981 newpat
= PATTERN (i3
);
2982 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2986 #ifdef SELECT_CC_MODE
2987 /* See if a COMPARE with the operand we substituted in should be done
2988 with the mode that is currently being used. If not, do the same
2989 processing we do in `subst' for a SET; namely, if the destination
2990 is used only once, try to replace it with a register of the proper
2991 mode and also replace the COMPARE. */
2992 if (undobuf
.other_insn
== 0
2993 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2994 &undobuf
.other_insn
))
2995 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2997 != GET_MODE (SET_DEST (newpat
))))
2999 if (can_change_dest_mode (SET_DEST (newpat
), added_sets_2
,
3002 unsigned int regno
= REGNO (SET_DEST (newpat
));
3005 if (regno
< FIRST_PSEUDO_REGISTER
)
3006 new_dest
= gen_rtx_REG (compare_mode
, regno
);
3009 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3010 new_dest
= regno_reg_rtx
[regno
];
3013 SUBST (SET_DEST (newpat
), new_dest
);
3014 SUBST (XEXP (*cc_use
, 0), new_dest
);
3015 SUBST (SET_SRC (newpat
),
3016 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
3019 undobuf
.other_insn
= 0;
3026 /* It is possible that the source of I2 or I1 may be performing
3027 an unneeded operation, such as a ZERO_EXTEND of something
3028 that is known to have the high part zero. Handle that case
3029 by letting subst look at the innermost one of them.
3031 Another way to do this would be to have a function that tries
3032 to simplify a single insn instead of merging two or more
3033 insns. We don't do this because of the potential of infinite
3034 loops and because of the potential extra memory required.
3035 However, doing it the way we are is a bit of a kludge and
3036 doesn't catch all cases.
3038 But only do this if -fexpensive-optimizations since it slows
3039 things down and doesn't usually win.
3041 This is not done in the COMPARE case above because the
3042 unmodified I2PAT is used in the PARALLEL and so a pattern
3043 with a modified I2SRC would not match. */
3045 if (flag_expensive_optimizations
)
3047 /* Pass pc_rtx so no substitutions are done, just
3051 subst_low_luid
= DF_INSN_LUID (i1
);
3052 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
3056 subst_low_luid
= DF_INSN_LUID (i2
);
3057 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
3061 n_occurrences
= 0; /* `subst' counts here */
3063 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a
3064 unique copy of I2SRC each time we substitute it to avoid
3065 self-referential rtl. */
3067 subst_low_luid
= DF_INSN_LUID (i2
);
3068 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
3069 ((i1_feeds_i2_n
&& i1dest_in_i1src
)
3070 || (i0_feeds_i2_n
&& i0dest_in_i0src
)));
3073 /* Record whether i2's body now appears within i3's body. */
3074 i2_is_used
= n_occurrences
;
3077 /* If we already got a failure, don't try to do more. Otherwise,
3078 try to substitute in I1 if we have it. */
3080 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3082 /* Check that an autoincrement side-effect on I1 has not been lost.
3083 This happens if I1DEST is mentioned in I2 and dies there, and
3084 has disappeared from the new pattern. */
3085 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3087 && dead_or_set_p (i2
, i1dest
)
3088 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3089 /* Before we can do this substitution, we must redo the test done
3090 above (see detailed comments there) that ensures that I1DEST
3091 isn't mentioned in any SETs in NEWPAT that are field assignments. */
3092 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3100 subst_low_luid
= DF_INSN_LUID (i1
);
3101 newpat
= subst (newpat
, i1dest
, i1src
, 0,
3102 i0_feeds_i1_n
&& i0dest_in_i0src
);
3104 i1_is_used
= n_occurrences
;
3106 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3108 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3109 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3110 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3111 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3112 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3120 subst_low_luid
= DF_INSN_LUID (i0
);
3121 newpat
= subst (newpat
, i0dest
, i0src
, 0,
3122 i0_feeds_i1_n
&& i0dest_in_i0src
);
3126 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3127 to count all the ways that I2SRC and I1SRC can be used. */
3128 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3129 && i2_is_used
+ added_sets_2
> 1)
3130 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3131 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3133 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3134 && (n_occurrences
+ added_sets_0
3135 + (added_sets_1
&& i0_feeds_i1_n
)
3136 + (added_sets_2
&& i0_feeds_i2_n
)
3138 /* Fail if we tried to make a new register. */
3139 || max_reg_num () != maxreg
3140 /* Fail if we couldn't do something and have a CLOBBER. */
3141 || GET_CODE (newpat
) == CLOBBER
3142 /* Fail if this new pattern is a MULT and we didn't have one before
3143 at the outer level. */
3144 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3151 /* If the actions of the earlier insns must be kept
3152 in addition to substituting them into the latest one,
3153 we must make a new PARALLEL for the latest insn
3154 to hold additional the SETs. */
3156 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3158 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3161 if (GET_CODE (newpat
) == PARALLEL
)
3163 rtvec old
= XVEC (newpat
, 0);
3164 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3165 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3166 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3167 sizeof (old
->elem
[0]) * old
->num_elem
);
3172 total_sets
= 1 + extra_sets
;
3173 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3174 XVECEXP (newpat
, 0, 0) = old
;
3178 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3184 t
= subst (t
, i0dest
, i0src
, 0, 0);
3186 XVECEXP (newpat
, 0, --total_sets
) = t
;
3192 t
= subst (t
, i0dest
, i0src
, 0, 0);
3194 t
= subst (t
, i1dest
, i1src
, 0, 0);
3195 if (i0_feeds_i1_n
&& i1_feeds_i2_n
)
3196 t
= subst (t
, i0dest
, i0src
, 0, 0);
3198 XVECEXP (newpat
, 0, --total_sets
) = t
;
3202 validate_replacement
:
3204 /* Note which hard regs this insn has as inputs. */
3205 mark_used_regs_combine (newpat
);
3207 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3208 consider splitting this pattern, we might need these clobbers. */
3209 if (i1
&& GET_CODE (newpat
) == PARALLEL
3210 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3212 int len
= XVECLEN (newpat
, 0);
3214 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3215 for (i
= 0; i
< len
; i
++)
3216 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3219 /* Is the result of combination a valid instruction? */
3220 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3222 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3223 the second SET's destination is a register that is unused and isn't
3224 marked as an instruction that might trap in an EH region. In that case,
3225 we just need the first SET. This can occur when simplifying a divmod
3226 insn. We *must* test for this case here because the code below that
3227 splits two independent SETs doesn't handle this case correctly when it
3228 updates the register status.
3230 It's pointless doing this if we originally had two sets, one from
3231 i3, and one from i2. Combining then splitting the parallel results
3232 in the original i2 again plus an invalid insn (which we delete).
3233 The net effect is only to move instructions around, which makes
3234 debug info less accurate.
3236 Also check the case where the first SET's destination is unused.
3237 That would not cause incorrect code, but does cause an unneeded
3240 if (insn_code_number
< 0
3241 && !(added_sets_2
&& i1
== 0)
3242 && GET_CODE (newpat
) == PARALLEL
3243 && XVECLEN (newpat
, 0) == 2
3244 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3245 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3246 && asm_noperands (newpat
) < 0)
3248 rtx set0
= XVECEXP (newpat
, 0, 0);
3249 rtx set1
= XVECEXP (newpat
, 0, 1);
3251 if (((REG_P (SET_DEST (set1
))
3252 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3253 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3254 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3255 && insn_nothrow_p (i3
)
3256 && !side_effects_p (SET_SRC (set1
)))
3259 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3262 else if (((REG_P (SET_DEST (set0
))
3263 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3264 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3265 && find_reg_note (i3
, REG_UNUSED
,
3266 SUBREG_REG (SET_DEST (set0
)))))
3267 && insn_nothrow_p (i3
)
3268 && !side_effects_p (SET_SRC (set0
)))
3271 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3273 if (insn_code_number
>= 0)
3274 changed_i3_dest
= 1;
3278 /* If we were combining three insns and the result is a simple SET
3279 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3280 insns. There are two ways to do this. It can be split using a
3281 machine-specific method (like when you have an addition of a large
3282 constant) or by combine in the function find_split_point. */
3284 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3285 && asm_noperands (newpat
) < 0)
3287 rtx parallel
, m_split
, *split
;
3289 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3290 use I2DEST as a scratch register will help. In the latter case,
3291 convert I2DEST to the mode of the source of NEWPAT if we can. */
3293 m_split
= combine_split_insns (newpat
, i3
);
3295 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3296 inputs of NEWPAT. */
3298 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3299 possible to try that as a scratch reg. This would require adding
3300 more code to make it work though. */
3302 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3304 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3306 /* First try to split using the original register as a
3307 scratch register. */
3308 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3309 gen_rtvec (2, newpat
,
3310 gen_rtx_CLOBBER (VOIDmode
,
3312 m_split
= combine_split_insns (parallel
, i3
);
3314 /* If that didn't work, try changing the mode of I2DEST if
3317 && new_mode
!= GET_MODE (i2dest
)
3318 && new_mode
!= VOIDmode
3319 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3321 enum machine_mode old_mode
= GET_MODE (i2dest
);
3324 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3325 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3328 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3329 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3332 parallel
= (gen_rtx_PARALLEL
3334 gen_rtvec (2, newpat
,
3335 gen_rtx_CLOBBER (VOIDmode
,
3337 m_split
= combine_split_insns (parallel
, i3
);
3340 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3344 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3345 buf
= undobuf
.undos
;
3346 undobuf
.undos
= buf
->next
;
3347 buf
->next
= undobuf
.frees
;
3348 undobuf
.frees
= buf
;
3352 i2scratch
= m_split
!= 0;
3355 /* If recog_for_combine has discarded clobbers, try to use them
3356 again for the split. */
3357 if (m_split
== 0 && newpat_vec_with_clobbers
)
3359 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3360 m_split
= combine_split_insns (parallel
, i3
);
3363 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3365 m_split
= PATTERN (m_split
);
3366 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3367 if (insn_code_number
>= 0)
3370 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3371 && (next_real_insn (i2
) == i3
3372 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3375 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3376 newi2pat
= PATTERN (m_split
);
3378 i3set
= single_set (NEXT_INSN (m_split
));
3379 i2set
= single_set (m_split
);
3381 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3383 /* If I2 or I3 has multiple SETs, we won't know how to track
3384 register status, so don't use these insns. If I2's destination
3385 is used between I2 and I3, we also can't use these insns. */
3387 if (i2_code_number
>= 0 && i2set
&& i3set
3388 && (next_real_insn (i2
) == i3
3389 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3390 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3392 if (insn_code_number
>= 0)
3395 /* It is possible that both insns now set the destination of I3.
3396 If so, we must show an extra use of it. */
3398 if (insn_code_number
>= 0)
3400 rtx new_i3_dest
= SET_DEST (i3set
);
3401 rtx new_i2_dest
= SET_DEST (i2set
);
3403 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3404 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3405 || GET_CODE (new_i3_dest
) == SUBREG
)
3406 new_i3_dest
= XEXP (new_i3_dest
, 0);
3408 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3409 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3410 || GET_CODE (new_i2_dest
) == SUBREG
)
3411 new_i2_dest
= XEXP (new_i2_dest
, 0);
3413 if (REG_P (new_i3_dest
)
3414 && REG_P (new_i2_dest
)
3415 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3416 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3420 /* If we can split it and use I2DEST, go ahead and see if that
3421 helps things be recognized. Verify that none of the registers
3422 are set between I2 and I3. */
3423 if (insn_code_number
< 0
3424 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3428 /* We need I2DEST in the proper mode. If it is a hard register
3429 or the only use of a pseudo, we can change its mode.
3430 Make sure we don't change a hard register to have a mode that
3431 isn't valid for it, or change the number of registers. */
3432 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3433 || GET_MODE (*split
) == VOIDmode
3434 || can_change_dest_mode (i2dest
, added_sets_2
,
3436 && (next_real_insn (i2
) == i3
3437 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3438 /* We can't overwrite I2DEST if its value is still used by
3440 && ! reg_referenced_p (i2dest
, newpat
))
3442 rtx newdest
= i2dest
;
3443 enum rtx_code split_code
= GET_CODE (*split
);
3444 enum machine_mode split_mode
= GET_MODE (*split
);
3445 bool subst_done
= false;
3446 newi2pat
= NULL_RTX
;
3450 /* *SPLIT may be part of I2SRC, so make sure we have the
3451 original expression around for later debug processing.
3452 We should not need I2SRC any more in other cases. */
3453 if (MAY_HAVE_DEBUG_INSNS
)
3454 i2src
= copy_rtx (i2src
);
3458 /* Get NEWDEST as a register in the proper mode. We have already
3459 validated that we can do this. */
3460 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3462 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3463 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3466 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3467 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3471 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3472 an ASHIFT. This can occur if it was inside a PLUS and hence
3473 appeared to be a memory address. This is a kludge. */
3474 if (split_code
== MULT
3475 && CONST_INT_P (XEXP (*split
, 1))
3476 && INTVAL (XEXP (*split
, 1)) > 0
3477 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
3479 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3480 XEXP (*split
, 0), GEN_INT (i
)));
3481 /* Update split_code because we may not have a multiply
3483 split_code
= GET_CODE (*split
);
3486 #ifdef INSN_SCHEDULING
3487 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3488 be written as a ZERO_EXTEND. */
3489 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3491 #ifdef LOAD_EXTEND_OP
3492 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3493 what it really is. */
3494 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3496 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3497 SUBREG_REG (*split
)));
3500 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3501 SUBREG_REG (*split
)));
3505 /* Attempt to split binary operators using arithmetic identities. */
3506 if (BINARY_P (SET_SRC (newpat
))
3507 && split_mode
== GET_MODE (SET_SRC (newpat
))
3508 && ! side_effects_p (SET_SRC (newpat
)))
3510 rtx setsrc
= SET_SRC (newpat
);
3511 enum machine_mode mode
= GET_MODE (setsrc
);
3512 enum rtx_code code
= GET_CODE (setsrc
);
3513 rtx src_op0
= XEXP (setsrc
, 0);
3514 rtx src_op1
= XEXP (setsrc
, 1);
3516 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3517 if (rtx_equal_p (src_op0
, src_op1
))
3519 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3520 SUBST (XEXP (setsrc
, 0), newdest
);
3521 SUBST (XEXP (setsrc
, 1), newdest
);
3524 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3525 else if ((code
== PLUS
|| code
== MULT
)
3526 && GET_CODE (src_op0
) == code
3527 && GET_CODE (XEXP (src_op0
, 0)) == code
3528 && (INTEGRAL_MODE_P (mode
)
3529 || (FLOAT_MODE_P (mode
)
3530 && flag_unsafe_math_optimizations
)))
3532 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3533 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3534 rtx r
= XEXP (src_op0
, 1);
3537 /* Split both "((X op Y) op X) op Y" and
3538 "((X op Y) op Y) op X" as "T op T" where T is
3540 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3541 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3543 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3545 SUBST (XEXP (setsrc
, 0), newdest
);
3546 SUBST (XEXP (setsrc
, 1), newdest
);
3549 /* Split "((X op X) op Y) op Y)" as "T op T" where
3551 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3553 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3554 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3555 SUBST (XEXP (setsrc
, 0), newdest
);
3556 SUBST (XEXP (setsrc
, 1), newdest
);
3564 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3565 SUBST (*split
, newdest
);
3568 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3570 /* recog_for_combine might have added CLOBBERs to newi2pat.
3571 Make sure NEWPAT does not depend on the clobbered regs. */
3572 if (GET_CODE (newi2pat
) == PARALLEL
)
3573 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3574 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3576 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3577 if (reg_overlap_mentioned_p (reg
, newpat
))
3584 /* If the split point was a MULT and we didn't have one before,
3585 don't use one now. */
3586 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3587 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3591 /* Check for a case where we loaded from memory in a narrow mode and
3592 then sign extended it, but we need both registers. In that case,
3593 we have a PARALLEL with both loads from the same memory location.
3594 We can split this into a load from memory followed by a register-register
3595 copy. This saves at least one insn, more if register allocation can
3598 We cannot do this if the destination of the first assignment is a
3599 condition code register or cc0. We eliminate this case by making sure
3600 the SET_DEST and SET_SRC have the same mode.
3602 We cannot do this if the destination of the second assignment is
3603 a register that we have already assumed is zero-extended. Similarly
3604 for a SUBREG of such a register. */
3606 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3607 && GET_CODE (newpat
) == PARALLEL
3608 && XVECLEN (newpat
, 0) == 2
3609 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3610 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3611 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3612 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3613 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3614 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3615 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3616 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3618 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3619 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3620 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3622 && VEC_index (reg_stat_type
, reg_stat
,
3623 REGNO (temp
))->nonzero_bits
!= 0
3624 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3625 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3626 && (VEC_index (reg_stat_type
, reg_stat
,
3627 REGNO (temp
))->nonzero_bits
3628 != GET_MODE_MASK (word_mode
))))
3629 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3630 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3632 && VEC_index (reg_stat_type
, reg_stat
,
3633 REGNO (temp
))->nonzero_bits
!= 0
3634 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
3635 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
3636 && (VEC_index (reg_stat_type
, reg_stat
,
3637 REGNO (temp
))->nonzero_bits
3638 != GET_MODE_MASK (word_mode
)))))
3639 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3640 SET_SRC (XVECEXP (newpat
, 0, 1)))
3641 && ! find_reg_note (i3
, REG_UNUSED
,
3642 SET_DEST (XVECEXP (newpat
, 0, 0))))
3646 newi2pat
= XVECEXP (newpat
, 0, 0);
3647 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3648 newpat
= XVECEXP (newpat
, 0, 1);
3649 SUBST (SET_SRC (newpat
),
3650 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3651 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3653 if (i2_code_number
>= 0)
3654 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3656 if (insn_code_number
>= 0)
3660 /* Similarly, check for a case where we have a PARALLEL of two independent
3661 SETs but we started with three insns. In this case, we can do the sets
3662 as two separate insns. This case occurs when some SET allows two
3663 other insns to combine, but the destination of that SET is still live. */
3665 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3666 && GET_CODE (newpat
) == PARALLEL
3667 && XVECLEN (newpat
, 0) == 2
3668 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3669 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3670 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3671 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3672 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3673 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3674 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3675 XVECEXP (newpat
, 0, 0))
3676 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3677 XVECEXP (newpat
, 0, 1))
3678 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3679 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3681 /* Normally, it doesn't matter which of the two is done first,
3682 but the one that references cc0 can't be the second, and
3683 one which uses any regs/memory set in between i2 and i3 can't
3685 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3688 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3692 newi2pat
= XVECEXP (newpat
, 0, 1);
3693 newpat
= XVECEXP (newpat
, 0, 0);
3695 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3698 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3702 newi2pat
= XVECEXP (newpat
, 0, 0);
3703 newpat
= XVECEXP (newpat
, 0, 1);
3711 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3713 if (i2_code_number
>= 0)
3715 /* recog_for_combine might have added CLOBBERs to newi2pat.
3716 Make sure NEWPAT does not depend on the clobbered regs. */
3717 if (GET_CODE (newi2pat
) == PARALLEL
)
3719 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3720 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3722 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3723 if (reg_overlap_mentioned_p (reg
, newpat
))
3731 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3735 /* If it still isn't recognized, fail and change things back the way they
3737 if ((insn_code_number
< 0
3738 /* Is the result a reasonable ASM_OPERANDS? */
3739 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3745 /* If we had to change another insn, make sure it is valid also. */
3746 if (undobuf
.other_insn
)
3748 CLEAR_HARD_REG_SET (newpat_used_regs
);
3750 other_pat
= PATTERN (undobuf
.other_insn
);
3751 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3754 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3762 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3763 they are adjacent to each other or not. */
3765 rtx p
= prev_nonnote_insn (i3
);
3766 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3767 && sets_cc0_p (newi2pat
))
3775 /* Only allow this combination if insn_rtx_costs reports that the
3776 replacement instructions are cheaper than the originals. */
3777 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3783 if (MAY_HAVE_DEBUG_INSNS
)
3787 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3788 if (undo
->kind
== UNDO_MODE
)
3790 rtx reg
= *undo
->where
.r
;
3791 enum machine_mode new_mode
= GET_MODE (reg
);
3792 enum machine_mode old_mode
= undo
->old_contents
.m
;
3794 /* Temporarily revert mode back. */
3795 adjust_reg_mode (reg
, old_mode
);
3797 if (reg
== i2dest
&& i2scratch
)
3799 /* If we used i2dest as a scratch register with a
3800 different mode, substitute it for the original
3801 i2src while its original mode is temporarily
3802 restored, and then clear i2scratch so that we don't
3803 do it again later. */
3804 propagate_for_debug (i2
, i3
, reg
, i2src
);
3806 /* Put back the new mode. */
3807 adjust_reg_mode (reg
, new_mode
);
3811 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3822 last
= undobuf
.other_insn
;
3826 /* We're dealing with a reg that changed mode but not
3827 meaning, so we want to turn it into a subreg for
3828 the new mode. However, because of REG sharing and
3829 because its mode had already changed, we have to do
3830 it in two steps. First, replace any debug uses of
3831 reg, with its original mode temporarily restored,
3832 with this copy we have created; then, replace the
3833 copy with the SUBREG of the original shared reg,
3834 once again changed to the new mode. */
3835 propagate_for_debug (first
, last
, reg
, tempreg
);
3836 adjust_reg_mode (reg
, new_mode
);
3837 propagate_for_debug (first
, last
, tempreg
,
3838 lowpart_subreg (old_mode
, reg
, new_mode
));
3843 /* If we will be able to accept this, we have made a
3844 change to the destination of I3. This requires us to
3845 do a few adjustments. */
3847 if (changed_i3_dest
)
3849 PATTERN (i3
) = newpat
;
3850 adjust_for_new_dest (i3
);
3853 /* We now know that we can do this combination. Merge the insns and
3854 update the status of registers and LOG_LINKS. */
3856 if (undobuf
.other_insn
)
3860 PATTERN (undobuf
.other_insn
) = other_pat
;
3862 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3863 are still valid. Then add any non-duplicate notes added by
3864 recog_for_combine. */
3865 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3867 next
= XEXP (note
, 1);
3869 if (REG_NOTE_KIND (note
) == REG_UNUSED
3870 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3871 remove_note (undobuf
.other_insn
, note
);
3874 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3875 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3885 /* I3 now uses what used to be its destination and which is now
3886 I2's destination. This requires us to do a few adjustments. */
3887 PATTERN (i3
) = newpat
;
3888 adjust_for_new_dest (i3
);
3890 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3893 However, some later insn might be using I2's dest and have
3894 a LOG_LINK pointing at I3. We must remove this link.
3895 The simplest way to remove the link is to point it at I1,
3896 which we know will be a NOTE. */
3898 /* newi2pat is usually a SET here; however, recog_for_combine might
3899 have added some clobbers. */
3900 if (GET_CODE (newi2pat
) == PARALLEL
)
3901 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3903 ni2dest
= SET_DEST (newi2pat
);
3905 for (insn
= NEXT_INSN (i3
);
3906 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3907 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3908 insn
= NEXT_INSN (insn
))
3910 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3912 for (link
= LOG_LINKS (insn
); link
;
3913 link
= XEXP (link
, 1))
3914 if (XEXP (link
, 0) == i3
)
3915 XEXP (link
, 0) = i1
;
3923 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3924 rtx i3links
, i2links
, i1links
= 0, i0links
= 0;
3928 /* Compute which registers we expect to eliminate. newi2pat may be setting
3929 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3930 same as i3dest, in which case newi2pat may be setting i1dest. */
3931 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3932 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3935 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3936 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3939 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3940 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3944 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3946 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3947 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3949 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3951 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
3953 /* Ensure that we do not have something that should not be shared but
3954 occurs multiple times in the new insns. Check this by first
3955 resetting all the `used' flags and then copying anything is shared. */
3957 reset_used_flags (i3notes
);
3958 reset_used_flags (i2notes
);
3959 reset_used_flags (i1notes
);
3960 reset_used_flags (i0notes
);
3961 reset_used_flags (newpat
);
3962 reset_used_flags (newi2pat
);
3963 if (undobuf
.other_insn
)
3964 reset_used_flags (PATTERN (undobuf
.other_insn
));
3966 i3notes
= copy_rtx_if_shared (i3notes
);
3967 i2notes
= copy_rtx_if_shared (i2notes
);
3968 i1notes
= copy_rtx_if_shared (i1notes
);
3969 i0notes
= copy_rtx_if_shared (i0notes
);
3970 newpat
= copy_rtx_if_shared (newpat
);
3971 newi2pat
= copy_rtx_if_shared (newi2pat
);
3972 if (undobuf
.other_insn
)
3973 reset_used_flags (PATTERN (undobuf
.other_insn
));
3975 INSN_CODE (i3
) = insn_code_number
;
3976 PATTERN (i3
) = newpat
;
3978 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
3980 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
3982 reset_used_flags (call_usage
);
3983 call_usage
= copy_rtx (call_usage
);
3987 /* I2SRC must still be meaningful at this point. Some splitting
3988 operations can invalidate I2SRC, but those operations do not
3991 replace_rtx (call_usage
, i2dest
, i2src
);
3995 replace_rtx (call_usage
, i1dest
, i1src
);
3997 replace_rtx (call_usage
, i0dest
, i0src
);
3999 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4002 if (undobuf
.other_insn
)
4003 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4005 /* We had one special case above where I2 had more than one set and
4006 we replaced a destination of one of those sets with the destination
4007 of I3. In that case, we have to update LOG_LINKS of insns later
4008 in this basic block. Note that this (expensive) case is rare.
4010 Also, in this case, we must pretend that all REG_NOTEs for I2
4011 actually came from I3, so that REG_UNUSED notes from I2 will be
4012 properly handled. */
4014 if (i3_subst_into_i2
)
4016 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4017 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4018 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4019 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4020 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4021 && ! find_reg_note (i2
, REG_UNUSED
,
4022 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4023 for (temp
= NEXT_INSN (i2
);
4024 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4025 || BB_HEAD (this_basic_block
) != temp
);
4026 temp
= NEXT_INSN (temp
))
4027 if (temp
!= i3
&& INSN_P (temp
))
4028 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
4029 if (XEXP (link
, 0) == i2
)
4030 XEXP (link
, 0) = i3
;
4035 while (XEXP (link
, 1))
4036 link
= XEXP (link
, 1);
4037 XEXP (link
, 1) = i2notes
;
4051 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4052 propagate_for_debug (i2
, i3
, i2dest
, i2src
);
4053 INSN_CODE (i2
) = i2_code_number
;
4054 PATTERN (i2
) = newi2pat
;
4058 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4059 propagate_for_debug (i2
, i3
, i2dest
, i2src
);
4060 SET_INSN_DELETED (i2
);
4067 if (MAY_HAVE_DEBUG_INSNS
)
4068 propagate_for_debug (i1
, i3
, i1dest
, i1src
);
4069 SET_INSN_DELETED (i1
);
4076 if (MAY_HAVE_DEBUG_INSNS
)
4077 propagate_for_debug (i0
, i3
, i0dest
, i0src
);
4078 SET_INSN_DELETED (i0
);
4081 /* Get death notes for everything that is now used in either I3 or
4082 I2 and used to die in a previous insn. If we built two new
4083 patterns, move from I1 to I2 then I2 to I3 so that we get the
4084 proper movement on registers that I2 modifies. */
4087 from_luid
= DF_INSN_LUID (i0
);
4089 from_luid
= DF_INSN_LUID (i1
);
4091 from_luid
= DF_INSN_LUID (i2
);
4093 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4094 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4096 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4098 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4099 elim_i2
, elim_i1
, elim_i0
);
4101 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4102 elim_i2
, elim_i1
, elim_i0
);
4104 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4105 elim_i2
, elim_i1
, elim_i0
);
4107 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4108 elim_i2
, elim_i1
, elim_i0
);
4110 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4111 elim_i2
, elim_i1
, elim_i0
);
4113 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4114 know these are REG_UNUSED and want them to go to the desired insn,
4115 so we always pass it as i3. */
4117 if (newi2pat
&& new_i2_notes
)
4118 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4122 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4125 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4126 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4127 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4128 in that case, it might delete I2. Similarly for I2 and I1.
4129 Show an additional death due to the REG_DEAD note we make here. If
4130 we discard it in distribute_notes, we will decrement it again. */
4134 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4135 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4137 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
, elim_i0
);
4139 distribute_notes (alloc_reg_note (REG_DEAD
, i3dest_killed
,
4141 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4142 elim_i2
, elim_i1
, elim_i0
);
4145 if (i2dest_in_i2src
)
4147 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4148 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4149 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4150 NULL_RTX
, NULL_RTX
);
4152 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4153 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4156 if (i1dest_in_i1src
)
4158 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4159 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4160 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4161 NULL_RTX
, NULL_RTX
);
4163 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4164 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4167 if (i0dest_in_i0src
)
4169 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4170 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4171 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4172 NULL_RTX
, NULL_RTX
);
4174 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4175 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4178 distribute_links (i3links
);
4179 distribute_links (i2links
);
4180 distribute_links (i1links
);
4181 distribute_links (i0links
);
4186 rtx i2_insn
= 0, i2_val
= 0, set
;
4188 /* The insn that used to set this register doesn't exist, and
4189 this life of the register may not exist either. See if one of
4190 I3's links points to an insn that sets I2DEST. If it does,
4191 that is now the last known value for I2DEST. If we don't update
4192 this and I2 set the register to a value that depended on its old
4193 contents, we will get confused. If this insn is used, thing
4194 will be set correctly in combine_instructions. */
4196 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4197 if ((set
= single_set (XEXP (link
, 0))) != 0
4198 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4199 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
4201 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4203 /* If the reg formerly set in I2 died only once and that was in I3,
4204 zero its use count so it won't make `reload' do any work. */
4206 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4207 && ! i2dest_in_i2src
)
4209 regno
= REGNO (i2dest
);
4210 INC_REG_N_SETS (regno
, -1);
4214 if (i1
&& REG_P (i1dest
))
4217 rtx i1_insn
= 0, i1_val
= 0, set
;
4219 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4220 if ((set
= single_set (XEXP (link
, 0))) != 0
4221 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4222 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
4224 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4226 regno
= REGNO (i1dest
);
4227 if (! added_sets_1
&& ! i1dest_in_i1src
)
4228 INC_REG_N_SETS (regno
, -1);
4231 if (i0
&& REG_P (i0dest
))
4234 rtx i0_insn
= 0, i0_val
= 0, set
;
4236 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
4237 if ((set
= single_set (XEXP (link
, 0))) != 0
4238 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4239 i0_insn
= XEXP (link
, 0), i0_val
= SET_SRC (set
);
4241 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4243 regno
= REGNO (i0dest
);
4244 if (! added_sets_0
&& ! i0dest_in_i0src
)
4245 INC_REG_N_SETS (regno
, -1);
4248 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4249 been made to this insn. The order of
4250 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4251 can affect nonzero_bits of newpat */
4253 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4254 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4257 if (undobuf
.other_insn
!= NULL_RTX
)
4261 fprintf (dump_file
, "modifying other_insn ");
4262 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4264 df_insn_rescan (undobuf
.other_insn
);
4267 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4271 fprintf (dump_file
, "modifying insn i1 ");
4272 dump_insn_slim (dump_file
, i0
);
4274 df_insn_rescan (i0
);
4277 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4281 fprintf (dump_file
, "modifying insn i1 ");
4282 dump_insn_slim (dump_file
, i1
);
4284 df_insn_rescan (i1
);
4287 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4291 fprintf (dump_file
, "modifying insn i2 ");
4292 dump_insn_slim (dump_file
, i2
);
4294 df_insn_rescan (i2
);
4297 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4301 fprintf (dump_file
, "modifying insn i3 ");
4302 dump_insn_slim (dump_file
, i3
);
4304 df_insn_rescan (i3
);
4307 /* Set new_direct_jump_p if a new return or simple jump instruction
4308 has been created. Adjust the CFG accordingly. */
4310 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4312 *new_direct_jump_p
= 1;
4313 mark_jump_label (PATTERN (i3
), i3
, 0);
4314 update_cfg_for_uncondjump (i3
);
4317 if (undobuf
.other_insn
!= NULL_RTX
4318 && (returnjump_p (undobuf
.other_insn
)
4319 || any_uncondjump_p (undobuf
.other_insn
)))
4321 *new_direct_jump_p
= 1;
4322 update_cfg_for_uncondjump (undobuf
.other_insn
);
4325 /* A noop might also need cleaning up of CFG, if it comes from the
4326 simplification of a jump. */
4327 if (GET_CODE (newpat
) == SET
4328 && SET_SRC (newpat
) == pc_rtx
4329 && SET_DEST (newpat
) == pc_rtx
)
4331 *new_direct_jump_p
= 1;
4332 update_cfg_for_uncondjump (i3
);
4335 combine_successes
++;
4338 if (added_links_insn
4339 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4340 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4341 return added_links_insn
;
4343 return newi2pat
? i2
: i3
;
4346 /* Undo all the modifications recorded in undobuf. */
4351 struct undo
*undo
, *next
;
4353 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4359 *undo
->where
.r
= undo
->old_contents
.r
;
4362 *undo
->where
.i
= undo
->old_contents
.i
;
4365 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4371 undo
->next
= undobuf
.frees
;
4372 undobuf
.frees
= undo
;
4378 /* We've committed to accepting the changes we made. Move all
4379 of the undos to the free list. */
4384 struct undo
*undo
, *next
;
4386 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4389 undo
->next
= undobuf
.frees
;
4390 undobuf
.frees
= undo
;
4395 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4396 where we have an arithmetic expression and return that point. LOC will
4399 try_combine will call this function to see if an insn can be split into
4403 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4406 enum rtx_code code
= GET_CODE (x
);
4408 unsigned HOST_WIDE_INT len
= 0;
4409 HOST_WIDE_INT pos
= 0;
4411 rtx inner
= NULL_RTX
;
4413 /* First special-case some codes. */
4417 #ifdef INSN_SCHEDULING
4418 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4420 if (MEM_P (SUBREG_REG (x
)))
4423 return find_split_point (&SUBREG_REG (x
), insn
, false);
4427 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4428 using LO_SUM and HIGH. */
4429 if (GET_CODE (XEXP (x
, 0)) == CONST
4430 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4432 enum machine_mode address_mode
4433 = targetm
.addr_space
.address_mode (MEM_ADDR_SPACE (x
));
4436 gen_rtx_LO_SUM (address_mode
,
4437 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4439 return &XEXP (XEXP (x
, 0), 0);
4443 /* If we have a PLUS whose second operand is a constant and the
4444 address is not valid, perhaps will can split it up using
4445 the machine-specific way to split large constants. We use
4446 the first pseudo-reg (one of the virtual regs) as a placeholder;
4447 it will not remain in the result. */
4448 if (GET_CODE (XEXP (x
, 0)) == PLUS
4449 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4450 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4451 MEM_ADDR_SPACE (x
)))
4453 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4454 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4458 /* This should have produced two insns, each of which sets our
4459 placeholder. If the source of the second is a valid address,
4460 we can make put both sources together and make a split point
4464 && NEXT_INSN (seq
) != NULL_RTX
4465 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4466 && NONJUMP_INSN_P (seq
)
4467 && GET_CODE (PATTERN (seq
)) == SET
4468 && SET_DEST (PATTERN (seq
)) == reg
4469 && ! reg_mentioned_p (reg
,
4470 SET_SRC (PATTERN (seq
)))
4471 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4472 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4473 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4474 && memory_address_addr_space_p
4475 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4476 MEM_ADDR_SPACE (x
)))
4478 rtx src1
= SET_SRC (PATTERN (seq
));
4479 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4481 /* Replace the placeholder in SRC2 with SRC1. If we can
4482 find where in SRC2 it was placed, that can become our
4483 split point and we can replace this address with SRC2.
4484 Just try two obvious places. */
4486 src2
= replace_rtx (src2
, reg
, src1
);
4488 if (XEXP (src2
, 0) == src1
)
4489 split
= &XEXP (src2
, 0);
4490 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4491 && XEXP (XEXP (src2
, 0), 0) == src1
)
4492 split
= &XEXP (XEXP (src2
, 0), 0);
4496 SUBST (XEXP (x
, 0), src2
);
4501 /* If that didn't work, perhaps the first operand is complex and
4502 needs to be computed separately, so make a split point there.
4503 This will occur on machines that just support REG + CONST
4504 and have a constant moved through some previous computation. */
4506 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4507 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4508 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4509 return &XEXP (XEXP (x
, 0), 0);
4512 /* If we have a PLUS whose first operand is complex, try computing it
4513 separately by making a split there. */
4514 if (GET_CODE (XEXP (x
, 0)) == PLUS
4515 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4517 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4518 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4519 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4520 return &XEXP (XEXP (x
, 0), 0);
4525 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4526 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4527 we need to put the operand into a register. So split at that
4530 if (SET_DEST (x
) == cc0_rtx
4531 && GET_CODE (SET_SRC (x
)) != COMPARE
4532 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4533 && !OBJECT_P (SET_SRC (x
))
4534 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4535 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4536 return &SET_SRC (x
);
4539 /* See if we can split SET_SRC as it stands. */
4540 split
= find_split_point (&SET_SRC (x
), insn
, true);
4541 if (split
&& split
!= &SET_SRC (x
))
4544 /* See if we can split SET_DEST as it stands. */
4545 split
= find_split_point (&SET_DEST (x
), insn
, false);
4546 if (split
&& split
!= &SET_DEST (x
))
4549 /* See if this is a bitfield assignment with everything constant. If
4550 so, this is an IOR of an AND, so split it into that. */
4551 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4552 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
4553 <= HOST_BITS_PER_WIDE_INT
)
4554 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4555 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4556 && CONST_INT_P (SET_SRC (x
))
4557 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4558 + INTVAL (XEXP (SET_DEST (x
), 2)))
4559 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
4560 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4562 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4563 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4564 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4565 rtx dest
= XEXP (SET_DEST (x
), 0);
4566 enum machine_mode mode
= GET_MODE (dest
);
4567 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
4570 if (BITS_BIG_ENDIAN
)
4571 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
4573 or_mask
= gen_int_mode (src
<< pos
, mode
);
4576 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4579 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4581 simplify_gen_binary (IOR
, mode
,
4582 simplify_gen_binary (AND
, mode
,
4587 SUBST (SET_DEST (x
), dest
);
4589 split
= find_split_point (&SET_SRC (x
), insn
, true);
4590 if (split
&& split
!= &SET_SRC (x
))
4594 /* Otherwise, see if this is an operation that we can split into two.
4595 If so, try to split that. */
4596 code
= GET_CODE (SET_SRC (x
));
4601 /* If we are AND'ing with a large constant that is only a single
4602 bit and the result is only being used in a context where we
4603 need to know if it is zero or nonzero, replace it with a bit
4604 extraction. This will avoid the large constant, which might
4605 have taken more than one insn to make. If the constant were
4606 not a valid argument to the AND but took only one insn to make,
4607 this is no worse, but if it took more than one insn, it will
4610 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4611 && REG_P (XEXP (SET_SRC (x
), 0))
4612 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4613 && REG_P (SET_DEST (x
))
4614 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4615 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4616 && XEXP (*split
, 0) == SET_DEST (x
)
4617 && XEXP (*split
, 1) == const0_rtx
)
4619 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4620 XEXP (SET_SRC (x
), 0),
4621 pos
, NULL_RTX
, 1, 1, 0, 0);
4622 if (extraction
!= 0)
4624 SUBST (SET_SRC (x
), extraction
);
4625 return find_split_point (loc
, insn
, false);
4631 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4632 is known to be on, this can be converted into a NEG of a shift. */
4633 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4634 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4635 && 1 <= (pos
= exact_log2
4636 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4637 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4639 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4643 gen_rtx_LSHIFTRT (mode
,
4644 XEXP (SET_SRC (x
), 0),
4647 split
= find_split_point (&SET_SRC (x
), insn
, true);
4648 if (split
&& split
!= &SET_SRC (x
))
4654 inner
= XEXP (SET_SRC (x
), 0);
4656 /* We can't optimize if either mode is a partial integer
4657 mode as we don't know how many bits are significant
4659 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4660 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4664 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
4670 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4671 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4673 inner
= XEXP (SET_SRC (x
), 0);
4674 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4675 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4677 if (BITS_BIG_ENDIAN
)
4678 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
4679 unsignedp
= (code
== ZERO_EXTRACT
);
4687 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
4689 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4691 /* For unsigned, we have a choice of a shift followed by an
4692 AND or two shifts. Use two shifts for field sizes where the
4693 constant might be too large. We assume here that we can
4694 always at least get 8-bit constants in an AND insn, which is
4695 true for every current RISC. */
4697 if (unsignedp
&& len
<= 8)
4702 (mode
, gen_lowpart (mode
, inner
),
4704 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
4706 split
= find_split_point (&SET_SRC (x
), insn
, true);
4707 if (split
&& split
!= &SET_SRC (x
))
4714 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4715 gen_rtx_ASHIFT (mode
,
4716 gen_lowpart (mode
, inner
),
4717 GEN_INT (GET_MODE_BITSIZE (mode
)
4719 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
4721 split
= find_split_point (&SET_SRC (x
), insn
, true);
4722 if (split
&& split
!= &SET_SRC (x
))
4727 /* See if this is a simple operation with a constant as the second
4728 operand. It might be that this constant is out of range and hence
4729 could be used as a split point. */
4730 if (BINARY_P (SET_SRC (x
))
4731 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4732 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4733 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4734 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4735 return &XEXP (SET_SRC (x
), 1);
4737 /* Finally, see if this is a simple operation with its first operand
4738 not in a register. The operation might require this operand in a
4739 register, so return it as a split point. We can always do this
4740 because if the first operand were another operation, we would have
4741 already found it as a split point. */
4742 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4743 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4744 return &XEXP (SET_SRC (x
), 0);
4750 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4751 it is better to write this as (not (ior A B)) so we can split it.
4752 Similarly for IOR. */
4753 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4756 gen_rtx_NOT (GET_MODE (x
),
4757 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4759 XEXP (XEXP (x
, 0), 0),
4760 XEXP (XEXP (x
, 1), 0))));
4761 return find_split_point (loc
, insn
, set_src
);
4764 /* Many RISC machines have a large set of logical insns. If the
4765 second operand is a NOT, put it first so we will try to split the
4766 other operand first. */
4767 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4769 rtx tem
= XEXP (x
, 0);
4770 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4771 SUBST (XEXP (x
, 1), tem
);
4777 /* Canonicalization can produce (minus A (mult B C)), where C is a
4778 constant. It may be better to try splitting (plus (mult B -C) A)
4779 instead if this isn't a multiply by a power of two. */
4780 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4781 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4782 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4784 enum machine_mode mode
= GET_MODE (x
);
4785 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4786 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4787 SUBST (*loc
, gen_rtx_PLUS (mode
, gen_rtx_MULT (mode
,
4788 XEXP (XEXP (x
, 1), 0),
4789 GEN_INT (other_int
)),
4791 return find_split_point (loc
, insn
, set_src
);
4794 /* Split at a multiply-accumulate instruction. However if this is
4795 the SET_SRC, we likely do not have such an instruction and it's
4796 worthless to try this split. */
4797 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4804 /* Otherwise, select our actions depending on our rtx class. */
4805 switch (GET_RTX_CLASS (code
))
4807 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4809 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4812 /* ... fall through ... */
4814 case RTX_COMM_ARITH
:
4816 case RTX_COMM_COMPARE
:
4817 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4820 /* ... fall through ... */
4822 /* Some machines have (and (shift ...) ...) insns. If X is not
4823 an AND, but XEXP (X, 0) is, use it as our split point. */
4824 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4825 return &XEXP (x
, 0);
4827 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4833 /* Otherwise, we don't have a split point. */
4838 /* Throughout X, replace FROM with TO, and return the result.
4839 The result is TO if X is FROM;
4840 otherwise the result is X, but its contents may have been modified.
4841 If they were modified, a record was made in undobuf so that
4842 undo_all will (among other things) return X to its original state.
4844 If the number of changes necessary is too much to record to undo,
4845 the excess changes are not made, so the result is invalid.
4846 The changes already made can still be undone.
4847 undobuf.num_undo is incremented for such changes, so by testing that
4848 the caller can tell whether the result is valid.
4850 `n_occurrences' is incremented each time FROM is replaced.
4852 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4854 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4855 by copying if `n_occurrences' is nonzero. */
4858 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
4860 enum rtx_code code
= GET_CODE (x
);
4861 enum machine_mode op0_mode
= VOIDmode
;
4866 /* Two expressions are equal if they are identical copies of a shared
4867 RTX or if they are both registers with the same register number
4870 #define COMBINE_RTX_EQUAL_P(X,Y) \
4872 || (REG_P (X) && REG_P (Y) \
4873 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4875 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4878 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4881 /* If X and FROM are the same register but different modes, they
4882 will not have been seen as equal above. However, the log links code
4883 will make a LOG_LINKS entry for that case. If we do nothing, we
4884 will try to rerecognize our original insn and, when it succeeds,
4885 we will delete the feeding insn, which is incorrect.
4887 So force this insn not to match in this (rare) case. */
4888 if (! in_dest
&& code
== REG
&& REG_P (from
)
4889 && reg_overlap_mentioned_p (x
, from
))
4890 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4892 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4893 of which may contain things that can be combined. */
4894 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4897 /* It is possible to have a subexpression appear twice in the insn.
4898 Suppose that FROM is a register that appears within TO.
4899 Then, after that subexpression has been scanned once by `subst',
4900 the second time it is scanned, TO may be found. If we were
4901 to scan TO here, we would find FROM within it and create a
4902 self-referent rtl structure which is completely wrong. */
4903 if (COMBINE_RTX_EQUAL_P (x
, to
))
4906 /* Parallel asm_operands need special attention because all of the
4907 inputs are shared across the arms. Furthermore, unsharing the
4908 rtl results in recognition failures. Failure to handle this case
4909 specially can result in circular rtl.
4911 Solve this by doing a normal pass across the first entry of the
4912 parallel, and only processing the SET_DESTs of the subsequent
4915 if (code
== PARALLEL
4916 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4917 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4919 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
4921 /* If this substitution failed, this whole thing fails. */
4922 if (GET_CODE (new_rtx
) == CLOBBER
4923 && XEXP (new_rtx
, 0) == const0_rtx
)
4926 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4928 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4930 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4933 && GET_CODE (dest
) != CC0
4934 && GET_CODE (dest
) != PC
)
4936 new_rtx
= subst (dest
, from
, to
, 0, unique_copy
);
4938 /* If this substitution failed, this whole thing fails. */
4939 if (GET_CODE (new_rtx
) == CLOBBER
4940 && XEXP (new_rtx
, 0) == const0_rtx
)
4943 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4949 len
= GET_RTX_LENGTH (code
);
4950 fmt
= GET_RTX_FORMAT (code
);
4952 /* We don't need to process a SET_DEST that is a register, CC0,
4953 or PC, so set up to skip this common case. All other cases
4954 where we want to suppress replacing something inside a
4955 SET_SRC are handled via the IN_DEST operand. */
4957 && (REG_P (SET_DEST (x
))
4958 || GET_CODE (SET_DEST (x
)) == CC0
4959 || GET_CODE (SET_DEST (x
)) == PC
))
4962 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4965 op0_mode
= GET_MODE (XEXP (x
, 0));
4967 for (i
= 0; i
< len
; i
++)
4972 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4974 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
4976 new_rtx
= (unique_copy
&& n_occurrences
4977 ? copy_rtx (to
) : to
);
4982 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0,
4985 /* If this substitution failed, this whole thing
4987 if (GET_CODE (new_rtx
) == CLOBBER
4988 && XEXP (new_rtx
, 0) == const0_rtx
)
4992 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
4995 else if (fmt
[i
] == 'e')
4997 /* If this is a register being set, ignore it. */
4998 new_rtx
= XEXP (x
, i
);
5001 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5003 || code
== STRICT_LOW_PART
))
5006 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5008 /* In general, don't install a subreg involving two
5009 modes not tieable. It can worsen register
5010 allocation, and can even make invalid reload
5011 insns, since the reg inside may need to be copied
5012 from in the outside mode, and that may be invalid
5013 if it is an fp reg copied in integer mode.
5015 We allow two exceptions to this: It is valid if
5016 it is inside another SUBREG and the mode of that
5017 SUBREG and the mode of the inside of TO is
5018 tieable and it is valid if X is a SET that copies
5021 if (GET_CODE (to
) == SUBREG
5022 && ! MODES_TIEABLE_P (GET_MODE (to
),
5023 GET_MODE (SUBREG_REG (to
)))
5024 && ! (code
== SUBREG
5025 && MODES_TIEABLE_P (GET_MODE (x
),
5026 GET_MODE (SUBREG_REG (to
))))
5028 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5031 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5033 #ifdef CANNOT_CHANGE_MODE_CLASS
5036 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5037 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5040 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5043 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5047 /* If we are in a SET_DEST, suppress most cases unless we
5048 have gone inside a MEM, in which case we want to
5049 simplify the address. We assume here that things that
5050 are actually part of the destination have their inner
5051 parts in the first expression. This is true for SUBREG,
5052 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5053 things aside from REG and MEM that should appear in a
5055 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5057 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5058 || code
== ZERO_EXTRACT
))
5060 && i
== 0), unique_copy
);
5062 /* If we found that we will have to reject this combination,
5063 indicate that by returning the CLOBBER ourselves, rather than
5064 an expression containing it. This will speed things up as
5065 well as prevent accidents where two CLOBBERs are considered
5066 to be equal, thus producing an incorrect simplification. */
5068 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5071 if (GET_CODE (x
) == SUBREG
5072 && (CONST_INT_P (new_rtx
)
5073 || GET_CODE (new_rtx
) == CONST_DOUBLE
))
5075 enum machine_mode mode
= GET_MODE (x
);
5077 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5078 GET_MODE (SUBREG_REG (x
)),
5081 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5083 else if (CONST_INT_P (new_rtx
)
5084 && GET_CODE (x
) == ZERO_EXTEND
)
5086 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5087 new_rtx
, GET_MODE (XEXP (x
, 0)));
5091 SUBST (XEXP (x
, i
), new_rtx
);
5096 /* Check if we are loading something from the constant pool via float
5097 extension; in this case we would undo compress_float_constant
5098 optimization and degenerate constant load to an immediate value. */
5099 if (GET_CODE (x
) == FLOAT_EXTEND
5100 && MEM_P (XEXP (x
, 0))
5101 && MEM_READONLY_P (XEXP (x
, 0)))
5103 rtx tmp
= avoid_constant_pool_reference (x
);
5108 /* Try to simplify X. If the simplification changed the code, it is likely
5109 that further simplification will help, so loop, but limit the number
5110 of repetitions that will be performed. */
5112 for (i
= 0; i
< 4; i
++)
5114 /* If X is sufficiently simple, don't bother trying to do anything
5116 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5117 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
5119 if (GET_CODE (x
) == code
)
5122 code
= GET_CODE (x
);
5124 /* We no longer know the original mode of operand 0 since we
5125 have changed the form of X) */
5126 op0_mode
= VOIDmode
;
5132 /* Simplify X, a piece of RTL. We just operate on the expression at the
5133 outer level; call `subst' to simplify recursively. Return the new
5136 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5137 if we are inside a SET_DEST. */
5140 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
5142 enum rtx_code code
= GET_CODE (x
);
5143 enum machine_mode mode
= GET_MODE (x
);
5147 /* If this is a commutative operation, put a constant last and a complex
5148 expression first. We don't need to do this for comparisons here. */
5149 if (COMMUTATIVE_ARITH_P (x
)
5150 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5153 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5154 SUBST (XEXP (x
, 1), temp
);
5157 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5158 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5159 things. Check for cases where both arms are testing the same
5162 Don't do anything if all operands are very simple. */
5165 && ((!OBJECT_P (XEXP (x
, 0))
5166 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5167 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5168 || (!OBJECT_P (XEXP (x
, 1))
5169 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5170 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5172 && (!OBJECT_P (XEXP (x
, 0))
5173 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5174 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5176 rtx cond
, true_rtx
, false_rtx
;
5178 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5180 /* If everything is a comparison, what we have is highly unlikely
5181 to be simpler, so don't use it. */
5182 && ! (COMPARISON_P (x
)
5183 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5185 rtx cop1
= const0_rtx
;
5186 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5188 if (cond_code
== NE
&& COMPARISON_P (cond
))
5191 /* Simplify the alternative arms; this may collapse the true and
5192 false arms to store-flag values. Be careful to use copy_rtx
5193 here since true_rtx or false_rtx might share RTL with x as a
5194 result of the if_then_else_cond call above. */
5195 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5196 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
5198 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5199 is unlikely to be simpler. */
5200 if (general_operand (true_rtx
, VOIDmode
)
5201 && general_operand (false_rtx
, VOIDmode
))
5203 enum rtx_code reversed
;
5205 /* Restarting if we generate a store-flag expression will cause
5206 us to loop. Just drop through in this case. */
5208 /* If the result values are STORE_FLAG_VALUE and zero, we can
5209 just make the comparison operation. */
5210 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5211 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5213 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5214 && ((reversed
= reversed_comparison_code_parts
5215 (cond_code
, cond
, cop1
, NULL
))
5217 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5220 /* Likewise, we can make the negate of a comparison operation
5221 if the result values are - STORE_FLAG_VALUE and zero. */
5222 else if (CONST_INT_P (true_rtx
)
5223 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5224 && false_rtx
== const0_rtx
)
5225 x
= simplify_gen_unary (NEG
, mode
,
5226 simplify_gen_relational (cond_code
,
5230 else if (CONST_INT_P (false_rtx
)
5231 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5232 && true_rtx
== const0_rtx
5233 && ((reversed
= reversed_comparison_code_parts
5234 (cond_code
, cond
, cop1
, NULL
))
5236 x
= simplify_gen_unary (NEG
, mode
,
5237 simplify_gen_relational (reversed
,
5242 return gen_rtx_IF_THEN_ELSE (mode
,
5243 simplify_gen_relational (cond_code
,
5248 true_rtx
, false_rtx
);
5250 code
= GET_CODE (x
);
5251 op0_mode
= VOIDmode
;
5256 /* Try to fold this expression in case we have constants that weren't
5259 switch (GET_RTX_CLASS (code
))
5262 if (op0_mode
== VOIDmode
)
5263 op0_mode
= GET_MODE (XEXP (x
, 0));
5264 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5267 case RTX_COMM_COMPARE
:
5269 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5270 if (cmp_mode
== VOIDmode
)
5272 cmp_mode
= GET_MODE (XEXP (x
, 1));
5273 if (cmp_mode
== VOIDmode
)
5274 cmp_mode
= op0_mode
;
5276 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5277 XEXP (x
, 0), XEXP (x
, 1));
5280 case RTX_COMM_ARITH
:
5282 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5284 case RTX_BITFIELD_OPS
:
5286 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5287 XEXP (x
, 1), XEXP (x
, 2));
5296 code
= GET_CODE (temp
);
5297 op0_mode
= VOIDmode
;
5298 mode
= GET_MODE (temp
);
5301 /* First see if we can apply the inverse distributive law. */
5302 if (code
== PLUS
|| code
== MINUS
5303 || code
== AND
|| code
== IOR
|| code
== XOR
)
5305 x
= apply_distributive_law (x
);
5306 code
= GET_CODE (x
);
5307 op0_mode
= VOIDmode
;
5310 /* If CODE is an associative operation not otherwise handled, see if we
5311 can associate some operands. This can win if they are constants or
5312 if they are logically related (i.e. (a & b) & a). */
5313 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5314 || code
== AND
|| code
== IOR
|| code
== XOR
5315 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5316 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5317 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5319 if (GET_CODE (XEXP (x
, 0)) == code
)
5321 rtx other
= XEXP (XEXP (x
, 0), 0);
5322 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5323 rtx inner_op1
= XEXP (x
, 1);
5326 /* Make sure we pass the constant operand if any as the second
5327 one if this is a commutative operation. */
5328 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5330 rtx tem
= inner_op0
;
5331 inner_op0
= inner_op1
;
5334 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5335 : code
== DIV
? MULT
5337 mode
, inner_op0
, inner_op1
);
5339 /* For commutative operations, try the other pair if that one
5341 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5343 other
= XEXP (XEXP (x
, 0), 1);
5344 inner
= simplify_binary_operation (code
, mode
,
5345 XEXP (XEXP (x
, 0), 0),
5350 return simplify_gen_binary (code
, mode
, other
, inner
);
5354 /* A little bit of algebraic simplification here. */
5358 /* Ensure that our address has any ASHIFTs converted to MULT in case
5359 address-recognizing predicates are called later. */
5360 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5361 SUBST (XEXP (x
, 0), temp
);
5365 if (op0_mode
== VOIDmode
)
5366 op0_mode
= GET_MODE (SUBREG_REG (x
));
5368 /* See if this can be moved to simplify_subreg. */
5369 if (CONSTANT_P (SUBREG_REG (x
))
5370 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5371 /* Don't call gen_lowpart if the inner mode
5372 is VOIDmode and we cannot simplify it, as SUBREG without
5373 inner mode is invalid. */
5374 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5375 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5376 return gen_lowpart (mode
, SUBREG_REG (x
));
5378 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5382 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5388 /* Don't change the mode of the MEM if that would change the meaning
5390 if (MEM_P (SUBREG_REG (x
))
5391 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5392 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
5393 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5395 /* Note that we cannot do any narrowing for non-constants since
5396 we might have been counting on using the fact that some bits were
5397 zero. We now do this in the SET. */
5402 temp
= expand_compound_operation (XEXP (x
, 0));
5404 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5405 replaced by (lshiftrt X C). This will convert
5406 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5408 if (GET_CODE (temp
) == ASHIFTRT
5409 && CONST_INT_P (XEXP (temp
, 1))
5410 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5411 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5412 INTVAL (XEXP (temp
, 1)));
5414 /* If X has only a single bit that might be nonzero, say, bit I, convert
5415 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5416 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5417 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5418 or a SUBREG of one since we'd be making the expression more
5419 complex if it was just a register. */
5422 && ! (GET_CODE (temp
) == SUBREG
5423 && REG_P (SUBREG_REG (temp
)))
5424 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5426 rtx temp1
= simplify_shift_const
5427 (NULL_RTX
, ASHIFTRT
, mode
,
5428 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5429 GET_MODE_BITSIZE (mode
) - 1 - i
),
5430 GET_MODE_BITSIZE (mode
) - 1 - i
);
5432 /* If all we did was surround TEMP with the two shifts, we
5433 haven't improved anything, so don't use it. Otherwise,
5434 we are better off with TEMP1. */
5435 if (GET_CODE (temp1
) != ASHIFTRT
5436 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5437 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5443 /* We can't handle truncation to a partial integer mode here
5444 because we don't know the real bitsize of the partial
5446 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5449 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5451 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5452 GET_MODE_MASK (mode
), 0));
5454 /* We can truncate a constant value and return it. */
5455 if (CONST_INT_P (XEXP (x
, 0)))
5456 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5458 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5459 whose value is a comparison can be replaced with a subreg if
5460 STORE_FLAG_VALUE permits. */
5461 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5462 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5463 && (temp
= get_last_value (XEXP (x
, 0)))
5464 && COMPARISON_P (temp
))
5465 return gen_lowpart (mode
, XEXP (x
, 0));
5469 /* (const (const X)) can become (const X). Do it this way rather than
5470 returning the inner CONST since CONST can be shared with a
5472 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5473 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5478 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5479 can add in an offset. find_split_point will split this address up
5480 again if it doesn't match. */
5481 if (GET_CODE (XEXP (x
, 0)) == HIGH
5482 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5488 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5489 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5490 bit-field and can be replaced by either a sign_extend or a
5491 sign_extract. The `and' may be a zero_extend and the two
5492 <c>, -<c> constants may be reversed. */
5493 if (GET_CODE (XEXP (x
, 0)) == XOR
5494 && CONST_INT_P (XEXP (x
, 1))
5495 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5496 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5497 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5498 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
5499 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5500 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5501 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5502 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5503 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5504 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5505 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5506 == (unsigned int) i
+ 1))))
5507 return simplify_shift_const
5508 (NULL_RTX
, ASHIFTRT
, mode
,
5509 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5510 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5511 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
5512 GET_MODE_BITSIZE (mode
) - (i
+ 1));
5514 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5515 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5516 the bitsize of the mode - 1. This allows simplification of
5517 "a = (b & 8) == 0;" */
5518 if (XEXP (x
, 1) == constm1_rtx
5519 && !REG_P (XEXP (x
, 0))
5520 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5521 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5522 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5523 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5524 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5525 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5526 GET_MODE_BITSIZE (mode
) - 1),
5527 GET_MODE_BITSIZE (mode
) - 1);
5529 /* If we are adding two things that have no bits in common, convert
5530 the addition into an IOR. This will often be further simplified,
5531 for example in cases like ((a & 1) + (a & 2)), which can
5534 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5535 && (nonzero_bits (XEXP (x
, 0), mode
)
5536 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5538 /* Try to simplify the expression further. */
5539 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5540 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
5542 /* If we could, great. If not, do not go ahead with the IOR
5543 replacement, since PLUS appears in many special purpose
5544 address arithmetic instructions. */
5545 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
5551 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5552 (and <foo> (const_int pow2-1)) */
5553 if (GET_CODE (XEXP (x
, 1)) == AND
5554 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5555 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5556 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5557 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5558 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5562 /* If we have (mult (plus A B) C), apply the distributive law and then
5563 the inverse distributive law to see if things simplify. This
5564 occurs mostly in addresses, often when unrolling loops. */
5566 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5568 rtx result
= distribute_and_simplify_rtx (x
, 0);
5573 /* Try simplify a*(b/c) as (a*b)/c. */
5574 if (FLOAT_MODE_P (mode
) && flag_associative_math
5575 && GET_CODE (XEXP (x
, 0)) == DIV
)
5577 rtx tem
= simplify_binary_operation (MULT
, mode
,
5578 XEXP (XEXP (x
, 0), 0),
5581 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5586 /* If this is a divide by a power of two, treat it as a shift if
5587 its first operand is a shift. */
5588 if (CONST_INT_P (XEXP (x
, 1))
5589 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
5590 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5591 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5592 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5593 || GET_CODE (XEXP (x
, 0)) == ROTATE
5594 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5595 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5599 case GT
: case GTU
: case GE
: case GEU
:
5600 case LT
: case LTU
: case LE
: case LEU
:
5601 case UNEQ
: case LTGT
:
5602 case UNGT
: case UNGE
:
5603 case UNLT
: case UNLE
:
5604 case UNORDERED
: case ORDERED
:
5605 /* If the first operand is a condition code, we can't do anything
5607 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5608 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5609 && ! CC0_P (XEXP (x
, 0))))
5611 rtx op0
= XEXP (x
, 0);
5612 rtx op1
= XEXP (x
, 1);
5613 enum rtx_code new_code
;
5615 if (GET_CODE (op0
) == COMPARE
)
5616 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5618 /* Simplify our comparison, if possible. */
5619 new_code
= simplify_comparison (code
, &op0
, &op1
);
5621 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5622 if only the low-order bit is possibly nonzero in X (such as when
5623 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5624 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5625 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5628 Remove any ZERO_EXTRACT we made when thinking this was a
5629 comparison. It may now be simpler to use, e.g., an AND. If a
5630 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5631 the call to make_compound_operation in the SET case. */
5633 if (STORE_FLAG_VALUE
== 1
5634 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5635 && op1
== const0_rtx
5636 && mode
== GET_MODE (op0
)
5637 && nonzero_bits (op0
, mode
) == 1)
5638 return gen_lowpart (mode
,
5639 expand_compound_operation (op0
));
5641 else if (STORE_FLAG_VALUE
== 1
5642 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5643 && op1
== const0_rtx
5644 && mode
== GET_MODE (op0
)
5645 && (num_sign_bit_copies (op0
, mode
)
5646 == GET_MODE_BITSIZE (mode
)))
5648 op0
= expand_compound_operation (op0
);
5649 return simplify_gen_unary (NEG
, mode
,
5650 gen_lowpart (mode
, op0
),
5654 else if (STORE_FLAG_VALUE
== 1
5655 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5656 && op1
== const0_rtx
5657 && mode
== GET_MODE (op0
)
5658 && nonzero_bits (op0
, mode
) == 1)
5660 op0
= expand_compound_operation (op0
);
5661 return simplify_gen_binary (XOR
, mode
,
5662 gen_lowpart (mode
, op0
),
5666 else if (STORE_FLAG_VALUE
== 1
5667 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5668 && op1
== const0_rtx
5669 && mode
== GET_MODE (op0
)
5670 && (num_sign_bit_copies (op0
, mode
)
5671 == GET_MODE_BITSIZE (mode
)))
5673 op0
= expand_compound_operation (op0
);
5674 return plus_constant (gen_lowpart (mode
, op0
), 1);
5677 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5679 if (STORE_FLAG_VALUE
== -1
5680 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5681 && op1
== const0_rtx
5682 && (num_sign_bit_copies (op0
, mode
)
5683 == GET_MODE_BITSIZE (mode
)))
5684 return gen_lowpart (mode
,
5685 expand_compound_operation (op0
));
5687 else if (STORE_FLAG_VALUE
== -1
5688 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5689 && op1
== const0_rtx
5690 && mode
== GET_MODE (op0
)
5691 && nonzero_bits (op0
, mode
) == 1)
5693 op0
= expand_compound_operation (op0
);
5694 return simplify_gen_unary (NEG
, mode
,
5695 gen_lowpart (mode
, op0
),
5699 else if (STORE_FLAG_VALUE
== -1
5700 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5701 && op1
== const0_rtx
5702 && mode
== GET_MODE (op0
)
5703 && (num_sign_bit_copies (op0
, mode
)
5704 == GET_MODE_BITSIZE (mode
)))
5706 op0
= expand_compound_operation (op0
);
5707 return simplify_gen_unary (NOT
, mode
,
5708 gen_lowpart (mode
, op0
),
5712 /* If X is 0/1, (eq X 0) is X-1. */
5713 else if (STORE_FLAG_VALUE
== -1
5714 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5715 && op1
== const0_rtx
5716 && mode
== GET_MODE (op0
)
5717 && nonzero_bits (op0
, mode
) == 1)
5719 op0
= expand_compound_operation (op0
);
5720 return plus_constant (gen_lowpart (mode
, op0
), -1);
5723 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5724 one bit that might be nonzero, we can convert (ne x 0) to
5725 (ashift x c) where C puts the bit in the sign bit. Remove any
5726 AND with STORE_FLAG_VALUE when we are done, since we are only
5727 going to test the sign bit. */
5728 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5729 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5730 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5731 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5732 && op1
== const0_rtx
5733 && mode
== GET_MODE (op0
)
5734 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5736 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5737 expand_compound_operation (op0
),
5738 GET_MODE_BITSIZE (mode
) - 1 - i
);
5739 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5745 /* If the code changed, return a whole new comparison. */
5746 if (new_code
!= code
)
5747 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5749 /* Otherwise, keep this operation, but maybe change its operands.
5750 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5751 SUBST (XEXP (x
, 0), op0
);
5752 SUBST (XEXP (x
, 1), op1
);
5757 return simplify_if_then_else (x
);
5763 /* If we are processing SET_DEST, we are done. */
5767 return expand_compound_operation (x
);
5770 return simplify_set (x
);
5774 return simplify_logical (x
);
5781 /* If this is a shift by a constant amount, simplify it. */
5782 if (CONST_INT_P (XEXP (x
, 1)))
5783 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5784 INTVAL (XEXP (x
, 1)));
5786 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5788 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5790 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5802 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5805 simplify_if_then_else (rtx x
)
5807 enum machine_mode mode
= GET_MODE (x
);
5808 rtx cond
= XEXP (x
, 0);
5809 rtx true_rtx
= XEXP (x
, 1);
5810 rtx false_rtx
= XEXP (x
, 2);
5811 enum rtx_code true_code
= GET_CODE (cond
);
5812 int comparison_p
= COMPARISON_P (cond
);
5815 enum rtx_code false_code
;
5818 /* Simplify storing of the truth value. */
5819 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5820 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5821 XEXP (cond
, 0), XEXP (cond
, 1));
5823 /* Also when the truth value has to be reversed. */
5825 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5826 && (reversed
= reversed_comparison (cond
, mode
)))
5829 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5830 in it is being compared against certain values. Get the true and false
5831 comparisons and see if that says anything about the value of each arm. */
5834 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5836 && REG_P (XEXP (cond
, 0)))
5839 rtx from
= XEXP (cond
, 0);
5840 rtx true_val
= XEXP (cond
, 1);
5841 rtx false_val
= true_val
;
5844 /* If FALSE_CODE is EQ, swap the codes and arms. */
5846 if (false_code
== EQ
)
5848 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5849 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5852 /* If we are comparing against zero and the expression being tested has
5853 only a single bit that might be nonzero, that is its value when it is
5854 not equal to zero. Similarly if it is known to be -1 or 0. */
5856 if (true_code
== EQ
&& true_val
== const0_rtx
5857 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5860 false_val
= GEN_INT (trunc_int_for_mode (nzb
, GET_MODE (from
)));
5862 else if (true_code
== EQ
&& true_val
== const0_rtx
5863 && (num_sign_bit_copies (from
, GET_MODE (from
))
5864 == GET_MODE_BITSIZE (GET_MODE (from
))))
5867 false_val
= constm1_rtx
;
5870 /* Now simplify an arm if we know the value of the register in the
5871 branch and it is used in the arm. Be careful due to the potential
5872 of locally-shared RTL. */
5874 if (reg_mentioned_p (from
, true_rtx
))
5875 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5877 pc_rtx
, pc_rtx
, 0, 0);
5878 if (reg_mentioned_p (from
, false_rtx
))
5879 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5881 pc_rtx
, pc_rtx
, 0, 0);
5883 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5884 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5886 true_rtx
= XEXP (x
, 1);
5887 false_rtx
= XEXP (x
, 2);
5888 true_code
= GET_CODE (cond
);
5891 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5892 reversed, do so to avoid needing two sets of patterns for
5893 subtract-and-branch insns. Similarly if we have a constant in the true
5894 arm, the false arm is the same as the first operand of the comparison, or
5895 the false arm is more complicated than the true arm. */
5898 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5899 && (true_rtx
== pc_rtx
5900 || (CONSTANT_P (true_rtx
)
5901 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5902 || true_rtx
== const0_rtx
5903 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5904 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5905 && !OBJECT_P (false_rtx
))
5906 || reg_mentioned_p (true_rtx
, false_rtx
)
5907 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5909 true_code
= reversed_comparison_code (cond
, NULL
);
5910 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5911 SUBST (XEXP (x
, 1), false_rtx
);
5912 SUBST (XEXP (x
, 2), true_rtx
);
5914 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5917 /* It is possible that the conditional has been simplified out. */
5918 true_code
= GET_CODE (cond
);
5919 comparison_p
= COMPARISON_P (cond
);
5922 /* If the two arms are identical, we don't need the comparison. */
5924 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5927 /* Convert a == b ? b : a to "a". */
5928 if (true_code
== EQ
&& ! side_effects_p (cond
)
5929 && !HONOR_NANS (mode
)
5930 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5931 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5933 else if (true_code
== NE
&& ! side_effects_p (cond
)
5934 && !HONOR_NANS (mode
)
5935 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5936 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5939 /* Look for cases where we have (abs x) or (neg (abs X)). */
5941 if (GET_MODE_CLASS (mode
) == MODE_INT
5943 && XEXP (cond
, 1) == const0_rtx
5944 && GET_CODE (false_rtx
) == NEG
5945 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
5946 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
5947 && ! side_effects_p (true_rtx
))
5952 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
5956 simplify_gen_unary (NEG
, mode
,
5957 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
5963 /* Look for MIN or MAX. */
5965 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
5967 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5968 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
5969 && ! side_effects_p (cond
))
5974 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
5977 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
5980 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
5983 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
5988 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5989 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5990 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5991 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5992 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5993 neither 1 or -1, but it isn't worth checking for. */
5995 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5997 && GET_MODE_CLASS (mode
) == MODE_INT
5998 && ! side_effects_p (x
))
6000 rtx t
= make_compound_operation (true_rtx
, SET
);
6001 rtx f
= make_compound_operation (false_rtx
, SET
);
6002 rtx cond_op0
= XEXP (cond
, 0);
6003 rtx cond_op1
= XEXP (cond
, 1);
6004 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6005 enum machine_mode m
= mode
;
6006 rtx z
= 0, c1
= NULL_RTX
;
6008 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6009 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6010 || GET_CODE (t
) == ASHIFT
6011 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6012 && rtx_equal_p (XEXP (t
, 0), f
))
6013 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6015 /* If an identity-zero op is commutative, check whether there
6016 would be a match if we swapped the operands. */
6017 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6018 || GET_CODE (t
) == XOR
)
6019 && rtx_equal_p (XEXP (t
, 1), f
))
6020 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6021 else if (GET_CODE (t
) == SIGN_EXTEND
6022 && (GET_CODE (XEXP (t
, 0)) == PLUS
6023 || GET_CODE (XEXP (t
, 0)) == MINUS
6024 || GET_CODE (XEXP (t
, 0)) == IOR
6025 || GET_CODE (XEXP (t
, 0)) == XOR
6026 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6027 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6028 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6029 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6030 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6031 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6032 && (num_sign_bit_copies (f
, GET_MODE (f
))
6034 (GET_MODE_BITSIZE (mode
)
6035 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6037 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6038 extend_op
= SIGN_EXTEND
;
6039 m
= GET_MODE (XEXP (t
, 0));
6041 else if (GET_CODE (t
) == SIGN_EXTEND
6042 && (GET_CODE (XEXP (t
, 0)) == PLUS
6043 || GET_CODE (XEXP (t
, 0)) == IOR
6044 || GET_CODE (XEXP (t
, 0)) == XOR
)
6045 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6046 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6047 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6048 && (num_sign_bit_copies (f
, GET_MODE (f
))
6050 (GET_MODE_BITSIZE (mode
)
6051 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6053 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6054 extend_op
= SIGN_EXTEND
;
6055 m
= GET_MODE (XEXP (t
, 0));
6057 else if (GET_CODE (t
) == ZERO_EXTEND
6058 && (GET_CODE (XEXP (t
, 0)) == PLUS
6059 || GET_CODE (XEXP (t
, 0)) == MINUS
6060 || GET_CODE (XEXP (t
, 0)) == IOR
6061 || GET_CODE (XEXP (t
, 0)) == XOR
6062 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6063 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6064 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6065 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6066 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6067 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6068 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6069 && ((nonzero_bits (f
, GET_MODE (f
))
6070 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6073 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6074 extend_op
= ZERO_EXTEND
;
6075 m
= GET_MODE (XEXP (t
, 0));
6077 else if (GET_CODE (t
) == ZERO_EXTEND
6078 && (GET_CODE (XEXP (t
, 0)) == PLUS
6079 || GET_CODE (XEXP (t
, 0)) == IOR
6080 || GET_CODE (XEXP (t
, 0)) == XOR
)
6081 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6082 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6083 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6084 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6085 && ((nonzero_bits (f
, GET_MODE (f
))
6086 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6089 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6090 extend_op
= ZERO_EXTEND
;
6091 m
= GET_MODE (XEXP (t
, 0));
6096 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6097 cond_op0
, cond_op1
),
6098 pc_rtx
, pc_rtx
, 0, 0);
6099 temp
= simplify_gen_binary (MULT
, m
, temp
,
6100 simplify_gen_binary (MULT
, m
, c1
,
6102 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
6103 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6105 if (extend_op
!= UNKNOWN
)
6106 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6112 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6113 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6114 negation of a single bit, we can convert this operation to a shift. We
6115 can actually do this more generally, but it doesn't seem worth it. */
6117 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6118 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6119 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6120 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
6121 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6122 == GET_MODE_BITSIZE (mode
))
6123 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
6125 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6126 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6128 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6129 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6130 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6131 && GET_MODE (XEXP (cond
, 0)) == mode
6132 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6133 == nonzero_bits (XEXP (cond
, 0), mode
)
6134 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6135 return XEXP (cond
, 0);
6140 /* Simplify X, a SET expression. Return the new expression. */
6143 simplify_set (rtx x
)
6145 rtx src
= SET_SRC (x
);
6146 rtx dest
= SET_DEST (x
);
6147 enum machine_mode mode
6148 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6152 /* (set (pc) (return)) gets written as (return). */
6153 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
6156 /* Now that we know for sure which bits of SRC we are using, see if we can
6157 simplify the expression for the object knowing that we only need the
6160 if (GET_MODE_CLASS (mode
) == MODE_INT
6161 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
6163 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, 0);
6164 SUBST (SET_SRC (x
), src
);
6167 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6168 the comparison result and try to simplify it unless we already have used
6169 undobuf.other_insn. */
6170 if ((GET_MODE_CLASS (mode
) == MODE_CC
6171 || GET_CODE (src
) == COMPARE
6173 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6174 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6175 && COMPARISON_P (*cc_use
)
6176 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6178 enum rtx_code old_code
= GET_CODE (*cc_use
);
6179 enum rtx_code new_code
;
6181 int other_changed
= 0;
6182 enum machine_mode compare_mode
= GET_MODE (dest
);
6184 if (GET_CODE (src
) == COMPARE
)
6185 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6187 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6189 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6192 new_code
= old_code
;
6193 else if (!CONSTANT_P (tmp
))
6195 new_code
= GET_CODE (tmp
);
6196 op0
= XEXP (tmp
, 0);
6197 op1
= XEXP (tmp
, 1);
6201 rtx pat
= PATTERN (other_insn
);
6202 undobuf
.other_insn
= other_insn
;
6203 SUBST (*cc_use
, tmp
);
6205 /* Attempt to simplify CC user. */
6206 if (GET_CODE (pat
) == SET
)
6208 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6209 if (new_rtx
!= NULL_RTX
)
6210 SUBST (SET_SRC (pat
), new_rtx
);
6213 /* Convert X into a no-op move. */
6214 SUBST (SET_DEST (x
), pc_rtx
);
6215 SUBST (SET_SRC (x
), pc_rtx
);
6219 /* Simplify our comparison, if possible. */
6220 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6222 #ifdef SELECT_CC_MODE
6223 /* If this machine has CC modes other than CCmode, check to see if we
6224 need to use a different CC mode here. */
6225 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6226 compare_mode
= GET_MODE (op0
);
6228 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6231 /* If the mode changed, we have to change SET_DEST, the mode in the
6232 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6233 a hard register, just build new versions with the proper mode. If it
6234 is a pseudo, we lose unless it is only time we set the pseudo, in
6235 which case we can safely change its mode. */
6236 if (compare_mode
!= GET_MODE (dest
))
6238 if (can_change_dest_mode (dest
, 0, compare_mode
))
6240 unsigned int regno
= REGNO (dest
);
6243 if (regno
< FIRST_PSEUDO_REGISTER
)
6244 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6247 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6248 new_dest
= regno_reg_rtx
[regno
];
6251 SUBST (SET_DEST (x
), new_dest
);
6252 SUBST (XEXP (*cc_use
, 0), new_dest
);
6259 #endif /* SELECT_CC_MODE */
6261 /* If the code changed, we have to build a new comparison in
6262 undobuf.other_insn. */
6263 if (new_code
!= old_code
)
6265 int other_changed_previously
= other_changed
;
6266 unsigned HOST_WIDE_INT mask
;
6267 rtx old_cc_use
= *cc_use
;
6269 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6273 /* If the only change we made was to change an EQ into an NE or
6274 vice versa, OP0 has only one bit that might be nonzero, and OP1
6275 is zero, check if changing the user of the condition code will
6276 produce a valid insn. If it won't, we can keep the original code
6277 in that insn by surrounding our operation with an XOR. */
6279 if (((old_code
== NE
&& new_code
== EQ
)
6280 || (old_code
== EQ
&& new_code
== NE
))
6281 && ! other_changed_previously
&& op1
== const0_rtx
6282 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
6283 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6285 rtx pat
= PATTERN (other_insn
), note
= 0;
6287 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6288 && ! check_asm_operands (pat
)))
6290 *cc_use
= old_cc_use
;
6293 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6294 op0
, GEN_INT (mask
));
6300 undobuf
.other_insn
= other_insn
;
6302 /* Otherwise, if we didn't previously have a COMPARE in the
6303 correct mode, we need one. */
6304 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6306 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6309 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6311 SUBST (SET_SRC (x
), op0
);
6314 /* Otherwise, update the COMPARE if needed. */
6315 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6317 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6323 /* Get SET_SRC in a form where we have placed back any
6324 compound expressions. Then do the checks below. */
6325 src
= make_compound_operation (src
, SET
);
6326 SUBST (SET_SRC (x
), src
);
6329 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6330 and X being a REG or (subreg (reg)), we may be able to convert this to
6331 (set (subreg:m2 x) (op)).
6333 We can always do this if M1 is narrower than M2 because that means that
6334 we only care about the low bits of the result.
6336 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6337 perform a narrower operation than requested since the high-order bits will
6338 be undefined. On machine where it is defined, this transformation is safe
6339 as long as M1 and M2 have the same number of words. */
6341 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6342 && !OBJECT_P (SUBREG_REG (src
))
6343 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6345 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6346 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6347 #ifndef WORD_REGISTER_OPERATIONS
6348 && (GET_MODE_SIZE (GET_MODE (src
))
6349 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6351 #ifdef CANNOT_CHANGE_MODE_CLASS
6352 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6353 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6354 GET_MODE (SUBREG_REG (src
)),
6358 || (GET_CODE (dest
) == SUBREG
6359 && REG_P (SUBREG_REG (dest
)))))
6361 SUBST (SET_DEST (x
),
6362 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6364 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6366 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6370 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6373 && GET_CODE (src
) == SUBREG
6374 && subreg_lowpart_p (src
)
6375 && (GET_MODE_BITSIZE (GET_MODE (src
))
6376 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
6378 rtx inner
= SUBREG_REG (src
);
6379 enum machine_mode inner_mode
= GET_MODE (inner
);
6381 /* Here we make sure that we don't have a sign bit on. */
6382 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
6383 && (nonzero_bits (inner
, inner_mode
)
6384 < ((unsigned HOST_WIDE_INT
) 1
6385 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
6387 SUBST (SET_SRC (x
), inner
);
6393 #ifdef LOAD_EXTEND_OP
6394 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6395 would require a paradoxical subreg. Replace the subreg with a
6396 zero_extend to avoid the reload that would otherwise be required. */
6398 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6399 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6400 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6401 && SUBREG_BYTE (src
) == 0
6402 && (GET_MODE_SIZE (GET_MODE (src
))
6403 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6404 && MEM_P (SUBREG_REG (src
)))
6407 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6408 GET_MODE (src
), SUBREG_REG (src
)));
6414 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6415 are comparing an item known to be 0 or -1 against 0, use a logical
6416 operation instead. Check for one of the arms being an IOR of the other
6417 arm with some value. We compute three terms to be IOR'ed together. In
6418 practice, at most two will be nonzero. Then we do the IOR's. */
6420 if (GET_CODE (dest
) != PC
6421 && GET_CODE (src
) == IF_THEN_ELSE
6422 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6423 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6424 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6425 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6426 #ifdef HAVE_conditional_move
6427 && ! can_conditionally_move_p (GET_MODE (src
))
6429 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6430 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6431 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6432 && ! side_effects_p (src
))
6434 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6435 ? XEXP (src
, 1) : XEXP (src
, 2));
6436 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6437 ? XEXP (src
, 2) : XEXP (src
, 1));
6438 rtx term1
= const0_rtx
, term2
, term3
;
6440 if (GET_CODE (true_rtx
) == IOR
6441 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6442 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6443 else if (GET_CODE (true_rtx
) == IOR
6444 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6445 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6446 else if (GET_CODE (false_rtx
) == IOR
6447 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6448 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6449 else if (GET_CODE (false_rtx
) == IOR
6450 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6451 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6453 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6454 XEXP (XEXP (src
, 0), 0), true_rtx
);
6455 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6456 simplify_gen_unary (NOT
, GET_MODE (src
),
6457 XEXP (XEXP (src
, 0), 0),
6462 simplify_gen_binary (IOR
, GET_MODE (src
),
6463 simplify_gen_binary (IOR
, GET_MODE (src
),
6470 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6471 whole thing fail. */
6472 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6474 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6477 /* Convert this into a field assignment operation, if possible. */
6478 return make_field_assignment (x
);
6481 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6485 simplify_logical (rtx x
)
6487 enum machine_mode mode
= GET_MODE (x
);
6488 rtx op0
= XEXP (x
, 0);
6489 rtx op1
= XEXP (x
, 1);
6491 switch (GET_CODE (x
))
6494 /* We can call simplify_and_const_int only if we don't lose
6495 any (sign) bits when converting INTVAL (op1) to
6496 "unsigned HOST_WIDE_INT". */
6497 if (CONST_INT_P (op1
)
6498 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
6499 || INTVAL (op1
) > 0))
6501 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6502 if (GET_CODE (x
) != AND
)
6509 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6510 apply the distributive law and then the inverse distributive
6511 law to see if things simplify. */
6512 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6514 rtx result
= distribute_and_simplify_rtx (x
, 0);
6518 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6520 rtx result
= distribute_and_simplify_rtx (x
, 1);
6527 /* If we have (ior (and A B) C), apply the distributive law and then
6528 the inverse distributive law to see if things simplify. */
6530 if (GET_CODE (op0
) == AND
)
6532 rtx result
= distribute_and_simplify_rtx (x
, 0);
6537 if (GET_CODE (op1
) == AND
)
6539 rtx result
= distribute_and_simplify_rtx (x
, 1);
6552 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6553 operations" because they can be replaced with two more basic operations.
6554 ZERO_EXTEND is also considered "compound" because it can be replaced with
6555 an AND operation, which is simpler, though only one operation.
6557 The function expand_compound_operation is called with an rtx expression
6558 and will convert it to the appropriate shifts and AND operations,
6559 simplifying at each stage.
6561 The function make_compound_operation is called to convert an expression
6562 consisting of shifts and ANDs into the equivalent compound expression.
6563 It is the inverse of this function, loosely speaking. */
6566 expand_compound_operation (rtx x
)
6568 unsigned HOST_WIDE_INT pos
= 0, len
;
6570 unsigned int modewidth
;
6573 switch (GET_CODE (x
))
6578 /* We can't necessarily use a const_int for a multiword mode;
6579 it depends on implicitly extending the value.
6580 Since we don't know the right way to extend it,
6581 we can't tell whether the implicit way is right.
6583 Even for a mode that is no wider than a const_int,
6584 we can't win, because we need to sign extend one of its bits through
6585 the rest of it, and we don't know which bit. */
6586 if (CONST_INT_P (XEXP (x
, 0)))
6589 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6590 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6591 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6592 reloaded. If not for that, MEM's would very rarely be safe.
6594 Reject MODEs bigger than a word, because we might not be able
6595 to reference a two-register group starting with an arbitrary register
6596 (and currently gen_lowpart might crash for a SUBREG). */
6598 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6601 /* Reject MODEs that aren't scalar integers because turning vector
6602 or complex modes into shifts causes problems. */
6604 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6607 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
6608 /* If the inner object has VOIDmode (the only way this can happen
6609 is if it is an ASM_OPERANDS), we can't do anything since we don't
6610 know how much masking to do. */
6619 /* ... fall through ... */
6622 /* If the operand is a CLOBBER, just return it. */
6623 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6626 if (!CONST_INT_P (XEXP (x
, 1))
6627 || !CONST_INT_P (XEXP (x
, 2))
6628 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6631 /* Reject MODEs that aren't scalar integers because turning vector
6632 or complex modes into shifts causes problems. */
6634 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6637 len
= INTVAL (XEXP (x
, 1));
6638 pos
= INTVAL (XEXP (x
, 2));
6640 /* This should stay within the object being extracted, fail otherwise. */
6641 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
6644 if (BITS_BIG_ENDIAN
)
6645 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6652 /* Convert sign extension to zero extension, if we know that the high
6653 bit is not set, as this is easier to optimize. It will be converted
6654 back to cheaper alternative in make_extraction. */
6655 if (GET_CODE (x
) == SIGN_EXTEND
6656 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6657 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6658 & ~(((unsigned HOST_WIDE_INT
)
6659 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6663 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6664 rtx temp2
= expand_compound_operation (temp
);
6666 /* Make sure this is a profitable operation. */
6667 if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6668 > rtx_cost (temp2
, SET
, optimize_this_for_speed_p
))
6670 else if (rtx_cost (x
, SET
, optimize_this_for_speed_p
)
6671 > rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
6677 /* We can optimize some special cases of ZERO_EXTEND. */
6678 if (GET_CODE (x
) == ZERO_EXTEND
)
6680 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6681 know that the last value didn't have any inappropriate bits
6683 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6684 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6685 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6686 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6687 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6688 return XEXP (XEXP (x
, 0), 0);
6690 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6691 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6692 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6693 && subreg_lowpart_p (XEXP (x
, 0))
6694 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6695 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6696 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6697 return SUBREG_REG (XEXP (x
, 0));
6699 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6700 is a comparison and STORE_FLAG_VALUE permits. This is like
6701 the first case, but it works even when GET_MODE (x) is larger
6702 than HOST_WIDE_INT. */
6703 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6704 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6705 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6706 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6707 <= HOST_BITS_PER_WIDE_INT
)
6708 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6709 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6710 return XEXP (XEXP (x
, 0), 0);
6712 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6713 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6714 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6715 && subreg_lowpart_p (XEXP (x
, 0))
6716 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6717 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
6718 <= HOST_BITS_PER_WIDE_INT
)
6719 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
6720 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6721 return SUBREG_REG (XEXP (x
, 0));
6725 /* If we reach here, we want to return a pair of shifts. The inner
6726 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6727 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6728 logical depending on the value of UNSIGNEDP.
6730 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6731 converted into an AND of a shift.
6733 We must check for the case where the left shift would have a negative
6734 count. This can happen in a case like (x >> 31) & 255 on machines
6735 that can't shift by a constant. On those machines, we would first
6736 combine the shift with the AND to produce a variable-position
6737 extraction. Then the constant of 31 would be substituted in to produce
6738 a such a position. */
6740 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
6741 if (modewidth
+ len
>= pos
)
6743 enum machine_mode mode
= GET_MODE (x
);
6744 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6745 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6747 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6748 tem
, modewidth
- pos
- len
);
6749 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6750 mode
, tem
, modewidth
- len
);
6752 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6753 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6754 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6757 ((HOST_WIDE_INT
) 1 << len
) - 1);
6759 /* Any other cases we can't handle. */
6762 /* If we couldn't do this for some reason, return the original
6764 if (GET_CODE (tem
) == CLOBBER
)
6770 /* X is a SET which contains an assignment of one object into
6771 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6772 or certain SUBREGS). If possible, convert it into a series of
6775 We half-heartedly support variable positions, but do not at all
6776 support variable lengths. */
6779 expand_field_assignment (const_rtx x
)
6782 rtx pos
; /* Always counts from low bit. */
6784 rtx mask
, cleared
, masked
;
6785 enum machine_mode compute_mode
;
6787 /* Loop until we find something we can't simplify. */
6790 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6791 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6793 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6794 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6795 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6797 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6798 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6800 inner
= XEXP (SET_DEST (x
), 0);
6801 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6802 pos
= XEXP (SET_DEST (x
), 2);
6804 /* A constant position should stay within the width of INNER. */
6805 if (CONST_INT_P (pos
)
6806 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6809 if (BITS_BIG_ENDIAN
)
6811 if (CONST_INT_P (pos
))
6812 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6814 else if (GET_CODE (pos
) == MINUS
6815 && CONST_INT_P (XEXP (pos
, 1))
6816 && (INTVAL (XEXP (pos
, 1))
6817 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6818 /* If position is ADJUST - X, new position is X. */
6819 pos
= XEXP (pos
, 0);
6821 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6822 GEN_INT (GET_MODE_BITSIZE (
6829 /* A SUBREG between two modes that occupy the same numbers of words
6830 can be done by moving the SUBREG to the source. */
6831 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6832 /* We need SUBREGs to compute nonzero_bits properly. */
6833 && nonzero_sign_valid
6834 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6835 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6836 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6837 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6839 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6841 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6848 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6849 inner
= SUBREG_REG (inner
);
6851 compute_mode
= GET_MODE (inner
);
6853 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6854 if (! SCALAR_INT_MODE_P (compute_mode
))
6856 enum machine_mode imode
;
6858 /* Don't do anything for vector or complex integral types. */
6859 if (! FLOAT_MODE_P (compute_mode
))
6862 /* Try to find an integral mode to pun with. */
6863 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6864 if (imode
== BLKmode
)
6867 compute_mode
= imode
;
6868 inner
= gen_lowpart (imode
, inner
);
6871 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6872 if (len
>= HOST_BITS_PER_WIDE_INT
)
6875 /* Now compute the equivalent expression. Make a copy of INNER
6876 for the SET_DEST in case it is a MEM into which we will substitute;
6877 we don't want shared RTL in that case. */
6878 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6879 cleared
= simplify_gen_binary (AND
, compute_mode
,
6880 simplify_gen_unary (NOT
, compute_mode
,
6881 simplify_gen_binary (ASHIFT
,
6886 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6887 simplify_gen_binary (
6889 gen_lowpart (compute_mode
, SET_SRC (x
)),
6893 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6894 simplify_gen_binary (IOR
, compute_mode
,
6901 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6902 it is an RTX that represents a variable starting position; otherwise,
6903 POS is the (constant) starting bit position (counted from the LSB).
6905 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6908 IN_DEST is nonzero if this is a reference in the destination of a
6909 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6910 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6913 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6914 ZERO_EXTRACT should be built even for bits starting at bit 0.
6916 MODE is the desired mode of the result (if IN_DEST == 0).
6918 The result is an RTX for the extraction or NULL_RTX if the target
6922 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6923 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6924 int in_dest
, int in_compare
)
6926 /* This mode describes the size of the storage area
6927 to fetch the overall value from. Within that, we
6928 ignore the POS lowest bits, etc. */
6929 enum machine_mode is_mode
= GET_MODE (inner
);
6930 enum machine_mode inner_mode
;
6931 enum machine_mode wanted_inner_mode
;
6932 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6933 enum machine_mode pos_mode
= word_mode
;
6934 enum machine_mode extraction_mode
= word_mode
;
6935 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6937 rtx orig_pos_rtx
= pos_rtx
;
6938 HOST_WIDE_INT orig_pos
;
6940 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6942 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6943 consider just the QI as the memory to extract from.
6944 The subreg adds or removes high bits; its mode is
6945 irrelevant to the meaning of this extraction,
6946 since POS and LEN count from the lsb. */
6947 if (MEM_P (SUBREG_REG (inner
)))
6948 is_mode
= GET_MODE (SUBREG_REG (inner
));
6949 inner
= SUBREG_REG (inner
);
6951 else if (GET_CODE (inner
) == ASHIFT
6952 && CONST_INT_P (XEXP (inner
, 1))
6953 && pos_rtx
== 0 && pos
== 0
6954 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6956 /* We're extracting the least significant bits of an rtx
6957 (ashift X (const_int C)), where LEN > C. Extract the
6958 least significant (LEN - C) bits of X, giving an rtx
6959 whose mode is MODE, then shift it left C times. */
6960 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
6961 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6962 unsignedp
, in_dest
, in_compare
);
6964 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
6967 inner_mode
= GET_MODE (inner
);
6969 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
6970 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6972 /* See if this can be done without an extraction. We never can if the
6973 width of the field is not the same as that of some integer mode. For
6974 registers, we can only avoid the extraction if the position is at the
6975 low-order bit and this is either not in the destination or we have the
6976 appropriate STRICT_LOW_PART operation available.
6978 For MEM, we can avoid an extract if the field starts on an appropriate
6979 boundary and we can change the mode of the memory reference. */
6981 if (tmode
!= BLKmode
6982 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6984 && (inner_mode
== tmode
6986 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
6987 GET_MODE_BITSIZE (inner_mode
))
6988 || reg_truncated_to_mode (tmode
, inner
))
6991 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6992 || (MEM_P (inner
) && pos_rtx
== 0
6994 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6995 : BITS_PER_UNIT
)) == 0
6996 /* We can't do this if we are widening INNER_MODE (it
6997 may not be aligned, for one thing). */
6998 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6999 && (inner_mode
== tmode
7000 || (! mode_dependent_address_p (XEXP (inner
, 0))
7001 && ! MEM_VOLATILE_P (inner
))))))
7003 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7004 field. If the original and current mode are the same, we need not
7005 adjust the offset. Otherwise, we do if bytes big endian.
7007 If INNER is not a MEM, get a piece consisting of just the field
7008 of interest (in this case POS % BITS_PER_WORD must be 0). */
7012 HOST_WIDE_INT offset
;
7014 /* POS counts from lsb, but make OFFSET count in memory order. */
7015 if (BYTES_BIG_ENDIAN
)
7016 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7018 offset
= pos
/ BITS_PER_UNIT
;
7020 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7022 else if (REG_P (inner
))
7024 if (tmode
!= inner_mode
)
7026 /* We can't call gen_lowpart in a DEST since we
7027 always want a SUBREG (see below) and it would sometimes
7028 return a new hard register. */
7031 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7033 if (WORDS_BIG_ENDIAN
7034 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7035 final_word
= ((GET_MODE_SIZE (inner_mode
)
7036 - GET_MODE_SIZE (tmode
))
7037 / UNITS_PER_WORD
) - final_word
;
7039 final_word
*= UNITS_PER_WORD
;
7040 if (BYTES_BIG_ENDIAN
&&
7041 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7042 final_word
+= (GET_MODE_SIZE (inner_mode
)
7043 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7045 /* Avoid creating invalid subregs, for example when
7046 simplifying (x>>32)&255. */
7047 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7050 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7053 new_rtx
= gen_lowpart (tmode
, inner
);
7059 new_rtx
= force_to_mode (inner
, tmode
,
7060 len
>= HOST_BITS_PER_WIDE_INT
7061 ? ~(unsigned HOST_WIDE_INT
) 0
7062 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7065 /* If this extraction is going into the destination of a SET,
7066 make a STRICT_LOW_PART unless we made a MEM. */
7069 return (MEM_P (new_rtx
) ? new_rtx
7070 : (GET_CODE (new_rtx
) != SUBREG
7071 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7072 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7077 if (CONST_INT_P (new_rtx
)
7078 || GET_CODE (new_rtx
) == CONST_DOUBLE
)
7079 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7080 mode
, new_rtx
, tmode
);
7082 /* If we know that no extraneous bits are set, and that the high
7083 bit is not set, convert the extraction to the cheaper of
7084 sign and zero extension, that are equivalent in these cases. */
7085 if (flag_expensive_optimizations
7086 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
7087 && ((nonzero_bits (new_rtx
, tmode
)
7088 & ~(((unsigned HOST_WIDE_INT
)
7089 GET_MODE_MASK (tmode
))
7093 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7094 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7096 /* Prefer ZERO_EXTENSION, since it gives more information to
7098 if (rtx_cost (temp
, SET
, optimize_this_for_speed_p
)
7099 <= rtx_cost (temp1
, SET
, optimize_this_for_speed_p
))
7104 /* Otherwise, sign- or zero-extend unless we already are in the
7107 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7111 /* Unless this is a COMPARE or we have a funny memory reference,
7112 don't do anything with zero-extending field extracts starting at
7113 the low-order bit since they are simple AND operations. */
7114 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7115 && ! in_compare
&& unsignedp
)
7118 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7119 if the position is not a constant and the length is not 1. In all
7120 other cases, we would only be going outside our object in cases when
7121 an original shift would have been undefined. */
7123 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
7124 || (pos_rtx
!= 0 && len
!= 1)))
7127 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7128 and the mode for the result. */
7129 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
7131 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
7132 pos_mode
= mode_for_extraction (EP_insv
, 2);
7133 extraction_mode
= mode_for_extraction (EP_insv
, 3);
7136 if (! in_dest
&& unsignedp
7137 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
7139 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
7140 pos_mode
= mode_for_extraction (EP_extzv
, 3);
7141 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
7144 if (! in_dest
&& ! unsignedp
7145 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
7147 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
7148 pos_mode
= mode_for_extraction (EP_extv
, 3);
7149 extraction_mode
= mode_for_extraction (EP_extv
, 0);
7152 /* Never narrow an object, since that might not be safe. */
7154 if (mode
!= VOIDmode
7155 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7156 extraction_mode
= mode
;
7158 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
7159 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7160 pos_mode
= GET_MODE (pos_rtx
);
7162 /* If this is not from memory, the desired mode is the preferred mode
7163 for an extraction pattern's first input operand, or word_mode if there
7166 wanted_inner_mode
= wanted_inner_reg_mode
;
7169 /* Be careful not to go beyond the extracted object and maintain the
7170 natural alignment of the memory. */
7171 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7172 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7173 > GET_MODE_BITSIZE (wanted_inner_mode
))
7175 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7176 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7179 /* If we have to change the mode of memory and cannot, the desired mode
7180 is EXTRACTION_MODE. */
7181 if (inner_mode
!= wanted_inner_mode
7182 && (mode_dependent_address_p (XEXP (inner
, 0))
7183 || MEM_VOLATILE_P (inner
)
7185 wanted_inner_mode
= extraction_mode
;
7190 if (BITS_BIG_ENDIAN
)
7192 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7193 BITS_BIG_ENDIAN style. If position is constant, compute new
7194 position. Otherwise, build subtraction.
7195 Note that POS is relative to the mode of the original argument.
7196 If it's a MEM we need to recompute POS relative to that.
7197 However, if we're extracting from (or inserting into) a register,
7198 we want to recompute POS relative to wanted_inner_mode. */
7199 int width
= (MEM_P (inner
)
7200 ? GET_MODE_BITSIZE (is_mode
)
7201 : GET_MODE_BITSIZE (wanted_inner_mode
));
7204 pos
= width
- len
- pos
;
7207 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
7208 /* POS may be less than 0 now, but we check for that below.
7209 Note that it can only be less than 0 if !MEM_P (inner). */
7212 /* If INNER has a wider mode, and this is a constant extraction, try to
7213 make it smaller and adjust the byte to point to the byte containing
7215 if (wanted_inner_mode
!= VOIDmode
7216 && inner_mode
!= wanted_inner_mode
7218 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7220 && ! mode_dependent_address_p (XEXP (inner
, 0))
7221 && ! MEM_VOLATILE_P (inner
))
7225 /* The computations below will be correct if the machine is big
7226 endian in both bits and bytes or little endian in bits and bytes.
7227 If it is mixed, we must adjust. */
7229 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7230 adjust OFFSET to compensate. */
7231 if (BYTES_BIG_ENDIAN
7232 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7233 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7235 /* We can now move to the desired byte. */
7236 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7237 * GET_MODE_SIZE (wanted_inner_mode
);
7238 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7240 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7241 && is_mode
!= wanted_inner_mode
)
7242 offset
= (GET_MODE_SIZE (is_mode
)
7243 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7245 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7248 /* If INNER is not memory, get it into the proper mode. If we are changing
7249 its mode, POS must be a constant and smaller than the size of the new
7251 else if (!MEM_P (inner
))
7253 /* On the LHS, don't create paradoxical subregs implicitely truncating
7254 the register unless TRULY_NOOP_TRUNCATION. */
7256 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner
)),
7257 GET_MODE_BITSIZE (wanted_inner_mode
)))
7260 if (GET_MODE (inner
) != wanted_inner_mode
7262 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7268 inner
= force_to_mode (inner
, wanted_inner_mode
,
7270 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7271 ? ~(unsigned HOST_WIDE_INT
) 0
7272 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7277 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7278 have to zero extend. Otherwise, we can just use a SUBREG. */
7280 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7282 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7284 /* If we know that no extraneous bits are set, and that the high
7285 bit is not set, convert extraction to cheaper one - either
7286 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7288 if (flag_expensive_optimizations
7289 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
7290 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7291 & ~(((unsigned HOST_WIDE_INT
)
7292 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7296 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7298 /* Prefer ZERO_EXTENSION, since it gives more information to
7300 if (rtx_cost (temp1
, SET
, optimize_this_for_speed_p
)
7301 < rtx_cost (temp
, SET
, optimize_this_for_speed_p
))
7306 else if (pos_rtx
!= 0
7307 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7308 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
7310 /* Make POS_RTX unless we already have it and it is correct. If we don't
7311 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7313 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7314 pos_rtx
= orig_pos_rtx
;
7316 else if (pos_rtx
== 0)
7317 pos_rtx
= GEN_INT (pos
);
7319 /* Make the required operation. See if we can use existing rtx. */
7320 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7321 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7323 new_rtx
= gen_lowpart (mode
, new_rtx
);
7328 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7329 with any other operations in X. Return X without that shift if so. */
7332 extract_left_shift (rtx x
, int count
)
7334 enum rtx_code code
= GET_CODE (x
);
7335 enum machine_mode mode
= GET_MODE (x
);
7341 /* This is the shift itself. If it is wide enough, we will return
7342 either the value being shifted if the shift count is equal to
7343 COUNT or a shift for the difference. */
7344 if (CONST_INT_P (XEXP (x
, 1))
7345 && INTVAL (XEXP (x
, 1)) >= count
)
7346 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7347 INTVAL (XEXP (x
, 1)) - count
);
7351 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7352 return simplify_gen_unary (code
, mode
, tem
, mode
);
7356 case PLUS
: case IOR
: case XOR
: case AND
:
7357 /* If we can safely shift this constant and we find the inner shift,
7358 make a new operation. */
7359 if (CONST_INT_P (XEXP (x
, 1))
7360 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7361 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7362 return simplify_gen_binary (code
, mode
, tem
,
7363 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7374 /* Look at the expression rooted at X. Look for expressions
7375 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7376 Form these expressions.
7378 Return the new rtx, usually just X.
7380 Also, for machines like the VAX that don't have logical shift insns,
7381 try to convert logical to arithmetic shift operations in cases where
7382 they are equivalent. This undoes the canonicalizations to logical
7383 shifts done elsewhere.
7385 We try, as much as possible, to re-use rtl expressions to save memory.
7387 IN_CODE says what kind of expression we are processing. Normally, it is
7388 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7389 being kludges), it is MEM. When processing the arguments of a comparison
7390 or a COMPARE against zero, it is COMPARE. */
7393 make_compound_operation (rtx x
, enum rtx_code in_code
)
7395 enum rtx_code code
= GET_CODE (x
);
7396 enum machine_mode mode
= GET_MODE (x
);
7397 int mode_width
= GET_MODE_BITSIZE (mode
);
7399 enum rtx_code next_code
;
7405 /* Select the code to be used in recursive calls. Once we are inside an
7406 address, we stay there. If we have a comparison, set to COMPARE,
7407 but once inside, go back to our default of SET. */
7409 next_code
= (code
== MEM
? MEM
7410 : ((code
== PLUS
|| code
== MINUS
)
7411 && SCALAR_INT_MODE_P (mode
)) ? MEM
7412 : ((code
== COMPARE
|| COMPARISON_P (x
))
7413 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7414 : in_code
== COMPARE
? SET
: in_code
);
7416 /* Process depending on the code of this operation. If NEW is set
7417 nonzero, it will be returned. */
7422 /* Convert shifts by constants into multiplications if inside
7424 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7425 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7426 && INTVAL (XEXP (x
, 1)) >= 0)
7428 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7429 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7431 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7432 if (GET_CODE (new_rtx
) == NEG
)
7434 new_rtx
= XEXP (new_rtx
, 0);
7437 multval
= trunc_int_for_mode (multval
, mode
);
7438 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, GEN_INT (multval
));
7445 lhs
= make_compound_operation (lhs
, next_code
);
7446 rhs
= make_compound_operation (rhs
, next_code
);
7447 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7448 && SCALAR_INT_MODE_P (mode
))
7450 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7452 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7454 else if (GET_CODE (lhs
) == MULT
7455 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7457 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7458 simplify_gen_unary (NEG
, mode
,
7461 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7465 SUBST (XEXP (x
, 0), lhs
);
7466 SUBST (XEXP (x
, 1), rhs
);
7469 x
= gen_lowpart (mode
, new_rtx
);
7475 lhs
= make_compound_operation (lhs
, next_code
);
7476 rhs
= make_compound_operation (rhs
, next_code
);
7477 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7478 && SCALAR_INT_MODE_P (mode
))
7480 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7482 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7484 else if (GET_CODE (rhs
) == MULT
7485 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7487 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7488 simplify_gen_unary (NEG
, mode
,
7491 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7495 SUBST (XEXP (x
, 0), lhs
);
7496 SUBST (XEXP (x
, 1), rhs
);
7499 return gen_lowpart (mode
, new_rtx
);
7502 /* If the second operand is not a constant, we can't do anything
7504 if (!CONST_INT_P (XEXP (x
, 1)))
7507 /* If the constant is a power of two minus one and the first operand
7508 is a logical right shift, make an extraction. */
7509 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7510 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7512 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7513 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7514 0, in_code
== COMPARE
);
7517 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7518 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7519 && subreg_lowpart_p (XEXP (x
, 0))
7520 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7521 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7523 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7525 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7526 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7527 0, in_code
== COMPARE
);
7529 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7530 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7531 || GET_CODE (XEXP (x
, 0)) == IOR
)
7532 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7533 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7534 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7536 /* Apply the distributive law, and then try to make extractions. */
7537 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7538 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7540 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7542 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7545 /* If we are have (and (rotate X C) M) and C is larger than the number
7546 of bits in M, this is an extraction. */
7548 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7549 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7550 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
7551 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7553 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7554 new_rtx
= make_extraction (mode
, new_rtx
,
7555 (GET_MODE_BITSIZE (mode
)
7556 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7557 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7560 /* On machines without logical shifts, if the operand of the AND is
7561 a logical shift and our mask turns off all the propagated sign
7562 bits, we can replace the logical shift with an arithmetic shift. */
7563 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7564 && !have_insn_for (LSHIFTRT
, mode
)
7565 && have_insn_for (ASHIFTRT
, mode
)
7566 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7567 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7568 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7569 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7571 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7573 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7574 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7576 gen_rtx_ASHIFTRT (mode
,
7577 make_compound_operation
7578 (XEXP (XEXP (x
, 0), 0), next_code
),
7579 XEXP (XEXP (x
, 0), 1)));
7582 /* If the constant is one less than a power of two, this might be
7583 representable by an extraction even if no shift is present.
7584 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7585 we are in a COMPARE. */
7586 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
7587 new_rtx
= make_extraction (mode
,
7588 make_compound_operation (XEXP (x
, 0),
7590 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7592 /* If we are in a comparison and this is an AND with a power of two,
7593 convert this into the appropriate bit extract. */
7594 else if (in_code
== COMPARE
7595 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
7596 new_rtx
= make_extraction (mode
,
7597 make_compound_operation (XEXP (x
, 0),
7599 i
, NULL_RTX
, 1, 1, 0, 1);
7604 /* If the sign bit is known to be zero, replace this with an
7605 arithmetic shift. */
7606 if (have_insn_for (ASHIFTRT
, mode
)
7607 && ! have_insn_for (LSHIFTRT
, mode
)
7608 && mode_width
<= HOST_BITS_PER_WIDE_INT
7609 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7611 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7612 make_compound_operation (XEXP (x
, 0),
7618 /* ... fall through ... */
7624 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7625 this is a SIGN_EXTRACT. */
7626 if (CONST_INT_P (rhs
)
7627 && GET_CODE (lhs
) == ASHIFT
7628 && CONST_INT_P (XEXP (lhs
, 1))
7629 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7630 && INTVAL (rhs
) < mode_width
)
7632 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7633 new_rtx
= make_extraction (mode
, new_rtx
,
7634 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7635 NULL_RTX
, mode_width
- INTVAL (rhs
),
7636 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7640 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7641 If so, try to merge the shifts into a SIGN_EXTEND. We could
7642 also do this for some cases of SIGN_EXTRACT, but it doesn't
7643 seem worth the effort; the case checked for occurs on Alpha. */
7646 && ! (GET_CODE (lhs
) == SUBREG
7647 && (OBJECT_P (SUBREG_REG (lhs
))))
7648 && CONST_INT_P (rhs
)
7649 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7650 && INTVAL (rhs
) < mode_width
7651 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7652 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7653 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7654 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7659 /* Call ourselves recursively on the inner expression. If we are
7660 narrowing the object and it has a different RTL code from
7661 what it originally did, do this SUBREG as a force_to_mode. */
7663 rtx inner
= SUBREG_REG (x
), simplified
;
7665 tem
= make_compound_operation (inner
, in_code
);
7668 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7672 if (GET_CODE (tem
) != GET_CODE (inner
)
7673 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7674 && subreg_lowpart_p (x
))
7676 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0, 0);
7678 /* If we have something other than a SUBREG, we might have
7679 done an expansion, so rerun ourselves. */
7680 if (GET_CODE (newer
) != SUBREG
)
7681 newer
= make_compound_operation (newer
, in_code
);
7683 /* force_to_mode can expand compounds. If it just re-expanded the
7684 compound, use gen_lowpart to convert to the desired mode. */
7685 if (rtx_equal_p (newer
, x
)
7686 /* Likewise if it re-expanded the compound only partially.
7687 This happens for SUBREG of ZERO_EXTRACT if they extract
7688 the same number of bits. */
7689 || (GET_CODE (newer
) == SUBREG
7690 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7691 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7692 && GET_CODE (inner
) == AND
7693 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7694 return gen_lowpart (GET_MODE (x
), tem
);
7710 x
= gen_lowpart (mode
, new_rtx
);
7711 code
= GET_CODE (x
);
7714 /* Now recursively process each operand of this operation. */
7715 fmt
= GET_RTX_FORMAT (code
);
7716 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7719 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7720 SUBST (XEXP (x
, i
), new_rtx
);
7722 else if (fmt
[i
] == 'E')
7723 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7725 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7726 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7730 /* If this is a commutative operation, the changes to the operands
7731 may have made it noncanonical. */
7732 if (COMMUTATIVE_ARITH_P (x
)
7733 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7736 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7737 SUBST (XEXP (x
, 1), tem
);
7743 /* Given M see if it is a value that would select a field of bits
7744 within an item, but not the entire word. Return -1 if not.
7745 Otherwise, return the starting position of the field, where 0 is the
7748 *PLEN is set to the length of the field. */
7751 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7753 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7754 int pos
= m
? ctz_hwi (m
) : -1;
7758 /* Now shift off the low-order zero bits and see if we have a
7759 power of two minus 1. */
7760 len
= exact_log2 ((m
>> pos
) + 1);
7769 /* If X refers to a register that equals REG in value, replace these
7770 references with REG. */
7772 canon_reg_for_combine (rtx x
, rtx reg
)
7779 enum rtx_code code
= GET_CODE (x
);
7780 switch (GET_RTX_CLASS (code
))
7783 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7784 if (op0
!= XEXP (x
, 0))
7785 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7790 case RTX_COMM_ARITH
:
7791 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7792 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7793 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7794 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7798 case RTX_COMM_COMPARE
:
7799 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7800 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7801 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7802 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7803 GET_MODE (op0
), op0
, op1
);
7807 case RTX_BITFIELD_OPS
:
7808 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7809 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7810 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7811 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7812 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7813 GET_MODE (op0
), op0
, op1
, op2
);
7818 if (rtx_equal_p (get_last_value (reg
), x
)
7819 || rtx_equal_p (reg
, get_last_value (x
)))
7828 fmt
= GET_RTX_FORMAT (code
);
7830 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7833 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7834 if (op
!= XEXP (x
, i
))
7844 else if (fmt
[i
] == 'E')
7847 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7849 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7850 if (op
!= XVECEXP (x
, i
, j
))
7857 XVECEXP (x
, i
, j
) = op
;
7868 /* Return X converted to MODE. If the value is already truncated to
7869 MODE we can just return a subreg even though in the general case we
7870 would need an explicit truncation. */
7873 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7875 if (!CONST_INT_P (x
)
7876 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7877 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
7878 GET_MODE_BITSIZE (GET_MODE (x
)))
7879 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7881 /* Bit-cast X into an integer mode. */
7882 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7883 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7884 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7888 return gen_lowpart (mode
, x
);
7891 /* See if X can be simplified knowing that we will only refer to it in
7892 MODE and will only refer to those bits that are nonzero in MASK.
7893 If other bits are being computed or if masking operations are done
7894 that select a superset of the bits in MASK, they can sometimes be
7897 Return a possibly simplified expression, but always convert X to
7898 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7900 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7901 are all off in X. This is used when X will be complemented, by either
7902 NOT, NEG, or XOR. */
7905 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7908 enum rtx_code code
= GET_CODE (x
);
7909 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7910 enum machine_mode op_mode
;
7911 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7914 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7915 code below will do the wrong thing since the mode of such an
7916 expression is VOIDmode.
7918 Also do nothing if X is a CLOBBER; this can happen if X was
7919 the return value from a call to gen_lowpart. */
7920 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7923 /* We want to perform the operation is its present mode unless we know
7924 that the operation is valid in MODE, in which case we do the operation
7926 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7927 && have_insn_for (code
, mode
))
7928 ? mode
: GET_MODE (x
));
7930 /* It is not valid to do a right-shift in a narrower mode
7931 than the one it came in with. */
7932 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7933 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
7934 op_mode
= GET_MODE (x
);
7936 /* Truncate MASK to fit OP_MODE. */
7938 mask
&= GET_MODE_MASK (op_mode
);
7940 /* When we have an arithmetic operation, or a shift whose count we
7941 do not know, we need to assume that all bits up to the highest-order
7942 bit in MASK will be needed. This is how we form such a mask. */
7943 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
7944 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
7946 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
7949 /* Determine what bits of X are guaranteed to be (non)zero. */
7950 nonzero
= nonzero_bits (x
, mode
);
7952 /* If none of the bits in X are needed, return a zero. */
7953 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
7956 /* If X is a CONST_INT, return a new one. Do this here since the
7957 test below will fail. */
7958 if (CONST_INT_P (x
))
7960 if (SCALAR_INT_MODE_P (mode
))
7961 return gen_int_mode (INTVAL (x
) & mask
, mode
);
7964 x
= GEN_INT (INTVAL (x
) & mask
);
7965 return gen_lowpart_common (mode
, x
);
7969 /* If X is narrower than MODE and we want all the bits in X's mode, just
7970 get X in the proper mode. */
7971 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
7972 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
7973 return gen_lowpart (mode
, x
);
7975 /* We can ignore the effect of a SUBREG if it narrows the mode or
7976 if the constant masks to zero all the bits the mode doesn't have. */
7977 if (GET_CODE (x
) == SUBREG
7978 && subreg_lowpart_p (x
)
7979 && ((GET_MODE_SIZE (GET_MODE (x
))
7980 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7982 & GET_MODE_MASK (GET_MODE (x
))
7983 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
7984 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
7986 /* The arithmetic simplifications here only work for scalar integer modes. */
7987 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
7988 return gen_lowpart_or_truncate (mode
, x
);
7993 /* If X is a (clobber (const_int)), return it since we know we are
7994 generating something that won't match. */
8001 x
= expand_compound_operation (x
);
8002 if (GET_CODE (x
) != code
)
8003 return force_to_mode (x
, mode
, mask
, next_select
);
8007 /* Similarly for a truncate. */
8008 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8011 /* If this is an AND with a constant, convert it into an AND
8012 whose constant is the AND of that constant with MASK. If it
8013 remains an AND of MASK, delete it since it is redundant. */
8015 if (CONST_INT_P (XEXP (x
, 1)))
8017 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8018 mask
& INTVAL (XEXP (x
, 1)));
8020 /* If X is still an AND, see if it is an AND with a mask that
8021 is just some low-order bits. If so, and it is MASK, we don't
8024 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8025 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8029 /* If it remains an AND, try making another AND with the bits
8030 in the mode mask that aren't in MASK turned on. If the
8031 constant in the AND is wide enough, this might make a
8032 cheaper constant. */
8034 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8035 && GET_MODE_MASK (GET_MODE (x
)) != mask
8036 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
8038 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
8039 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
8040 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
8043 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8044 number, sign extend it. */
8045 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8046 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8047 cval
|= (HOST_WIDE_INT
) -1 << width
;
8049 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8050 XEXP (x
, 0), GEN_INT (cval
));
8051 if (rtx_cost (y
, SET
, optimize_this_for_speed_p
)
8052 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
8062 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8063 low-order bits (as in an alignment operation) and FOO is already
8064 aligned to that boundary, mask C1 to that boundary as well.
8065 This may eliminate that PLUS and, later, the AND. */
8068 unsigned int width
= GET_MODE_BITSIZE (mode
);
8069 unsigned HOST_WIDE_INT smask
= mask
;
8071 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8072 number, sign extend it. */
8074 if (width
< HOST_BITS_PER_WIDE_INT
8075 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8076 smask
|= (HOST_WIDE_INT
) -1 << width
;
8078 if (CONST_INT_P (XEXP (x
, 1))
8079 && exact_log2 (- smask
) >= 0
8080 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8081 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8082 return force_to_mode (plus_constant (XEXP (x
, 0),
8083 (INTVAL (XEXP (x
, 1)) & smask
)),
8084 mode
, smask
, next_select
);
8087 /* ... fall through ... */
8090 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8091 most significant bit in MASK since carries from those bits will
8092 affect the bits we are interested in. */
8097 /* If X is (minus C Y) where C's least set bit is larger than any bit
8098 in the mask, then we may replace with (neg Y). */
8099 if (CONST_INT_P (XEXP (x
, 0))
8100 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8101 & -INTVAL (XEXP (x
, 0))))
8104 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8106 return force_to_mode (x
, mode
, mask
, next_select
);
8109 /* Similarly, if C contains every bit in the fuller_mask, then we may
8110 replace with (not Y). */
8111 if (CONST_INT_P (XEXP (x
, 0))
8112 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
8113 == INTVAL (XEXP (x
, 0))))
8115 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8116 XEXP (x
, 1), GET_MODE (x
));
8117 return force_to_mode (x
, mode
, mask
, next_select
);
8125 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8126 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8127 operation which may be a bitfield extraction. Ensure that the
8128 constant we form is not wider than the mode of X. */
8130 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8131 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8132 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8133 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8134 && CONST_INT_P (XEXP (x
, 1))
8135 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8136 + floor_log2 (INTVAL (XEXP (x
, 1))))
8137 < GET_MODE_BITSIZE (GET_MODE (x
)))
8138 && (INTVAL (XEXP (x
, 1))
8139 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8141 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8142 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8143 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8144 XEXP (XEXP (x
, 0), 0), temp
);
8145 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8146 XEXP (XEXP (x
, 0), 1));
8147 return force_to_mode (x
, mode
, mask
, next_select
);
8151 /* For most binary operations, just propagate into the operation and
8152 change the mode if we have an operation of that mode. */
8154 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8155 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8157 /* If we ended up truncating both operands, truncate the result of the
8158 operation instead. */
8159 if (GET_CODE (op0
) == TRUNCATE
8160 && GET_CODE (op1
) == TRUNCATE
)
8162 op0
= XEXP (op0
, 0);
8163 op1
= XEXP (op1
, 0);
8166 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8167 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8169 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8170 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8174 /* For left shifts, do the same, but just for the first operand.
8175 However, we cannot do anything with shifts where we cannot
8176 guarantee that the counts are smaller than the size of the mode
8177 because such a count will have a different meaning in a
8180 if (! (CONST_INT_P (XEXP (x
, 1))
8181 && INTVAL (XEXP (x
, 1)) >= 0
8182 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
8183 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8184 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8185 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
8188 /* If the shift count is a constant and we can do arithmetic in
8189 the mode of the shift, refine which bits we need. Otherwise, use the
8190 conservative form of the mask. */
8191 if (CONST_INT_P (XEXP (x
, 1))
8192 && INTVAL (XEXP (x
, 1)) >= 0
8193 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
8194 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8195 mask
>>= INTVAL (XEXP (x
, 1));
8199 op0
= gen_lowpart_or_truncate (op_mode
,
8200 force_to_mode (XEXP (x
, 0), op_mode
,
8201 mask
, next_select
));
8203 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8204 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8208 /* Here we can only do something if the shift count is a constant,
8209 this shift constant is valid for the host, and we can do arithmetic
8212 if (CONST_INT_P (XEXP (x
, 1))
8213 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8214 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
8216 rtx inner
= XEXP (x
, 0);
8217 unsigned HOST_WIDE_INT inner_mask
;
8219 /* Select the mask of the bits we need for the shift operand. */
8220 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8222 /* We can only change the mode of the shift if we can do arithmetic
8223 in the mode of the shift and INNER_MASK is no wider than the
8224 width of X's mode. */
8225 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8226 op_mode
= GET_MODE (x
);
8228 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8230 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8231 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8234 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8235 shift and AND produces only copies of the sign bit (C2 is one less
8236 than a power of two), we can do this with just a shift. */
8238 if (GET_CODE (x
) == LSHIFTRT
8239 && CONST_INT_P (XEXP (x
, 1))
8240 /* The shift puts one of the sign bit copies in the least significant
8242 && ((INTVAL (XEXP (x
, 1))
8243 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8244 >= GET_MODE_BITSIZE (GET_MODE (x
)))
8245 && exact_log2 (mask
+ 1) >= 0
8246 /* Number of bits left after the shift must be more than the mask
8248 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8249 <= GET_MODE_BITSIZE (GET_MODE (x
)))
8250 /* Must be more sign bit copies than the mask needs. */
8251 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8252 >= exact_log2 (mask
+ 1)))
8253 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8254 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
8255 - exact_log2 (mask
+ 1)));
8260 /* If we are just looking for the sign bit, we don't need this shift at
8261 all, even if it has a variable count. */
8262 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8263 && (mask
== ((unsigned HOST_WIDE_INT
) 1
8264 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8265 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8267 /* If this is a shift by a constant, get a mask that contains those bits
8268 that are not copies of the sign bit. We then have two cases: If
8269 MASK only includes those bits, this can be a logical shift, which may
8270 allow simplifications. If MASK is a single-bit field not within
8271 those bits, we are requesting a copy of the sign bit and hence can
8272 shift the sign bit to the appropriate location. */
8274 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8275 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8279 /* If the considered data is wider than HOST_WIDE_INT, we can't
8280 represent a mask for all its bits in a single scalar.
8281 But we only care about the lower bits, so calculate these. */
8283 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8285 nonzero
= ~(HOST_WIDE_INT
) 0;
8287 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8288 is the number of bits a full-width mask would have set.
8289 We need only shift if these are fewer than nonzero can
8290 hold. If not, we must keep all bits set in nonzero. */
8292 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8293 < HOST_BITS_PER_WIDE_INT
)
8294 nonzero
>>= INTVAL (XEXP (x
, 1))
8295 + HOST_BITS_PER_WIDE_INT
8296 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
8300 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8301 nonzero
>>= INTVAL (XEXP (x
, 1));
8304 if ((mask
& ~nonzero
) == 0)
8306 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8307 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8308 if (GET_CODE (x
) != ASHIFTRT
)
8309 return force_to_mode (x
, mode
, mask
, next_select
);
8312 else if ((i
= exact_log2 (mask
)) >= 0)
8314 x
= simplify_shift_const
8315 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8316 GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
8318 if (GET_CODE (x
) != ASHIFTRT
)
8319 return force_to_mode (x
, mode
, mask
, next_select
);
8323 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8324 even if the shift count isn't a constant. */
8326 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8327 XEXP (x
, 0), XEXP (x
, 1));
8331 /* If this is a zero- or sign-extension operation that just affects bits
8332 we don't care about, remove it. Be sure the call above returned
8333 something that is still a shift. */
8335 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8336 && CONST_INT_P (XEXP (x
, 1))
8337 && INTVAL (XEXP (x
, 1)) >= 0
8338 && (INTVAL (XEXP (x
, 1))
8339 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8340 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8341 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8342 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8349 /* If the shift count is constant and we can do computations
8350 in the mode of X, compute where the bits we care about are.
8351 Otherwise, we can't do anything. Don't change the mode of
8352 the shift or propagate MODE into the shift, though. */
8353 if (CONST_INT_P (XEXP (x
, 1))
8354 && INTVAL (XEXP (x
, 1)) >= 0)
8356 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8357 GET_MODE (x
), GEN_INT (mask
),
8359 if (temp
&& CONST_INT_P (temp
))
8361 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8362 INTVAL (temp
), next_select
));
8367 /* If we just want the low-order bit, the NEG isn't needed since it
8368 won't change the low-order bit. */
8370 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8372 /* We need any bits less significant than the most significant bit in
8373 MASK since carries from those bits will affect the bits we are
8379 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8380 same as the XOR case above. Ensure that the constant we form is not
8381 wider than the mode of X. */
8383 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8384 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8385 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8386 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8387 < GET_MODE_BITSIZE (GET_MODE (x
)))
8388 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8390 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8392 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8393 XEXP (XEXP (x
, 0), 0), temp
);
8394 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8395 temp
, XEXP (XEXP (x
, 0), 1));
8397 return force_to_mode (x
, mode
, mask
, next_select
);
8400 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8401 use the full mask inside the NOT. */
8405 op0
= gen_lowpart_or_truncate (op_mode
,
8406 force_to_mode (XEXP (x
, 0), mode
, mask
,
8408 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8409 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8413 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8414 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8415 which is equal to STORE_FLAG_VALUE. */
8416 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
8417 && GET_MODE (XEXP (x
, 0)) == mode
8418 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8419 && (nonzero_bits (XEXP (x
, 0), mode
)
8420 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8421 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8426 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8427 written in a narrower mode. We play it safe and do not do so. */
8430 gen_lowpart_or_truncate (GET_MODE (x
),
8431 force_to_mode (XEXP (x
, 1), mode
,
8432 mask
, next_select
)));
8434 gen_lowpart_or_truncate (GET_MODE (x
),
8435 force_to_mode (XEXP (x
, 2), mode
,
8436 mask
, next_select
)));
8443 /* Ensure we return a value of the proper mode. */
8444 return gen_lowpart_or_truncate (mode
, x
);
8447 /* Return nonzero if X is an expression that has one of two values depending on
8448 whether some other value is zero or nonzero. In that case, we return the
8449 value that is being tested, *PTRUE is set to the value if the rtx being
8450 returned has a nonzero value, and *PFALSE is set to the other alternative.
8452 If we return zero, we set *PTRUE and *PFALSE to X. */
8455 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8457 enum machine_mode mode
= GET_MODE (x
);
8458 enum rtx_code code
= GET_CODE (x
);
8459 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8460 unsigned HOST_WIDE_INT nz
;
8462 /* If we are comparing a value against zero, we are done. */
8463 if ((code
== NE
|| code
== EQ
)
8464 && XEXP (x
, 1) == const0_rtx
)
8466 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8467 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8471 /* If this is a unary operation whose operand has one of two values, apply
8472 our opcode to compute those values. */
8473 else if (UNARY_P (x
)
8474 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8476 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8477 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8478 GET_MODE (XEXP (x
, 0)));
8482 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8483 make can't possibly match and would suppress other optimizations. */
8484 else if (code
== COMPARE
)
8487 /* If this is a binary operation, see if either side has only one of two
8488 values. If either one does or if both do and they are conditional on
8489 the same value, compute the new true and false values. */
8490 else if (BINARY_P (x
))
8492 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8493 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8495 if ((cond0
!= 0 || cond1
!= 0)
8496 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8498 /* If if_then_else_cond returned zero, then true/false are the
8499 same rtl. We must copy one of them to prevent invalid rtl
8502 true0
= copy_rtx (true0
);
8503 else if (cond1
== 0)
8504 true1
= copy_rtx (true1
);
8506 if (COMPARISON_P (x
))
8508 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8510 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8515 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8516 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8519 return cond0
? cond0
: cond1
;
8522 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8523 operands is zero when the other is nonzero, and vice-versa,
8524 and STORE_FLAG_VALUE is 1 or -1. */
8526 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8527 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8529 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8531 rtx op0
= XEXP (XEXP (x
, 0), 1);
8532 rtx op1
= XEXP (XEXP (x
, 1), 1);
8534 cond0
= XEXP (XEXP (x
, 0), 0);
8535 cond1
= XEXP (XEXP (x
, 1), 0);
8537 if (COMPARISON_P (cond0
)
8538 && COMPARISON_P (cond1
)
8539 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8540 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8541 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8542 || ((swap_condition (GET_CODE (cond0
))
8543 == reversed_comparison_code (cond1
, NULL
))
8544 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8545 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8546 && ! side_effects_p (x
))
8548 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8549 *pfalse
= simplify_gen_binary (MULT
, mode
,
8551 ? simplify_gen_unary (NEG
, mode
,
8559 /* Similarly for MULT, AND and UMIN, except that for these the result
8561 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8562 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8563 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8565 cond0
= XEXP (XEXP (x
, 0), 0);
8566 cond1
= XEXP (XEXP (x
, 1), 0);
8568 if (COMPARISON_P (cond0
)
8569 && COMPARISON_P (cond1
)
8570 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8571 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8572 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8573 || ((swap_condition (GET_CODE (cond0
))
8574 == reversed_comparison_code (cond1
, NULL
))
8575 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8576 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8577 && ! side_effects_p (x
))
8579 *ptrue
= *pfalse
= const0_rtx
;
8585 else if (code
== IF_THEN_ELSE
)
8587 /* If we have IF_THEN_ELSE already, extract the condition and
8588 canonicalize it if it is NE or EQ. */
8589 cond0
= XEXP (x
, 0);
8590 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8591 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8592 return XEXP (cond0
, 0);
8593 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8595 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8596 return XEXP (cond0
, 0);
8602 /* If X is a SUBREG, we can narrow both the true and false values
8603 if the inner expression, if there is a condition. */
8604 else if (code
== SUBREG
8605 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8608 true0
= simplify_gen_subreg (mode
, true0
,
8609 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8610 false0
= simplify_gen_subreg (mode
, false0
,
8611 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8612 if (true0
&& false0
)
8620 /* If X is a constant, this isn't special and will cause confusions
8621 if we treat it as such. Likewise if it is equivalent to a constant. */
8622 else if (CONSTANT_P (x
)
8623 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8626 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8627 will be least confusing to the rest of the compiler. */
8628 else if (mode
== BImode
)
8630 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8634 /* If X is known to be either 0 or -1, those are the true and
8635 false values when testing X. */
8636 else if (x
== constm1_rtx
|| x
== const0_rtx
8637 || (mode
!= VOIDmode
8638 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
8640 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8644 /* Likewise for 0 or a single bit. */
8645 else if (SCALAR_INT_MODE_P (mode
)
8646 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8647 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8649 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8653 /* Otherwise fail; show no condition with true and false values the same. */
8654 *ptrue
= *pfalse
= x
;
8658 /* Return the value of expression X given the fact that condition COND
8659 is known to be true when applied to REG as its first operand and VAL
8660 as its second. X is known to not be shared and so can be modified in
8663 We only handle the simplest cases, and specifically those cases that
8664 arise with IF_THEN_ELSE expressions. */
8667 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8669 enum rtx_code code
= GET_CODE (x
);
8674 if (side_effects_p (x
))
8677 /* If either operand of the condition is a floating point value,
8678 then we have to avoid collapsing an EQ comparison. */
8680 && rtx_equal_p (x
, reg
)
8681 && ! FLOAT_MODE_P (GET_MODE (x
))
8682 && ! FLOAT_MODE_P (GET_MODE (val
)))
8685 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8688 /* If X is (abs REG) and we know something about REG's relationship
8689 with zero, we may be able to simplify this. */
8691 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8694 case GE
: case GT
: case EQ
:
8697 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8699 GET_MODE (XEXP (x
, 0)));
8704 /* The only other cases we handle are MIN, MAX, and comparisons if the
8705 operands are the same as REG and VAL. */
8707 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8709 if (rtx_equal_p (XEXP (x
, 0), val
))
8710 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8712 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8714 if (COMPARISON_P (x
))
8716 if (comparison_dominates_p (cond
, code
))
8717 return const_true_rtx
;
8719 code
= reversed_comparison_code (x
, NULL
);
8721 && comparison_dominates_p (cond
, code
))
8726 else if (code
== SMAX
|| code
== SMIN
8727 || code
== UMIN
|| code
== UMAX
)
8729 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8731 /* Do not reverse the condition when it is NE or EQ.
8732 This is because we cannot conclude anything about
8733 the value of 'SMAX (x, y)' when x is not equal to y,
8734 but we can when x equals y. */
8735 if ((code
== SMAX
|| code
== UMAX
)
8736 && ! (cond
== EQ
|| cond
== NE
))
8737 cond
= reverse_condition (cond
);
8742 return unsignedp
? x
: XEXP (x
, 1);
8744 return unsignedp
? x
: XEXP (x
, 0);
8746 return unsignedp
? XEXP (x
, 1) : x
;
8748 return unsignedp
? XEXP (x
, 0) : x
;
8755 else if (code
== SUBREG
)
8757 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8758 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8760 if (SUBREG_REG (x
) != r
)
8762 /* We must simplify subreg here, before we lose track of the
8763 original inner_mode. */
8764 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8765 inner_mode
, SUBREG_BYTE (x
));
8769 SUBST (SUBREG_REG (x
), r
);
8774 /* We don't have to handle SIGN_EXTEND here, because even in the
8775 case of replacing something with a modeless CONST_INT, a
8776 CONST_INT is already (supposed to be) a valid sign extension for
8777 its narrower mode, which implies it's already properly
8778 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8779 story is different. */
8780 else if (code
== ZERO_EXTEND
)
8782 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8783 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8785 if (XEXP (x
, 0) != r
)
8787 /* We must simplify the zero_extend here, before we lose
8788 track of the original inner_mode. */
8789 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8794 SUBST (XEXP (x
, 0), r
);
8800 fmt
= GET_RTX_FORMAT (code
);
8801 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8804 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8805 else if (fmt
[i
] == 'E')
8806 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8807 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8814 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8815 assignment as a field assignment. */
8818 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8820 if (x
== y
|| rtx_equal_p (x
, y
))
8823 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8826 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8827 Note that all SUBREGs of MEM are paradoxical; otherwise they
8828 would have been rewritten. */
8829 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8830 && MEM_P (SUBREG_REG (y
))
8831 && rtx_equal_p (SUBREG_REG (y
),
8832 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8835 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8836 && MEM_P (SUBREG_REG (x
))
8837 && rtx_equal_p (SUBREG_REG (x
),
8838 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8841 /* We used to see if get_last_value of X and Y were the same but that's
8842 not correct. In one direction, we'll cause the assignment to have
8843 the wrong destination and in the case, we'll import a register into this
8844 insn that might have already have been dead. So fail if none of the
8845 above cases are true. */
8849 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8850 Return that assignment if so.
8852 We only handle the most common cases. */
8855 make_field_assignment (rtx x
)
8857 rtx dest
= SET_DEST (x
);
8858 rtx src
= SET_SRC (x
);
8863 unsigned HOST_WIDE_INT len
;
8865 enum machine_mode mode
;
8867 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8868 a clear of a one-bit field. We will have changed it to
8869 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8872 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8873 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8874 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8875 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8877 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8880 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8884 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8885 && subreg_lowpart_p (XEXP (src
, 0))
8886 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8887 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8888 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8889 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8890 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8891 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8893 assign
= make_extraction (VOIDmode
, dest
, 0,
8894 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8897 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8901 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8903 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8904 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8905 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8907 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8910 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8914 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8915 SRC is an AND with all bits of that field set, then we can discard
8917 if (GET_CODE (dest
) == ZERO_EXTRACT
8918 && CONST_INT_P (XEXP (dest
, 1))
8919 && GET_CODE (src
) == AND
8920 && CONST_INT_P (XEXP (src
, 1)))
8922 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8923 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8924 unsigned HOST_WIDE_INT ze_mask
;
8926 if (width
>= HOST_BITS_PER_WIDE_INT
)
8929 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8931 /* Complete overlap. We can remove the source AND. */
8932 if ((and_mask
& ze_mask
) == ze_mask
)
8933 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
8935 /* Partial overlap. We can reduce the source AND. */
8936 if ((and_mask
& ze_mask
) != and_mask
)
8938 mode
= GET_MODE (src
);
8939 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
8940 gen_int_mode (and_mask
& ze_mask
, mode
));
8941 return gen_rtx_SET (VOIDmode
, dest
, src
);
8945 /* The other case we handle is assignments into a constant-position
8946 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8947 a mask that has all one bits except for a group of zero bits and
8948 OTHER is known to have zeros where C1 has ones, this is such an
8949 assignment. Compute the position and length from C1. Shift OTHER
8950 to the appropriate position, force it to the required mode, and
8951 make the extraction. Check for the AND in both operands. */
8953 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
8956 rhs
= expand_compound_operation (XEXP (src
, 0));
8957 lhs
= expand_compound_operation (XEXP (src
, 1));
8959 if (GET_CODE (rhs
) == AND
8960 && CONST_INT_P (XEXP (rhs
, 1))
8961 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
8962 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
8963 else if (GET_CODE (lhs
) == AND
8964 && CONST_INT_P (XEXP (lhs
, 1))
8965 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
8966 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
8970 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
8971 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
8972 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
8973 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
8976 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
8980 /* The mode to use for the source is the mode of the assignment, or of
8981 what is inside a possible STRICT_LOW_PART. */
8982 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
8983 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
8985 /* Shift OTHER right POS places and make it the source, restricting it
8986 to the proper length and mode. */
8988 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
8992 src
= force_to_mode (src
, mode
,
8993 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
8994 ? ~(unsigned HOST_WIDE_INT
) 0
8995 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
8998 /* If SRC is masked by an AND that does not make a difference in
8999 the value being stored, strip it. */
9000 if (GET_CODE (assign
) == ZERO_EXTRACT
9001 && CONST_INT_P (XEXP (assign
, 1))
9002 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9003 && GET_CODE (src
) == AND
9004 && CONST_INT_P (XEXP (src
, 1))
9005 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
9006 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
9007 src
= XEXP (src
, 0);
9009 return gen_rtx_SET (VOIDmode
, assign
, src
);
9012 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9016 apply_distributive_law (rtx x
)
9018 enum rtx_code code
= GET_CODE (x
);
9019 enum rtx_code inner_code
;
9020 rtx lhs
, rhs
, other
;
9023 /* Distributivity is not true for floating point as it can change the
9024 value. So we don't do it unless -funsafe-math-optimizations. */
9025 if (FLOAT_MODE_P (GET_MODE (x
))
9026 && ! flag_unsafe_math_optimizations
)
9029 /* The outer operation can only be one of the following: */
9030 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9031 && code
!= PLUS
&& code
!= MINUS
)
9037 /* If either operand is a primitive we can't do anything, so get out
9039 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9042 lhs
= expand_compound_operation (lhs
);
9043 rhs
= expand_compound_operation (rhs
);
9044 inner_code
= GET_CODE (lhs
);
9045 if (inner_code
!= GET_CODE (rhs
))
9048 /* See if the inner and outer operations distribute. */
9055 /* These all distribute except over PLUS. */
9056 if (code
== PLUS
|| code
== MINUS
)
9061 if (code
!= PLUS
&& code
!= MINUS
)
9066 /* This is also a multiply, so it distributes over everything. */
9070 /* Non-paradoxical SUBREGs distributes over all operations,
9071 provided the inner modes and byte offsets are the same, this
9072 is an extraction of a low-order part, we don't convert an fp
9073 operation to int or vice versa, this is not a vector mode,
9074 and we would not be converting a single-word operation into a
9075 multi-word operation. The latter test is not required, but
9076 it prevents generating unneeded multi-word operations. Some
9077 of the previous tests are redundant given the latter test,
9078 but are retained because they are required for correctness.
9080 We produce the result slightly differently in this case. */
9082 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
9083 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
9084 || ! subreg_lowpart_p (lhs
)
9085 || (GET_MODE_CLASS (GET_MODE (lhs
))
9086 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
9087 || (GET_MODE_SIZE (GET_MODE (lhs
))
9088 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
9089 || VECTOR_MODE_P (GET_MODE (lhs
))
9090 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
9091 /* Result might need to be truncated. Don't change mode if
9092 explicit truncation is needed. */
9093 || !TRULY_NOOP_TRUNCATION
9094 (GET_MODE_BITSIZE (GET_MODE (x
)),
9095 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs
)))))
9098 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
9099 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
9100 return gen_lowpart (GET_MODE (x
), tem
);
9106 /* Set LHS and RHS to the inner operands (A and B in the example
9107 above) and set OTHER to the common operand (C in the example).
9108 There is only one way to do this unless the inner operation is
9110 if (COMMUTATIVE_ARITH_P (lhs
)
9111 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9112 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9113 else if (COMMUTATIVE_ARITH_P (lhs
)
9114 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9115 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9116 else if (COMMUTATIVE_ARITH_P (lhs
)
9117 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9118 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9119 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9120 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9124 /* Form the new inner operation, seeing if it simplifies first. */
9125 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9127 /* There is one exception to the general way of distributing:
9128 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9129 if (code
== XOR
&& inner_code
== IOR
)
9132 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9135 /* We may be able to continuing distributing the result, so call
9136 ourselves recursively on the inner operation before forming the
9137 outer operation, which we return. */
9138 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9139 apply_distributive_law (tem
), other
);
9142 /* See if X is of the form (* (+ A B) C), and if so convert to
9143 (+ (* A C) (* B C)) and try to simplify.
9145 Most of the time, this results in no change. However, if some of
9146 the operands are the same or inverses of each other, simplifications
9149 For example, (and (ior A B) (not B)) can occur as the result of
9150 expanding a bit field assignment. When we apply the distributive
9151 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9152 which then simplifies to (and (A (not B))).
9154 Note that no checks happen on the validity of applying the inverse
9155 distributive law. This is pointless since we can do it in the
9156 few places where this routine is called.
9158 N is the index of the term that is decomposed (the arithmetic operation,
9159 i.e. (+ A B) in the first example above). !N is the index of the term that
9160 is distributed, i.e. of C in the first example above. */
9162 distribute_and_simplify_rtx (rtx x
, int n
)
9164 enum machine_mode mode
;
9165 enum rtx_code outer_code
, inner_code
;
9166 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9168 /* Distributivity is not true for floating point as it can change the
9169 value. So we don't do it unless -funsafe-math-optimizations. */
9170 if (FLOAT_MODE_P (GET_MODE (x
))
9171 && ! flag_unsafe_math_optimizations
)
9174 decomposed
= XEXP (x
, n
);
9175 if (!ARITHMETIC_P (decomposed
))
9178 mode
= GET_MODE (x
);
9179 outer_code
= GET_CODE (x
);
9180 distributed
= XEXP (x
, !n
);
9182 inner_code
= GET_CODE (decomposed
);
9183 inner_op0
= XEXP (decomposed
, 0);
9184 inner_op1
= XEXP (decomposed
, 1);
9186 /* Special case (and (xor B C) (not A)), which is equivalent to
9187 (xor (ior A B) (ior A C)) */
9188 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9190 distributed
= XEXP (distributed
, 0);
9196 /* Distribute the second term. */
9197 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9198 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9202 /* Distribute the first term. */
9203 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9204 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9207 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9209 if (GET_CODE (tmp
) != outer_code
9210 && rtx_cost (tmp
, SET
, optimize_this_for_speed_p
)
9211 < rtx_cost (x
, SET
, optimize_this_for_speed_p
))
9217 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9218 in MODE. Return an equivalent form, if different from (and VAROP
9219 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9222 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9223 unsigned HOST_WIDE_INT constop
)
9225 unsigned HOST_WIDE_INT nonzero
;
9226 unsigned HOST_WIDE_INT orig_constop
;
9231 orig_constop
= constop
;
9232 if (GET_CODE (varop
) == CLOBBER
)
9235 /* Simplify VAROP knowing that we will be only looking at some of the
9238 Note by passing in CONSTOP, we guarantee that the bits not set in
9239 CONSTOP are not significant and will never be examined. We must
9240 ensure that is the case by explicitly masking out those bits
9241 before returning. */
9242 varop
= force_to_mode (varop
, mode
, constop
, 0);
9244 /* If VAROP is a CLOBBER, we will fail so return it. */
9245 if (GET_CODE (varop
) == CLOBBER
)
9248 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9249 to VAROP and return the new constant. */
9250 if (CONST_INT_P (varop
))
9251 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9253 /* See what bits may be nonzero in VAROP. Unlike the general case of
9254 a call to nonzero_bits, here we don't care about bits outside
9257 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9259 /* Turn off all bits in the constant that are known to already be zero.
9260 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9261 which is tested below. */
9265 /* If we don't have any bits left, return zero. */
9269 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9270 a power of two, we can replace this with an ASHIFT. */
9271 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9272 && (i
= exact_log2 (constop
)) >= 0)
9273 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9275 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9276 or XOR, then try to apply the distributive law. This may eliminate
9277 operations if either branch can be simplified because of the AND.
9278 It may also make some cases more complex, but those cases probably
9279 won't match a pattern either with or without this. */
9281 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9285 apply_distributive_law
9286 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9287 simplify_and_const_int (NULL_RTX
,
9291 simplify_and_const_int (NULL_RTX
,
9296 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9297 the AND and see if one of the operands simplifies to zero. If so, we
9298 may eliminate it. */
9300 if (GET_CODE (varop
) == PLUS
9301 && exact_log2 (constop
+ 1) >= 0)
9305 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9306 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9307 if (o0
== const0_rtx
)
9309 if (o1
== const0_rtx
)
9313 /* Make a SUBREG if necessary. If we can't make it, fail. */
9314 varop
= gen_lowpart (mode
, varop
);
9315 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9318 /* If we are only masking insignificant bits, return VAROP. */
9319 if (constop
== nonzero
)
9322 if (varop
== orig_varop
&& constop
== orig_constop
)
9325 /* Otherwise, return an AND. */
9326 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9330 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9333 Return an equivalent form, if different from X. Otherwise, return X. If
9334 X is zero, we are to always construct the equivalent form. */
9337 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9338 unsigned HOST_WIDE_INT constop
)
9340 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9345 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9346 gen_int_mode (constop
, mode
));
9347 if (GET_MODE (x
) != mode
)
9348 x
= gen_lowpart (mode
, x
);
9352 /* Given a REG, X, compute which bits in X can be nonzero.
9353 We don't care about bits outside of those defined in MODE.
9355 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9356 a shift, AND, or zero_extract, we can do better. */
9359 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9360 const_rtx known_x ATTRIBUTE_UNUSED
,
9361 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9362 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9363 unsigned HOST_WIDE_INT
*nonzero
)
9368 /* If X is a register whose nonzero bits value is current, use it.
9369 Otherwise, if X is a register whose value we can find, use that
9370 value. Otherwise, use the previously-computed global nonzero bits
9371 for this register. */
9373 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9374 if (rsp
->last_set_value
!= 0
9375 && (rsp
->last_set_mode
== mode
9376 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9377 && GET_MODE_CLASS (mode
) == MODE_INT
))
9378 && ((rsp
->last_set_label
>= label_tick_ebb_start
9379 && rsp
->last_set_label
< label_tick
)
9380 || (rsp
->last_set_label
== label_tick
9381 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9382 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9383 && REG_N_SETS (REGNO (x
)) == 1
9385 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9387 *nonzero
&= rsp
->last_set_nonzero_bits
;
9391 tem
= get_last_value (x
);
9395 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9396 /* If X is narrower than MODE and TEM is a non-negative
9397 constant that would appear negative in the mode of X,
9398 sign-extend it for use in reg_nonzero_bits because some
9399 machines (maybe most) will actually do the sign-extension
9400 and this is the conservative approach.
9402 ??? For 2.5, try to tighten up the MD files in this regard
9403 instead of this kludge. */
9405 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
9406 && CONST_INT_P (tem
)
9408 && 0 != (INTVAL (tem
)
9409 & ((HOST_WIDE_INT
) 1
9410 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
9411 tem
= GEN_INT (INTVAL (tem
)
9412 | ((HOST_WIDE_INT
) (-1)
9413 << GET_MODE_BITSIZE (GET_MODE (x
))));
9417 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9419 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9421 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
9422 /* We don't know anything about the upper bits. */
9423 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9430 /* Return the number of bits at the high-order end of X that are known to
9431 be equal to the sign bit. X will be used in mode MODE; if MODE is
9432 VOIDmode, X will be used in its own mode. The returned value will always
9433 be between 1 and the number of bits in MODE. */
9436 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9437 const_rtx known_x ATTRIBUTE_UNUSED
,
9438 enum machine_mode known_mode
9440 unsigned int known_ret ATTRIBUTE_UNUSED
,
9441 unsigned int *result
)
9446 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
9447 if (rsp
->last_set_value
!= 0
9448 && rsp
->last_set_mode
== mode
9449 && ((rsp
->last_set_label
>= label_tick_ebb_start
9450 && rsp
->last_set_label
< label_tick
)
9451 || (rsp
->last_set_label
== label_tick
9452 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9453 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9454 && REG_N_SETS (REGNO (x
)) == 1
9456 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9458 *result
= rsp
->last_set_sign_bit_copies
;
9462 tem
= get_last_value (x
);
9466 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9467 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
9468 *result
= rsp
->sign_bit_copies
;
9473 /* Return the number of "extended" bits there are in X, when interpreted
9474 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9475 unsigned quantities, this is the number of high-order zero bits.
9476 For signed quantities, this is the number of copies of the sign bit
9477 minus 1. In both case, this function returns the number of "spare"
9478 bits. For example, if two quantities for which this function returns
9479 at least 1 are added, the addition is known not to overflow.
9481 This function will always return 0 unless called during combine, which
9482 implies that it must be called from a define_split. */
9485 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9487 if (nonzero_sign_valid
== 0)
9491 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9492 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
9493 - floor_log2 (nonzero_bits (x
, mode
)))
9495 : num_sign_bit_copies (x
, mode
) - 1);
9498 /* This function is called from `simplify_shift_const' to merge two
9499 outer operations. Specifically, we have already found that we need
9500 to perform operation *POP0 with constant *PCONST0 at the outermost
9501 position. We would now like to also perform OP1 with constant CONST1
9502 (with *POP0 being done last).
9504 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9505 the resulting operation. *PCOMP_P is set to 1 if we would need to
9506 complement the innermost operand, otherwise it is unchanged.
9508 MODE is the mode in which the operation will be done. No bits outside
9509 the width of this mode matter. It is assumed that the width of this mode
9510 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9512 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9513 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9514 result is simply *PCONST0.
9516 If the resulting operation cannot be expressed as one operation, we
9517 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9520 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9522 enum rtx_code op0
= *pop0
;
9523 HOST_WIDE_INT const0
= *pconst0
;
9525 const0
&= GET_MODE_MASK (mode
);
9526 const1
&= GET_MODE_MASK (mode
);
9528 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9532 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9535 if (op1
== UNKNOWN
|| op0
== SET
)
9538 else if (op0
== UNKNOWN
)
9539 op0
= op1
, const0
= const1
;
9541 else if (op0
== op1
)
9565 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9566 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9569 /* If the two constants aren't the same, we can't do anything. The
9570 remaining six cases can all be done. */
9571 else if (const0
!= const1
)
9579 /* (a & b) | b == b */
9581 else /* op1 == XOR */
9582 /* (a ^ b) | b == a | b */
9588 /* (a & b) ^ b == (~a) & b */
9589 op0
= AND
, *pcomp_p
= 1;
9590 else /* op1 == IOR */
9591 /* (a | b) ^ b == a & ~b */
9592 op0
= AND
, const0
= ~const0
;
9597 /* (a | b) & b == b */
9599 else /* op1 == XOR */
9600 /* (a ^ b) & b) == (~a) & b */
9607 /* Check for NO-OP cases. */
9608 const0
&= GET_MODE_MASK (mode
);
9610 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9612 else if (const0
== 0 && op0
== AND
)
9614 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9620 /* ??? Slightly redundant with the above mask, but not entirely.
9621 Moving this above means we'd have to sign-extend the mode mask
9622 for the final test. */
9623 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9624 *pconst0
= trunc_int_for_mode (const0
, mode
);
9629 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9630 the shift in. The original shift operation CODE is performed on OP in
9631 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9632 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9633 result of the shift is subject to operation OUTER_CODE with operand
9636 static enum machine_mode
9637 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9638 enum machine_mode orig_mode
, enum machine_mode mode
,
9639 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9641 if (orig_mode
== mode
)
9643 gcc_assert (GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (orig_mode
));
9645 /* In general we can't perform in wider mode for right shift and rotate. */
9649 /* We can still widen if the bits brought in from the left are identical
9650 to the sign bit of ORIG_MODE. */
9651 if (num_sign_bit_copies (op
, mode
)
9652 > (unsigned) (GET_MODE_BITSIZE (mode
)
9653 - GET_MODE_BITSIZE (orig_mode
)))
9658 /* Similarly here but with zero bits. */
9659 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9660 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9663 /* We can also widen if the bits brought in will be masked off. This
9664 operation is performed in ORIG_MODE. */
9665 if (outer_code
== AND
)
9667 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9670 && GET_MODE_BITSIZE (orig_mode
) - care_bits
>= count
)
9686 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9687 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9688 simplify it. Otherwise, return a simplified value.
9690 The shift is normally computed in the widest mode we find in VAROP, as
9691 long as it isn't a different number of words than RESULT_MODE. Exceptions
9692 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9695 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9696 rtx varop
, int orig_count
)
9698 enum rtx_code orig_code
= code
;
9699 rtx orig_varop
= varop
;
9701 enum machine_mode mode
= result_mode
;
9702 enum machine_mode shift_mode
, tmode
;
9703 unsigned int mode_words
9704 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9705 /* We form (outer_op (code varop count) (outer_const)). */
9706 enum rtx_code outer_op
= UNKNOWN
;
9707 HOST_WIDE_INT outer_const
= 0;
9708 int complement_p
= 0;
9711 /* Make sure and truncate the "natural" shift on the way in. We don't
9712 want to do this inside the loop as it makes it more difficult to
9714 if (SHIFT_COUNT_TRUNCATED
)
9715 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9717 /* If we were given an invalid count, don't do anything except exactly
9718 what was requested. */
9720 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9725 /* Unless one of the branches of the `if' in this loop does a `continue',
9726 we will `break' the loop after the `if'. */
9730 /* If we have an operand of (clobber (const_int 0)), fail. */
9731 if (GET_CODE (varop
) == CLOBBER
)
9734 /* Convert ROTATERT to ROTATE. */
9735 if (code
== ROTATERT
)
9737 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9739 if (VECTOR_MODE_P (result_mode
))
9740 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9742 count
= bitsize
- count
;
9745 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9746 mode
, outer_op
, outer_const
);
9748 /* Handle cases where the count is greater than the size of the mode
9749 minus 1. For ASHIFT, use the size minus one as the count (this can
9750 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9751 take the count modulo the size. For other shifts, the result is
9754 Since these shifts are being produced by the compiler by combining
9755 multiple operations, each of which are defined, we know what the
9756 result is supposed to be. */
9758 if (count
> (GET_MODE_BITSIZE (shift_mode
) - 1))
9760 if (code
== ASHIFTRT
)
9761 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9762 else if (code
== ROTATE
|| code
== ROTATERT
)
9763 count
%= GET_MODE_BITSIZE (shift_mode
);
9766 /* We can't simply return zero because there may be an
9774 /* If we discovered we had to complement VAROP, leave. Making a NOT
9775 here would cause an infinite loop. */
9779 /* An arithmetic right shift of a quantity known to be -1 or 0
9781 if (code
== ASHIFTRT
9782 && (num_sign_bit_copies (varop
, shift_mode
)
9783 == GET_MODE_BITSIZE (shift_mode
)))
9789 /* If we are doing an arithmetic right shift and discarding all but
9790 the sign bit copies, this is equivalent to doing a shift by the
9791 bitsize minus one. Convert it into that shift because it will often
9792 allow other simplifications. */
9794 if (code
== ASHIFTRT
9795 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9796 >= GET_MODE_BITSIZE (shift_mode
)))
9797 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9799 /* We simplify the tests below and elsewhere by converting
9800 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9801 `make_compound_operation' will convert it to an ASHIFTRT for
9802 those machines (such as VAX) that don't have an LSHIFTRT. */
9803 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9805 && ((nonzero_bits (varop
, shift_mode
)
9806 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9810 if (((code
== LSHIFTRT
9811 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9812 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9814 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9815 && !((nonzero_bits (varop
, shift_mode
) << count
)
9816 & GET_MODE_MASK (shift_mode
))))
9817 && !side_effects_p (varop
))
9820 switch (GET_CODE (varop
))
9826 new_rtx
= expand_compound_operation (varop
);
9827 if (new_rtx
!= varop
)
9835 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9836 minus the width of a smaller mode, we can do this with a
9837 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9838 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9839 && ! mode_dependent_address_p (XEXP (varop
, 0))
9840 && ! MEM_VOLATILE_P (varop
)
9841 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9842 MODE_INT
, 1)) != BLKmode
)
9844 new_rtx
= adjust_address_nv (varop
, tmode
,
9845 BYTES_BIG_ENDIAN
? 0
9846 : count
/ BITS_PER_UNIT
);
9848 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9849 : ZERO_EXTEND
, mode
, new_rtx
);
9856 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9857 the same number of words as what we've seen so far. Then store
9858 the widest mode in MODE. */
9859 if (subreg_lowpart_p (varop
)
9860 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9861 > GET_MODE_SIZE (GET_MODE (varop
)))
9862 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9863 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9865 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9866 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9868 varop
= SUBREG_REG (varop
);
9869 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9870 mode
= GET_MODE (varop
);
9876 /* Some machines use MULT instead of ASHIFT because MULT
9877 is cheaper. But it is still better on those machines to
9878 merge two shifts into one. */
9879 if (CONST_INT_P (XEXP (varop
, 1))
9880 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9883 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9885 GEN_INT (exact_log2 (
9886 INTVAL (XEXP (varop
, 1)))));
9892 /* Similar, for when divides are cheaper. */
9893 if (CONST_INT_P (XEXP (varop
, 1))
9894 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9897 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9899 GEN_INT (exact_log2 (
9900 INTVAL (XEXP (varop
, 1)))));
9906 /* If we are extracting just the sign bit of an arithmetic
9907 right shift, that shift is not needed. However, the sign
9908 bit of a wider mode may be different from what would be
9909 interpreted as the sign bit in a narrower mode, so, if
9910 the result is narrower, don't discard the shift. */
9911 if (code
== LSHIFTRT
9912 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9913 && (GET_MODE_BITSIZE (result_mode
)
9914 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9916 varop
= XEXP (varop
, 0);
9920 /* ... fall through ... */
9925 /* Here we have two nested shifts. The result is usually the
9926 AND of a new shift with a mask. We compute the result below. */
9927 if (CONST_INT_P (XEXP (varop
, 1))
9928 && INTVAL (XEXP (varop
, 1)) >= 0
9929 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9930 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9931 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9932 && !VECTOR_MODE_P (result_mode
))
9934 enum rtx_code first_code
= GET_CODE (varop
);
9935 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9936 unsigned HOST_WIDE_INT mask
;
9939 /* We have one common special case. We can't do any merging if
9940 the inner code is an ASHIFTRT of a smaller mode. However, if
9941 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9942 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9943 we can convert it to
9944 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9945 This simplifies certain SIGN_EXTEND operations. */
9946 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9947 && count
== (GET_MODE_BITSIZE (result_mode
)
9948 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9950 /* C3 has the low-order C1 bits zero. */
9952 mask
= (GET_MODE_MASK (mode
)
9953 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9955 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9956 XEXP (varop
, 0), mask
);
9957 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9959 count
= first_count
;
9964 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9965 than C1 high-order bits equal to the sign bit, we can convert
9966 this to either an ASHIFT or an ASHIFTRT depending on the
9969 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9971 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9972 && GET_MODE (varop
) == shift_mode
9973 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9976 varop
= XEXP (varop
, 0);
9977 count
-= first_count
;
9987 /* There are some cases we can't do. If CODE is ASHIFTRT,
9988 we can only do this if FIRST_CODE is also ASHIFTRT.
9990 We can't do the case when CODE is ROTATE and FIRST_CODE is
9993 If the mode of this shift is not the mode of the outer shift,
9994 we can't do this if either shift is a right shift or ROTATE.
9996 Finally, we can't do any of these if the mode is too wide
9997 unless the codes are the same.
9999 Handle the case where the shift codes are the same
10002 if (code
== first_code
)
10004 if (GET_MODE (varop
) != result_mode
10005 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10006 || code
== ROTATE
))
10009 count
+= first_count
;
10010 varop
= XEXP (varop
, 0);
10014 if (code
== ASHIFTRT
10015 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10016 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
10017 || (GET_MODE (varop
) != result_mode
10018 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10019 || first_code
== ROTATE
10020 || code
== ROTATE
)))
10023 /* To compute the mask to apply after the shift, shift the
10024 nonzero bits of the inner shift the same way the
10025 outer shift will. */
10027 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10030 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10033 /* Give up if we can't compute an outer operation to use. */
10035 || !CONST_INT_P (mask_rtx
)
10036 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10038 result_mode
, &complement_p
))
10041 /* If the shifts are in the same direction, we add the
10042 counts. Otherwise, we subtract them. */
10043 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10044 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10045 count
+= first_count
;
10047 count
-= first_count
;
10049 /* If COUNT is positive, the new shift is usually CODE,
10050 except for the two exceptions below, in which case it is
10051 FIRST_CODE. If the count is negative, FIRST_CODE should
10054 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10055 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10057 else if (count
< 0)
10058 code
= first_code
, count
= -count
;
10060 varop
= XEXP (varop
, 0);
10064 /* If we have (A << B << C) for any shift, we can convert this to
10065 (A << C << B). This wins if A is a constant. Only try this if
10066 B is not a constant. */
10068 else if (GET_CODE (varop
) == code
10069 && CONST_INT_P (XEXP (varop
, 0))
10070 && !CONST_INT_P (XEXP (varop
, 1)))
10072 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10075 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10082 if (VECTOR_MODE_P (mode
))
10085 /* Make this fit the case below. */
10086 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
10087 GEN_INT (GET_MODE_MASK (mode
)));
10093 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10094 with C the size of VAROP - 1 and the shift is logical if
10095 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10096 we have an (le X 0) operation. If we have an arithmetic shift
10097 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10098 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10100 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10101 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10102 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10103 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10104 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10105 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10108 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10111 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10112 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10117 /* If we have (shift (logical)), move the logical to the outside
10118 to allow it to possibly combine with another logical and the
10119 shift to combine with another shift. This also canonicalizes to
10120 what a ZERO_EXTRACT looks like. Also, some machines have
10121 (and (shift)) insns. */
10123 if (CONST_INT_P (XEXP (varop
, 1))
10124 /* We can't do this if we have (ashiftrt (xor)) and the
10125 constant has its sign bit set in shift_mode. */
10126 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10127 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10129 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10131 GEN_INT (count
))) != 0
10132 && CONST_INT_P (new_rtx
)
10133 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10134 INTVAL (new_rtx
), result_mode
, &complement_p
))
10136 varop
= XEXP (varop
, 0);
10140 /* If we can't do that, try to simplify the shift in each arm of the
10141 logical expression, make a new logical expression, and apply
10142 the inverse distributive law. This also can't be done
10143 for some (ashiftrt (xor)). */
10144 if (CONST_INT_P (XEXP (varop
, 1))
10145 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10146 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10149 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10150 XEXP (varop
, 0), count
);
10151 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10152 XEXP (varop
, 1), count
);
10154 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10156 varop
= apply_distributive_law (varop
);
10164 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10165 says that the sign bit can be tested, FOO has mode MODE, C is
10166 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10167 that may be nonzero. */
10168 if (code
== LSHIFTRT
10169 && XEXP (varop
, 1) == const0_rtx
10170 && GET_MODE (XEXP (varop
, 0)) == result_mode
10171 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10172 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10173 && STORE_FLAG_VALUE
== -1
10174 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10175 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10176 (HOST_WIDE_INT
) 1, result_mode
,
10179 varop
= XEXP (varop
, 0);
10186 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10187 than the number of bits in the mode is equivalent to A. */
10188 if (code
== LSHIFTRT
10189 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10190 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10192 varop
= XEXP (varop
, 0);
10197 /* NEG commutes with ASHIFT since it is multiplication. Move the
10198 NEG outside to allow shifts to combine. */
10200 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
10201 (HOST_WIDE_INT
) 0, result_mode
,
10204 varop
= XEXP (varop
, 0);
10210 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10211 is one less than the number of bits in the mode is
10212 equivalent to (xor A 1). */
10213 if (code
== LSHIFTRT
10214 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10215 && XEXP (varop
, 1) == constm1_rtx
10216 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10217 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10218 (HOST_WIDE_INT
) 1, result_mode
,
10222 varop
= XEXP (varop
, 0);
10226 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10227 that might be nonzero in BAR are those being shifted out and those
10228 bits are known zero in FOO, we can replace the PLUS with FOO.
10229 Similarly in the other operand order. This code occurs when
10230 we are computing the size of a variable-size array. */
10232 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10233 && count
< HOST_BITS_PER_WIDE_INT
10234 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10235 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10236 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10238 varop
= XEXP (varop
, 0);
10241 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10242 && count
< HOST_BITS_PER_WIDE_INT
10243 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
10244 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10246 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10247 & nonzero_bits (XEXP (varop
, 1),
10250 varop
= XEXP (varop
, 1);
10254 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10256 && CONST_INT_P (XEXP (varop
, 1))
10257 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10259 GEN_INT (count
))) != 0
10260 && CONST_INT_P (new_rtx
)
10261 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10262 INTVAL (new_rtx
), result_mode
, &complement_p
))
10264 varop
= XEXP (varop
, 0);
10268 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10269 signbit', and attempt to change the PLUS to an XOR and move it to
10270 the outer operation as is done above in the AND/IOR/XOR case
10271 leg for shift(logical). See details in logical handling above
10272 for reasoning in doing so. */
10273 if (code
== LSHIFTRT
10274 && CONST_INT_P (XEXP (varop
, 1))
10275 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10276 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10278 GEN_INT (count
))) != 0
10279 && CONST_INT_P (new_rtx
)
10280 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10281 INTVAL (new_rtx
), result_mode
, &complement_p
))
10283 varop
= XEXP (varop
, 0);
10290 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10291 with C the size of VAROP - 1 and the shift is logical if
10292 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10293 we have a (gt X 0) operation. If the shift is arithmetic with
10294 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10295 we have a (neg (gt X 0)) operation. */
10297 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10298 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10299 && count
== (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
10300 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10301 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10302 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10303 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10306 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10309 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10310 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10317 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10318 if the truncate does not affect the value. */
10319 if (code
== LSHIFTRT
10320 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10321 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10322 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10323 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
10324 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
10326 rtx varop_inner
= XEXP (varop
, 0);
10329 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10330 XEXP (varop_inner
, 0),
10332 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10333 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10346 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10347 outer_op
, outer_const
);
10349 /* We have now finished analyzing the shift. The result should be
10350 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10351 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10352 to the result of the shift. OUTER_CONST is the relevant constant,
10353 but we must turn off all bits turned off in the shift. */
10355 if (outer_op
== UNKNOWN
10356 && orig_code
== code
&& orig_count
== count
10357 && varop
== orig_varop
10358 && shift_mode
== GET_MODE (varop
))
10361 /* Make a SUBREG if necessary. If we can't make it, fail. */
10362 varop
= gen_lowpart (shift_mode
, varop
);
10363 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10366 /* If we have an outer operation and we just made a shift, it is
10367 possible that we could have simplified the shift were it not
10368 for the outer operation. So try to do the simplification
10371 if (outer_op
!= UNKNOWN
)
10372 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10377 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10379 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10380 turn off all the bits that the shift would have turned off. */
10381 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10382 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10383 GET_MODE_MASK (result_mode
) >> orig_count
);
10385 /* Do the remainder of the processing in RESULT_MODE. */
10386 x
= gen_lowpart_or_truncate (result_mode
, x
);
10388 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10391 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10393 if (outer_op
!= UNKNOWN
)
10395 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10396 && GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10397 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10399 if (outer_op
== AND
)
10400 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10401 else if (outer_op
== SET
)
10403 /* This means that we have determined that the result is
10404 equivalent to a constant. This should be rare. */
10405 if (!side_effects_p (x
))
10406 x
= GEN_INT (outer_const
);
10408 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10409 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10411 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10412 GEN_INT (outer_const
));
10418 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10419 The result of the shift is RESULT_MODE. If we cannot simplify it,
10420 return X or, if it is NULL, synthesize the expression with
10421 simplify_gen_binary. Otherwise, return a simplified value.
10423 The shift is normally computed in the widest mode we find in VAROP, as
10424 long as it isn't a different number of words than RESULT_MODE. Exceptions
10425 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10428 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10429 rtx varop
, int count
)
10431 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10436 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10437 if (GET_MODE (x
) != result_mode
)
10438 x
= gen_lowpart (result_mode
, x
);
10443 /* Like recog, but we receive the address of a pointer to a new pattern.
10444 We try to match the rtx that the pointer points to.
10445 If that fails, we may try to modify or replace the pattern,
10446 storing the replacement into the same pointer object.
10448 Modifications include deletion or addition of CLOBBERs.
10450 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10451 the CLOBBERs are placed.
10453 The value is the final insn code from the pattern ultimately matched,
10457 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10459 rtx pat
= *pnewpat
;
10460 int insn_code_number
;
10461 int num_clobbers_to_add
= 0;
10464 rtx old_notes
, old_pat
;
10466 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10467 we use to indicate that something didn't match. If we find such a
10468 thing, force rejection. */
10469 if (GET_CODE (pat
) == PARALLEL
)
10470 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10471 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10472 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10475 old_pat
= PATTERN (insn
);
10476 old_notes
= REG_NOTES (insn
);
10477 PATTERN (insn
) = pat
;
10478 REG_NOTES (insn
) = 0;
10480 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10481 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10483 if (insn_code_number
< 0)
10484 fputs ("Failed to match this instruction:\n", dump_file
);
10486 fputs ("Successfully matched this instruction:\n", dump_file
);
10487 print_rtl_single (dump_file
, pat
);
10490 /* If it isn't, there is the possibility that we previously had an insn
10491 that clobbered some register as a side effect, but the combined
10492 insn doesn't need to do that. So try once more without the clobbers
10493 unless this represents an ASM insn. */
10495 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10496 && GET_CODE (pat
) == PARALLEL
)
10500 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10501 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10504 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10508 SUBST_INT (XVECLEN (pat
, 0), pos
);
10511 pat
= XVECEXP (pat
, 0, 0);
10513 PATTERN (insn
) = pat
;
10514 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10515 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10517 if (insn_code_number
< 0)
10518 fputs ("Failed to match this instruction:\n", dump_file
);
10520 fputs ("Successfully matched this instruction:\n", dump_file
);
10521 print_rtl_single (dump_file
, pat
);
10524 PATTERN (insn
) = old_pat
;
10525 REG_NOTES (insn
) = old_notes
;
10527 /* Recognize all noop sets, these will be killed by followup pass. */
10528 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10529 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10531 /* If we had any clobbers to add, make a new pattern than contains
10532 them. Then check to make sure that all of them are dead. */
10533 if (num_clobbers_to_add
)
10535 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10536 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10537 ? (XVECLEN (pat
, 0)
10538 + num_clobbers_to_add
)
10539 : num_clobbers_to_add
+ 1));
10541 if (GET_CODE (pat
) == PARALLEL
)
10542 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10543 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10545 XVECEXP (newpat
, 0, 0) = pat
;
10547 add_clobbers (newpat
, insn_code_number
);
10549 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10550 i
< XVECLEN (newpat
, 0); i
++)
10552 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10553 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10555 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10557 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10558 notes
= alloc_reg_note (REG_UNUSED
,
10559 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10568 return insn_code_number
;
10571 /* Like gen_lowpart_general but for use by combine. In combine it
10572 is not possible to create any new pseudoregs. However, it is
10573 safe to create invalid memory addresses, because combine will
10574 try to recognize them and all they will do is make the combine
10577 If for some reason this cannot do its job, an rtx
10578 (clobber (const_int 0)) is returned.
10579 An insn containing that will not be recognized. */
10582 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10584 enum machine_mode imode
= GET_MODE (x
);
10585 unsigned int osize
= GET_MODE_SIZE (omode
);
10586 unsigned int isize
= GET_MODE_SIZE (imode
);
10589 if (omode
== imode
)
10592 /* Return identity if this is a CONST or symbolic reference. */
10594 && (GET_CODE (x
) == CONST
10595 || GET_CODE (x
) == SYMBOL_REF
10596 || GET_CODE (x
) == LABEL_REF
))
10599 /* We can only support MODE being wider than a word if X is a
10600 constant integer or has a mode the same size. */
10601 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10602 && ! ((imode
== VOIDmode
10603 && (CONST_INT_P (x
)
10604 || GET_CODE (x
) == CONST_DOUBLE
))
10605 || isize
== osize
))
10608 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10609 won't know what to do. So we will strip off the SUBREG here and
10610 process normally. */
10611 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10613 x
= SUBREG_REG (x
);
10615 /* For use in case we fall down into the address adjustments
10616 further below, we need to adjust the known mode and size of
10617 x; imode and isize, since we just adjusted x. */
10618 imode
= GET_MODE (x
);
10620 if (imode
== omode
)
10623 isize
= GET_MODE_SIZE (imode
);
10626 result
= gen_lowpart_common (omode
, x
);
10635 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10637 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10640 /* If we want to refer to something bigger than the original memref,
10641 generate a paradoxical subreg instead. That will force a reload
10642 of the original memref X. */
10644 return gen_rtx_SUBREG (omode
, x
, 0);
10646 if (WORDS_BIG_ENDIAN
)
10647 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10649 /* Adjust the address so that the address-after-the-data is
10651 if (BYTES_BIG_ENDIAN
)
10652 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10654 return adjust_address_nv (x
, omode
, offset
);
10657 /* If X is a comparison operator, rewrite it in a new mode. This
10658 probably won't match, but may allow further simplifications. */
10659 else if (COMPARISON_P (x
))
10660 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10662 /* If we couldn't simplify X any other way, just enclose it in a
10663 SUBREG. Normally, this SUBREG won't match, but some patterns may
10664 include an explicit SUBREG or we may simplify it further in combine. */
10670 offset
= subreg_lowpart_offset (omode
, imode
);
10671 if (imode
== VOIDmode
)
10673 imode
= int_mode_for_mode (omode
);
10674 x
= gen_lowpart_common (imode
, x
);
10678 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10684 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10687 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10688 comparison code that will be tested.
10690 The result is a possibly different comparison code to use. *POP0 and
10691 *POP1 may be updated.
10693 It is possible that we might detect that a comparison is either always
10694 true or always false. However, we do not perform general constant
10695 folding in combine, so this knowledge isn't useful. Such tautologies
10696 should have been detected earlier. Hence we ignore all such cases. */
10698 static enum rtx_code
10699 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10705 enum machine_mode mode
, tmode
;
10707 /* Try a few ways of applying the same transformation to both operands. */
10710 #ifndef WORD_REGISTER_OPERATIONS
10711 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10712 so check specially. */
10713 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10714 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10715 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10716 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10717 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10718 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10719 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10720 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10721 && CONST_INT_P (XEXP (op0
, 1))
10722 && XEXP (op0
, 1) == XEXP (op1
, 1)
10723 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10724 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10725 && (INTVAL (XEXP (op0
, 1))
10726 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10727 - (GET_MODE_BITSIZE
10728 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10730 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10731 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10735 /* If both operands are the same constant shift, see if we can ignore the
10736 shift. We can if the shift is a rotate or if the bits shifted out of
10737 this shift are known to be zero for both inputs and if the type of
10738 comparison is compatible with the shift. */
10739 if (GET_CODE (op0
) == GET_CODE (op1
)
10740 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10741 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10742 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10743 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10744 || (GET_CODE (op0
) == ASHIFTRT
10745 && (code
!= GTU
&& code
!= LTU
10746 && code
!= GEU
&& code
!= LEU
)))
10747 && CONST_INT_P (XEXP (op0
, 1))
10748 && INTVAL (XEXP (op0
, 1)) >= 0
10749 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10750 && XEXP (op0
, 1) == XEXP (op1
, 1))
10752 enum machine_mode mode
= GET_MODE (op0
);
10753 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10754 int shift_count
= INTVAL (XEXP (op0
, 1));
10756 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10757 mask
&= (mask
>> shift_count
) << shift_count
;
10758 else if (GET_CODE (op0
) == ASHIFT
)
10759 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10761 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10762 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10763 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10768 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10769 SUBREGs are of the same mode, and, in both cases, the AND would
10770 be redundant if the comparison was done in the narrower mode,
10771 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10772 and the operand's possibly nonzero bits are 0xffffff01; in that case
10773 if we only care about QImode, we don't need the AND). This case
10774 occurs if the output mode of an scc insn is not SImode and
10775 STORE_FLAG_VALUE == 1 (e.g., the 386).
10777 Similarly, check for a case where the AND's are ZERO_EXTEND
10778 operations from some narrower mode even though a SUBREG is not
10781 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10782 && CONST_INT_P (XEXP (op0
, 1))
10783 && CONST_INT_P (XEXP (op1
, 1)))
10785 rtx inner_op0
= XEXP (op0
, 0);
10786 rtx inner_op1
= XEXP (op1
, 0);
10787 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10788 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10791 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10792 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10793 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10794 && (GET_MODE (SUBREG_REG (inner_op0
))
10795 == GET_MODE (SUBREG_REG (inner_op1
)))
10796 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10797 <= HOST_BITS_PER_WIDE_INT
)
10798 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10799 GET_MODE (SUBREG_REG (inner_op0
)))))
10800 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10801 GET_MODE (SUBREG_REG (inner_op1
))))))
10803 op0
= SUBREG_REG (inner_op0
);
10804 op1
= SUBREG_REG (inner_op1
);
10806 /* The resulting comparison is always unsigned since we masked
10807 off the original sign bit. */
10808 code
= unsigned_condition (code
);
10814 for (tmode
= GET_CLASS_NARROWEST_MODE
10815 (GET_MODE_CLASS (GET_MODE (op0
)));
10816 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10817 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10819 op0
= gen_lowpart (tmode
, inner_op0
);
10820 op1
= gen_lowpart (tmode
, inner_op1
);
10821 code
= unsigned_condition (code
);
10830 /* If both operands are NOT, we can strip off the outer operation
10831 and adjust the comparison code for swapped operands; similarly for
10832 NEG, except that this must be an equality comparison. */
10833 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10834 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10835 && (code
== EQ
|| code
== NE
)))
10836 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10842 /* If the first operand is a constant, swap the operands and adjust the
10843 comparison code appropriately, but don't do this if the second operand
10844 is already a constant integer. */
10845 if (swap_commutative_operands_p (op0
, op1
))
10847 tem
= op0
, op0
= op1
, op1
= tem
;
10848 code
= swap_condition (code
);
10851 /* We now enter a loop during which we will try to simplify the comparison.
10852 For the most part, we only are concerned with comparisons with zero,
10853 but some things may really be comparisons with zero but not start
10854 out looking that way. */
10856 while (CONST_INT_P (op1
))
10858 enum machine_mode mode
= GET_MODE (op0
);
10859 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10860 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10861 int equality_comparison_p
;
10862 int sign_bit_comparison_p
;
10863 int unsigned_comparison_p
;
10864 HOST_WIDE_INT const_op
;
10866 /* We only want to handle integral modes. This catches VOIDmode,
10867 CCmode, and the floating-point modes. An exception is that we
10868 can handle VOIDmode if OP0 is a COMPARE or a comparison
10871 if (GET_MODE_CLASS (mode
) != MODE_INT
10872 && ! (mode
== VOIDmode
10873 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
10876 /* Get the constant we are comparing against and turn off all bits
10877 not on in our mode. */
10878 const_op
= INTVAL (op1
);
10879 if (mode
!= VOIDmode
)
10880 const_op
= trunc_int_for_mode (const_op
, mode
);
10881 op1
= GEN_INT (const_op
);
10883 /* If we are comparing against a constant power of two and the value
10884 being compared can only have that single bit nonzero (e.g., it was
10885 `and'ed with that bit), we can replace this with a comparison
10888 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10889 || code
== LT
|| code
== LTU
)
10890 && mode_width
<= HOST_BITS_PER_WIDE_INT
10891 && exact_log2 (const_op
) >= 0
10892 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10894 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10895 op1
= const0_rtx
, const_op
= 0;
10898 /* Similarly, if we are comparing a value known to be either -1 or
10899 0 with -1, change it to the opposite comparison against zero. */
10902 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10903 || code
== GEU
|| code
== LTU
)
10904 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10906 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10907 op1
= const0_rtx
, const_op
= 0;
10910 /* Do some canonicalizations based on the comparison code. We prefer
10911 comparisons against zero and then prefer equality comparisons.
10912 If we can reduce the size of a constant, we will do that too. */
10917 /* < C is equivalent to <= (C - 1) */
10921 op1
= GEN_INT (const_op
);
10923 /* ... fall through to LE case below. */
10929 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10933 op1
= GEN_INT (const_op
);
10937 /* If we are doing a <= 0 comparison on a value known to have
10938 a zero sign bit, we can replace this with == 0. */
10939 else if (const_op
== 0
10940 && mode_width
<= HOST_BITS_PER_WIDE_INT
10941 && (nonzero_bits (op0
, mode
)
10942 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10947 /* >= C is equivalent to > (C - 1). */
10951 op1
= GEN_INT (const_op
);
10953 /* ... fall through to GT below. */
10959 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10963 op1
= GEN_INT (const_op
);
10967 /* If we are doing a > 0 comparison on a value known to have
10968 a zero sign bit, we can replace this with != 0. */
10969 else if (const_op
== 0
10970 && mode_width
<= HOST_BITS_PER_WIDE_INT
10971 && (nonzero_bits (op0
, mode
)
10972 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10977 /* < C is equivalent to <= (C - 1). */
10981 op1
= GEN_INT (const_op
);
10983 /* ... fall through ... */
10986 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10987 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10988 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10990 const_op
= 0, op1
= const0_rtx
;
10998 /* unsigned <= 0 is equivalent to == 0 */
11002 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11003 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
11004 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
11006 const_op
= 0, op1
= const0_rtx
;
11012 /* >= C is equivalent to > (C - 1). */
11016 op1
= GEN_INT (const_op
);
11018 /* ... fall through ... */
11021 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11022 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
11023 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11025 const_op
= 0, op1
= const0_rtx
;
11033 /* unsigned > 0 is equivalent to != 0 */
11037 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11038 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
11039 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
11041 const_op
= 0, op1
= const0_rtx
;
11050 /* Compute some predicates to simplify code below. */
11052 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11053 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11054 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11057 /* If this is a sign bit comparison and we can do arithmetic in
11058 MODE, say that we will only be needing the sign bit of OP0. */
11059 if (sign_bit_comparison_p
11060 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11061 op0
= force_to_mode (op0
, mode
,
11063 << (GET_MODE_BITSIZE (mode
) - 1)),
11066 /* Now try cases based on the opcode of OP0. If none of the cases
11067 does a "continue", we exit this loop immediately after the
11070 switch (GET_CODE (op0
))
11073 /* If we are extracting a single bit from a variable position in
11074 a constant that has only a single bit set and are comparing it
11075 with zero, we can convert this into an equality comparison
11076 between the position and the location of the single bit. */
11077 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11078 have already reduced the shift count modulo the word size. */
11079 if (!SHIFT_COUNT_TRUNCATED
11080 && CONST_INT_P (XEXP (op0
, 0))
11081 && XEXP (op0
, 1) == const1_rtx
11082 && equality_comparison_p
&& const_op
== 0
11083 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
11085 if (BITS_BIG_ENDIAN
)
11087 enum machine_mode new_mode
11088 = mode_for_extraction (EP_extzv
, 1);
11089 if (new_mode
== MAX_MACHINE_MODE
)
11090 i
= BITS_PER_WORD
- 1 - i
;
11094 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
11098 op0
= XEXP (op0
, 2);
11102 /* Result is nonzero iff shift count is equal to I. */
11103 code
= reverse_condition (code
);
11107 /* ... fall through ... */
11110 tem
= expand_compound_operation (op0
);
11119 /* If testing for equality, we can take the NOT of the constant. */
11120 if (equality_comparison_p
11121 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11123 op0
= XEXP (op0
, 0);
11128 /* If just looking at the sign bit, reverse the sense of the
11130 if (sign_bit_comparison_p
)
11132 op0
= XEXP (op0
, 0);
11133 code
= (code
== GE
? LT
: GE
);
11139 /* If testing for equality, we can take the NEG of the constant. */
11140 if (equality_comparison_p
11141 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11143 op0
= XEXP (op0
, 0);
11148 /* The remaining cases only apply to comparisons with zero. */
11152 /* When X is ABS or is known positive,
11153 (neg X) is < 0 if and only if X != 0. */
11155 if (sign_bit_comparison_p
11156 && (GET_CODE (XEXP (op0
, 0)) == ABS
11157 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11158 && (nonzero_bits (XEXP (op0
, 0), mode
)
11159 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
11161 op0
= XEXP (op0
, 0);
11162 code
= (code
== LT
? NE
: EQ
);
11166 /* If we have NEG of something whose two high-order bits are the
11167 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11168 if (num_sign_bit_copies (op0
, mode
) >= 2)
11170 op0
= XEXP (op0
, 0);
11171 code
= swap_condition (code
);
11177 /* If we are testing equality and our count is a constant, we
11178 can perform the inverse operation on our RHS. */
11179 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11180 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11181 op1
, XEXP (op0
, 1))) != 0)
11183 op0
= XEXP (op0
, 0);
11188 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11189 a particular bit. Convert it to an AND of a constant of that
11190 bit. This will be converted into a ZERO_EXTRACT. */
11191 if (const_op
== 0 && sign_bit_comparison_p
11192 && CONST_INT_P (XEXP (op0
, 1))
11193 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11195 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11198 - INTVAL (XEXP (op0
, 1)))));
11199 code
= (code
== LT
? NE
: EQ
);
11203 /* Fall through. */
11206 /* ABS is ignorable inside an equality comparison with zero. */
11207 if (const_op
== 0 && equality_comparison_p
)
11209 op0
= XEXP (op0
, 0);
11215 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11216 (compare FOO CONST) if CONST fits in FOO's mode and we
11217 are either testing inequality or have an unsigned
11218 comparison with ZERO_EXTEND or a signed comparison with
11219 SIGN_EXTEND. But don't do it if we don't have a compare
11220 insn of the given mode, since we'd have to revert it
11221 later on, and then we wouldn't know whether to sign- or
11223 mode
= GET_MODE (XEXP (op0
, 0));
11224 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11225 && ! unsigned_comparison_p
11226 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11227 && ((unsigned HOST_WIDE_INT
) const_op
11228 < (((unsigned HOST_WIDE_INT
) 1
11229 << (GET_MODE_BITSIZE (mode
) - 1))))
11230 && have_insn_for (COMPARE
, mode
))
11232 op0
= XEXP (op0
, 0);
11238 /* Check for the case where we are comparing A - C1 with C2, that is
11240 (subreg:MODE (plus (A) (-C1))) op (C2)
11242 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11243 comparison in the wider mode. One of the following two conditions
11244 must be true in order for this to be valid:
11246 1. The mode extension results in the same bit pattern being added
11247 on both sides and the comparison is equality or unsigned. As
11248 C2 has been truncated to fit in MODE, the pattern can only be
11251 2. The mode extension results in the sign bit being copied on
11254 The difficulty here is that we have predicates for A but not for
11255 (A - C1) so we need to check that C1 is within proper bounds so
11256 as to perturbate A as little as possible. */
11258 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11259 && subreg_lowpart_p (op0
)
11260 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
11261 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11262 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11264 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11265 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11266 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11269 && (unsigned HOST_WIDE_INT
) c1
11270 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11271 && (equality_comparison_p
|| unsigned_comparison_p
)
11272 /* (A - C1) zero-extends if it is positive and sign-extends
11273 if it is negative, C2 both zero- and sign-extends. */
11274 && ((0 == (nonzero_bits (a
, inner_mode
)
11275 & ~GET_MODE_MASK (mode
))
11277 /* (A - C1) sign-extends if it is positive and 1-extends
11278 if it is negative, C2 both sign- and 1-extends. */
11279 || (num_sign_bit_copies (a
, inner_mode
)
11280 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11283 || ((unsigned HOST_WIDE_INT
) c1
11284 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11285 /* (A - C1) always sign-extends, like C2. */
11286 && num_sign_bit_copies (a
, inner_mode
)
11287 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
11288 - (mode_width
- 1))))
11290 op0
= SUBREG_REG (op0
);
11295 /* If the inner mode is narrower and we are extracting the low part,
11296 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11297 if (subreg_lowpart_p (op0
)
11298 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11299 /* Fall through */ ;
11303 /* ... fall through ... */
11306 mode
= GET_MODE (XEXP (op0
, 0));
11307 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11308 && (unsigned_comparison_p
|| equality_comparison_p
)
11309 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11310 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
11311 && have_insn_for (COMPARE
, mode
))
11313 op0
= XEXP (op0
, 0);
11319 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11320 this for equality comparisons due to pathological cases involving
11322 if (equality_comparison_p
11323 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11324 op1
, XEXP (op0
, 1))))
11326 op0
= XEXP (op0
, 0);
11331 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11332 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11333 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11335 op0
= XEXP (XEXP (op0
, 0), 0);
11336 code
= (code
== LT
? EQ
: NE
);
11342 /* We used to optimize signed comparisons against zero, but that
11343 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11344 arrive here as equality comparisons, or (GEU, LTU) are
11345 optimized away. No need to special-case them. */
11347 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11348 (eq B (minus A C)), whichever simplifies. We can only do
11349 this for equality comparisons due to pathological cases involving
11351 if (equality_comparison_p
11352 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11353 XEXP (op0
, 1), op1
)))
11355 op0
= XEXP (op0
, 0);
11360 if (equality_comparison_p
11361 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11362 XEXP (op0
, 0), op1
)))
11364 op0
= XEXP (op0
, 1);
11369 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11370 of bits in X minus 1, is one iff X > 0. */
11371 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11372 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11373 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
11375 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11377 op0
= XEXP (op0
, 1);
11378 code
= (code
== GE
? LE
: GT
);
11384 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11385 if C is zero or B is a constant. */
11386 if (equality_comparison_p
11387 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11388 XEXP (op0
, 1), op1
)))
11390 op0
= XEXP (op0
, 0);
11397 case UNEQ
: case LTGT
:
11398 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11399 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11400 case UNORDERED
: case ORDERED
:
11401 /* We can't do anything if OP0 is a condition code value, rather
11402 than an actual data value. */
11404 || CC0_P (XEXP (op0
, 0))
11405 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11408 /* Get the two operands being compared. */
11409 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11410 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11412 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11414 /* Check for the cases where we simply want the result of the
11415 earlier test or the opposite of that result. */
11416 if (code
== NE
|| code
== EQ
11417 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
11418 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11419 && (STORE_FLAG_VALUE
11420 & (((HOST_WIDE_INT
) 1
11421 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
11422 && (code
== LT
|| code
== GE
)))
11424 enum rtx_code new_code
;
11425 if (code
== LT
|| code
== NE
)
11426 new_code
= GET_CODE (op0
);
11428 new_code
= reversed_comparison_code (op0
, NULL
);
11430 if (new_code
!= UNKNOWN
)
11441 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11443 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11444 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11445 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11447 op0
= XEXP (op0
, 1);
11448 code
= (code
== GE
? GT
: LE
);
11454 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11455 will be converted to a ZERO_EXTRACT later. */
11456 if (const_op
== 0 && equality_comparison_p
11457 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11458 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11460 op0
= simplify_and_const_int
11461 (NULL_RTX
, mode
, gen_rtx_LSHIFTRT (mode
,
11463 XEXP (XEXP (op0
, 0), 1)),
11464 (HOST_WIDE_INT
) 1);
11468 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11469 zero and X is a comparison and C1 and C2 describe only bits set
11470 in STORE_FLAG_VALUE, we can compare with X. */
11471 if (const_op
== 0 && equality_comparison_p
11472 && mode_width
<= HOST_BITS_PER_WIDE_INT
11473 && CONST_INT_P (XEXP (op0
, 1))
11474 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11475 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11476 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11477 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11479 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11480 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11481 if ((~STORE_FLAG_VALUE
& mask
) == 0
11482 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11483 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11484 && COMPARISON_P (tem
))))
11486 op0
= XEXP (XEXP (op0
, 0), 0);
11491 /* If we are doing an equality comparison of an AND of a bit equal
11492 to the sign bit, replace this with a LT or GE comparison of
11493 the underlying value. */
11494 if (equality_comparison_p
11496 && CONST_INT_P (XEXP (op0
, 1))
11497 && mode_width
<= HOST_BITS_PER_WIDE_INT
11498 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11499 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11501 op0
= XEXP (op0
, 0);
11502 code
= (code
== EQ
? GE
: LT
);
11506 /* If this AND operation is really a ZERO_EXTEND from a narrower
11507 mode, the constant fits within that mode, and this is either an
11508 equality or unsigned comparison, try to do this comparison in
11513 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11514 -> (ne:DI (reg:SI 4) (const_int 0))
11516 unless TRULY_NOOP_TRUNCATION allows it or the register is
11517 known to hold a value of the required mode the
11518 transformation is invalid. */
11519 if ((equality_comparison_p
|| unsigned_comparison_p
)
11520 && CONST_INT_P (XEXP (op0
, 1))
11521 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
11522 & GET_MODE_MASK (mode
))
11524 && const_op
>> i
== 0
11525 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11526 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode
),
11527 GET_MODE_BITSIZE (GET_MODE (op0
)))
11528 || (REG_P (XEXP (op0
, 0))
11529 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11531 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11535 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11536 fits in both M1 and M2 and the SUBREG is either paradoxical
11537 or represents the low part, permute the SUBREG and the AND
11539 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11541 unsigned HOST_WIDE_INT c1
;
11542 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11543 /* Require an integral mode, to avoid creating something like
11545 if (SCALAR_INT_MODE_P (tmode
)
11546 /* It is unsafe to commute the AND into the SUBREG if the
11547 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11548 not defined. As originally written the upper bits
11549 have a defined value due to the AND operation.
11550 However, if we commute the AND inside the SUBREG then
11551 they no longer have defined values and the meaning of
11552 the code has been changed. */
11554 #ifdef WORD_REGISTER_OPERATIONS
11555 || (mode_width
> GET_MODE_BITSIZE (tmode
)
11556 && mode_width
<= BITS_PER_WORD
)
11558 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
11559 && subreg_lowpart_p (XEXP (op0
, 0))))
11560 && CONST_INT_P (XEXP (op0
, 1))
11561 && mode_width
<= HOST_BITS_PER_WIDE_INT
11562 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
11563 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11564 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11566 && c1
!= GET_MODE_MASK (tmode
))
11568 op0
= simplify_gen_binary (AND
, tmode
,
11569 SUBREG_REG (XEXP (op0
, 0)),
11570 gen_int_mode (c1
, tmode
));
11571 op0
= gen_lowpart (mode
, op0
);
11576 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11577 if (const_op
== 0 && equality_comparison_p
11578 && XEXP (op0
, 1) == const1_rtx
11579 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11581 op0
= simplify_and_const_int
11582 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
11583 code
= (code
== NE
? EQ
: NE
);
11587 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11588 (eq (and (lshiftrt X) 1) 0).
11589 Also handle the case where (not X) is expressed using xor. */
11590 if (const_op
== 0 && equality_comparison_p
11591 && XEXP (op0
, 1) == const1_rtx
11592 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11594 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11595 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11597 if (GET_CODE (shift_op
) == NOT
11598 || (GET_CODE (shift_op
) == XOR
11599 && CONST_INT_P (XEXP (shift_op
, 1))
11600 && CONST_INT_P (shift_count
)
11601 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11602 && (INTVAL (XEXP (shift_op
, 1))
11603 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11605 op0
= simplify_and_const_int
11607 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11608 (HOST_WIDE_INT
) 1);
11609 code
= (code
== NE
? EQ
: NE
);
11616 /* If we have (compare (ashift FOO N) (const_int C)) and
11617 the high order N bits of FOO (N+1 if an inequality comparison)
11618 are known to be zero, we can do this by comparing FOO with C
11619 shifted right N bits so long as the low-order N bits of C are
11621 if (CONST_INT_P (XEXP (op0
, 1))
11622 && INTVAL (XEXP (op0
, 1)) >= 0
11623 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11624 < HOST_BITS_PER_WIDE_INT
)
11626 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11627 && mode_width
<= HOST_BITS_PER_WIDE_INT
11628 && (nonzero_bits (XEXP (op0
, 0), mode
)
11629 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11630 + ! equality_comparison_p
))) == 0)
11632 /* We must perform a logical shift, not an arithmetic one,
11633 as we want the top N bits of C to be zero. */
11634 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11636 temp
>>= INTVAL (XEXP (op0
, 1));
11637 op1
= gen_int_mode (temp
, mode
);
11638 op0
= XEXP (op0
, 0);
11642 /* If we are doing a sign bit comparison, it means we are testing
11643 a particular bit. Convert it to the appropriate AND. */
11644 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11645 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11647 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11650 - INTVAL (XEXP (op0
, 1)))));
11651 code
= (code
== LT
? NE
: EQ
);
11655 /* If this an equality comparison with zero and we are shifting
11656 the low bit to the sign bit, we can convert this to an AND of the
11658 if (const_op
== 0 && equality_comparison_p
11659 && CONST_INT_P (XEXP (op0
, 1))
11660 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11663 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11664 (HOST_WIDE_INT
) 1);
11670 /* If this is an equality comparison with zero, we can do this
11671 as a logical shift, which might be much simpler. */
11672 if (equality_comparison_p
&& const_op
== 0
11673 && CONST_INT_P (XEXP (op0
, 1)))
11675 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11677 INTVAL (XEXP (op0
, 1)));
11681 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11682 do the comparison in a narrower mode. */
11683 if (! unsigned_comparison_p
11684 && CONST_INT_P (XEXP (op0
, 1))
11685 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11686 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11687 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11688 MODE_INT
, 1)) != BLKmode
11689 && (((unsigned HOST_WIDE_INT
) const_op
11690 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11691 <= GET_MODE_MASK (tmode
)))
11693 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11697 /* Likewise if OP0 is a PLUS of a sign extension with a
11698 constant, which is usually represented with the PLUS
11699 between the shifts. */
11700 if (! unsigned_comparison_p
11701 && CONST_INT_P (XEXP (op0
, 1))
11702 && GET_CODE (XEXP (op0
, 0)) == PLUS
11703 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11704 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11705 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11706 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11707 MODE_INT
, 1)) != BLKmode
11708 && (((unsigned HOST_WIDE_INT
) const_op
11709 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11710 <= GET_MODE_MASK (tmode
)))
11712 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11713 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11714 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11715 add_const
, XEXP (op0
, 1));
11717 op0
= simplify_gen_binary (PLUS
, tmode
,
11718 gen_lowpart (tmode
, inner
),
11723 /* ... fall through ... */
11725 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11726 the low order N bits of FOO are known to be zero, we can do this
11727 by comparing FOO with C shifted left N bits so long as no
11728 overflow occurs. Even if the low order N bits of FOO aren't known
11729 to be zero, if the comparison is >= or < we can use the same
11730 optimization and for > or <= by setting all the low
11731 order N bits in the comparison constant. */
11732 if (CONST_INT_P (XEXP (op0
, 1))
11733 && INTVAL (XEXP (op0
, 1)) > 0
11734 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11735 && mode_width
<= HOST_BITS_PER_WIDE_INT
11736 && (((unsigned HOST_WIDE_INT
) const_op
11737 + (GET_CODE (op0
) != LSHIFTRT
11738 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11741 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11743 unsigned HOST_WIDE_INT low_bits
11744 = (nonzero_bits (XEXP (op0
, 0), mode
)
11745 & (((unsigned HOST_WIDE_INT
) 1
11746 << INTVAL (XEXP (op0
, 1))) - 1));
11747 if (low_bits
== 0 || !equality_comparison_p
)
11749 /* If the shift was logical, then we must make the condition
11751 if (GET_CODE (op0
) == LSHIFTRT
)
11752 code
= unsigned_condition (code
);
11754 const_op
<<= INTVAL (XEXP (op0
, 1));
11756 && (code
== GT
|| code
== GTU
11757 || code
== LE
|| code
== LEU
))
11759 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11760 op1
= GEN_INT (const_op
);
11761 op0
= XEXP (op0
, 0);
11766 /* If we are using this shift to extract just the sign bit, we
11767 can replace this with an LT or GE comparison. */
11769 && (equality_comparison_p
|| sign_bit_comparison_p
)
11770 && CONST_INT_P (XEXP (op0
, 1))
11771 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11774 op0
= XEXP (op0
, 0);
11775 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11787 /* Now make any compound operations involved in this comparison. Then,
11788 check for an outmost SUBREG on OP0 that is not doing anything or is
11789 paradoxical. The latter transformation must only be performed when
11790 it is known that the "extra" bits will be the same in op0 and op1 or
11791 that they don't matter. There are three cases to consider:
11793 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11794 care bits and we can assume they have any convenient value. So
11795 making the transformation is safe.
11797 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11798 In this case the upper bits of op0 are undefined. We should not make
11799 the simplification in that case as we do not know the contents of
11802 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11803 UNKNOWN. In that case we know those bits are zeros or ones. We must
11804 also be sure that they are the same as the upper bits of op1.
11806 We can never remove a SUBREG for a non-equality comparison because
11807 the sign bit is in a different place in the underlying object. */
11809 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11810 op1
= make_compound_operation (op1
, SET
);
11812 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11813 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11814 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11815 && (code
== NE
|| code
== EQ
))
11817 if (GET_MODE_SIZE (GET_MODE (op0
))
11818 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11820 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11822 if (REG_P (SUBREG_REG (op0
)))
11824 op0
= SUBREG_REG (op0
);
11825 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11828 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11829 <= HOST_BITS_PER_WIDE_INT
)
11830 && (nonzero_bits (SUBREG_REG (op0
),
11831 GET_MODE (SUBREG_REG (op0
)))
11832 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11834 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11836 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11837 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11838 op0
= SUBREG_REG (op0
), op1
= tem
;
11842 /* We now do the opposite procedure: Some machines don't have compare
11843 insns in all modes. If OP0's mode is an integer mode smaller than a
11844 word and we can't do a compare in that mode, see if there is a larger
11845 mode for which we can do the compare. There are a number of cases in
11846 which we can use the wider mode. */
11848 mode
= GET_MODE (op0
);
11849 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11850 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11851 && ! have_insn_for (COMPARE
, mode
))
11852 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11854 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11855 tmode
= GET_MODE_WIDER_MODE (tmode
))
11856 if (have_insn_for (COMPARE
, tmode
))
11860 /* If this is a test for negative, we can make an explicit
11861 test of the sign bit. Test this first so we can use
11862 a paradoxical subreg to extend OP0. */
11864 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11865 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11867 op0
= simplify_gen_binary (AND
, tmode
,
11868 gen_lowpart (tmode
, op0
),
11869 GEN_INT ((HOST_WIDE_INT
) 1
11870 << (GET_MODE_BITSIZE (mode
)
11872 code
= (code
== LT
) ? NE
: EQ
;
11876 /* If the only nonzero bits in OP0 and OP1 are those in the
11877 narrower mode and this is an equality or unsigned comparison,
11878 we can use the wider mode. Similarly for sign-extended
11879 values, in which case it is true for all comparisons. */
11880 zero_extended
= ((code
== EQ
|| code
== NE
11881 || code
== GEU
|| code
== GTU
11882 || code
== LEU
|| code
== LTU
)
11883 && (nonzero_bits (op0
, tmode
)
11884 & ~GET_MODE_MASK (mode
)) == 0
11885 && ((CONST_INT_P (op1
)
11886 || (nonzero_bits (op1
, tmode
)
11887 & ~GET_MODE_MASK (mode
)) == 0)));
11890 || ((num_sign_bit_copies (op0
, tmode
)
11891 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11892 - GET_MODE_BITSIZE (mode
)))
11893 && (num_sign_bit_copies (op1
, tmode
)
11894 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11895 - GET_MODE_BITSIZE (mode
)))))
11897 /* If OP0 is an AND and we don't have an AND in MODE either,
11898 make a new AND in the proper mode. */
11899 if (GET_CODE (op0
) == AND
11900 && !have_insn_for (AND
, mode
))
11901 op0
= simplify_gen_binary (AND
, tmode
,
11902 gen_lowpart (tmode
,
11904 gen_lowpart (tmode
,
11910 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
11911 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
11915 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
11916 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
11923 #ifdef CANONICALIZE_COMPARISON
11924 /* If this machine only supports a subset of valid comparisons, see if we
11925 can convert an unsupported one into a supported one. */
11926 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11935 /* Utility function for record_value_for_reg. Count number of
11940 enum rtx_code code
= GET_CODE (x
);
11944 if (GET_RTX_CLASS (code
) == '2'
11945 || GET_RTX_CLASS (code
) == 'c')
11947 rtx x0
= XEXP (x
, 0);
11948 rtx x1
= XEXP (x
, 1);
11951 return 1 + 2 * count_rtxs (x0
);
11953 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11954 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11955 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11956 return 2 + 2 * count_rtxs (x0
)
11957 + count_rtxs (x
== XEXP (x1
, 0)
11958 ? XEXP (x1
, 1) : XEXP (x1
, 0));
11960 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11961 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11962 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11963 return 2 + 2 * count_rtxs (x1
)
11964 + count_rtxs (x
== XEXP (x0
, 0)
11965 ? XEXP (x0
, 1) : XEXP (x0
, 0));
11968 fmt
= GET_RTX_FORMAT (code
);
11969 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11971 ret
+= count_rtxs (XEXP (x
, i
));
11972 else if (fmt
[i
] == 'E')
11973 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11974 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
11979 /* Utility function for following routine. Called when X is part of a value
11980 being stored into last_set_value. Sets last_set_table_tick
11981 for each register mentioned. Similar to mention_regs in cse.c */
11984 update_table_tick (rtx x
)
11986 enum rtx_code code
= GET_CODE (x
);
11987 const char *fmt
= GET_RTX_FORMAT (code
);
11992 unsigned int regno
= REGNO (x
);
11993 unsigned int endregno
= END_REGNO (x
);
11996 for (r
= regno
; r
< endregno
; r
++)
11998 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, r
);
11999 rsp
->last_set_table_tick
= label_tick
;
12005 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12008 /* Check for identical subexpressions. If x contains
12009 identical subexpression we only have to traverse one of
12011 if (i
== 0 && ARITHMETIC_P (x
))
12013 /* Note that at this point x1 has already been
12015 rtx x0
= XEXP (x
, 0);
12016 rtx x1
= XEXP (x
, 1);
12018 /* If x0 and x1 are identical then there is no need to
12023 /* If x0 is identical to a subexpression of x1 then while
12024 processing x1, x0 has already been processed. Thus we
12025 are done with x. */
12026 if (ARITHMETIC_P (x1
)
12027 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12030 /* If x1 is identical to a subexpression of x0 then we
12031 still have to process the rest of x0. */
12032 if (ARITHMETIC_P (x0
)
12033 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12035 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12040 update_table_tick (XEXP (x
, i
));
12042 else if (fmt
[i
] == 'E')
12043 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12044 update_table_tick (XVECEXP (x
, i
, j
));
12047 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12048 are saying that the register is clobbered and we no longer know its
12049 value. If INSN is zero, don't update reg_stat[].last_set; this is
12050 only permitted with VALUE also zero and is used to invalidate the
12054 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12056 unsigned int regno
= REGNO (reg
);
12057 unsigned int endregno
= END_REGNO (reg
);
12059 reg_stat_type
*rsp
;
12061 /* If VALUE contains REG and we have a previous value for REG, substitute
12062 the previous value. */
12063 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12067 /* Set things up so get_last_value is allowed to see anything set up to
12069 subst_low_luid
= DF_INSN_LUID (insn
);
12070 tem
= get_last_value (reg
);
12072 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12073 it isn't going to be useful and will take a lot of time to process,
12074 so just use the CLOBBER. */
12078 if (ARITHMETIC_P (tem
)
12079 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12080 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12081 tem
= XEXP (tem
, 0);
12082 else if (count_occurrences (value
, reg
, 1) >= 2)
12084 /* If there are two or more occurrences of REG in VALUE,
12085 prevent the value from growing too much. */
12086 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12087 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12090 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12094 /* For each register modified, show we don't know its value, that
12095 we don't know about its bitwise content, that its value has been
12096 updated, and that we don't know the location of the death of the
12098 for (i
= regno
; i
< endregno
; i
++)
12100 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12103 rsp
->last_set
= insn
;
12105 rsp
->last_set_value
= 0;
12106 rsp
->last_set_mode
= VOIDmode
;
12107 rsp
->last_set_nonzero_bits
= 0;
12108 rsp
->last_set_sign_bit_copies
= 0;
12109 rsp
->last_death
= 0;
12110 rsp
->truncated_to_mode
= VOIDmode
;
12113 /* Mark registers that are being referenced in this value. */
12115 update_table_tick (value
);
12117 /* Now update the status of each register being set.
12118 If someone is using this register in this block, set this register
12119 to invalid since we will get confused between the two lives in this
12120 basic block. This makes using this register always invalid. In cse, we
12121 scan the table to invalidate all entries using this register, but this
12122 is too much work for us. */
12124 for (i
= regno
; i
< endregno
; i
++)
12126 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12127 rsp
->last_set_label
= label_tick
;
12129 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12130 rsp
->last_set_invalid
= 1;
12132 rsp
->last_set_invalid
= 0;
12135 /* The value being assigned might refer to X (like in "x++;"). In that
12136 case, we must replace it with (clobber (const_int 0)) to prevent
12138 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12139 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12141 value
= copy_rtx (value
);
12142 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12146 /* For the main register being modified, update the value, the mode, the
12147 nonzero bits, and the number of sign bit copies. */
12149 rsp
->last_set_value
= value
;
12153 enum machine_mode mode
= GET_MODE (reg
);
12154 subst_low_luid
= DF_INSN_LUID (insn
);
12155 rsp
->last_set_mode
= mode
;
12156 if (GET_MODE_CLASS (mode
) == MODE_INT
12157 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
12158 mode
= nonzero_bits_mode
;
12159 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12160 rsp
->last_set_sign_bit_copies
12161 = num_sign_bit_copies (value
, GET_MODE (reg
));
12165 /* Called via note_stores from record_dead_and_set_regs to handle one
12166 SET or CLOBBER in an insn. DATA is the instruction in which the
12167 set is occurring. */
12170 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12172 rtx record_dead_insn
= (rtx
) data
;
12174 if (GET_CODE (dest
) == SUBREG
)
12175 dest
= SUBREG_REG (dest
);
12177 if (!record_dead_insn
)
12180 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12186 /* If we are setting the whole register, we know its value. Otherwise
12187 show that we don't know the value. We can handle SUBREG in
12189 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12190 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12191 else if (GET_CODE (setter
) == SET
12192 && GET_CODE (SET_DEST (setter
)) == SUBREG
12193 && SUBREG_REG (SET_DEST (setter
)) == dest
12194 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
12195 && subreg_lowpart_p (SET_DEST (setter
)))
12196 record_value_for_reg (dest
, record_dead_insn
,
12197 gen_lowpart (GET_MODE (dest
),
12198 SET_SRC (setter
)));
12200 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12202 else if (MEM_P (dest
)
12203 /* Ignore pushes, they clobber nothing. */
12204 && ! push_operand (dest
, GET_MODE (dest
)))
12205 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12208 /* Update the records of when each REG was most recently set or killed
12209 for the things done by INSN. This is the last thing done in processing
12210 INSN in the combiner loop.
12212 We update reg_stat[], in particular fields last_set, last_set_value,
12213 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12214 last_death, and also the similar information mem_last_set (which insn
12215 most recently modified memory) and last_call_luid (which insn was the
12216 most recent subroutine call). */
12219 record_dead_and_set_regs (rtx insn
)
12224 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12226 if (REG_NOTE_KIND (link
) == REG_DEAD
12227 && REG_P (XEXP (link
, 0)))
12229 unsigned int regno
= REGNO (XEXP (link
, 0));
12230 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12232 for (i
= regno
; i
< endregno
; i
++)
12234 reg_stat_type
*rsp
;
12236 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12237 rsp
->last_death
= insn
;
12240 else if (REG_NOTE_KIND (link
) == REG_INC
)
12241 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12246 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12247 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
12249 reg_stat_type
*rsp
;
12251 rsp
= VEC_index (reg_stat_type
, reg_stat
, i
);
12252 rsp
->last_set_invalid
= 1;
12253 rsp
->last_set
= insn
;
12254 rsp
->last_set_value
= 0;
12255 rsp
->last_set_mode
= VOIDmode
;
12256 rsp
->last_set_nonzero_bits
= 0;
12257 rsp
->last_set_sign_bit_copies
= 0;
12258 rsp
->last_death
= 0;
12259 rsp
->truncated_to_mode
= VOIDmode
;
12262 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12264 /* We can't combine into a call pattern. Remember, though, that
12265 the return value register is set at this LUID. We could
12266 still replace a register with the return value from the
12267 wrong subroutine call! */
12268 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12271 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12274 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12275 register present in the SUBREG, so for each such SUBREG go back and
12276 adjust nonzero and sign bit information of the registers that are
12277 known to have some zero/sign bits set.
12279 This is needed because when combine blows the SUBREGs away, the
12280 information on zero/sign bits is lost and further combines can be
12281 missed because of that. */
12284 record_promoted_value (rtx insn
, rtx subreg
)
12287 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12288 enum machine_mode mode
= GET_MODE (subreg
);
12290 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
12293 for (links
= LOG_LINKS (insn
); links
;)
12295 reg_stat_type
*rsp
;
12297 insn
= XEXP (links
, 0);
12298 set
= single_set (insn
);
12300 if (! set
|| !REG_P (SET_DEST (set
))
12301 || REGNO (SET_DEST (set
)) != regno
12302 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12304 links
= XEXP (links
, 1);
12308 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12309 if (rsp
->last_set
== insn
)
12311 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12312 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12315 if (REG_P (SET_SRC (set
)))
12317 regno
= REGNO (SET_SRC (set
));
12318 links
= LOG_LINKS (insn
);
12325 /* Check if X, a register, is known to contain a value already
12326 truncated to MODE. In this case we can use a subreg to refer to
12327 the truncated value even though in the generic case we would need
12328 an explicit truncation. */
12331 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12333 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12334 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12337 || rsp
->truncation_label
< label_tick_ebb_start
)
12339 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12341 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
12342 GET_MODE_BITSIZE (truncated
)))
12347 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12348 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12349 might be able to turn a truncate into a subreg using this information.
12350 Return -1 if traversing *P is complete or 0 otherwise. */
12353 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12356 enum machine_mode truncated_mode
;
12357 reg_stat_type
*rsp
;
12359 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12361 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12362 truncated_mode
= GET_MODE (x
);
12364 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12367 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode
),
12368 GET_MODE_BITSIZE (original_mode
)))
12371 x
= SUBREG_REG (x
);
12373 /* ??? For hard-regs we now record everything. We might be able to
12374 optimize this using last_set_mode. */
12375 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12376 truncated_mode
= GET_MODE (x
);
12380 rsp
= VEC_index (reg_stat_type
, reg_stat
, REGNO (x
));
12381 if (rsp
->truncated_to_mode
== 0
12382 || rsp
->truncation_label
< label_tick_ebb_start
12383 || (GET_MODE_SIZE (truncated_mode
)
12384 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12386 rsp
->truncated_to_mode
= truncated_mode
;
12387 rsp
->truncation_label
= label_tick
;
12393 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12394 the modes they are used in. This can help truning TRUNCATEs into
12398 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12400 for_each_rtx (x
, record_truncated_value
, NULL
);
12403 /* Scan X for promoted SUBREGs. For each one found,
12404 note what it implies to the registers used in it. */
12407 check_promoted_subreg (rtx insn
, rtx x
)
12409 if (GET_CODE (x
) == SUBREG
12410 && SUBREG_PROMOTED_VAR_P (x
)
12411 && REG_P (SUBREG_REG (x
)))
12412 record_promoted_value (insn
, x
);
12415 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12418 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12422 check_promoted_subreg (insn
, XEXP (x
, i
));
12426 if (XVEC (x
, i
) != 0)
12427 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12428 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12434 /* Verify that all the registers and memory references mentioned in *LOC are
12435 still valid. *LOC was part of a value set in INSN when label_tick was
12436 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12437 the invalid references with (clobber (const_int 0)) and return 1. This
12438 replacement is useful because we often can get useful information about
12439 the form of a value (e.g., if it was produced by a shift that always
12440 produces -1 or 0) even though we don't know exactly what registers it
12441 was produced from. */
12444 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12447 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12448 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12453 unsigned int regno
= REGNO (x
);
12454 unsigned int endregno
= END_REGNO (x
);
12457 for (j
= regno
; j
< endregno
; j
++)
12459 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, j
);
12460 if (rsp
->last_set_invalid
12461 /* If this is a pseudo-register that was only set once and not
12462 live at the beginning of the function, it is always valid. */
12463 || (! (regno
>= FIRST_PSEUDO_REGISTER
12464 && REG_N_SETS (regno
) == 1
12465 && (!REGNO_REG_SET_P
12466 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12467 && rsp
->last_set_label
> tick
))
12470 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12477 /* If this is a memory reference, make sure that there were no stores after
12478 it that might have clobbered the value. We don't have alias info, so we
12479 assume any store invalidates it. Moreover, we only have local UIDs, so
12480 we also assume that there were stores in the intervening basic blocks. */
12481 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12482 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12485 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12489 for (i
= 0; i
< len
; i
++)
12493 /* Check for identical subexpressions. If x contains
12494 identical subexpression we only have to traverse one of
12496 if (i
== 1 && ARITHMETIC_P (x
))
12498 /* Note that at this point x0 has already been checked
12499 and found valid. */
12500 rtx x0
= XEXP (x
, 0);
12501 rtx x1
= XEXP (x
, 1);
12503 /* If x0 and x1 are identical then x is also valid. */
12507 /* If x1 is identical to a subexpression of x0 then
12508 while checking x0, x1 has already been checked. Thus
12509 it is valid and so as x. */
12510 if (ARITHMETIC_P (x0
)
12511 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12514 /* If x0 is identical to a subexpression of x1 then x is
12515 valid iff the rest of x1 is valid. */
12516 if (ARITHMETIC_P (x1
)
12517 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12519 get_last_value_validate (&XEXP (x1
,
12520 x0
== XEXP (x1
, 0) ? 1 : 0),
12521 insn
, tick
, replace
);
12524 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12528 else if (fmt
[i
] == 'E')
12529 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12530 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12531 insn
, tick
, replace
) == 0)
12535 /* If we haven't found a reason for it to be invalid, it is valid. */
12539 /* Get the last value assigned to X, if known. Some registers
12540 in the value may be replaced with (clobber (const_int 0)) if their value
12541 is known longer known reliably. */
12544 get_last_value (const_rtx x
)
12546 unsigned int regno
;
12548 reg_stat_type
*rsp
;
12550 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12551 then convert it to the desired mode. If this is a paradoxical SUBREG,
12552 we cannot predict what values the "extra" bits might have. */
12553 if (GET_CODE (x
) == SUBREG
12554 && subreg_lowpart_p (x
)
12555 && (GET_MODE_SIZE (GET_MODE (x
))
12556 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
12557 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12558 return gen_lowpart (GET_MODE (x
), value
);
12564 rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12565 value
= rsp
->last_set_value
;
12567 /* If we don't have a value, or if it isn't for this basic block and
12568 it's either a hard register, set more than once, or it's a live
12569 at the beginning of the function, return 0.
12571 Because if it's not live at the beginning of the function then the reg
12572 is always set before being used (is never used without being set).
12573 And, if it's set only once, and it's always set before use, then all
12574 uses must have the same last value, even if it's not from this basic
12578 || (rsp
->last_set_label
< label_tick_ebb_start
12579 && (regno
< FIRST_PSEUDO_REGISTER
12580 || REG_N_SETS (regno
) != 1
12582 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12585 /* If the value was set in a later insn than the ones we are processing,
12586 we can't use it even if the register was only set once. */
12587 if (rsp
->last_set_label
== label_tick
12588 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12591 /* If the value has all its registers valid, return it. */
12592 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12595 /* Otherwise, make a copy and replace any invalid register with
12596 (clobber (const_int 0)). If that fails for some reason, return 0. */
12598 value
= copy_rtx (value
);
12599 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12605 /* Return nonzero if expression X refers to a REG or to memory
12606 that is set in an instruction more recent than FROM_LUID. */
12609 use_crosses_set_p (const_rtx x
, int from_luid
)
12613 enum rtx_code code
= GET_CODE (x
);
12617 unsigned int regno
= REGNO (x
);
12618 unsigned endreg
= END_REGNO (x
);
12620 #ifdef PUSH_ROUNDING
12621 /* Don't allow uses of the stack pointer to be moved,
12622 because we don't know whether the move crosses a push insn. */
12623 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12626 for (; regno
< endreg
; regno
++)
12628 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
12630 && rsp
->last_set_label
== label_tick
12631 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12637 if (code
== MEM
&& mem_last_set
> from_luid
)
12640 fmt
= GET_RTX_FORMAT (code
);
12642 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12647 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12648 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12651 else if (fmt
[i
] == 'e'
12652 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12658 /* Define three variables used for communication between the following
12661 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12662 static int reg_dead_flag
;
12664 /* Function called via note_stores from reg_dead_at_p.
12666 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12667 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12670 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12672 unsigned int regno
, endregno
;
12677 regno
= REGNO (dest
);
12678 endregno
= END_REGNO (dest
);
12679 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12680 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12683 /* Return nonzero if REG is known to be dead at INSN.
12685 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12686 referencing REG, it is dead. If we hit a SET referencing REG, it is
12687 live. Otherwise, see if it is live or dead at the start of the basic
12688 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12689 must be assumed to be always live. */
12692 reg_dead_at_p (rtx reg
, rtx insn
)
12697 /* Set variables for reg_dead_at_p_1. */
12698 reg_dead_regno
= REGNO (reg
);
12699 reg_dead_endregno
= END_REGNO (reg
);
12703 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12704 we allow the machine description to decide whether use-and-clobber
12705 patterns are OK. */
12706 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12708 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12709 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12713 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12714 beginning of basic block. */
12715 block
= BLOCK_FOR_INSN (insn
);
12720 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12722 return reg_dead_flag
== 1 ? 1 : 0;
12724 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12728 if (insn
== BB_HEAD (block
))
12731 insn
= PREV_INSN (insn
);
12734 /* Look at live-in sets for the basic block that we were in. */
12735 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12736 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12742 /* Note hard registers in X that are used. */
12745 mark_used_regs_combine (rtx x
)
12747 RTX_CODE code
= GET_CODE (x
);
12748 unsigned int regno
;
12761 case ADDR_DIFF_VEC
:
12764 /* CC0 must die in the insn after it is set, so we don't need to take
12765 special note of it here. */
12771 /* If we are clobbering a MEM, mark any hard registers inside the
12772 address as used. */
12773 if (MEM_P (XEXP (x
, 0)))
12774 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12779 /* A hard reg in a wide mode may really be multiple registers.
12780 If so, mark all of them just like the first. */
12781 if (regno
< FIRST_PSEUDO_REGISTER
)
12783 /* None of this applies to the stack, frame or arg pointers. */
12784 if (regno
== STACK_POINTER_REGNUM
12785 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12786 || regno
== HARD_FRAME_POINTER_REGNUM
12788 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12789 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12791 || regno
== FRAME_POINTER_REGNUM
)
12794 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12800 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12802 rtx testreg
= SET_DEST (x
);
12804 while (GET_CODE (testreg
) == SUBREG
12805 || GET_CODE (testreg
) == ZERO_EXTRACT
12806 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12807 testreg
= XEXP (testreg
, 0);
12809 if (MEM_P (testreg
))
12810 mark_used_regs_combine (XEXP (testreg
, 0));
12812 mark_used_regs_combine (SET_SRC (x
));
12820 /* Recursively scan the operands of this expression. */
12823 const char *fmt
= GET_RTX_FORMAT (code
);
12825 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12828 mark_used_regs_combine (XEXP (x
, i
));
12829 else if (fmt
[i
] == 'E')
12833 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12834 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12840 /* Remove register number REGNO from the dead registers list of INSN.
12842 Return the note used to record the death, if there was one. */
12845 remove_death (unsigned int regno
, rtx insn
)
12847 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12850 remove_note (insn
, note
);
12855 /* For each register (hardware or pseudo) used within expression X, if its
12856 death is in an instruction with luid between FROM_LUID (inclusive) and
12857 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12858 list headed by PNOTES.
12860 That said, don't move registers killed by maybe_kill_insn.
12862 This is done when X is being merged by combination into TO_INSN. These
12863 notes will then be distributed as needed. */
12866 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12871 enum rtx_code code
= GET_CODE (x
);
12875 unsigned int regno
= REGNO (x
);
12876 rtx where_dead
= VEC_index (reg_stat_type
, reg_stat
, regno
)->last_death
;
12878 /* Don't move the register if it gets killed in between from and to. */
12879 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12880 && ! reg_referenced_p (x
, maybe_kill_insn
))
12884 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12885 && DF_INSN_LUID (where_dead
) >= from_luid
12886 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12888 rtx note
= remove_death (regno
, where_dead
);
12890 /* It is possible for the call above to return 0. This can occur
12891 when last_death points to I2 or I1 that we combined with.
12892 In that case make a new note.
12894 We must also check for the case where X is a hard register
12895 and NOTE is a death note for a range of hard registers
12896 including X. In that case, we must put REG_DEAD notes for
12897 the remaining registers in place of NOTE. */
12899 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12900 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12901 > GET_MODE_SIZE (GET_MODE (x
))))
12903 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12904 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12905 unsigned int ourend
= END_HARD_REGNO (x
);
12908 for (i
= deadregno
; i
< deadend
; i
++)
12909 if (i
< regno
|| i
>= ourend
)
12910 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12913 /* If we didn't find any note, or if we found a REG_DEAD note that
12914 covers only part of the given reg, and we have a multi-reg hard
12915 register, then to be safe we must check for REG_DEAD notes
12916 for each register other than the first. They could have
12917 their own REG_DEAD notes lying around. */
12918 else if ((note
== 0
12920 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12921 < GET_MODE_SIZE (GET_MODE (x
)))))
12922 && regno
< FIRST_PSEUDO_REGISTER
12923 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12925 unsigned int ourend
= END_HARD_REGNO (x
);
12926 unsigned int i
, offset
;
12930 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12934 for (i
= regno
+ offset
; i
< ourend
; i
++)
12935 move_deaths (regno_reg_rtx
[i
],
12936 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
12939 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12941 XEXP (note
, 1) = *pnotes
;
12945 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
12951 else if (GET_CODE (x
) == SET
)
12953 rtx dest
= SET_DEST (x
);
12955 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12957 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12958 that accesses one word of a multi-word item, some
12959 piece of everything register in the expression is used by
12960 this insn, so remove any old death. */
12961 /* ??? So why do we test for equality of the sizes? */
12963 if (GET_CODE (dest
) == ZERO_EXTRACT
12964 || GET_CODE (dest
) == STRICT_LOW_PART
12965 || (GET_CODE (dest
) == SUBREG
12966 && (((GET_MODE_SIZE (GET_MODE (dest
))
12967 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12968 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12969 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12971 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12975 /* If this is some other SUBREG, we know it replaces the entire
12976 value, so use that as the destination. */
12977 if (GET_CODE (dest
) == SUBREG
)
12978 dest
= SUBREG_REG (dest
);
12980 /* If this is a MEM, adjust deaths of anything used in the address.
12981 For a REG (the only other possibility), the entire value is
12982 being replaced so the old value is not used in this insn. */
12985 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
12990 else if (GET_CODE (x
) == CLOBBER
)
12993 len
= GET_RTX_LENGTH (code
);
12994 fmt
= GET_RTX_FORMAT (code
);
12996 for (i
= 0; i
< len
; i
++)
13001 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13002 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13005 else if (fmt
[i
] == 'e')
13006 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13010 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13011 pattern of an insn. X must be a REG. */
13014 reg_bitfield_target_p (rtx x
, rtx body
)
13018 if (GET_CODE (body
) == SET
)
13020 rtx dest
= SET_DEST (body
);
13022 unsigned int regno
, tregno
, endregno
, endtregno
;
13024 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13025 target
= XEXP (dest
, 0);
13026 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13027 target
= SUBREG_REG (XEXP (dest
, 0));
13031 if (GET_CODE (target
) == SUBREG
)
13032 target
= SUBREG_REG (target
);
13034 if (!REG_P (target
))
13037 tregno
= REGNO (target
), regno
= REGNO (x
);
13038 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13039 return target
== x
;
13041 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13042 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13044 return endregno
> tregno
&& regno
< endtregno
;
13047 else if (GET_CODE (body
) == PARALLEL
)
13048 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13049 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13055 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13056 as appropriate. I3 and I2 are the insns resulting from the combination
13057 insns including FROM (I2 may be zero).
13059 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13060 not need REG_DEAD notes because they are being substituted for. This
13061 saves searching in the most common cases.
13063 Each note in the list is either ignored or placed on some insns, depending
13064 on the type of note. */
13067 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13068 rtx elim_i1
, rtx elim_i0
)
13070 rtx note
, next_note
;
13073 for (note
= notes
; note
; note
= next_note
)
13075 rtx place
= 0, place2
= 0;
13077 next_note
= XEXP (note
, 1);
13078 switch (REG_NOTE_KIND (note
))
13082 /* Doesn't matter much where we put this, as long as it's somewhere.
13083 It is preferable to keep these notes on branches, which is most
13084 likely to be i3. */
13088 case REG_VALUE_PROFILE
:
13089 /* Just get rid of this note, as it is unused later anyway. */
13092 case REG_NON_LOCAL_GOTO
:
13097 gcc_assert (i2
&& JUMP_P (i2
));
13102 case REG_EH_REGION
:
13103 /* These notes must remain with the call or trapping instruction. */
13106 else if (i2
&& CALL_P (i2
))
13110 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13111 if (may_trap_p (i3
))
13113 else if (i2
&& may_trap_p (i2
))
13115 /* ??? Otherwise assume we've combined things such that we
13116 can now prove that the instructions can't trap. Drop the
13117 note in this case. */
13123 /* These notes must remain with the call. It should not be
13124 possible for both I2 and I3 to be a call. */
13129 gcc_assert (i2
&& CALL_P (i2
));
13135 /* Any clobbers for i3 may still exist, and so we must process
13136 REG_UNUSED notes from that insn.
13138 Any clobbers from i2 or i1 can only exist if they were added by
13139 recog_for_combine. In that case, recog_for_combine created the
13140 necessary REG_UNUSED notes. Trying to keep any original
13141 REG_UNUSED notes from these insns can cause incorrect output
13142 if it is for the same register as the original i3 dest.
13143 In that case, we will notice that the register is set in i3,
13144 and then add a REG_UNUSED note for the destination of i3, which
13145 is wrong. However, it is possible to have REG_UNUSED notes from
13146 i2 or i1 for register which were both used and clobbered, so
13147 we keep notes from i2 or i1 if they will turn into REG_DEAD
13150 /* If this register is set or clobbered in I3, put the note there
13151 unless there is one already. */
13152 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13154 if (from_insn
!= i3
)
13157 if (! (REG_P (XEXP (note
, 0))
13158 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13159 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13162 /* Otherwise, if this register is used by I3, then this register
13163 now dies here, so we must put a REG_DEAD note here unless there
13165 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13166 && ! (REG_P (XEXP (note
, 0))
13167 ? find_regno_note (i3
, REG_DEAD
,
13168 REGNO (XEXP (note
, 0)))
13169 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13171 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13179 /* These notes say something about results of an insn. We can
13180 only support them if they used to be on I3 in which case they
13181 remain on I3. Otherwise they are ignored.
13183 If the note refers to an expression that is not a constant, we
13184 must also ignore the note since we cannot tell whether the
13185 equivalence is still true. It might be possible to do
13186 slightly better than this (we only have a problem if I2DEST
13187 or I1DEST is present in the expression), but it doesn't
13188 seem worth the trouble. */
13190 if (from_insn
== i3
13191 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13196 /* These notes say something about how a register is used. They must
13197 be present on any use of the register in I2 or I3. */
13198 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13201 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13210 case REG_LABEL_TARGET
:
13211 case REG_LABEL_OPERAND
:
13212 /* This can show up in several ways -- either directly in the
13213 pattern, or hidden off in the constant pool with (or without?)
13214 a REG_EQUAL note. */
13215 /* ??? Ignore the without-reg_equal-note problem for now. */
13216 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13217 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13218 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13219 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13223 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13224 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13225 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13226 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13234 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13235 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13237 if (place
&& JUMP_P (place
)
13238 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13239 && (JUMP_LABEL (place
) == NULL
13240 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13242 rtx label
= JUMP_LABEL (place
);
13245 JUMP_LABEL (place
) = XEXP (note
, 0);
13246 else if (LABEL_P (label
))
13247 LABEL_NUSES (label
)--;
13250 if (place2
&& JUMP_P (place2
)
13251 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13252 && (JUMP_LABEL (place2
) == NULL
13253 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13255 rtx label
= JUMP_LABEL (place2
);
13258 JUMP_LABEL (place2
) = XEXP (note
, 0);
13259 else if (LABEL_P (label
))
13260 LABEL_NUSES (label
)--;
13266 /* This note says something about the value of a register prior
13267 to the execution of an insn. It is too much trouble to see
13268 if the note is still correct in all situations. It is better
13269 to simply delete it. */
13273 /* If we replaced the right hand side of FROM_INSN with a
13274 REG_EQUAL note, the original use of the dying register
13275 will not have been combined into I3 and I2. In such cases,
13276 FROM_INSN is guaranteed to be the first of the combined
13277 instructions, so we simply need to search back before
13278 FROM_INSN for the previous use or set of this register,
13279 then alter the notes there appropriately.
13281 If the register is used as an input in I3, it dies there.
13282 Similarly for I2, if it is nonzero and adjacent to I3.
13284 If the register is not used as an input in either I3 or I2
13285 and it is not one of the registers we were supposed to eliminate,
13286 there are two possibilities. We might have a non-adjacent I2
13287 or we might have somehow eliminated an additional register
13288 from a computation. For example, we might have had A & B where
13289 we discover that B will always be zero. In this case we will
13290 eliminate the reference to A.
13292 In both cases, we must search to see if we can find a previous
13293 use of A and put the death note there. */
13296 && from_insn
== i2mod
13297 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13302 && CALL_P (from_insn
)
13303 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13305 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13307 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13308 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13310 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13312 && reg_overlap_mentioned_p (XEXP (note
, 0),
13314 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13315 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13322 basic_block bb
= this_basic_block
;
13324 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13326 if (!NONDEBUG_INSN_P (tem
))
13328 if (tem
== BB_HEAD (bb
))
13333 /* If the register is being set at TEM, see if that is all
13334 TEM is doing. If so, delete TEM. Otherwise, make this
13335 into a REG_UNUSED note instead. Don't delete sets to
13336 global register vars. */
13337 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13338 || !global_regs
[REGNO (XEXP (note
, 0))])
13339 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13341 rtx set
= single_set (tem
);
13342 rtx inner_dest
= 0;
13344 rtx cc0_setter
= NULL_RTX
;
13348 for (inner_dest
= SET_DEST (set
);
13349 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13350 || GET_CODE (inner_dest
) == SUBREG
13351 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13352 inner_dest
= XEXP (inner_dest
, 0))
13355 /* Verify that it was the set, and not a clobber that
13356 modified the register.
13358 CC0 targets must be careful to maintain setter/user
13359 pairs. If we cannot delete the setter due to side
13360 effects, mark the user with an UNUSED note instead
13363 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13364 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13366 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13367 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13368 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13372 /* Move the notes and links of TEM elsewhere.
13373 This might delete other dead insns recursively.
13374 First set the pattern to something that won't use
13376 rtx old_notes
= REG_NOTES (tem
);
13378 PATTERN (tem
) = pc_rtx
;
13379 REG_NOTES (tem
) = NULL
;
13381 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13382 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13383 distribute_links (LOG_LINKS (tem
));
13385 SET_INSN_DELETED (tem
);
13390 /* Delete the setter too. */
13393 PATTERN (cc0_setter
) = pc_rtx
;
13394 old_notes
= REG_NOTES (cc0_setter
);
13395 REG_NOTES (cc0_setter
) = NULL
;
13397 distribute_notes (old_notes
, cc0_setter
,
13398 cc0_setter
, NULL_RTX
,
13399 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13400 distribute_links (LOG_LINKS (cc0_setter
));
13402 SET_INSN_DELETED (cc0_setter
);
13403 if (cc0_setter
== i2
)
13410 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13412 /* If there isn't already a REG_UNUSED note, put one
13413 here. Do not place a REG_DEAD note, even if
13414 the register is also used here; that would not
13415 match the algorithm used in lifetime analysis
13416 and can cause the consistency check in the
13417 scheduler to fail. */
13418 if (! find_regno_note (tem
, REG_UNUSED
,
13419 REGNO (XEXP (note
, 0))))
13424 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13426 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13430 /* If we are doing a 3->2 combination, and we have a
13431 register which formerly died in i3 and was not used
13432 by i2, which now no longer dies in i3 and is used in
13433 i2 but does not die in i2, and place is between i2
13434 and i3, then we may need to move a link from place to
13436 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13438 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13439 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13441 rtx links
= LOG_LINKS (place
);
13442 LOG_LINKS (place
) = 0;
13443 distribute_links (links
);
13448 if (tem
== BB_HEAD (bb
))
13454 /* If the register is set or already dead at PLACE, we needn't do
13455 anything with this note if it is still a REG_DEAD note.
13456 We check here if it is set at all, not if is it totally replaced,
13457 which is what `dead_or_set_p' checks, so also check for it being
13460 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13462 unsigned int regno
= REGNO (XEXP (note
, 0));
13463 reg_stat_type
*rsp
= VEC_index (reg_stat_type
, reg_stat
, regno
);
13465 if (dead_or_set_p (place
, XEXP (note
, 0))
13466 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13468 /* Unless the register previously died in PLACE, clear
13469 last_death. [I no longer understand why this is
13471 if (rsp
->last_death
!= place
)
13472 rsp
->last_death
= 0;
13476 rsp
->last_death
= place
;
13478 /* If this is a death note for a hard reg that is occupying
13479 multiple registers, ensure that we are still using all
13480 parts of the object. If we find a piece of the object
13481 that is unused, we must arrange for an appropriate REG_DEAD
13482 note to be added for it. However, we can't just emit a USE
13483 and tag the note to it, since the register might actually
13484 be dead; so we recourse, and the recursive call then finds
13485 the previous insn that used this register. */
13487 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13488 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13490 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13494 for (i
= regno
; i
< endregno
; i
++)
13495 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13496 && ! find_regno_fusage (place
, USE
, i
))
13497 || dead_or_set_regno_p (place
, i
))
13502 /* Put only REG_DEAD notes for pieces that are
13503 not already dead or set. */
13505 for (i
= regno
; i
< endregno
;
13506 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13508 rtx piece
= regno_reg_rtx
[i
];
13509 basic_block bb
= this_basic_block
;
13511 if (! dead_or_set_p (place
, piece
)
13512 && ! reg_bitfield_target_p (piece
,
13515 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13518 distribute_notes (new_note
, place
, place
,
13519 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13522 else if (! refers_to_regno_p (i
, i
+ 1,
13523 PATTERN (place
), 0)
13524 && ! find_regno_fusage (place
, USE
, i
))
13525 for (tem
= PREV_INSN (place
); ;
13526 tem
= PREV_INSN (tem
))
13528 if (!NONDEBUG_INSN_P (tem
))
13530 if (tem
== BB_HEAD (bb
))
13534 if (dead_or_set_p (tem
, piece
)
13535 || reg_bitfield_target_p (piece
,
13538 add_reg_note (tem
, REG_UNUSED
, piece
);
13552 /* Any other notes should not be present at this point in the
13554 gcc_unreachable ();
13559 XEXP (note
, 1) = REG_NOTES (place
);
13560 REG_NOTES (place
) = note
;
13564 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13568 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13569 I3, I2, and I1 to new locations. This is also called to add a link
13570 pointing at I3 when I3's destination is changed. */
13573 distribute_links (rtx links
)
13575 rtx link
, next_link
;
13577 for (link
= links
; link
; link
= next_link
)
13583 next_link
= XEXP (link
, 1);
13585 /* If the insn that this link points to is a NOTE or isn't a single
13586 set, ignore it. In the latter case, it isn't clear what we
13587 can do other than ignore the link, since we can't tell which
13588 register it was for. Such links wouldn't be used by combine
13591 It is not possible for the destination of the target of the link to
13592 have been changed by combine. The only potential of this is if we
13593 replace I3, I2, and I1 by I3 and I2. But in that case the
13594 destination of I2 also remains unchanged. */
13596 if (NOTE_P (XEXP (link
, 0))
13597 || (set
= single_set (XEXP (link
, 0))) == 0)
13600 reg
= SET_DEST (set
);
13601 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13602 || GET_CODE (reg
) == STRICT_LOW_PART
)
13603 reg
= XEXP (reg
, 0);
13605 /* A LOG_LINK is defined as being placed on the first insn that uses
13606 a register and points to the insn that sets the register. Start
13607 searching at the next insn after the target of the link and stop
13608 when we reach a set of the register or the end of the basic block.
13610 Note that this correctly handles the link that used to point from
13611 I3 to I2. Also note that not much searching is typically done here
13612 since most links don't point very far away. */
13614 for (insn
= NEXT_INSN (XEXP (link
, 0));
13615 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13616 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13617 insn
= NEXT_INSN (insn
))
13618 if (DEBUG_INSN_P (insn
))
13620 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13622 if (reg_referenced_p (reg
, PATTERN (insn
)))
13626 else if (CALL_P (insn
)
13627 && find_reg_fusage (insn
, USE
, reg
))
13632 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13635 /* If we found a place to put the link, place it there unless there
13636 is already a link to the same insn as LINK at that point. */
13642 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13643 if (XEXP (link2
, 0) == XEXP (link
, 0))
13648 XEXP (link
, 1) = LOG_LINKS (place
);
13649 LOG_LINKS (place
) = link
;
13651 /* Set added_links_insn to the earliest insn we added a
13653 if (added_links_insn
== 0
13654 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13655 added_links_insn
= place
;
13661 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13662 Check whether the expression pointer to by LOC is a register or
13663 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13664 Otherwise return zero. */
13667 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13672 && (REG_P (x
) || MEM_P (x
))
13673 && ! reg_mentioned_p (x
, (rtx
) expr
))
13678 /* Check for any register or memory mentioned in EQUIV that is not
13679 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13680 of EXPR where some registers may have been replaced by constants. */
13683 unmentioned_reg_p (rtx equiv
, rtx expr
)
13685 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13689 dump_combine_stats (FILE *file
)
13693 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13694 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13698 dump_combine_total_stats (FILE *file
)
13702 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13703 total_attempts
, total_merges
, total_extras
, total_successes
);
13707 gate_handle_combine (void)
13709 return (optimize
> 0);
13712 /* Try combining insns through substitution. */
13713 static unsigned int
13714 rest_of_handle_combine (void)
13716 int rebuild_jump_labels_after_combine
;
13718 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13719 df_note_add_problem ();
13722 regstat_init_n_sets_and_refs ();
13724 rebuild_jump_labels_after_combine
13725 = combine_instructions (get_insns (), max_reg_num ());
13727 /* Combining insns may have turned an indirect jump into a
13728 direct jump. Rebuild the JUMP_LABEL fields of jumping
13730 if (rebuild_jump_labels_after_combine
)
13732 timevar_push (TV_JUMP
);
13733 rebuild_jump_labels (get_insns ());
13735 timevar_pop (TV_JUMP
);
13738 regstat_free_n_sets_and_refs ();
13742 struct rtl_opt_pass pass_combine
=
13746 "combine", /* name */
13747 gate_handle_combine
, /* gate */
13748 rest_of_handle_combine
, /* execute */
13751 0, /* static_pass_number */
13752 TV_COMBINE
, /* tv_id */
13753 PROP_cfglayout
, /* properties_required */
13754 0, /* properties_provided */
13755 0, /* properties_destroyed */
13756 0, /* todo_flags_start */
13758 TODO_df_finish
| TODO_verify_rtl_sharing
|
13759 TODO_ggc_collect
, /* todo_flags_finish */