1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92, 93, 94, 1995 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
39 /* 1 if the caller has placed an "unimp" insn immediately after the call.
40 This is used in v8 code when calling a function that returns a structure.
41 v9 doesn't have this. */
43 #define SKIP_CALLERS_UNIMP_P (!TARGET_V9 && current_function_returns_struct)
45 /* Global variables for machine-dependent things. */
47 /* Says what architecture we're compiling for. */
48 enum arch_type sparc_arch_type
;
50 /* Size of frame. Need to know this to emit return insns from leaf procedures.
51 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
52 reload pass. This is important as the value is later used in insn
53 scheduling (to see what can go in a delay slot).
54 APPARENT_FSIZE is the size of the stack less the register save area and less
55 the outgoing argument area. It is used when saving call preserved regs. */
56 static int apparent_fsize
;
57 static int actual_fsize
;
59 /* Save the operands last given to a compare for use when we
60 generate a scc or bcc insn. */
62 rtx sparc_compare_op0
, sparc_compare_op1
;
64 /* Count of named arguments (v9 only).
65 ??? INIT_CUMULATIVE_ARGS initializes these, and FUNCTION_ARG_ADVANCE
66 increments SPARC_ARG_COUNT. They are then used by
67 FUNCTION_ARG_CALLEE_COPIES to determine if the argument is really a named
68 argument or not. This hack is necessary because the NAMED argument to the
69 FUNCTION_ARG_XXX macros is not what it says it is: it does not include the
70 last named argument. */
73 int sparc_n_named_args
;
75 /* We may need an epilogue if we spill too many registers.
76 If this is non-zero, then we branch here for the epilogue. */
77 static rtx leaf_label
;
81 /* Vector to say how input registers are mapped to output
82 registers. FRAME_POINTER_REGNUM cannot be remapped by
83 this function to eliminate it. You must use -fomit-frame-pointer
85 char leaf_reg_remap
[] =
86 { 0, 1, 2, 3, 4, 5, 6, 7,
87 -1, -1, -1, -1, -1, -1, 14, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1,
89 8, 9, 10, 11, 12, 13, -1, 15,
91 32, 33, 34, 35, 36, 37, 38, 39,
92 40, 41, 42, 43, 44, 45, 46, 47,
93 48, 49, 50, 51, 52, 53, 54, 55,
94 56, 57, 58, 59, 60, 61, 62, 63,
95 64, 65, 66, 67, 68, 69, 70, 71,
96 72, 73, 74, 75, 76, 77, 78, 79,
97 80, 81, 82, 83, 84, 85, 86, 87,
98 88, 89, 90, 91, 92, 93, 94, 95,
103 /* Name of where we pretend to think the frame pointer points.
104 Normally, this is "%fp", but if we are in a leaf procedure,
105 this is "%sp+something". We record "something" separately as it may be
106 too big for reg+constant addressing. */
108 static char *frame_base_name
;
109 static int frame_base_offset
;
111 static rtx
find_addr_reg ();
112 static void sparc_init_modes ();
114 /* Option handling. */
116 /* Validate and override various options, and do some machine dependent
120 sparc_override_options ()
122 /* Check for any conflicts in the choice of options. */
123 /* ??? This stuff isn't really usable yet. */
127 if (target_flags
& MASK_CODE_MODEL
)
128 error ("code model support is only available with -mv9");
130 error ("-mint64 is only available with -mv9");
132 error ("-mlong64 is only available with -mv9");
134 error ("-mptr64 is only available with -mv9");
136 error ("-menv32 is only available with -mv9");
137 if (TARGET_STACK_BIAS
)
138 error ("-mstack-bias is only available with -mv9");
142 /* ??? Are there any options that aren't usable with v9.
143 -munaligned-doubles? */
146 /* Check for conflicts in cpu specification.
147 If we use -mcpu=xxx, this can be removed. */
149 if ((TARGET_V8
!= 0) + (TARGET_SPARCLITE
!= 0) + (TARGET_V9
!= 0) > 1)
150 error ("conflicting architectures defined");
152 /* Do various machine dependent initializations. */
156 /* Float conversions (v9 only).
158 The floating point registers cannot hold DImode values because SUBREG's
159 on them get the wrong register. "(subreg:SI (reg:DI M int-reg) 0)" is the
160 same as "(subreg:SI (reg:DI N float-reg) 1)", but gcc doesn't know how to
161 turn the "0" to a "1". Therefore, we must explicitly do the conversions
162 to/from int/fp regs. `sparc64_fpconv_stack_slot' is the address of an
163 8 byte stack slot used during the transfer.
164 ??? I could have used [%fp-16] but I didn't want to add yet another
165 dependence on this. */
166 /* ??? Can we use assign_stack_temp here? */
168 static rtx fpconv_stack_temp
;
170 /* Called once for each function. */
173 sparc64_init_expanders ()
175 fpconv_stack_temp
= NULL_RTX
;
178 /* Assign a stack temp for fp/int DImode conversions. */
181 sparc64_fpconv_stack_temp ()
183 if (fpconv_stack_temp
== NULL_RTX
)
185 assign_stack_local (DImode
, GET_MODE_SIZE (DImode
), 0);
187 return fpconv_stack_temp
;
190 /* Return non-zero only if OP is a register of mode MODE,
193 reg_or_0_operand (op
, mode
)
195 enum machine_mode mode
;
197 if (op
== const0_rtx
|| register_operand (op
, mode
))
199 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
200 && CONST_DOUBLE_HIGH (op
) == 0
201 && CONST_DOUBLE_LOW (op
) == 0)
203 if (GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
204 && GET_CODE (op
) == CONST_DOUBLE
205 && fp_zero_operand (op
))
210 /* Nonzero if OP is a floating point value with value 0.0. */
217 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
218 return REAL_VALUES_EQUAL (r
, dconst0
);
221 /* Nonzero if OP is an integer register. */
224 intreg_operand (op
, mode
)
226 enum machine_mode mode
;
228 return (register_operand (op
, SImode
)
229 || (TARGET_V9
&& register_operand (op
, DImode
)));
232 /* Nonzero if OP is a floating point condition code register. */
235 ccfp_reg_operand (op
, mode
)
237 enum machine_mode mode
;
239 /* This can happen when recog is called from combine. Op may be a MEM.
240 Fail instead of calling abort in this case. */
241 if (GET_CODE (op
) != REG
|| REGNO (op
) == 0)
243 if (GET_MODE (op
) != mode
)
246 #if 0 /* ??? ==> 1 when %fcc1-3 are pseudos first. See gen_compare_reg(). */
247 if (reg_renumber
== 0)
248 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
249 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
251 return (unsigned) REGNO (op
) - 96 < 4;
255 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
257 restore_operand (op
, mode
)
259 enum machine_mode mode
;
261 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
262 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
265 /* Call insn on SPARC can take a PC-relative constant address, or any regular
269 call_operand (op
, mode
)
271 enum machine_mode mode
;
273 if (GET_CODE (op
) != MEM
)
276 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
280 call_operand_address (op
, mode
)
282 enum machine_mode mode
;
284 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
287 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
288 reference and a constant. */
291 symbolic_operand (op
, mode
)
293 enum machine_mode mode
;
295 switch (GET_CODE (op
))
303 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
304 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
305 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
307 /* ??? This clause seems to be irrelevant. */
309 return GET_MODE (op
) == mode
;
316 /* Return truth value of statement that OP is a symbolic memory
317 operand of mode MODE. */
320 symbolic_memory_operand (op
, mode
)
322 enum machine_mode mode
;
324 if (GET_CODE (op
) == SUBREG
)
325 op
= SUBREG_REG (op
);
326 if (GET_CODE (op
) != MEM
)
329 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
330 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
333 /* Return 1 if the operand is a data segment reference. This includes
334 the readonly data segment, or in other words anything but the text segment.
335 This is needed in the medium/anywhere code model on v9. These values
336 are accessed with MEDANY_BASE_REG. */
339 data_segment_operand (op
, mode
)
341 enum machine_mode mode
;
343 switch (GET_CODE (op
))
346 return ! SYMBOL_REF_FLAG (op
);
348 /* Assume canonical format of symbol + constant. */
350 return data_segment_operand (XEXP (op
, 0));
356 /* Return 1 if the operand is a text segment reference.
357 This is needed in the medium/anywhere code model on v9. */
360 text_segment_operand (op
, mode
)
362 enum machine_mode mode
;
364 switch (GET_CODE (op
))
369 return SYMBOL_REF_FLAG (op
);
371 /* Assume canonical format of symbol + constant. */
373 return text_segment_operand (XEXP (op
, 0));
379 /* Return 1 if the operand is either a register or a memory operand that is
383 reg_or_nonsymb_mem_operand (op
, mode
)
385 enum machine_mode mode
;
387 if (register_operand (op
, mode
))
390 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
397 sparc_operand (op
, mode
)
399 enum machine_mode mode
;
401 if (register_operand (op
, mode
))
403 if (GET_CODE (op
) == CONST_INT
)
404 return SMALL_INT (op
);
405 if (GET_MODE (op
) != mode
)
407 if (GET_CODE (op
) == SUBREG
)
408 op
= SUBREG_REG (op
);
409 if (GET_CODE (op
) != MEM
)
413 if (GET_CODE (op
) == LO_SUM
)
414 return (GET_CODE (XEXP (op
, 0)) == REG
415 && symbolic_operand (XEXP (op
, 1), Pmode
));
416 return memory_address_p (mode
, op
);
420 move_operand (op
, mode
)
422 enum machine_mode mode
;
424 if (mode
== DImode
&& arith_double_operand (op
, mode
))
426 if (register_operand (op
, mode
))
428 if (GET_CODE (op
) == CONST_INT
)
429 return (SMALL_INT (op
) || (INTVAL (op
) & 0x3ff) == 0);
431 if (GET_MODE (op
) != mode
)
433 if (GET_CODE (op
) == SUBREG
)
434 op
= SUBREG_REG (op
);
435 if (GET_CODE (op
) != MEM
)
438 if (GET_CODE (op
) == LO_SUM
)
439 return (register_operand (XEXP (op
, 0), Pmode
)
440 && CONSTANT_P (XEXP (op
, 1)));
441 return memory_address_p (mode
, op
);
445 move_pic_label (op
, mode
)
447 enum machine_mode mode
;
449 /* Special case for PIC. */
450 if (flag_pic
&& GET_CODE (op
) == LABEL_REF
)
458 enum machine_mode mode
;
460 if (GET_CODE (op
) == MEM
)
461 return (mode
== VOIDmode
|| mode
== GET_MODE (op
));
465 /* Return truth value of whether OP is EQ or NE. */
470 enum machine_mode mode
;
472 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
475 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
476 or LTU for non-floating-point. We handle those specially. */
479 normal_comp_operator (op
, mode
)
481 enum machine_mode mode
;
483 enum rtx_code code
= GET_CODE (op
);
485 if (GET_RTX_CLASS (code
) != '<')
488 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
489 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
492 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
495 /* Return 1 if this is a comparison operator. This allows the use of
496 MATCH_OPERATOR to recognize all the branch insns. */
499 noov_compare_op (op
, mode
)
501 enum machine_mode mode
;
503 enum rtx_code code
= GET_CODE (op
);
505 if (GET_RTX_CLASS (code
) != '<')
508 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
)
509 /* These are the only branches which work with CC_NOOVmode. */
510 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
514 /* Nonzero if OP is a comparison operator suitable for use in v9
515 conditional move or branch on register contents instructions. */
518 v9_regcmp_op (op
, mode
)
520 enum machine_mode mode
;
522 enum rtx_code code
= GET_CODE (op
);
524 if (GET_RTX_CLASS (code
) != '<')
527 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
528 || code
== LE
|| code
== GT
);
531 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
536 enum machine_mode mode
;
538 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
541 /* Return nonzero if OP is an operator of mode MODE which can set
542 the condition codes explicitly. We do not include PLUS and MINUS
543 because these require CC_NOOVmode, which we handle explicitly. */
546 cc_arithop (op
, mode
)
548 enum machine_mode mode
;
550 if (GET_CODE (op
) == AND
551 || GET_CODE (op
) == IOR
552 || GET_CODE (op
) == XOR
)
558 /* Return nonzero if OP is an operator of mode MODE which can bitwise
559 complement its second operand and set the condition codes explicitly. */
562 cc_arithopn (op
, mode
)
564 enum machine_mode mode
;
566 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
567 and (xor ... (not ...)) to (not (xor ...)). */
568 return (GET_CODE (op
) == AND
569 || GET_CODE (op
) == IOR
);
572 /* Return true if OP is a register, or is a CONST_INT that can fit in a 13
573 bit immediate field. This is an acceptable SImode operand for most 3
574 address instructions. */
577 arith_operand (op
, mode
)
579 enum machine_mode mode
;
581 return (register_operand (op
, mode
)
582 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
)));
585 /* Return true if OP is a register, or is a CONST_INT that can fit in an 11
586 bit immediate field. This is an acceptable SImode operand for the movcc
590 arith11_operand (op
, mode
)
592 enum machine_mode mode
;
594 return (register_operand (op
, mode
)
595 || (GET_CODE (op
) == CONST_INT
596 && ((unsigned) (INTVAL (op
) + 0x400) < 0x800)));
599 /* Return true if OP is a register, or is a CONST_INT that can fit in an 10
600 bit immediate field. This is an acceptable SImode operand for the movrcc
604 arith10_operand (op
, mode
)
606 enum machine_mode mode
;
608 return (register_operand (op
, mode
)
609 || (GET_CODE (op
) == CONST_INT
610 && ((unsigned) (INTVAL (op
) + 0x200) < 0x400)));
613 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
614 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
616 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
617 can fit in a 13 bit immediate field. This is an acceptable DImode operand
618 for most 3 address instructions. */
621 arith_double_operand (op
, mode
)
623 enum machine_mode mode
;
625 return (register_operand (op
, mode
)
626 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
628 && GET_CODE (op
) == CONST_DOUBLE
629 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
630 && (unsigned) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
632 && GET_CODE (op
) == CONST_DOUBLE
633 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
634 && ((CONST_DOUBLE_HIGH (op
) == -1
635 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
636 || (CONST_DOUBLE_HIGH (op
) == 0
637 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
640 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
641 can fit in an 11 bit immediate field. This is an acceptable DImode
642 operand for the movcc instructions. */
643 /* ??? Replace with arith11_operand? */
646 arith11_double_operand (op
, mode
)
648 enum machine_mode mode
;
650 return (register_operand (op
, mode
)
651 || (GET_CODE (op
) == CONST_DOUBLE
652 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
653 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
654 && ((CONST_DOUBLE_HIGH (op
) == -1
655 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
656 || (CONST_DOUBLE_HIGH (op
) == 0
657 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
658 || (GET_CODE (op
) == CONST_INT
659 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
660 && (unsigned) (INTVAL (op
) + 0x400) < 0x800));
663 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
664 can fit in an 10 bit immediate field. This is an acceptable DImode
665 operand for the movrcc instructions. */
666 /* ??? Replace with arith10_operand? */
669 arith10_double_operand (op
, mode
)
671 enum machine_mode mode
;
673 return (register_operand (op
, mode
)
674 || (GET_CODE (op
) == CONST_DOUBLE
675 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
676 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
677 && ((CONST_DOUBLE_HIGH (op
) == -1
678 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
679 || (CONST_DOUBLE_HIGH (op
) == 0
680 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
681 || (GET_CODE (op
) == CONST_INT
682 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
683 && (unsigned) (INTVAL (op
) + 0x200) < 0x400));
686 /* Return truth value of whether OP is a integer which fits the
687 range constraining immediate operands in most three-address insns,
688 which have a 13 bit immediate field. */
693 enum machine_mode mode
;
695 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
698 /* Recognize operand values for the umul instruction. That instruction sign
699 extends immediate values just like all other sparc instructions, but
700 interprets the extended result as an unsigned number. */
703 uns_small_int (op
, mode
)
705 enum machine_mode mode
;
707 #if HOST_BITS_PER_WIDE_INT > 32
708 /* All allowed constants will fit a CONST_INT. */
709 return (GET_CODE (op
) == CONST_INT
710 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
711 || (INTVAL (op
) >= 0xFFFFF000 && INTVAL (op
) < 0x100000000L
)));
713 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
714 || (GET_CODE (op
) == CONST_DOUBLE
715 && CONST_DOUBLE_HIGH (op
) == 0
716 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
721 uns_arith_operand (op
, mode
)
723 enum machine_mode mode
;
725 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
728 /* Return truth value of statement that OP is a call-clobbered register. */
730 clobbered_register (op
, mode
)
732 enum machine_mode mode
;
734 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
737 /* X and Y are two things to compare using CODE. Emit the compare insn and
738 return the rtx for the cc reg in the proper mode. */
741 gen_compare_reg (code
, x
, y
)
745 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
748 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
749 fpcc regs (cse can't tell they're really call clobbered regs and will
750 remove a duplicate comparison even if there is an intervening function
751 call - it will then try to reload the cc reg via an int reg which is why
752 we need the movcc patterns). It is possible to provide the movcc
753 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
754 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
755 to tell cse that CCFPE mode registers (even pseudoes) are call
758 /* ??? This is an experiment. Rather than making changes to cse which may
759 or may not be easy/clean, we do our own cse. This is possible because
760 we will generate hard registers. Cse knows they're call clobbered (it
761 doesn't know the same thing about pseudos). If we guess wrong, no big
762 deal, but if we win, great! */
764 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
765 #if 1 /* experiment */
768 /* We cycle through the registers to ensure they're all exercised. */
769 static int next_fpcc_reg
= 0;
770 /* Previous x,y for each fpcc reg. */
771 static rtx prev_args
[4][2];
773 /* Scan prev_args for x,y. */
774 for (reg
= 0; reg
< 4; reg
++)
775 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
780 prev_args
[reg
][0] = x
;
781 prev_args
[reg
][1] = y
;
782 next_fpcc_reg
= (next_fpcc_reg
+ 1) & 3;
784 cc_reg
= gen_rtx (REG
, mode
, reg
+ 96);
787 cc_reg
= gen_reg_rtx (mode
);
788 #endif /* ! experiment */
790 cc_reg
= gen_rtx (REG
, mode
, 0);
792 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
793 gen_rtx (COMPARE
, mode
, x
, y
)));
798 /* This function is used for v9 only.
799 CODE is the code for an Scc's comparison.
800 OPERANDS[0] is the target of the Scc insn.
801 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
804 This function is needed to turn
811 (gt:DI (reg:CCX 0 %g0)
814 IE: The instruction recognizer needs to see the mode of the comparison to
815 find the right instruction. We could use "gt:DI" right in the
816 define_expand, but leaving it out allows us to handle DI, SI, etc.
818 We refer to the global sparc compare operands sparc_compare_op0 and
821 ??? Some of this is outdated as the scc insns set the mode of the
824 ??? We optimize for the case where op1 is 0 and the comparison allows us to
825 use the "movrCC" insns. This reduces the generated code from three to two
826 insns. This way seems too brute force though. Is there a more elegant way
827 to achieve the same effect?
829 Currently, this function always returns 1. ??? Can it ever fail? */
832 gen_v9_scc (compare_code
, operands
)
833 enum rtx_code compare_code
;
834 register rtx
*operands
;
838 if (GET_MODE_CLASS (GET_MODE (sparc_compare_op0
)) == MODE_INT
839 && sparc_compare_op1
== const0_rtx
840 && (compare_code
== EQ
|| compare_code
== NE
841 || compare_code
== LT
|| compare_code
== LE
842 || compare_code
== GT
|| compare_code
== GE
))
844 /* Special case for op0 != 0. This can be done with one instruction if
845 op0 can be clobbered. We store to a temp, and then clobber the temp,
846 but the combiner will remove the first insn. */
848 if (compare_code
== NE
849 && GET_MODE (operands
[0]) == DImode
850 && GET_MODE (sparc_compare_op0
) == DImode
)
852 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0], sparc_compare_op0
));
853 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0],
854 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
855 gen_rtx (compare_code
, DImode
,
856 sparc_compare_op0
, const0_rtx
),
862 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0], const0_rtx
));
863 if (GET_MODE (sparc_compare_op0
) != DImode
)
865 temp
= gen_reg_rtx (DImode
);
866 convert_move (temp
, sparc_compare_op0
, 0);
870 temp
= sparc_compare_op0
;
872 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0],
873 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
874 gen_rtx (compare_code
, DImode
,
882 operands
[1] = gen_compare_reg (compare_code
,
883 sparc_compare_op0
, sparc_compare_op1
);
885 switch (GET_MODE (operands
[1]))
895 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0], const0_rtx
));
896 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0],
897 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
898 gen_rtx (compare_code
,
899 GET_MODE (operands
[1]),
900 operands
[1], const0_rtx
),
901 const1_rtx
, operands
[0])));
906 /* Emit a conditional jump insn for the v9 architecture using comparison code
907 CODE and jump target LABEL.
908 This function exists to take advantage of the v9 brxx insns. */
911 emit_v9_brxx_insn (code
, op0
, label
)
915 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
917 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
918 gen_rtx (code
, GET_MODE (op0
),
920 gen_rtx (LABEL_REF
, VOIDmode
, label
),
924 /* Return nonzero if a return peephole merging return with
925 setting of output register is ok. */
927 leaf_return_peephole_ok ()
929 return (actual_fsize
== 0);
932 /* Return nonzero if TRIAL can go into the function epilogue's
933 delay slot. SLOT is the slot we are trying to fill. */
936 eligible_for_epilogue_delay (trial
, slot
)
944 if (GET_CODE (trial
) != INSN
945 || GET_CODE (PATTERN (trial
)) != SET
)
947 if (get_attr_length (trial
) != 1)
950 /* In the case of a true leaf function, anything can go into the delay slot.
951 A delay slot only exists however if the frame size is zero, otherwise
952 we will put an insn to adjust the stack after the return. */
955 if (leaf_return_peephole_ok ())
956 return (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
);
960 /* Otherwise, only operations which can be done in tandem with
961 a `restore' insn can go into the delay slot. */
962 pat
= PATTERN (trial
);
963 if (GET_CODE (SET_DEST (pat
)) != REG
964 || REGNO (SET_DEST (pat
)) == 0
965 || REGNO (SET_DEST (pat
)) >= 32
966 || REGNO (SET_DEST (pat
)) < 24)
970 if (arith_operand (src
, GET_MODE (src
)))
971 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
972 if (arith_double_operand (src
, GET_MODE (src
)))
973 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
974 if (GET_CODE (src
) == PLUS
)
976 if (register_operand (XEXP (src
, 0), SImode
)
977 && arith_operand (XEXP (src
, 1), SImode
))
979 if (register_operand (XEXP (src
, 1), SImode
)
980 && arith_operand (XEXP (src
, 0), SImode
))
982 if (register_operand (XEXP (src
, 0), DImode
)
983 && arith_double_operand (XEXP (src
, 1), DImode
))
985 if (register_operand (XEXP (src
, 1), DImode
)
986 && arith_double_operand (XEXP (src
, 0), DImode
))
989 if (GET_CODE (src
) == MINUS
990 && register_operand (XEXP (src
, 0), SImode
)
991 && small_int (XEXP (src
, 1), VOIDmode
))
993 if (GET_CODE (src
) == MINUS
994 && register_operand (XEXP (src
, 0), DImode
)
995 && !register_operand (XEXP (src
, 1), DImode
)
996 && arith_double_operand (XEXP (src
, 1), DImode
))
1002 short_branch (uid1
, uid2
)
1005 unsigned int delta
= insn_addresses
[uid1
] - insn_addresses
[uid2
];
1006 if (delta
+ 1024 < 2048)
1008 /* warning ("long branch, distance %d", delta); */
1012 /* Return non-zero if REG is not used after INSN.
1013 We assume REG is a reload reg, and therefore does
1014 not live past labels or calls or jumps. */
1016 reg_unused_after (reg
, insn
)
1020 enum rtx_code code
, prev_code
= UNKNOWN
;
1022 while (insn
= NEXT_INSN (insn
))
1024 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
1027 code
= GET_CODE (insn
);
1028 if (GET_CODE (insn
) == CODE_LABEL
)
1031 if (GET_RTX_CLASS (code
) == 'i')
1033 rtx set
= single_set (insn
);
1034 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
1037 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1039 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
1047 /* The rtx for the global offset table which is a special form
1048 that *is* a position independent symbolic constant. */
1049 static rtx pic_pc_rtx
;
1051 /* Ensure that we are not using patterns that are not OK with PIC. */
1060 if (GET_CODE (recog_operand
[i
]) == SYMBOL_REF
1061 || (GET_CODE (recog_operand
[i
]) == CONST
1062 && ! rtx_equal_p (pic_pc_rtx
, recog_operand
[i
])))
1070 /* Return true if X is an address which needs a temporary register when
1071 reloaded while generating PIC code. */
1074 pic_address_needs_scratch (x
)
1077 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1078 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1079 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1080 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1081 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1087 /* Legitimize PIC addresses. If the address is already position-independent,
1088 we return ORIG. Newly generated position-independent addresses go into a
1089 reg. This is REG if non zero, otherwise we allocate register(s) as
1093 legitimize_pic_address (orig
, mode
, reg
)
1095 enum machine_mode mode
;
1098 if (GET_CODE (orig
) == SYMBOL_REF
)
1100 rtx pic_ref
, address
;
1105 if (reload_in_progress
|| reload_completed
)
1108 reg
= gen_reg_rtx (Pmode
);
1113 /* If not during reload, allocate another temp reg here for loading
1114 in the address, so that these instructions can be optimized
1116 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
1117 ? reg
: gen_reg_rtx (Pmode
));
1119 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
1120 won't get confused into thinking that these two instructions
1121 are loading in the true address of the symbol. If in the
1122 future a PIC rtx exists, that should be used instead. */
1123 emit_insn (gen_rtx (SET
, VOIDmode
, temp_reg
,
1124 gen_rtx (HIGH
, Pmode
,
1125 gen_rtx (UNSPEC
, Pmode
,
1126 gen_rtvec (1, orig
),
1128 emit_insn (gen_rtx (SET
, VOIDmode
, temp_reg
,
1129 gen_rtx (LO_SUM
, Pmode
, temp_reg
,
1130 gen_rtx (UNSPEC
, Pmode
,
1131 gen_rtvec (1, orig
),
1138 pic_ref
= gen_rtx (MEM
, Pmode
,
1139 gen_rtx (PLUS
, Pmode
,
1140 pic_offset_table_rtx
, address
));
1141 current_function_uses_pic_offset_table
= 1;
1142 RTX_UNCHANGING_P (pic_ref
) = 1;
1143 insn
= emit_move_insn (reg
, pic_ref
);
1144 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1146 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_EQUAL
, orig
,
1150 else if (GET_CODE (orig
) == CONST
)
1154 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1155 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1160 if (reload_in_progress
|| reload_completed
)
1163 reg
= gen_reg_rtx (Pmode
);
1166 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1168 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1169 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1170 base
== reg
? 0 : reg
);
1175 if (GET_CODE (offset
) == CONST_INT
)
1177 if (SMALL_INT (offset
))
1178 return plus_constant_for_output (base
, INTVAL (offset
));
1179 else if (! reload_in_progress
&& ! reload_completed
)
1180 offset
= force_reg (Pmode
, offset
);
1182 /* If we reach here, then something is seriously wrong. */
1185 return gen_rtx (PLUS
, Pmode
, base
, offset
);
1187 else if (GET_CODE (orig
) == LABEL_REF
)
1188 current_function_uses_pic_offset_table
= 1;
1193 /* Set up PIC-specific rtl. This should not cause any insns
1201 /* Emit special PIC prologues and epilogues. */
1206 /* The table we use to reference PIC data. */
1207 rtx global_offset_table
;
1208 /* Labels to get the PC in the prologue of this function. */
1211 int orig_flag_pic
= flag_pic
;
1213 if (current_function_uses_pic_offset_table
== 0)
1220 l1
= gen_label_rtx ();
1221 l2
= gen_label_rtx ();
1226 /* Note that we pun calls and jumps here! */
1227 emit_jump_insn (gen_rtx (PARALLEL
, VOIDmode
,
1229 gen_rtx (SET
, VOIDmode
, pc_rtx
, gen_rtx (LABEL_REF
, VOIDmode
, l2
)),
1230 gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, SImode
, 15), gen_rtx (LABEL_REF
, VOIDmode
, l2
)))));
1233 /* Initialize every time through, since we can't easily
1234 know this to be permanent. */
1235 global_offset_table
= gen_rtx (SYMBOL_REF
, Pmode
, "_GLOBAL_OFFSET_TABLE_");
1236 pic_pc_rtx
= gen_rtx (CONST
, Pmode
,
1237 gen_rtx (MINUS
, Pmode
,
1238 global_offset_table
,
1239 gen_rtx (CONST
, Pmode
,
1240 gen_rtx (MINUS
, Pmode
,
1241 gen_rtx (LABEL_REF
, VOIDmode
, l1
),
1244 if (Pmode
== DImode
)
1245 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
1247 gen_rtx (SET
, VOIDmode
, pic_offset_table_rtx
,
1248 gen_rtx (HIGH
, Pmode
, pic_pc_rtx
)),
1249 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, Pmode
, 1)))));
1251 emit_insn (gen_rtx (SET
, VOIDmode
, pic_offset_table_rtx
,
1252 gen_rtx (HIGH
, Pmode
, pic_pc_rtx
)));
1254 emit_insn (gen_rtx (SET
, VOIDmode
,
1255 pic_offset_table_rtx
,
1256 gen_rtx (LO_SUM
, Pmode
,
1257 pic_offset_table_rtx
, pic_pc_rtx
)));
1258 emit_insn (gen_rtx (SET
, VOIDmode
,
1259 pic_offset_table_rtx
,
1260 gen_rtx (PLUS
, Pmode
,
1261 pic_offset_table_rtx
, gen_rtx (REG
, Pmode
, 15))));
1262 /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */
1263 LABEL_PRESERVE_P (l1
) = 1;
1264 LABEL_PRESERVE_P (l2
) = 1;
1265 flag_pic
= orig_flag_pic
;
1267 seq
= gen_sequence ();
1269 emit_insn_after (seq
, get_insns ());
1271 /* Need to emit this whether or not we obey regdecls,
1272 since setjmp/longjmp can cause life info to screw up. */
1273 emit_insn (gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
));
1276 /* Emit insns to move operands[1] into operands[0].
1278 Return 1 if we have written out everything that needs to be done to
1279 do the move. Otherwise, return 0 and the caller will emit the move
1283 emit_move_sequence (operands
, mode
)
1285 enum machine_mode mode
;
1287 register rtx operand0
= operands
[0];
1288 register rtx operand1
= operands
[1];
1290 if (CONSTANT_P (operand1
) && flag_pic
1291 && pic_address_needs_scratch (operand1
))
1292 operands
[1] = operand1
= legitimize_pic_address (operand1
, mode
, 0);
1294 /* Handle most common case first: storing into a register. */
1295 if (register_operand (operand0
, mode
))
1297 if (register_operand (operand1
, mode
)
1298 || (GET_CODE (operand1
) == CONST_INT
&& SMALL_INT (operand1
))
1299 || (GET_CODE (operand1
) == CONST_DOUBLE
1300 && arith_double_operand (operand1
, DImode
))
1301 || (GET_CODE (operand1
) == HIGH
&& GET_MODE (operand1
) != DImode
)
1302 /* Only `general_operands' can come here, so MEM is ok. */
1303 || GET_CODE (operand1
) == MEM
)
1305 /* Run this case quickly. */
1306 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
1310 else if (GET_CODE (operand0
) == MEM
)
1312 if (register_operand (operand1
, mode
) || operand1
== const0_rtx
)
1314 /* Run this case quickly. */
1315 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
1318 if (! reload_in_progress
)
1320 operands
[0] = validize_mem (operand0
);
1321 operands
[1] = operand1
= force_reg (mode
, operand1
);
1325 /* Simplify the source if we need to. Must handle DImode HIGH operators
1326 here because such a move needs a clobber added. */
1327 if ((GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
1328 || (GET_CODE (operand1
) == HIGH
&& GET_MODE (operand1
) == DImode
))
1330 if (flag_pic
&& symbolic_operand (operand1
, mode
))
1332 rtx temp_reg
= reload_in_progress
? operand0
: 0;
1334 operands
[1] = legitimize_pic_address (operand1
, mode
, temp_reg
);
1336 else if (GET_CODE (operand1
) == CONST_INT
1337 ? (! SMALL_INT (operand1
)
1338 && (INTVAL (operand1
) & 0x3ff) != 0)
1339 : (GET_CODE (operand1
) == CONST_DOUBLE
1340 ? ! arith_double_operand (operand1
, DImode
)
1343 /* For DImode values, temp must be operand0 because of the way
1344 HI and LO_SUM work. The LO_SUM operator only copies half of
1345 the LSW from the dest of the HI operator. If the LO_SUM dest is
1346 not the same as the HI dest, then the MSW of the LO_SUM dest will
1349 ??? The real problem here is that the ...(HI:DImode pattern emits
1350 multiple instructions, and the ...(LO_SUM:DImode pattern emits
1351 one instruction. This fails, because the compiler assumes that
1352 LO_SUM copies all bits of the first operand to its dest. Better
1353 would be to have the HI pattern emit one instruction and the
1354 LO_SUM pattern multiple instructions. Even better would be
1355 to use four rtl insns. */
1356 rtx temp
= ((reload_in_progress
|| mode
== DImode
)
1357 ? operand0
: gen_reg_rtx (mode
));
1359 if (TARGET_V9
&& mode
== DImode
)
1361 int high_operand
= 0;
1363 /* If the operand is already a HIGH, then remove the HIGH so
1364 that we won't get duplicate HIGH operators in this insn.
1365 Also, we must store the result into the original dest,
1366 because that is where the following LO_SUM expects it. */
1367 if (GET_CODE (operand1
) == HIGH
)
1369 operand1
= XEXP (operand1
, 0);
1373 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
1375 gen_rtx (SET
, VOIDmode
, temp
,
1376 gen_rtx (HIGH
, mode
, operand1
)),
1377 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, DImode
, 1)))));
1379 /* If this was a high operand, then we are now finished. */
1384 emit_insn (gen_rtx (SET
, VOIDmode
, temp
,
1385 gen_rtx (HIGH
, mode
, operand1
)));
1387 operands
[1] = gen_rtx (LO_SUM
, mode
, temp
, operand1
);
1391 if (GET_CODE (operand1
) == LABEL_REF
&& flag_pic
)
1393 /* The procedure for doing this involves using a call instruction to
1394 get the pc into o7. We need to indicate this explicitly because
1395 the tablejump pattern assumes that it can use this value also. */
1396 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
1398 gen_rtx (SET
, VOIDmode
, operand0
,
1400 gen_rtx (SET
, VOIDmode
,
1401 gen_rtx (REG
, mode
, 15),
1406 /* Now have insn-emit do whatever it normally does. */
1410 /* Return the best assembler insn template
1411 for moving operands[1] into operands[0] as a fullword. */
1414 singlemove_string (operands
)
1417 if (GET_CODE (operands
[0]) == MEM
)
1419 if (GET_CODE (operands
[1]) != MEM
)
1424 else if (GET_CODE (operands
[1]) == MEM
)
1426 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1431 /* Must be SFmode, otherwise this doesn't make sense. */
1432 if (GET_MODE (operands
[1]) != SFmode
)
1435 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1436 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1437 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
);
1439 if (CONST_OK_FOR_LETTER_P (i
, 'I'))
1441 else if ((i
& 0x000003FF) != 0)
1442 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1444 return "sethi %%hi(%a1),%0";
1446 else if (GET_CODE (operands
[1]) == CONST_INT
1447 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands
[1]), 'I'))
1449 int i
= INTVAL (operands
[1]);
1451 /* If all low order 10 bits are clear, then we only need a single
1452 sethi insn to load the constant. */
1453 if ((i
& 0x000003FF) != 0)
1454 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1456 return "sethi %%hi(%a1),%0";
1458 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1462 /* Return non-zero if it is OK to assume that the given memory operand is
1463 aligned at least to a 8-byte boundary. This should only be called
1464 for memory accesses whose size is 8 bytes or larger. */
1472 register rtx offset
;
1474 if (GET_CODE (mem
) != MEM
)
1475 return 0; /* It's gotta be a MEM! */
1477 addr
= XEXP (mem
, 0);
1479 /* Now that all misaligned double parms are copied on function entry,
1480 we can assume any 64-bit object is 64-bit aligned except those which
1481 are at unaligned offsets from the stack or frame pointer. If the
1482 TARGET_UNALIGNED_DOUBLES switch is given, we do not make this
1485 /* See what register we use in the address. */
1487 if (GET_CODE (addr
) == PLUS
)
1489 if (GET_CODE (XEXP (addr
, 0)) == REG
1490 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
1492 base
= XEXP (addr
, 0);
1493 offset
= XEXP (addr
, 1);
1496 else if (GET_CODE (addr
) == REG
)
1499 offset
= const0_rtx
;
1502 /* If it's the stack or frame pointer, check offset alignment.
1503 We can have improper alignment in the function entry code. */
1505 && (REGNO (base
) == FRAME_POINTER_REGNUM
1506 || REGNO (base
) == STACK_POINTER_REGNUM
))
1508 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & 0x7) == 0)
1511 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
1512 is true, in which case we can only assume that an access is aligned if
1513 it is to a constant address, or the address involves a LO_SUM.
1515 We used to assume an address was aligned if MEM_IN_STRUCT_P was true.
1516 That assumption was deleted so that gcc generated code can be used with
1517 memory allocators that only guarantee 4 byte alignment. */
1518 else if (! TARGET_UNALIGNED_DOUBLES
|| CONSTANT_P (addr
)
1519 || GET_CODE (addr
) == LO_SUM
)
1522 /* An obviously unaligned address. */
1526 enum optype
{ REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
};
1528 /* Output assembler code to perform a doubleword move insn
1529 with operands OPERANDS. This is very similar to the following
1530 output_move_quad function. */
1533 output_move_double (operands
)
1536 register rtx op0
= operands
[0];
1537 register rtx op1
= operands
[1];
1538 register enum optype optype0
;
1539 register enum optype optype1
;
1543 int highest_first
= 0;
1544 int no_addreg1_decrement
= 0;
1546 /* First classify both operands. */
1550 else if (offsettable_memref_p (op0
))
1552 else if (GET_CODE (op0
) == MEM
)
1559 else if (CONSTANT_P (op1
))
1561 else if (offsettable_memref_p (op1
))
1563 else if (GET_CODE (op1
) == MEM
)
1568 /* Check for the cases that the operand constraints are not
1569 supposed to allow to happen. Abort if we get one,
1570 because generating code for these cases is painful. */
1572 if (optype0
== RNDOP
|| optype1
== RNDOP
1573 || (optype0
== MEM
&& optype1
== MEM
))
1576 /* If an operand is an unoffsettable memory ref, find a register
1577 we can increment temporarily to make it refer to the second word. */
1579 if (optype0
== MEMOP
)
1580 addreg0
= find_addr_reg (XEXP (op0
, 0));
1582 if (optype1
== MEMOP
)
1583 addreg1
= find_addr_reg (XEXP (op1
, 0));
1585 /* Ok, we can do one word at a time.
1586 Set up in LATEHALF the operands to use for the
1587 high-numbered (least significant) word and in some cases alter the
1588 operands in OPERANDS to be suitable for the low-numbered word. */
1590 if (optype0
== REGOP
)
1591 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 1);
1592 else if (optype0
== OFFSOP
)
1593 latehalf
[0] = adj_offsettable_operand (op0
, 4);
1597 if (optype1
== REGOP
)
1598 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 1);
1599 else if (optype1
== OFFSOP
)
1600 latehalf
[1] = adj_offsettable_operand (op1
, 4);
1601 else if (optype1
== CNSTOP
)
1605 if (arith_double_operand (op1
, DImode
))
1607 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
,
1608 CONST_DOUBLE_LOW (op1
));
1613 /* The only way to handle CONST_DOUBLEs or other 64 bit
1614 constants here is to use a temporary, such as is done
1615 for the V9 DImode sethi insn pattern. This is not
1616 a practical solution, so abort if we reach here.
1617 The md file should always force such constants to
1623 split_double (op1
, &operands
[1], &latehalf
[1]);
1628 /* Easy case: try moving both words at once. Check for moving between
1629 an even/odd register pair and a memory location. */
1630 if ((optype0
== REGOP
&& optype1
!= REGOP
&& optype1
!= CNSTOP
1631 && (TARGET_V9
|| (REGNO (op0
) & 1) == 0))
1632 || (optype0
!= REGOP
&& optype0
!= CNSTOP
&& optype1
== REGOP
1633 && (TARGET_V9
|| (REGNO (op1
) & 1) == 0)))
1635 register rtx mem
,reg
;
1637 if (optype0
== REGOP
)
1638 mem
= op1
, reg
= op0
;
1640 mem
= op0
, reg
= op1
;
1642 /* In v9, ldd can be used for word aligned addresses, so technically
1643 some of this logic is unneeded. We still avoid ldd if the address
1644 is obviously unaligned though. */
1646 if (mem_aligned_8 (mem
)
1647 /* If this is a floating point register higher than %f31,
1648 then we *must* use an aligned load, since `ld' will not accept
1649 the register number. */
1650 || (TARGET_V9
&& REGNO (reg
) >= 64))
1652 if (FP_REG_P (reg
) || ! TARGET_V9
)
1653 return (mem
== op1
? "ldd %1,%0" : "std %1,%0");
1655 return (mem
== op1
? "ldx %1,%0" : "stx %1,%0");
1661 if (optype0
== REGOP
&& optype1
== REGOP
)
1664 return "fmovd %1,%0";
1670 /* If the first move would clobber the source of the second one,
1671 do them in the other order. */
1673 /* Overlapping registers. */
1674 if (optype0
== REGOP
&& optype1
== REGOP
1675 && REGNO (op0
) == REGNO (latehalf
[1]))
1678 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1679 /* Do low-numbered word. */
1680 return singlemove_string (operands
);
1682 /* Loading into a register which overlaps a register used in the address. */
1683 else if (optype0
== REGOP
&& optype1
!= REGOP
1684 && reg_overlap_mentioned_p (op0
, op1
))
1686 /* If both halves of dest are used in the src memory address,
1687 add the two regs and put them in the low reg (op0).
1688 Then it works to load latehalf first. */
1689 if (reg_mentioned_p (op0
, XEXP (op1
, 0))
1690 && reg_mentioned_p (latehalf
[0], XEXP (op1
, 0)))
1693 xops
[0] = latehalf
[0];
1695 output_asm_insn ("add %1,%0,%1", xops
);
1696 operands
[1] = gen_rtx (MEM
, DImode
, op0
);
1697 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1701 /* Only one register in the dest is used in the src memory address,
1702 and this is the first register of the dest, so we want to do
1703 the late half first here also. */
1704 else if (! reg_mentioned_p (latehalf
[0], XEXP (op1
, 0)))
1706 /* Only one register in the dest is used in the src memory address,
1707 and this is the second register of the dest, so we want to do
1708 the late half last. If addreg1 is set, and addreg1 is the same
1709 register as latehalf, then we must suppress the trailing decrement,
1710 because it would clobber the value just loaded. */
1711 else if (addreg1
&& reg_mentioned_p (addreg1
, latehalf
[0]))
1712 no_addreg1_decrement
= 1;
1715 /* Normal case: do the two words, low-numbered first.
1716 Overlap case (highest_first set): do high-numbered word first. */
1718 if (! highest_first
)
1719 output_asm_insn (singlemove_string (operands
), operands
);
1721 /* Make any unoffsettable addresses point at high-numbered word. */
1723 output_asm_insn ("add %0,0x4,%0", &addreg0
);
1725 output_asm_insn ("add %0,0x4,%0", &addreg1
);
1728 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1730 /* Undo the adds we just did. */
1732 output_asm_insn ("add %0,-0x4,%0", &addreg0
);
1733 if (addreg1
&& ! no_addreg1_decrement
)
1734 output_asm_insn ("add %0,-0x4,%0", &addreg1
);
1737 output_asm_insn (singlemove_string (operands
), operands
);
1742 /* Output assembler code to perform a quadword move insn
1743 with operands OPERANDS. This is very similar to the preceding
1744 output_move_double function. */
1747 output_move_quad (operands
)
1750 register rtx op0
= operands
[0];
1751 register rtx op1
= operands
[1];
1752 register enum optype optype0
;
1753 register enum optype optype1
;
1758 /* First classify both operands. */
1762 else if (offsettable_memref_p (op0
))
1764 else if (GET_CODE (op0
) == MEM
)
1771 else if (CONSTANT_P (op1
))
1773 else if (offsettable_memref_p (op1
))
1775 else if (GET_CODE (op1
) == MEM
)
1780 /* Check for the cases that the operand constraints are not
1781 supposed to allow to happen. Abort if we get one,
1782 because generating code for these cases is painful. */
1784 if (optype0
== RNDOP
|| optype1
== RNDOP
1785 || (optype0
== MEM
&& optype1
== MEM
))
1788 /* If an operand is an unoffsettable memory ref, find a register
1789 we can increment temporarily to make it refer to the later words. */
1791 if (optype0
== MEMOP
)
1792 addreg0
= find_addr_reg (XEXP (op0
, 0));
1794 if (optype1
== MEMOP
)
1795 addreg1
= find_addr_reg (XEXP (op1
, 0));
1797 /* Ok, we can do one word at a time.
1798 Set up in wordpart the operands to use for each word of the arguments. */
1800 if (optype0
== REGOP
)
1802 wordpart
[0][0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 0);
1803 wordpart
[1][0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 1);
1804 wordpart
[2][0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 2);
1805 wordpart
[3][0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 3);
1807 else if (optype0
== OFFSOP
)
1809 wordpart
[0][0] = adj_offsettable_operand (op0
, 0);
1810 wordpart
[1][0] = adj_offsettable_operand (op0
, 4);
1811 wordpart
[2][0] = adj_offsettable_operand (op0
, 8);
1812 wordpart
[3][0] = adj_offsettable_operand (op0
, 12);
1816 wordpart
[0][0] = op0
;
1817 wordpart
[1][0] = op0
;
1818 wordpart
[2][0] = op0
;
1819 wordpart
[3][0] = op0
;
1822 if (optype1
== REGOP
)
1824 wordpart
[0][1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 0);
1825 wordpart
[1][1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 1);
1826 wordpart
[2][1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 2);
1827 wordpart
[3][1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 3);
1829 else if (optype1
== OFFSOP
)
1831 wordpart
[0][1] = adj_offsettable_operand (op1
, 0);
1832 wordpart
[1][1] = adj_offsettable_operand (op1
, 4);
1833 wordpart
[2][1] = adj_offsettable_operand (op1
, 8);
1834 wordpart
[3][1] = adj_offsettable_operand (op1
, 12);
1836 else if (optype1
== CNSTOP
)
1841 /* This only works for TFmode floating point constants. */
1842 if (GET_CODE (op1
) != CONST_DOUBLE
|| GET_MODE (op1
) != TFmode
)
1845 REAL_VALUE_FROM_CONST_DOUBLE (r
, op1
);
1846 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1848 wordpart
[0][1] = GEN_INT (l
[0]);
1849 wordpart
[1][1] = GEN_INT (l
[1]);
1850 wordpart
[2][1] = GEN_INT (l
[2]);
1851 wordpart
[3][1] = GEN_INT (l
[3]);
1855 wordpart
[0][1] = op1
;
1856 wordpart
[1][1] = op1
;
1857 wordpart
[2][1] = op1
;
1858 wordpart
[3][1] = op1
;
1861 /* Easy case: try moving the quad as two pairs. Check for moving between
1862 an even/odd register pair and a memory location.
1863 Also handle new v9 fp regs here. */
1864 /* ??? Should also handle the case of non-offsettable addresses here.
1865 We can at least do the first pair as a ldd/std, and then do the third
1866 and fourth words individually. */
1867 if ((optype0
== REGOP
&& optype1
== OFFSOP
&& (REGNO (op0
) & 1) == 0)
1868 || (optype0
== OFFSOP
&& optype1
== REGOP
&& (REGNO (op1
) & 1) == 0))
1872 if (optype0
== REGOP
)
1873 mem
= op1
, reg
= op0
;
1875 mem
= op0
, reg
= op1
;
1877 if (mem_aligned_8 (mem
)
1878 /* If this is a floating point register higher than %f31,
1879 then we *must* use an aligned load, since `ld' will not accept
1880 the register number. */
1881 || (TARGET_V9
&& REGNO (reg
) >= 64))
1883 if (TARGET_V9
&& FP_REG_P (reg
))
1885 if ((REGNO (reg
) & 3) != 0)
1887 return (mem
== op1
? "ldq %1,%0" : "stq %1,%0");
1889 operands
[2] = adj_offsettable_operand (mem
, 8);
1891 return TARGET_V9
? "ldx %1,%0;ldx %2,%R0" : "ldd %1,%0;ldd %2,%S0";
1893 return TARGET_V9
? "stx %1,%0;stx %R1,%2" : "std %1,%0;std %S1,%2";
1897 /* If the first move would clobber the source of the second one,
1898 do them in the other order. */
1900 /* Overlapping registers. */
1901 if (optype0
== REGOP
&& optype1
== REGOP
1902 && (REGNO (op0
) == REGNO (wordpart
[1][3])
1903 || REGNO (op0
) == REGNO (wordpart
[1][2])
1904 || REGNO (op0
) == REGNO (wordpart
[1][1])))
1906 /* Do fourth word. */
1907 output_asm_insn (singlemove_string (wordpart
[3]), wordpart
[3]);
1908 /* Do the third word. */
1909 output_asm_insn (singlemove_string (wordpart
[2]), wordpart
[2]);
1910 /* Do the second word. */
1911 output_asm_insn (singlemove_string (wordpart
[1]), wordpart
[1]);
1912 /* Do lowest-numbered word. */
1913 return singlemove_string (wordpart
[0]);
1915 /* Loading into a register which overlaps a register used in the address. */
1916 if (optype0
== REGOP
&& optype1
!= REGOP
1917 && reg_overlap_mentioned_p (op0
, op1
))
1919 /* ??? Not implemented yet. This is a bit complicated, because we
1920 must load which ever part overlaps the address last. If the address
1921 is a double-reg address, then there are two parts which need to
1922 be done last, which is impossible. We would need a scratch register
1927 /* Normal case: move the four words in lowest to higest address order. */
1929 output_asm_insn (singlemove_string (wordpart
[0]), wordpart
[0]);
1931 /* Make any unoffsettable addresses point at the second word. */
1933 output_asm_insn ("add %0,0x4,%0", &addreg0
);
1935 output_asm_insn ("add %0,0x4,%0", &addreg1
);
1937 /* Do the second word. */
1938 output_asm_insn (singlemove_string (wordpart
[1]), wordpart
[1]);
1940 /* Make any unoffsettable addresses point at the third word. */
1942 output_asm_insn ("add %0,0x4,%0", &addreg0
);
1944 output_asm_insn ("add %0,0x4,%0", &addreg1
);
1946 /* Do the third word. */
1947 output_asm_insn (singlemove_string (wordpart
[2]), wordpart
[2]);
1949 /* Make any unoffsettable addresses point at the fourth word. */
1951 output_asm_insn ("add %0,0x4,%0", &addreg0
);
1953 output_asm_insn ("add %0,0x4,%0", &addreg1
);
1955 /* Do the fourth word. */
1956 output_asm_insn (singlemove_string (wordpart
[3]), wordpart
[3]);
1958 /* Undo the adds we just did. */
1960 output_asm_insn ("add %0,-0xc,%0", &addreg0
);
1962 output_asm_insn ("add %0,-0xc,%0", &addreg1
);
1967 /* Output assembler code to perform a doubleword move insn with operands
1968 OPERANDS, one of which must be a floating point register. */
1971 output_fp_move_double (operands
)
1974 if (FP_REG_P (operands
[0]))
1976 if (FP_REG_P (operands
[1]))
1979 return "fmovd %1,%0";
1981 return "fmovs %1,%0\n\tfmovs %R1,%R0";
1983 else if (GET_CODE (operands
[1]) == REG
)
1986 return output_move_double (operands
);
1988 else if (FP_REG_P (operands
[1]))
1990 if (GET_CODE (operands
[0]) == REG
)
1993 return output_move_double (operands
);
1998 /* Output assembler code to perform a quadword move insn with operands
1999 OPERANDS, one of which must be a floating point register. */
2002 output_fp_move_quad (operands
)
2005 register rtx op0
= operands
[0];
2006 register rtx op1
= operands
[1];
2013 return "fmovq %1,%0";
2015 return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0";
2017 else if (GET_CODE (op1
) == REG
)
2020 return output_move_quad (operands
);
2022 else if (FP_REG_P (op1
))
2024 if (GET_CODE (op0
) == REG
)
2027 return output_move_quad (operands
);
2033 /* Return a REG that occurs in ADDR with coefficient 1.
2034 ADDR can be effectively incremented by incrementing REG. */
2037 find_addr_reg (addr
)
2040 while (GET_CODE (addr
) == PLUS
)
2042 /* We absolutely can not fudge the frame pointer here, because the
2043 frame pointer must always be 8 byte aligned. It also confuses
2045 if (GET_CODE (XEXP (addr
, 0)) == REG
2046 && REGNO (XEXP (addr
, 0)) != FRAME_POINTER_REGNUM
)
2047 addr
= XEXP (addr
, 0);
2048 else if (GET_CODE (XEXP (addr
, 1)) == REG
2049 && REGNO (XEXP (addr
, 1)) != FRAME_POINTER_REGNUM
)
2050 addr
= XEXP (addr
, 1);
2051 else if (CONSTANT_P (XEXP (addr
, 0)))
2052 addr
= XEXP (addr
, 1);
2053 else if (CONSTANT_P (XEXP (addr
, 1)))
2054 addr
= XEXP (addr
, 0);
2058 if (GET_CODE (addr
) == REG
)
2063 #if 0 /* not currently used */
2066 output_sized_memop (opname
, mode
, signedp
)
2068 enum machine_mode mode
;
2071 static char *ld_size_suffix_u
[] = { "ub", "uh", "", "?", "d" };
2072 static char *ld_size_suffix_s
[] = { "sb", "sh", "", "?", "d" };
2073 static char *st_size_suffix
[] = { "b", "h", "", "?", "d" };
2074 char **opnametab
, *modename
;
2076 if (opname
[0] == 'l')
2078 opnametab
= ld_size_suffix_s
;
2080 opnametab
= ld_size_suffix_u
;
2082 opnametab
= st_size_suffix
;
2083 modename
= opnametab
[GET_MODE_SIZE (mode
) >> 1];
2085 fprintf (asm_out_file
, "\t%s%s", opname
, modename
);
2089 output_move_with_extension (operands
)
2092 if (GET_MODE (operands
[2]) == HImode
)
2093 output_asm_insn ("sll %2,0x10,%0", operands
);
2094 else if (GET_MODE (operands
[2]) == QImode
)
2095 output_asm_insn ("sll %2,0x18,%0", operands
);
2099 #endif /* not currently used */
2102 /* ??? These are only used by the movstrsi pattern, but we get better code
2103 in general without that, because emit_block_move can do just as good a
2104 job as this function does when alignment and size are known. When they
2105 aren't known, a call to strcpy may be faster anyways, because it is
2106 likely to be carefully crafted assembly language code, and below we just
2107 do a byte-wise copy.
2109 Also, emit_block_move expands into multiple read/write RTL insns, which
2110 can then be optimized, whereas our movstrsi pattern can not be optimized
2113 /* Load the address specified by OPERANDS[3] into the register
2114 specified by OPERANDS[0].
2116 OPERANDS[3] may be the result of a sum, hence it could either be:
2121 (3) REG + REG + CONST_INT
2122 (4) REG + REG (special case of 3).
2124 Note that (3) is not a legitimate address.
2125 All cases are handled here. */
2128 output_load_address (operands
)
2133 if (CONSTANT_P (operands
[3]))
2135 output_asm_insn ("set %3,%0", operands
);
2139 if (REG_P (operands
[3]))
2141 if (REGNO (operands
[0]) != REGNO (operands
[3]))
2142 output_asm_insn ("mov %3,%0", operands
);
2146 if (GET_CODE (operands
[3]) != PLUS
)
2149 base
= XEXP (operands
[3], 0);
2150 offset
= XEXP (operands
[3], 1);
2152 if (GET_CODE (base
) == CONST_INT
)
2159 if (GET_CODE (offset
) != CONST_INT
)
2161 /* Operand is (PLUS (REG) (REG)). */
2163 offset
= const0_rtx
;
2169 operands
[7] = offset
;
2170 if (SMALL_INT (offset
))
2171 output_asm_insn ("add %6,%7,%0", operands
);
2173 output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands
);
2175 else if (GET_CODE (base
) == PLUS
)
2177 operands
[6] = XEXP (base
, 0);
2178 operands
[7] = XEXP (base
, 1);
2179 operands
[8] = offset
;
2181 if (SMALL_INT (offset
))
2182 output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands
);
2184 output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands
);
2190 /* Output code to place a size count SIZE in register REG.
2191 ALIGN is the size of the unit of transfer.
2193 Because block moves are pipelined, we don't include the
2194 first element in the transfer of SIZE to REG. */
2197 output_size_for_block_move (size
, reg
, align
)
2204 xoperands
[1] = size
;
2205 xoperands
[2] = align
;
2206 if (GET_CODE (size
) == REG
)
2207 output_asm_insn ("sub %1,%2,%0", xoperands
);
2211 = gen_rtx (CONST_INT
, VOIDmode
, INTVAL (size
) - INTVAL (align
));
2212 output_asm_insn ("set %1,%0", xoperands
);
2216 /* Emit code to perform a block move.
2218 OPERANDS[0] is the destination.
2219 OPERANDS[1] is the source.
2220 OPERANDS[2] is the size.
2221 OPERANDS[3] is the alignment safe to use.
2222 OPERANDS[4] is a register we can safely clobber as a temp. */
2225 output_block_move (operands
)
2228 /* A vector for our computed operands. Note that load_output_address
2229 makes use of (and can clobber) up to the 8th element of this vector. */
2232 static int movstrsi_label
= 0;
2234 rtx temp1
= operands
[4];
2235 rtx sizertx
= operands
[2];
2236 rtx alignrtx
= operands
[3];
2237 int align
= INTVAL (alignrtx
);
2238 char label3
[30], label5
[30];
2240 xoperands
[0] = operands
[0];
2241 xoperands
[1] = operands
[1];
2242 xoperands
[2] = temp1
;
2244 /* We can't move more than this many bytes at a time because we have only
2245 one register, %g1, to move them through. */
2246 if (align
> UNITS_PER_WORD
)
2248 align
= UNITS_PER_WORD
;
2249 alignrtx
= gen_rtx (CONST_INT
, VOIDmode
, UNITS_PER_WORD
);
2252 /* We consider 8 ld/st pairs, for a total of 16 inline insns to be
2253 reasonable here. (Actually will emit a maximum of 18 inline insns for
2254 the case of size == 31 and align == 4). */
2256 if (GET_CODE (sizertx
) == CONST_INT
&& (INTVAL (sizertx
) / align
) <= 8
2257 && memory_address_p (QImode
, plus_constant_for_output (xoperands
[0],
2259 && memory_address_p (QImode
, plus_constant_for_output (xoperands
[1],
2262 int size
= INTVAL (sizertx
);
2265 /* We will store different integers into this particular RTX. */
2266 xoperands
[2] = rtx_alloc (CONST_INT
);
2267 PUT_MODE (xoperands
[2], VOIDmode
);
2269 /* This case is currently not handled. Abort instead of generating
2271 if (align
> UNITS_PER_WORD
)
2274 if (TARGET_V9
&& align
>= 8)
2276 for (i
= (size
>> 3) - 1; i
>= 0; i
--)
2278 INTVAL (xoperands
[2]) = (i
<< 3) + offset
;
2279 output_asm_insn ("ldx [%a1+%2],%%g1\n\tstx %%g1,[%a0+%2]",
2282 offset
+= (size
& ~0x7);
2290 for (i
= (size
>> 2) - 1; i
>= 0; i
--)
2292 INTVAL (xoperands
[2]) = (i
<< 2) + offset
;
2293 output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]",
2296 offset
+= (size
& ~0x3);
2304 for (i
= (size
>> 1) - 1; i
>= 0; i
--)
2306 INTVAL (xoperands
[2]) = (i
<< 1) + offset
;
2307 output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]",
2310 offset
+= (size
& ~0x1);
2318 for (i
= size
- 1; i
>= 0; i
--)
2320 INTVAL (xoperands
[2]) = i
+ offset
;
2321 output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]",
2327 /* We should never reach here. */
2331 /* If the size isn't known to be a multiple of the alignment,
2332 we have to do it in smaller pieces. If we could determine that
2333 the size was a multiple of 2 (or whatever), we could be smarter
2335 if (GET_CODE (sizertx
) != CONST_INT
)
2339 int size
= INTVAL (sizertx
);
2340 while (size
% align
)
2344 if (align
!= INTVAL (alignrtx
))
2345 alignrtx
= gen_rtx (CONST_INT
, VOIDmode
, align
);
2347 xoperands
[3] = gen_rtx (CONST_INT
, VOIDmode
, movstrsi_label
++);
2348 xoperands
[4] = gen_rtx (CONST_INT
, VOIDmode
, align
);
2349 xoperands
[5] = gen_rtx (CONST_INT
, VOIDmode
, movstrsi_label
++);
2351 ASM_GENERATE_INTERNAL_LABEL (label3
, "Lm", INTVAL (xoperands
[3]));
2352 ASM_GENERATE_INTERNAL_LABEL (label5
, "Lm", INTVAL (xoperands
[5]));
2354 /* This is the size of the transfer. Emit code to decrement the size
2355 value by ALIGN, and store the result in the temp1 register. */
2356 output_size_for_block_move (sizertx
, temp1
, alignrtx
);
2358 /* Must handle the case when the size is zero or negative, so the first thing
2359 we do is compare the size against zero, and only copy bytes if it is
2360 zero or greater. Note that we have already subtracted off the alignment
2361 once, so we must copy 1 alignment worth of bytes if the size is zero
2364 The SUN assembler complains about labels in branch delay slots, so we
2365 do this before outputting the load address, so that there will always
2366 be a harmless insn between the branch here and the next label emitted
2372 sprintf (pattern
, "cmp %%2,0\n\tbl %s", &label5
[1]);
2373 output_asm_insn (pattern
, xoperands
);
2376 zoperands
[0] = operands
[0];
2377 zoperands
[3] = plus_constant_for_output (operands
[0], align
);
2378 output_load_address (zoperands
);
2380 /* ??? This might be much faster if the loops below were preconditioned
2383 That is, at run time, copy enough bytes one at a time to ensure that the
2384 target and source addresses are aligned to the the largest possible
2385 alignment. Then use a preconditioned unrolled loop to copy say 16
2386 bytes at a time. Then copy bytes one at a time until finish the rest. */
2388 /* Output the first label separately, so that it is spaced properly. */
2390 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "Lm", INTVAL (xoperands
[3]));
2394 register char *ld_suffix
= ((align
== 1) ? "ub" : (align
== 2) ? "uh"
2395 : (align
== 8 && TARGET_V9
) ? "x" : "");
2396 register char *st_suffix
= ((align
== 1) ? "b" : (align
== 2) ? "h"
2397 : (align
== 8 && TARGET_V9
) ? "x" : "");
2399 sprintf (pattern
, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix
, &label3
[1], st_suffix
, &label5
[1]);
2400 output_asm_insn (pattern
, xoperands
);
2407 /* Output reasonable peephole for set-on-condition-code insns.
2408 Note that these insns assume a particular way of defining
2409 labels. Therefore, *both* sparc.h and this function must
2410 be changed if a new syntax is needed. */
2413 output_scc_insn (operands
, insn
)
2417 static char string
[100];
2418 rtx label
= 0, next
= insn
;
2421 /* Try doing a jump optimization which jump.c can't do for us
2422 because we did not expose that setcc works by using branches.
2424 If this scc insn is followed by an unconditional branch, then have
2425 the jump insn emitted here jump to that location, instead of to
2426 the end of the scc sequence as usual. */
2430 if (GET_CODE (next
) == CODE_LABEL
)
2432 next
= NEXT_INSN (next
);
2436 while (GET_CODE (next
) == NOTE
|| GET_CODE (next
) == CODE_LABEL
);
2438 /* If we are in a sequence, and the following insn is a sequence also,
2439 then just following the current insn's next field will take us to the
2440 first insn of the next sequence, which is the wrong place. We don't
2441 want to optimize with a branch that has had its delay slot filled.
2442 Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next
2443 which fails only if NEXT is such a branch. */
2445 if (next
&& GET_CODE (next
) == JUMP_INSN
&& simplejump_p (next
)
2446 && (! final_sequence
|| NEXT_INSN (PREV_INSN (next
)) == next
))
2447 label
= JUMP_LABEL (next
);
2448 /* If not optimizing, jump label fields are not set. To be safe, always
2449 check here to whether label is still zero. */
2452 label
= gen_label_rtx ();
2456 LABEL_NUSES (label
) += 1;
2458 operands
[2] = label
;
2460 /* If we are in a delay slot, assume it is the delay slot of an fpcc
2461 insn since our type isn't allowed anywhere else. */
2463 /* ??? Fpcc instructions no longer have delay slots, so this code is
2464 probably obsolete. */
2466 /* The fastest way to emit code for this is an annulled branch followed
2467 by two move insns. This will take two cycles if the branch is taken,
2468 and three cycles if the branch is not taken.
2470 However, if we are in the delay slot of another branch, this won't work,
2471 because we can't put a branch in the delay slot of another branch.
2472 The above sequence would effectively take 3 or 4 cycles respectively
2473 since a no op would have be inserted between the two branches.
2474 In this case, we want to emit a move, annulled branch, and then the
2475 second move. This sequence always takes 3 cycles, and hence is faster
2476 when we are in a branch delay slot. */
2480 strcpy (string
, "mov 0,%0\n\t");
2481 strcat (string
, output_cbranch (operands
[1], 0, 2, 0, 1, 0));
2482 strcat (string
, "\n\tmov 1,%0");
2486 strcpy (string
, output_cbranch (operands
[1], 0, 2, 0, 1, 0));
2487 strcat (string
, "\n\tmov 1,%0\n\tmov 0,%0");
2491 strcat (string
, "\n%l2:");
2496 /* Vectors to keep interesting information about registers where it can easily
2497 be got. We use to use the actual mode value as the bit number, but there
2498 are more than 32 modes now. Instead we use two tables: one indexed by
2499 hard register number, and one indexed by mode. */
2501 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2502 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2503 mapped into one sparc_mode_class mode. */
2505 enum sparc_mode_class
{
2507 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
2508 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
2511 /* Modes for condition codes. */
2512 #define C_MODES ((1 << (int) C_MODE) | (1 << (int) CCFP_MODE))
2513 #define CCFP_MODES (1 << (int) CCFP_MODE)
2515 /* Modes for single-word and smaller quantities. */
2516 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2518 /* Modes for double-word and smaller quantities. */
2519 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2521 /* Modes for quad-word and smaller quantities. */
2522 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2524 /* Modes for single-float quantities. We must allow any single word or
2525 smaller quantity. This is because the fix/float conversion instructions
2526 take integer inputs/outputs from the float registers. */
2527 #define SF_MODES (S_MODES)
2529 /* Modes for double-float and smaller quantities. */
2530 #define DF_MODES (S_MODES | D_MODES)
2532 /* ??? Sparc64 fp regs cannot hold DImode values. */
2533 #define DF_MODES64 (SF_MODES | DF_MODE /* | D_MODE*/)
2535 /* Modes for double-float only quantities. */
2536 /* ??? Sparc64 fp regs cannot hold DImode values. */
2537 #define DF_ONLY_MODES ((1 << (int) DF_MODE) /*| (1 << (int) D_MODE)*/)
2539 /* Modes for double-float and larger quantities. */
2540 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2542 /* Modes for quad-float only quantities. */
2543 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2545 /* Modes for quad-float and smaller quantities. */
2546 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2548 /* ??? Sparc64 fp regs cannot hold DImode values. */
2549 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2551 /* Value is 1 if register/mode pair is acceptable on sparc.
2552 The funny mixture of D and T modes is because integer operations
2553 do not specially operate on tetra quantities, so non-quad-aligned
2554 registers can hold quadword quantities (except %o4 and %i4 because
2555 they cross fixed registers. */
2557 /* This points to either the 32 bit or the 64 bit version. */
2558 int *hard_regno_mode_classes
;
2560 static int hard_32bit_mode_classes
[] = {
2561 C_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2562 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
2563 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2564 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
2566 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2567 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2568 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2569 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2572 static int hard_64bit_mode_classes
[] = {
2573 C_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
2574 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
2575 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
2576 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
2578 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
2579 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
2580 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
2581 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
2583 /* The remaining registers do not exist on a non-v9 sparc machine.
2584 FP regs f32 to f63. Only the even numbered registers actually exist,
2585 and none can hold SFmode/SImode values. */
2586 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2587 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2588 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2589 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2592 CCFP_MODE
, CCFP_MODE
, CCFP_MODE
, CCFP_MODE
2595 int sparc_mode_class
[NUM_MACHINE_MODES
];
2602 sparc_arch_type
= TARGET_V9
? ARCH_64BIT
: ARCH_32BIT
;
2604 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
2606 switch (GET_MODE_CLASS (i
))
2609 case MODE_PARTIAL_INT
:
2610 case MODE_COMPLEX_INT
:
2611 if (GET_MODE_SIZE (i
) <= 4)
2612 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
2613 else if (GET_MODE_SIZE (i
) == 8)
2614 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
2615 else if (GET_MODE_SIZE (i
) == 16)
2616 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
2617 else if (GET_MODE_SIZE (i
) == 32)
2618 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
2620 sparc_mode_class
[i
] = 0;
2623 case MODE_COMPLEX_FLOAT
:
2624 if (GET_MODE_SIZE (i
) <= 4)
2625 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
2626 else if (GET_MODE_SIZE (i
) == 8)
2627 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
2628 else if (GET_MODE_SIZE (i
) == 16)
2629 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
2630 else if (GET_MODE_SIZE (i
) == 32)
2631 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
2633 sparc_mode_class
[i
] = 0;
2637 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2638 we must explicitly check for them here. */
2639 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
2640 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
2641 else if (i
== (int) CCmode
|| i
== (int) CC_NOOVmode
2643 || i
== (int) CCXmode
2644 || i
== (int) CCX_NOOVmode
2647 sparc_mode_class
[i
] = 1 << (int) C_MODE
;
2649 sparc_mode_class
[i
] = 0;
2655 hard_regno_mode_classes
= hard_64bit_mode_classes
;
2657 hard_regno_mode_classes
= hard_32bit_mode_classes
;
2660 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
2661 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2662 v9 int regs as it simplifies the code. */
2668 save_regs (file
, low
, high
, base
, offset
, n_regs
)
2677 if (TARGET_V9
&& high
<= 32)
2679 for (i
= low
; i
< high
; i
++)
2681 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2682 fprintf (file
, "\tstx %s,[%s+%d]\n",
2683 reg_names
[i
], base
, offset
+ 4 * n_regs
),
2689 for (i
= low
; i
< high
; i
+= 2)
2691 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2692 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2693 fprintf (file
, "\tstd %s,[%s+%d]\n",
2694 reg_names
[i
], base
, offset
+ 4 * n_regs
),
2697 fprintf (file
, "\tst %s,[%s+%d]\n",
2698 reg_names
[i
], base
, offset
+ 4 * n_regs
),
2700 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2701 fprintf (file
, "\tst %s,[%s+%d]\n",
2702 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4),
2709 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
2711 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2712 v9 int regs as it simplifies the code. */
2718 restore_regs (file
, low
, high
, base
, offset
, n_regs
)
2727 if (TARGET_V9
&& high
<= 32)
2729 for (i
= low
; i
< high
; i
++)
2731 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2732 fprintf (file
, "\tldx [%s+%d], %s\n",
2733 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
2739 for (i
= low
; i
< high
; i
+= 2)
2741 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2742 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2743 fprintf (file
, "\tldd [%s+%d], %s\n",
2744 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
2747 fprintf (file
, "\tld [%s+%d],%s\n",
2748 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
2750 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2751 fprintf (file
, "\tld [%s+%d],%s\n",
2752 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
2759 /* Static variables we want to share between prologue and epilogue. */
2761 /* Number of live general or floating point registers needed to be saved
2762 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
2763 static int num_gfregs
;
2765 /* Compute the frame size required by the function. This function is called
2766 during the reload pass and also by output_function_prologue(). */
2769 compute_frame_size (size
, leaf_function
)
2774 int outgoing_args_size
= (current_function_outgoing_args_size
2776 + REG_PARM_STACK_SPACE (current_function_decl
)
2780 if (TARGET_EPILOGUE
)
2782 /* N_REGS is the number of 4-byte regs saved thus far. This applies
2783 even to v9 int regs to be consistent with save_regs/restore_regs. */
2787 for (i
= 0; i
< 8; i
++)
2788 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2793 for (i
= 0; i
< 8; i
+= 2)
2794 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
2795 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
2799 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
2800 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
2801 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
2805 /* Set up values for use in `function_epilogue'. */
2806 num_gfregs
= n_regs
;
2808 if (leaf_function
&& n_regs
== 0
2809 && size
== 0 && current_function_outgoing_args_size
== 0)
2811 actual_fsize
= apparent_fsize
= 0;
2815 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
2816 The stack bias (if any) is taken out to undo its effects. */
2817 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ SPARC_STACK_BIAS
+ 7) & -8;
2818 apparent_fsize
+= n_regs
* 4;
2819 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
2822 /* Make sure nothing can clobber our register windows.
2823 If a SAVE must be done, or there is a stack-local variable,
2824 the register window area must be allocated.
2825 ??? For v9 we need an additional 8 bytes of reserved space, apparently
2826 it's needed by v8 as well. */
2827 if (leaf_function
== 0 || size
> 0)
2828 actual_fsize
+= (16 * UNITS_PER_WORD
) + 8;
2830 return SPARC_STACK_ALIGN (actual_fsize
);
2833 /* Build a (32 bit) big number in a register. */
2834 /* ??? We may be able to use the set macro here too. */
2837 build_big_number (file
, num
, reg
)
2842 if (num
>= 0 || ! TARGET_V9
)
2844 fprintf (file
, "\tsethi %%hi(%d),%s\n", num
, reg
);
2845 if ((num
& 0x3ff) != 0)
2846 fprintf (file
, "\tor %s,%%lo(%d),%s\n", reg
, num
, reg
);
2848 else /* num < 0 && TARGET_V9 */
2850 /* Sethi does not sign extend, so we must use a little trickery
2851 to use it for negative numbers. Invert the constant before
2852 loading it in, then use xor immediate to invert the loaded bits
2853 (along with the upper 32 bits) to the desired constant. This
2854 works because the sethi and immediate fields overlap. */
2857 int low
= -0x400 + (asize
& 0x3FF);
2859 fprintf (file
, "\tsethi %%hi(%d),%s\n\txor %s,%d,%s\n",
2860 inv
, reg
, reg
, low
, reg
);
2864 /* Output code for the function prologue. */
2867 output_function_prologue (file
, size
, leaf_function
)
2872 /* Need to use actual_fsize, since we are also allocating
2873 space for our callee (and our own register save area). */
2874 actual_fsize
= compute_frame_size (size
, leaf_function
);
2878 frame_base_name
= "%sp";
2879 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
2883 frame_base_name
= "%fp";
2884 frame_base_offset
= SPARC_STACK_BIAS
;
2887 /* This is only for the human reader. */
2888 fprintf (file
, "\t!#PROLOGUE# 0\n");
2890 if (actual_fsize
== 0)
2892 else if (actual_fsize
<= 4096)
2894 if (! leaf_function
)
2895 fprintf (file
, "\tsave %%sp,-%d,%%sp\n", actual_fsize
);
2897 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
);
2899 else if (actual_fsize
<= 8192)
2901 /* For frames in the range 4097..8192, we can use just two insns. */
2902 if (! leaf_function
)
2904 fprintf (file
, "\tsave %%sp,-4096,%%sp\n");
2905 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
- 4096);
2909 fprintf (file
, "\tadd %%sp,-4096,%%sp\n");
2910 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
- 4096);
2915 build_big_number (file
, -actual_fsize
, "%g1");
2916 if (! leaf_function
)
2917 fprintf (file
, "\tsave %%sp,%%g1,%%sp\n");
2919 fprintf (file
, "\tadd %%sp,%%g1,%%sp\n");
2922 /* If doing anything with PIC, do it now. */
2924 fprintf (file
, "\t!#PROLOGUE# 1\n");
2926 /* Call saved registers are saved just above the outgoing argument area. */
2932 offset
= -apparent_fsize
+ frame_base_offset
;
2933 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
2935 /* ??? This might be optimized a little as %g1 might already have a
2936 value close enough that a single add insn will do. */
2937 /* ??? Although, all of this is probably only a temporary fix
2938 because if %g1 can hold a function result, then
2939 output_function_epilogue will lose (the result will get
2941 build_big_number (file
, offset
, "%g1");
2942 fprintf (file
, "\tadd %s,%%g1,%%g1\n", frame_base_name
);
2948 base
= frame_base_name
;
2951 if (TARGET_EPILOGUE
&& ! leaf_function
)
2952 /* ??? Originally saved regs 0-15 here. */
2953 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0);
2954 else if (leaf_function
)
2955 /* ??? Originally saved regs 0-31 here. */
2956 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0);
2957 if (TARGET_EPILOGUE
)
2958 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
2962 if (leaf_function
&& actual_fsize
!= 0)
2964 /* warning ("leaf procedure with frame size %d", actual_fsize); */
2965 if (! TARGET_EPILOGUE
)
2966 leaf_label
= gen_label_rtx ();
2970 /* Output code for the function epilogue. */
2973 output_function_epilogue (file
, size
, leaf_function
)
2982 emit_label_after (leaf_label
, get_last_insn ());
2983 final_scan_insn (get_last_insn (), file
, 0, 0, 1);
2986 /* Restore any call saved registers. */
2992 offset
= -apparent_fsize
+ frame_base_offset
;
2993 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
2995 build_big_number (file
, offset
, "%g1");
2996 fprintf (file
, "\tadd %s,%%g1,%%g1\n", frame_base_name
);
3002 base
= frame_base_name
;
3005 if (TARGET_EPILOGUE
&& ! leaf_function
)
3006 /* ??? Originally saved regs 0-15 here. */
3007 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3008 else if (leaf_function
)
3009 /* ??? Originally saved regs 0-31 here. */
3010 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3011 if (TARGET_EPILOGUE
)
3012 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
3015 /* Work out how to skip the caller's unimp instruction if required. */
3017 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp %o7+12" : "retl");
3019 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp %i7+12" : "ret");
3021 if (TARGET_EPILOGUE
|| leaf_label
)
3023 int old_target_epilogue
= TARGET_EPILOGUE
;
3024 target_flags
&= ~old_target_epilogue
;
3026 if (! leaf_function
)
3028 /* If we wound up with things in our delay slot, flush them here. */
3029 if (current_function_epilogue_delay_list
)
3031 rtx insn
= emit_jump_insn_after (gen_rtx (RETURN
, VOIDmode
),
3033 PATTERN (insn
) = gen_rtx (PARALLEL
, VOIDmode
,
3035 PATTERN (XEXP (current_function_epilogue_delay_list
, 0)),
3037 final_scan_insn (insn
, file
, 1, 0, 1);
3040 fprintf (file
, "\t%s\n\trestore\n", ret
);
3042 /* All of the following cases are for leaf functions. */
3043 else if (current_function_epilogue_delay_list
)
3045 /* eligible_for_epilogue_delay_slot ensures that if this is a
3046 leaf function, then we will only have insn in the delay slot
3047 if the frame size is zero, thus no adjust for the stack is
3049 if (actual_fsize
!= 0)
3051 fprintf (file
, "\t%s\n", ret
);
3052 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
3055 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3056 avoid generating confusing assembly language output. */
3057 else if (actual_fsize
== 0)
3058 fprintf (file
, "\t%s\n\tnop\n", ret
);
3059 else if (actual_fsize
<= 4096)
3060 fprintf (file
, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret
, actual_fsize
);
3061 else if (actual_fsize
<= 8192)
3062 fprintf (file
, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n",
3063 ret
, actual_fsize
- 4096);
3064 else if ((actual_fsize
& 0x3ff) == 0)
3065 fprintf (file
, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3068 fprintf (file
, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3069 actual_fsize
, actual_fsize
, ret
);
3070 target_flags
|= old_target_epilogue
;
3074 /* Do what is necessary for `va_start'. The argument is ignored.
3075 !v9: We look at the current function to determine if stdarg or varargs
3076 is used and return the address of the first unnamed parameter.
3077 v9: We save the argument integer and floating point regs in a buffer, and
3078 return the address of this buffer. The rest is handled in va-sparc.h. */
3079 /* ??? This is currently conditioned on #ifdef SPARCV9 because
3080 current_function_args_info is different in each compiler. */
3085 sparc_builtin_saveregs (arglist
)
3088 tree fntype
= TREE_TYPE (current_function_decl
);
3089 /* First unnamed integer register. */
3090 int first_intreg
= current_function_args_info
.arg_count
[(int) SPARC_ARG_INT
];
3091 /* Number of integer registers we need to save. */
3092 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
3093 /* First unnamed SFmode float reg (no, you can't pass SFmode floats as
3094 unnamed arguments, we just number them that way). We must round up to
3095 the next double word float reg - that is the first one to save. */
3096 int first_floatreg
= current_function_args_info
.arg_count
[(int) SPARC_ARG_FLOAT
] + 1 & ~1;
3097 /* Number of SFmode float regs to save. */
3098 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
3099 int ptrsize
= GET_MODE_SIZE (Pmode
);
3100 rtx valist
, regbuf
, fpregs
;
3101 int bufsize
, adjust
, regno
;
3103 /* Allocate block of memory for the regs.
3104 We only allocate as much as we need, but we must ensure quadword float
3105 regs are stored with the appropriate alignment. */
3106 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
3107 Or can assign_stack_local accept a 0 SIZE argument? */
3109 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* (UNITS_PER_WORD
/ 2));
3110 /* Add space in front of the int regs to ensure proper alignment of quadword
3111 fp regs. We must add the space in front because va_start assumes this. */
3112 if (n_floatregs
>= 4)
3113 adjust
= ((n_intregs
+ first_floatreg
/ 2) % 2) * UNITS_PER_WORD
;
3117 regbuf
= assign_stack_local (BLKmode
, bufsize
+ adjust
,
3118 GET_MODE_BITSIZE (TFmode
));
3119 regbuf
= gen_rtx (MEM
, BLKmode
, plus_constant (XEXP (regbuf
, 0), adjust
));
3120 MEM_IN_STRUCT_P (regbuf
) = 1;
3123 This is optimized to only save the regs that are necessary. Explicitly
3124 named args need not be saved. */
3127 move_block_from_reg (BASE_INCOMING_ARG_REG (SImode
) + first_intreg
,
3128 regbuf
, n_intregs
, n_intregs
* UNITS_PER_WORD
);
3131 This is optimized to only save the regs that are necessary. Explicitly
3132 named args need not be saved.
3133 We explicitly build a pointer to the buffer because it halves the insn
3134 count when not optimizing (otherwise the pointer is built for each reg
3137 fpregs
= gen_reg_rtx (Pmode
);
3138 emit_move_insn (fpregs
, plus_constant (XEXP (regbuf
, 0),
3139 n_intregs
* UNITS_PER_WORD
));
3140 for (regno
= first_floatreg
; regno
< NPARM_REGS (SFmode
); regno
+= 2)
3141 emit_move_insn (gen_rtx (MEM
, DFmode
,
3142 plus_constant (fpregs
,
3143 GET_MODE_SIZE (SFmode
)
3144 * (regno
- first_floatreg
))),
3145 gen_rtx (REG
, DFmode
,
3146 BASE_INCOMING_ARG_REG (DFmode
) + regno
));
3148 /* Return the address of the regbuf. */
3150 return XEXP (regbuf
, 0);
3153 #else /* ! SPARCV9 */
3156 sparc_builtin_saveregs (arglist
)
3159 tree fntype
= TREE_TYPE (current_function_decl
);
3160 int stdarg
= (TYPE_ARG_TYPES (fntype
) != 0
3161 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
3162 != void_type_node
));
3163 int first_reg
= current_function_args_info
;
3167 #if 0 /* This code seemed to have no effect except to make
3168 varargs not work right when va_list wasn't the first arg. */
3173 for (regno
= first_reg
; regno
< NPARM_REGS (SImode
); regno
++)
3174 emit_move_insn (gen_rtx (MEM
, word_mode
,
3175 gen_rtx (PLUS
, Pmode
,
3177 GEN_INT (STACK_POINTER_OFFSET
3178 + UNITS_PER_WORD
* regno
))),
3179 gen_rtx (REG
, word_mode
, BASE_INCOMING_ARG_REG (word_mode
)
3182 address
= gen_rtx (PLUS
, Pmode
,
3184 GEN_INT (STACK_POINTER_OFFSET
3185 + UNITS_PER_WORD
* first_reg
));
3190 #endif /* ! SPARCV9 */
3192 /* Return the string to output a conditional branch to LABEL, which is
3193 the operand number of the label. OP is the conditional expression. The
3194 mode of register 0 says what kind of comparison we made.
3196 FP_COND_REG indicates which fp condition code register to use if this is
3197 a floating point branch.
3199 REVERSED is non-zero if we should reverse the sense of the comparison.
3201 ANNUL is non-zero if we should generate an annulling branch.
3203 NOOP is non-zero if we have to follow this branch by a noop. */
3206 output_cbranch (op
, fp_cond_reg
, label
, reversed
, annul
, noop
)
3207 rtx op
, fp_cond_reg
;
3209 int reversed
, annul
, noop
;
3211 static char string
[20];
3212 enum rtx_code code
= GET_CODE (op
);
3213 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
3214 static char v8_labelno
[] = " %lX";
3215 static char v9_icc_labelno
[] = " %%icc,%lX";
3216 static char v9_xcc_labelno
[] = " %%xcc,%lX";
3217 static char v9_fcc_labelno
[] = " %%fccX,%lY";
3221 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
3222 Because there is currently no concept of pre-delay slots, we can fix
3223 this only by always emitting a nop before a floating point branch. */
3225 if ((mode
== CCFPmode
|| mode
== CCFPEmode
) && ! TARGET_V9
)
3226 strcpy (string
, "nop\n\t");
3230 /* If not floating-point or if EQ or NE, we can just reverse the code. */
3232 && ((mode
!= CCFPmode
&& mode
!= CCFPEmode
) || code
== EQ
|| code
== NE
))
3233 code
= reverse_condition (code
), reversed
= 0;
3235 /* Start by writing the branch condition. */
3239 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
3240 strcat (string
, "fbne");
3242 strcpy (string
, "bne");
3246 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
3247 strcat (string
, "fbe");
3249 strcpy (string
, "be");
3253 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
3256 strcat (string
, "fbul");
3258 strcat (string
, "fbge");
3260 else if (mode
== CC_NOOVmode
)
3261 strcpy (string
, "bpos");
3263 strcpy (string
, "bge");
3267 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
3270 strcat (string
, "fbule");
3272 strcat (string
, "fbg");
3275 strcpy (string
, "bg");
3279 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
3282 strcat (string
, "fbug");
3284 strcat (string
, "fble");
3287 strcpy (string
, "ble");
3291 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
3294 strcat (string
, "fbuge");
3296 strcat (string
, "fbl");
3298 else if (mode
== CC_NOOVmode
)
3299 strcpy (string
, "bneg");
3301 strcpy (string
, "bl");
3305 strcpy (string
, "bgeu");
3309 strcpy (string
, "bgu");
3313 strcpy (string
, "bleu");
3317 strcpy (string
, "blu");
3321 /* Now add the annulling, the label, and a possible noop. */
3323 strcat (string
, ",a");
3325 /* ??? If v9, optional prediction bit ",pt" or ",pf" goes here. */
3330 labelno
= v8_labelno
;
3335 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
3338 labelno
= v9_fcc_labelno
;
3339 /* Set the char indicating the number of the fcc reg to use. */
3340 labelno
[6] = REGNO (fp_cond_reg
) - 96 + '0';
3342 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
3343 labelno
= v9_xcc_labelno
;
3345 labelno
= v9_icc_labelno
;
3347 /* Set the char indicating the number of the operand containing the
3349 labelno
[labeloff
] = label
+ '0';
3350 strcat (string
, labelno
);
3353 strcat (string
, "\n\tnop");
3358 /* Return the string to output a conditional branch to LABEL, testing
3359 register REG. LABEL is the operand number of the label; REG is the
3360 operand number of the reg. OP is the conditional expression. The mode
3361 of REG says what kind of comparison we made.
3363 REVERSED is non-zero if we should reverse the sense of the comparison.
3365 ANNUL is non-zero if we should generate an annulling branch.
3367 NOOP is non-zero if we have to follow this branch by a noop. */
3370 output_v9branch (op
, reg
, label
, reversed
, annul
, noop
)
3373 int reversed
, annul
, noop
;
3375 static char string
[20];
3376 enum rtx_code code
= GET_CODE (op
);
3377 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
3378 static char labelno
[] = " %X,%lX";
3380 /* If not floating-point or if EQ or NE, we can just reverse the code. */
3382 code
= reverse_condition (code
), reversed
= 0;
3384 /* Only 64 bit versions of these instructions exist. */
3388 /* Start by writing the branch condition. */
3393 strcpy (string
, "brnz");
3397 strcpy (string
, "brz");
3401 strcpy (string
, "brgez");
3405 strcpy (string
, "brlz");
3409 strcpy (string
, "brlez");
3413 strcpy (string
, "brgz");
3420 /* Now add the annulling, reg, label, and nop. */
3422 strcat (string
, ",a");
3424 /* ??? Optional prediction bit ",pt" or ",pf" goes here. */
3426 labelno
[2] = reg
+ '0';
3427 labelno
[6] = label
+ '0';
3428 strcat (string
, labelno
);
3431 strcat (string
, "\n\tnop");
3436 /* Output assembler code to return from a function. */
3438 /* ??? v9: Update to use the new `return' instruction. Also, add patterns to
3439 md file for the `return' instruction. */
3442 output_return (operands
)
3447 operands
[0] = leaf_label
;
3450 else if (leaf_function
)
3452 /* If we didn't allocate a frame pointer for the current function,
3453 the stack pointer might have been adjusted. Output code to
3456 operands
[0] = gen_rtx (CONST_INT
, VOIDmode
, actual_fsize
);
3458 /* Use sub of negated value in first two cases instead of add to
3459 allow actual_fsize == 4096. */
3461 if (actual_fsize
<= 4096)
3463 if (SKIP_CALLERS_UNIMP_P
)
3464 return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp";
3466 return "retl\n\tsub %%sp,-%0,%%sp";
3468 else if (actual_fsize
<= 8192)
3470 operands
[0] = gen_rtx (CONST_INT
, VOIDmode
, actual_fsize
- 4096);
3471 if (SKIP_CALLERS_UNIMP_P
)
3472 return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp";
3474 return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp";
3476 else if (SKIP_CALLERS_UNIMP_P
)
3478 if ((actual_fsize
& 0x3ff) != 0)
3479 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
3481 return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
3485 if ((actual_fsize
& 0x3ff) != 0)
3486 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
3488 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
3493 if (SKIP_CALLERS_UNIMP_P
)
3494 return "jmp %%i7+12\n\trestore";
3496 return "ret\n\trestore";
3500 /* Leaf functions and non-leaf functions have different needs. */
3503 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
3506 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
3508 static int *reg_alloc_orders
[] = {
3509 reg_leaf_alloc_order
,
3510 reg_nonleaf_alloc_order
};
3513 order_regs_for_local_alloc ()
3515 static int last_order_nonleaf
= 1;
3517 if (regs_ever_live
[15] != last_order_nonleaf
)
3519 last_order_nonleaf
= !last_order_nonleaf
;
3520 bcopy ((char *) reg_alloc_orders
[last_order_nonleaf
],
3521 (char *) reg_alloc_order
, FIRST_PSEUDO_REGISTER
* sizeof (int));
3525 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
3526 This makes them candidates for using ldd and std insns.
3528 Note reg1 and reg2 *must* be hard registers. To be sure we will
3529 abort if we are passed pseudo registers. */
3532 registers_ok_for_ldd_peep (reg1
, reg2
)
3535 /* We might have been passed a SUBREG. */
3536 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
3539 if (REGNO (reg1
) % 2 != 0)
3542 return (REGNO (reg1
) == REGNO (reg2
) - 1);
3545 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
3548 This can only happen when addr1 and addr2 are consecutive memory
3549 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
3550 64 bit boundary (addr1 % 8 == 0).
3552 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
3553 registers are assumed to *never* be properly aligned and are
3556 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
3557 need only check that the offset for addr1 % 8 == 0. */
3560 addrs_ok_for_ldd_peep (addr1
, addr2
)
3565 /* Extract a register number and offset (if used) from the first addr. */
3566 if (GET_CODE (addr1
) == PLUS
)
3568 /* If not a REG, return zero. */
3569 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
3573 reg1
= REGNO (XEXP (addr1
, 0));
3574 /* The offset must be constant! */
3575 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
3577 offset1
= INTVAL (XEXP (addr1
, 1));
3580 else if (GET_CODE (addr1
) != REG
)
3584 reg1
= REGNO (addr1
);
3585 /* This was a simple (mem (reg)) expression. Offset is 0. */
3589 /* Make sure the second address is a (mem (plus (reg) (const_int). */
3590 if (GET_CODE (addr2
) != PLUS
)
3593 if (GET_CODE (XEXP (addr2
, 0)) != REG
3594 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
3597 /* Only %fp and %sp are allowed. Additionally both addresses must
3598 use the same register. */
3599 if (reg1
!= FRAME_POINTER_REGNUM
&& reg1
!= STACK_POINTER_REGNUM
)
3602 if (reg1
!= REGNO (XEXP (addr2
, 0)))
3605 /* The first offset must be evenly divisible by 8 to ensure the
3606 address is 64 bit aligned. */
3607 if (offset1
% 8 != 0)
3610 /* The offset for the second addr must be 4 more than the first addr. */
3611 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
3614 /* All the tests passed. addr1 and addr2 are valid for ldd and std
3619 /* Return 1 if reg is a pseudo, or is the first register in
3620 a hard register pair. This makes it a candidate for use in
3621 ldd and std insns. */
3624 register_ok_for_ldd (reg
)
3627 /* We might have been passed a SUBREG. */
3628 if (GET_CODE (reg
) != REG
)
3631 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
3632 return (REGNO (reg
) % 2 == 0);
3637 /* Print operand X (an rtx) in assembler syntax to file FILE.
3638 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3639 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3642 print_operand (file
, x
, code
)
3650 /* Output a 'nop' if there's nothing for the delay slot. */
3651 if (dbr_sequence_length () == 0)
3652 fputs ("\n\tnop", file
);
3655 /* Output an annul flag if there's nothing for the delay slot and we
3656 are optimizing. This is always used with '(' below. */
3657 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
3658 this is a dbx bug. So, we only do this when optimizing. */
3659 if (dbr_sequence_length () == 0 && optimize
)
3663 /* Output a 'nop' if there's nothing for the delay slot and we are
3664 not optimizing. This is always used with '*' above. */
3665 if (dbr_sequence_length () == 0 && ! optimize
)
3666 fputs ("\n\tnop", file
);
3669 /* Output the Medium/Anywhere code model base register. */
3670 fputs (MEDANY_BASE_REG
, file
);
3673 /* Print out what we are using as the frame pointer. This might
3674 be %fp, or might be %sp+offset. */
3675 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
3676 fprintf (file
, "%s+%d", frame_base_name
, frame_base_offset
);
3679 /* Adjust the operand to take into account a RESTORE operation. */
3680 if (GET_CODE (x
) != REG
)
3681 output_operand_lossage ("Invalid %%Y operand");
3682 else if (REGNO (x
) < 8)
3683 fputs (reg_names
[REGNO (x
)], file
);
3684 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
3685 fputs (reg_names
[REGNO (x
)-16], file
);
3687 output_operand_lossage ("Invalid %%Y operand");
3690 /* Print out the second register name of a register pair or quad.
3691 I.e., R (%o0) => %o1. */
3692 fputs (reg_names
[REGNO (x
)+1], file
);
3695 /* Print out the third register name of a register quad.
3696 I.e., S (%o0) => %o2. */
3697 fputs (reg_names
[REGNO (x
)+2], file
);
3700 /* Print out the fourth register name of a register quad.
3701 I.e., T (%o0) => %o3. */
3702 fputs (reg_names
[REGNO (x
)+3], file
);
3705 /* Print the operand's address only. */
3706 output_address (XEXP (x
, 0));
3709 /* In this case we need a register. Use %g0 if the
3710 operand is const0_rtx. */
3712 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
3714 fputs ("%g0", file
);
3721 switch (GET_CODE (x
))
3723 case IOR
: fputs ("or", file
); break;
3724 case AND
: fputs ("and", file
); break;
3725 case XOR
: fputs ("xor", file
); break;
3726 default: output_operand_lossage ("Invalid %%A operand");
3731 switch (GET_CODE (x
))
3733 case IOR
: fputs ("orn", file
); break;
3734 case AND
: fputs ("andn", file
); break;
3735 case XOR
: fputs ("xnor", file
); break;
3736 default: output_operand_lossage ("Invalid %%B operand");
3740 /* This is used by the conditional move instructions. */
3742 switch (GET_CODE (x
))
3744 case NE
: fputs ("ne", file
); break;
3745 case EQ
: fputs ("e", file
); break;
3746 case GE
: fputs ("ge", file
); break;
3747 case GT
: fputs ("g", file
); break;
3748 case LE
: fputs ("le", file
); break;
3749 case LT
: fputs ("l", file
); break;
3750 case GEU
: fputs ("geu", file
); break;
3751 case GTU
: fputs ("gu", file
); break;
3752 case LEU
: fputs ("leu", file
); break;
3753 case LTU
: fputs ("lu", file
); break;
3754 default: output_operand_lossage ("Invalid %%C operand");
3758 /* This is used by the movr instruction pattern. */
3760 switch (GET_CODE (x
))
3762 case NE
: fputs ("ne", file
); break;
3763 case EQ
: fputs ("e", file
); break;
3764 case GE
: fputs ("gez", file
); break;
3765 case LT
: fputs ("lz", file
); break;
3766 case LE
: fputs ("lez", file
); break;
3767 case GT
: fputs ("gz", file
); break;
3768 default: output_operand_lossage ("Invalid %%D operand");
3774 /* Print a sign-extended character. */
3775 int i
= INTVAL (x
) & 0xff;
3778 fprintf (file
, "%d", i
);
3783 /* Operand must be a MEM; write its address. */
3784 if (GET_CODE (x
) != MEM
)
3785 output_operand_lossage ("Invalid %%f operand");
3786 output_address (XEXP (x
, 0));
3790 /* Do nothing special. */
3794 /* Undocumented flag. */
3795 output_operand_lossage ("invalid operand output code");
3798 if (GET_CODE (x
) == REG
)
3799 fputs (reg_names
[REGNO (x
)], file
);
3800 else if (GET_CODE (x
) == MEM
)
3803 if (CONSTANT_P (XEXP (x
, 0)))
3804 /* Poor Sun assembler doesn't understand absolute addressing. */
3805 fputs ("%g0+", file
);
3806 output_address (XEXP (x
, 0));
3809 else if (GET_CODE (x
) == HIGH
)
3811 fputs ("%hi(", file
);
3812 output_addr_const (file
, XEXP (x
, 0));
3815 else if (GET_CODE (x
) == LO_SUM
)
3817 print_operand (file
, XEXP (x
, 0), 0);
3818 fputs ("+%lo(", file
);
3819 output_addr_const (file
, XEXP (x
, 1));
3822 else if (GET_CODE (x
) == CONST_DOUBLE
3823 && (GET_MODE (x
) == VOIDmode
3824 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
3826 if (CONST_DOUBLE_HIGH (x
) == 0)
3827 fprintf (file
, "%u", CONST_DOUBLE_LOW (x
));
3828 else if (CONST_DOUBLE_HIGH (x
) == -1
3829 && CONST_DOUBLE_LOW (x
) < 0)
3830 fprintf (file
, "%d", CONST_DOUBLE_LOW (x
));
3832 output_operand_lossage ("long long constant not a valid immediate operand");
3834 else if (GET_CODE (x
) == CONST_DOUBLE
)
3835 output_operand_lossage ("floating point constant not a valid immediate operand");
3836 else { output_addr_const (file
, x
); }
3839 /* This function outputs assembler code for VALUE to FILE, where VALUE is
3840 a 64 bit (DImode) value. */
3842 /* ??? If there is a 64 bit counterpart to .word that the assembler
3843 understands, then using that would simply this code greatly. */
3844 /* ??? We only output .xword's for symbols and only then in environments
3845 where the assembler can handle them. */
3848 output_double_int (file
, value
)
3852 if (GET_CODE (value
) == CONST_INT
)
3854 if (INTVAL (value
) < 0)
3855 ASM_OUTPUT_INT (file
, constm1_rtx
);
3857 ASM_OUTPUT_INT (file
, const0_rtx
);
3858 ASM_OUTPUT_INT (file
, value
);
3860 else if (GET_CODE (value
) == CONST_DOUBLE
)
3862 ASM_OUTPUT_INT (file
, gen_rtx (CONST_INT
, VOIDmode
,
3863 CONST_DOUBLE_HIGH (value
)));
3864 ASM_OUTPUT_INT (file
, gen_rtx (CONST_INT
, VOIDmode
,
3865 CONST_DOUBLE_LOW (value
)));
3867 else if (GET_CODE (value
) == SYMBOL_REF
3868 || GET_CODE (value
) == CONST
3869 || GET_CODE (value
) == PLUS
3871 (GET_CODE (value
) == LABEL_REF
3872 || GET_CODE (value
) == MINUS
)))
3874 if (!TARGET_V9
|| TARGET_ENV32
)
3876 ASM_OUTPUT_INT (file
, const0_rtx
);
3877 ASM_OUTPUT_INT (file
, value
);
3881 fprintf (file
, "\t%s\t", ASM_LONGLONG
);
3882 output_addr_const (file
, value
);
3883 fprintf (file
, "\n");
3890 /* Return the value of a code used in the .proc pseudo-op that says
3891 what kind of result this function returns. For non-C types, we pick
3892 the closest C type. */
3894 #ifndef CHAR_TYPE_SIZE
3895 #define CHAR_TYPE_SIZE BITS_PER_UNIT
3898 #ifndef SHORT_TYPE_SIZE
3899 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
3902 #ifndef INT_TYPE_SIZE
3903 #define INT_TYPE_SIZE BITS_PER_WORD
3906 #ifndef LONG_TYPE_SIZE
3907 #define LONG_TYPE_SIZE BITS_PER_WORD
3910 #ifndef LONG_LONG_TYPE_SIZE
3911 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
3914 #ifndef FLOAT_TYPE_SIZE
3915 #define FLOAT_TYPE_SIZE BITS_PER_WORD
3918 #ifndef DOUBLE_TYPE_SIZE
3919 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
3922 #ifndef LONG_DOUBLE_TYPE_SIZE
3923 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
3927 sparc_type_code (type
)
3930 register unsigned long qualifiers
= 0;
3931 register unsigned shift
= 6;
3933 /* Only the first 30 bits of the qualifer are valid. We must refrain from
3934 setting more, since some assemblers will give an error for this. Also,
3935 we must be careful to avoid shifts of 32 bits or more to avoid getting
3936 unpredictable results. */
3940 switch (TREE_CODE (type
))
3947 qualifiers
|= (3 << shift
);
3949 type
= TREE_TYPE (type
);
3955 qualifiers
|= (2 << shift
);
3957 type
= TREE_TYPE (type
);
3961 case REFERENCE_TYPE
:
3964 qualifiers
|= (1 << shift
);
3966 type
= TREE_TYPE (type
);
3970 return (qualifiers
| 8);
3973 case QUAL_UNION_TYPE
:
3974 return (qualifiers
| 9);
3977 return (qualifiers
| 10);
3980 return (qualifiers
| 16);
3983 /* If this is a range type, consider it to be the underlying
3985 if (TREE_TYPE (type
) != 0)
3987 type
= TREE_TYPE (type
);
3991 /* Carefully distinguish all the standard types of C,
3992 without messing up if the language is not C. We do this by
3993 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
3994 look at both the names and the above fields, but that's redundant.
3995 Any type whose size is between two C types will be considered
3996 to be the wider of the two types. Also, we do not have a
3997 special code to use for "long long", so anything wider than
3998 long is treated the same. Note that we can't distinguish
3999 between "int" and "long" in this code if they are the same
4000 size, but that's fine, since neither can the assembler. */
4002 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
4003 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
4005 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
4006 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
4008 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
4009 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
4012 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
4015 /* Carefully distinguish all the standard types of C,
4016 without messing up if the language is not C. */
4018 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
4019 return (qualifiers
| 6);
4022 return (qualifiers
| 7);
4024 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
4025 /* ??? We need to distinguish between double and float complex types,
4026 but I don't know how yet because I can't reach this code from
4027 existing front-ends. */
4028 return (qualifiers
| 7); /* Who knows? */
4030 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
4031 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
4032 case FILE_TYPE
: /* GNU Pascal FILE type. */
4033 case SET_TYPE
: /* GNU Pascal SET type. */
4034 case LANG_TYPE
: /* ? */
4038 abort (); /* Not a type! */
4043 /* Nested function support. */
4045 /* Emit RTL insns to initialize the variable parts of a trampoline.
4046 FNADDR is an RTX for the address of the function's pure code.
4047 CXT is an RTX for the static chain value for the function.
4049 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
4050 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
4051 (to store insns). This is a bit excessive. Perhaps a different
4052 mechanism would be better here.
4054 Emit 3 FLUSH instructions to synchonize the data and instruction caches.
4056 ??? v9: We assume the top 32 bits of function addresses are 0. */
4059 sparc_initialize_trampoline (tramp
, fnaddr
, cxt
)
4060 rtx tramp
, fnaddr
, cxt
;
4062 rtx high_cxt
= expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
4063 size_int (10), 0, 1);
4064 rtx high_fn
= expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
4065 size_int (10), 0, 1);
4066 rtx low_cxt
= expand_and (cxt
, gen_rtx (CONST_INT
, VOIDmode
, 0x3ff), 0);
4067 rtx low_fn
= expand_and (fnaddr
, gen_rtx (CONST_INT
, VOIDmode
, 0x3ff), 0);
4068 rtx g1_sethi
= gen_rtx (HIGH
, SImode
,
4069 gen_rtx (CONST_INT
, VOIDmode
, 0x03000000));
4070 rtx g2_sethi
= gen_rtx (HIGH
, SImode
,
4071 gen_rtx (CONST_INT
, VOIDmode
, 0x05000000));
4072 rtx g1_ori
= gen_rtx (HIGH
, SImode
,
4073 gen_rtx (CONST_INT
, VOIDmode
, 0x82106000));
4074 rtx g2_ori
= gen_rtx (HIGH
, SImode
,
4075 gen_rtx (CONST_INT
, VOIDmode
, 0x8410A000));
4076 rtx tem
= gen_reg_rtx (SImode
);
4077 emit_move_insn (tem
, g1_sethi
);
4078 emit_insn (gen_iorsi3 (high_fn
, high_fn
, tem
));
4079 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 0)), high_fn
);
4080 emit_move_insn (tem
, g1_ori
);
4081 emit_insn (gen_iorsi3 (low_fn
, low_fn
, tem
));
4082 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 4)), low_fn
);
4083 emit_move_insn (tem
, g2_sethi
);
4084 emit_insn (gen_iorsi3 (high_cxt
, high_cxt
, tem
));
4085 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 8)), high_cxt
);
4086 emit_move_insn (tem
, g2_ori
);
4087 emit_insn (gen_iorsi3 (low_cxt
, low_cxt
, tem
));
4088 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 16)), low_cxt
);
4089 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, SImode
, tramp
))));
4090 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, SImode
,
4091 plus_constant (tramp
, 8)))));
4092 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, SImode
,
4093 plus_constant (tramp
, 16)))));
4097 sparc64_initialize_trampoline (tramp
, fnaddr
, cxt
)
4098 rtx tramp
, fnaddr
, cxt
;
4100 rtx fnaddrdi
= gen_reg_rtx (Pmode
);
4101 rtx fnaddrsi
= (emit_move_insn (fnaddrdi
, fnaddr
),
4102 gen_rtx (SUBREG
, SImode
, fnaddrdi
, 0));
4103 rtx cxtdi
= gen_reg_rtx (Pmode
);
4104 rtx cxtsi
= (emit_move_insn (cxtdi
, cxt
),
4105 gen_rtx (SUBREG
, SImode
, cxtdi
, 0));
4106 rtx high_cxt
= expand_shift (RSHIFT_EXPR
, SImode
, cxtsi
,
4107 size_int (10), 0, 1);
4108 rtx high_fn
= expand_shift (RSHIFT_EXPR
, SImode
, fnaddrsi
,
4109 size_int (10), 0, 1);
4110 rtx low_cxt
= expand_and (cxtsi
, gen_rtx (CONST_INT
, VOIDmode
, 0x3ff), 0);
4111 rtx low_fn
= expand_and (fnaddrsi
, gen_rtx (CONST_INT
, VOIDmode
, 0x3ff), 0);
4112 rtx g1_sethi
= gen_rtx (HIGH
, SImode
,
4113 gen_rtx (CONST_INT
, VOIDmode
, 0x03000000));
4114 rtx g2_sethi
= gen_rtx (HIGH
, SImode
,
4115 gen_rtx (CONST_INT
, VOIDmode
, 0x05000000));
4116 rtx g1_ori
= gen_rtx (HIGH
, SImode
,
4117 gen_rtx (CONST_INT
, VOIDmode
, 0x82106000));
4118 rtx g2_ori
= gen_rtx (HIGH
, SImode
,
4119 gen_rtx (CONST_INT
, VOIDmode
, 0x8410A000));
4120 rtx tem
= gen_reg_rtx (SImode
);
4121 emit_move_insn (tem
, g2_sethi
);
4122 emit_insn (gen_iorsi3 (high_fn
, high_fn
, tem
));
4123 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 0)), high_fn
);
4124 emit_move_insn (tem
, g2_ori
);
4125 emit_insn (gen_iorsi3 (low_fn
, low_fn
, tem
));
4126 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 4)), low_fn
);
4127 emit_move_insn (tem
, g1_sethi
);
4128 emit_insn (gen_iorsi3 (high_cxt
, high_cxt
, tem
));
4129 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 8)), high_cxt
);
4130 emit_move_insn (tem
, g1_ori
);
4131 emit_insn (gen_iorsi3 (low_cxt
, low_cxt
, tem
));
4132 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 16)), low_cxt
);
4133 emit_insn (gen_rtx (UNSPEC_VOLATILE
, VOIDmode
,
4134 gen_rtvec (1, plus_constant (tramp
, 0)),
4136 emit_insn (gen_rtx (UNSPEC_VOLATILE
, VOIDmode
,
4137 gen_rtvec (1, plus_constant (tramp
, 8)),
4139 emit_insn (gen_rtx (UNSPEC_VOLATILE
, VOIDmode
,
4140 gen_rtvec (1, plus_constant (tramp
, 16)),
4144 /* Subroutines to support a flat (single) register window calling
4147 /* Single-register window sparc stack frames look like:
4149 Before call After call
4150 +-----------------------+ +-----------------------+
4152 mem | caller's temps. | | caller's temps. |
4154 +-----------------------+ +-----------------------+
4156 | arguments on stack. | | arguments on stack. |
4158 +-----------------------+FP+92->+-----------------------+
4159 | 6 words to save | | 6 words to save |
4160 | arguments passed | | arguments passed |
4161 | in registers, even | | in registers, even |
4162 | if not passed. | | if not passed. |
4163 SP+68->+-----------------------+FP+68->+-----------------------+
4164 | 1 word struct addr | | 1 word struct addr |
4165 +-----------------------+FP+64->+-----------------------+
4167 | 16 word reg save area | | 16 word reg save area |
4169 SP->+-----------------------+ FP->+-----------------------+
4171 | fp/alu reg moves |
4172 FP-16->+-----------------------+
4176 +-----------------------+
4178 | fp register save |
4180 +-----------------------+
4182 | gp register save |
4184 +-----------------------+
4186 | alloca allocations |
4188 +-----------------------+
4190 | arguments on stack |
4192 SP+92->+-----------------------+
4194 | arguments passed |
4195 | in registers, even |
4196 low | if not passed. |
4197 memory SP+68->+-----------------------+
4198 | 1 word struct addr |
4199 SP+64->+-----------------------+
4201 I 16 word reg save area |
4203 SP->+-----------------------+ */
4205 /* Structure to be filled in by sparc_flat_compute_frame_size with register
4206 save masks, and offsets for the current function. */
4208 struct sparc_frame_info
4210 unsigned long total_size
; /* # bytes that the entire frame takes up. */
4211 unsigned long var_size
; /* # bytes that variables take up. */
4212 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
4213 unsigned long extra_size
; /* # bytes of extra gunk. */
4214 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
4215 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
4216 unsigned long gmask
; /* Mask of saved gp registers. */
4217 unsigned long fmask
; /* Mask of saved fp registers. */
4218 unsigned long reg_offset
; /* Offset from new sp to store regs. */
4219 int initialized
; /* Nonzero if frame size already calculated. */
4222 /* Current frame information calculated by sparc_flat_compute_frame_size. */
4223 struct sparc_frame_info current_frame_info
;
4225 /* Zero structure to initialize current_frame_info. */
4226 struct sparc_frame_info zero_frame_info
;
4228 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
4230 #define RETURN_ADDR_REGNUM 15
4231 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
4232 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
4234 #define MUST_SAVE_REGISTER(regno) \
4235 ((regs_ever_live[regno] && !call_used_regs[regno]) \
4236 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
4237 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
4239 /* Return the bytes needed to compute the frame pointer from the current
4243 sparc_flat_compute_frame_size (size
)
4244 int size
; /* # of var. bytes allocated. */
4247 unsigned long total_size
; /* # bytes that the entire frame takes up. */
4248 unsigned long var_size
; /* # bytes that variables take up. */
4249 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
4250 unsigned long extra_size
; /* # extra bytes. */
4251 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
4252 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
4253 unsigned long gmask
; /* Mask of saved gp registers. */
4254 unsigned long fmask
; /* Mask of saved fp registers. */
4255 unsigned long reg_offset
; /* Offset to register save area. */
4256 int need_aligned_p
; /* 1 if need the save area 8 byte aligned. */
4258 /* This is the size of the 16 word reg save area, 1 word struct addr
4259 area, and 4 word fp/alu register copy area. */
4260 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
4262 /* Also include the size needed for the 6 parameter registers. */
4263 args_size
= current_function_outgoing_args_size
+ 24;
4264 total_size
= var_size
+ args_size
+ extra_size
;
4272 /* Calculate space needed for gp registers. */
4273 for (regno
= 1; regno
<= 31; regno
++)
4275 if (MUST_SAVE_REGISTER (regno
))
4277 /* If we need to save two regs in a row, ensure there's room to bump
4278 up the address to align it to a doubleword boundary. */
4279 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
4281 if (gp_reg_size
% 8 != 0)
4283 gp_reg_size
+= 2 * UNITS_PER_WORD
;
4284 gmask
|= 3 << regno
;
4290 gp_reg_size
+= UNITS_PER_WORD
;
4291 gmask
|= 1 << regno
;
4296 /* Calculate space needed for fp registers. */
4297 for (regno
= 32; regno
<= 63; regno
++)
4299 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4301 fp_reg_size
+= UNITS_PER_WORD
;
4302 fmask
|= 1 << (regno
- 32);
4309 reg_offset
= FIRST_PARM_OFFSET(0) + args_size
;
4310 /* Ensure save area is 8 byte aligned if we need it. */
4312 if (need_aligned_p
&& n
!= 0)
4314 total_size
+= 8 - n
;
4315 reg_offset
+= 8 - n
;
4317 total_size
+= gp_reg_size
+ fp_reg_size
;
4320 /* ??? This looks a little suspicious. Clarify. */
4321 if (total_size
== extra_size
)
4322 total_size
= extra_size
= 0;
4324 total_size
= SPARC_STACK_ALIGN (total_size
);
4326 /* Save other computed information. */
4327 current_frame_info
.total_size
= total_size
;
4328 current_frame_info
.var_size
= var_size
;
4329 current_frame_info
.args_size
= args_size
;
4330 current_frame_info
.extra_size
= extra_size
;
4331 current_frame_info
.gp_reg_size
= gp_reg_size
;
4332 current_frame_info
.fp_reg_size
= fp_reg_size
;
4333 current_frame_info
.gmask
= gmask
;
4334 current_frame_info
.fmask
= fmask
;
4335 current_frame_info
.reg_offset
= reg_offset
;
4336 current_frame_info
.initialized
= reload_completed
;
4338 /* Ok, we're done. */
4342 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
4345 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
4346 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
4347 [BASE_REG+OFFSET] will always be a valid address.
4349 WORD_OP is either "st" for save, "ld" for restore.
4350 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
4353 sparc_flat_save_restore (file
, base_reg
, offset
, gmask
, fmask
, word_op
, doubleword_op
)
4356 unsigned int offset
;
4357 unsigned long gmask
;
4358 unsigned long fmask
;
4360 char *doubleword_op
;
4364 if (gmask
== 0 && fmask
== 0)
4367 /* Save registers starting from high to low. We've already saved the
4368 previous frame pointer and previous return address for the debugger's
4369 sake. The debugger allows us to not need a nop in the epilog if at least
4370 one register is reloaded in addition to return address. */
4374 for (regno
= 1; regno
<= 31; regno
++)
4376 if ((gmask
& (1L << regno
)) != 0)
4378 if ((regno
& 0x1) == 0 && ((gmask
& (1L << (regno
+1))) != 0))
4380 /* We can save two registers in a row. If we're not at a
4381 double word boundary, move to one.
4382 sparc_flat_compute_frame_size ensures there's room to do
4384 if (offset
% 8 != 0)
4385 offset
+= UNITS_PER_WORD
;
4387 if (word_op
[0] == 's')
4388 fprintf (file
, "\t%s %s,[%s+%d]\n",
4389 doubleword_op
, reg_names
[regno
],
4392 fprintf (file
, "\t%s [%s+%d],%s\n",
4393 doubleword_op
, base_reg
, offset
,
4396 offset
+= 2 * UNITS_PER_WORD
;
4401 if (word_op
[0] == 's')
4402 fprintf (file
, "\t%s %s,[%s+%d]\n",
4403 word_op
, reg_names
[regno
],
4406 fprintf (file
, "\t%s [%s+%d],%s\n",
4407 word_op
, base_reg
, offset
, reg_names
[regno
]);
4409 offset
+= UNITS_PER_WORD
;
4417 for (regno
= 32; regno
<= 63; regno
++)
4419 if ((fmask
& (1L << (regno
- 32))) != 0)
4421 if (word_op
[0] == 's')
4422 fprintf (file
, "\t%s %s,[%s+%d]\n",
4423 word_op
, reg_names
[regno
],
4426 fprintf (file
, "\t%s [%s+%d],%s\n",
4427 word_op
, base_reg
, offset
, reg_names
[regno
]);
4429 offset
+= UNITS_PER_WORD
;
4435 /* Set up the stack and frame (if desired) for the function. */
4438 sparc_flat_output_function_prologue (file
, size
)
4442 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
4443 unsigned long gmask
= current_frame_info
.gmask
;
4445 /* This is only for the human reader. */
4446 fprintf (file
, "\t!#PROLOGUE# 0\n");
4447 fprintf (file
, "\t!# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
4448 current_frame_info
.var_size
,
4449 current_frame_info
.gp_reg_size
/ 4,
4450 current_frame_info
.fp_reg_size
/ 4,
4451 current_function_outgoing_args_size
,
4452 current_frame_info
.extra_size
);
4454 size
= SPARC_STACK_ALIGN (size
);
4455 size
= (! current_frame_info
.initialized
4456 ? sparc_flat_compute_frame_size (size
)
4457 : current_frame_info
.total_size
);
4459 /* These cases shouldn't happen. Catch them now. */
4460 if (size
== 0 && (gmask
|| current_frame_info
.fmask
))
4463 /* Allocate our stack frame by decrementing %sp.
4464 At present, the only algorithm gdb can use to determine if this is a
4465 flat frame is if we always set %i7 if we set %sp. This can be optimized
4466 in the future by putting in some sort of debugging information that says
4467 this is a `flat' function. However, there is still the case of debugging
4468 code without such debugging information (including cases where most fns
4469 have such info, but there is one that doesn't). So, always do this now
4470 so we don't get a lot of code out there that gdb can't handle.
4471 If the frame pointer isn't needn't then that's ok - gdb won't be able to
4472 distinguish us from a non-flat function but there won't (and shouldn't)
4473 be any differences anyway. The return pc is saved (if necessary) right
4474 after %i7 so gdb won't have to look too far to find it. */
4477 unsigned int reg_offset
= current_frame_info
.reg_offset
;
4478 char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
4479 char *t1_str
= "%g1";
4481 /* Things get a little tricky if local variables take up more than ~4096
4482 bytes and outgoing arguments take up more than ~4096 bytes. When that
4483 happens, the register save area can't be accessed from either end of
4484 the frame. Handle this by decrementing %sp to the start of the gp
4485 register save area, save the regs, update %i7, and then set %sp to its
4486 final value. Given that we only have one scratch register to play
4487 with it is the cheapest solution, and it helps gdb out as it won't
4488 slow down recognition of flat functions.
4489 Don't change the order of insns emitted here without checking with
4490 the gdb folk first. */
4492 /* Is the entire register save area offsetable from %sp? */
4493 if (reg_offset
< 4096 - 64 * UNITS_PER_WORD
)
4497 fprintf (file
, "\tadd %s,%d,%s\n",
4498 sp_str
, -size
, sp_str
);
4499 if (gmask
& FRAME_POINTER_MASK
)
4501 fprintf (file
, "\tst %s,[%s+%d]\n",
4502 fp_str
, sp_str
, reg_offset
);
4503 fprintf (file
, "\tsub %s,%d,%s\t!# set up frame pointer\n",
4504 sp_str
, -size
, fp_str
);
4510 fprintf (file
, "\tset %d,%s\n\tsub %s,%s,%s\n",
4511 size
, t1_str
, sp_str
, t1_str
, sp_str
);
4512 if (gmask
& FRAME_POINTER_MASK
)
4514 fprintf (file
, "\tst %s,[%s+%d]\n",
4515 fp_str
, sp_str
, reg_offset
);
4516 fprintf (file
, "\tadd %s,%s,%s\t!# set up frame pointer\n",
4517 sp_str
, t1_str
, fp_str
);
4521 if (gmask
& RETURN_ADDR_MASK
)
4523 fprintf (file
, "\tst %s,[%s+%d]\n",
4524 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, reg_offset
);
4527 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
4528 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
4529 current_frame_info
.fmask
,
4534 /* Subtract %sp in two steps, but make sure there is always a
4535 64 byte register save area, and %sp is properly aligned. */
4536 /* Amount to decrement %sp by, the first time. */
4537 unsigned int size1
= ((size
- reg_offset
+ 64) + 15) & -16;
4538 /* Offset to register save area from %sp. */
4539 unsigned int offset
= size1
- (size
- reg_offset
);
4543 fprintf (file
, "\tadd %s,%d,%s\n",
4544 sp_str
, -size1
, sp_str
);
4545 if (gmask
& FRAME_POINTER_MASK
)
4547 fprintf (file
, "\tst %s,[%s+%d]\n\tsub %s,%d,%s\t!# set up frame pointer\n",
4548 fp_str
, sp_str
, offset
, sp_str
, -size1
, fp_str
);
4554 fprintf (file
, "\tset %d,%s\n\tsub %s,%s,%s\n",
4555 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
4556 if (gmask
& FRAME_POINTER_MASK
)
4558 fprintf (file
, "\tst %s,[%s+%d]\n\tadd %s,%s,%s\t!# set up frame pointer\n",
4559 fp_str
, sp_str
, offset
, sp_str
, t1_str
, fp_str
);
4563 if (gmask
& RETURN_ADDR_MASK
)
4565 fprintf (file
, "\tst %s,[%s+%d]\n",
4566 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, offset
);
4569 sparc_flat_save_restore (file
, sp_str
, offset
,
4570 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
4571 current_frame_info
.fmask
,
4573 fprintf (file
, "\tset %d,%s\n\tsub %s,%s,%s\n",
4574 size
- size1
, t1_str
, sp_str
, t1_str
, sp_str
);
4578 fprintf (file
, "\t!#PROLOGUE# 1\n");
4581 /* Do any necessary cleanup after a function to restore stack, frame,
4585 sparc_flat_output_function_epilogue (file
, size
)
4589 rtx epilogue_delay
= current_function_epilogue_delay_list
;
4590 int noepilogue
= FALSE
;
4592 /* This is only for the human reader. */
4593 fprintf (file
, "\t!#EPILOGUE#\n");
4595 /* The epilogue does not depend on any registers, but the stack
4596 registers, so we assume that if we have 1 pending nop, it can be
4597 ignored, and 2 it must be filled (2 nops occur for integer
4598 multiply and divide). */
4600 size
= SPARC_STACK_ALIGN (size
);
4601 size
= (!current_frame_info
.initialized
4602 ? sparc_flat_compute_frame_size (size
)
4603 : current_frame_info
.total_size
);
4605 if (size
== 0 && epilogue_delay
== 0)
4607 rtx insn
= get_last_insn ();
4609 /* If the last insn was a BARRIER, we don't have to write any code
4610 because a jump (aka return) was put there. */
4611 if (GET_CODE (insn
) == NOTE
)
4612 insn
= prev_nonnote_insn (insn
);
4613 if (insn
&& GET_CODE (insn
) == BARRIER
)
4619 unsigned int reg_offset
= current_frame_info
.reg_offset
;
4621 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
4622 char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
4623 char *t1_str
= "%g1";
4625 /* In the reload sequence, we don't need to fill the load delay
4626 slots for most of the loads, also see if we can fill the final
4627 delay slot if not otherwise filled by the reload sequence. */
4630 fprintf (file
, "\tset %d,%s\n", size
, t1_str
);
4632 if (frame_pointer_needed
)
4635 fprintf (file
,"\tsub %s,%s,%s\t\t!# sp not trusted here\n",
4636 fp_str
, t1_str
, sp_str
);
4638 fprintf (file
,"\tsub %s,%d,%s\t\t!# sp not trusted here\n",
4639 fp_str
, size
, sp_str
);
4642 /* Is the entire register save area offsetable from %sp? */
4643 if (reg_offset
< 4096 - 64 * UNITS_PER_WORD
)
4649 /* Restore %sp in two steps, but make sure there is always a
4650 64 byte register save area, and %sp is properly aligned. */
4651 /* Amount to increment %sp by, the first time. */
4652 size1
= ((reg_offset
- 64 - 16) + 15) & -16;
4653 /* Offset to register save area from %sp. */
4654 reg_offset
= size1
- reg_offset
;
4656 fprintf (file
, "\tset %d,%s\n\tadd %s,%s,%s\n",
4657 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
4660 /* We must restore the frame pointer and return address reg first
4661 because they are treated specially by the prologue output code. */
4662 if (current_frame_info
.gmask
& FRAME_POINTER_MASK
)
4664 fprintf (file
, "\tld [%s+%d],%s\n",
4665 sp_str
, reg_offset
, fp_str
);
4668 if (current_frame_info
.gmask
& RETURN_ADDR_MASK
)
4670 fprintf (file
, "\tld [%s+%d],%s\n",
4671 sp_str
, reg_offset
, reg_names
[RETURN_ADDR_REGNUM
]);
4675 /* Restore any remaining saved registers. */
4676 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
4677 current_frame_info
.gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
4678 current_frame_info
.fmask
,
4681 /* If we had to increment %sp in two steps, record it so the second
4682 restoration in the epilogue finishes up. */
4687 fprintf (file
, "\tset %d,%s\n",
4691 if (current_function_returns_struct
)
4692 fprintf (file
, "\tjmp %%o7+12\n");
4694 fprintf (file
, "\tretl\n");
4696 /* If the only register saved is the return address, we need a
4697 nop, unless we have an instruction to put into it. Otherwise
4698 we don't since reloading multiple registers doesn't reference
4699 the register being loaded. */
4705 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
4708 else if (size
> 4095)
4709 fprintf (file
, "\tadd %s,%s,%s\n", sp_str
, t1_str
, sp_str
);
4712 fprintf (file
, "\tadd %s,%d,%s\n", sp_str
, size
, sp_str
);
4715 fprintf (file
, "\tnop\n");
4718 /* Reset state info for each function. */
4719 current_frame_info
= zero_frame_info
;
4722 /* Define the number of delay slots needed for the function epilogue.
4724 On the sparc, we need a slot if either no stack has been allocated,
4725 or the only register saved is the return register. */
4728 sparc_flat_epilogue_delay_slots ()
4730 if (!current_frame_info
.initialized
)
4731 (void) sparc_flat_compute_frame_size (get_frame_size ());
4733 if (current_frame_info
.total_size
== 0)
4739 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
4740 Any single length instruction which doesn't reference the stack or frame
4744 sparc_flat_eligible_for_epilogue_delay (trial
, slot
)
4748 if (get_attr_length (trial
) == 1
4749 && ! reg_mentioned_p (stack_pointer_rtx
, PATTERN (trial
))
4750 && ! reg_mentioned_p (frame_pointer_rtx
, PATTERN (trial
)))
4755 /* Adjust the cost of a scheduling dependency. Return the new cost of
4756 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4759 supersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
4765 enum attr_type insn_type
;
4767 if (! recog_memoized (insn
))
4770 insn_type
= get_attr_type (insn
);
4772 if (REG_NOTE_KIND (link
) == 0)
4774 /* Data dependency; DEP_INSN writes a register that INSN reads some
4777 /* if a load, then the dependence must be on the memory address;
4778 add an extra 'cycle'. Note that the cost could be two cycles
4779 if the reg was written late in an instruction group; we can't tell
4781 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
4784 /* Get the delay only if the address of the store is the dependence. */
4785 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
4787 rtx pat
= PATTERN(insn
);
4788 rtx dep_pat
= PATTERN (dep_insn
);
4790 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4791 return cost
; /* This shouldn't happen! */
4793 /* The dependency between the two instructions was on the data that
4794 is being stored. Assume that this implies that the address of the
4795 store is not dependent. */
4796 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
4799 return cost
+ 3; /* An approximation. */
4802 /* A shift instruction cannot receive its data from an instruction
4803 in the same cycle; add a one cycle penalty. */
4804 if (insn_type
== TYPE_SHIFT
)
4805 return cost
+ 3; /* Split before cascade into shift. */
4809 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
4810 INSN writes some cycles later. */
4812 /* These are only significant for the fpu unit; writing a fp reg before
4813 the fpu has finished with it stalls the processor. */
4815 /* Reusing an integer register causes no problems. */
4816 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)