1 ; Options for the rs6000 port of the compiler
3 ; Copyright (C) 2005-2018 Free Software Foundation, Inc.
4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
6 ; This file is part of GCC.
8 ; GCC is free software; you can redistribute it and/or modify it under
9 ; the terms of the GNU General Public License as published by the Free
10 ; Software Foundation; either version 3, or (at your option) any later
13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ; License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with GCC; see the file COPYING3. If not see
20 ; <http://www.gnu.org/licenses/>.
23 config/rs6000/rs6000-opts.h
25 ;; ISA flag bits (on/off)
27 HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
30 HOST_WIDE_INT x_rs6000_isa_flags
32 ;; Miscellaneous flag bits that were set explicitly by the user
34 HOST_WIDE_INT rs6000_isa_flags_explicit
37 HOST_WIDE_INT x_rs6000_isa_flags_explicit
41 enum processor_type rs6000_cpu = PROCESSOR_PPC603
45 enum processor_type rs6000_tune = PROCESSOR_PPC603
47 ;; Always emit branch hint bits.
49 unsigned char rs6000_always_hint
51 ;; Schedule instructions for group formation.
53 unsigned char rs6000_sched_groups
55 ;; Align branch targets.
57 unsigned char rs6000_align_branch_targets
59 ;; Support for -msched-costly-dep option.
61 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
63 ;; Support for -minsert-sched-nops option.
65 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
67 ;; Non-zero to allow overriding loop alignment.
69 unsigned char can_override_loop_align
71 ;; Which small data model to use (for System V targets only)
73 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
75 ;; Bit size of immediate TLS offsets and string from which it is decoded.
77 int rs6000_tls_size = 32
79 ;; ABI enumeration available for subtarget to use.
81 enum rs6000_abi rs6000_current_abi = ABI_NONE
83 ;; Type of traceback to use.
85 enum rs6000_traceback_type rs6000_traceback = traceback_default
87 ;; Control alignment for fields within structures.
89 unsigned char rs6000_alignment_flags
91 ;; Code model for 64-bit linux.
93 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
95 ;; What type of reciprocal estimation instructions to generate
97 unsigned int rs6000_recip_control
99 ;; Mask of what builtin functions are allowed
101 HOST_WIDE_INT rs6000_builtin_mask
105 unsigned int rs6000_debug
107 ;; Whether to enable the -mfloat128 stuff without necessarily enabling the
108 ;; __float128 keyword.
110 unsigned char x_TARGET_FLOAT128_TYPE
113 unsigned char TARGET_FLOAT128_TYPE
115 ;; This option existed in the past, but now is always on.
117 Target RejectNegative Undocumented Ignore
120 Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
121 Use PowerPC-64 instruction set.
124 Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
125 Use PowerPC General Purpose group optional instructions.
128 Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
129 Use PowerPC Graphics group optional instructions.
132 Target Report Mask(MFCRF) Var(rs6000_isa_flags)
133 Use PowerPC V2.01 single field mfcr instruction.
136 Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
137 Use PowerPC V2.02 popcntb instruction.
140 Target Report Mask(FPRND) Var(rs6000_isa_flags)
141 Use PowerPC V2.02 floating point rounding instructions.
144 Target Report Mask(CMPB) Var(rs6000_isa_flags)
145 Use PowerPC V2.05 compare bytes instruction.
148 Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
149 Use extended PowerPC V2.05 move floating point to/from GPR instructions.
152 Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
153 Use AltiVec instructions.
156 Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save
157 Generate AltiVec instructions using little-endian element order.
160 Target Report RejectNegative Var(rs6000_altivec_element_order, 2)
161 Generate AltiVec instructions using big-endian element order.
164 Target Report Var(rs6000_fold_gimple) Init(1)
165 Enable early gimple folding of builtins.
168 Target Report Mask(DFP) Var(rs6000_isa_flags)
169 Use decimal floating point instructions.
172 Target Report Mask(MULHW) Var(rs6000_isa_flags)
173 Use 4xx half-word multiply instructions.
176 Target Report Mask(DLMZB) Var(rs6000_isa_flags)
177 Use 4xx string-search dlmzb instruction.
180 Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
181 Generate load/store multiple instructions.
183 ;; This option existed in the past, but now is always off.
185 Target RejectNegative Undocumented Ignore
188 Target RejectNegative Undocumented Warn(%<-mstring%> is deprecated)
191 Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
192 Do not use hardware floating point.
195 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
196 Use hardware floating point.
199 Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
200 Use PowerPC V2.06 popcntd instruction.
203 Target Report Var(TARGET_FRIZ) Init(-1) Save
204 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
207 Target RejectNegative Joined Var(rs6000_veclibabi_name)
208 Vector library ABI to use.
211 Target Report Mask(VSX) Var(rs6000_isa_flags)
212 Use vector/scalar (VSX) instructions.
215 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
216 ; If -mvsx, set alignment to 128 bits instead of 32/64
219 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
220 ; Allow the movmisalign in DF/DI vectors
222 mefficient-unaligned-vsx
223 Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
224 ; Consider unaligned VSX vector and fp accesses to be efficient
227 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
228 ; Explicitly set rs6000_sched_groups
231 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
232 ; Explicitly set rs6000_always_hint
234 malign-branch-targets
235 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
236 ; Explicitly set rs6000_align_branch_targets
239 Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
240 Do not generate load/store with update instructions.
243 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
244 Generate load/store with update instructions.
247 Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
248 Do not load the PIC register in function prologues.
250 mavoid-indexed-addresses
251 Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
252 Avoid generation of indexed load/store instructions when possible.
255 Target Report Var(tls_markers) Init(1) Save
256 Mark __tls_get_addr calls with argument info.
259 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
262 Target Report Var(TARGET_SCHED_PROLOG) Save
263 Schedule the start and end of the procedure.
266 Target Report RejectNegative Var(aix_struct_return) Save
267 Return all structures in memory (AIX default).
270 Target Report RejectNegative Var(aix_struct_return,0) Save
271 Return small structures in registers (SVR4 default).
274 Target Report Var(TARGET_XL_COMPAT) Save
275 Conform more closely to IBM XLC semantics.
279 Generate software reciprocal divide and square root for better throughput.
282 Target Report RejectNegative Joined Var(rs6000_recip_name)
283 Generate software reciprocal divide and square root for better throughput.
286 Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
287 Assume that the reciprocal estimate instructions provide more accuracy.
290 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
291 Do not place floating point constants in TOC.
294 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
295 Place floating point constants in TOC.
298 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
299 Do not place symbol+offset constants in TOC.
302 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
303 Place symbol+offset constants in TOC.
305 ; Output only one TOC entry per module. Normally linking fails if
306 ; there are more than 16K unique variables/constants in an executable. With
307 ; this option, linking fails only if there are more than 16K modules, or
308 ; if there are more than 16K unique variables/constant in a single module.
310 ; This is at the cost of having 2 extra loads and one extra store per
311 ; function, and one less allocable register.
313 Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
314 Use only one TOC entry per procedure.
318 Put everything in the regular TOC.
321 Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
322 Generate VRSAVE instructions when generating AltiVec code.
325 Target RejectNegative Alias(mvrsave) NegativeAlias
326 Deprecated option. Use -mno-vrsave instead.
329 Target RejectNegative Alias(mvrsave)
330 Deprecated option. Use -mvrsave instead.
332 mblock-move-inline-limit=
333 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
334 Specify how many bytes should be moved inline before calling out to memcpy/memmove.
336 mblock-compare-inline-limit=
337 Target Report Var(rs6000_block_compare_inline_limit) Init(31) RejectNegative Joined UInteger Save
338 Specify the maximum number of bytes to compare inline with non-looping code. If this is set to 0, all inline expansion (non-loop and loop) of memcmp is disabled.
340 mblock-compare-inline-loop-limit=
341 Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save
342 Specify the maximum number of bytes to compare inline with loop code generation. If the length is not known at compile time, memcmp will be called after this many bytes are compared. By default, a length will be picked depending on the tuning target.
344 mstring-compare-inline-limit=
345 Target Report Var(rs6000_string_compare_inline_limit) Init(8) RejectNegative Joined UInteger Save
346 Specify the maximum number pairs of load instructions that should be generated inline for the compare. If the number needed exceeds the limit, a call to strncmp will be generated instead.
349 Target Report Mask(ISEL) Var(rs6000_isa_flags)
350 Generate isel instructions.
353 Target RejectNegative Alias(misel) NegativeAlias
354 Deprecated option. Use -mno-isel instead.
357 Target RejectNegative Alias(misel)
358 Deprecated option. Use -misel instead.
361 Target Var(rs6000_paired_float) Save
362 Generate PPC750CL paired-single instructions.
365 Target RejectNegative Joined
366 -mdebug= Enable debug output.
369 Target RejectNegative Var(rs6000_altivec_abi) Save
370 Use the AltiVec ABI extensions.
373 Target RejectNegative Var(rs6000_altivec_abi, 0)
374 Do not use the AltiVec ABI extensions.
377 Target RejectNegative Var(rs6000_elf_abi, 1) Save
381 Target RejectNegative Var(rs6000_elf_abi, 2)
384 ; These are here for testing during development only, do not document
385 ; in the manual please.
387 ; If we want Darwin's struct-by-value-in-regs ABI.
389 Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
392 Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
395 Target RejectNegative Var(rs6000_ieeequad) Save
398 Target RejectNegative Var(rs6000_ieeequad, 0)
401 Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
402 -mcpu= Use features of and schedule code for given CPU.
405 Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
406 -mtune= Schedule code for given CPU.
409 Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
410 -mtraceback= Select full, part, or no traceback table.
413 Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
416 Enum(rs6000_traceback_type) String(full) Value(traceback_full)
419 Enum(rs6000_traceback_type) String(part) Value(traceback_part)
422 Enum(rs6000_traceback_type) String(no) Value(traceback_none)
425 Target Report Var(rs6000_default_long_calls) Save
426 Avoid all range limits on call instructions.
428 ; This option existed in the past, but now is always on.
430 Target RejectNegative Undocumented Ignore
433 Target Var(rs6000_warn_altivec_long) Init(1) Save
434 Warn about deprecated 'vector long ...' AltiVec type usage.
437 Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
438 -mlong-double-<n> Specify size of long double (64 or 128 bits).
440 ; This option existed in the past, but now is always on.
442 Target RejectNegative Undocumented Ignore
445 Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
446 Determine which dependences between insns are considered costly.
449 Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
450 Specify which post scheduling nop insertion scheme to apply.
453 Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
454 Specify alignment of structure fields default/natural.
457 Name(rs6000_alignment_flags) Type(unsigned char)
458 Valid arguments to -malign-:
461 Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
464 Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
466 mprioritize-restricted-insns=
467 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
468 Specify scheduling priority for dispatch slot restricted insns.
471 Target RejectNegative Var(rs6000_single_float) Save
472 Single-precision floating point unit.
475 Target RejectNegative Var(rs6000_double_float) Save
476 Double-precision floating point unit.
479 Target RejectNegative Var(rs6000_simple_fpu) Save
480 Floating point unit does not support divide & sqrt.
483 Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
484 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu).
487 Name(fpu_type_t) Type(enum fpu_type_t)
490 Enum(fpu_type_t) String(none) Value(FPU_NONE)
493 Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)
496 Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)
499 Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)
502 Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)
505 Target Var(rs6000_xilinx_fpu) Save
508 mpointers-to-nested-functions
509 Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
510 Use r11 to hold the static link in calls to functions via pointers.
513 Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
514 Save the TOC in the prologue for indirect calls rather than inline.
516 ; This option existed in the past, but now is always the same as -mvsx.
518 Target RejectNegative Undocumented Ignore
521 Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
522 Fuse certain integer operations together for better performance on power8.
525 Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
526 Allow sign extension in fusion operations.
529 Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
530 Use vector and scalar instructions added in ISA 2.07.
533 Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
534 Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
537 Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)
538 Use ISA 2.07 direct move between GPR & VSX register instructions.
541 Target Report Mask(HTM) Var(rs6000_isa_flags)
542 Use ISA 2.07 transactional memory (HTM) instructions.
545 Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
546 Generate the quad word memory instructions (lq/stq).
549 Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
550 Generate the quad word memory atomic instructions (lqarx/stqcx).
553 Target Report Var(rs6000_compat_align_parm) Init(0) Save
554 Generate aggregate parameter passing code with at most 64-bit alignment.
557 Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
558 Analyze and remove doubleword swaps from VSX computations.
561 Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
562 Fuse certain operations together for better performance on power9.
565 Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
566 Use certain scalar instructions added in ISA 3.0.
569 Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
570 Use vector instructions added in ISA 3.0.
573 Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
574 Use the new min/max instructions defined in ISA 3.0.
577 Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
578 Fuse medium/large code model toc references with the memory instruction.
581 Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
582 Generate the integer modulo instructions.
585 Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
586 Enable IEEE 128-bit floating point via the __float128 keyword.
589 Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
590 Enable using IEEE 128-bit floating point instructions.
593 Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
594 Enable default conversions between __float128 & long double.
596 mstack-protector-guard=
597 Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
598 Use given stack-protector guard.
601 Name(stack_protector_guard) Type(enum stack_protector_guard)
602 Valid arguments to -mstack-protector-guard=:
605 Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
608 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
610 mstack-protector-guard-reg=
611 Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str)
612 Use the given base register for addressing the stack-protector guard.
615 int rs6000_stack_protector_guard_reg = 0
617 mstack-protector-guard-offset=
618 Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str)
619 Use the given offset for addressing the stack-protector guard.
622 long rs6000_stack_protector_guard_offset = 0
624 ;; -mno-speculate-indirect-jumps adds deliberate misprediction to indirect
625 ;; branches via the CTR.
626 mspeculate-indirect-jumps
627 Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save